src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

*** 3229,3238 ****
--- 3229,3258 ----
  
  void LIR_Assembler::membar_release() {
    // no-op on TSO
  }
  
+ void LIR_Assembler::membar_loadload() {
+   // no-op
+   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
+ }
+ 
+ void LIR_Assembler::membar_storestore() {
+   // no-op
+   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
+ }
+ 
+ void LIR_Assembler::membar_loadstore() {
+   // no-op
+   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
+ }
+ 
+ void LIR_Assembler::membar_storeload() {
+   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
+ }
+ 
+ 
  // Pack two sequential registers containing 32 bit values
  // into a single 64 bit register.
  // src and src->successor() are packed into dst
  // src and dst may be the same register.
  // Note: src is destroyed