3214   } else {
3215     // use normal move for all other volatiles since they don't need
3216     // special handling to remain atomic.
3217     move_op(src, dest, type, lir_patch_none, info, false, false, false);
3218   }
3219 }
3220 
3221 void LIR_Assembler::membar() {
3222   // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3223   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3224 }
3225 
3226 void LIR_Assembler::membar_acquire() {
3227   // no-op on TSO
3228 }
3229 
3230 void LIR_Assembler::membar_release() {
3231   // no-op on TSO
3232 }
3233 




















3234 // Pack two sequential registers containing 32 bit values
3235 // into a single 64 bit register.
3236 // src and src->successor() are packed into dst
3237 // src and dst may be the same register.
3238 // Note: src is destroyed
3239 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3240   Register rs = src->as_register();
3241   Register rd = dst->as_register_lo();
3242   __ sllx(rs, 32, rs);
3243   __ srl(rs->successor(), 0, rs->successor());
3244   __ or3(rs, rs->successor(), rd);
3245 }
3246 
3247 // Unpack a 64 bit value in a register into
3248 // two sequential registers.
3249 // src is unpacked into dst and dst->successor()
3250 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3251   Register rs = src->as_register_lo();
3252   Register rd = dst->as_register_hi();
3253   assert_different_registers(rs, rd, rd->successor());

3214   } else {
3215     // use normal move for all other volatiles since they don't need
3216     // special handling to remain atomic.
3217     move_op(src, dest, type, lir_patch_none, info, false, false, false);
3218   }
3219 }
3220 
3221 void LIR_Assembler::membar() {
3222   // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3223   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3224 }
3225 
3226 void LIR_Assembler::membar_acquire() {
3227   // no-op on TSO
3228 }
3229 
3230 void LIR_Assembler::membar_release() {
3231   // no-op on TSO
3232 }
3233 
3234 void LIR_Assembler::membar_loadload() {
3235   // no-op
3236   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3237 }
3238 
3239 void LIR_Assembler::membar_storestore() {
3240   // no-op
3241   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3242 }
3243 
3244 void LIR_Assembler::membar_loadstore() {
3245   // no-op
3246   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3247 }
3248 
3249 void LIR_Assembler::membar_storeload() {
3250   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3251 }
3252 
3253 
3254 // Pack two sequential registers containing 32 bit values
3255 // into a single 64 bit register.
3256 // src and src->successor() are packed into dst
3257 // src and dst may be the same register.
3258 // Note: src is destroyed
3259 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3260   Register rs = src->as_register();
3261   Register rd = dst->as_register_lo();
3262   __ sllx(rs, 32, rs);
3263   __ srl(rs->successor(), 0, rs->successor());
3264   __ or3(rs, rs->successor(), rd);
3265 }
3266 
3267 // Unpack a 64 bit value in a register into
3268 // two sequential registers.
3269 // src is unpacked into dst and dst->successor()
3270 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3271   Register rs = src->as_register_lo();
3272   Register rd = dst->as_register_hi();
3273   assert_different_registers(rs, rd, rd->successor());