1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "runtime/java.hpp"
29 #include "runtime/os.hpp"
30 #include "runtime/stubCodeGenerator.hpp"
31 #include "vm_version_sparc.hpp"
32
33 int VM_Version::_features = VM_Version::unknown_m;
34 const char* VM_Version::_features_str = "";
35 unsigned int VM_Version::_L2_data_cache_line_size = 0;
36
37 void VM_Version::initialize() {
38 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
39 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
40 PrefetchFieldsAhead = prefetch_fields_ahead();
41
42 // Allocation prefetch settings
43 intx cache_line_size = prefetch_data_size();
44 if( cache_line_size > AllocatePrefetchStepSize )
45 AllocatePrefetchStepSize = cache_line_size;
46
47 assert(AllocatePrefetchLines > 0, "invalid value");
48 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
49 AllocatePrefetchLines = 3;
50 assert(AllocateInstancePrefetchLines > 0, "invalid value");
51 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
52 AllocateInstancePrefetchLines = 1;
53
54 AllocatePrefetchDistance = allocate_prefetch_distance();
55 AllocatePrefetchStyle = allocate_prefetch_style();
56
57 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
58 warning("BIS instructions are not available on this CPU");
59 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
60 }
61
62 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
63
64 UseSSE = 0; // Only on x86 and x64
65
66 _supports_cx8 = has_v9();
67 _supports_atomic_getset4 = true; // swap instruction
68
69 if (is_niagara()) {
70 // Indirect branch is the same cost as direct
71 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
72 FLAG_SET_DEFAULT(UseInlineCaches, false);
73 }
74 // Align loops on a single instruction boundary.
75 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
76 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
77 }
78 #ifdef _LP64
79 // 32-bit oops don't make sense for the 64-bit VM on sparc
80 // since the 32-bit VM has the same registers and smaller objects.
81 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
82 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
83 #endif // _LP64
84 #ifdef COMPILER2
85 // Indirect branch is the same cost as direct
86 if (FLAG_IS_DEFAULT(UseJumpTables)) {
87 FLAG_SET_DEFAULT(UseJumpTables, true);
88 }
89 // Single-issue, so entry and loop tops are
90 // aligned on a single instruction boundary
91 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
92 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
93 }
94 if (is_niagara_plus()) {
95 if (has_blk_init() && UseTLAB &&
96 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
97 // Use BIS instruction for TLAB allocation prefetch.
98 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
99 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
100 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
101 }
102 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
103 // Use smaller prefetch distance with BIS
104 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
105 }
106 }
107 if (is_T4()) {
108 // Double number of prefetched cache lines on T4
109 // since L2 cache line size is smaller (32 bytes).
110 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
111 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
112 }
113 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
114 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
115 }
116 }
117 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
118 // Use different prefetch distance without BIS
119 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
120 }
121 if (AllocatePrefetchInstr == 1) {
122 // Need a space at the end of TLAB for BIS since it
123 // will fault when accessing memory outside of heap.
124
125 // +1 for rounding up to next cache line, +1 to be safe
126 int lines = AllocatePrefetchLines + 2;
127 int step_size = AllocatePrefetchStepSize;
128 int distance = AllocatePrefetchDistance;
129 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
130 }
131 }
132 #endif
133 }
134
135 // Use hardware population count instruction if available.
136 if (has_hardware_popc()) {
137 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
138 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
139 }
140 } else if (UsePopCountInstruction) {
141 warning("POPC instruction is not available on this CPU");
142 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
143 }
144
145 // T4 and newer Sparc cpus have new compare and branch instruction.
146 if (has_cbcond()) {
147 if (FLAG_IS_DEFAULT(UseCBCond)) {
148 FLAG_SET_DEFAULT(UseCBCond, true);
149 }
150 } else if (UseCBCond) {
151 warning("CBCOND instruction is not available on this CPU");
152 FLAG_SET_DEFAULT(UseCBCond, false);
153 }
154
155 assert(BlockZeroingLowLimit > 0, "invalid value");
156 if (has_block_zeroing() && cache_line_size > 0) {
157 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
158 FLAG_SET_DEFAULT(UseBlockZeroing, true);
159 }
160 } else if (UseBlockZeroing) {
161 warning("BIS zeroing instructions are not available on this CPU");
162 FLAG_SET_DEFAULT(UseBlockZeroing, false);
163 }
164
165 assert(BlockCopyLowLimit > 0, "invalid value");
166 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
167 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
168 FLAG_SET_DEFAULT(UseBlockCopy, true);
169 }
170 } else if (UseBlockCopy) {
171 warning("BIS instructions are not available or expensive on this CPU");
172 FLAG_SET_DEFAULT(UseBlockCopy, false);
173 }
174
175 #ifdef COMPILER2
176 // T4 and newer Sparc cpus have fast RDPC.
177 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
178 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
179 }
180
181 // Currently not supported anywhere.
182 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
183
184 MaxVectorSize = 8;
185
186 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
187 #endif
188
189 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
190 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
191
192 char buf[512];
193 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
194 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
195 (has_hardware_popc() ? ", popc" : ""),
196 (has_vis1() ? ", vis1" : ""),
197 (has_vis2() ? ", vis2" : ""),
198 (has_vis3() ? ", vis3" : ""),
199 (has_blk_init() ? ", blk_init" : ""),
200 (has_cbcond() ? ", cbcond" : ""),
201 (has_aes() ? ", aes" : ""),
202 (has_sha1() ? ", sha1" : ""),
203 (has_sha256() ? ", sha256" : ""),
204 (has_sha512() ? ", sha512" : ""),
205 (has_crc32c() ? ", crc32c" : ""),
206 (is_ultra3() ? ", ultra3" : ""),
207 (is_sun4v() ? ", sun4v" : ""),
208 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
209 (is_sparc64() ? ", sparc64" : ""),
210 (!has_hardware_mul32() ? ", no-mul32" : ""),
211 (!has_hardware_div32() ? ", no-div32" : ""),
212 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
213
214 // buf is started with ", " or is empty
215 _features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
216
217 // UseVIS is set to the smallest of what hardware supports and what
218 // the command line requires. I.e., you cannot set UseVIS to 3 on
219 // older UltraSparc which do not support it.
220 if (UseVIS > 3) UseVIS=3;
221 if (UseVIS < 0) UseVIS=0;
222 if (!has_vis3()) // Drop to 2 if no VIS3 support
223 UseVIS = MIN2((intx)2,UseVIS);
224 if (!has_vis2()) // Drop to 1 if no VIS2 support
225 UseVIS = MIN2((intx)1,UseVIS);
226 if (!has_vis1()) // Drop to 0 if no VIS1 support
227 UseVIS = 0;
228
229 // SPARC T4 and above should have support for AES instructions
230 if (has_aes()) {
231 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
232 if (FLAG_IS_DEFAULT(UseAES)) {
233 FLAG_SET_DEFAULT(UseAES, true);
234 }
235 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
236 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
237 }
238 // we disable both the AES flags if either of them is disabled on the command line
239 if (!UseAES || !UseAESIntrinsics) {
240 FLAG_SET_DEFAULT(UseAES, false);
241 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
242 }
243 } else {
244 if (UseAES || UseAESIntrinsics) {
245 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
246 if (UseAES) {
247 FLAG_SET_DEFAULT(UseAES, false);
248 }
249 if (UseAESIntrinsics) {
250 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
251 }
252 }
253 }
254 } else if (UseAES || UseAESIntrinsics) {
255 warning("AES instructions are not available on this CPU");
256 if (UseAES) {
257 FLAG_SET_DEFAULT(UseAES, false);
258 }
259 if (UseAESIntrinsics) {
260 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
261 }
262 }
263
264 // GHASH/GCM intrinsics
265 if (has_vis3() && (UseVIS > 2)) {
266 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
267 UseGHASHIntrinsics = true;
268 }
269 } else if (UseGHASHIntrinsics) {
270 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
271 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
272 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
273 }
274
275 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
276 if (has_sha1() || has_sha256() || has_sha512()) {
277 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
278 if (FLAG_IS_DEFAULT(UseSHA)) {
279 FLAG_SET_DEFAULT(UseSHA, true);
280 }
281 } else {
282 if (UseSHA) {
283 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
284 FLAG_SET_DEFAULT(UseSHA, false);
285 }
286 }
287 } else if (UseSHA) {
288 warning("SHA instructions are not available on this CPU");
289 FLAG_SET_DEFAULT(UseSHA, false);
290 }
291
292 if (UseSHA && has_sha1()) {
293 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
294 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
295 }
296 } else if (UseSHA1Intrinsics) {
297 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
298 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
299 }
300
301 if (UseSHA && has_sha256()) {
302 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
303 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
304 }
305 } else if (UseSHA256Intrinsics) {
306 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
307 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
308 }
309
310 if (UseSHA && has_sha512()) {
311 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
312 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
313 }
314 } else if (UseSHA512Intrinsics) {
315 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
316 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
317 }
318
319 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
320 FLAG_SET_DEFAULT(UseSHA, false);
321 }
322
323 // SPARC T4 and above should have support for CRC32C instruction
324 if (has_crc32c()) {
325 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
326 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
327 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
328 }
329 } else {
330 if (UseCRC32CIntrinsics) {
331 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
332 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
333 }
334 }
335 } else if (UseCRC32CIntrinsics) {
336 warning("CRC32C instruction is not available on this CPU");
337 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
338 }
339
340 if (UseVIS > 2) {
341 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
342 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
343 }
344 } else if (UseAdler32Intrinsics) {
345 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
346 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
347 }
348
349 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
350 (cache_line_size > ContendedPaddingWidth))
351 ContendedPaddingWidth = cache_line_size;
352
353 // This machine does not allow unaligned memory accesses
354 if (UseUnalignedAccesses) {
355 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
356 warning("Unaligned memory access is not available on this CPU");
357 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
358 }
359
360 #ifndef PRODUCT
361 if (PrintMiscellaneous && Verbose) {
362 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
363 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
364 tty->print("Allocation");
365 if (AllocatePrefetchStyle <= 0) {
366 tty->print_cr(": no prefetching");
367 } else {
368 tty->print(" prefetching: ");
369 if (AllocatePrefetchInstr == 0) {
370 tty->print("PREFETCH");
371 } else if (AllocatePrefetchInstr == 1) {
372 tty->print("BIS");
373 }
374 if (AllocatePrefetchLines > 1) {
375 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
376 } else {
377 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
378 }
379 }
380 if (PrefetchCopyIntervalInBytes > 0) {
381 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
382 }
383 if (PrefetchScanIntervalInBytes > 0) {
384 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
385 }
386 if (PrefetchFieldsAhead > 0) {
387 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
388 }
389 if (ContendedPaddingWidth > 0) {
390 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
391 }
392 }
393 #endif // PRODUCT
394 }
395
396 void VM_Version::print_features() {
397 tty->print_cr("Version:%s", cpu_features());
398 }
399
400 int VM_Version::determine_features() {
401 if (UseV8InstrsOnly) {
402 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
403 return generic_v8_m;
404 }
405
406 int features = platform_features(unknown_m); // platform_features() is os_arch specific
407
408 if (features == unknown_m) {
409 features = generic_v9_m;
410 warning("Cannot recognize SPARC version. Default to V9");
411 }
412
413 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
414 if (UseNiagaraInstrs) { // Force code generation for Niagara
415 if (is_T_family(features)) {
416 // Happy to accomodate...
417 } else {
418 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
419 features |= T_family_m;
420 }
421 } else {
422 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
423 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
424 features &= ~(T_family_m | T1_model_m);
425 } else {
426 // Happy to accomodate...
427 }
428 }
429
430 return features;
431 }
432
433 static int saved_features = 0;
434
435 void VM_Version::allow_all() {
436 saved_features = _features;
437 _features = all_features_m;
438 }
439
440 void VM_Version::revert() {
441 _features = saved_features;
442 }
443
444 unsigned int VM_Version::calc_parallel_worker_threads() {
445 unsigned int result;
446 if (is_M_series()) {
447 // for now, use same gc thread calculation for M-series as for niagara-plus
448 // in future, we may want to tweak parameters for nof_parallel_worker_thread
449 result = nof_parallel_worker_threads(5, 16, 8);
450 } else if (is_niagara_plus()) {
451 result = nof_parallel_worker_threads(5, 16, 8);
452 } else {
453 result = nof_parallel_worker_threads(5, 8, 8);
454 }
455 return result;
456 }
457
458 void VM_Version::early_initialize() {
459
460 os::Solaris::initialize_features_info();
461
462 _features = determine_features();
463 }