107 static int platform_features(int features);
108
109 // Returns true if the platform is in the niagara line (T series)
110 static bool is_M_family(int features) { return (features & M_family_m) != 0; }
111 static bool is_T_family(int features) { return (features & T_family_m) != 0; }
112 static bool is_niagara() { return is_T_family(_features); }
113 #ifdef ASSERT
114 static bool is_niagara(int features) {
115 // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
116 // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
117 return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
118 }
119 #endif
120
121 // Returns true if it is niagara1 (T1).
122 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
123
124 static int maximum_niagara1_processor_count() { return 32; }
125
126 public:
127 // Initialization
128 static void initialize();
129
130 // Instruction support
131 static bool has_v8() { return (_features & v8_instructions_m) != 0; }
132 static bool has_v9() { return (_features & v9_instructions_m) != 0; }
133 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }
134 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }
135 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }
136 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
137 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
138 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
139 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
140 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
141 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
142 static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; }
143 static bool has_aes() { return (_features & aes_instructions_m) != 0; }
144 static bool has_sha1() { return (_features & sha1_instruction_m) != 0; }
145 static bool has_sha256() { return (_features & sha256_instruction_m) != 0; }
146 static bool has_sha512() { return (_features & sha512_instruction_m) != 0; }
147 static bool has_crc32c() { return (_features & crc32c_instruction_m) != 0; }
148
149 static bool supports_compare_and_exchange()
150 { return has_v9(); }
151
152 // Returns true if the platform is in the niagara line (T series)
153 // and newer than the niagara1.
154 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
155
156 static bool is_M_series() { return is_M_family(_features); }
157 static bool is_T4() { return is_T_family(_features) && has_cbcond(); }
158 static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); }
159
160 // Fujitsu SPARC64
161 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
162
163 static bool is_sun4v() { return (_features & sun4v_m) != 0; }
164 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
165
166 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
167 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
168
169 // T4 and newer Sparc have fast RDPC instruction.
170 static bool has_fast_rdpc() { return is_T4(); }
171
172 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
173 static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
174
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107 static int platform_features(int features);
108
109 // Returns true if the platform is in the niagara line (T series)
110 static bool is_M_family(int features) { return (features & M_family_m) != 0; }
111 static bool is_T_family(int features) { return (features & T_family_m) != 0; }
112 static bool is_niagara() { return is_T_family(_features); }
113 #ifdef ASSERT
114 static bool is_niagara(int features) {
115 // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
116 // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
117 return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
118 }
119 #endif
120
121 // Returns true if it is niagara1 (T1).
122 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
123
124 static int maximum_niagara1_processor_count() { return 32; }
125
126 public:
127 static void early_initialize();
128 // Initialization
129 static void initialize();
130
131 // Instruction support
132 static bool has_v8() { return (_features & v8_instructions_m) != 0; }
133 static bool has_v9() { return (_features & v9_instructions_m) != 0; }
134 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }
135 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }
136 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }
137 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
138 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
139 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
140 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
141 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
142 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
143 static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; }
144 static bool has_aes() { return (_features & aes_instructions_m) != 0; }
145 static bool has_sha1() { return (_features & sha1_instruction_m) != 0; }
146 static bool has_sha256() { return (_features & sha256_instruction_m) != 0; }
147 static bool has_sha512() { return (_features & sha512_instruction_m) != 0; }
148 static bool has_crc32c() { return (_features & crc32c_instruction_m) != 0; }
149
150 static bool supports_compare_and_exchange()
151 { return has_v9(); }
152
153 // Returns true if the platform is in the niagara line (T series)
154 // and newer than the niagara1.
155 static bool is_niagara_plus() { assert(_features != 0, "System initialization is not complete."); return is_T_family(_features) && !is_T1_model(_features); }
156
157 static bool is_M_series() { return is_M_family(_features); }
158 static bool is_T4() { return is_T_family(_features) && has_cbcond(); }
159 static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); }
160
161 // Fujitsu SPARC64
162 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
163
164 static bool is_sun4v() { return (_features & sun4v_m) != 0; }
165 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
166
167 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
168 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
169
170 // T4 and newer Sparc have fast RDPC instruction.
171 static bool has_fast_rdpc() { return is_T4(); }
172
173 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
174 static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
175
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