1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "assembler_sparc.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #ifndef SERIALGC
40 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
41 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
42 #include "gc_implementation/g1/heapRegion.hpp"
43 #endif
44
45 #ifdef PRODUCT
46 #define BLOCK_COMMENT(str) /* nothing */
47 #else
48 #define BLOCK_COMMENT(str) block_comment(str)
49 #endif
50
51 // Convert the raw encoding form into the form expected by the
52 // constructor for Address.
53 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
54 assert(scale == 0, "not supported");
55 RelocationHolder rspec;
56 if (disp_is_oop) {
57 rspec = Relocation::spec_simple(relocInfo::oop_type);
58 }
59
60 Register rindex = as_Register(index);
61 if (rindex != G0) {
62 Address madr(as_Register(base), rindex);
63 madr._rspec = rspec;
64 return madr;
65 } else {
66 Address madr(as_Register(base), disp);
67 madr._rspec = rspec;
68 return madr;
69 }
70 }
71
72 Address Argument::address_in_frame() const {
73 // Warning: In LP64 mode disp will occupy more than 10 bits, but
74 // op codes such as ld or ldx, only access disp() to get
75 // their simm13 argument.
76 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS;
77 if (is_in())
78 return Address(FP, disp); // In argument.
79 else
80 return Address(SP, disp); // Out argument.
81 }
82
83 static const char* argumentNames[][2] = {
84 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},
85 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},
86 {"A(n>9)","P(n>9)"}
87 };
88
89 const char* Argument::name() const {
90 int nofArgs = sizeof argumentNames / sizeof argumentNames[0];
91 int num = number();
92 if (num >= nofArgs) num = nofArgs - 1;
93 return argumentNames[num][is_in() ? 1 : 0];
94 }
95
96 void Assembler::print_instruction(int inst) {
97 const char* s;
98 switch (inv_op(inst)) {
99 default: s = "????"; break;
100 case call_op: s = "call"; break;
101 case branch_op:
102 switch (inv_op2(inst)) {
103 case fb_op2: s = "fb"; break;
104 case fbp_op2: s = "fbp"; break;
105 case br_op2: s = "br"; break;
106 case bp_op2: s = "bp"; break;
107 case cb_op2: s = "cb"; break;
108 case bpr_op2: {
109 if (is_cbc(inst)) {
110 s = is_cxb(inst) ? "cxb" : "cwb";
111 } else {
112 s = "bpr";
113 }
114 break;
115 }
116 default: s = "????"; break;
117 }
118 }
119 ::tty->print("%s", s);
120 }
121
122
123 // Patch instruction inst at offset inst_pos to refer to dest_pos
124 // and return the resulting instruction.
125 // We should have pcs, not offsets, but since all is relative, it will work out
126 // OK.
127 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) {
128
129 int m; // mask for displacement field
130 int v; // new value for displacement field
131 const int word_aligned_ones = -4;
132 switch (inv_op(inst)) {
133 default: ShouldNotReachHere();
134 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break;
135 case branch_op:
136 switch (inv_op2(inst)) {
137 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
138 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
139 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
140 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
141 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
142 case bpr_op2: {
143 if (is_cbc(inst)) {
144 m = wdisp10(word_aligned_ones, 0);
145 v = wdisp10(dest_pos, inst_pos);
146 } else {
147 m = wdisp16(word_aligned_ones, 0);
148 v = wdisp16(dest_pos, inst_pos);
149 }
150 break;
151 }
152 default: ShouldNotReachHere();
153 }
154 }
155 return inst & ~m | v;
156 }
157
158 // Return the offset of the branch destionation of instruction inst
159 // at offset pos.
160 // Should have pcs, but since all is relative, it works out.
161 int Assembler::branch_destination(int inst, int pos) {
162 int r;
163 switch (inv_op(inst)) {
164 default: ShouldNotReachHere();
165 case call_op: r = inv_wdisp(inst, pos, 30); break;
166 case branch_op:
167 switch (inv_op2(inst)) {
168 case fbp_op2: r = inv_wdisp( inst, pos, 19); break;
169 case bp_op2: r = inv_wdisp( inst, pos, 19); break;
170 case fb_op2: r = inv_wdisp( inst, pos, 22); break;
171 case br_op2: r = inv_wdisp( inst, pos, 22); break;
172 case cb_op2: r = inv_wdisp( inst, pos, 22); break;
173 case bpr_op2: {
174 if (is_cbc(inst)) {
175 r = inv_wdisp10(inst, pos);
176 } else {
177 r = inv_wdisp16(inst, pos);
178 }
179 break;
180 }
181 default: ShouldNotReachHere();
182 }
183 }
184 return r;
185 }
186
187 int AbstractAssembler::code_fill_byte() {
188 return 0x00; // illegal instruction 0x00000000
189 }
190
191 Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) {
192 switch (in) {
193 case rc_z: return equal;
194 case rc_lez: return lessEqual;
195 case rc_lz: return less;
196 case rc_nz: return notEqual;
197 case rc_gz: return greater;
198 case rc_gez: return greaterEqual;
199 default:
200 ShouldNotReachHere();
201 }
202 return equal;
203 }
204
205 // Generate a bunch 'o stuff (including v9's
206 #ifndef PRODUCT
207 void Assembler::test_v9() {
208 add( G0, G1, G2 );
209 add( G3, 0, G4 );
210
211 addcc( G5, G6, G7 );
212 addcc( I0, 1, I1 );
213 addc( I2, I3, I4 );
214 addc( I5, -1, I6 );
215 addccc( I7, L0, L1 );
216 addccc( L2, (1 << 12) - 2, L3 );
217
218 Label lbl1, lbl2, lbl3;
219
220 bind(lbl1);
221
222 bpr( rc_z, true, pn, L4, pc(), relocInfo::oop_type );
223 delayed()->nop();
224 bpr( rc_lez, false, pt, L5, lbl1);
225 delayed()->nop();
226
227 fb( f_never, true, pc() + 4, relocInfo::none);
228 delayed()->nop();
229 fb( f_notEqual, false, lbl2 );
230 delayed()->nop();
231
232 fbp( f_notZero, true, fcc0, pn, pc() - 4, relocInfo::none);
233 delayed()->nop();
234 fbp( f_lessOrGreater, false, fcc1, pt, lbl3 );
235 delayed()->nop();
236
237 br( equal, true, pc() + 1024, relocInfo::none);
238 delayed()->nop();
239 br( lessEqual, false, lbl1 );
240 delayed()->nop();
241 br( never, false, lbl1 );
242 delayed()->nop();
243
244 bp( less, true, icc, pn, pc(), relocInfo::none);
245 delayed()->nop();
246 bp( lessEqualUnsigned, false, xcc, pt, lbl2 );
247 delayed()->nop();
248
249 call( pc(), relocInfo::none);
250 delayed()->nop();
251 call( lbl3 );
252 delayed()->nop();
253
254
255 casa( L6, L7, O0 );
256 casxa( O1, O2, O3, 0 );
257
258 udiv( O4, O5, O7 );
259 udiv( G0, (1 << 12) - 1, G1 );
260 sdiv( G1, G2, G3 );
261 sdiv( G4, -((1 << 12) - 1), G5 );
262 udivcc( G6, G7, I0 );
263 udivcc( I1, -((1 << 12) - 2), I2 );
264 sdivcc( I3, I4, I5 );
265 sdivcc( I6, -((1 << 12) - 0), I7 );
266
267 done();
268 retry();
269
270 fadd( FloatRegisterImpl::S, F0, F1, F2 );
271 fsub( FloatRegisterImpl::D, F34, F0, F62 );
272
273 fcmp( FloatRegisterImpl::Q, fcc0, F0, F60);
274 fcmpe( FloatRegisterImpl::S, fcc1, F31, F30);
275
276 ftox( FloatRegisterImpl::D, F2, F4 );
277 ftoi( FloatRegisterImpl::Q, F4, F8 );
278
279 ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 );
280
281 fxtof( FloatRegisterImpl::S, F4, F5 );
282 fitof( FloatRegisterImpl::D, F6, F8 );
283
284 fmov( FloatRegisterImpl::Q, F16, F20 );
285 fneg( FloatRegisterImpl::S, F6, F7 );
286 fabs( FloatRegisterImpl::D, F10, F12 );
287
288 fmul( FloatRegisterImpl::Q, F24, F28, F32 );
289 fmul( FloatRegisterImpl::S, FloatRegisterImpl::D, F8, F9, F14 );
290 fdiv( FloatRegisterImpl::S, F10, F11, F12 );
291
292 fsqrt( FloatRegisterImpl::S, F13, F14 );
293
294 flush( L0, L1 );
295 flush( L2, -1 );
296
297 flushw();
298
299 illtrap( (1 << 22) - 2);
300
301 impdep1( 17, (1 << 19) - 1 );
302 impdep2( 3, 0 );
303
304 jmpl( L3, L4, L5 );
305 delayed()->nop();
306 jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none));
307 delayed()->nop();
308
309
310 ldf( FloatRegisterImpl::S, O0, O1, F15 );
311 ldf( FloatRegisterImpl::D, O2, -1, F14 );
312
313
314 ldfsr( O3, O4 );
315 ldfsr( O5, -1 );
316 ldxfsr( O6, O7 );
317 ldxfsr( I0, -1 );
318
319 ldfa( FloatRegisterImpl::D, I1, I2, 1, F16 );
320 ldfa( FloatRegisterImpl::Q, I3, -1, F36 );
321
322 ldsb( I4, I5, I6 );
323 ldsb( I7, -1, G0 );
324 ldsh( G1, G3, G4 );
325 ldsh( G5, -1, G6 );
326 ldsw( G7, L0, L1 );
327 ldsw( L2, -1, L3 );
328 ldub( L4, L5, L6 );
329 ldub( L7, -1, O0 );
330 lduh( O1, O2, O3 );
331 lduh( O4, -1, O5 );
332 lduw( O6, O7, G0 );
333 lduw( G1, -1, G2 );
334 ldx( G3, G4, G5 );
335 ldx( G6, -1, G7 );
336 ldd( I0, I1, I2 );
337 ldd( I3, -1, I4 );
338
339 ldsba( I5, I6, 2, I7 );
340 ldsba( L0, -1, L1 );
341 ldsha( L2, L3, 3, L4 );
342 ldsha( L5, -1, L6 );
343 ldswa( L7, O0, (1 << 8) - 1, O1 );
344 ldswa( O2, -1, O3 );
345 lduba( O4, O5, 0, O6 );
346 lduba( O7, -1, I0 );
347 lduha( I1, I2, 1, I3 );
348 lduha( I4, -1, I5 );
349 lduwa( I6, I7, 2, L0 );
350 lduwa( L1, -1, L2 );
351 ldxa( L3, L4, 3, L5 );
352 ldxa( L6, -1, L7 );
353 ldda( G0, G1, 4, G2 );
354 ldda( G3, -1, G4 );
355
356 ldstub( G5, G6, G7 );
357 ldstub( O0, -1, O1 );
358
359 ldstuba( O2, O3, 5, O4 );
360 ldstuba( O5, -1, O6 );
361
362 and3( I0, L0, O0 );
363 and3( G7, -1, O7 );
364 andcc( L2, I2, G2 );
365 andcc( L4, -1, G4 );
366 andn( I5, I6, I7 );
367 andn( I6, -1, I7 );
368 andncc( I5, I6, I7 );
369 andncc( I7, -1, I6 );
370 or3( I5, I6, I7 );
371 or3( I7, -1, I6 );
372 orcc( I5, I6, I7 );
373 orcc( I7, -1, I6 );
374 orn( I5, I6, I7 );
375 orn( I7, -1, I6 );
376 orncc( I5, I6, I7 );
377 orncc( I7, -1, I6 );
378 xor3( I5, I6, I7 );
379 xor3( I7, -1, I6 );
380 xorcc( I5, I6, I7 );
381 xorcc( I7, -1, I6 );
382 xnor( I5, I6, I7 );
383 xnor( I7, -1, I6 );
384 xnorcc( I5, I6, I7 );
385 xnorcc( I7, -1, I6 );
386
387 membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) );
388 membar( StoreStore );
389 membar( LoadStore );
390 membar( StoreLoad );
391 membar( LoadLoad );
392 membar( Sync );
393 membar( MemIssue );
394 membar( Lookaside );
395
396 fmov( FloatRegisterImpl::S, f_ordered, true, fcc2, F16, F17 );
397 fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 );
398
399 movcc( overflowClear, false, icc, I6, L4 );
400 movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 );
401
402 movr( rc_nz, I5, I6, I7 );
403 movr( rc_gz, L1, -1, L2 );
404
405 mulx( I5, I6, I7 );
406 mulx( I7, -1, I6 );
407 sdivx( I5, I6, I7 );
408 sdivx( I7, -1, I6 );
409 udivx( I5, I6, I7 );
410 udivx( I7, -1, I6 );
411
412 umul( I5, I6, I7 );
413 umul( I7, -1, I6 );
414 smul( I5, I6, I7 );
415 smul( I7, -1, I6 );
416 umulcc( I5, I6, I7 );
417 umulcc( I7, -1, I6 );
418 smulcc( I5, I6, I7 );
419 smulcc( I7, -1, I6 );
420
421 mulscc( I5, I6, I7 );
422 mulscc( I7, -1, I6 );
423
424 nop();
425
426
427 popc( G0, G1);
428 popc( -1, G2);
429
430 prefetch( L1, L2, severalReads );
431 prefetch( L3, -1, oneRead );
432 prefetcha( O3, O2, 6, severalWritesAndPossiblyReads );
433 prefetcha( G2, -1, oneWrite );
434
435 rett( I7, I7);
436 delayed()->nop();
437 rett( G0, -1, relocInfo::none);
438 delayed()->nop();
439
440 save( I5, I6, I7 );
441 save( I7, -1, I6 );
442 restore( I5, I6, I7 );
443 restore( I7, -1, I6 );
444
445 saved();
446 restored();
447
448 sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none));
449
450 sll( I5, I6, I7 );
451 sll( I7, 31, I6 );
452 srl( I5, I6, I7 );
453 srl( I7, 0, I6 );
454 sra( I5, I6, I7 );
455 sra( I7, 30, I6 );
456 sllx( I5, I6, I7 );
457 sllx( I7, 63, I6 );
458 srlx( I5, I6, I7 );
459 srlx( I7, 0, I6 );
460 srax( I5, I6, I7 );
461 srax( I7, 62, I6 );
462
463 sir( -1 );
464
465 stbar();
466
467 stf( FloatRegisterImpl::Q, F40, G0, I7 );
468 stf( FloatRegisterImpl::S, F18, I3, -1 );
469
470 stfsr( L1, L2 );
471 stfsr( I7, -1 );
472 stxfsr( I6, I5 );
473 stxfsr( L4, -1 );
474
475 stfa( FloatRegisterImpl::D, F22, I6, I7, 7 );
476 stfa( FloatRegisterImpl::Q, F44, G0, -1 );
477
478 stb( L5, O2, I7 );
479 stb( I7, I6, -1 );
480 sth( L5, O2, I7 );
481 sth( I7, I6, -1 );
482 stw( L5, O2, I7 );
483 stw( I7, I6, -1 );
484 stx( L5, O2, I7 );
485 stx( I7, I6, -1 );
486 std( L5, O2, I7 );
487 std( I7, I6, -1 );
488
489 stba( L5, O2, I7, 8 );
490 stba( I7, I6, -1 );
491 stha( L5, O2, I7, 9 );
492 stha( I7, I6, -1 );
493 stwa( L5, O2, I7, 0 );
494 stwa( I7, I6, -1 );
495 stxa( L5, O2, I7, 11 );
496 stxa( I7, I6, -1 );
497 stda( L5, O2, I7, 12 );
498 stda( I7, I6, -1 );
499
500 sub( I5, I6, I7 );
501 sub( I7, -1, I6 );
502 subcc( I5, I6, I7 );
503 subcc( I7, -1, I6 );
504 subc( I5, I6, I7 );
505 subc( I7, -1, I6 );
506 subccc( I5, I6, I7 );
507 subccc( I7, -1, I6 );
508
509 swap( I5, I6, I7 );
510 swap( I7, -1, I6 );
511
512 swapa( G0, G1, 13, G2 );
513 swapa( I7, -1, I6 );
514
515 taddcc( I5, I6, I7 );
516 taddcc( I7, -1, I6 );
517 taddcctv( I5, I6, I7 );
518 taddcctv( I7, -1, I6 );
519
520 tsubcc( I5, I6, I7 );
521 tsubcc( I7, -1, I6 );
522 tsubcctv( I5, I6, I7 );
523 tsubcctv( I7, -1, I6 );
524
525 trap( overflowClear, xcc, G0, G1 );
526 trap( lessEqual, icc, I7, 17 );
527
528 bind(lbl2);
529 bind(lbl3);
530
531 code()->decode();
532 }
533
534 // Generate a bunch 'o stuff unique to V8
535 void Assembler::test_v8_onlys() {
536 Label lbl1;
537
538 cb( cp_0or1or2, false, pc() - 4, relocInfo::none);
539 delayed()->nop();
540 cb( cp_never, true, lbl1);
541 delayed()->nop();
542
543 cpop1(1, 2, 3, 4);
544 cpop2(5, 6, 7, 8);
545
546 ldc( I0, I1, 31);
547 ldc( I2, -1, 0);
548
549 lddc( I4, I4, 30);
550 lddc( I6, 0, 1 );
551
552 ldcsr( L0, L1, 0);
553 ldcsr( L1, (1 << 12) - 1, 17 );
554
555 stc( 31, L4, L5);
556 stc( 30, L6, -(1 << 12) );
557
558 stdc( 0, L7, G0);
559 stdc( 1, G1, 0 );
560
561 stcsr( 16, G2, G3);
562 stcsr( 17, G4, 1 );
563
564 stdcq( 4, G5, G6);
565 stdcq( 5, G7, -1 );
566
567 bind(lbl1);
568
569 code()->decode();
570 }
571 #endif
572
573 // Implementation of MacroAssembler
574
575 void MacroAssembler::null_check(Register reg, int offset) {
576 if (needs_explicit_null_check((intptr_t)offset)) {
577 // provoke OS NULL exception if reg = NULL by
578 // accessing M[reg] w/o changing any registers
579 ld_ptr(reg, 0, G0);
580 }
581 else {
582 // nothing to do, (later) access of M[reg + offset]
583 // will provoke OS NULL exception if reg = NULL
584 }
585 }
586
587 // Ring buffer jumps
588
589 #ifndef PRODUCT
590 void MacroAssembler::ret( bool trace ) { if (trace) {
591 mov(I7, O7); // traceable register
592 JMP(O7, 2 * BytesPerInstWord);
593 } else {
594 jmpl( I7, 2 * BytesPerInstWord, G0 );
595 }
596 }
597
598 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
599 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
600 #endif /* PRODUCT */
601
602
603 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) {
604 assert_not_delayed();
605 // This can only be traceable if r1 & r2 are visible after a window save
606 if (TraceJumps) {
607 #ifndef PRODUCT
608 save_frame(0);
609 verify_thread();
610 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
611 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
612 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
613 add(O2, O1, O1);
614
615 add(r1->after_save(), r2->after_save(), O2);
616 set((intptr_t)file, O3);
617 set(line, O4);
618 Label L;
619 // get nearby pc, store jmp target
620 call(L, relocInfo::none); // No relocation for call to pc+0x8
621 delayed()->st(O2, O1, 0);
622 bind(L);
623
624 // store nearby pc
625 st(O7, O1, sizeof(intptr_t));
626 // store file
627 st(O3, O1, 2*sizeof(intptr_t));
628 // store line
629 st(O4, O1, 3*sizeof(intptr_t));
630 add(O0, 1, O0);
631 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
632 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
633 restore();
634 #endif /* PRODUCT */
635 }
636 jmpl(r1, r2, G0);
637 }
638 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) {
639 assert_not_delayed();
640 // This can only be traceable if r1 is visible after a window save
641 if (TraceJumps) {
642 #ifndef PRODUCT
643 save_frame(0);
644 verify_thread();
645 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
646 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
647 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
648 add(O2, O1, O1);
649
650 add(r1->after_save(), offset, O2);
651 set((intptr_t)file, O3);
652 set(line, O4);
653 Label L;
654 // get nearby pc, store jmp target
655 call(L, relocInfo::none); // No relocation for call to pc+0x8
656 delayed()->st(O2, O1, 0);
657 bind(L);
658
659 // store nearby pc
660 st(O7, O1, sizeof(intptr_t));
661 // store file
662 st(O3, O1, 2*sizeof(intptr_t));
663 // store line
664 st(O4, O1, 3*sizeof(intptr_t));
665 add(O0, 1, O0);
666 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
667 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
668 restore();
669 #endif /* PRODUCT */
670 }
671 jmp(r1, offset);
672 }
673
674 // This code sequence is relocatable to any address, even on LP64.
675 void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) {
676 assert_not_delayed();
677 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
678 // variable length instruction streams.
679 patchable_sethi(addrlit, temp);
680 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement.
681 if (TraceJumps) {
682 #ifndef PRODUCT
683 // Must do the add here so relocation can find the remainder of the
684 // value to be relocated.
685 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset));
686 save_frame(0);
687 verify_thread();
688 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
689 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
690 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
691 add(O2, O1, O1);
692
693 set((intptr_t)file, O3);
694 set(line, O4);
695 Label L;
696
697 // get nearby pc, store jmp target
698 call(L, relocInfo::none); // No relocation for call to pc+0x8
699 delayed()->st(a.base()->after_save(), O1, 0);
700 bind(L);
701
702 // store nearby pc
703 st(O7, O1, sizeof(intptr_t));
704 // store file
705 st(O3, O1, 2*sizeof(intptr_t));
706 // store line
707 st(O4, O1, 3*sizeof(intptr_t));
708 add(O0, 1, O0);
709 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
710 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
711 restore();
712 jmpl(a.base(), G0, d);
713 #else
714 jmpl(a.base(), a.disp(), d);
715 #endif /* PRODUCT */
716 } else {
717 jmpl(a.base(), a.disp(), d);
718 }
719 }
720
721 void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) {
722 jumpl(addrlit, temp, G0, offset, file, line);
723 }
724
725
726 // Convert to C varargs format
727 void MacroAssembler::set_varargs( Argument inArg, Register d ) {
728 // spill register-resident args to their memory slots
729 // (SPARC calling convention requires callers to have already preallocated these)
730 // Note that the inArg might in fact be an outgoing argument,
731 // if a leaf routine or stub does some tricky argument shuffling.
732 // This routine must work even though one of the saved arguments
733 // is in the d register (e.g., set_varargs(Argument(0, false), O0)).
734 for (Argument savePtr = inArg;
735 savePtr.is_register();
736 savePtr = savePtr.successor()) {
737 st_ptr(savePtr.as_register(), savePtr.address_in_frame());
738 }
739 // return the address of the first memory slot
740 Address a = inArg.address_in_frame();
741 add(a.base(), a.disp(), d);
742 }
743
744 // Conditional breakpoint (for assertion checks in assembly code)
745 void MacroAssembler::breakpoint_trap(Condition c, CC cc) {
746 trap(c, cc, G0, ST_RESERVED_FOR_USER_0);
747 }
748
749 // We want to use ST_BREAKPOINT here, but the debugger is confused by it.
750 void MacroAssembler::breakpoint_trap() {
751 trap(ST_RESERVED_FOR_USER_0);
752 }
753
754 // flush windows (except current) using flushw instruction if avail.
755 void MacroAssembler::flush_windows() {
756 if (VM_Version::v9_instructions_work()) flushw();
757 else flush_windows_trap();
758 }
759
760 // Write serialization page so VM thread can do a pseudo remote membar
761 // We use the current thread pointer to calculate a thread specific
762 // offset to write to within the page. This minimizes bus traffic
763 // due to cache line collision.
764 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
765 srl(thread, os::get_serialize_page_shift_count(), tmp2);
766 if (Assembler::is_simm13(os::vm_page_size())) {
767 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2);
768 }
769 else {
770 set((os::vm_page_size() - sizeof(int)), tmp1);
771 and3(tmp2, tmp1, tmp2);
772 }
773 set(os::get_memory_serialize_page(), tmp1);
774 st(G0, tmp1, tmp2);
775 }
776
777
778
779 void MacroAssembler::enter() {
780 Unimplemented();
781 }
782
783 void MacroAssembler::leave() {
784 Unimplemented();
785 }
786
787 void MacroAssembler::mult(Register s1, Register s2, Register d) {
788 if(VM_Version::v9_instructions_work()) {
789 mulx (s1, s2, d);
790 } else {
791 smul (s1, s2, d);
792 }
793 }
794
795 void MacroAssembler::mult(Register s1, int simm13a, Register d) {
796 if(VM_Version::v9_instructions_work()) {
797 mulx (s1, simm13a, d);
798 } else {
799 smul (s1, simm13a, d);
800 }
801 }
802
803
804 #ifdef ASSERT
805 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) {
806 const Register s1 = G3_scratch;
807 const Register s2 = G4_scratch;
808 Label get_psr_test;
809 // Get the condition codes the V8 way.
810 read_ccr_trap(s1);
811 mov(ccr_save, s2);
812 // This is a test of V8 which has icc but not xcc
813 // so mask off the xcc bits
814 and3(s2, 0xf, s2);
815 // Compare condition codes from the V8 and V9 ways.
816 subcc(s2, s1, G0);
817 br(Assembler::notEqual, true, Assembler::pt, get_psr_test);
818 delayed()->breakpoint_trap();
819 bind(get_psr_test);
820 }
821
822 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) {
823 const Register s1 = G3_scratch;
824 const Register s2 = G4_scratch;
825 Label set_psr_test;
826 // Write out the saved condition codes the V8 way
827 write_ccr_trap(ccr_save, s1, s2);
828 // Read back the condition codes using the V9 instruction
829 rdccr(s1);
830 mov(ccr_save, s2);
831 // This is a test of V8 which has icc but not xcc
832 // so mask off the xcc bits
833 and3(s2, 0xf, s2);
834 and3(s1, 0xf, s1);
835 // Compare the V8 way with the V9 way.
836 subcc(s2, s1, G0);
837 br(Assembler::notEqual, true, Assembler::pt, set_psr_test);
838 delayed()->breakpoint_trap();
839 bind(set_psr_test);
840 }
841 #else
842 #define read_ccr_v8_assert(x)
843 #define write_ccr_v8_assert(x)
844 #endif // ASSERT
845
846 void MacroAssembler::read_ccr(Register ccr_save) {
847 if (VM_Version::v9_instructions_work()) {
848 rdccr(ccr_save);
849 // Test code sequence used on V8. Do not move above rdccr.
850 read_ccr_v8_assert(ccr_save);
851 } else {
852 read_ccr_trap(ccr_save);
853 }
854 }
855
856 void MacroAssembler::write_ccr(Register ccr_save) {
857 if (VM_Version::v9_instructions_work()) {
858 // Test code sequence used on V8. Do not move below wrccr.
859 write_ccr_v8_assert(ccr_save);
860 wrccr(ccr_save);
861 } else {
862 const Register temp_reg1 = G3_scratch;
863 const Register temp_reg2 = G4_scratch;
864 write_ccr_trap(ccr_save, temp_reg1, temp_reg2);
865 }
866 }
867
868
869 // Calls to C land
870
871 #ifdef ASSERT
872 // a hook for debugging
873 static Thread* reinitialize_thread() {
874 return ThreadLocalStorage::thread();
875 }
876 #else
877 #define reinitialize_thread ThreadLocalStorage::thread
878 #endif
879
880 #ifdef ASSERT
881 address last_get_thread = NULL;
882 #endif
883
884 // call this when G2_thread is not known to be valid
885 void MacroAssembler::get_thread() {
886 save_frame(0); // to avoid clobbering O0
887 mov(G1, L0); // avoid clobbering G1
888 mov(G5_method, L1); // avoid clobbering G5
889 mov(G3, L2); // avoid clobbering G3 also
890 mov(G4, L5); // avoid clobbering G4
891 #ifdef ASSERT
892 AddressLiteral last_get_thread_addrlit(&last_get_thread);
893 set(last_get_thread_addrlit, L3);
894 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call
895 st_ptr(L4, L3, 0);
896 #endif
897 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type);
898 delayed()->nop();
899 mov(L0, G1);
900 mov(L1, G5_method);
901 mov(L2, G3);
902 mov(L5, G4);
903 restore(O0, 0, G2_thread);
904 }
905
906 static Thread* verify_thread_subroutine(Thread* gthread_value) {
907 Thread* correct_value = ThreadLocalStorage::thread();
908 guarantee(gthread_value == correct_value, "G2_thread value must be the thread");
909 return correct_value;
910 }
911
912 void MacroAssembler::verify_thread() {
913 if (VerifyThread) {
914 // NOTE: this chops off the heads of the 64-bit O registers.
915 #ifdef CC_INTERP
916 save_frame(0);
917 #else
918 // make sure G2_thread contains the right value
919 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof)
920 mov(G1, L1); // avoid clobbering G1
921 // G2 saved below
922 mov(G3, L3); // avoid clobbering G3
923 mov(G4, L4); // avoid clobbering G4
924 mov(G5_method, L5); // avoid clobbering G5_method
925 #endif /* CC_INTERP */
926 #if defined(COMPILER2) && !defined(_LP64)
927 // Save & restore possible 64-bit Long arguments in G-regs
928 srlx(G1,32,L0);
929 srlx(G4,32,L6);
930 #endif
931 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type);
932 delayed()->mov(G2_thread, O0);
933
934 mov(L1, G1); // Restore G1
935 // G2 restored below
936 mov(L3, G3); // restore G3
937 mov(L4, G4); // restore G4
938 mov(L5, G5_method); // restore G5_method
939 #if defined(COMPILER2) && !defined(_LP64)
940 // Save & restore possible 64-bit Long arguments in G-regs
941 sllx(L0,32,G2); // Move old high G1 bits high in G2
942 srl(G1, 0,G1); // Clear current high G1 bits
943 or3 (G1,G2,G1); // Recover 64-bit G1
944 sllx(L6,32,G2); // Move old high G4 bits high in G2
945 srl(G4, 0,G4); // Clear current high G4 bits
946 or3 (G4,G2,G4); // Recover 64-bit G4
947 #endif
948 restore(O0, 0, G2_thread);
949 }
950 }
951
952
953 void MacroAssembler::save_thread(const Register thread_cache) {
954 verify_thread();
955 if (thread_cache->is_valid()) {
956 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
957 mov(G2_thread, thread_cache);
958 }
959 if (VerifyThread) {
960 // smash G2_thread, as if the VM were about to anyway
961 set(0x67676767, G2_thread);
962 }
963 }
964
965
966 void MacroAssembler::restore_thread(const Register thread_cache) {
967 if (thread_cache->is_valid()) {
968 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
969 mov(thread_cache, G2_thread);
970 verify_thread();
971 } else {
972 // do it the slow way
973 get_thread();
974 }
975 }
976
977
978 // %%% maybe get rid of [re]set_last_Java_frame
979 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) {
980 assert_not_delayed();
981 Address flags(G2_thread, JavaThread::frame_anchor_offset() +
982 JavaFrameAnchor::flags_offset());
983 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset());
984
985 // Always set last_Java_pc and flags first because once last_Java_sp is visible
986 // has_last_Java_frame is true and users will look at the rest of the fields.
987 // (Note: flags should always be zero before we get here so doesn't need to be set.)
988
989 #ifdef ASSERT
990 // Verify that flags was zeroed on return to Java
991 Label PcOk;
992 save_frame(0); // to avoid clobbering O0
993 ld_ptr(pc_addr, L0);
994 br_null(L0, false, Assembler::pt, PcOk);
995 stop("last_Java_pc not zeroed before leaving Java");
996 bind(PcOk);
997
998 // Verify that flags was zeroed on return to Java
999 Label FlagsOk;
1000 ld(flags, L0);
1001 tst(L0);
1002 br(Assembler::zero, false, Assembler::pt, FlagsOk);
1003 delayed() -> restore();
1004 stop("flags not zeroed before leaving Java");
1005 bind(FlagsOk);
1006 #endif /* ASSERT */
1007 //
1008 // When returning from calling out from Java mode the frame anchor's last_Java_pc
1009 // will always be set to NULL. It is set here so that if we are doing a call to
1010 // native (not VM) that we capture the known pc and don't have to rely on the
1011 // native call having a standard frame linkage where we can find the pc.
1012
1013 if (last_Java_pc->is_valid()) {
1014 st_ptr(last_Java_pc, pc_addr);
1015 }
1016
1017 #ifdef _LP64
1018 #ifdef ASSERT
1019 // Make sure that we have an odd stack
1020 Label StackOk;
1021 andcc(last_java_sp, 0x01, G0);
1022 br(Assembler::notZero, false, Assembler::pt, StackOk);
1023 delayed()->nop();
1024 stop("Stack Not Biased in set_last_Java_frame");
1025 bind(StackOk);
1026 #endif // ASSERT
1027 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame");
1028 add( last_java_sp, STACK_BIAS, G4_scratch );
1029 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset());
1030 #else
1031 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset());
1032 #endif // _LP64
1033 }
1034
1035 void MacroAssembler::reset_last_Java_frame(void) {
1036 assert_not_delayed();
1037
1038 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset());
1039 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
1040 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
1041
1042 #ifdef ASSERT
1043 // check that it WAS previously set
1044 #ifdef CC_INTERP
1045 save_frame(0);
1046 #else
1047 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof
1048 #endif /* CC_INTERP */
1049 ld_ptr(sp_addr, L0);
1050 tst(L0);
1051 breakpoint_trap(Assembler::zero, Assembler::ptr_cc);
1052 restore();
1053 #endif // ASSERT
1054
1055 st_ptr(G0, sp_addr);
1056 // Always return last_Java_pc to zero
1057 st_ptr(G0, pc_addr);
1058 // Always null flags after return to Java
1059 st(G0, flags);
1060 }
1061
1062
1063 void MacroAssembler::call_VM_base(
1064 Register oop_result,
1065 Register thread_cache,
1066 Register last_java_sp,
1067 address entry_point,
1068 int number_of_arguments,
1069 bool check_exceptions)
1070 {
1071 assert_not_delayed();
1072
1073 // determine last_java_sp register
1074 if (!last_java_sp->is_valid()) {
1075 last_java_sp = SP;
1076 }
1077 // debugging support
1078 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1079
1080 // 64-bit last_java_sp is biased!
1081 set_last_Java_frame(last_java_sp, noreg);
1082 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early
1083 save_thread(thread_cache);
1084 // do the call
1085 call(entry_point, relocInfo::runtime_call_type);
1086 if (!VerifyThread)
1087 delayed()->mov(G2_thread, O0); // pass thread as first argument
1088 else
1089 delayed()->nop(); // (thread already passed)
1090 restore_thread(thread_cache);
1091 reset_last_Java_frame();
1092
1093 // check for pending exceptions. use Gtemp as scratch register.
1094 if (check_exceptions) {
1095 check_and_forward_exception(Gtemp);
1096 }
1097
1098 #ifdef ASSERT
1099 set(badHeapWordVal, G3);
1100 set(badHeapWordVal, G4);
1101 set(badHeapWordVal, G5);
1102 #endif
1103
1104 // get oop result if there is one and reset the value in the thread
1105 if (oop_result->is_valid()) {
1106 get_vm_result(oop_result);
1107 }
1108 }
1109
1110 void MacroAssembler::check_and_forward_exception(Register scratch_reg)
1111 {
1112 Label L;
1113
1114 check_and_handle_popframe(scratch_reg);
1115 check_and_handle_earlyret(scratch_reg);
1116
1117 Address exception_addr(G2_thread, Thread::pending_exception_offset());
1118 ld_ptr(exception_addr, scratch_reg);
1119 br_null(scratch_reg,false,pt,L);
1120 // we use O7 linkage so that forward_exception_entry has the issuing PC
1121 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
1122 delayed()->nop();
1123 bind(L);
1124 }
1125
1126
1127 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) {
1128 }
1129
1130
1131 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) {
1132 }
1133
1134
1135 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1136 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
1137 }
1138
1139
1140 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
1141 // O0 is reserved for the thread
1142 mov(arg_1, O1);
1143 call_VM(oop_result, entry_point, 1, check_exceptions);
1144 }
1145
1146
1147 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
1148 // O0 is reserved for the thread
1149 mov(arg_1, O1);
1150 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1151 call_VM(oop_result, entry_point, 2, check_exceptions);
1152 }
1153
1154
1155 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
1156 // O0 is reserved for the thread
1157 mov(arg_1, O1);
1158 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1159 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
1160 call_VM(oop_result, entry_point, 3, check_exceptions);
1161 }
1162
1163
1164
1165 // Note: The following call_VM overloadings are useful when a "save"
1166 // has already been performed by a stub, and the last Java frame is
1167 // the previous one. In that case, last_java_sp must be passed as FP
1168 // instead of SP.
1169
1170
1171 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
1172 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1173 }
1174
1175
1176 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
1177 // O0 is reserved for the thread
1178 mov(arg_1, O1);
1179 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1180 }
1181
1182
1183 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
1184 // O0 is reserved for the thread
1185 mov(arg_1, O1);
1186 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1187 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1188 }
1189
1190
1191 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
1192 // O0 is reserved for the thread
1193 mov(arg_1, O1);
1194 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1195 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
1196 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1197 }
1198
1199
1200
1201 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) {
1202 assert_not_delayed();
1203 save_thread(thread_cache);
1204 // do the call
1205 call(entry_point, relocInfo::runtime_call_type);
1206 delayed()->nop();
1207 restore_thread(thread_cache);
1208 #ifdef ASSERT
1209 set(badHeapWordVal, G3);
1210 set(badHeapWordVal, G4);
1211 set(badHeapWordVal, G5);
1212 #endif
1213 }
1214
1215
1216 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) {
1217 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments);
1218 }
1219
1220
1221 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) {
1222 mov(arg_1, O0);
1223 call_VM_leaf(thread_cache, entry_point, 1);
1224 }
1225
1226
1227 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) {
1228 mov(arg_1, O0);
1229 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
1230 call_VM_leaf(thread_cache, entry_point, 2);
1231 }
1232
1233
1234 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) {
1235 mov(arg_1, O0);
1236 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
1237 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument");
1238 call_VM_leaf(thread_cache, entry_point, 3);
1239 }
1240
1241
1242 void MacroAssembler::get_vm_result(Register oop_result) {
1243 verify_thread();
1244 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
1245 ld_ptr( vm_result_addr, oop_result);
1246 st_ptr(G0, vm_result_addr);
1247 verify_oop(oop_result);
1248 }
1249
1250
1251 void MacroAssembler::get_vm_result_2(Register oop_result) {
1252 verify_thread();
1253 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
1254 ld_ptr(vm_result_addr_2, oop_result);
1255 st_ptr(G0, vm_result_addr_2);
1256 verify_oop(oop_result);
1257 }
1258
1259
1260 // We require that C code which does not return a value in vm_result will
1261 // leave it undisturbed.
1262 void MacroAssembler::set_vm_result(Register oop_result) {
1263 verify_thread();
1264 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
1265 verify_oop(oop_result);
1266
1267 # ifdef ASSERT
1268 // Check that we are not overwriting any other oop.
1269 #ifdef CC_INTERP
1270 save_frame(0);
1271 #else
1272 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof
1273 #endif /* CC_INTERP */
1274 ld_ptr(vm_result_addr, L0);
1275 tst(L0);
1276 restore();
1277 breakpoint_trap(notZero, Assembler::ptr_cc);
1278 // }
1279 # endif
1280
1281 st_ptr(oop_result, vm_result_addr);
1282 }
1283
1284
1285 void MacroAssembler::card_table_write(jbyte* byte_map_base,
1286 Register tmp, Register obj) {
1287 #ifdef _LP64
1288 srlx(obj, CardTableModRefBS::card_shift, obj);
1289 #else
1290 srl(obj, CardTableModRefBS::card_shift, obj);
1291 #endif
1292 assert(tmp != obj, "need separate temp reg");
1293 set((address) byte_map_base, tmp);
1294 stb(G0, tmp, obj);
1295 }
1296
1297
1298 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
1299 address save_pc;
1300 int shiftcnt;
1301 #ifdef _LP64
1302 # ifdef CHECK_DELAY
1303 assert_not_delayed((char*) "cannot put two instructions in delay slot");
1304 # endif
1305 v9_dep();
1306 save_pc = pc();
1307
1308 int msb32 = (int) (addrlit.value() >> 32);
1309 int lsb32 = (int) (addrlit.value());
1310
1311 if (msb32 == 0 && lsb32 >= 0) {
1312 Assembler::sethi(lsb32, d, addrlit.rspec());
1313 }
1314 else if (msb32 == -1) {
1315 Assembler::sethi(~lsb32, d, addrlit.rspec());
1316 xor3(d, ~low10(~0), d);
1317 }
1318 else {
1319 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits
1320 if (msb32 & 0x3ff) // Any bits?
1321 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32
1322 if (lsb32 & 0xFFFFFC00) { // done?
1323 if ((lsb32 >> 20) & 0xfff) { // Any bits set?
1324 sllx(d, 12, d); // Make room for next 12 bits
1325 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12
1326 shiftcnt = 0; // We already shifted
1327 }
1328 else
1329 shiftcnt = 12;
1330 if ((lsb32 >> 10) & 0x3ff) {
1331 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits
1332 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10
1333 shiftcnt = 0;
1334 }
1335 else
1336 shiftcnt = 10;
1337 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd
1338 }
1339 else
1340 sllx(d, 32, d);
1341 }
1342 // Pad out the instruction sequence so it can be patched later.
1343 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none &&
1344 addrlit.rtype() != relocInfo::runtime_call_type)) {
1345 while (pc() < (save_pc + (7 * BytesPerInstWord)))
1346 nop();
1347 }
1348 #else
1349 Assembler::sethi(addrlit.value(), d, addrlit.rspec());
1350 #endif
1351 }
1352
1353
1354 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) {
1355 internal_sethi(addrlit, d, false);
1356 }
1357
1358
1359 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) {
1360 internal_sethi(addrlit, d, true);
1361 }
1362
1363
1364 int MacroAssembler::insts_for_sethi(address a, bool worst_case) {
1365 #ifdef _LP64
1366 if (worst_case) return 7;
1367 intptr_t iaddr = (intptr_t) a;
1368 int msb32 = (int) (iaddr >> 32);
1369 int lsb32 = (int) (iaddr);
1370 int count;
1371 if (msb32 == 0 && lsb32 >= 0)
1372 count = 1;
1373 else if (msb32 == -1)
1374 count = 2;
1375 else {
1376 count = 2;
1377 if (msb32 & 0x3ff)
1378 count++;
1379 if (lsb32 & 0xFFFFFC00 ) {
1380 if ((lsb32 >> 20) & 0xfff) count += 2;
1381 if ((lsb32 >> 10) & 0x3ff) count += 2;
1382 }
1383 }
1384 return count;
1385 #else
1386 return 1;
1387 #endif
1388 }
1389
1390 int MacroAssembler::worst_case_insts_for_set() {
1391 return insts_for_sethi(NULL, true) + 1;
1392 }
1393
1394
1395 // Keep in sync with MacroAssembler::insts_for_internal_set
1396 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
1397 intptr_t value = addrlit.value();
1398
1399 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) {
1400 // can optimize
1401 if (-4096 <= value && value <= 4095) {
1402 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended)
1403 return;
1404 }
1405 if (inv_hi22(hi22(value)) == value) {
1406 sethi(addrlit, d);
1407 return;
1408 }
1409 }
1410 assert_not_delayed((char*) "cannot put two instructions in delay slot");
1411 internal_sethi(addrlit, d, ForceRelocatable);
1412 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
1413 add(d, addrlit.low10(), d, addrlit.rspec());
1414 }
1415 }
1416
1417 // Keep in sync with MacroAssembler::internal_set
1418 int MacroAssembler::insts_for_internal_set(intptr_t value) {
1419 // can optimize
1420 if (-4096 <= value && value <= 4095) {
1421 return 1;
1422 }
1423 if (inv_hi22(hi22(value)) == value) {
1424 return insts_for_sethi((address) value);
1425 }
1426 int count = insts_for_sethi((address) value);
1427 AddressLiteral al(value);
1428 if (al.low10() != 0) {
1429 count++;
1430 }
1431 return count;
1432 }
1433
1434 void MacroAssembler::set(const AddressLiteral& al, Register d) {
1435 internal_set(al, d, false);
1436 }
1437
1438 void MacroAssembler::set(intptr_t value, Register d) {
1439 AddressLiteral al(value);
1440 internal_set(al, d, false);
1441 }
1442
1443 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) {
1444 AddressLiteral al(addr, rspec);
1445 internal_set(al, d, false);
1446 }
1447
1448 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) {
1449 internal_set(al, d, true);
1450 }
1451
1452 void MacroAssembler::patchable_set(intptr_t value, Register d) {
1453 AddressLiteral al(value);
1454 internal_set(al, d, true);
1455 }
1456
1457
1458 void MacroAssembler::set64(jlong value, Register d, Register tmp) {
1459 assert_not_delayed();
1460 v9_dep();
1461
1462 int hi = (int)(value >> 32);
1463 int lo = (int)(value & ~0);
1464 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
1465 if (Assembler::is_simm13(lo) && value == lo) {
1466 or3(G0, lo, d);
1467 } else if (hi == 0) {
1468 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32
1469 if (low10(lo) != 0)
1470 or3(d, low10(lo), d);
1471 }
1472 else if (hi == -1) {
1473 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32
1474 xor3(d, low10(lo) ^ ~low10(~0), d);
1475 }
1476 else if (lo == 0) {
1477 if (Assembler::is_simm13(hi)) {
1478 or3(G0, hi, d);
1479 } else {
1480 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32
1481 if (low10(hi) != 0)
1482 or3(d, low10(hi), d);
1483 }
1484 sllx(d, 32, d);
1485 }
1486 else {
1487 Assembler::sethi(hi, tmp);
1488 Assembler::sethi(lo, d); // macro assembler version sign-extends
1489 if (low10(hi) != 0)
1490 or3 (tmp, low10(hi), tmp);
1491 if (low10(lo) != 0)
1492 or3 ( d, low10(lo), d);
1493 sllx(tmp, 32, tmp);
1494 or3 (d, tmp, d);
1495 }
1496 }
1497
1498 int MacroAssembler::insts_for_set64(jlong value) {
1499 v9_dep();
1500
1501 int hi = (int) (value >> 32);
1502 int lo = (int) (value & ~0);
1503 int count = 0;
1504
1505 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
1506 if (Assembler::is_simm13(lo) && value == lo) {
1507 count++;
1508 } else if (hi == 0) {
1509 count++;
1510 if (low10(lo) != 0)
1511 count++;
1512 }
1513 else if (hi == -1) {
1514 count += 2;
1515 }
1516 else if (lo == 0) {
1517 if (Assembler::is_simm13(hi)) {
1518 count++;
1519 } else {
1520 count++;
1521 if (low10(hi) != 0)
1522 count++;
1523 }
1524 count++;
1525 }
1526 else {
1527 count += 2;
1528 if (low10(hi) != 0)
1529 count++;
1530 if (low10(lo) != 0)
1531 count++;
1532 count += 2;
1533 }
1534 return count;
1535 }
1536
1537 // compute size in bytes of sparc frame, given
1538 // number of extraWords
1539 int MacroAssembler::total_frame_size_in_bytes(int extraWords) {
1540
1541 int nWords = frame::memory_parameter_word_sp_offset;
1542
1543 nWords += extraWords;
1544
1545 if (nWords & 1) ++nWords; // round up to double-word
1546
1547 return nWords * BytesPerWord;
1548 }
1549
1550
1551 // save_frame: given number of "extra" words in frame,
1552 // issue approp. save instruction (p 200, v8 manual)
1553
1554 void MacroAssembler::save_frame(int extraWords) {
1555 int delta = -total_frame_size_in_bytes(extraWords);
1556 if (is_simm13(delta)) {
1557 save(SP, delta, SP);
1558 } else {
1559 set(delta, G3_scratch);
1560 save(SP, G3_scratch, SP);
1561 }
1562 }
1563
1564
1565 void MacroAssembler::save_frame_c1(int size_in_bytes) {
1566 if (is_simm13(-size_in_bytes)) {
1567 save(SP, -size_in_bytes, SP);
1568 } else {
1569 set(-size_in_bytes, G3_scratch);
1570 save(SP, G3_scratch, SP);
1571 }
1572 }
1573
1574
1575 void MacroAssembler::save_frame_and_mov(int extraWords,
1576 Register s1, Register d1,
1577 Register s2, Register d2) {
1578 assert_not_delayed();
1579
1580 // The trick here is to use precisely the same memory word
1581 // that trap handlers also use to save the register.
1582 // This word cannot be used for any other purpose, but
1583 // it works fine to save the register's value, whether or not
1584 // an interrupt flushes register windows at any given moment!
1585 Address s1_addr;
1586 if (s1->is_valid() && (s1->is_in() || s1->is_local())) {
1587 s1_addr = s1->address_in_saved_window();
1588 st_ptr(s1, s1_addr);
1589 }
1590
1591 Address s2_addr;
1592 if (s2->is_valid() && (s2->is_in() || s2->is_local())) {
1593 s2_addr = s2->address_in_saved_window();
1594 st_ptr(s2, s2_addr);
1595 }
1596
1597 save_frame(extraWords);
1598
1599 if (s1_addr.base() == SP) {
1600 ld_ptr(s1_addr.after_save(), d1);
1601 } else if (s1->is_valid()) {
1602 mov(s1->after_save(), d1);
1603 }
1604
1605 if (s2_addr.base() == SP) {
1606 ld_ptr(s2_addr.after_save(), d2);
1607 } else if (s2->is_valid()) {
1608 mov(s2->after_save(), d2);
1609 }
1610 }
1611
1612
1613 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) {
1614 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1615 int oop_index = oop_recorder()->allocate_index(obj);
1616 return AddressLiteral(obj, oop_Relocation::spec(oop_index));
1617 }
1618
1619
1620 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
1621 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1622 int oop_index = oop_recorder()->find_index(obj);
1623 return AddressLiteral(obj, oop_Relocation::spec(oop_index));
1624 }
1625
1626 void MacroAssembler::set_narrow_oop(jobject obj, Register d) {
1627 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1628 int oop_index = oop_recorder()->find_index(obj);
1629 RelocationHolder rspec = oop_Relocation::spec(oop_index);
1630
1631 assert_not_delayed();
1632 // Relocation with special format (see relocInfo_sparc.hpp).
1633 relocate(rspec, 1);
1634 // Assembler::sethi(0x3fffff, d);
1635 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) );
1636 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
1637 add(d, 0x3ff, d);
1638
1639 }
1640
1641
1642 void MacroAssembler::align(int modulus) {
1643 while (offset() % modulus != 0) nop();
1644 }
1645
1646
1647 void MacroAssembler::safepoint() {
1648 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint));
1649 }
1650
1651
1652 void RegistersForDebugging::print(outputStream* s) {
1653 int j;
1654 for ( j = 0; j < 8; ++j )
1655 if ( j != 6 ) s->print_cr("i%d = 0x%.16lx", j, i[j]);
1656 else s->print_cr( "fp = 0x%.16lx", i[j]);
1657 s->cr();
1658
1659 for ( j = 0; j < 8; ++j )
1660 s->print_cr("l%d = 0x%.16lx", j, l[j]);
1661 s->cr();
1662
1663 for ( j = 0; j < 8; ++j )
1664 if ( j != 6 ) s->print_cr("o%d = 0x%.16lx", j, o[j]);
1665 else s->print_cr( "sp = 0x%.16lx", o[j]);
1666 s->cr();
1667
1668 for ( j = 0; j < 8; ++j )
1669 s->print_cr("g%d = 0x%.16lx", j, g[j]);
1670 s->cr();
1671
1672 // print out floats with compression
1673 for (j = 0; j < 32; ) {
1674 jfloat val = f[j];
1675 int last = j;
1676 for ( ; last+1 < 32; ++last ) {
1677 char b1[1024], b2[1024];
1678 sprintf(b1, "%f", val);
1679 sprintf(b2, "%f", f[last+1]);
1680 if (strcmp(b1, b2))
1681 break;
1682 }
1683 s->print("f%d", j);
1684 if ( j != last ) s->print(" - f%d", last);
1685 s->print(" = %f", val);
1686 s->fill_to(25);
1687 s->print_cr(" (0x%x)", val);
1688 j = last + 1;
1689 }
1690 s->cr();
1691
1692 // and doubles (evens only)
1693 for (j = 0; j < 32; ) {
1694 jdouble val = d[j];
1695 int last = j;
1696 for ( ; last+1 < 32; ++last ) {
1697 char b1[1024], b2[1024];
1698 sprintf(b1, "%f", val);
1699 sprintf(b2, "%f", d[last+1]);
1700 if (strcmp(b1, b2))
1701 break;
1702 }
1703 s->print("d%d", 2 * j);
1704 if ( j != last ) s->print(" - d%d", last);
1705 s->print(" = %f", val);
1706 s->fill_to(30);
1707 s->print("(0x%x)", *(int*)&val);
1708 s->fill_to(42);
1709 s->print_cr("(0x%x)", *(1 + (int*)&val));
1710 j = last + 1;
1711 }
1712 s->cr();
1713 }
1714
1715 void RegistersForDebugging::save_registers(MacroAssembler* a) {
1716 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0);
1717 a->flush_windows();
1718 int i;
1719 for (i = 0; i < 8; ++i) {
1720 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i));
1721 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i));
1722 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i));
1723 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i));
1724 }
1725 for (i = 0; i < 32; ++i) {
1726 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i));
1727 }
1728 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) {
1729 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i));
1730 }
1731 }
1732
1733 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) {
1734 for (int i = 1; i < 8; ++i) {
1735 a->ld_ptr(r, g_offset(i), as_gRegister(i));
1736 }
1737 for (int j = 0; j < 32; ++j) {
1738 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j));
1739 }
1740 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) {
1741 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k));
1742 }
1743 }
1744
1745
1746 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1747 void MacroAssembler::push_fTOS() {
1748 // %%%%%% need to implement this
1749 }
1750
1751 // pops double TOS element from CPU stack and pushes on FPU stack
1752 void MacroAssembler::pop_fTOS() {
1753 // %%%%%% need to implement this
1754 }
1755
1756 void MacroAssembler::empty_FPU_stack() {
1757 // %%%%%% need to implement this
1758 }
1759
1760 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) {
1761 // plausibility check for oops
1762 if (!VerifyOops) return;
1763
1764 if (reg == G0) return; // always NULL, which is always an oop
1765
1766 BLOCK_COMMENT("verify_oop {");
1767 char buffer[64];
1768 #ifdef COMPILER1
1769 if (CommentedAssembly) {
1770 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset());
1771 block_comment(buffer);
1772 }
1773 #endif
1774
1775 int len = strlen(file) + strlen(msg) + 1 + 4;
1776 sprintf(buffer, "%d", line);
1777 len += strlen(buffer);
1778 sprintf(buffer, " at offset %d ", offset());
1779 len += strlen(buffer);
1780 char * real_msg = new char[len];
1781 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line);
1782
1783 // Call indirectly to solve generation ordering problem
1784 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
1785
1786 // Make some space on stack above the current register window.
1787 // Enough to hold 8 64-bit registers.
1788 add(SP,-8*8,SP);
1789
1790 // Save some 64-bit registers; a normal 'save' chops the heads off
1791 // of 64-bit longs in the 32-bit build.
1792 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
1793 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
1794 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed
1795 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
1796
1797 set((intptr_t)real_msg, O1);
1798 // Load address to call to into O7
1799 load_ptr_contents(a, O7);
1800 // Register call to verify_oop_subroutine
1801 callr(O7, G0);
1802 delayed()->nop();
1803 // recover frame size
1804 add(SP, 8*8,SP);
1805 BLOCK_COMMENT("} verify_oop");
1806 }
1807
1808 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) {
1809 // plausibility check for oops
1810 if (!VerifyOops) return;
1811
1812 char buffer[64];
1813 sprintf(buffer, "%d", line);
1814 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer);
1815 sprintf(buffer, " at SP+%d ", addr.disp());
1816 len += strlen(buffer);
1817 char * real_msg = new char[len];
1818 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line);
1819
1820 // Call indirectly to solve generation ordering problem
1821 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
1822
1823 // Make some space on stack above the current register window.
1824 // Enough to hold 8 64-bit registers.
1825 add(SP,-8*8,SP);
1826
1827 // Save some 64-bit registers; a normal 'save' chops the heads off
1828 // of 64-bit longs in the 32-bit build.
1829 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
1830 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
1831 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed
1832 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
1833
1834 set((intptr_t)real_msg, O1);
1835 // Load address to call to into O7
1836 load_ptr_contents(a, O7);
1837 // Register call to verify_oop_subroutine
1838 callr(O7, G0);
1839 delayed()->nop();
1840 // recover frame size
1841 add(SP, 8*8,SP);
1842 }
1843
1844 // side-door communication with signalHandler in os_solaris.cpp
1845 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL };
1846
1847 // This macro is expanded just once; it creates shared code. Contract:
1848 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY
1849 // registers, including flags. May not use a register 'save', as this blows
1850 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf'
1851 // call.
1852 void MacroAssembler::verify_oop_subroutine() {
1853 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" );
1854
1855 // Leaf call; no frame.
1856 Label succeed, fail, null_or_fail;
1857
1858 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home).
1859 // O0 is now the oop to be checked. O7 is the return address.
1860 Register O0_obj = O0;
1861
1862 // Save some more registers for temps.
1863 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8);
1864 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8);
1865 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8);
1866 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8);
1867
1868 // Save flags
1869 Register O5_save_flags = O5;
1870 rdccr( O5_save_flags );
1871
1872 { // count number of verifies
1873 Register O2_adr = O2;
1874 Register O3_accum = O3;
1875 inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum);
1876 }
1877
1878 Register O2_mask = O2;
1879 Register O3_bits = O3;
1880 Register O4_temp = O4;
1881
1882 // mark lower end of faulting range
1883 assert(_verify_oop_implicit_branch[0] == NULL, "set once");
1884 _verify_oop_implicit_branch[0] = pc();
1885
1886 // We can't check the mark oop because it could be in the process of
1887 // locking or unlocking while this is running.
1888 set(Universe::verify_oop_mask (), O2_mask);
1889 set(Universe::verify_oop_bits (), O3_bits);
1890
1891 // assert((obj & oop_mask) == oop_bits);
1892 and3(O0_obj, O2_mask, O4_temp);
1893 cmp_and_brx(O4_temp, O3_bits, notEqual, false, pn, null_or_fail);
1894
1895 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) {
1896 // the null_or_fail case is useless; must test for null separately
1897 br_null(O0_obj, false, pn, succeed);
1898 }
1899
1900 // Check the klassOop of this object for being in the right area of memory.
1901 // Cannot do the load in the delay above slot in case O0 is null
1902 load_klass(O0_obj, O0_obj);
1903 // assert((klass & klass_mask) == klass_bits);
1904 if( Universe::verify_klass_mask() != Universe::verify_oop_mask() )
1905 set(Universe::verify_klass_mask(), O2_mask);
1906 if( Universe::verify_klass_bits() != Universe::verify_oop_bits() )
1907 set(Universe::verify_klass_bits(), O3_bits);
1908 and3(O0_obj, O2_mask, O4_temp);
1909 cmp_and_brx(O4_temp, O3_bits, notEqual, false, pn, fail);
1910 // Check the klass's klass
1911 load_klass(O0_obj, O0_obj);
1912 and3(O0_obj, O2_mask, O4_temp);
1913 cmp(O4_temp, O3_bits);
1914 brx(notEqual, false, pn, fail);
1915 delayed()->wrccr( O5_save_flags ); // Restore CCR's
1916
1917 // mark upper end of faulting range
1918 _verify_oop_implicit_branch[1] = pc();
1919
1920 //-----------------------
1921 // all tests pass
1922 bind(succeed);
1923
1924 // Restore prior 64-bit registers
1925 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0);
1926 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1);
1927 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2);
1928 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3);
1929 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4);
1930 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5);
1931
1932 retl(); // Leaf return; restore prior O7 in delay slot
1933 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7);
1934
1935 //-----------------------
1936 bind(null_or_fail); // nulls are less common but OK
1937 br_null(O0_obj, false, pt, succeed, false);
1938 delayed()->wrccr( O5_save_flags ); // Restore CCR's
1939
1940 //-----------------------
1941 // report failure:
1942 bind(fail);
1943 _verify_oop_implicit_branch[2] = pc();
1944
1945 wrccr( O5_save_flags ); // Restore CCR's
1946
1947 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1948
1949 // stop_subroutine expects message pointer in I1.
1950 mov(I1, O1);
1951
1952 // Restore prior 64-bit registers
1953 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0);
1954 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1);
1955 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2);
1956 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3);
1957 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4);
1958 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5);
1959
1960 // factor long stop-sequence into subroutine to save space
1961 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
1962
1963 // call indirectly to solve generation ordering problem
1964 AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address());
1965 load_ptr_contents(al, O5);
1966 jmpl(O5, 0, O7);
1967 delayed()->nop();
1968 }
1969
1970
1971 void MacroAssembler::stop(const char* msg) {
1972 // save frame first to get O7 for return address
1973 // add one word to size in case struct is odd number of words long
1974 // It must be doubleword-aligned for storing doubles into it.
1975
1976 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1977
1978 // stop_subroutine expects message pointer in I1.
1979 set((intptr_t)msg, O1);
1980
1981 // factor long stop-sequence into subroutine to save space
1982 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
1983
1984 // call indirectly to solve generation ordering problem
1985 AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address());
1986 load_ptr_contents(a, O5);
1987 jmpl(O5, 0, O7);
1988 delayed()->nop();
1989
1990 breakpoint_trap(); // make stop actually stop rather than writing
1991 // unnoticeable results in the output files.
1992
1993 // restore(); done in callee to save space!
1994 }
1995
1996
1997 void MacroAssembler::warn(const char* msg) {
1998 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1999 RegistersForDebugging::save_registers(this);
2000 mov(O0, L0);
2001 set((intptr_t)msg, O0);
2002 call( CAST_FROM_FN_PTR(address, warning) );
2003 delayed()->nop();
2004 // ret();
2005 // delayed()->restore();
2006 RegistersForDebugging::restore_registers(this, L0);
2007 restore();
2008 }
2009
2010
2011 void MacroAssembler::untested(const char* what) {
2012 // We must be able to turn interactive prompting off
2013 // in order to run automated test scripts on the VM
2014 // Use the flag ShowMessageBoxOnError
2015
2016 char* b = new char[1024];
2017 sprintf(b, "untested: %s", what);
2018
2019 if ( ShowMessageBoxOnError ) stop(b);
2020 else warn(b);
2021 }
2022
2023
2024 void MacroAssembler::stop_subroutine() {
2025 RegistersForDebugging::save_registers(this);
2026
2027 // for the sake of the debugger, stick a PC on the current frame
2028 // (this assumes that the caller has performed an extra "save")
2029 mov(I7, L7);
2030 add(O7, -7 * BytesPerInt, I7);
2031
2032 save_frame(); // one more save to free up another O7 register
2033 mov(I0, O1); // addr of reg save area
2034
2035 // We expect pointer to message in I1. Caller must set it up in O1
2036 mov(I1, O0); // get msg
2037 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
2038 delayed()->nop();
2039
2040 restore();
2041
2042 RegistersForDebugging::restore_registers(this, O0);
2043
2044 save_frame(0);
2045 call(CAST_FROM_FN_PTR(address,breakpoint));
2046 delayed()->nop();
2047 restore();
2048
2049 mov(L7, I7);
2050 retl();
2051 delayed()->restore(); // see stop above
2052 }
2053
2054
2055 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) {
2056 if ( ShowMessageBoxOnError ) {
2057 JavaThreadState saved_state = JavaThread::current()->thread_state();
2058 JavaThread::current()->set_thread_state(_thread_in_vm);
2059 {
2060 // In order to get locks work, we need to fake a in_VM state
2061 ttyLocker ttyl;
2062 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);
2063 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
2064 ::tty->print_cr("Interpreter::bytecode_counter = %d", BytecodeCounter::counter_value());
2065 }
2066 if (os::message_box(msg, "Execution stopped, print registers?"))
2067 regs->print(::tty);
2068 }
2069 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);
2070 }
2071 else
2072 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
2073 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
2074 }
2075
2076
2077 #ifndef PRODUCT
2078 void MacroAssembler::test() {
2079 ResourceMark rm;
2080
2081 CodeBuffer cb("test", 10000, 10000);
2082 MacroAssembler* a = new MacroAssembler(&cb);
2083 VM_Version::allow_all();
2084 a->test_v9();
2085 a->test_v8_onlys();
2086 VM_Version::revert();
2087
2088 StubRoutines::Sparc::test_stop_entry()();
2089 }
2090 #endif
2091
2092
2093 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) {
2094 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words?
2095 Label no_extras;
2096 br( negative, true, pt, no_extras ); // if neg, clear reg
2097 delayed()->set(0, Rresult); // annuled, so only if taken
2098 bind( no_extras );
2099 }
2100
2101
2102 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) {
2103 #ifdef _LP64
2104 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult);
2105 #else
2106 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult);
2107 #endif
2108 bclr(1, Rresult);
2109 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes
2110 }
2111
2112
2113 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) {
2114 calc_frame_size(Rextra_words, Rresult);
2115 neg(Rresult);
2116 save(SP, Rresult, SP);
2117 }
2118
2119
2120 // ---------------------------------------------------------
2121 Assembler::RCondition cond2rcond(Assembler::Condition c) {
2122 switch (c) {
2123 /*case zero: */
2124 case Assembler::equal: return Assembler::rc_z;
2125 case Assembler::lessEqual: return Assembler::rc_lez;
2126 case Assembler::less: return Assembler::rc_lz;
2127 /*case notZero:*/
2128 case Assembler::notEqual: return Assembler::rc_nz;
2129 case Assembler::greater: return Assembler::rc_gz;
2130 case Assembler::greaterEqual: return Assembler::rc_gez;
2131 }
2132 ShouldNotReachHere();
2133 return Assembler::rc_z;
2134 }
2135
2136 // compares (32 bit) register with zero and branches. NOT FOR USE WITH 64-bit POINTERS
2137 void MacroAssembler::br_zero(Register s1, Label& L) {
2138 assert_not_delayed();
2139 if (use_cbc(L)) {
2140 Assembler::cbc(zero, icc, s1, 0, L);
2141 } else {
2142 tst(s1);
2143 br (zero, false, pt, L);
2144 delayed()->nop();
2145 }
2146 }
2147
2148 // Compares a pointer register with zero and branches on null.
2149 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
2150 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L, bool emit_delayed_nop ) {
2151 assert_not_delayed();
2152 if (emit_delayed_nop && use_cbc(L)) {
2153 Assembler::cbc(zero, ptr_cc, s1, 0, L);
2154 return;
2155 }
2156 #ifdef _LP64
2157 bpr( rc_z, a, p, s1, L );
2158 #else
2159 tst(s1);
2160 br ( zero, a, p, L );
2161 #endif
2162 // Some callers can fill the delay slot.
2163 if (emit_delayed_nop) {
2164 delayed()->nop();
2165 }
2166 }
2167
2168 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L, bool emit_delayed_nop ) {
2169 assert_not_delayed();
2170 if (emit_delayed_nop && use_cbc(L)) {
2171 Assembler::cbc(notZero, ptr_cc, s1, 0, L);
2172 return;
2173 }
2174 #ifdef _LP64
2175 bpr( rc_nz, a, p, s1, L );
2176 #else
2177 tst(s1);
2178 br ( notZero, a, p, L );
2179 #endif
2180 // Some callers can fill the delay slot.
2181 if (emit_delayed_nop) {
2182 delayed()->nop();
2183 }
2184 }
2185
2186 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,
2187 Register s1, address d,
2188 relocInfo::relocType rt ) {
2189 assert_not_delayed();
2190 if (VM_Version::v9_instructions_work()) {
2191 bpr(rc, a, p, s1, d, rt);
2192 } else {
2193 tst(s1);
2194 br(reg_cond_to_cc_cond(rc), a, p, d, rt);
2195 }
2196 }
2197
2198 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,
2199 Register s1, Label& L, bool emit_delayed_nop ) {
2200 assert_not_delayed();
2201 if (emit_delayed_nop && use_cbc(L)) {
2202 // Use xcc to have the same result as bpr (it tests all 64 bits).
2203 Assembler::cbc(reg_cond_to_cc_cond(rc), xcc, s1, 0, L);
2204 return;
2205 }
2206 if (VM_Version::v9_instructions_work()) {
2207 bpr(rc, a, p, s1, L);
2208 } else {
2209 tst(s1);
2210 br(reg_cond_to_cc_cond(rc), a, p, L);
2211 }
2212 // Some callers can fill the delay slot.
2213 if (emit_delayed_nop) {
2214 delayed()->nop();
2215 }
2216 }
2217
2218 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
2219 void MacroAssembler::cmp_and_br(Register s1, Register s2, Condition c,
2220 bool a, Predict p, Label& L) {
2221 assert_not_delayed();
2222 if (use_cbc(L)) {
2223 Assembler::cbc(c, icc, s1, s2, L);
2224 } else {
2225 cmp(s1, s2);
2226 br(c, a, p, L);
2227 delayed()->nop();
2228 }
2229 }
2230
2231 void MacroAssembler::cmp_and_br(Register s1, int simm13a, Condition c,
2232 bool a, Predict p, Label& L) {
2233 assert_not_delayed();
2234 if (is_simm(simm13a,5) && use_cbc(L)) {
2235 Assembler::cbc(c, icc, s1, simm13a, L);
2236 } else {
2237 cmp(s1, simm13a);
2238 br(c, a, p, L);
2239 delayed()->nop();
2240 }
2241 }
2242
2243 // Branch that tests xcc in LP64 and icc in !LP64
2244 void MacroAssembler::cmp_and_brx(Register s1, Register s2, Condition c,
2245 bool a, Predict p, Label& L) {
2246 assert_not_delayed();
2247 if (use_cbc(L)) {
2248 Assembler::cbc(c, ptr_cc, s1, s2, L);
2249 } else {
2250 cmp(s1, s2);
2251 brx(c, a, p, L);
2252 delayed()->nop();
2253 }
2254 }
2255
2256 void MacroAssembler::cmp_and_brx(Register s1, int simm13a, Condition c,
2257 bool a, Predict p, Label& L) {
2258 assert_not_delayed();
2259 if (is_simm(simm13a,5) && use_cbc(L)) {
2260 Assembler::cbc(c, ptr_cc, s1, simm13a, L);
2261 } else {
2262 cmp(s1, simm13a);
2263 brx(c, a, p, L);
2264 delayed()->nop();
2265 }
2266 }
2267
2268 // instruction sequences factored across compiler & interpreter
2269
2270
2271 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low,
2272 Register Rb_hi, Register Rb_low,
2273 Register Rresult) {
2274
2275 Label check_low_parts, done;
2276
2277 cmp(Ra_hi, Rb_hi ); // compare hi parts
2278 br(equal, true, pt, check_low_parts);
2279 delayed()->cmp(Ra_low, Rb_low); // test low parts
2280
2281 // And, with an unsigned comparison, it does not matter if the numbers
2282 // are negative or not.
2283 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff.
2284 // The second one is bigger (unsignedly).
2285
2286 // Other notes: The first move in each triplet can be unconditional
2287 // (and therefore probably prefetchable).
2288 // And the equals case for the high part does not need testing,
2289 // since that triplet is reached only after finding the high halves differ.
2290
2291 if (VM_Version::v9_instructions_work()) {
2292 mov(-1, Rresult);
2293 ba(done, false); delayed()-> movcc(greater, false, icc, 1, Rresult);
2294 } else {
2295 br(less, true, pt, done); delayed()-> set(-1, Rresult);
2296 br(greater, true, pt, done); delayed()-> set( 1, Rresult);
2297 }
2298
2299 bind( check_low_parts );
2300
2301 if (VM_Version::v9_instructions_work()) {
2302 mov( -1, Rresult);
2303 movcc(equal, false, icc, 0, Rresult);
2304 movcc(greaterUnsigned, false, icc, 1, Rresult);
2305 } else {
2306 set(-1, Rresult);
2307 br(equal, true, pt, done); delayed()->set( 0, Rresult);
2308 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult);
2309 }
2310 bind( done );
2311 }
2312
2313 void MacroAssembler::lneg( Register Rhi, Register Rlow ) {
2314 subcc( G0, Rlow, Rlow );
2315 subc( G0, Rhi, Rhi );
2316 }
2317
2318 void MacroAssembler::lshl( Register Rin_high, Register Rin_low,
2319 Register Rcount,
2320 Register Rout_high, Register Rout_low,
2321 Register Rtemp ) {
2322
2323
2324 Register Ralt_count = Rtemp;
2325 Register Rxfer_bits = Rtemp;
2326
2327 assert( Ralt_count != Rin_high
2328 && Ralt_count != Rin_low
2329 && Ralt_count != Rcount
2330 && Rxfer_bits != Rin_low
2331 && Rxfer_bits != Rin_high
2332 && Rxfer_bits != Rcount
2333 && Rxfer_bits != Rout_low
2334 && Rout_low != Rin_high,
2335 "register alias checks");
2336
2337 Label big_shift, done;
2338
2339 // This code can be optimized to use the 64 bit shifts in V9.
2340 // Here we use the 32 bit shifts.
2341
2342 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
2343 subcc(Rcount, 31, Ralt_count);
2344 br(greater, true, pn, big_shift);
2345 delayed()->dec(Ralt_count);
2346
2347 // shift < 32 bits, Ralt_count = Rcount-31
2348
2349 // We get the transfer bits by shifting right by 32-count the low
2350 // register. This is done by shifting right by 31-count and then by one
2351 // more to take care of the special (rare) case where count is zero
2352 // (shifting by 32 would not work).
2353
2354 neg(Ralt_count);
2355
2356 // The order of the next two instructions is critical in the case where
2357 // Rin and Rout are the same and should not be reversed.
2358
2359 srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count
2360 if (Rcount != Rout_low) {
2361 sll(Rin_low, Rcount, Rout_low); // low half
2362 }
2363 sll(Rin_high, Rcount, Rout_high);
2364 if (Rcount == Rout_low) {
2365 sll(Rin_low, Rcount, Rout_low); // low half
2366 }
2367 srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more
2368 ba(done, false);
2369 delayed()->or3(Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low
2370
2371 // shift >= 32 bits, Ralt_count = Rcount-32
2372 bind(big_shift);
2373 sll(Rin_low, Ralt_count, Rout_high );
2374 clr(Rout_low);
2375
2376 bind(done);
2377 }
2378
2379
2380 void MacroAssembler::lshr( Register Rin_high, Register Rin_low,
2381 Register Rcount,
2382 Register Rout_high, Register Rout_low,
2383 Register Rtemp ) {
2384
2385 Register Ralt_count = Rtemp;
2386 Register Rxfer_bits = Rtemp;
2387
2388 assert( Ralt_count != Rin_high
2389 && Ralt_count != Rin_low
2390 && Ralt_count != Rcount
2391 && Rxfer_bits != Rin_low
2392 && Rxfer_bits != Rin_high
2393 && Rxfer_bits != Rcount
2394 && Rxfer_bits != Rout_high
2395 && Rout_high != Rin_low,
2396 "register alias checks");
2397
2398 Label big_shift, done;
2399
2400 // This code can be optimized to use the 64 bit shifts in V9.
2401 // Here we use the 32 bit shifts.
2402
2403 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
2404 subcc(Rcount, 31, Ralt_count);
2405 br(greater, true, pn, big_shift);
2406 delayed()->dec(Ralt_count);
2407
2408 // shift < 32 bits, Ralt_count = Rcount-31
2409
2410 // We get the transfer bits by shifting left by 32-count the high
2411 // register. This is done by shifting left by 31-count and then by one
2412 // more to take care of the special (rare) case where count is zero
2413 // (shifting by 32 would not work).
2414
2415 neg(Ralt_count);
2416 if (Rcount != Rout_low) {
2417 srl(Rin_low, Rcount, Rout_low);
2418 }
2419
2420 // The order of the next two instructions is critical in the case where
2421 // Rin and Rout are the same and should not be reversed.
2422
2423 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
2424 sra(Rin_high, Rcount, Rout_high ); // high half
2425 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more
2426 if (Rcount == Rout_low) {
2427 srl(Rin_low, Rcount, Rout_low);
2428 }
2429 ba(done, false);
2430 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
2431
2432 // shift >= 32 bits, Ralt_count = Rcount-32
2433 bind(big_shift);
2434
2435 sra(Rin_high, Ralt_count, Rout_low);
2436 sra(Rin_high, 31, Rout_high); // sign into hi
2437
2438 bind( done );
2439 }
2440
2441
2442
2443 void MacroAssembler::lushr( Register Rin_high, Register Rin_low,
2444 Register Rcount,
2445 Register Rout_high, Register Rout_low,
2446 Register Rtemp ) {
2447
2448 Register Ralt_count = Rtemp;
2449 Register Rxfer_bits = Rtemp;
2450
2451 assert( Ralt_count != Rin_high
2452 && Ralt_count != Rin_low
2453 && Ralt_count != Rcount
2454 && Rxfer_bits != Rin_low
2455 && Rxfer_bits != Rin_high
2456 && Rxfer_bits != Rcount
2457 && Rxfer_bits != Rout_high
2458 && Rout_high != Rin_low,
2459 "register alias checks");
2460
2461 Label big_shift, done;
2462
2463 // This code can be optimized to use the 64 bit shifts in V9.
2464 // Here we use the 32 bit shifts.
2465
2466 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
2467 subcc(Rcount, 31, Ralt_count);
2468 br(greater, true, pn, big_shift);
2469 delayed()->dec(Ralt_count);
2470
2471 // shift < 32 bits, Ralt_count = Rcount-31
2472
2473 // We get the transfer bits by shifting left by 32-count the high
2474 // register. This is done by shifting left by 31-count and then by one
2475 // more to take care of the special (rare) case where count is zero
2476 // (shifting by 32 would not work).
2477
2478 neg(Ralt_count);
2479 if (Rcount != Rout_low) {
2480 srl(Rin_low, Rcount, Rout_low);
2481 }
2482
2483 // The order of the next two instructions is critical in the case where
2484 // Rin and Rout are the same and should not be reversed.
2485
2486 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
2487 srl(Rin_high, Rcount, Rout_high ); // high half
2488 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more
2489 if (Rcount == Rout_low) {
2490 srl(Rin_low, Rcount, Rout_low);
2491 }
2492 ba(done, false);
2493 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
2494
2495 // shift >= 32 bits, Ralt_count = Rcount-32
2496 bind(big_shift);
2497
2498 srl(Rin_high, Ralt_count, Rout_low);
2499 clr(Rout_high);
2500
2501 bind( done );
2502 }
2503
2504 #ifdef _LP64
2505 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) {
2506 cmp(Ra, Rb);
2507 mov(-1, Rresult);
2508 movcc(equal, false, xcc, 0, Rresult);
2509 movcc(greater, false, xcc, 1, Rresult);
2510 }
2511 #endif
2512
2513
2514 void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) {
2515 switch (size_in_bytes) {
2516 case 8: ld_long(src, dst); break;
2517 case 4: ld( src, dst); break;
2518 case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break;
2519 case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break;
2520 default: ShouldNotReachHere();
2521 }
2522 }
2523
2524 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) {
2525 switch (size_in_bytes) {
2526 case 8: st_long(src, dst); break;
2527 case 4: st( src, dst); break;
2528 case 2: sth( src, dst); break;
2529 case 1: stb( src, dst); break;
2530 default: ShouldNotReachHere();
2531 }
2532 }
2533
2534
2535 void MacroAssembler::float_cmp( bool is_float, int unordered_result,
2536 FloatRegister Fa, FloatRegister Fb,
2537 Register Rresult) {
2538
2539 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb);
2540
2541 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less;
2542 Condition eq = f_equal;
2543 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater;
2544
2545 if (VM_Version::v9_instructions_work()) {
2546
2547 mov(-1, Rresult);
2548 movcc(eq, true, fcc0, 0, Rresult);
2549 movcc(gt, true, fcc0, 1, Rresult);
2550
2551 } else {
2552 Label done;
2553
2554 set( -1, Rresult );
2555 //fb(lt, true, pn, done); delayed()->set( -1, Rresult );
2556 fb( eq, true, pn, done); delayed()->set( 0, Rresult );
2557 fb( gt, true, pn, done); delayed()->set( 1, Rresult );
2558
2559 bind (done);
2560 }
2561 }
2562
2563
2564 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2565 {
2566 if (VM_Version::v9_instructions_work()) {
2567 Assembler::fneg(w, s, d);
2568 } else {
2569 if (w == FloatRegisterImpl::S) {
2570 Assembler::fneg(w, s, d);
2571 } else if (w == FloatRegisterImpl::D) {
2572 // number() does a sanity check on the alignment.
2573 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2574 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2575
2576 Assembler::fneg(FloatRegisterImpl::S, s, d);
2577 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2578 } else {
2579 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2580
2581 // number() does a sanity check on the alignment.
2582 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2583 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2584
2585 Assembler::fneg(FloatRegisterImpl::S, s, d);
2586 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2587 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2588 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2589 }
2590 }
2591 }
2592
2593 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2594 {
2595 if (VM_Version::v9_instructions_work()) {
2596 Assembler::fmov(w, s, d);
2597 } else {
2598 if (w == FloatRegisterImpl::S) {
2599 Assembler::fmov(w, s, d);
2600 } else if (w == FloatRegisterImpl::D) {
2601 // number() does a sanity check on the alignment.
2602 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2603 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2604
2605 Assembler::fmov(FloatRegisterImpl::S, s, d);
2606 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2607 } else {
2608 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2609
2610 // number() does a sanity check on the alignment.
2611 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2612 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2613
2614 Assembler::fmov(FloatRegisterImpl::S, s, d);
2615 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2616 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2617 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2618 }
2619 }
2620 }
2621
2622 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2623 {
2624 if (VM_Version::v9_instructions_work()) {
2625 Assembler::fabs(w, s, d);
2626 } else {
2627 if (w == FloatRegisterImpl::S) {
2628 Assembler::fabs(w, s, d);
2629 } else if (w == FloatRegisterImpl::D) {
2630 // number() does a sanity check on the alignment.
2631 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2632 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2633
2634 Assembler::fabs(FloatRegisterImpl::S, s, d);
2635 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2636 } else {
2637 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2638
2639 // number() does a sanity check on the alignment.
2640 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2641 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2642
2643 Assembler::fabs(FloatRegisterImpl::S, s, d);
2644 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2645 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2646 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2647 }
2648 }
2649 }
2650
2651 void MacroAssembler::save_all_globals_into_locals() {
2652 mov(G1,L1);
2653 mov(G2,L2);
2654 mov(G3,L3);
2655 mov(G4,L4);
2656 mov(G5,L5);
2657 mov(G6,L6);
2658 mov(G7,L7);
2659 }
2660
2661 void MacroAssembler::restore_globals_from_locals() {
2662 mov(L1,G1);
2663 mov(L2,G2);
2664 mov(L3,G3);
2665 mov(L4,G4);
2666 mov(L5,G5);
2667 mov(L6,G6);
2668 mov(L7,G7);
2669 }
2670
2671 // Use for 64 bit operation.
2672 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
2673 {
2674 // store ptr_reg as the new top value
2675 #ifdef _LP64
2676 casx(top_ptr_reg, top_reg, ptr_reg);
2677 #else
2678 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm);
2679 #endif // _LP64
2680 }
2681
2682 // [RGV] This routine does not handle 64 bit operations.
2683 // use casx_under_lock() or casx directly!!!
2684 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
2685 {
2686 // store ptr_reg as the new top value
2687 if (VM_Version::v9_instructions_work()) {
2688 cas(top_ptr_reg, top_reg, ptr_reg);
2689 } else {
2690
2691 // If the register is not an out nor global, it is not visible
2692 // after the save. Allocate a register for it, save its
2693 // value in the register save area (the save may not flush
2694 // registers to the save area).
2695
2696 Register top_ptr_reg_after_save;
2697 Register top_reg_after_save;
2698 Register ptr_reg_after_save;
2699
2700 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) {
2701 top_ptr_reg_after_save = top_ptr_reg->after_save();
2702 } else {
2703 Address reg_save_addr = top_ptr_reg->address_in_saved_window();
2704 top_ptr_reg_after_save = L0;
2705 st(top_ptr_reg, reg_save_addr);
2706 }
2707
2708 if (top_reg->is_out() || top_reg->is_global()) {
2709 top_reg_after_save = top_reg->after_save();
2710 } else {
2711 Address reg_save_addr = top_reg->address_in_saved_window();
2712 top_reg_after_save = L1;
2713 st(top_reg, reg_save_addr);
2714 }
2715
2716 if (ptr_reg->is_out() || ptr_reg->is_global()) {
2717 ptr_reg_after_save = ptr_reg->after_save();
2718 } else {
2719 Address reg_save_addr = ptr_reg->address_in_saved_window();
2720 ptr_reg_after_save = L2;
2721 st(ptr_reg, reg_save_addr);
2722 }
2723
2724 const Register& lock_reg = L3;
2725 const Register& lock_ptr_reg = L4;
2726 const Register& value_reg = L5;
2727 const Register& yield_reg = L6;
2728 const Register& yieldall_reg = L7;
2729
2730 save_frame();
2731
2732 if (top_ptr_reg_after_save == L0) {
2733 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save);
2734 }
2735
2736 if (top_reg_after_save == L1) {
2737 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save);
2738 }
2739
2740 if (ptr_reg_after_save == L2) {
2741 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save);
2742 }
2743
2744 Label(retry_get_lock);
2745 Label(not_same);
2746 Label(dont_yield);
2747
2748 assert(lock_addr, "lock_address should be non null for v8");
2749 set((intptr_t)lock_addr, lock_ptr_reg);
2750 // Initialize yield counter
2751 mov(G0,yield_reg);
2752 mov(G0, yieldall_reg);
2753 set(StubRoutines::Sparc::locked, lock_reg);
2754
2755 bind(retry_get_lock);
2756 cmp_and_br(yield_reg, V8AtomicOperationUnderLockSpinCount, Assembler::less, false, Assembler::pt, dont_yield);
2757
2758 if(use_call_vm) {
2759 Untested("Need to verify global reg consistancy");
2760 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg);
2761 } else {
2762 // Save the regs and make space for a C call
2763 save(SP, -96, SP);
2764 save_all_globals_into_locals();
2765 call(CAST_FROM_FN_PTR(address,os::yield_all));
2766 delayed()->mov(yieldall_reg, O0);
2767 restore_globals_from_locals();
2768 restore();
2769 }
2770
2771 // reset the counter
2772 mov(G0,yield_reg);
2773 add(yieldall_reg, 1, yieldall_reg);
2774
2775 bind(dont_yield);
2776 // try to get lock
2777 swap(lock_ptr_reg, 0, lock_reg);
2778
2779 // did we get the lock?
2780 cmp(lock_reg, StubRoutines::Sparc::unlocked);
2781 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock);
2782 delayed()->add(yield_reg,1,yield_reg);
2783
2784 // yes, got lock. do we have the same top?
2785 ld(top_ptr_reg_after_save, 0, value_reg);
2786 cmp_and_br(value_reg, top_reg_after_save, Assembler::notEqual, false, Assembler::pt, not_same);
2787
2788 // yes, same top.
2789 st(ptr_reg_after_save, top_ptr_reg_after_save, 0);
2790 membar(Assembler::StoreStore);
2791
2792 bind(not_same);
2793 mov(value_reg, ptr_reg_after_save);
2794 st(lock_reg, lock_ptr_reg, 0); // unlock
2795
2796 restore();
2797 }
2798 }
2799
2800 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
2801 Register tmp,
2802 int offset) {
2803 intptr_t value = *delayed_value_addr;
2804 if (value != 0)
2805 return RegisterOrConstant(value + offset);
2806
2807 // load indirectly to solve generation ordering problem
2808 AddressLiteral a(delayed_value_addr);
2809 load_ptr_contents(a, tmp);
2810
2811 #ifdef ASSERT
2812 tst(tmp);
2813 breakpoint_trap(zero, xcc);
2814 #endif
2815
2816 if (offset != 0)
2817 add(tmp, offset, tmp);
2818
2819 return RegisterOrConstant(tmp);
2820 }
2821
2822
2823 RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2824 assert(d.register_or_noreg() != G0, "lost side effect");
2825 if ((s2.is_constant() && s2.as_constant() == 0) ||
2826 (s2.is_register() && s2.as_register() == G0)) {
2827 // Do nothing, just move value.
2828 if (s1.is_register()) {
2829 if (d.is_constant()) d = temp;
2830 mov(s1.as_register(), d.as_register());
2831 return d;
2832 } else {
2833 return s1;
2834 }
2835 }
2836
2837 if (s1.is_register()) {
2838 assert_different_registers(s1.as_register(), temp);
2839 if (d.is_constant()) d = temp;
2840 andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2841 return d;
2842 } else {
2843 if (s2.is_register()) {
2844 assert_different_registers(s2.as_register(), temp);
2845 if (d.is_constant()) d = temp;
2846 set(s1.as_constant(), temp);
2847 andn(temp, s2.as_register(), d.as_register());
2848 return d;
2849 } else {
2850 intptr_t res = s1.as_constant() & ~s2.as_constant();
2851 return res;
2852 }
2853 }
2854 }
2855
2856 RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2857 assert(d.register_or_noreg() != G0, "lost side effect");
2858 if ((s2.is_constant() && s2.as_constant() == 0) ||
2859 (s2.is_register() && s2.as_register() == G0)) {
2860 // Do nothing, just move value.
2861 if (s1.is_register()) {
2862 if (d.is_constant()) d = temp;
2863 mov(s1.as_register(), d.as_register());
2864 return d;
2865 } else {
2866 return s1;
2867 }
2868 }
2869
2870 if (s1.is_register()) {
2871 assert_different_registers(s1.as_register(), temp);
2872 if (d.is_constant()) d = temp;
2873 add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2874 return d;
2875 } else {
2876 if (s2.is_register()) {
2877 assert_different_registers(s2.as_register(), temp);
2878 if (d.is_constant()) d = temp;
2879 add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register());
2880 return d;
2881 } else {
2882 intptr_t res = s1.as_constant() + s2.as_constant();
2883 return res;
2884 }
2885 }
2886 }
2887
2888 RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2889 assert(d.register_or_noreg() != G0, "lost side effect");
2890 if (!is_simm13(s2.constant_or_zero()))
2891 s2 = (s2.as_constant() & 0xFF);
2892 if ((s2.is_constant() && s2.as_constant() == 0) ||
2893 (s2.is_register() && s2.as_register() == G0)) {
2894 // Do nothing, just move value.
2895 if (s1.is_register()) {
2896 if (d.is_constant()) d = temp;
2897 mov(s1.as_register(), d.as_register());
2898 return d;
2899 } else {
2900 return s1;
2901 }
2902 }
2903
2904 if (s1.is_register()) {
2905 assert_different_registers(s1.as_register(), temp);
2906 if (d.is_constant()) d = temp;
2907 sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2908 return d;
2909 } else {
2910 if (s2.is_register()) {
2911 assert_different_registers(s2.as_register(), temp);
2912 if (d.is_constant()) d = temp;
2913 set(s1.as_constant(), temp);
2914 sll_ptr(temp, s2.as_register(), d.as_register());
2915 return d;
2916 } else {
2917 intptr_t res = s1.as_constant() << s2.as_constant();
2918 return res;
2919 }
2920 }
2921 }
2922
2923
2924 // Look up the method for a megamorphic invokeinterface call.
2925 // The target method is determined by <intf_klass, itable_index>.
2926 // The receiver klass is in recv_klass.
2927 // On success, the result will be in method_result, and execution falls through.
2928 // On failure, execution transfers to the given label.
2929 void MacroAssembler::lookup_interface_method(Register recv_klass,
2930 Register intf_klass,
2931 RegisterOrConstant itable_index,
2932 Register method_result,
2933 Register scan_temp,
2934 Register sethi_temp,
2935 Label& L_no_such_interface) {
2936 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
2937 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
2938 "caller must use same register for non-constant itable index as for method");
2939
2940 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
2941 int vtable_base = instanceKlass::vtable_start_offset() * wordSize;
2942 int scan_step = itableOffsetEntry::size() * wordSize;
2943 int vte_size = vtableEntry::size() * wordSize;
2944
2945 lduw(recv_klass, instanceKlass::vtable_length_offset() * wordSize, scan_temp);
2946 // %%% We should store the aligned, prescaled offset in the klassoop.
2947 // Then the next several instructions would fold away.
2948
2949 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0);
2950 int itb_offset = vtable_base;
2951 if (round_to_unit != 0) {
2952 // hoist first instruction of round_to(scan_temp, BytesPerLong):
2953 itb_offset += round_to_unit - wordSize;
2954 }
2955 int itb_scale = exact_log2(vtableEntry::size() * wordSize);
2956 sll(scan_temp, itb_scale, scan_temp);
2957 add(scan_temp, itb_offset, scan_temp);
2958 if (round_to_unit != 0) {
2959 // Round up to align_object_offset boundary
2960 // see code for instanceKlass::start_of_itable!
2961 // Was: round_to(scan_temp, BytesPerLong);
2962 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp);
2963 and3(scan_temp, -round_to_unit, scan_temp);
2964 }
2965 add(recv_klass, scan_temp, scan_temp);
2966
2967 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
2968 RegisterOrConstant itable_offset = itable_index;
2969 itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset);
2970 itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset);
2971 add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass);
2972
2973 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
2974 // if (scan->interface() == intf) {
2975 // result = (klass + scan->offset() + itable_index);
2976 // }
2977 // }
2978 Label search, found_method;
2979
2980 for (int peel = 1; peel >= 0; peel--) {
2981 // %%%% Could load both offset and interface in one ldx, if they were
2982 // in the opposite order. This would save a load.
2983 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result);
2984
2985 // Check that this entry is non-null. A null entry means that
2986 // the receiver class doesn't implement the interface, and wasn't the
2987 // same as when the caller was compiled.
2988 bpr(Assembler::rc_z, false, Assembler::pn, method_result, L_no_such_interface);
2989 delayed()->cmp(method_result, intf_klass);
2990
2991 if (peel) {
2992 brx(Assembler::equal, false, Assembler::pt, found_method);
2993 } else {
2994 brx(Assembler::notEqual, false, Assembler::pn, search);
2995 // (invert the test to fall through to found_method...)
2996 }
2997 delayed()->add(scan_temp, scan_step, scan_temp);
2998
2999 if (!peel) break;
3000
3001 bind(search);
3002 }
3003
3004 bind(found_method);
3005
3006 // Got a hit.
3007 int ito_offset = itableOffsetEntry::offset_offset_in_bytes();
3008 // scan_temp[-scan_step] points to the vtable offset we need
3009 ito_offset -= scan_step;
3010 lduw(scan_temp, ito_offset, scan_temp);
3011 ld_ptr(recv_klass, scan_temp, method_result);
3012 }
3013
3014
3015 void MacroAssembler::check_klass_subtype(Register sub_klass,
3016 Register super_klass,
3017 Register temp_reg,
3018 Register temp2_reg,
3019 Label& L_success) {
3020 Label L_failure, L_pop_to_failure;
3021 check_klass_subtype_fast_path(sub_klass, super_klass,
3022 temp_reg, temp2_reg,
3023 &L_success, &L_failure, NULL);
3024 Register sub_2 = sub_klass;
3025 Register sup_2 = super_klass;
3026 if (!sub_2->is_global()) sub_2 = L0;
3027 if (!sup_2->is_global()) sup_2 = L1;
3028
3029 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
3030 check_klass_subtype_slow_path(sub_2, sup_2,
3031 L2, L3, L4, L5,
3032 NULL, &L_pop_to_failure);
3033
3034 // on success:
3035 restore();
3036 ba(L_success);
3037
3038 // on failure:
3039 bind(L_pop_to_failure);
3040 restore();
3041 bind(L_failure);
3042 }
3043
3044
3045 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3046 Register super_klass,
3047 Register temp_reg,
3048 Register temp2_reg,
3049 Label* L_success,
3050 Label* L_failure,
3051 Label* L_slow_path,
3052 RegisterOrConstant super_check_offset) {
3053 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
3054 Klass::secondary_super_cache_offset_in_bytes());
3055 int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
3056 Klass::super_check_offset_offset_in_bytes());
3057
3058 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3059 bool need_slow_path = (must_load_sco ||
3060 super_check_offset.constant_or_zero() == sco_offset);
3061
3062 assert_different_registers(sub_klass, super_klass, temp_reg);
3063 if (super_check_offset.is_register()) {
3064 assert_different_registers(sub_klass, super_klass, temp_reg,
3065 super_check_offset.as_register());
3066 } else if (must_load_sco) {
3067 assert(temp2_reg != noreg, "supply either a temp or a register offset");
3068 }
3069
3070 Label L_fallthrough;
3071 int label_nulls = 0;
3072 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3073 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3074 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3075 assert(label_nulls <= 1 ||
3076 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
3077 "at most one NULL in the batch, usually");
3078
3079 // If the pointers are equal, we are done (e.g., String[] elements).
3080 // This self-check enables sharing of secondary supertype arrays among
3081 // non-primary types such as array-of-interface. Otherwise, each such
3082 // type would need its own customized SSA.
3083 // We move this check to the front of the fast path because many
3084 // type checks are in fact trivially successful in this manner,
3085 // so we get a nicely predicted branch right at the start of the check.
3086 cmp(super_klass, sub_klass);
3087 brx(Assembler::equal, false, Assembler::pn, *L_success);
3088 delayed()->nop();
3089
3090 // Check the supertype display:
3091 if (must_load_sco) {
3092 // The super check offset is always positive...
3093 lduw(super_klass, sco_offset, temp2_reg);
3094 super_check_offset = RegisterOrConstant(temp2_reg);
3095 // super_check_offset is register.
3096 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register());
3097 }
3098 ld_ptr(sub_klass, super_check_offset, temp_reg);
3099 cmp(super_klass, temp_reg);
3100
3101 // This check has worked decisively for primary supers.
3102 // Secondary supers are sought in the super_cache ('super_cache_addr').
3103 // (Secondary supers are interfaces and very deeply nested subtypes.)
3104 // This works in the same check above because of a tricky aliasing
3105 // between the super_cache and the primary super display elements.
3106 // (The 'super_check_addr' can address either, as the case requires.)
3107 // Note that the cache is updated below if it does not help us find
3108 // what we need immediately.
3109 // So if it was a primary super, we can just fail immediately.
3110 // Otherwise, it's the slow path for us (no success at this point).
3111
3112 // Hacked ba(), which may only be used just before L_fallthrough.
3113 #define FINAL_JUMP(label) \
3114 if (&(label) != &L_fallthrough) { \
3115 ba(label, false); \
3116 delayed()->nop(); \
3117 }
3118
3119 if (super_check_offset.is_register()) {
3120 brx(Assembler::equal, false, Assembler::pn, *L_success);
3121 delayed()->cmp(super_check_offset.as_register(), sc_offset);
3122
3123 if (L_failure == &L_fallthrough) {
3124 brx(Assembler::equal, false, Assembler::pt, *L_slow_path);
3125 delayed()->nop();
3126 } else {
3127 brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
3128 delayed()->nop();
3129 FINAL_JUMP(*L_slow_path);
3130 }
3131 } else if (super_check_offset.as_constant() == sc_offset) {
3132 // Need a slow path; fast failure is impossible.
3133 if (L_slow_path == &L_fallthrough) {
3134 brx(Assembler::equal, false, Assembler::pt, *L_success);
3135 delayed()->nop();
3136 } else {
3137 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path);
3138 delayed()->nop();
3139 FINAL_JUMP(*L_success);
3140 }
3141 } else {
3142 // No slow path; it's a fast decision.
3143 if (L_failure == &L_fallthrough) {
3144 brx(Assembler::equal, false, Assembler::pt, *L_success);
3145 delayed()->nop();
3146 } else {
3147 brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
3148 delayed()->nop();
3149 FINAL_JUMP(*L_success);
3150 }
3151 }
3152
3153 bind(L_fallthrough);
3154
3155 #undef FINAL_JUMP
3156 }
3157
3158
3159 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
3160 Register super_klass,
3161 Register count_temp,
3162 Register scan_temp,
3163 Register scratch_reg,
3164 Register coop_reg,
3165 Label* L_success,
3166 Label* L_failure) {
3167 assert_different_registers(sub_klass, super_klass,
3168 count_temp, scan_temp, scratch_reg, coop_reg);
3169
3170 Label L_fallthrough, L_loop;
3171 int label_nulls = 0;
3172 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3173 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3174 assert(label_nulls <= 1, "at most one NULL in the batch");
3175
3176 // a couple of useful fields in sub_klass:
3177 int ss_offset = (klassOopDesc::header_size() * HeapWordSize +
3178 Klass::secondary_supers_offset_in_bytes());
3179 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
3180 Klass::secondary_super_cache_offset_in_bytes());
3181
3182 // Do a linear scan of the secondary super-klass chain.
3183 // This code is rarely used, so simplicity is a virtue here.
3184
3185 #ifndef PRODUCT
3186 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
3187 inc_counter((address) pst_counter, count_temp, scan_temp);
3188 #endif
3189
3190 // We will consult the secondary-super array.
3191 ld_ptr(sub_klass, ss_offset, scan_temp);
3192
3193 // Compress superclass if necessary.
3194 Register search_key = super_klass;
3195 bool decode_super_klass = false;
3196 if (UseCompressedOops) {
3197 if (coop_reg != noreg) {
3198 encode_heap_oop_not_null(super_klass, coop_reg);
3199 search_key = coop_reg;
3200 } else {
3201 encode_heap_oop_not_null(super_klass);
3202 decode_super_klass = true; // scarce temps!
3203 }
3204 // The superclass is never null; it would be a basic system error if a null
3205 // pointer were to sneak in here. Note that we have already loaded the
3206 // Klass::super_check_offset from the super_klass in the fast path,
3207 // so if there is a null in that register, we are already in the afterlife.
3208 }
3209
3210 // Load the array length. (Positive movl does right thing on LP64.)
3211 lduw(scan_temp, arrayOopDesc::length_offset_in_bytes(), count_temp);
3212
3213 // Check for empty secondary super list
3214 tst(count_temp);
3215
3216 // Top of search loop
3217 bind(L_loop);
3218 br(Assembler::equal, false, Assembler::pn, *L_failure);
3219 delayed()->add(scan_temp, heapOopSize, scan_temp);
3220 assert(heapOopSize != 0, "heapOopSize should be initialized");
3221
3222 // Skip the array header in all array accesses.
3223 int elem_offset = arrayOopDesc::base_offset_in_bytes(T_OBJECT);
3224 elem_offset -= heapOopSize; // the scan pointer was pre-incremented also
3225
3226 // Load next super to check
3227 if (UseCompressedOops) {
3228 // Don't use load_heap_oop; we don't want to decode the element.
3229 lduw( scan_temp, elem_offset, scratch_reg );
3230 } else {
3231 ld_ptr( scan_temp, elem_offset, scratch_reg );
3232 }
3233
3234 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
3235 cmp(scratch_reg, search_key);
3236
3237 // A miss means we are NOT a subtype and need to keep looping
3238 brx(Assembler::notEqual, false, Assembler::pn, L_loop);
3239 delayed()->deccc(count_temp); // decrement trip counter in delay slot
3240
3241 // Falling out the bottom means we found a hit; we ARE a subtype
3242 if (decode_super_klass) decode_heap_oop(super_klass);
3243
3244 // Success. Cache the super we found and proceed in triumph.
3245 st_ptr(super_klass, sub_klass, sc_offset);
3246
3247 if (L_success != &L_fallthrough) {
3248 ba(*L_success, false);
3249 delayed()->nop();
3250 }
3251
3252 bind(L_fallthrough);
3253 }
3254
3255
3256 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
3257 Register temp_reg,
3258 Label& wrong_method_type) {
3259 assert_different_registers(mtype_reg, mh_reg, temp_reg);
3260 // compare method type against that of the receiver
3261 RegisterOrConstant mhtype_offset = delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg);
3262 load_heap_oop(mh_reg, mhtype_offset, temp_reg);
3263 cmp_and_brx(temp_reg, mtype_reg, Assembler::notEqual, false, Assembler::pn, wrong_method_type);
3264 }
3265
3266
3267 // A method handle has a "vmslots" field which gives the size of its
3268 // argument list in JVM stack slots. This field is either located directly
3269 // in every method handle, or else is indirectly accessed through the
3270 // method handle's MethodType. This macro hides the distinction.
3271 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
3272 Register temp_reg) {
3273 assert_different_registers(vmslots_reg, mh_reg, temp_reg);
3274 // load mh.type.form.vmslots
3275 if (java_lang_invoke_MethodHandle::vmslots_offset_in_bytes() != 0) {
3276 // hoist vmslots into every mh to avoid dependent load chain
3277 ld( Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::vmslots_offset_in_bytes, temp_reg)), vmslots_reg);
3278 } else {
3279 Register temp2_reg = vmslots_reg;
3280 load_heap_oop(Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg)), temp2_reg);
3281 load_heap_oop(Address(temp2_reg, delayed_value(java_lang_invoke_MethodType::form_offset_in_bytes, temp_reg)), temp2_reg);
3282 ld( Address(temp2_reg, delayed_value(java_lang_invoke_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)), vmslots_reg);
3283 }
3284 }
3285
3286
3287 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop) {
3288 assert(mh_reg == G3_method_handle, "caller must put MH object in G3");
3289 assert_different_registers(mh_reg, temp_reg);
3290
3291 // pick out the interpreted side of the handler
3292 // NOTE: vmentry is not an oop!
3293 ld_ptr(mh_reg, delayed_value(java_lang_invoke_MethodHandle::vmentry_offset_in_bytes, temp_reg), temp_reg);
3294
3295 // off we go...
3296 ld_ptr(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes(), temp_reg);
3297 jmp(temp_reg, 0);
3298
3299 // for the various stubs which take control at this point,
3300 // see MethodHandles::generate_method_handle_stub
3301
3302 // Some callers can fill the delay slot.
3303 if (emit_delayed_nop) {
3304 delayed()->nop();
3305 }
3306 }
3307
3308
3309 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot,
3310 Register temp_reg,
3311 int extra_slot_offset) {
3312 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
3313 int stackElementSize = Interpreter::stackElementSize;
3314 int offset = extra_slot_offset * stackElementSize;
3315 if (arg_slot.is_constant()) {
3316 offset += arg_slot.as_constant() * stackElementSize;
3317 return offset;
3318 } else {
3319 assert(temp_reg != noreg, "must specify");
3320 sll_ptr(arg_slot.as_register(), exact_log2(stackElementSize), temp_reg);
3321 if (offset != 0)
3322 add(temp_reg, offset, temp_reg);
3323 return temp_reg;
3324 }
3325 }
3326
3327
3328 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
3329 Register temp_reg,
3330 int extra_slot_offset) {
3331 return Address(Gargs, argument_offset(arg_slot, temp_reg, extra_slot_offset));
3332 }
3333
3334
3335 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg,
3336 Register temp_reg,
3337 Label& done, Label* slow_case,
3338 BiasedLockingCounters* counters) {
3339 assert(UseBiasedLocking, "why call this otherwise?");
3340
3341 if (PrintBiasedLockingStatistics) {
3342 assert_different_registers(obj_reg, mark_reg, temp_reg, O7);
3343 if (counters == NULL)
3344 counters = BiasedLocking::counters();
3345 }
3346
3347 Label cas_label;
3348
3349 // Biased locking
3350 // See whether the lock is currently biased toward our thread and
3351 // whether the epoch is still valid
3352 // Note that the runtime guarantees sufficient alignment of JavaThread
3353 // pointers to allow age to be placed into low bits
3354 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
3355 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3356 cmp_and_brx(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, false, Assembler::pn, cas_label);
3357
3358 load_klass(obj_reg, temp_reg);
3359 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3360 or3(G2_thread, temp_reg, temp_reg);
3361 xor3(mark_reg, temp_reg, temp_reg);
3362 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg);
3363 if (counters != NULL) {
3364 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg);
3365 // Reload mark_reg as we may need it later
3366 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg);
3367 }
3368 brx(Assembler::equal, true, Assembler::pt, done);
3369 delayed()->nop();
3370
3371 Label try_revoke_bias;
3372 Label try_rebias;
3373 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
3374 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3375
3376 // At this point we know that the header has the bias pattern and
3377 // that we are not the bias owner in the current epoch. We need to
3378 // figure out more details about the state of the header in order to
3379 // know what operations can be legally performed on the object's
3380 // header.
3381
3382 // If the low three bits in the xor result aren't clear, that means
3383 // the prototype header is no longer biased and we have to revoke
3384 // the bias on this object.
3385 btst(markOopDesc::biased_lock_mask_in_place, temp_reg);
3386 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias);
3387
3388 // Biasing is still enabled for this data type. See whether the
3389 // epoch of the current bias is still valid, meaning that the epoch
3390 // bits of the mark word are equal to the epoch bits of the
3391 // prototype header. (Note that the prototype header's epoch bits
3392 // only change at a safepoint.) If not, attempt to rebias the object
3393 // toward the current thread. Note that we must be absolutely sure
3394 // that the current epoch is invalid in order to do this because
3395 // otherwise the manipulations it performs on the mark word are
3396 // illegal.
3397 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg);
3398 brx(Assembler::notZero, false, Assembler::pn, try_rebias);
3399
3400 // The epoch of the current bias is still valid but we know nothing
3401 // about the owner; it might be set or it might be clear. Try to
3402 // acquire the bias of the object using an atomic operation. If this
3403 // fails we will go in to the runtime to revoke the object's bias.
3404 // Note that we first construct the presumed unbiased header so we
3405 // don't accidentally blow away another thread's valid bias.
3406 delayed()->and3(mark_reg,
3407 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place,
3408 mark_reg);
3409 or3(G2_thread, mark_reg, temp_reg);
3410 casn(mark_addr.base(), mark_reg, temp_reg);
3411 // If the biasing toward our thread failed, this means that
3412 // another thread succeeded in biasing it toward itself and we
3413 // need to revoke that bias. The revocation will occur in the
3414 // interpreter runtime in the slow case.
3415 cmp(mark_reg, temp_reg);
3416 if (counters != NULL) {
3417 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg);
3418 }
3419 if (slow_case != NULL) {
3420 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3421 delayed()->nop();
3422 }
3423 ba(done);
3424
3425 bind(try_rebias);
3426 // At this point we know the epoch has expired, meaning that the
3427 // current "bias owner", if any, is actually invalid. Under these
3428 // circumstances _only_, we are allowed to use the current header's
3429 // value as the comparison value when doing the cas to acquire the
3430 // bias in the current epoch. In other words, we allow transfer of
3431 // the bias from one thread to another directly in this situation.
3432 //
3433 // FIXME: due to a lack of registers we currently blow away the age
3434 // bits in this situation. Should attempt to preserve them.
3435 load_klass(obj_reg, temp_reg);
3436 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3437 or3(G2_thread, temp_reg, temp_reg);
3438 casn(mark_addr.base(), mark_reg, temp_reg);
3439 // If the biasing toward our thread failed, this means that
3440 // another thread succeeded in biasing it toward itself and we
3441 // need to revoke that bias. The revocation will occur in the
3442 // interpreter runtime in the slow case.
3443 cmp(mark_reg, temp_reg);
3444 if (counters != NULL) {
3445 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg);
3446 }
3447 if (slow_case != NULL) {
3448 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3449 delayed()->nop();
3450 }
3451 ba(done);
3452
3453 bind(try_revoke_bias);
3454 // The prototype mark in the klass doesn't have the bias bit set any
3455 // more, indicating that objects of this data type are not supposed
3456 // to be biased any more. We are going to try to reset the mark of
3457 // this object to the prototype value and fall through to the
3458 // CAS-based locking scheme. Note that if our CAS fails, it means
3459 // that another thread raced us for the privilege of revoking the
3460 // bias of this particular object, so it's okay to continue in the
3461 // normal locking code.
3462 //
3463 // FIXME: due to a lack of registers we currently blow away the age
3464 // bits in this situation. Should attempt to preserve them.
3465 load_klass(obj_reg, temp_reg);
3466 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3467 casn(mark_addr.base(), mark_reg, temp_reg);
3468 // Fall through to the normal CAS-based lock, because no matter what
3469 // the result of the above CAS, some thread must have succeeded in
3470 // removing the bias bit from the object's header.
3471 if (counters != NULL) {
3472 cmp(mark_reg, temp_reg);
3473 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg);
3474 }
3475
3476 bind(cas_label);
3477 }
3478
3479 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done,
3480 bool allow_delay_slot_filling) {
3481 // Check for biased locking unlock case, which is a no-op
3482 // Note: we do not have to check the thread ID for two reasons.
3483 // First, the interpreter checks for IllegalMonitorStateException at
3484 // a higher level. Second, if the bias was revoked while we held the
3485 // lock, the object could not be rebiased toward another thread, so
3486 // the bias bit would be clear.
3487 ld_ptr(mark_addr, temp_reg);
3488 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3489 cmp(temp_reg, markOopDesc::biased_lock_pattern);
3490 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done);
3491 delayed();
3492 if (!allow_delay_slot_filling) {
3493 nop();
3494 }
3495 }
3496
3497
3498 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by
3499 // Solaris/SPARC's "as". Another apt name would be cas_ptr()
3500
3501 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) {
3502 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()) ;
3503 }
3504
3505
3506
3507 // compiler_lock_object() and compiler_unlock_object() are direct transliterations
3508 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments.
3509 // The code could be tightened up considerably.
3510 //
3511 // box->dhw disposition - post-conditions at DONE_LABEL.
3512 // - Successful inflated lock: box->dhw != 0.
3513 // Any non-zero value suffices.
3514 // Consider G2_thread, rsp, boxReg, or unused_mark()
3515 // - Successful Stack-lock: box->dhw == mark.
3516 // box->dhw must contain the displaced mark word value
3517 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined.
3518 // The slow-path fast_enter() and slow_enter() operators
3519 // are responsible for setting box->dhw = NonZero (typically ::unused_mark).
3520 // - Biased: box->dhw is undefined
3521 //
3522 // SPARC refworkload performance - specifically jetstream and scimark - are
3523 // extremely sensitive to the size of the code emitted by compiler_lock_object
3524 // and compiler_unlock_object. Critically, the key factor is code size, not path
3525 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the
3526 // effect).
3527
3528
3529 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark,
3530 Register Rbox, Register Rscratch,
3531 BiasedLockingCounters* counters,
3532 bool try_bias) {
3533 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3534
3535 verify_oop(Roop);
3536 Label done ;
3537
3538 if (counters != NULL) {
3539 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch);
3540 }
3541
3542 if (EmitSync & 1) {
3543 mov (3, Rscratch) ;
3544 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3545 cmp (SP, G0) ;
3546 return ;
3547 }
3548
3549 if (EmitSync & 2) {
3550
3551 // Fetch object's markword
3552 ld_ptr(mark_addr, Rmark);
3553
3554 if (try_bias) {
3555 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3556 }
3557
3558 // Save Rbox in Rscratch to be used for the cas operation
3559 mov(Rbox, Rscratch);
3560
3561 // set Rmark to markOop | markOopDesc::unlocked_value
3562 or3(Rmark, markOopDesc::unlocked_value, Rmark);
3563
3564 // Initialize the box. (Must happen before we update the object mark!)
3565 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3566
3567 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop
3568 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3569 casx_under_lock(mark_addr.base(), Rmark, Rscratch,
3570 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3571
3572 // if compare/exchange succeeded we found an unlocked object and we now have locked it
3573 // hence we are done
3574 cmp(Rmark, Rscratch);
3575 #ifdef _LP64
3576 sub(Rscratch, STACK_BIAS, Rscratch);
3577 #endif
3578 brx(Assembler::equal, false, Assembler::pt, done);
3579 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot
3580
3581 // we did not find an unlocked object so see if this is a recursive case
3582 // sub(Rscratch, SP, Rscratch);
3583 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3584 andcc(Rscratch, 0xfffff003, Rscratch);
3585 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3586 bind (done) ;
3587 return ;
3588 }
3589
3590 Label Egress ;
3591
3592 if (EmitSync & 256) {
3593 Label IsInflated ;
3594
3595 ld_ptr (mark_addr, Rmark); // fetch obj->mark
3596 // Triage: biased, stack-locked, neutral, inflated
3597 if (try_bias) {
3598 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3599 // Invariant: if control reaches this point in the emitted stream
3600 // then Rmark has not been modified.
3601 }
3602
3603 // Store mark into displaced mark field in the on-stack basic-lock "box"
3604 // Critically, this must happen before the CAS
3605 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty.
3606 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3607 andcc (Rmark, 2, G0) ;
3608 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ;
3609 delayed() ->
3610
3611 // Try stack-lock acquisition.
3612 // Beware: the 1st instruction is in a delay slot
3613 mov (Rbox, Rscratch);
3614 or3 (Rmark, markOopDesc::unlocked_value, Rmark);
3615 assert (mark_addr.disp() == 0, "cas must take a zero displacement");
3616 casn (mark_addr.base(), Rmark, Rscratch) ;
3617 cmp (Rmark, Rscratch);
3618 brx (Assembler::equal, false, Assembler::pt, done);
3619 delayed()->sub(Rscratch, SP, Rscratch);
3620
3621 // Stack-lock attempt failed - check for recursive stack-lock.
3622 // See the comments below about how we might remove this case.
3623 #ifdef _LP64
3624 sub (Rscratch, STACK_BIAS, Rscratch);
3625 #endif
3626 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3627 andcc (Rscratch, 0xfffff003, Rscratch);
3628 br (Assembler::always, false, Assembler::pt, done) ;
3629 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3630
3631 bind (IsInflated) ;
3632 if (EmitSync & 64) {
3633 // If m->owner != null goto IsLocked
3634 // Pessimistic form: Test-and-CAS vs CAS
3635 // The optimistic form avoids RTS->RTO cache line upgrades.
3636 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3637 andcc (Rscratch, Rscratch, G0) ;
3638 brx (Assembler::notZero, false, Assembler::pn, done) ;
3639 delayed()->nop() ;
3640 // m->owner == null : it's unlocked.
3641 }
3642
3643 // Try to CAS m->owner from null to Self
3644 // Invariant: if we acquire the lock then _recursions should be 0.
3645 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3646 mov (G2_thread, Rscratch) ;
3647 casn (Rmark, G0, Rscratch) ;
3648 cmp (Rscratch, G0) ;
3649 // Intentional fall-through into done
3650 } else {
3651 // Aggressively avoid the Store-before-CAS penalty
3652 // Defer the store into box->dhw until after the CAS
3653 Label IsInflated, Recursive ;
3654
3655 // Anticipate CAS -- Avoid RTS->RTO upgrade
3656 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ;
3657
3658 ld_ptr (mark_addr, Rmark); // fetch obj->mark
3659 // Triage: biased, stack-locked, neutral, inflated
3660
3661 if (try_bias) {
3662 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3663 // Invariant: if control reaches this point in the emitted stream
3664 // then Rmark has not been modified.
3665 }
3666 andcc (Rmark, 2, G0) ;
3667 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ;
3668 delayed()-> // Beware - dangling delay-slot
3669
3670 // Try stack-lock acquisition.
3671 // Transiently install BUSY (0) encoding in the mark word.
3672 // if the CAS of 0 into the mark was successful then we execute:
3673 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box
3674 // ST obj->mark = box -- overwrite transient 0 value
3675 // This presumes TSO, of course.
3676
3677 mov (0, Rscratch) ;
3678 or3 (Rmark, markOopDesc::unlocked_value, Rmark);
3679 assert (mark_addr.disp() == 0, "cas must take a zero displacement");
3680 casn (mark_addr.base(), Rmark, Rscratch) ;
3681 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ;
3682 cmp (Rscratch, Rmark) ;
3683 brx (Assembler::notZero, false, Assembler::pn, Recursive) ;
3684 delayed() ->
3685 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3686 if (counters != NULL) {
3687 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3688 }
3689 br (Assembler::always, false, Assembler::pt, done);
3690 delayed() ->
3691 st_ptr (Rbox, mark_addr) ;
3692
3693 bind (Recursive) ;
3694 // Stack-lock attempt failed - check for recursive stack-lock.
3695 // Tests show that we can remove the recursive case with no impact
3696 // on refworkload 0.83. If we need to reduce the size of the code
3697 // emitted by compiler_lock_object() the recursive case is perfect
3698 // candidate.
3699 //
3700 // A more extreme idea is to always inflate on stack-lock recursion.
3701 // This lets us eliminate the recursive checks in compiler_lock_object
3702 // and compiler_unlock_object and the (box->dhw == 0) encoding.
3703 // A brief experiment - requiring changes to synchronizer.cpp, interpreter,
3704 // and showed a performance *increase*. In the same experiment I eliminated
3705 // the fast-path stack-lock code from the interpreter and always passed
3706 // control to the "slow" operators in synchronizer.cpp.
3707
3708 // RScratch contains the fetched obj->mark value from the failed CASN.
3709 #ifdef _LP64
3710 sub (Rscratch, STACK_BIAS, Rscratch);
3711 #endif
3712 sub(Rscratch, SP, Rscratch);
3713 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3714 andcc (Rscratch, 0xfffff003, Rscratch);
3715 if (counters != NULL) {
3716 // Accounting needs the Rscratch register
3717 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3718 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3719 br (Assembler::always, false, Assembler::pt, done) ;
3720 delayed()->nop() ;
3721 } else {
3722 br (Assembler::always, false, Assembler::pt, done) ;
3723 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3724 }
3725
3726 bind (IsInflated) ;
3727 if (EmitSync & 64) {
3728 // If m->owner != null goto IsLocked
3729 // Test-and-CAS vs CAS
3730 // Pessimistic form avoids futile (doomed) CAS attempts
3731 // The optimistic form avoids RTS->RTO cache line upgrades.
3732 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3733 andcc (Rscratch, Rscratch, G0) ;
3734 brx (Assembler::notZero, false, Assembler::pn, done) ;
3735 delayed()->nop() ;
3736 // m->owner == null : it's unlocked.
3737 }
3738
3739 // Try to CAS m->owner from null to Self
3740 // Invariant: if we acquire the lock then _recursions should be 0.
3741 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3742 mov (G2_thread, Rscratch) ;
3743 casn (Rmark, G0, Rscratch) ;
3744 cmp (Rscratch, G0) ;
3745 // ST box->displaced_header = NonZero.
3746 // Any non-zero value suffices:
3747 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc.
3748 st_ptr (Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes());
3749 // Intentional fall-through into done
3750 }
3751
3752 bind (done) ;
3753 }
3754
3755 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark,
3756 Register Rbox, Register Rscratch,
3757 bool try_bias) {
3758 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3759
3760 Label done ;
3761
3762 if (EmitSync & 4) {
3763 cmp (SP, G0) ;
3764 return ;
3765 }
3766
3767 if (EmitSync & 8) {
3768 if (try_bias) {
3769 biased_locking_exit(mark_addr, Rscratch, done);
3770 }
3771
3772 // Test first if it is a fast recursive unlock
3773 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark);
3774 br_null(Rmark, false, Assembler::pt, done);
3775
3776 // Check if it is still a light weight lock, this is is true if we see
3777 // the stack address of the basicLock in the markOop of the object
3778 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3779 casx_under_lock(mark_addr.base(), Rbox, Rmark,
3780 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3781 ba(done, false);
3782 delayed()->cmp(Rbox, Rmark);
3783 bind (done) ;
3784 return ;
3785 }
3786
3787 // Beware ... If the aggregate size of the code emitted by CLO and CUO is
3788 // is too large performance rolls abruptly off a cliff.
3789 // This could be related to inlining policies, code cache management, or
3790 // I$ effects.
3791 Label LStacked ;
3792
3793 if (try_bias) {
3794 // TODO: eliminate redundant LDs of obj->mark
3795 biased_locking_exit(mark_addr, Rscratch, done);
3796 }
3797
3798 ld_ptr (Roop, oopDesc::mark_offset_in_bytes(), Rmark) ;
3799 ld_ptr (Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch);
3800 andcc (Rscratch, Rscratch, G0);
3801 brx (Assembler::zero, false, Assembler::pn, done);
3802 delayed()-> nop() ; // consider: relocate fetch of mark, above, into this DS
3803 andcc (Rmark, 2, G0) ;
3804 brx (Assembler::zero, false, Assembler::pt, LStacked) ;
3805 delayed()-> nop() ;
3806
3807 // It's inflated
3808 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before
3809 // the ST of 0 into _owner which releases the lock. This prevents loads
3810 // and stores within the critical section from reordering (floating)
3811 // past the store that releases the lock. But TSO is a strong memory model
3812 // and that particular flavor of barrier is a noop, so we can safely elide it.
3813 // Note that we use 1-0 locking by default for the inflated case. We
3814 // close the resultant (and rare) race by having contented threads in
3815 // monitorenter periodically poll _owner.
3816 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3817 ld_ptr (Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox);
3818 xor3 (Rscratch, G2_thread, Rscratch) ;
3819 orcc (Rbox, Rscratch, Rbox) ;
3820 brx (Assembler::notZero, false, Assembler::pn, done) ;
3821 delayed()->
3822 ld_ptr (Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch);
3823 ld_ptr (Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox);
3824 orcc (Rbox, Rscratch, G0) ;
3825 if (EmitSync & 65536) {
3826 Label LSucc ;
3827 brx (Assembler::notZero, false, Assembler::pn, LSucc) ;
3828 delayed()->nop() ;
3829 ba (done, false) ;
3830 delayed()->
3831 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3832
3833 bind (LSucc) ;
3834 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3835 if (os::is_MP()) { membar (StoreLoad) ; }
3836 ld_ptr (Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch);
3837 andcc (Rscratch, Rscratch, G0) ;
3838 brx (Assembler::notZero, false, Assembler::pt, done) ;
3839 delayed()-> andcc (G0, G0, G0) ;
3840 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3841 mov (G2_thread, Rscratch) ;
3842 casn (Rmark, G0, Rscratch) ;
3843 // invert icc.zf and goto done
3844 br_notnull(Rscratch, false, Assembler::pt, done, false) ;
3845 delayed() -> cmp (G0, G0) ;
3846 ba (done, false);
3847 delayed() -> cmp (G0, 1) ;
3848 } else {
3849 brx (Assembler::notZero, false, Assembler::pn, done) ;
3850 delayed()->nop() ;
3851 ba (done, false) ;
3852 delayed()->
3853 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3854 }
3855
3856 bind (LStacked) ;
3857 // Consider: we could replace the expensive CAS in the exit
3858 // path with a simple ST of the displaced mark value fetched from
3859 // the on-stack basiclock box. That admits a race where a thread T2
3860 // in the slow lock path -- inflating with monitor M -- could race a
3861 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2.
3862 // More precisely T1 in the stack-lock unlock path could "stomp" the
3863 // inflated mark value M installed by T2, resulting in an orphan
3864 // object monitor M and T2 becoming stranded. We can remedy that situation
3865 // by having T2 periodically poll the object's mark word using timed wait
3866 // operations. If T2 discovers that a stomp has occurred it vacates
3867 // the monitor M and wakes any other threads stranded on the now-orphan M.
3868 // In addition the monitor scavenger, which performs deflation,
3869 // would also need to check for orpan monitors and stranded threads.
3870 //
3871 // Finally, inflation is also used when T2 needs to assign a hashCode
3872 // to O and O is stack-locked by T1. The "stomp" race could cause
3873 // an assigned hashCode value to be lost. We can avoid that condition
3874 // and provide the necessary hashCode stability invariants by ensuring
3875 // that hashCode generation is idempotent between copying GCs.
3876 // For example we could compute the hashCode of an object O as
3877 // O's heap address XOR some high quality RNG value that is refreshed
3878 // at GC-time. The monitor scavenger would install the hashCode
3879 // found in any orphan monitors. Again, the mechanism admits a
3880 // lost-update "stomp" WAW race but detects and recovers as needed.
3881 //
3882 // A prototype implementation showed excellent results, although
3883 // the scavenger and timeout code was rather involved.
3884
3885 casn (mark_addr.base(), Rbox, Rscratch) ;
3886 cmp (Rbox, Rscratch);
3887 // Intentional fall through into done ...
3888
3889 bind (done) ;
3890 }
3891
3892
3893
3894 void MacroAssembler::print_CPU_state() {
3895 // %%%%% need to implement this
3896 }
3897
3898 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
3899 // %%%%% need to implement this
3900 }
3901
3902 void MacroAssembler::push_IU_state() {
3903 // %%%%% need to implement this
3904 }
3905
3906
3907 void MacroAssembler::pop_IU_state() {
3908 // %%%%% need to implement this
3909 }
3910
3911
3912 void MacroAssembler::push_FPU_state() {
3913 // %%%%% need to implement this
3914 }
3915
3916
3917 void MacroAssembler::pop_FPU_state() {
3918 // %%%%% need to implement this
3919 }
3920
3921
3922 void MacroAssembler::push_CPU_state() {
3923 // %%%%% need to implement this
3924 }
3925
3926
3927 void MacroAssembler::pop_CPU_state() {
3928 // %%%%% need to implement this
3929 }
3930
3931
3932
3933 void MacroAssembler::verify_tlab() {
3934 #ifdef ASSERT
3935 if (UseTLAB && VerifyOops) {
3936 Label next, next2, ok;
3937 Register t1 = L0;
3938 Register t2 = L1;
3939 Register t3 = L2;
3940
3941 save_frame(0);
3942 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3943 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2);
3944 or3(t1, t2, t3);
3945 cmp_and_br(t1, t2, Assembler::greaterEqual, false, Assembler::pn, next);
3946 stop("assert(top >= start)");
3947 should_not_reach_here();
3948
3949 bind(next);
3950 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3951 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2);
3952 or3(t3, t2, t3);
3953 cmp_and_br(t1, t2, Assembler::lessEqual, false, Assembler::pn, next2);
3954 stop("assert(top <= end)");
3955 should_not_reach_here();
3956
3957 bind(next2);
3958 and3(t3, MinObjAlignmentInBytesMask, t3);
3959 cmp_and_br(t3, 0, Assembler::lessEqual, false, Assembler::pn, ok);
3960 stop("assert(aligned)");
3961 should_not_reach_here();
3962
3963 bind(ok);
3964 restore();
3965 }
3966 #endif
3967 }
3968
3969
3970 void MacroAssembler::eden_allocate(
3971 Register obj, // result: pointer to object after successful allocation
3972 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
3973 int con_size_in_bytes, // object size in bytes if known at compile time
3974 Register t1, // temp register
3975 Register t2, // temp register
3976 Label& slow_case // continuation point if fast allocation fails
3977 ){
3978 // make sure arguments make sense
3979 assert_different_registers(obj, var_size_in_bytes, t1, t2);
3980 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size");
3981 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3982
3983 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
3984 // No allocation in the shared eden.
3985 ba(slow_case);
3986 } else {
3987 // get eden boundaries
3988 // note: we need both top & top_addr!
3989 const Register top_addr = t1;
3990 const Register end = t2;
3991
3992 CollectedHeap* ch = Universe::heap();
3993 set((intx)ch->top_addr(), top_addr);
3994 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr();
3995 ld_ptr(top_addr, delta, end);
3996 ld_ptr(top_addr, 0, obj);
3997
3998 // try to allocate
3999 Label retry;
4000 bind(retry);
4001 #ifdef ASSERT
4002 // make sure eden top is properly aligned
4003 {
4004 Label L;
4005 btst(MinObjAlignmentInBytesMask, obj);
4006 br(Assembler::zero, false, Assembler::pt, L);
4007 delayed()->nop();
4008 stop("eden top is not properly aligned");
4009 bind(L);
4010 }
4011 #endif // ASSERT
4012 const Register free = end;
4013 sub(end, obj, free); // compute amount of free space
4014 if (var_size_in_bytes->is_valid()) {
4015 // size is unknown at compile time
4016 cmp(free, var_size_in_bytes);
4017 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
4018 delayed()->add(obj, var_size_in_bytes, end);
4019 } else {
4020 // size is known at compile time
4021 cmp(free, con_size_in_bytes);
4022 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
4023 delayed()->add(obj, con_size_in_bytes, end);
4024 }
4025 // Compare obj with the value at top_addr; if still equal, swap the value of
4026 // end with the value at top_addr. If not equal, read the value at top_addr
4027 // into end.
4028 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
4029 // if someone beat us on the allocation, try again, otherwise continue
4030 cmp(obj, end);
4031 brx(Assembler::notEqual, false, Assembler::pn, retry);
4032 delayed()->mov(end, obj); // nop if successfull since obj == end
4033
4034 #ifdef ASSERT
4035 // make sure eden top is properly aligned
4036 {
4037 Label L;
4038 const Register top_addr = t1;
4039
4040 set((intx)ch->top_addr(), top_addr);
4041 ld_ptr(top_addr, 0, top_addr);
4042 btst(MinObjAlignmentInBytesMask, top_addr);
4043 br(Assembler::zero, false, Assembler::pt, L);
4044 delayed()->nop();
4045 stop("eden top is not properly aligned");
4046 bind(L);
4047 }
4048 #endif // ASSERT
4049 }
4050 }
4051
4052
4053 void MacroAssembler::tlab_allocate(
4054 Register obj, // result: pointer to object after successful allocation
4055 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
4056 int con_size_in_bytes, // object size in bytes if known at compile time
4057 Register t1, // temp register
4058 Label& slow_case // continuation point if fast allocation fails
4059 ){
4060 // make sure arguments make sense
4061 assert_different_registers(obj, var_size_in_bytes, t1);
4062 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size");
4063 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
4064
4065 const Register free = t1;
4066
4067 verify_tlab();
4068
4069 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj);
4070
4071 // calculate amount of free space
4072 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free);
4073 sub(free, obj, free);
4074
4075 Label done;
4076 if (var_size_in_bytes == noreg) {
4077 cmp(free, con_size_in_bytes);
4078 } else {
4079 cmp(free, var_size_in_bytes);
4080 }
4081 br(Assembler::less, false, Assembler::pn, slow_case);
4082 // calculate the new top pointer
4083 if (var_size_in_bytes == noreg) {
4084 delayed()->add(obj, con_size_in_bytes, free);
4085 } else {
4086 delayed()->add(obj, var_size_in_bytes, free);
4087 }
4088
4089 bind(done);
4090
4091 #ifdef ASSERT
4092 // make sure new free pointer is properly aligned
4093 {
4094 Label L;
4095 btst(MinObjAlignmentInBytesMask, free);
4096 br(Assembler::zero, false, Assembler::pt, L);
4097 delayed()->nop();
4098 stop("updated TLAB free is not properly aligned");
4099 bind(L);
4100 }
4101 #endif // ASSERT
4102
4103 // update the tlab top pointer
4104 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
4105 verify_tlab();
4106 }
4107
4108
4109 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
4110 Register top = O0;
4111 Register t1 = G1;
4112 Register t2 = G3;
4113 Register t3 = O1;
4114 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */);
4115 Label do_refill, discard_tlab;
4116
4117 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
4118 // No allocation in the shared eden.
4119 ba(slow_case);
4120 }
4121
4122 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top);
4123 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1);
4124 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2);
4125
4126 // calculate amount of free space
4127 sub(t1, top, t1);
4128 srl_ptr(t1, LogHeapWordSize, t1);
4129
4130 // Retain tlab and allocate object in shared space if
4131 // the amount free in the tlab is too large to discard.
4132 cmp(t1, t2);
4133 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab);
4134
4135 // increment waste limit to prevent getting stuck on this slow path
4136 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2);
4137 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
4138 if (TLABStats) {
4139 // increment number of slow_allocations
4140 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2);
4141 add(t2, 1, t2);
4142 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()));
4143 }
4144 ba(try_eden);
4145
4146 bind(discard_tlab);
4147 if (TLABStats) {
4148 // increment number of refills
4149 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2);
4150 add(t2, 1, t2);
4151 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()));
4152 // accumulate wastage
4153 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2);
4154 add(t2, t1, t2);
4155 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
4156 }
4157
4158 // if tlab is currently allocated (top or end != null) then
4159 // fill [top, end + alignment_reserve) with array object
4160 br_null(top, false, Assembler::pn, do_refill);
4161
4162 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2);
4163 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word
4164 // set klass to intArrayKlass
4165 sub(t1, typeArrayOopDesc::header_size(T_INT), t1);
4166 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1);
4167 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1);
4168 st(t1, top, arrayOopDesc::length_offset_in_bytes());
4169 set((intptr_t)Universe::intArrayKlassObj_addr(), t2);
4170 ld_ptr(t2, 0, t2);
4171 // store klass last. concurrent gcs assumes klass length is valid if
4172 // klass field is not null.
4173 store_klass(t2, top);
4174 verify_oop(top);
4175
4176 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1);
4177 sub(top, t1, t1); // size of tlab's allocated portion
4178 incr_allocated_bytes(t1, t2, t3);
4179
4180 // refill the tlab with an eden allocation
4181 bind(do_refill);
4182 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1);
4183 sll_ptr(t1, LogHeapWordSize, t1);
4184 // allocate new tlab, address returned in top
4185 eden_allocate(top, t1, 0, t2, t3, slow_case);
4186
4187 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset()));
4188 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
4189 #ifdef ASSERT
4190 // check that tlab_size (t1) is still valid
4191 {
4192 Label ok;
4193 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2);
4194 sll_ptr(t2, LogHeapWordSize, t2);
4195 cmp_and_br(t1, t2, Assembler::equal, false, Assembler::pn, ok);
4196 stop("assert(t1 == tlab_size)");
4197 should_not_reach_here();
4198
4199 bind(ok);
4200 }
4201 #endif // ASSERT
4202 add(top, t1, top); // t1 is tlab_size
4203 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top);
4204 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset()));
4205 verify_tlab();
4206 ba(retry);
4207 }
4208
4209 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes,
4210 Register t1, Register t2) {
4211 // Bump total bytes allocated by this thread
4212 assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch
4213 assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2);
4214 // v8 support has gone the way of the dodo
4215 ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1);
4216 add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1);
4217 stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset()));
4218 }
4219
4220 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
4221 switch (cond) {
4222 // Note some conditions are synonyms for others
4223 case Assembler::never: return Assembler::always;
4224 case Assembler::zero: return Assembler::notZero;
4225 case Assembler::lessEqual: return Assembler::greater;
4226 case Assembler::less: return Assembler::greaterEqual;
4227 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned;
4228 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned;
4229 case Assembler::negative: return Assembler::positive;
4230 case Assembler::overflowSet: return Assembler::overflowClear;
4231 case Assembler::always: return Assembler::never;
4232 case Assembler::notZero: return Assembler::zero;
4233 case Assembler::greater: return Assembler::lessEqual;
4234 case Assembler::greaterEqual: return Assembler::less;
4235 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned;
4236 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned;
4237 case Assembler::positive: return Assembler::negative;
4238 case Assembler::overflowClear: return Assembler::overflowSet;
4239 }
4240
4241 ShouldNotReachHere(); return Assembler::overflowClear;
4242 }
4243
4244 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr,
4245 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) {
4246 Condition negated_cond = negate_condition(cond);
4247 Label L;
4248 brx(negated_cond, false, Assembler::pt, L);
4249 delayed()->nop();
4250 inc_counter(counter_ptr, Rtmp1, Rtmp2);
4251 bind(L);
4252 }
4253
4254 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) {
4255 AddressLiteral addrlit(counter_addr);
4256 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register.
4257 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits.
4258 ld(addr, Rtmp2);
4259 inc(Rtmp2);
4260 st(Rtmp2, addr);
4261 }
4262
4263 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) {
4264 inc_counter((address) counter_addr, Rtmp1, Rtmp2);
4265 }
4266
4267 SkipIfEqual::SkipIfEqual(
4268 MacroAssembler* masm, Register temp, const bool* flag_addr,
4269 Assembler::Condition condition) {
4270 _masm = masm;
4271 AddressLiteral flag(flag_addr);
4272 _masm->sethi(flag, temp);
4273 _masm->ldub(temp, flag.low10(), temp);
4274 _masm->tst(temp);
4275 _masm->br(condition, false, Assembler::pt, _label);
4276 _masm->delayed()->nop();
4277 }
4278
4279 SkipIfEqual::~SkipIfEqual() {
4280 _masm->bind(_label);
4281 }
4282
4283
4284 // Writes to stack successive pages until offset reached to check for
4285 // stack overflow + shadow pages. This clobbers tsp and scratch.
4286 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp,
4287 Register Rscratch) {
4288 // Use stack pointer in temp stack pointer
4289 mov(SP, Rtsp);
4290
4291 // Bang stack for total size given plus stack shadow page size.
4292 // Bang one page at a time because a large size can overflow yellow and
4293 // red zones (the bang will fail but stack overflow handling can't tell that
4294 // it was a stack overflow bang vs a regular segv).
4295 int offset = os::vm_page_size();
4296 Register Roffset = Rscratch;
4297
4298 Label loop;
4299 bind(loop);
4300 set((-offset)+STACK_BIAS, Rscratch);
4301 st(G0, Rtsp, Rscratch);
4302 set(offset, Roffset);
4303 sub(Rsize, Roffset, Rsize);
4304 cmp(Rsize, G0);
4305 br(Assembler::greater, false, Assembler::pn, loop);
4306 delayed()->sub(Rtsp, Roffset, Rtsp);
4307
4308 // Bang down shadow pages too.
4309 // The -1 because we already subtracted 1 page.
4310 for (int i = 0; i< StackShadowPages-1; i++) {
4311 set((-i*offset)+STACK_BIAS, Rscratch);
4312 st(G0, Rtsp, Rscratch);
4313 }
4314 }
4315
4316 ///////////////////////////////////////////////////////////////////////////////////
4317 #ifndef SERIALGC
4318
4319 static address satb_log_enqueue_with_frame = NULL;
4320 static u_char* satb_log_enqueue_with_frame_end = NULL;
4321
4322 static address satb_log_enqueue_frameless = NULL;
4323 static u_char* satb_log_enqueue_frameless_end = NULL;
4324
4325 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions?
4326
4327 static void generate_satb_log_enqueue(bool with_frame) {
4328 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize);
4329 CodeBuffer buf(bb);
4330 MacroAssembler masm(&buf);
4331
4332 #define __ masm.
4333
4334 address start = __ pc();
4335 Register pre_val;
4336
4337 Label refill, restart;
4338 if (with_frame) {
4339 __ save_frame(0);
4340 pre_val = I0; // Was O0 before the save.
4341 } else {
4342 pre_val = O0;
4343 }
4344 int satb_q_index_byte_offset =
4345 in_bytes(JavaThread::satb_mark_queue_offset() +
4346 PtrQueue::byte_offset_of_index());
4347 int satb_q_buf_byte_offset =
4348 in_bytes(JavaThread::satb_mark_queue_offset() +
4349 PtrQueue::byte_offset_of_buf());
4350 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) &&
4351 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t),
4352 "check sizes in assembly below");
4353
4354 __ bind(restart);
4355 __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0);
4356
4357 __ br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, L0, refill, false);
4358 // If the branch is taken, no harm in executing this in the delay slot.
4359 __ delayed()->ld_ptr(G2_thread, satb_q_buf_byte_offset, L1);
4360 __ sub(L0, oopSize, L0);
4361
4362 __ st_ptr(pre_val, L1, L0); // [_buf + index] := I0
4363 if (!with_frame) {
4364 // Use return-from-leaf
4365 __ retl();
4366 __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset);
4367 } else {
4368 // Not delayed.
4369 __ st_ptr(L0, G2_thread, satb_q_index_byte_offset);
4370 }
4371 if (with_frame) {
4372 __ ret();
4373 __ delayed()->restore();
4374 }
4375 __ bind(refill);
4376
4377 address handle_zero =
4378 CAST_FROM_FN_PTR(address,
4379 &SATBMarkQueueSet::handle_zero_index_for_thread);
4380 // This should be rare enough that we can afford to save all the
4381 // scratch registers that the calling context might be using.
4382 __ mov(G1_scratch, L0);
4383 __ mov(G3_scratch, L1);
4384 __ mov(G4, L2);
4385 // We need the value of O0 above (for the write into the buffer), so we
4386 // save and restore it.
4387 __ mov(O0, L3);
4388 // Since the call will overwrite O7, we save and restore that, as well.
4389 __ mov(O7, L4);
4390 __ call_VM_leaf(L5, handle_zero, G2_thread);
4391 __ mov(L0, G1_scratch);
4392 __ mov(L1, G3_scratch);
4393 __ mov(L2, G4);
4394 __ mov(L3, O0);
4395 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4396 __ delayed()->mov(L4, O7);
4397
4398 if (with_frame) {
4399 satb_log_enqueue_with_frame = start;
4400 satb_log_enqueue_with_frame_end = __ pc();
4401 } else {
4402 satb_log_enqueue_frameless = start;
4403 satb_log_enqueue_frameless_end = __ pc();
4404 }
4405
4406 #undef __
4407 }
4408
4409 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) {
4410 if (with_frame) {
4411 if (satb_log_enqueue_with_frame == 0) {
4412 generate_satb_log_enqueue(with_frame);
4413 assert(satb_log_enqueue_with_frame != 0, "postcondition.");
4414 if (G1SATBPrintStubs) {
4415 tty->print_cr("Generated with-frame satb enqueue:");
4416 Disassembler::decode((u_char*)satb_log_enqueue_with_frame,
4417 satb_log_enqueue_with_frame_end,
4418 tty);
4419 }
4420 }
4421 } else {
4422 if (satb_log_enqueue_frameless == 0) {
4423 generate_satb_log_enqueue(with_frame);
4424 assert(satb_log_enqueue_frameless != 0, "postcondition.");
4425 if (G1SATBPrintStubs) {
4426 tty->print_cr("Generated frameless satb enqueue:");
4427 Disassembler::decode((u_char*)satb_log_enqueue_frameless,
4428 satb_log_enqueue_frameless_end,
4429 tty);
4430 }
4431 }
4432 }
4433 }
4434
4435 void MacroAssembler::g1_write_barrier_pre(Register obj,
4436 Register index,
4437 int offset,
4438 Register pre_val,
4439 Register tmp,
4440 bool preserve_o_regs) {
4441 Label filtered;
4442
4443 if (obj == noreg) {
4444 // We are not loading the previous value so make
4445 // sure that we don't trash the value in pre_val
4446 // with the code below.
4447 assert_different_registers(pre_val, tmp);
4448 } else {
4449 // We will be loading the previous value
4450 // in this code so...
4451 assert(offset == 0 || index == noreg, "choose one");
4452 assert(pre_val == noreg, "check this code");
4453 }
4454
4455 // Is marking active?
4456 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4457 ld(G2,
4458 in_bytes(JavaThread::satb_mark_queue_offset() +
4459 PtrQueue::byte_offset_of_active()),
4460 tmp);
4461 } else {
4462 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1,
4463 "Assumption");
4464 ldsb(G2,
4465 in_bytes(JavaThread::satb_mark_queue_offset() +
4466 PtrQueue::byte_offset_of_active()),
4467 tmp);
4468 }
4469
4470 // Check on whether to annul.
4471 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered);
4472
4473 // Do we need to load the previous value?
4474 if (obj != noreg) {
4475 // Load the previous value...
4476 if (index == noreg) {
4477 if (Assembler::is_simm13(offset)) {
4478 load_heap_oop(obj, offset, tmp);
4479 } else {
4480 set(offset, tmp);
4481 load_heap_oop(obj, tmp, tmp);
4482 }
4483 } else {
4484 load_heap_oop(obj, index, tmp);
4485 }
4486 // Previous value has been loaded into tmp
4487 pre_val = tmp;
4488 }
4489
4490 assert(pre_val != noreg, "must have a real register");
4491
4492 // Is the previous value null?
4493 // Check on whether to annul.
4494 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, pre_val, filtered);
4495
4496 // OK, it's not filtered, so we'll need to call enqueue. In the normal
4497 // case, pre_val will be a scratch G-reg, but there are some cases in
4498 // which it's an O-reg. In the first case, do a normal call. In the
4499 // latter, do a save here and call the frameless version.
4500
4501 guarantee(pre_val->is_global() || pre_val->is_out(),
4502 "Or we need to think harder.");
4503
4504 if (pre_val->is_global() && !preserve_o_regs) {
4505 generate_satb_log_enqueue_if_necessary(true); // with frame
4506
4507 call(satb_log_enqueue_with_frame);
4508 delayed()->mov(pre_val, O0);
4509 } else {
4510 generate_satb_log_enqueue_if_necessary(false); // frameless
4511
4512 save_frame(0);
4513 call(satb_log_enqueue_frameless);
4514 delayed()->mov(pre_val->after_save(), O0);
4515 restore();
4516 }
4517
4518 bind(filtered);
4519 }
4520
4521 static jint num_ct_writes = 0;
4522 static jint num_ct_writes_filtered_in_hr = 0;
4523 static jint num_ct_writes_filtered_null = 0;
4524 static G1CollectedHeap* g1 = NULL;
4525
4526 static Thread* count_ct_writes(void* filter_val, void* new_val) {
4527 Atomic::inc(&num_ct_writes);
4528 if (filter_val == NULL) {
4529 Atomic::inc(&num_ct_writes_filtered_in_hr);
4530 } else if (new_val == NULL) {
4531 Atomic::inc(&num_ct_writes_filtered_null);
4532 } else {
4533 if (g1 == NULL) {
4534 g1 = G1CollectedHeap::heap();
4535 }
4536 }
4537 if ((num_ct_writes % 1000000) == 0) {
4538 jint num_ct_writes_filtered =
4539 num_ct_writes_filtered_in_hr +
4540 num_ct_writes_filtered_null;
4541
4542 tty->print_cr("%d potential CT writes: %5.2f%% filtered\n"
4543 " (%5.2f%% intra-HR, %5.2f%% null).",
4544 num_ct_writes,
4545 100.0*(float)num_ct_writes_filtered/(float)num_ct_writes,
4546 100.0*(float)num_ct_writes_filtered_in_hr/
4547 (float)num_ct_writes,
4548 100.0*(float)num_ct_writes_filtered_null/
4549 (float)num_ct_writes);
4550 }
4551 return Thread::current();
4552 }
4553
4554 static address dirty_card_log_enqueue = 0;
4555 static u_char* dirty_card_log_enqueue_end = 0;
4556
4557 // This gets to assume that o0 contains the object address.
4558 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) {
4559 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2);
4560 CodeBuffer buf(bb);
4561 MacroAssembler masm(&buf);
4562 #define __ masm.
4563 address start = __ pc();
4564
4565 Label not_already_dirty, restart, refill;
4566
4567 #ifdef _LP64
4568 __ srlx(O0, CardTableModRefBS::card_shift, O0);
4569 #else
4570 __ srl(O0, CardTableModRefBS::card_shift, O0);
4571 #endif
4572 AddressLiteral addrlit(byte_map_base);
4573 __ set(addrlit, O1); // O1 := <card table base>
4574 __ ldub(O0, O1, O2); // O2 := [O0 + O1]
4575
4576 __ br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt,
4577 O2, not_already_dirty, false);
4578 // Get O1 + O2 into a reg by itself -- useful in the take-the-branch
4579 // case, harmless if not.
4580 __ delayed()->add(O0, O1, O3);
4581
4582 // We didn't take the branch, so we're already dirty: return.
4583 // Use return-from-leaf
4584 __ retl();
4585 __ delayed()->nop();
4586
4587 // Not dirty.
4588 __ bind(not_already_dirty);
4589 // First, dirty it.
4590 __ stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty).
4591 int dirty_card_q_index_byte_offset =
4592 in_bytes(JavaThread::dirty_card_queue_offset() +
4593 PtrQueue::byte_offset_of_index());
4594 int dirty_card_q_buf_byte_offset =
4595 in_bytes(JavaThread::dirty_card_queue_offset() +
4596 PtrQueue::byte_offset_of_buf());
4597 __ bind(restart);
4598 __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0);
4599
4600 __ br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn,
4601 L0, refill, false);
4602 // If the branch is taken, no harm in executing this in the delay slot.
4603 __ delayed()->ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1);
4604 __ sub(L0, oopSize, L0);
4605
4606 __ st_ptr(O3, L1, L0); // [_buf + index] := I0
4607 // Use return-from-leaf
4608 __ retl();
4609 __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset);
4610
4611 __ bind(refill);
4612 address handle_zero =
4613 CAST_FROM_FN_PTR(address,
4614 &DirtyCardQueueSet::handle_zero_index_for_thread);
4615 // This should be rare enough that we can afford to save all the
4616 // scratch registers that the calling context might be using.
4617 __ mov(G1_scratch, L3);
4618 __ mov(G3_scratch, L5);
4619 // We need the value of O3 above (for the write into the buffer), so we
4620 // save and restore it.
4621 __ mov(O3, L6);
4622 // Since the call will overwrite O7, we save and restore that, as well.
4623 __ mov(O7, L4);
4624
4625 __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread);
4626 __ mov(L3, G1_scratch);
4627 __ mov(L5, G3_scratch);
4628 __ mov(L6, O3);
4629 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4630 __ delayed()->mov(L4, O7);
4631
4632 dirty_card_log_enqueue = start;
4633 dirty_card_log_enqueue_end = __ pc();
4634 // XXX Should have a guarantee here about not going off the end!
4635 // Does it already do so? Do an experiment...
4636
4637 #undef __
4638
4639 }
4640
4641 static inline void
4642 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) {
4643 if (dirty_card_log_enqueue == 0) {
4644 generate_dirty_card_log_enqueue(byte_map_base);
4645 assert(dirty_card_log_enqueue != 0, "postcondition.");
4646 if (G1SATBPrintStubs) {
4647 tty->print_cr("Generated dirty_card enqueue:");
4648 Disassembler::decode((u_char*)dirty_card_log_enqueue,
4649 dirty_card_log_enqueue_end,
4650 tty);
4651 }
4652 }
4653 }
4654
4655
4656 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
4657
4658 Label filtered;
4659 MacroAssembler* post_filter_masm = this;
4660
4661 if (new_val == G0) return;
4662
4663 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set();
4664 assert(bs->kind() == BarrierSet::G1SATBCT ||
4665 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier");
4666 if (G1RSBarrierRegionFilter) {
4667 xor3(store_addr, new_val, tmp);
4668 #ifdef _LP64
4669 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
4670 #else
4671 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
4672 #endif
4673
4674 if (G1PrintCTFilterStats) {
4675 guarantee(tmp->is_global(), "Or stats won't work...");
4676 // This is a sleazy hack: I'm temporarily hijacking G2, which I
4677 // promise to restore.
4678 mov(new_val, G2);
4679 save_frame(0);
4680 mov(tmp, O0);
4681 mov(G2, O1);
4682 // Save G-regs that target may use.
4683 mov(G1, L1);
4684 mov(G2, L2);
4685 mov(G3, L3);
4686 mov(G4, L4);
4687 mov(G5, L5);
4688 call(CAST_FROM_FN_PTR(address, &count_ct_writes));
4689 delayed()->nop();
4690 mov(O0, G2);
4691 // Restore G-regs that target may have used.
4692 mov(L1, G1);
4693 mov(L3, G3);
4694 mov(L4, G4);
4695 mov(L5, G5);
4696 restore(G0, G0, G0);
4697 }
4698 // XXX Should I predict this taken or not? Does it mattern?
4699 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered);
4700 }
4701
4702 // If the "store_addr" register is an "in" or "local" register, move it to
4703 // a scratch reg so we can pass it as an argument.
4704 bool use_scr = !(store_addr->is_global() || store_addr->is_out());
4705 // Pick a scratch register different from "tmp".
4706 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch);
4707 // Make sure we use up the delay slot!
4708 if (use_scr) {
4709 post_filter_masm->mov(store_addr, scr);
4710 } else {
4711 post_filter_masm->nop();
4712 }
4713 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base);
4714 save_frame(0);
4715 call(dirty_card_log_enqueue);
4716 if (use_scr) {
4717 delayed()->mov(scr, O0);
4718 } else {
4719 delayed()->mov(store_addr->after_save(), O0);
4720 }
4721 restore();
4722
4723 bind(filtered);
4724
4725 }
4726
4727 #endif // SERIALGC
4728 ///////////////////////////////////////////////////////////////////////////////////
4729
4730 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
4731 // If we're writing constant NULL, we can skip the write barrier.
4732 if (new_val == G0) return;
4733 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set();
4734 assert(bs->kind() == BarrierSet::CardTableModRef ||
4735 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier");
4736 card_table_write(bs->byte_map_base, tmp, store_addr);
4737 }
4738
4739 void MacroAssembler::load_klass(Register src_oop, Register klass) {
4740 // The number of bytes in this code is used by
4741 // MachCallDynamicJavaNode::ret_addr_offset()
4742 // if this changes, change that.
4743 if (UseCompressedOops) {
4744 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass);
4745 decode_heap_oop_not_null(klass);
4746 } else {
4747 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass);
4748 }
4749 }
4750
4751 void MacroAssembler::store_klass(Register klass, Register dst_oop) {
4752 if (UseCompressedOops) {
4753 assert(dst_oop != klass, "not enough registers");
4754 encode_heap_oop_not_null(klass);
4755 st(klass, dst_oop, oopDesc::klass_offset_in_bytes());
4756 } else {
4757 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes());
4758 }
4759 }
4760
4761 void MacroAssembler::store_klass_gap(Register s, Register d) {
4762 if (UseCompressedOops) {
4763 assert(s != d, "not enough registers");
4764 st(s, d, oopDesc::klass_gap_offset_in_bytes());
4765 }
4766 }
4767
4768 void MacroAssembler::load_heap_oop(const Address& s, Register d) {
4769 if (UseCompressedOops) {
4770 lduw(s, d);
4771 decode_heap_oop(d);
4772 } else {
4773 ld_ptr(s, d);
4774 }
4775 }
4776
4777 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) {
4778 if (UseCompressedOops) {
4779 lduw(s1, s2, d);
4780 decode_heap_oop(d, d);
4781 } else {
4782 ld_ptr(s1, s2, d);
4783 }
4784 }
4785
4786 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) {
4787 if (UseCompressedOops) {
4788 lduw(s1, simm13a, d);
4789 decode_heap_oop(d, d);
4790 } else {
4791 ld_ptr(s1, simm13a, d);
4792 }
4793 }
4794
4795 void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) {
4796 if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d);
4797 else load_heap_oop(s1, s2.as_register(), d);
4798 }
4799
4800 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) {
4801 if (UseCompressedOops) {
4802 assert(s1 != d && s2 != d, "not enough registers");
4803 encode_heap_oop(d);
4804 st(d, s1, s2);
4805 } else {
4806 st_ptr(d, s1, s2);
4807 }
4808 }
4809
4810 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) {
4811 if (UseCompressedOops) {
4812 assert(s1 != d, "not enough registers");
4813 encode_heap_oop(d);
4814 st(d, s1, simm13a);
4815 } else {
4816 st_ptr(d, s1, simm13a);
4817 }
4818 }
4819
4820 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) {
4821 if (UseCompressedOops) {
4822 assert(a.base() != d, "not enough registers");
4823 encode_heap_oop(d);
4824 st(d, a, offset);
4825 } else {
4826 st_ptr(d, a, offset);
4827 }
4828 }
4829
4830
4831 void MacroAssembler::encode_heap_oop(Register src, Register dst) {
4832 assert (UseCompressedOops, "must be compressed");
4833 assert (Universe::heap() != NULL, "java heap should be initialized");
4834 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4835 verify_oop(src);
4836 if (Universe::narrow_oop_base() == NULL) {
4837 srlx(src, LogMinObjAlignmentInBytes, dst);
4838 return;
4839 }
4840 Label done;
4841 if (src == dst) {
4842 // optimize for frequent case src == dst
4843 bpr(rc_nz, true, Assembler::pt, src, done);
4844 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken
4845 bind(done);
4846 srlx(src, LogMinObjAlignmentInBytes, dst);
4847 } else {
4848 bpr(rc_z, false, Assembler::pn, src, done);
4849 delayed() -> mov(G0, dst);
4850 // could be moved before branch, and annulate delay,
4851 // but may add some unneeded work decoding null
4852 sub(src, G6_heapbase, dst);
4853 srlx(dst, LogMinObjAlignmentInBytes, dst);
4854 bind(done);
4855 }
4856 }
4857
4858
4859 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4860 assert (UseCompressedOops, "must be compressed");
4861 assert (Universe::heap() != NULL, "java heap should be initialized");
4862 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4863 verify_oop(r);
4864 if (Universe::narrow_oop_base() != NULL)
4865 sub(r, G6_heapbase, r);
4866 srlx(r, LogMinObjAlignmentInBytes, r);
4867 }
4868
4869 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) {
4870 assert (UseCompressedOops, "must be compressed");
4871 assert (Universe::heap() != NULL, "java heap should be initialized");
4872 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4873 verify_oop(src);
4874 if (Universe::narrow_oop_base() == NULL) {
4875 srlx(src, LogMinObjAlignmentInBytes, dst);
4876 } else {
4877 sub(src, G6_heapbase, dst);
4878 srlx(dst, LogMinObjAlignmentInBytes, dst);
4879 }
4880 }
4881
4882 // Same algorithm as oops.inline.hpp decode_heap_oop.
4883 void MacroAssembler::decode_heap_oop(Register src, Register dst) {
4884 assert (UseCompressedOops, "must be compressed");
4885 assert (Universe::heap() != NULL, "java heap should be initialized");
4886 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4887 sllx(src, LogMinObjAlignmentInBytes, dst);
4888 if (Universe::narrow_oop_base() != NULL) {
4889 Label done;
4890 bpr(rc_nz, true, Assembler::pt, dst, done);
4891 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken
4892 bind(done);
4893 }
4894 verify_oop(dst);
4895 }
4896
4897 void MacroAssembler::decode_heap_oop_not_null(Register r) {
4898 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4899 // pd_code_size_limit.
4900 // Also do not verify_oop as this is called by verify_oop.
4901 assert (UseCompressedOops, "must be compressed");
4902 assert (Universe::heap() != NULL, "java heap should be initialized");
4903 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4904 sllx(r, LogMinObjAlignmentInBytes, r);
4905 if (Universe::narrow_oop_base() != NULL)
4906 add(r, G6_heapbase, r);
4907 }
4908
4909 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) {
4910 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4911 // pd_code_size_limit.
4912 // Also do not verify_oop as this is called by verify_oop.
4913 assert (UseCompressedOops, "must be compressed");
4914 assert (Universe::heap() != NULL, "java heap should be initialized");
4915 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4916 sllx(src, LogMinObjAlignmentInBytes, dst);
4917 if (Universe::narrow_oop_base() != NULL)
4918 add(dst, G6_heapbase, dst);
4919 }
4920
4921 void MacroAssembler::reinit_heapbase() {
4922 if (UseCompressedOops) {
4923 // call indirectly to solve generation ordering problem
4924 AddressLiteral base(Universe::narrow_oop_base_addr());
4925 load_ptr_contents(base, G6_heapbase);
4926 }
4927 }
4928
4929 // Compare char[] arrays aligned to 4 bytes.
4930 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
4931 Register limit, Register result,
4932 Register chr1, Register chr2, Label& Ldone) {
4933 Label Lvector, Lloop;
4934 assert(chr1 == result, "should be the same");
4935
4936 // Note: limit contains number of bytes (2*char_elements) != 0.
4937 andcc(limit, 0x2, chr1); // trailing character ?
4938 br(Assembler::zero, false, Assembler::pt, Lvector);
4939 delayed()->nop();
4940
4941 // compare the trailing char
4942 sub(limit, sizeof(jchar), limit);
4943 lduh(ary1, limit, chr1);
4944 lduh(ary2, limit, chr2);
4945 cmp(chr1, chr2);
4946 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4947 delayed()->mov(G0, result); // not equal
4948
4949 // only one char ?
4950 bpr(rc_z, true, Assembler::pn, limit, Ldone);
4951 delayed()->add(G0, 1, result); // zero-length arrays are equal
4952
4953 // word by word compare, dont't need alignment check
4954 bind(Lvector);
4955 // Shift ary1 and ary2 to the end of the arrays, negate limit
4956 add(ary1, limit, ary1);
4957 add(ary2, limit, ary2);
4958 neg(limit, limit);
4959
4960 lduw(ary1, limit, chr1);
4961 bind(Lloop);
4962 lduw(ary2, limit, chr2);
4963 cmp(chr1, chr2);
4964 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4965 delayed()->mov(G0, result); // not equal
4966 inccc(limit, 2*sizeof(jchar));
4967 // annul LDUW if branch is not taken to prevent access past end of array
4968 br(Assembler::notZero, true, Assembler::pt, Lloop);
4969 delayed()->lduw(ary1, limit, chr1); // hoisted
4970
4971 // Caller should set it:
4972 // add(G0, 1, result); // equals
4973 }