src/cpu/sparc/vm/assembler_sparc.hpp

*** 982,1002 ****
    static int opf_low5( int         w)  { return  u_field(w,              9,  5); }
    static int trapcc(   CC         cc)  { return  u_field(cc,            12, 11); }
    static int sx(       int         i)  { return  u_field(i,             12, 12); } // shift x=1 means 64-bit
    static int opf(      int         x)  { return  u_field(x,             13,  5); }
  
!   static bool is_cbc( int x ) {
      return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
              inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
    }
    static bool is_cxb( int x ) {
!     assert(is_cbc(x), "wrong instruction");
      return (x & (1<<21)) != 0;
    }
!   static int cond_cbc( int         x)  { return  u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
!   static int inv_cond_cbc(int      x)  {
!     assert(is_cbc(x), "wrong instruction");
      return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
    }
  
    static int opf_cc(   CC          c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
    static int mov_cc(   CC          c, bool useFloat ) { return u_field(useFloat ? 0 : 1,  18, 18) | u_field(c, 12, 11); }
--- 982,1002 ----
    static int opf_low5( int         w)  { return  u_field(w,              9,  5); }
    static int trapcc(   CC         cc)  { return  u_field(cc,            12, 11); }
    static int sx(       int         i)  { return  u_field(i,             12, 12); } // shift x=1 means 64-bit
    static int opf(      int         x)  { return  u_field(x,             13,  5); }
  
!   static bool is_cbcond( int x ) {
      return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
              inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
    }
    static bool is_cxb( int x ) {
!     assert(is_cbcond(x), "wrong instruction");
      return (x & (1<<21)) != 0;
    }
!   static int cond_cbcond( int         x)  { return  u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
!   static int inv_cond_cbcond(int      x)  {
!     assert(is_cbcond(x), "wrong instruction");
      return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
    }
  
    static int opf_cc(   CC          c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
    static int mov_cc(   CC          c, bool useFloat ) { return u_field(useFloat ? 0 : 1,  18, 18) | u_field(c, 12, 11); }
*** 1049,1059 ****
      return r;
    }
  
    // compute inverse of wdisp10
    static intptr_t inv_wdisp10(int x, intptr_t pos) {
!     assert(is_cbc(x), "wrong instruction");
      int lo = inv_u_field(x, 12, 5);
      int hi = (x >> 19) & 3;
      if (hi >= 2) hi |= ~1;
      return (((hi << 8) | lo) << 2) + pos;
    }
--- 1049,1059 ----
      return r;
    }
  
    // compute inverse of wdisp10
    static intptr_t inv_wdisp10(int x, intptr_t pos) {
!     assert(is_cbcond(x), "wrong instruction");
      int lo = inv_u_field(x, 12, 5);
      int hi = (x >> 19) & 3;
      if (hi >= 2) hi |= ~1;
      return (((hi << 8) | lo) << 2) + pos;
    }
*** 1063,1074 ****
      assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
      intptr_t xx = x - off;
      assert_signed_word_disp_range(xx, 10);
      int r =  ( ( (xx >>  2   ) & ((1 << 8) - 1) ) <<  5 )
             | ( ( (xx >> (2+8)) & 3              ) << 19 );
!     // Have to fake cbc instruction to pass assert in inv_wdisp10()
!     assert(inv_wdisp10((r | op(branch_op) | cond_cbc(rc_last+1) | op2(bpr_op2)), off) == x,  "inverse is not inverse");
      return r;
    }
  
    // word displacement in low-order nbits bits
  
--- 1063,1074 ----
      assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
      intptr_t xx = x - off;
      assert_signed_word_disp_range(xx, 10);
      int r =  ( ( (xx >>  2   ) & ((1 << 8) - 1) ) <<  5 )
             | ( ( (xx >> (2+8)) & 3              ) << 19 );
!     // Have to fake cbcond instruction to pass assert in inv_wdisp10()
!     assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x,  "inverse is not inverse");
      return r;
    }
  
    // word displacement in low-order nbits bits
  
*** 1180,1201 ****
      delay_state = at_delay_slot;
  #endif
    }
  
    // cbcond instruction should not be generated one after an other
!   bool cbc_before() {
      if (offset() == 0) return false; // it is first instruction
      int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
!     return is_cbc(x);
    }
  
!   void no_cbc_before() {
!     assert(offset() == 0 || !cbc_before(), "cbcond should not follow an other cbcond");
    }
  
!   bool use_cbc(Label& L) {
!     if (!UseCBCond || cbc_before()) return false;
      intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
      assert( (x & 3) == 0, "not word aligned");
      return is_simm(x, 12);
    }
  
--- 1180,1201 ----
      delay_state = at_delay_slot;
  #endif
    }
  
    // cbcond instruction should not be generated one after an other
!   bool cbcond_before() {
      if (offset() == 0) return false; // it is first instruction
      int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
!     return is_cbcond(x);
    }
  
!   void no_cbcond_before() {
!     assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
    }
  
!   bool use_cbcond(Label& L) {
!     if (!UseCBCond || cbcond_before()) return false;
      intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
      assert( (x & 3) == 0, "not word aligned");
      return is_simm(x, 12);
    }
  
*** 1274,1285 ****
  
    inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
    inline void cb( Condition c, bool a, Label& L );
  
    // compare and branch
!   inline void cbc(Condition c, CC cc, Register s1, Register s2, Label& L);
!   inline void cbc(Condition c, CC cc, Register s1, int simm5, Label& L);
  
    // pp 149
  
    inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
    inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
--- 1274,1285 ----
  
    inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
    inline void cb( Condition c, bool a, Label& L );
  
    // compare and branch
!   inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
!   inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
  
    // pp 149
  
    inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
    inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
*** 1927,1937 ****
  
    inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
    inline void fb( Condition c, bool a, Predict p, Label& L );
  
    // compares register with zero (32 bit) and branches (V9 and V8 instructions)
!   void br_zero   ( Register s1, Label& L );
    // Compares a pointer register with zero and branches on (not)null.
    // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
    void br_null   ( Register s1, bool a, Predict p, Label& L, bool emit_delayed_nop = true );
    void br_notnull( Register s1, bool a, Predict p, Label& L, bool emit_delayed_nop = true );
  
--- 1927,1937 ----
  
    inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
    inline void fb( Condition c, bool a, Predict p, Label& L );
  
    // compares register with zero (32 bit) and branches (V9 and V8 instructions)
!   void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
    // Compares a pointer register with zero and branches on (not)null.
    // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
    void br_null   ( Register s1, bool a, Predict p, Label& L, bool emit_delayed_nop = true );
    void br_notnull( Register s1, bool a, Predict p, Label& L, bool emit_delayed_nop = true );
  
*** 1939,1964 ****
    // this is what the routine above was meant to do, but it didn't (and
    // didn't cover both target address kinds.)
    void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
    void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L, bool emit_delayed_nop = true );
  
    // Compare registers and branch with nop in delay slot or cbcond without delay slot.
!   void cmp_and_br(Register s1, Register s2, Condition c, bool a, Predict p, Label& L);
!   void cmp_and_br(Register s1, int simm13a, Condition c, bool a, Predict p, Label& L);
!   // Platform depending version
!   void cmp_and_brx(Register s1, Register s2, Condition c, bool a, Predict p, Label& L);
!   void cmp_and_brx(Register s1, int simm13a, Condition c, bool a, Predict p, Label& L);
  
    inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
    inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
  
    // Branch that tests xcc in LP64 and icc in !LP64
    inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
    inline void brx( Condition c, bool a, Predict p, Label& L );
  
!   // unconditional short branch
!   inline void ba( Label& L, bool emit_delayed_nop = true );
  
    // Branch that tests fp condition codes
    inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
    inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
  
--- 1939,1977 ----
    // this is what the routine above was meant to do, but it didn't (and
    // didn't cover both target address kinds.)
    void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
    void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L, bool emit_delayed_nop = true );
  
+   //
    // Compare registers and branch with nop in delay slot or cbcond without delay slot.
!   //
!   // ATTENTION: use these instructions with caution because cbcond instruction
!   //            has very short distance: 512 instructions (2Kbyte).
  
+   // Compare integer (32 bit) values (icc only).
+   void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
+   void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
+   // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64).
+   void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
+   void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
+ 
+   // Short branch version for compares a pointer pwith zero.
+   void br_null_short   ( Register s1, Predict p, Label& L );
+   void br_notnull_short( Register s1, Predict p, Label& L );
+ 
+   // unconditional short branch
+   void ba_short(Label& L);
+ 
    inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
    inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
  
    // Branch that tests xcc in LP64 and icc in !LP64
    inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
    inline void brx( Condition c, bool a, Predict p, Label& L );
  
!   // unconditional branch
!   inline void ba( Label& L );
  
    // Branch that tests fp condition codes
    inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
    inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );