src/cpu/sparc/vm/assembler_sparc.inline.hpp
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src/cpu/sparc/vm/assembler_sparc.inline.hpp

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  82 
  83 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only();  cti();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt);  has_delay_slot(); }
  84 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }
  85 
  86 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();  cti();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
  87 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }
  88 
  89 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  cti();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }
  90 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }
  91 
  92 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only();  cti();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
  93 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }
  94 
  95 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();  cti();   emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
  96 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }
  97 
  98 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  cti();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }
  99 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }
 100 
 101 // compare and branch
 102 inline void Assembler::cbc(Condition c, CC cc, Register s1, Register s2, Label& L) { cti();  no_cbc_before();  emit_data(op(branch_op) | cond_cbc(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2)); }
 103 inline void Assembler::cbc(Condition c, CC cc, Register s1, int simm5, Label& L)   { cti();  no_cbc_before();  emit_data(op(branch_op) | cond_cbc(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5)); }
 104 
 105 inline void Assembler::call( address d,  relocInfo::relocType rt ) { cti();  emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt);  has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
 106 inline void Assembler::call( Label& L,   relocInfo::relocType rt ) { call( target(L), rt); }
 107 
 108 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
 109 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 110 
 111 inline void Assembler::jmpl( Register s1, Register s2, Register d ) { cti();  emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2));  has_delay_slot(); }
 112 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { cti();  emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec);  has_delay_slot(); }
 113 
 114 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d) {
 115   if (s2.is_register()) ldf(w, s1, s2.as_register(), d);
 116   else                  ldf(w, s1, s2.as_constant(), d);
 117 }
 118 
 119 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
 120 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); }
 121 
 122 inline void Assembler::ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }
 123 


 544 
 545 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
 546   br(c, a, p, target(L));
 547 }
 548 
 549 
 550 // Branch that tests either xcc or icc depending on the
 551 // architecture compiled (LP64 or not)
 552 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 553 #ifdef _LP64
 554     Assembler::bp(c, a, xcc, p, d, rt);
 555 #else
 556     MacroAssembler::br(c, a, p, d, rt);
 557 #endif
 558 }
 559 
 560 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
 561   brx(c, a, p, target(L));
 562 }
 563 
 564 inline void MacroAssembler::ba( Label& L, bool emit_delayed_nop ) {
 565   if (emit_delayed_nop && use_cbc(L)) {
 566     Assembler::cbc(equal, icc, G0, G0, L);
 567     return;
 568   }
 569   br(always, false, pt, L);
 570   // Some callers can fill the delay slot.
 571   if (emit_delayed_nop) {
 572     delayed()->nop();
 573   }
 574 }
 575 
 576 // Warning: V9 only functions
 577 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
 578   Assembler::bp(c, a, cc, p, d, rt);
 579 }
 580 
 581 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
 582   Assembler::bp(c, a, cc, p, L);
 583 }
 584 
 585 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 586   if (VM_Version::v9_instructions_work())
 587     fbp(c, a, fcc0, p, d, rt);
 588   else
 589     Assembler::fb(c, a, d, rt);
 590 }
 591 
 592 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
 593   fb(c, a, p, target(L));




  82 
  83 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only();  cti();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt);  has_delay_slot(); }
  84 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }
  85 
  86 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();  cti();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
  87 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }
  88 
  89 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  cti();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }
  90 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }
  91 
  92 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only();  cti();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
  93 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }
  94 
  95 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();  cti();   emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
  96 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }
  97 
  98 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  cti();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }
  99 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }
 100 
 101 // compare and branch
 102 inline void Assembler::cbcond(Condition c, CC cc, Register s1, Register s2, Label& L) { cti();  no_cbcond_before();  emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2)); }
 103 inline void Assembler::cbcond(Condition c, CC cc, Register s1, int simm5, Label& L)   { cti();  no_cbcond_before();  emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5)); }
 104 
 105 inline void Assembler::call( address d,  relocInfo::relocType rt ) { cti();  emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt);  has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
 106 inline void Assembler::call( Label& L,   relocInfo::relocType rt ) { call( target(L), rt); }
 107 
 108 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
 109 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 110 
 111 inline void Assembler::jmpl( Register s1, Register s2, Register d ) { cti();  emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2));  has_delay_slot(); }
 112 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { cti();  emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec);  has_delay_slot(); }
 113 
 114 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d) {
 115   if (s2.is_register()) ldf(w, s1, s2.as_register(), d);
 116   else                  ldf(w, s1, s2.as_constant(), d);
 117 }
 118 
 119 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
 120 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); }
 121 
 122 inline void Assembler::ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }
 123 


 544 
 545 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
 546   br(c, a, p, target(L));
 547 }
 548 
 549 
 550 // Branch that tests either xcc or icc depending on the
 551 // architecture compiled (LP64 or not)
 552 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 553 #ifdef _LP64
 554     Assembler::bp(c, a, xcc, p, d, rt);
 555 #else
 556     MacroAssembler::br(c, a, p, d, rt);
 557 #endif
 558 }
 559 
 560 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
 561   brx(c, a, p, target(L));
 562 }
 563 
 564 inline void MacroAssembler::ba( Label& L ) {




 565   br(always, false, pt, L);




 566 }
 567 
 568 // Warning: V9 only functions
 569 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
 570   Assembler::bp(c, a, cc, p, d, rt);
 571 }
 572 
 573 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
 574   Assembler::bp(c, a, cc, p, L);
 575 }
 576 
 577 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 578   if (VM_Version::v9_instructions_work())
 579     fbp(c, a, fcc0, p, d, rt);
 580   else
 581     Assembler::fb(c, a, d, rt);
 582 }
 583 
 584 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
 585   fb(c, a, p, target(L));


src/cpu/sparc/vm/assembler_sparc.inline.hpp
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