--- old/src/cpu/sparc/vm/interpreter_sparc.cpp	Fri Jul 15 19:09:46 2011
+++ new/src/cpu/sparc/vm/interpreter_sparc.cpp	Fri Jul 15 19:09:46 2011
@@ -191,19 +191,19 @@
     // Optimization, see if there are any more args and get out prior to checking
     // all 16 float registers.  My guess is that this is rare.
     // If is_register is false, then we are done the first six integer args.
-      __ br_null(G4_scratch, false, Assembler::pt, done);
+      __ br_null_short(G4_scratch, Assembler::pt, done);
     }
-    __ ba(NextArg, false);
+    __ ba(NextArg);
     __ delayed()->srl( G4_scratch, 2, G4_scratch );
 
     __ bind(LoadFloatArg);
     __ ldf( FloatRegisterImpl::S, a, ldarg.as_float_register(), 4);
-    __ ba(NextArg, false);
+    __ ba(NextArg);
     __ delayed()->srl( G4_scratch, 2, G4_scratch );
 
     __ bind(LoadDoubleArg);
     __ ldf( FloatRegisterImpl::D, a, ldarg.as_double_register() );
-    __ ba(NextArg, false);
+    __ ba(NextArg);
     __ delayed()->srl( G4_scratch, 2, G4_scratch );
 
     __ bind(NextArg);
@@ -231,7 +231,7 @@
   __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::frequency_counter_overflow), O2, O2, true);
   // returns verified_entry_point or NULL
   // we ignore it in any case
-  __ ba(Lcontinue);
+  __ ba_short(Lcontinue);
 
 }