1 //
2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // Block initializing store
475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2
476
477 // tertiary op of a LoadP or StoreP encoding
478 #define REGP_OP true
479
480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
482 static Register reg_to_register_object(int register_encoding);
483
484 // Used by the DFA in dfa_sparc.cpp.
485 // Check for being able to use a V9 branch-on-register. Requires a
486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
487 // extended. Doesn't work following an integer ADD, for example, because of
488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
490 // replace them with zero, which could become sign-extension in a different OS
491 // release. There's no obvious reason why an interrupt will ever fill these
492 // bits with non-zero junk (the registers are reloaded with standard LD
493 // instructions which either zero-fill or sign-fill).
494 bool can_branch_register( Node *bol, Node *cmp ) {
495 if( !BranchOnRegister ) return false;
496 #ifdef _LP64
497 if( cmp->Opcode() == Op_CmpP )
498 return true; // No problems with pointer compares
499 #endif
500 if( cmp->Opcode() == Op_CmpL )
501 return true; // No problems with long compares
502
503 if( !SparcV9RegsHiBitsZero ) return false;
504 if( bol->as_Bool()->_test._test != BoolTest::ne &&
505 bol->as_Bool()->_test._test != BoolTest::eq )
506 return false;
507
508 // Check for comparing against a 'safe' value. Any operation which
509 // clears out the high word is safe. Thus, loads and certain shifts
510 // are safe, as are non-negative constants. Any operation which
511 // preserves zero bits in the high word is safe as long as each of its
512 // inputs are safe. Thus, phis and bitwise booleans are safe if their
513 // inputs are safe. At present, the only important case to recognize
514 // seems to be loads. Constants should fold away, and shifts &
515 // logicals can use the 'cc' forms.
516 Node *x = cmp->in(1);
517 if( x->is_Load() ) return true;
518 if( x->is_Phi() ) {
519 for( uint i = 1; i < x->req(); i++ )
520 if( !x->in(i)->is_Load() )
521 return false;
522 return true;
523 }
524 return false;
525 }
526
527 // ****************************************************************************
528
529 // REQUIRED FUNCTIONALITY
530
531 // !!!!! Special hack to get all type of calls to specify the byte offset
532 // from the start of the call to the point where the return address
533 // will point.
534 // The "return address" is the address of the call instruction, plus 8.
535
536 int MachCallStaticJavaNode::ret_addr_offset() {
537 int offset = NativeCall::instruction_size; // call; delay slot
538 if (_method_handle_invoke)
539 offset += 4; // restore SP
540 return offset;
541 }
542
543 int MachCallDynamicJavaNode::ret_addr_offset() {
544 int vtable_index = this->_vtable_index;
545 if (vtable_index < 0) {
546 // must be invalid_vtable_index, not nonvirtual_vtable_index
547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
548 return (NativeMovConstReg::instruction_size +
549 NativeCall::instruction_size); // sethi; setlo; call; delay slot
550 } else {
551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
554 int klass_load_size;
555 if (UseCompressedOops) {
556 assert(Universe::heap() != NULL, "java heap should be initialized");
557 if (Universe::narrow_oop_base() == NULL)
558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
559 else
560 klass_load_size = 3*BytesPerInstWord;
561 } else {
562 klass_load_size = 1*BytesPerInstWord;
563 }
564 if( Assembler::is_simm13(v_off) ) {
565 return klass_load_size +
566 (2*BytesPerInstWord + // ld_ptr, ld_ptr
567 NativeCall::instruction_size); // call; delay slot
568 } else {
569 return klass_load_size +
570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
571 NativeCall::instruction_size); // call; delay slot
572 }
573 }
574 }
575
576 int MachCallRuntimeNode::ret_addr_offset() {
577 #ifdef _LP64
578 if (MacroAssembler::is_far_target(entry_point())) {
579 return NativeFarCall::instruction_size;
580 } else {
581 return NativeCall::instruction_size;
582 }
583 #else
584 return NativeCall::instruction_size; // call; delay slot
585 #endif
586 }
587
588 // Indicate if the safepoint node needs the polling page as an input.
589 // Since Sparc does not have absolute addressing, it does.
590 bool SafePointNode::needs_polling_address_input() {
591 return true;
592 }
593
594 // emit an interrupt that is caught by the debugger (for debugging compiler)
595 void emit_break(CodeBuffer &cbuf) {
596 MacroAssembler _masm(&cbuf);
597 __ breakpoint_trap();
598 }
599
600 #ifndef PRODUCT
601 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
602 st->print("TA");
603 }
604 #endif
605
606 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
607 emit_break(cbuf);
608 }
609
610 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
611 return MachNode::size(ra_);
612 }
613
614 // Traceable jump
615 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
616 MacroAssembler _masm(&cbuf);
617 Register rdest = reg_to_register_object(jump_target);
618 __ JMP(rdest, 0);
619 __ delayed()->nop();
620 }
621
622 // Traceable jump and set exception pc
623 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
624 MacroAssembler _masm(&cbuf);
625 Register rdest = reg_to_register_object(jump_target);
626 __ JMP(rdest, 0);
627 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
628 }
629
630 void emit_nop(CodeBuffer &cbuf) {
631 MacroAssembler _masm(&cbuf);
632 __ nop();
633 }
634
635 void emit_illtrap(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ illtrap(0);
638 }
639
640
641 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
642 assert(n->rule() != loadUB_rule, "");
643
644 intptr_t offset = 0;
645 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
646 const Node* addr = n->get_base_and_disp(offset, adr_type);
647 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
648 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
649 assert(addr->bottom_type()->isa_oopptr() == atype, "");
650 atype = atype->add_offset(offset);
651 assert(disp32 == offset, "wrong disp32");
652 return atype->_offset;
653 }
654
655
656 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
657 assert(n->rule() != loadUB_rule, "");
658
659 intptr_t offset = 0;
660 Node* addr = n->in(2);
661 assert(addr->bottom_type()->isa_oopptr() == atype, "");
662 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
663 Node* a = addr->in(2/*AddPNode::Address*/);
664 Node* o = addr->in(3/*AddPNode::Offset*/);
665 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
666 atype = a->bottom_type()->is_ptr()->add_offset(offset);
667 assert(atype->isa_oop_ptr(), "still an oop");
668 }
669 offset = atype->is_ptr()->_offset;
670 if (offset != Type::OffsetBot) offset += disp32;
671 return offset;
672 }
673
674 static inline jdouble replicate_immI(int con, int count, int width) {
675 // Load a constant replicated "count" times with width "width"
676 int bit_width = width * 8;
677 jlong elt_val = con;
678 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
679 jlong val = elt_val;
680 for (int i = 0; i < count - 1; i++) {
681 val <<= bit_width;
682 val |= elt_val;
683 }
684 jdouble dval = *((jdouble*) &val); // coerce to double type
685 return dval;
686 }
687
688 // Standard Sparc opcode form2 field breakdown
689 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
690 f0 &= (1<<19)-1; // Mask displacement to 19 bits
691 int op = (f30 << 30) |
692 (f29 << 29) |
693 (f25 << 25) |
694 (f22 << 22) |
695 (f20 << 20) |
696 (f19 << 19) |
697 (f0 << 0);
698 cbuf.insts()->emit_int32(op);
699 }
700
701 // Standard Sparc opcode form2 field breakdown
702 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
703 f0 >>= 10; // Drop 10 bits
704 f0 &= (1<<22)-1; // Mask displacement to 22 bits
705 int op = (f30 << 30) |
706 (f25 << 25) |
707 (f22 << 22) |
708 (f0 << 0);
709 cbuf.insts()->emit_int32(op);
710 }
711
712 // Standard Sparc opcode form3 field breakdown
713 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
714 int op = (f30 << 30) |
715 (f25 << 25) |
716 (f19 << 19) |
717 (f14 << 14) |
718 (f5 << 5) |
719 (f0 << 0);
720 cbuf.insts()->emit_int32(op);
721 }
722
723 // Standard Sparc opcode form3 field breakdown
724 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
725 simm13 &= (1<<13)-1; // Mask to 13 bits
726 int op = (f30 << 30) |
727 (f25 << 25) |
728 (f19 << 19) |
729 (f14 << 14) |
730 (1 << 13) | // bit to indicate immediate-mode
731 (simm13<<0);
732 cbuf.insts()->emit_int32(op);
733 }
734
735 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
736 simm10 &= (1<<10)-1; // Mask to 10 bits
737 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
738 }
739
740 #ifdef ASSERT
741 // Helper function for VerifyOops in emit_form3_mem_reg
742 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
743 warning("VerifyOops encountered unexpected instruction:");
744 n->dump(2);
745 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
746 }
747 #endif
748
749
750 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
751 int src1_enc, int disp32, int src2_enc, int dst_enc) {
752
753 #ifdef ASSERT
754 // The following code implements the +VerifyOops feature.
755 // It verifies oop values which are loaded into or stored out of
756 // the current method activation. +VerifyOops complements techniques
757 // like ScavengeALot, because it eagerly inspects oops in transit,
758 // as they enter or leave the stack, as opposed to ScavengeALot,
759 // which inspects oops "at rest", in the stack or heap, at safepoints.
760 // For this reason, +VerifyOops can sometimes detect bugs very close
761 // to their point of creation. It can also serve as a cross-check
762 // on the validity of oop maps, when used toegether with ScavengeALot.
763
764 // It would be good to verify oops at other points, especially
765 // when an oop is used as a base pointer for a load or store.
766 // This is presently difficult, because it is hard to know when
767 // a base address is biased or not. (If we had such information,
768 // it would be easy and useful to make a two-argument version of
769 // verify_oop which unbiases the base, and performs verification.)
770
771 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
772 bool is_verified_oop_base = false;
773 bool is_verified_oop_load = false;
774 bool is_verified_oop_store = false;
775 int tmp_enc = -1;
776 if (VerifyOops && src1_enc != R_SP_enc) {
777 // classify the op, mainly for an assert check
778 int st_op = 0, ld_op = 0;
779 switch (primary) {
780 case Assembler::stb_op3: st_op = Op_StoreB; break;
781 case Assembler::sth_op3: st_op = Op_StoreC; break;
782 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
783 case Assembler::stw_op3: st_op = Op_StoreI; break;
784 case Assembler::std_op3: st_op = Op_StoreL; break;
785 case Assembler::stf_op3: st_op = Op_StoreF; break;
786 case Assembler::stdf_op3: st_op = Op_StoreD; break;
787
788 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
789 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
790 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
791 case Assembler::ldx_op3: // may become LoadP or stay LoadI
792 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
793 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
794 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
795 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
796 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
797 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
798 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
799
800 default: ShouldNotReachHere();
801 }
802 if (tertiary == REGP_OP) {
803 if (st_op == Op_StoreI) st_op = Op_StoreP;
804 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
805 else ShouldNotReachHere();
806 if (st_op) {
807 // a store
808 // inputs are (0:control, 1:memory, 2:address, 3:value)
809 Node* n2 = n->in(3);
810 if (n2 != NULL) {
811 const Type* t = n2->bottom_type();
812 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
813 }
814 } else {
815 // a load
816 const Type* t = n->bottom_type();
817 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
818 }
819 }
820
821 if (ld_op) {
822 // a Load
823 // inputs are (0:control, 1:memory, 2:address)
824 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
825 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
826 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
827 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
828 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
829 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
830 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
831 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
832 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
833 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
834 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
835 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
836 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
839 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
840 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
841 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
842 !(n->rule() == loadUB_rule)) {
843 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
844 }
845 } else if (st_op) {
846 // a Store
847 // inputs are (0:control, 1:memory, 2:address, 3:value)
848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
853 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
854 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
855 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
856 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
857 verify_oops_warning(n, n->ideal_Opcode(), st_op);
858 }
859 }
860
861 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
862 Node* addr = n->in(2);
863 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
864 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
865 if (atype != NULL) {
866 intptr_t offset = get_offset_from_base(n, atype, disp32);
867 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
868 if (offset != offset_2) {
869 get_offset_from_base(n, atype, disp32);
870 get_offset_from_base_2(n, atype, disp32);
871 }
872 assert(offset == offset_2, "different offsets");
873 if (offset == disp32) {
874 // we now know that src1 is a true oop pointer
875 is_verified_oop_base = true;
876 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
877 if( primary == Assembler::ldd_op3 ) {
878 is_verified_oop_base = false; // Cannot 'ldd' into O7
879 } else {
880 tmp_enc = dst_enc;
881 dst_enc = R_O7_enc; // Load into O7; preserve source oop
882 assert(src1_enc != dst_enc, "");
883 }
884 }
885 }
886 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
887 || offset == oopDesc::mark_offset_in_bytes())) {
888 // loading the mark should not be allowed either, but
889 // we don't check this since it conflicts with InlineObjectHash
890 // usage of LoadINode to get the mark. We could keep the
891 // check if we create a new LoadMarkNode
892 // but do not verify the object before its header is initialized
893 ShouldNotReachHere();
894 }
895 }
896 }
897 }
898 }
899 #endif
900
901 uint instr;
902 instr = (Assembler::ldst_op << 30)
903 | (dst_enc << 25)
904 | (primary << 19)
905 | (src1_enc << 14);
906
907 uint index = src2_enc;
908 int disp = disp32;
909
910 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
911 disp += STACK_BIAS;
912
913 // We should have a compiler bailout here rather than a guarantee.
914 // Better yet would be some mechanism to handle variable-size matches correctly.
915 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
916
917 if( disp == 0 ) {
918 // use reg-reg form
919 // bit 13 is already zero
920 instr |= index;
921 } else {
922 // use reg-imm form
923 instr |= 0x00002000; // set bit 13 to one
924 instr |= disp & 0x1FFF;
925 }
926
927 cbuf.insts()->emit_int32(instr);
928
929 #ifdef ASSERT
930 {
931 MacroAssembler _masm(&cbuf);
932 if (is_verified_oop_base) {
933 __ verify_oop(reg_to_register_object(src1_enc));
934 }
935 if (is_verified_oop_store) {
936 __ verify_oop(reg_to_register_object(dst_enc));
937 }
938 if (tmp_enc != -1) {
939 __ mov(O7, reg_to_register_object(tmp_enc));
940 }
941 if (is_verified_oop_load) {
942 __ verify_oop(reg_to_register_object(dst_enc));
943 }
944 }
945 #endif
946 }
947
948 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
949 // The method which records debug information at every safepoint
950 // expects the call to be the first instruction in the snippet as
951 // it creates a PcDesc structure which tracks the offset of a call
952 // from the start of the codeBlob. This offset is computed as
953 // code_end() - code_begin() of the code which has been emitted
954 // so far.
955 // In this particular case we have skirted around the problem by
956 // putting the "mov" instruction in the delay slot but the problem
957 // may bite us again at some other point and a cleaner/generic
958 // solution using relocations would be needed.
959 MacroAssembler _masm(&cbuf);
960 __ set_inst_mark();
961
962 // We flush the current window just so that there is a valid stack copy
963 // the fact that the current window becomes active again instantly is
964 // not a problem there is nothing live in it.
965
966 #ifdef ASSERT
967 int startpos = __ offset();
968 #endif /* ASSERT */
969
970 __ call((address)entry_point, rtype);
971
972 if (preserve_g2) __ delayed()->mov(G2, L7);
973 else __ delayed()->nop();
974
975 if (preserve_g2) __ mov(L7, G2);
976
977 #ifdef ASSERT
978 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
979 #ifdef _LP64
980 // Trash argument dump slots.
981 __ set(0xb0b8ac0db0b8ac0d, G1);
982 __ mov(G1, G5);
983 __ stx(G1, SP, STACK_BIAS + 0x80);
984 __ stx(G1, SP, STACK_BIAS + 0x88);
985 __ stx(G1, SP, STACK_BIAS + 0x90);
986 __ stx(G1, SP, STACK_BIAS + 0x98);
987 __ stx(G1, SP, STACK_BIAS + 0xA0);
988 __ stx(G1, SP, STACK_BIAS + 0xA8);
989 #else // _LP64
990 // this is also a native call, so smash the first 7 stack locations,
991 // and the various registers
992
993 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
994 // while [SP+0x44..0x58] are the argument dump slots.
995 __ set((intptr_t)0xbaadf00d, G1);
996 __ mov(G1, G5);
997 __ sllx(G1, 32, G1);
998 __ or3(G1, G5, G1);
999 __ mov(G1, G5);
1000 __ stx(G1, SP, 0x40);
1001 __ stx(G1, SP, 0x48);
1002 __ stx(G1, SP, 0x50);
1003 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1004 #endif // _LP64
1005 }
1006 #endif /*ASSERT*/
1007 }
1008
1009 //=============================================================================
1010 // REQUIRED FUNCTIONALITY for encoding
1011 void emit_lo(CodeBuffer &cbuf, int val) { }
1012 void emit_hi(CodeBuffer &cbuf, int val) { }
1013
1014
1015 //=============================================================================
1016 const bool Matcher::constant_table_absolute_addressing = false;
1017 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
1018
1019 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1020 Compile* C = ra_->C;
1021 Compile::ConstantTable& constant_table = C->constant_table();
1022 MacroAssembler _masm(&cbuf);
1023
1024 Register r = as_Register(ra_->get_encode(this));
1025 CodeSection* cs = __ code()->consts();
1026 int consts_size = cs->align_at_start(cs->size());
1027
1028 if (UseRDPCForConstantTableBase) {
1029 // For the following RDPC logic to work correctly the consts
1030 // section must be allocated right before the insts section. This
1031 // assert checks for that. The layout and the SECT_* constants
1032 // are defined in src/share/vm/asm/codeBuffer.hpp.
1033 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1034 int offset = __ offset();
1035 int disp;
1036
1037 // If the displacement from the current PC to the constant table
1038 // base fits into simm13 we set the constant table base to the
1039 // current PC.
1040 if (__ is_simm13(-(consts_size + offset))) {
1041 constant_table.set_table_base_offset(-(consts_size + offset));
1042 disp = 0;
1043 } else {
1044 // If the offset of the top constant (last entry in the table)
1045 // fits into simm13 we set the constant table base to the actual
1046 // table base.
1047 if (__ is_simm13(constant_table.top_offset())) {
1048 constant_table.set_table_base_offset(0);
1049 disp = consts_size + offset;
1050 } else {
1051 // Otherwise we set the constant table base in the middle of the
1052 // constant table.
1053 int half_consts_size = consts_size / 2;
1054 assert(half_consts_size * 2 == consts_size, "sanity");
1055 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement.
1056 disp = half_consts_size + offset;
1057 }
1058 }
1059
1060 __ rdpc(r);
1061
1062 if (disp != 0) {
1063 assert(r != O7, "need temporary");
1064 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1065 }
1066 }
1067 else {
1068 // Materialize the constant table base.
1069 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1070 address baseaddr = cs->start() + -(constant_table.table_base_offset());
1071 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1072 AddressLiteral base(baseaddr, rspec);
1073 __ set(base, r);
1074 }
1075 }
1076
1077 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1078 if (UseRDPCForConstantTableBase) {
1079 // This is really the worst case but generally it's only 1 instruction.
1080 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1081 } else {
1082 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1083 }
1084 }
1085
1086 #ifndef PRODUCT
1087 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1088 char reg[128];
1089 ra_->dump_register(this, reg);
1090 if (UseRDPCForConstantTableBase) {
1091 st->print("RDPC %s\t! constant table base", reg);
1092 } else {
1093 st->print("SET &constanttable,%s\t! constant table base", reg);
1094 }
1095 }
1096 #endif
1097
1098
1099 //=============================================================================
1100
1101 #ifndef PRODUCT
1102 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1103 Compile* C = ra_->C;
1104
1105 for (int i = 0; i < OptoPrologueNops; i++) {
1106 st->print_cr("NOP"); st->print("\t");
1107 }
1108
1109 if( VerifyThread ) {
1110 st->print_cr("Verify_Thread"); st->print("\t");
1111 }
1112
1113 size_t framesize = C->frame_slots() << LogBytesPerInt;
1114
1115 // Calls to C2R adapters often do not accept exceptional returns.
1116 // We require that their callers must bang for them. But be careful, because
1117 // some VM calls (such as call site linkage) can use several kilobytes of
1118 // stack. But the stack safety zone should account for that.
1119 // See bugs 4446381, 4468289, 4497237.
1120 if (C->need_stack_bang(framesize)) {
1121 st->print_cr("! stack bang"); st->print("\t");
1122 }
1123
1124 if (Assembler::is_simm13(-framesize)) {
1125 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1126 } else {
1127 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1128 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1129 st->print ("SAVE R_SP,R_G3,R_SP");
1130 }
1131
1132 }
1133 #endif
1134
1135 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1136 Compile* C = ra_->C;
1137 MacroAssembler _masm(&cbuf);
1138
1139 for (int i = 0; i < OptoPrologueNops; i++) {
1140 __ nop();
1141 }
1142
1143 __ verify_thread();
1144
1145 size_t framesize = C->frame_slots() << LogBytesPerInt;
1146 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1147 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1148
1149 // Calls to C2R adapters often do not accept exceptional returns.
1150 // We require that their callers must bang for them. But be careful, because
1151 // some VM calls (such as call site linkage) can use several kilobytes of
1152 // stack. But the stack safety zone should account for that.
1153 // See bugs 4446381, 4468289, 4497237.
1154 if (C->need_stack_bang(framesize)) {
1155 __ generate_stack_overflow_check(framesize);
1156 }
1157
1158 if (Assembler::is_simm13(-framesize)) {
1159 __ save(SP, -framesize, SP);
1160 } else {
1161 __ sethi(-framesize & ~0x3ff, G3);
1162 __ add(G3, -framesize & 0x3ff, G3);
1163 __ save(SP, G3, SP);
1164 }
1165 C->set_frame_complete( __ offset() );
1166 }
1167
1168 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1169 return MachNode::size(ra_);
1170 }
1171
1172 int MachPrologNode::reloc() const {
1173 return 10; // a large enough number
1174 }
1175
1176 //=============================================================================
1177 #ifndef PRODUCT
1178 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1179 Compile* C = ra_->C;
1180
1181 if( do_polling() && ra_->C->is_method_compilation() ) {
1182 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1183 #ifdef _LP64
1184 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1185 #else
1186 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1187 #endif
1188 }
1189
1190 if( do_polling() )
1191 st->print("RET\n\t");
1192
1193 st->print("RESTORE");
1194 }
1195 #endif
1196
1197 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1198 MacroAssembler _masm(&cbuf);
1199 Compile* C = ra_->C;
1200
1201 __ verify_thread();
1202
1203 // If this does safepoint polling, then do it here
1204 if( do_polling() && ra_->C->is_method_compilation() ) {
1205 AddressLiteral polling_page(os::get_polling_page());
1206 __ sethi(polling_page, L0);
1207 __ relocate(relocInfo::poll_return_type);
1208 __ ld_ptr( L0, 0, G0 );
1209 }
1210
1211 // If this is a return, then stuff the restore in the delay slot
1212 if( do_polling() ) {
1213 __ ret();
1214 __ delayed()->restore();
1215 } else {
1216 __ restore();
1217 }
1218 }
1219
1220 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1221 return MachNode::size(ra_);
1222 }
1223
1224 int MachEpilogNode::reloc() const {
1225 return 16; // a large enough number
1226 }
1227
1228 const Pipeline * MachEpilogNode::pipeline() const {
1229 return MachNode::pipeline_class();
1230 }
1231
1232 int MachEpilogNode::safepoint_offset() const {
1233 assert( do_polling(), "no return for this epilog node");
1234 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1235 }
1236
1237 //=============================================================================
1238
1239 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1240 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1241 static enum RC rc_class( OptoReg::Name reg ) {
1242 if( !OptoReg::is_valid(reg) ) return rc_bad;
1243 if (OptoReg::is_stack(reg)) return rc_stack;
1244 VMReg r = OptoReg::as_VMReg(reg);
1245 if (r->is_Register()) return rc_int;
1246 assert(r->is_FloatRegister(), "must be");
1247 return rc_float;
1248 }
1249
1250 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1251 if( cbuf ) {
1252 // Better yet would be some mechanism to handle variable-size matches correctly
1253 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1254 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1255 } else {
1256 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1257 }
1258 }
1259 #ifndef PRODUCT
1260 else if( !do_size ) {
1261 if( size != 0 ) st->print("\n\t");
1262 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1263 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1264 }
1265 #endif
1266 return size+4;
1267 }
1268
1269 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1270 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1271 #ifndef PRODUCT
1272 else if( !do_size ) {
1273 if( size != 0 ) st->print("\n\t");
1274 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1275 }
1276 #endif
1277 return size+4;
1278 }
1279
1280 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1281 PhaseRegAlloc *ra_,
1282 bool do_size,
1283 outputStream* st ) const {
1284 // Get registers to move
1285 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1286 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1287 OptoReg::Name dst_second = ra_->get_reg_second(this );
1288 OptoReg::Name dst_first = ra_->get_reg_first(this );
1289
1290 enum RC src_second_rc = rc_class(src_second);
1291 enum RC src_first_rc = rc_class(src_first);
1292 enum RC dst_second_rc = rc_class(dst_second);
1293 enum RC dst_first_rc = rc_class(dst_first);
1294
1295 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1296
1297 // Generate spill code!
1298 int size = 0;
1299
1300 if( src_first == dst_first && src_second == dst_second )
1301 return size; // Self copy, no move
1302
1303 // --------------------------------------
1304 // Check for mem-mem move. Load into unused float registers and fall into
1305 // the float-store case.
1306 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1307 int offset = ra_->reg2offset(src_first);
1308 // Further check for aligned-adjacent pair, so we can use a double load
1309 if( (src_first&1)==0 && src_first+1 == src_second ) {
1310 src_second = OptoReg::Name(R_F31_num);
1311 src_second_rc = rc_float;
1312 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1313 } else {
1314 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1315 }
1316 src_first = OptoReg::Name(R_F30_num);
1317 src_first_rc = rc_float;
1318 }
1319
1320 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1321 int offset = ra_->reg2offset(src_second);
1322 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1323 src_second = OptoReg::Name(R_F31_num);
1324 src_second_rc = rc_float;
1325 }
1326
1327 // --------------------------------------
1328 // Check for float->int copy; requires a trip through memory
1329 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1330 int offset = frame::register_save_words*wordSize;
1331 if (cbuf) {
1332 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1333 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1334 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1335 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1336 }
1337 #ifndef PRODUCT
1338 else if (!do_size) {
1339 if (size != 0) st->print("\n\t");
1340 st->print( "SUB R_SP,16,R_SP\n");
1341 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1342 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1343 st->print("\tADD R_SP,16,R_SP\n");
1344 }
1345 #endif
1346 size += 16;
1347 }
1348
1349 // Check for float->int copy on T4
1350 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1351 // Further check for aligned-adjacent pair, so we can use a double move
1352 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1353 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1354 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1355 }
1356 // Check for int->float copy on T4
1357 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1358 // Further check for aligned-adjacent pair, so we can use a double move
1359 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1360 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1361 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1362 }
1363
1364 // --------------------------------------
1365 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1366 // In such cases, I have to do the big-endian swap. For aligned targets, the
1367 // hardware does the flop for me. Doubles are always aligned, so no problem
1368 // there. Misaligned sources only come from native-long-returns (handled
1369 // special below).
1370 #ifndef _LP64
1371 if( src_first_rc == rc_int && // source is already big-endian
1372 src_second_rc != rc_bad && // 64-bit move
1373 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1374 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1375 // Do the big-endian flop.
1376 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1377 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1378 }
1379 #endif
1380
1381 // --------------------------------------
1382 // Check for integer reg-reg copy
1383 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1384 #ifndef _LP64
1385 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1386 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1387 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1388 // operand contains the least significant word of the 64-bit value and vice versa.
1389 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1390 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1391 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1392 if( cbuf ) {
1393 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1394 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1395 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1396 #ifndef PRODUCT
1397 } else if( !do_size ) {
1398 if( size != 0 ) st->print("\n\t");
1399 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1400 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1401 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1402 #endif
1403 }
1404 return size+12;
1405 }
1406 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1407 // returning a long value in I0/I1
1408 // a SpillCopy must be able to target a return instruction's reg_class
1409 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1410 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1411 // operand contains the least significant word of the 64-bit value and vice versa.
1412 OptoReg::Name tdest = dst_first;
1413
1414 if (src_first == dst_first) {
1415 tdest = OptoReg::Name(R_O7_num);
1416 size += 4;
1417 }
1418
1419 if( cbuf ) {
1420 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1421 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1422 // ShrL_reg_imm6
1423 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1424 // ShrR_reg_imm6 src, 0, dst
1425 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1426 if (tdest != dst_first) {
1427 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1428 }
1429 }
1430 #ifndef PRODUCT
1431 else if( !do_size ) {
1432 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1433 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1434 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1435 if (tdest != dst_first) {
1436 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1437 }
1438 }
1439 #endif // PRODUCT
1440 return size+8;
1441 }
1442 #endif // !_LP64
1443 // Else normal reg-reg copy
1444 assert( src_second != dst_first, "smashed second before evacuating it" );
1445 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1446 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1447 // This moves an aligned adjacent pair.
1448 // See if we are done.
1449 if( src_first+1 == src_second && dst_first+1 == dst_second )
1450 return size;
1451 }
1452
1453 // Check for integer store
1454 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1455 int offset = ra_->reg2offset(dst_first);
1456 // Further check for aligned-adjacent pair, so we can use a double store
1457 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1458 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1459 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1460 }
1461
1462 // Check for integer load
1463 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1464 int offset = ra_->reg2offset(src_first);
1465 // Further check for aligned-adjacent pair, so we can use a double load
1466 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1467 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1468 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1469 }
1470
1471 // Check for float reg-reg copy
1472 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1473 // Further check for aligned-adjacent pair, so we can use a double move
1474 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1475 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1476 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1477 }
1478
1479 // Check for float store
1480 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1481 int offset = ra_->reg2offset(dst_first);
1482 // Further check for aligned-adjacent pair, so we can use a double store
1483 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1484 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1485 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1486 }
1487
1488 // Check for float load
1489 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1490 int offset = ra_->reg2offset(src_first);
1491 // Further check for aligned-adjacent pair, so we can use a double load
1492 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1493 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1494 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1495 }
1496
1497 // --------------------------------------------------------------------
1498 // Check for hi bits still needing moving. Only happens for misaligned
1499 // arguments to native calls.
1500 if( src_second == dst_second )
1501 return size; // Self copy; no move
1502 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1503
1504 #ifndef _LP64
1505 // In the LP64 build, all registers can be moved as aligned/adjacent
1506 // pairs, so there's never any need to move the high bits separately.
1507 // The 32-bit builds have to deal with the 32-bit ABI which can force
1508 // all sorts of silly alignment problems.
1509
1510 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1511 // 32-bits of a 64-bit register, but are needed in low bits of another
1512 // register (else it's a hi-bits-to-hi-bits copy which should have
1513 // happened already as part of a 64-bit move)
1514 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1515 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1516 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1517 // Shift src_second down to dst_second's low bits.
1518 if( cbuf ) {
1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1520 #ifndef PRODUCT
1521 } else if( !do_size ) {
1522 if( size != 0 ) st->print("\n\t");
1523 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1524 #endif
1525 }
1526 return size+4;
1527 }
1528
1529 // Check for high word integer store. Must down-shift the hi bits
1530 // into a temp register, then fall into the case of storing int bits.
1531 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1532 // Shift src_second down to dst_second's low bits.
1533 if( cbuf ) {
1534 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1535 #ifndef PRODUCT
1536 } else if( !do_size ) {
1537 if( size != 0 ) st->print("\n\t");
1538 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1539 #endif
1540 }
1541 size+=4;
1542 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1543 }
1544
1545 // Check for high word integer load
1546 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1547 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1548
1549 // Check for high word integer store
1550 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1551 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1552
1553 // Check for high word float store
1554 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1555 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1556
1557 #endif // !_LP64
1558
1559 Unimplemented();
1560 }
1561
1562 #ifndef PRODUCT
1563 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1564 implementation( NULL, ra_, false, st );
1565 }
1566 #endif
1567
1568 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1569 implementation( &cbuf, ra_, false, NULL );
1570 }
1571
1572 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1573 return implementation( NULL, ra_, true, NULL );
1574 }
1575
1576 //=============================================================================
1577 #ifndef PRODUCT
1578 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1579 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1580 }
1581 #endif
1582
1583 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1584 MacroAssembler _masm(&cbuf);
1585 for(int i = 0; i < _count; i += 1) {
1586 __ nop();
1587 }
1588 }
1589
1590 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1591 return 4 * _count;
1592 }
1593
1594
1595 //=============================================================================
1596 #ifndef PRODUCT
1597 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1598 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1599 int reg = ra_->get_reg_first(this);
1600 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1601 }
1602 #endif
1603
1604 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1605 MacroAssembler _masm(&cbuf);
1606 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1607 int reg = ra_->get_encode(this);
1608
1609 if (Assembler::is_simm13(offset)) {
1610 __ add(SP, offset, reg_to_register_object(reg));
1611 } else {
1612 __ set(offset, O7);
1613 __ add(SP, O7, reg_to_register_object(reg));
1614 }
1615 }
1616
1617 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1618 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1619 assert(ra_ == ra_->C->regalloc(), "sanity");
1620 return ra_->C->scratch_emit_size(this);
1621 }
1622
1623 //=============================================================================
1624
1625 // emit call stub, compiled java to interpretor
1626 void emit_java_to_interp(CodeBuffer &cbuf ) {
1627
1628 // Stub is fixed up when the corresponding call is converted from calling
1629 // compiled code to calling interpreted code.
1630 // set (empty), G5
1631 // jmp -1
1632
1633 address mark = cbuf.insts_mark(); // get mark within main instrs section
1634
1635 MacroAssembler _masm(&cbuf);
1636
1637 address base =
1638 __ start_a_stub(Compile::MAX_stubs_size);
1639 if (base == NULL) return; // CodeBuffer::expand failed
1640
1641 // static stub relocation stores the instruction address of the call
1642 __ relocate(static_stub_Relocation::spec(mark));
1643
1644 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1645
1646 __ set_inst_mark();
1647 AddressLiteral addrlit(-1);
1648 __ JUMP(addrlit, G3, 0);
1649
1650 __ delayed()->nop();
1651
1652 // Update current stubs pointer and restore code_end.
1653 __ end_a_stub();
1654 }
1655
1656 // size of call stub, compiled java to interpretor
1657 uint size_java_to_interp() {
1658 // This doesn't need to be accurate but it must be larger or equal to
1659 // the real size of the stub.
1660 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1661 NativeJump::instruction_size + // sethi; jmp; nop
1662 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1663 }
1664 // relocation entries for call stub, compiled java to interpretor
1665 uint reloc_java_to_interp() {
1666 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1667 }
1668
1669
1670 //=============================================================================
1671 #ifndef PRODUCT
1672 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1673 st->print_cr("\nUEP:");
1674 #ifdef _LP64
1675 if (UseCompressedOops) {
1676 assert(Universe::heap() != NULL, "java heap should be initialized");
1677 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1678 st->print_cr("\tSLL R_G5,3,R_G5");
1679 if (Universe::narrow_oop_base() != NULL)
1680 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1681 } else {
1682 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1683 }
1684 st->print_cr("\tCMP R_G5,R_G3" );
1685 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1686 #else // _LP64
1687 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1688 st->print_cr("\tCMP R_G5,R_G3" );
1689 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1690 #endif // _LP64
1691 }
1692 #endif
1693
1694 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1695 MacroAssembler _masm(&cbuf);
1696 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1697 Register temp_reg = G3;
1698 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1699
1700 // Load klass from receiver
1701 __ load_klass(O0, temp_reg);
1702 // Compare against expected klass
1703 __ cmp(temp_reg, G5_ic_reg);
1704 // Branch to miss code, checks xcc or icc depending
1705 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1706 }
1707
1708 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1709 return MachNode::size(ra_);
1710 }
1711
1712
1713 //=============================================================================
1714
1715 uint size_exception_handler() {
1716 if (TraceJumps) {
1717 return (400); // just a guess
1718 }
1719 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1720 }
1721
1722 uint size_deopt_handler() {
1723 if (TraceJumps) {
1724 return (400); // just a guess
1725 }
1726 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1727 }
1728
1729 // Emit exception handler code.
1730 int emit_exception_handler(CodeBuffer& cbuf) {
1731 Register temp_reg = G3;
1732 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1733 MacroAssembler _masm(&cbuf);
1734
1735 address base =
1736 __ start_a_stub(size_exception_handler());
1737 if (base == NULL) return 0; // CodeBuffer::expand failed
1738
1739 int offset = __ offset();
1740
1741 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1742 __ delayed()->nop();
1743
1744 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1745
1746 __ end_a_stub();
1747
1748 return offset;
1749 }
1750
1751 int emit_deopt_handler(CodeBuffer& cbuf) {
1752 // Can't use any of the current frame's registers as we may have deopted
1753 // at a poll and everything (including G3) can be live.
1754 Register temp_reg = L0;
1755 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1756 MacroAssembler _masm(&cbuf);
1757
1758 address base =
1759 __ start_a_stub(size_deopt_handler());
1760 if (base == NULL) return 0; // CodeBuffer::expand failed
1761
1762 int offset = __ offset();
1763 __ save_frame(0);
1764 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1765 __ delayed()->restore();
1766
1767 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1768
1769 __ end_a_stub();
1770 return offset;
1771
1772 }
1773
1774 // Given a register encoding, produce a Integer Register object
1775 static Register reg_to_register_object(int register_encoding) {
1776 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1777 return as_Register(register_encoding);
1778 }
1779
1780 // Given a register encoding, produce a single-precision Float Register object
1781 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1782 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1783 return as_SingleFloatRegister(register_encoding);
1784 }
1785
1786 // Given a register encoding, produce a double-precision Float Register object
1787 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1788 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1789 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1790 return as_DoubleFloatRegister(register_encoding);
1791 }
1792
1793 const bool Matcher::match_rule_supported(int opcode) {
1794 if (!has_match_rule(opcode))
1795 return false;
1796
1797 switch (opcode) {
1798 case Op_CountLeadingZerosI:
1799 case Op_CountLeadingZerosL:
1800 case Op_CountTrailingZerosI:
1801 case Op_CountTrailingZerosL:
1802 if (!UsePopCountInstruction)
1803 return false;
1804 break;
1805 }
1806
1807 return true; // Per default match rules are supported.
1808 }
1809
1810 int Matcher::regnum_to_fpu_offset(int regnum) {
1811 return regnum - 32; // The FP registers are in the second chunk
1812 }
1813
1814 #ifdef ASSERT
1815 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1816 #endif
1817
1818 // Vector width in bytes
1819 const uint Matcher::vector_width_in_bytes(void) {
1820 return 8;
1821 }
1822
1823 // Vector ideal reg
1824 const uint Matcher::vector_ideal_reg(void) {
1825 return Op_RegD;
1826 }
1827
1828 // USII supports fxtof through the whole range of number, USIII doesn't
1829 const bool Matcher::convL2FSupported(void) {
1830 return VM_Version::has_fast_fxtof();
1831 }
1832
1833 // Is this branch offset short enough that a short branch can be used?
1834 //
1835 // NOTE: If the platform does not provide any short branch variants, then
1836 // this method should return false for offset 0.
1837 bool Matcher::is_short_branch_offset(int rule, int offset) {
1838 return false;
1839 }
1840
1841 const bool Matcher::isSimpleConstant64(jlong value) {
1842 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1843 // Depends on optimizations in MacroAssembler::setx.
1844 int hi = (int)(value >> 32);
1845 int lo = (int)(value & ~0);
1846 return (hi == 0) || (hi == -1) || (lo == 0);
1847 }
1848
1849 // No scaling for the parameter the ClearArray node.
1850 const bool Matcher::init_array_count_is_in_bytes = true;
1851
1852 // Threshold size for cleararray.
1853 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1854
1855 // Should the Matcher clone shifts on addressing modes, expecting them to
1856 // be subsumed into complex addressing expressions or compute them into
1857 // registers? True for Intel but false for most RISCs
1858 const bool Matcher::clone_shift_expressions = false;
1859
1860 // Do we need to mask the count passed to shift instructions or does
1861 // the cpu only look at the lower 5/6 bits anyway?
1862 const bool Matcher::need_masked_shift_count = false;
1863
1864 bool Matcher::narrow_oop_use_complex_address() {
1865 NOT_LP64(ShouldNotCallThis());
1866 assert(UseCompressedOops, "only for compressed oops code");
1867 return false;
1868 }
1869
1870 // Is it better to copy float constants, or load them directly from memory?
1871 // Intel can load a float constant from a direct address, requiring no
1872 // extra registers. Most RISCs will have to materialize an address into a
1873 // register first, so they would do better to copy the constant from stack.
1874 const bool Matcher::rematerialize_float_constants = false;
1875
1876 // If CPU can load and store mis-aligned doubles directly then no fixup is
1877 // needed. Else we split the double into 2 integer pieces and move it
1878 // piece-by-piece. Only happens when passing doubles into C code as the
1879 // Java calling convention forces doubles to be aligned.
1880 #ifdef _LP64
1881 const bool Matcher::misaligned_doubles_ok = true;
1882 #else
1883 const bool Matcher::misaligned_doubles_ok = false;
1884 #endif
1885
1886 // No-op on SPARC.
1887 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1888 }
1889
1890 // Advertise here if the CPU requires explicit rounding operations
1891 // to implement the UseStrictFP mode.
1892 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1893
1894 // Are floats conerted to double when stored to stack during deoptimization?
1895 // Sparc does not handle callee-save floats.
1896 bool Matcher::float_in_double() { return false; }
1897
1898 // Do ints take an entire long register or just half?
1899 // Note that we if-def off of _LP64.
1900 // The relevant question is how the int is callee-saved. In _LP64
1901 // the whole long is written but de-opt'ing will have to extract
1902 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1903 #ifdef _LP64
1904 const bool Matcher::int_in_long = true;
1905 #else
1906 const bool Matcher::int_in_long = false;
1907 #endif
1908
1909 // Return whether or not this register is ever used as an argument. This
1910 // function is used on startup to build the trampoline stubs in generateOptoStub.
1911 // Registers not mentioned will be killed by the VM call in the trampoline, and
1912 // arguments in those registers not be available to the callee.
1913 bool Matcher::can_be_java_arg( int reg ) {
1914 // Standard sparc 6 args in registers
1915 if( reg == R_I0_num ||
1916 reg == R_I1_num ||
1917 reg == R_I2_num ||
1918 reg == R_I3_num ||
1919 reg == R_I4_num ||
1920 reg == R_I5_num ) return true;
1921 #ifdef _LP64
1922 // 64-bit builds can pass 64-bit pointers and longs in
1923 // the high I registers
1924 if( reg == R_I0H_num ||
1925 reg == R_I1H_num ||
1926 reg == R_I2H_num ||
1927 reg == R_I3H_num ||
1928 reg == R_I4H_num ||
1929 reg == R_I5H_num ) return true;
1930
1931 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1932 return true;
1933 }
1934
1935 #else
1936 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1937 // Longs cannot be passed in O regs, because O regs become I regs
1938 // after a 'save' and I regs get their high bits chopped off on
1939 // interrupt.
1940 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1941 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1942 #endif
1943 // A few float args in registers
1944 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1945
1946 return false;
1947 }
1948
1949 bool Matcher::is_spillable_arg( int reg ) {
1950 return can_be_java_arg(reg);
1951 }
1952
1953 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1954 // Use hardware SDIVX instruction when it is
1955 // faster than a code which use multiply.
1956 return VM_Version::has_fast_idiv();
1957 }
1958
1959 // Register for DIVI projection of divmodI
1960 RegMask Matcher::divI_proj_mask() {
1961 ShouldNotReachHere();
1962 return RegMask();
1963 }
1964
1965 // Register for MODI projection of divmodI
1966 RegMask Matcher::modI_proj_mask() {
1967 ShouldNotReachHere();
1968 return RegMask();
1969 }
1970
1971 // Register for DIVL projection of divmodL
1972 RegMask Matcher::divL_proj_mask() {
1973 ShouldNotReachHere();
1974 return RegMask();
1975 }
1976
1977 // Register for MODL projection of divmodL
1978 RegMask Matcher::modL_proj_mask() {
1979 ShouldNotReachHere();
1980 return RegMask();
1981 }
1982
1983 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1984 return L7_REGP_mask;
1985 }
1986
1987 %}
1988
1989
1990 // The intptr_t operand types, defined by textual substitution.
1991 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1992 #ifdef _LP64
1993 #define immX immL
1994 #define immX13 immL13
1995 #define immX13m7 immL13m7
1996 #define iRegX iRegL
1997 #define g1RegX g1RegL
1998 #else
1999 #define immX immI
2000 #define immX13 immI13
2001 #define immX13m7 immI13m7
2002 #define iRegX iRegI
2003 #define g1RegX g1RegI
2004 #endif
2005
2006 //----------ENCODING BLOCK-----------------------------------------------------
2007 // This block specifies the encoding classes used by the compiler to output
2008 // byte streams. Encoding classes are parameterized macros used by
2009 // Machine Instruction Nodes in order to generate the bit encoding of the
2010 // instruction. Operands specify their base encoding interface with the
2011 // interface keyword. There are currently supported four interfaces,
2012 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2013 // operand to generate a function which returns its register number when
2014 // queried. CONST_INTER causes an operand to generate a function which
2015 // returns the value of the constant when queried. MEMORY_INTER causes an
2016 // operand to generate four functions which return the Base Register, the
2017 // Index Register, the Scale Value, and the Offset Value of the operand when
2018 // queried. COND_INTER causes an operand to generate six functions which
2019 // return the encoding code (ie - encoding bits for the instruction)
2020 // associated with each basic boolean condition for a conditional instruction.
2021 //
2022 // Instructions specify two basic values for encoding. Again, a function
2023 // is available to check if the constant displacement is an oop. They use the
2024 // ins_encode keyword to specify their encoding classes (which must be
2025 // a sequence of enc_class names, and their parameters, specified in
2026 // the encoding block), and they use the
2027 // opcode keyword to specify, in order, their primary, secondary, and
2028 // tertiary opcode. Only the opcode sections which a particular instruction
2029 // needs for encoding need to be specified.
2030 encode %{
2031 enc_class enc_untested %{
2032 #ifdef ASSERT
2033 MacroAssembler _masm(&cbuf);
2034 __ untested("encoding");
2035 #endif
2036 %}
2037
2038 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2039 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2040 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2041 %}
2042
2043 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2044 emit_form3_mem_reg(cbuf, this, $primary, -1,
2045 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2046 %}
2047
2048 enc_class form3_mem_prefetch_read( memory mem ) %{
2049 emit_form3_mem_reg(cbuf, this, $primary, -1,
2050 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2051 %}
2052
2053 enc_class form3_mem_prefetch_write( memory mem ) %{
2054 emit_form3_mem_reg(cbuf, this, $primary, -1,
2055 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2056 %}
2057
2058 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2059 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2060 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2061 guarantee($mem$$index == R_G0_enc, "double index?");
2062 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2063 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2064 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2065 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2066 %}
2067
2068 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2069 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2070 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2071 guarantee($mem$$index == R_G0_enc, "double index?");
2072 // Load long with 2 instructions
2073 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2074 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2075 %}
2076
2077 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2078 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2079 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2080 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2081 %}
2082
2083 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2084 // Encode a reg-reg copy. If it is useless, then empty encoding.
2085 if( $rs2$$reg != $rd$$reg )
2086 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2087 %}
2088
2089 // Target lo half of long
2090 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2091 // Encode a reg-reg copy. If it is useless, then empty encoding.
2092 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2093 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2094 %}
2095
2096 // Source lo half of long
2097 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2098 // Encode a reg-reg copy. If it is useless, then empty encoding.
2099 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2100 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2101 %}
2102
2103 // Target hi half of long
2104 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2105 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2106 %}
2107
2108 // Source lo half of long, and leave it sign extended.
2109 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2110 // Sign extend low half
2111 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2112 %}
2113
2114 // Source hi half of long, and leave it sign extended.
2115 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2116 // Shift high half to low half
2117 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2118 %}
2119
2120 // Source hi half of long
2121 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2122 // Encode a reg-reg copy. If it is useless, then empty encoding.
2123 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2124 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2125 %}
2126
2127 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2128 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2129 %}
2130
2131 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2132 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2133 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2134 %}
2135
2136 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2137 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2138 // clear if nothing else is happening
2139 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2140 // blt,a,pn done
2141 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2142 // mov dst,-1 in delay slot
2143 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2144 %}
2145
2146 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2147 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2148 %}
2149
2150 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2151 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2152 %}
2153
2154 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2155 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2156 %}
2157
2158 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2159 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2160 %}
2161
2162 enc_class move_return_pc_to_o1() %{
2163 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2164 %}
2165
2166 #ifdef _LP64
2167 /* %%% merge with enc_to_bool */
2168 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2169 MacroAssembler _masm(&cbuf);
2170
2171 Register src_reg = reg_to_register_object($src$$reg);
2172 Register dst_reg = reg_to_register_object($dst$$reg);
2173 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2174 %}
2175 #endif
2176
2177 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2178 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2179 MacroAssembler _masm(&cbuf);
2180
2181 Register p_reg = reg_to_register_object($p$$reg);
2182 Register q_reg = reg_to_register_object($q$$reg);
2183 Register y_reg = reg_to_register_object($y$$reg);
2184 Register tmp_reg = reg_to_register_object($tmp$$reg);
2185
2186 __ subcc( p_reg, q_reg, p_reg );
2187 __ add ( p_reg, y_reg, tmp_reg );
2188 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2189 %}
2190
2191 enc_class form_d2i_helper(regD src, regF dst) %{
2192 // fcmp %fcc0,$src,$src
2193 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2194 // branch %fcc0 not-nan, predict taken
2195 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2196 // fdtoi $src,$dst
2197 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2198 // fitos $dst,$dst (if nan)
2199 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2200 // clear $dst (if nan)
2201 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2202 // carry on here...
2203 %}
2204
2205 enc_class form_d2l_helper(regD src, regD dst) %{
2206 // fcmp %fcc0,$src,$src check for NAN
2207 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2208 // branch %fcc0 not-nan, predict taken
2209 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2210 // fdtox $src,$dst convert in delay slot
2211 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2212 // fxtod $dst,$dst (if nan)
2213 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2214 // clear $dst (if nan)
2215 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2216 // carry on here...
2217 %}
2218
2219 enc_class form_f2i_helper(regF src, regF dst) %{
2220 // fcmps %fcc0,$src,$src
2221 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2222 // branch %fcc0 not-nan, predict taken
2223 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2224 // fstoi $src,$dst
2225 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2226 // fitos $dst,$dst (if nan)
2227 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2228 // clear $dst (if nan)
2229 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2230 // carry on here...
2231 %}
2232
2233 enc_class form_f2l_helper(regF src, regD dst) %{
2234 // fcmps %fcc0,$src,$src
2235 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2236 // branch %fcc0 not-nan, predict taken
2237 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2238 // fstox $src,$dst
2239 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2240 // fxtod $dst,$dst (if nan)
2241 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2242 // clear $dst (if nan)
2243 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2244 // carry on here...
2245 %}
2246
2247 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2248 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2249 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2250 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2251
2252 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2253
2254 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2255 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2256
2257 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2258 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2259 %}
2260
2261 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2262 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2263 %}
2264
2265 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2266 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2267 %}
2268
2269 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2270 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2271 %}
2272
2273 enc_class form3_convI2F(regF rs2, regF rd) %{
2274 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2275 %}
2276
2277 // Encloding class for traceable jumps
2278 enc_class form_jmpl(g3RegP dest) %{
2279 emit_jmpl(cbuf, $dest$$reg);
2280 %}
2281
2282 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2283 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2284 %}
2285
2286 enc_class form2_nop() %{
2287 emit_nop(cbuf);
2288 %}
2289
2290 enc_class form2_illtrap() %{
2291 emit_illtrap(cbuf);
2292 %}
2293
2294
2295 // Compare longs and convert into -1, 0, 1.
2296 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2297 // CMP $src1,$src2
2298 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2299 // blt,a,pn done
2300 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2301 // mov dst,-1 in delay slot
2302 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2303 // bgt,a,pn done
2304 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2305 // mov dst,1 in delay slot
2306 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2307 // CLR $dst
2308 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2309 %}
2310
2311 enc_class enc_PartialSubtypeCheck() %{
2312 MacroAssembler _masm(&cbuf);
2313 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2314 __ delayed()->nop();
2315 %}
2316
2317 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2318 MacroAssembler _masm(&cbuf);
2319 Label* L = $labl$$label;
2320 assert(L != NULL, "need Label");
2321 Assembler::Predict predict_taken =
2322 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2323
2324 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2325 __ delayed()->nop();
2326 %}
2327
2328 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2329 MacroAssembler _masm(&cbuf);
2330 Label* L = $labl$$label;
2331 assert(L != NULL, "need Label");
2332 Assembler::Predict predict_taken =
2333 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2334
2335 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2336 __ delayed()->nop();
2337 %}
2338
2339 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2340 int op = (Assembler::arith_op << 30) |
2341 ($dst$$reg << 25) |
2342 (Assembler::movcc_op3 << 19) |
2343 (1 << 18) | // cc2 bit for 'icc'
2344 ($cmp$$cmpcode << 14) |
2345 (0 << 13) | // select register move
2346 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2347 ($src$$reg << 0);
2348 cbuf.insts()->emit_int32(op);
2349 %}
2350
2351 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2352 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2353 int op = (Assembler::arith_op << 30) |
2354 ($dst$$reg << 25) |
2355 (Assembler::movcc_op3 << 19) |
2356 (1 << 18) | // cc2 bit for 'icc'
2357 ($cmp$$cmpcode << 14) |
2358 (1 << 13) | // select immediate move
2359 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2360 (simm11 << 0);
2361 cbuf.insts()->emit_int32(op);
2362 %}
2363
2364 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2365 int op = (Assembler::arith_op << 30) |
2366 ($dst$$reg << 25) |
2367 (Assembler::movcc_op3 << 19) |
2368 (0 << 18) | // cc2 bit for 'fccX'
2369 ($cmp$$cmpcode << 14) |
2370 (0 << 13) | // select register move
2371 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2372 ($src$$reg << 0);
2373 cbuf.insts()->emit_int32(op);
2374 %}
2375
2376 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2377 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2378 int op = (Assembler::arith_op << 30) |
2379 ($dst$$reg << 25) |
2380 (Assembler::movcc_op3 << 19) |
2381 (0 << 18) | // cc2 bit for 'fccX'
2382 ($cmp$$cmpcode << 14) |
2383 (1 << 13) | // select immediate move
2384 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2385 (simm11 << 0);
2386 cbuf.insts()->emit_int32(op);
2387 %}
2388
2389 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2390 int op = (Assembler::arith_op << 30) |
2391 ($dst$$reg << 25) |
2392 (Assembler::fpop2_op3 << 19) |
2393 (0 << 18) |
2394 ($cmp$$cmpcode << 14) |
2395 (1 << 13) | // select register move
2396 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2397 ($primary << 5) | // select single, double or quad
2398 ($src$$reg << 0);
2399 cbuf.insts()->emit_int32(op);
2400 %}
2401
2402 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2403 int op = (Assembler::arith_op << 30) |
2404 ($dst$$reg << 25) |
2405 (Assembler::fpop2_op3 << 19) |
2406 (0 << 18) |
2407 ($cmp$$cmpcode << 14) |
2408 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2409 ($primary << 5) | // select single, double or quad
2410 ($src$$reg << 0);
2411 cbuf.insts()->emit_int32(op);
2412 %}
2413
2414 // Used by the MIN/MAX encodings. Same as a CMOV, but
2415 // the condition comes from opcode-field instead of an argument.
2416 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2417 int op = (Assembler::arith_op << 30) |
2418 ($dst$$reg << 25) |
2419 (Assembler::movcc_op3 << 19) |
2420 (1 << 18) | // cc2 bit for 'icc'
2421 ($primary << 14) |
2422 (0 << 13) | // select register move
2423 (0 << 11) | // cc1, cc0 bits for 'icc'
2424 ($src$$reg << 0);
2425 cbuf.insts()->emit_int32(op);
2426 %}
2427
2428 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2429 int op = (Assembler::arith_op << 30) |
2430 ($dst$$reg << 25) |
2431 (Assembler::movcc_op3 << 19) |
2432 (6 << 16) | // cc2 bit for 'xcc'
2433 ($primary << 14) |
2434 (0 << 13) | // select register move
2435 (0 << 11) | // cc1, cc0 bits for 'icc'
2436 ($src$$reg << 0);
2437 cbuf.insts()->emit_int32(op);
2438 %}
2439
2440 enc_class Set13( immI13 src, iRegI rd ) %{
2441 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2442 %}
2443
2444 enc_class SetHi22( immI src, iRegI rd ) %{
2445 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2446 %}
2447
2448 enc_class Set32( immI src, iRegI rd ) %{
2449 MacroAssembler _masm(&cbuf);
2450 __ set($src$$constant, reg_to_register_object($rd$$reg));
2451 %}
2452
2453 enc_class call_epilog %{
2454 if( VerifyStackAtCalls ) {
2455 MacroAssembler _masm(&cbuf);
2456 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2457 Register temp_reg = G3;
2458 __ add(SP, framesize, temp_reg);
2459 __ cmp(temp_reg, FP);
2460 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2461 }
2462 %}
2463
2464 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2465 // to G1 so the register allocator will not have to deal with the misaligned register
2466 // pair.
2467 enc_class adjust_long_from_native_call %{
2468 #ifndef _LP64
2469 if (returns_long()) {
2470 // sllx O0,32,O0
2471 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2472 // srl O1,0,O1
2473 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2474 // or O0,O1,G1
2475 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2476 }
2477 #endif
2478 %}
2479
2480 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2481 // CALL directly to the runtime
2482 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2483 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2484 /*preserve_g2=*/true);
2485 %}
2486
2487 enc_class preserve_SP %{
2488 MacroAssembler _masm(&cbuf);
2489 __ mov(SP, L7_mh_SP_save);
2490 %}
2491
2492 enc_class restore_SP %{
2493 MacroAssembler _masm(&cbuf);
2494 __ mov(L7_mh_SP_save, SP);
2495 %}
2496
2497 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2498 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2499 // who we intended to call.
2500 if ( !_method ) {
2501 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2502 } else if (_optimized_virtual) {
2503 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2504 } else {
2505 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2506 }
2507 if( _method ) { // Emit stub for static call
2508 emit_java_to_interp(cbuf);
2509 }
2510 %}
2511
2512 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2513 MacroAssembler _masm(&cbuf);
2514 __ set_inst_mark();
2515 int vtable_index = this->_vtable_index;
2516 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2517 if (vtable_index < 0) {
2518 // must be invalid_vtable_index, not nonvirtual_vtable_index
2519 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2520 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2521 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2522 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2523 // !!!!!
2524 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2525 // emit_call_dynamic_prologue( cbuf );
2526 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2527
2528 address virtual_call_oop_addr = __ inst_mark();
2529 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2530 // who we intended to call.
2531 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2532 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2533 } else {
2534 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2535 // Just go thru the vtable
2536 // get receiver klass (receiver already checked for non-null)
2537 // If we end up going thru a c2i adapter interpreter expects method in G5
2538 int off = __ offset();
2539 __ load_klass(O0, G3_scratch);
2540 int klass_load_size;
2541 if (UseCompressedOops) {
2542 assert(Universe::heap() != NULL, "java heap should be initialized");
2543 if (Universe::narrow_oop_base() == NULL)
2544 klass_load_size = 2*BytesPerInstWord;
2545 else
2546 klass_load_size = 3*BytesPerInstWord;
2547 } else {
2548 klass_load_size = 1*BytesPerInstWord;
2549 }
2550 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2551 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2552 if( __ is_simm13(v_off) ) {
2553 __ ld_ptr(G3, v_off, G5_method);
2554 } else {
2555 // Generate 2 instructions
2556 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2557 __ or3(G5_method, v_off & 0x3ff, G5_method);
2558 // ld_ptr, set_hi, set
2559 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2560 "Unexpected instruction size(s)");
2561 __ ld_ptr(G3, G5_method, G5_method);
2562 }
2563 // NOTE: for vtable dispatches, the vtable entry will never be null.
2564 // However it may very well end up in handle_wrong_method if the
2565 // method is abstract for the particular class.
2566 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2567 // jump to target (either compiled code or c2iadapter)
2568 __ jmpl(G3_scratch, G0, O7);
2569 __ delayed()->nop();
2570 }
2571 %}
2572
2573 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2574 MacroAssembler _masm(&cbuf);
2575
2576 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2577 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2578 // we might be calling a C2I adapter which needs it.
2579
2580 assert(temp_reg != G5_ic_reg, "conflicting registers");
2581 // Load nmethod
2582 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2583
2584 // CALL to compiled java, indirect the contents of G3
2585 __ set_inst_mark();
2586 __ callr(temp_reg, G0);
2587 __ delayed()->nop();
2588 %}
2589
2590 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2591 MacroAssembler _masm(&cbuf);
2592 Register Rdividend = reg_to_register_object($src1$$reg);
2593 Register Rdivisor = reg_to_register_object($src2$$reg);
2594 Register Rresult = reg_to_register_object($dst$$reg);
2595
2596 __ sra(Rdivisor, 0, Rdivisor);
2597 __ sra(Rdividend, 0, Rdividend);
2598 __ sdivx(Rdividend, Rdivisor, Rresult);
2599 %}
2600
2601 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2602 MacroAssembler _masm(&cbuf);
2603
2604 Register Rdividend = reg_to_register_object($src1$$reg);
2605 int divisor = $imm$$constant;
2606 Register Rresult = reg_to_register_object($dst$$reg);
2607
2608 __ sra(Rdividend, 0, Rdividend);
2609 __ sdivx(Rdividend, divisor, Rresult);
2610 %}
2611
2612 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2613 MacroAssembler _masm(&cbuf);
2614 Register Rsrc1 = reg_to_register_object($src1$$reg);
2615 Register Rsrc2 = reg_to_register_object($src2$$reg);
2616 Register Rdst = reg_to_register_object($dst$$reg);
2617
2618 __ sra( Rsrc1, 0, Rsrc1 );
2619 __ sra( Rsrc2, 0, Rsrc2 );
2620 __ mulx( Rsrc1, Rsrc2, Rdst );
2621 __ srlx( Rdst, 32, Rdst );
2622 %}
2623
2624 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2625 MacroAssembler _masm(&cbuf);
2626 Register Rdividend = reg_to_register_object($src1$$reg);
2627 Register Rdivisor = reg_to_register_object($src2$$reg);
2628 Register Rresult = reg_to_register_object($dst$$reg);
2629 Register Rscratch = reg_to_register_object($scratch$$reg);
2630
2631 assert(Rdividend != Rscratch, "");
2632 assert(Rdivisor != Rscratch, "");
2633
2634 __ sra(Rdividend, 0, Rdividend);
2635 __ sra(Rdivisor, 0, Rdivisor);
2636 __ sdivx(Rdividend, Rdivisor, Rscratch);
2637 __ mulx(Rscratch, Rdivisor, Rscratch);
2638 __ sub(Rdividend, Rscratch, Rresult);
2639 %}
2640
2641 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2642 MacroAssembler _masm(&cbuf);
2643
2644 Register Rdividend = reg_to_register_object($src1$$reg);
2645 int divisor = $imm$$constant;
2646 Register Rresult = reg_to_register_object($dst$$reg);
2647 Register Rscratch = reg_to_register_object($scratch$$reg);
2648
2649 assert(Rdividend != Rscratch, "");
2650
2651 __ sra(Rdividend, 0, Rdividend);
2652 __ sdivx(Rdividend, divisor, Rscratch);
2653 __ mulx(Rscratch, divisor, Rscratch);
2654 __ sub(Rdividend, Rscratch, Rresult);
2655 %}
2656
2657 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2658 MacroAssembler _masm(&cbuf);
2659
2660 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2661 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2662
2663 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2664 %}
2665
2666 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2667 MacroAssembler _masm(&cbuf);
2668
2669 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2670 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2671
2672 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2673 %}
2674
2675 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2676 MacroAssembler _masm(&cbuf);
2677
2678 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2679 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2680
2681 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2682 %}
2683
2684 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2685 MacroAssembler _masm(&cbuf);
2686
2687 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2688 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2689
2690 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2691 %}
2692
2693 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2694 MacroAssembler _masm(&cbuf);
2695
2696 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2697 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2698
2699 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2700 %}
2701
2702 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2703 MacroAssembler _masm(&cbuf);
2704
2705 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2706 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2707
2708 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2709 %}
2710
2711 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2712 MacroAssembler _masm(&cbuf);
2713
2714 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2715 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2716
2717 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2718 %}
2719
2720 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2721 MacroAssembler _masm(&cbuf);
2722
2723 Register Roop = reg_to_register_object($oop$$reg);
2724 Register Rbox = reg_to_register_object($box$$reg);
2725 Register Rscratch = reg_to_register_object($scratch$$reg);
2726 Register Rmark = reg_to_register_object($scratch2$$reg);
2727
2728 assert(Roop != Rscratch, "");
2729 assert(Roop != Rmark, "");
2730 assert(Rbox != Rscratch, "");
2731 assert(Rbox != Rmark, "");
2732
2733 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2734 %}
2735
2736 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2737 MacroAssembler _masm(&cbuf);
2738
2739 Register Roop = reg_to_register_object($oop$$reg);
2740 Register Rbox = reg_to_register_object($box$$reg);
2741 Register Rscratch = reg_to_register_object($scratch$$reg);
2742 Register Rmark = reg_to_register_object($scratch2$$reg);
2743
2744 assert(Roop != Rscratch, "");
2745 assert(Roop != Rmark, "");
2746 assert(Rbox != Rscratch, "");
2747 assert(Rbox != Rmark, "");
2748
2749 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2750 %}
2751
2752 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2753 MacroAssembler _masm(&cbuf);
2754 Register Rmem = reg_to_register_object($mem$$reg);
2755 Register Rold = reg_to_register_object($old$$reg);
2756 Register Rnew = reg_to_register_object($new$$reg);
2757
2758 // casx_under_lock picks 1 of 3 encodings:
2759 // For 32-bit pointers you get a 32-bit CAS
2760 // For 64-bit pointers you get a 64-bit CASX
2761 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2762 __ cmp( Rold, Rnew );
2763 %}
2764
2765 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2766 Register Rmem = reg_to_register_object($mem$$reg);
2767 Register Rold = reg_to_register_object($old$$reg);
2768 Register Rnew = reg_to_register_object($new$$reg);
2769
2770 MacroAssembler _masm(&cbuf);
2771 __ mov(Rnew, O7);
2772 __ casx(Rmem, Rold, O7);
2773 __ cmp( Rold, O7 );
2774 %}
2775
2776 // raw int cas, used for compareAndSwap
2777 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2778 Register Rmem = reg_to_register_object($mem$$reg);
2779 Register Rold = reg_to_register_object($old$$reg);
2780 Register Rnew = reg_to_register_object($new$$reg);
2781
2782 MacroAssembler _masm(&cbuf);
2783 __ mov(Rnew, O7);
2784 __ cas(Rmem, Rold, O7);
2785 __ cmp( Rold, O7 );
2786 %}
2787
2788 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2789 Register Rres = reg_to_register_object($res$$reg);
2790
2791 MacroAssembler _masm(&cbuf);
2792 __ mov(1, Rres);
2793 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2794 %}
2795
2796 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2797 Register Rres = reg_to_register_object($res$$reg);
2798
2799 MacroAssembler _masm(&cbuf);
2800 __ mov(1, Rres);
2801 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2802 %}
2803
2804 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2805 MacroAssembler _masm(&cbuf);
2806 Register Rdst = reg_to_register_object($dst$$reg);
2807 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2808 : reg_to_DoubleFloatRegister_object($src1$$reg);
2809 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2810 : reg_to_DoubleFloatRegister_object($src2$$reg);
2811
2812 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2813 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2814 %}
2815
2816 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2817 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2818 MacroAssembler _masm(&cbuf);
2819 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2820 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2821 Register base_pointer_arg = reg_to_register_object($base$$reg);
2822
2823 Label loop;
2824 __ mov(nof_bytes_arg, nof_bytes_tmp);
2825
2826 // Loop and clear, walking backwards through the array.
2827 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2828 __ bind(loop);
2829 __ deccc(nof_bytes_tmp, 8);
2830 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2831 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2832 // %%%% this mini-loop must not cross a cache boundary!
2833 %}
2834
2835
2836 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2837 Label Ldone, Lloop;
2838 MacroAssembler _masm(&cbuf);
2839
2840 Register str1_reg = reg_to_register_object($str1$$reg);
2841 Register str2_reg = reg_to_register_object($str2$$reg);
2842 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2843 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2844 Register result_reg = reg_to_register_object($result$$reg);
2845
2846 assert(result_reg != str1_reg &&
2847 result_reg != str2_reg &&
2848 result_reg != cnt1_reg &&
2849 result_reg != cnt2_reg ,
2850 "need different registers");
2851
2852 // Compute the minimum of the string lengths(str1_reg) and the
2853 // difference of the string lengths (stack)
2854
2855 // See if the lengths are different, and calculate min in str1_reg.
2856 // Stash diff in O7 in case we need it for a tie-breaker.
2857 Label Lskip;
2858 __ subcc(cnt1_reg, cnt2_reg, O7);
2859 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2860 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2861 // cnt2 is shorter, so use its count:
2862 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2863 __ bind(Lskip);
2864
2865 // reallocate cnt1_reg, cnt2_reg, result_reg
2866 // Note: limit_reg holds the string length pre-scaled by 2
2867 Register limit_reg = cnt1_reg;
2868 Register chr2_reg = cnt2_reg;
2869 Register chr1_reg = result_reg;
2870 // str{12} are the base pointers
2871
2872 // Is the minimum length zero?
2873 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2874 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2875 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2876
2877 // Load first characters
2878 __ lduh(str1_reg, 0, chr1_reg);
2879 __ lduh(str2_reg, 0, chr2_reg);
2880
2881 // Compare first characters
2882 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2883 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2884 assert(chr1_reg == result_reg, "result must be pre-placed");
2885 __ delayed()->nop();
2886
2887 {
2888 // Check after comparing first character to see if strings are equivalent
2889 Label LSkip2;
2890 // Check if the strings start at same location
2891 __ cmp(str1_reg, str2_reg);
2892 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2893 __ delayed()->nop();
2894
2895 // Check if the length difference is zero (in O7)
2896 __ cmp(G0, O7);
2897 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2898 __ delayed()->mov(G0, result_reg); // result is zero
2899
2900 // Strings might not be equal
2901 __ bind(LSkip2);
2902 }
2903
2904 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2905 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2906 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2907
2908 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2909 __ add(str1_reg, limit_reg, str1_reg);
2910 __ add(str2_reg, limit_reg, str2_reg);
2911 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2912
2913 // Compare the rest of the characters
2914 __ lduh(str1_reg, limit_reg, chr1_reg);
2915 __ bind(Lloop);
2916 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2917 __ lduh(str2_reg, limit_reg, chr2_reg);
2918 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2919 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2920 assert(chr1_reg == result_reg, "result must be pre-placed");
2921 __ delayed()->inccc(limit_reg, sizeof(jchar));
2922 // annul LDUH if branch is not taken to prevent access past end of string
2923 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2924 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2925
2926 // If strings are equal up to min length, return the length difference.
2927 __ mov(O7, result_reg);
2928
2929 // Otherwise, return the difference between the first mismatched chars.
2930 __ bind(Ldone);
2931 %}
2932
2933 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2934 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2935 MacroAssembler _masm(&cbuf);
2936
2937 Register str1_reg = reg_to_register_object($str1$$reg);
2938 Register str2_reg = reg_to_register_object($str2$$reg);
2939 Register cnt_reg = reg_to_register_object($cnt$$reg);
2940 Register tmp1_reg = O7;
2941 Register result_reg = reg_to_register_object($result$$reg);
2942
2943 assert(result_reg != str1_reg &&
2944 result_reg != str2_reg &&
2945 result_reg != cnt_reg &&
2946 result_reg != tmp1_reg ,
2947 "need different registers");
2948
2949 __ cmp(str1_reg, str2_reg); //same char[] ?
2950 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2951 __ delayed()->add(G0, 1, result_reg);
2952
2953 __ bpr(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone);
2954 __ delayed()->add(G0, 1, result_reg); // count == 0
2955
2956 //rename registers
2957 Register limit_reg = cnt_reg;
2958 Register chr1_reg = result_reg;
2959 Register chr2_reg = tmp1_reg;
2960
2961 //check for alignment and position the pointers to the ends
2962 __ or3(str1_reg, str2_reg, chr1_reg);
2963 __ andcc(chr1_reg, 0x3, chr1_reg);
2964 // notZero means at least one not 4-byte aligned.
2965 // We could optimize the case when both arrays are not aligned
2966 // but it is not frequent case and it requires additional checks.
2967 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2968 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2969
2970 // Compare char[] arrays aligned to 4 bytes.
2971 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2972 chr1_reg, chr2_reg, Ldone);
2973 __ ba(Ldone, false);
2974 __ delayed()->add(G0, 1, result_reg);
2975
2976 // char by char compare
2977 __ bind(Lchar);
2978 __ add(str1_reg, limit_reg, str1_reg);
2979 __ add(str2_reg, limit_reg, str2_reg);
2980 __ neg(limit_reg); //negate count
2981
2982 __ lduh(str1_reg, limit_reg, chr1_reg);
2983 // Lchar_loop
2984 __ bind(Lchar_loop);
2985 __ lduh(str2_reg, limit_reg, chr2_reg);
2986 __ cmp(chr1_reg, chr2_reg);
2987 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2988 __ delayed()->mov(G0, result_reg); //not equal
2989 __ inccc(limit_reg, sizeof(jchar));
2990 // annul LDUH if branch is not taken to prevent access past end of string
2991 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
2992 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2993
2994 __ add(G0, 1, result_reg); //equal
2995
2996 __ bind(Ldone);
2997 %}
2998
2999 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3000 Label Lvector, Ldone, Lloop;
3001 MacroAssembler _masm(&cbuf);
3002
3003 Register ary1_reg = reg_to_register_object($ary1$$reg);
3004 Register ary2_reg = reg_to_register_object($ary2$$reg);
3005 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3006 Register tmp2_reg = O7;
3007 Register result_reg = reg_to_register_object($result$$reg);
3008
3009 int length_offset = arrayOopDesc::length_offset_in_bytes();
3010 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3011
3012 // return true if the same array
3013 __ cmp(ary1_reg, ary2_reg);
3014 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3015 __ delayed()->add(G0, 1, result_reg); // equal
3016
3017 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3018 __ delayed()->mov(G0, result_reg); // not equal
3019
3020 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3021 __ delayed()->mov(G0, result_reg); // not equal
3022
3023 //load the lengths of arrays
3024 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3025 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3026
3027 // return false if the two arrays are not equal length
3028 __ cmp(tmp1_reg, tmp2_reg);
3029 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3030 __ delayed()->mov(G0, result_reg); // not equal
3031
3032 __ bpr(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone);
3033 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3034
3035 // load array addresses
3036 __ add(ary1_reg, base_offset, ary1_reg);
3037 __ add(ary2_reg, base_offset, ary2_reg);
3038
3039 // renaming registers
3040 Register chr1_reg = result_reg; // for characters in ary1
3041 Register chr2_reg = tmp2_reg; // for characters in ary2
3042 Register limit_reg = tmp1_reg; // length
3043
3044 // set byte count
3045 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3046
3047 // Compare char[] arrays aligned to 4 bytes.
3048 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3049 chr1_reg, chr2_reg, Ldone);
3050 __ add(G0, 1, result_reg); // equals
3051
3052 __ bind(Ldone);
3053 %}
3054
3055 enc_class enc_rethrow() %{
3056 cbuf.set_insts_mark();
3057 Register temp_reg = G3;
3058 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3059 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3060 MacroAssembler _masm(&cbuf);
3061 #ifdef ASSERT
3062 __ save_frame(0);
3063 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3064 __ sethi(last_rethrow_addrlit, L1);
3065 Address addr(L1, last_rethrow_addrlit.low10());
3066 __ get_pc(L2);
3067 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3068 __ st_ptr(L2, addr);
3069 __ restore();
3070 #endif
3071 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3072 __ delayed()->nop();
3073 %}
3074
3075 enc_class emit_mem_nop() %{
3076 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3077 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3078 %}
3079
3080 enc_class emit_fadd_nop() %{
3081 // Generates the instruction FMOVS f31,f31
3082 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3083 %}
3084
3085 enc_class emit_br_nop() %{
3086 // Generates the instruction BPN,PN .
3087 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3088 %}
3089
3090 enc_class enc_membar_acquire %{
3091 MacroAssembler _masm(&cbuf);
3092 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3093 %}
3094
3095 enc_class enc_membar_release %{
3096 MacroAssembler _masm(&cbuf);
3097 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3098 %}
3099
3100 enc_class enc_membar_volatile %{
3101 MacroAssembler _masm(&cbuf);
3102 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3103 %}
3104
3105 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3106 MacroAssembler _masm(&cbuf);
3107 Register src_reg = reg_to_register_object($src$$reg);
3108 Register dst_reg = reg_to_register_object($dst$$reg);
3109 __ sllx(src_reg, 56, dst_reg);
3110 __ srlx(dst_reg, 8, O7);
3111 __ or3 (dst_reg, O7, dst_reg);
3112 __ srlx(dst_reg, 16, O7);
3113 __ or3 (dst_reg, O7, dst_reg);
3114 __ srlx(dst_reg, 32, O7);
3115 __ or3 (dst_reg, O7, dst_reg);
3116 %}
3117
3118 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3119 MacroAssembler _masm(&cbuf);
3120 Register src_reg = reg_to_register_object($src$$reg);
3121 Register dst_reg = reg_to_register_object($dst$$reg);
3122 __ sll(src_reg, 24, dst_reg);
3123 __ srl(dst_reg, 8, O7);
3124 __ or3(dst_reg, O7, dst_reg);
3125 __ srl(dst_reg, 16, O7);
3126 __ or3(dst_reg, O7, dst_reg);
3127 %}
3128
3129 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3130 MacroAssembler _masm(&cbuf);
3131 Register src_reg = reg_to_register_object($src$$reg);
3132 Register dst_reg = reg_to_register_object($dst$$reg);
3133 __ sllx(src_reg, 48, dst_reg);
3134 __ srlx(dst_reg, 16, O7);
3135 __ or3 (dst_reg, O7, dst_reg);
3136 __ srlx(dst_reg, 32, O7);
3137 __ or3 (dst_reg, O7, dst_reg);
3138 %}
3139
3140 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3141 MacroAssembler _masm(&cbuf);
3142 Register src_reg = reg_to_register_object($src$$reg);
3143 Register dst_reg = reg_to_register_object($dst$$reg);
3144 __ sllx(src_reg, 32, dst_reg);
3145 __ srlx(dst_reg, 32, O7);
3146 __ or3 (dst_reg, O7, dst_reg);
3147 %}
3148
3149 %}
3150
3151 //----------FRAME--------------------------------------------------------------
3152 // Definition of frame structure and management information.
3153 //
3154 // S T A C K L A Y O U T Allocators stack-slot number
3155 // | (to get allocators register number
3156 // G Owned by | | v add VMRegImpl::stack0)
3157 // r CALLER | |
3158 // o | +--------+ pad to even-align allocators stack-slot
3159 // w V | pad0 | numbers; owned by CALLER
3160 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3161 // h ^ | in | 5
3162 // | | args | 4 Holes in incoming args owned by SELF
3163 // | | | | 3
3164 // | | +--------+
3165 // V | | old out| Empty on Intel, window on Sparc
3166 // | old |preserve| Must be even aligned.
3167 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3168 // | | in | 3 area for Intel ret address
3169 // Owned by |preserve| Empty on Sparc.
3170 // SELF +--------+
3171 // | | pad2 | 2 pad to align old SP
3172 // | +--------+ 1
3173 // | | locks | 0
3174 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3175 // | | pad1 | 11 pad to align new SP
3176 // | +--------+
3177 // | | | 10
3178 // | | spills | 9 spills
3179 // V | | 8 (pad0 slot for callee)
3180 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3181 // ^ | out | 7
3182 // | | args | 6 Holes in outgoing args owned by CALLEE
3183 // Owned by +--------+
3184 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3185 // | new |preserve| Must be even-aligned.
3186 // | SP-+--------+----> Matcher::_new_SP, even aligned
3187 // | | |
3188 //
3189 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3190 // known from SELF's arguments and the Java calling convention.
3191 // Region 6-7 is determined per call site.
3192 // Note 2: If the calling convention leaves holes in the incoming argument
3193 // area, those holes are owned by SELF. Holes in the outgoing area
3194 // are owned by the CALLEE. Holes should not be nessecary in the
3195 // incoming area, as the Java calling convention is completely under
3196 // the control of the AD file. Doubles can be sorted and packed to
3197 // avoid holes. Holes in the outgoing arguments may be nessecary for
3198 // varargs C calling conventions.
3199 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3200 // even aligned with pad0 as needed.
3201 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3202 // region 6-11 is even aligned; it may be padded out more so that
3203 // the region from SP to FP meets the minimum stack alignment.
3204
3205 frame %{
3206 // What direction does stack grow in (assumed to be same for native & Java)
3207 stack_direction(TOWARDS_LOW);
3208
3209 // These two registers define part of the calling convention
3210 // between compiled code and the interpreter.
3211 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3212 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3213
3214 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3215 cisc_spilling_operand_name(indOffset);
3216
3217 // Number of stack slots consumed by a Monitor enter
3218 #ifdef _LP64
3219 sync_stack_slots(2);
3220 #else
3221 sync_stack_slots(1);
3222 #endif
3223
3224 // Compiled code's Frame Pointer
3225 frame_pointer(R_SP);
3226
3227 // Stack alignment requirement
3228 stack_alignment(StackAlignmentInBytes);
3229 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3230 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3231
3232 // Number of stack slots between incoming argument block and the start of
3233 // a new frame. The PROLOG must add this many slots to the stack. The
3234 // EPILOG must remove this many slots.
3235 in_preserve_stack_slots(0);
3236
3237 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3238 // for calls to C. Supports the var-args backing area for register parms.
3239 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3240 #ifdef _LP64
3241 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3242 varargs_C_out_slots_killed(12);
3243 #else
3244 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3245 varargs_C_out_slots_killed( 7);
3246 #endif
3247
3248 // The after-PROLOG location of the return address. Location of
3249 // return address specifies a type (REG or STACK) and a number
3250 // representing the register number (i.e. - use a register name) or
3251 // stack slot.
3252 return_addr(REG R_I7); // Ret Addr is in register I7
3253
3254 // Body of function which returns an OptoRegs array locating
3255 // arguments either in registers or in stack slots for calling
3256 // java
3257 calling_convention %{
3258 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3259
3260 %}
3261
3262 // Body of function which returns an OptoRegs array locating
3263 // arguments either in registers or in stack slots for callin
3264 // C.
3265 c_calling_convention %{
3266 // This is obviously always outgoing
3267 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3268 %}
3269
3270 // Location of native (C/C++) and interpreter return values. This is specified to
3271 // be the same as Java. In the 32-bit VM, long values are actually returned from
3272 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3273 // to and from the register pairs is done by the appropriate call and epilog
3274 // opcodes. This simplifies the register allocator.
3275 c_return_value %{
3276 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3277 #ifdef _LP64
3278 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3279 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3280 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3281 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3282 #else // !_LP64
3283 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3284 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3285 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3286 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3287 #endif
3288 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3289 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3290 %}
3291
3292 // Location of compiled Java return values. Same as C
3293 return_value %{
3294 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3295 #ifdef _LP64
3296 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3297 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3298 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3299 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3300 #else // !_LP64
3301 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3302 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3303 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3304 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3305 #endif
3306 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3307 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3308 %}
3309
3310 %}
3311
3312
3313 //----------ATTRIBUTES---------------------------------------------------------
3314 //----------Operand Attributes-------------------------------------------------
3315 op_attrib op_cost(1); // Required cost attribute
3316
3317 //----------Instruction Attributes---------------------------------------------
3318 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3319 ins_attrib ins_size(32); // Required size attribute (in bits)
3320 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3321 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3322 // non-matching short branch variant of some
3323 // long branch?
3324
3325 //----------OPERANDS-----------------------------------------------------------
3326 // Operand definitions must precede instruction definitions for correct parsing
3327 // in the ADLC because operands constitute user defined types which are used in
3328 // instruction definitions.
3329
3330 //----------Simple Operands----------------------------------------------------
3331 // Immediate Operands
3332 // Integer Immediate: 32-bit
3333 operand immI() %{
3334 match(ConI);
3335
3336 op_cost(0);
3337 // formats are generated automatically for constants and base registers
3338 format %{ %}
3339 interface(CONST_INTER);
3340 %}
3341
3342 // Integer Immediate: 8-bit
3343 operand immI8() %{
3344 predicate(Assembler::is_simm(n->get_int(), 8));
3345 match(ConI);
3346 op_cost(0);
3347 format %{ %}
3348 interface(CONST_INTER);
3349 %}
3350
3351 // Integer Immediate: 13-bit
3352 operand immI13() %{
3353 predicate(Assembler::is_simm13(n->get_int()));
3354 match(ConI);
3355 op_cost(0);
3356
3357 format %{ %}
3358 interface(CONST_INTER);
3359 %}
3360
3361 // Integer Immediate: 13-bit minus 7
3362 operand immI13m7() %{
3363 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3364 match(ConI);
3365 op_cost(0);
3366
3367 format %{ %}
3368 interface(CONST_INTER);
3369 %}
3370
3371 // Integer Immediate: 16-bit
3372 operand immI16() %{
3373 predicate(Assembler::is_simm(n->get_int(), 16));
3374 match(ConI);
3375 op_cost(0);
3376 format %{ %}
3377 interface(CONST_INTER);
3378 %}
3379
3380 // Unsigned (positive) Integer Immediate: 13-bit
3381 operand immU13() %{
3382 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3383 match(ConI);
3384 op_cost(0);
3385
3386 format %{ %}
3387 interface(CONST_INTER);
3388 %}
3389
3390 // Integer Immediate: 6-bit
3391 operand immU6() %{
3392 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3393 match(ConI);
3394 op_cost(0);
3395 format %{ %}
3396 interface(CONST_INTER);
3397 %}
3398
3399 // Integer Immediate: 11-bit
3400 operand immI11() %{
3401 predicate(Assembler::is_simm(n->get_int(),11));
3402 match(ConI);
3403 op_cost(0);
3404 format %{ %}
3405 interface(CONST_INTER);
3406 %}
3407
3408 // Integer Immediate: 0-bit
3409 operand immI0() %{
3410 predicate(n->get_int() == 0);
3411 match(ConI);
3412 op_cost(0);
3413
3414 format %{ %}
3415 interface(CONST_INTER);
3416 %}
3417
3418 // Integer Immediate: the value 10
3419 operand immI10() %{
3420 predicate(n->get_int() == 10);
3421 match(ConI);
3422 op_cost(0);
3423
3424 format %{ %}
3425 interface(CONST_INTER);
3426 %}
3427
3428 // Integer Immediate: the values 0-31
3429 operand immU5() %{
3430 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3431 match(ConI);
3432 op_cost(0);
3433
3434 format %{ %}
3435 interface(CONST_INTER);
3436 %}
3437
3438 // Integer Immediate: the values 1-31
3439 operand immI_1_31() %{
3440 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3441 match(ConI);
3442 op_cost(0);
3443
3444 format %{ %}
3445 interface(CONST_INTER);
3446 %}
3447
3448 // Integer Immediate: the values 32-63
3449 operand immI_32_63() %{
3450 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3451 match(ConI);
3452 op_cost(0);
3453
3454 format %{ %}
3455 interface(CONST_INTER);
3456 %}
3457
3458 // Immediates for special shifts (sign extend)
3459
3460 // Integer Immediate: the value 16
3461 operand immI_16() %{
3462 predicate(n->get_int() == 16);
3463 match(ConI);
3464 op_cost(0);
3465
3466 format %{ %}
3467 interface(CONST_INTER);
3468 %}
3469
3470 // Integer Immediate: the value 24
3471 operand immI_24() %{
3472 predicate(n->get_int() == 24);
3473 match(ConI);
3474 op_cost(0);
3475
3476 format %{ %}
3477 interface(CONST_INTER);
3478 %}
3479
3480 // Integer Immediate: the value 255
3481 operand immI_255() %{
3482 predicate( n->get_int() == 255 );
3483 match(ConI);
3484 op_cost(0);
3485
3486 format %{ %}
3487 interface(CONST_INTER);
3488 %}
3489
3490 // Integer Immediate: the value 65535
3491 operand immI_65535() %{
3492 predicate(n->get_int() == 65535);
3493 match(ConI);
3494 op_cost(0);
3495
3496 format %{ %}
3497 interface(CONST_INTER);
3498 %}
3499
3500 // Long Immediate: the value FF
3501 operand immL_FF() %{
3502 predicate( n->get_long() == 0xFFL );
3503 match(ConL);
3504 op_cost(0);
3505
3506 format %{ %}
3507 interface(CONST_INTER);
3508 %}
3509
3510 // Long Immediate: the value FFFF
3511 operand immL_FFFF() %{
3512 predicate( n->get_long() == 0xFFFFL );
3513 match(ConL);
3514 op_cost(0);
3515
3516 format %{ %}
3517 interface(CONST_INTER);
3518 %}
3519
3520 // Pointer Immediate: 32 or 64-bit
3521 operand immP() %{
3522 match(ConP);
3523
3524 op_cost(5);
3525 // formats are generated automatically for constants and base registers
3526 format %{ %}
3527 interface(CONST_INTER);
3528 %}
3529
3530 #ifdef _LP64
3531 // Pointer Immediate: 64-bit
3532 operand immP_set() %{
3533 predicate(!VM_Version::is_niagara_plus());
3534 match(ConP);
3535
3536 op_cost(5);
3537 // formats are generated automatically for constants and base registers
3538 format %{ %}
3539 interface(CONST_INTER);
3540 %}
3541
3542 // Pointer Immediate: 64-bit
3543 // From Niagara2 processors on a load should be better than materializing.
3544 operand immP_load() %{
3545 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3546 match(ConP);
3547
3548 op_cost(5);
3549 // formats are generated automatically for constants and base registers
3550 format %{ %}
3551 interface(CONST_INTER);
3552 %}
3553
3554 // Pointer Immediate: 64-bit
3555 operand immP_no_oop_cheap() %{
3556 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3557 match(ConP);
3558
3559 op_cost(5);
3560 // formats are generated automatically for constants and base registers
3561 format %{ %}
3562 interface(CONST_INTER);
3563 %}
3564 #endif
3565
3566 operand immP13() %{
3567 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3568 match(ConP);
3569 op_cost(0);
3570
3571 format %{ %}
3572 interface(CONST_INTER);
3573 %}
3574
3575 operand immP0() %{
3576 predicate(n->get_ptr() == 0);
3577 match(ConP);
3578 op_cost(0);
3579
3580 format %{ %}
3581 interface(CONST_INTER);
3582 %}
3583
3584 operand immP_poll() %{
3585 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3586 match(ConP);
3587
3588 // formats are generated automatically for constants and base registers
3589 format %{ %}
3590 interface(CONST_INTER);
3591 %}
3592
3593 // Pointer Immediate
3594 operand immN()
3595 %{
3596 match(ConN);
3597
3598 op_cost(10);
3599 format %{ %}
3600 interface(CONST_INTER);
3601 %}
3602
3603 // NULL Pointer Immediate
3604 operand immN0()
3605 %{
3606 predicate(n->get_narrowcon() == 0);
3607 match(ConN);
3608
3609 op_cost(0);
3610 format %{ %}
3611 interface(CONST_INTER);
3612 %}
3613
3614 operand immL() %{
3615 match(ConL);
3616 op_cost(40);
3617 // formats are generated automatically for constants and base registers
3618 format %{ %}
3619 interface(CONST_INTER);
3620 %}
3621
3622 operand immL0() %{
3623 predicate(n->get_long() == 0L);
3624 match(ConL);
3625 op_cost(0);
3626 // formats are generated automatically for constants and base registers
3627 format %{ %}
3628 interface(CONST_INTER);
3629 %}
3630
3631 // Long Immediate: 13-bit
3632 operand immL13() %{
3633 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3634 match(ConL);
3635 op_cost(0);
3636
3637 format %{ %}
3638 interface(CONST_INTER);
3639 %}
3640
3641 // Long Immediate: 13-bit minus 7
3642 operand immL13m7() %{
3643 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3644 match(ConL);
3645 op_cost(0);
3646
3647 format %{ %}
3648 interface(CONST_INTER);
3649 %}
3650
3651 // Long Immediate: low 32-bit mask
3652 operand immL_32bits() %{
3653 predicate(n->get_long() == 0xFFFFFFFFL);
3654 match(ConL);
3655 op_cost(0);
3656
3657 format %{ %}
3658 interface(CONST_INTER);
3659 %}
3660
3661 // Long Immediate: cheap (materialize in <= 3 instructions)
3662 operand immL_cheap() %{
3663 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3664 match(ConL);
3665 op_cost(0);
3666
3667 format %{ %}
3668 interface(CONST_INTER);
3669 %}
3670
3671 // Long Immediate: expensive (materialize in > 3 instructions)
3672 operand immL_expensive() %{
3673 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3674 match(ConL);
3675 op_cost(0);
3676
3677 format %{ %}
3678 interface(CONST_INTER);
3679 %}
3680
3681 // Double Immediate
3682 operand immD() %{
3683 match(ConD);
3684
3685 op_cost(40);
3686 format %{ %}
3687 interface(CONST_INTER);
3688 %}
3689
3690 operand immD0() %{
3691 #ifdef _LP64
3692 // on 64-bit architectures this comparision is faster
3693 predicate(jlong_cast(n->getd()) == 0);
3694 #else
3695 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3696 #endif
3697 match(ConD);
3698
3699 op_cost(0);
3700 format %{ %}
3701 interface(CONST_INTER);
3702 %}
3703
3704 // Float Immediate
3705 operand immF() %{
3706 match(ConF);
3707
3708 op_cost(20);
3709 format %{ %}
3710 interface(CONST_INTER);
3711 %}
3712
3713 // Float Immediate: 0
3714 operand immF0() %{
3715 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3716 match(ConF);
3717
3718 op_cost(0);
3719 format %{ %}
3720 interface(CONST_INTER);
3721 %}
3722
3723 // Integer Register Operands
3724 // Integer Register
3725 operand iRegI() %{
3726 constraint(ALLOC_IN_RC(int_reg));
3727 match(RegI);
3728
3729 match(notemp_iRegI);
3730 match(g1RegI);
3731 match(o0RegI);
3732 match(iRegIsafe);
3733
3734 format %{ %}
3735 interface(REG_INTER);
3736 %}
3737
3738 operand notemp_iRegI() %{
3739 constraint(ALLOC_IN_RC(notemp_int_reg));
3740 match(RegI);
3741
3742 match(o0RegI);
3743
3744 format %{ %}
3745 interface(REG_INTER);
3746 %}
3747
3748 operand o0RegI() %{
3749 constraint(ALLOC_IN_RC(o0_regI));
3750 match(iRegI);
3751
3752 format %{ %}
3753 interface(REG_INTER);
3754 %}
3755
3756 // Pointer Register
3757 operand iRegP() %{
3758 constraint(ALLOC_IN_RC(ptr_reg));
3759 match(RegP);
3760
3761 match(lock_ptr_RegP);
3762 match(g1RegP);
3763 match(g2RegP);
3764 match(g3RegP);
3765 match(g4RegP);
3766 match(i0RegP);
3767 match(o0RegP);
3768 match(o1RegP);
3769 match(l7RegP);
3770
3771 format %{ %}
3772 interface(REG_INTER);
3773 %}
3774
3775 operand sp_ptr_RegP() %{
3776 constraint(ALLOC_IN_RC(sp_ptr_reg));
3777 match(RegP);
3778 match(iRegP);
3779
3780 format %{ %}
3781 interface(REG_INTER);
3782 %}
3783
3784 operand lock_ptr_RegP() %{
3785 constraint(ALLOC_IN_RC(lock_ptr_reg));
3786 match(RegP);
3787 match(i0RegP);
3788 match(o0RegP);
3789 match(o1RegP);
3790 match(l7RegP);
3791
3792 format %{ %}
3793 interface(REG_INTER);
3794 %}
3795
3796 operand g1RegP() %{
3797 constraint(ALLOC_IN_RC(g1_regP));
3798 match(iRegP);
3799
3800 format %{ %}
3801 interface(REG_INTER);
3802 %}
3803
3804 operand g2RegP() %{
3805 constraint(ALLOC_IN_RC(g2_regP));
3806 match(iRegP);
3807
3808 format %{ %}
3809 interface(REG_INTER);
3810 %}
3811
3812 operand g3RegP() %{
3813 constraint(ALLOC_IN_RC(g3_regP));
3814 match(iRegP);
3815
3816 format %{ %}
3817 interface(REG_INTER);
3818 %}
3819
3820 operand g1RegI() %{
3821 constraint(ALLOC_IN_RC(g1_regI));
3822 match(iRegI);
3823
3824 format %{ %}
3825 interface(REG_INTER);
3826 %}
3827
3828 operand g3RegI() %{
3829 constraint(ALLOC_IN_RC(g3_regI));
3830 match(iRegI);
3831
3832 format %{ %}
3833 interface(REG_INTER);
3834 %}
3835
3836 operand g4RegI() %{
3837 constraint(ALLOC_IN_RC(g4_regI));
3838 match(iRegI);
3839
3840 format %{ %}
3841 interface(REG_INTER);
3842 %}
3843
3844 operand g4RegP() %{
3845 constraint(ALLOC_IN_RC(g4_regP));
3846 match(iRegP);
3847
3848 format %{ %}
3849 interface(REG_INTER);
3850 %}
3851
3852 operand i0RegP() %{
3853 constraint(ALLOC_IN_RC(i0_regP));
3854 match(iRegP);
3855
3856 format %{ %}
3857 interface(REG_INTER);
3858 %}
3859
3860 operand o0RegP() %{
3861 constraint(ALLOC_IN_RC(o0_regP));
3862 match(iRegP);
3863
3864 format %{ %}
3865 interface(REG_INTER);
3866 %}
3867
3868 operand o1RegP() %{
3869 constraint(ALLOC_IN_RC(o1_regP));
3870 match(iRegP);
3871
3872 format %{ %}
3873 interface(REG_INTER);
3874 %}
3875
3876 operand o2RegP() %{
3877 constraint(ALLOC_IN_RC(o2_regP));
3878 match(iRegP);
3879
3880 format %{ %}
3881 interface(REG_INTER);
3882 %}
3883
3884 operand o7RegP() %{
3885 constraint(ALLOC_IN_RC(o7_regP));
3886 match(iRegP);
3887
3888 format %{ %}
3889 interface(REG_INTER);
3890 %}
3891
3892 operand l7RegP() %{
3893 constraint(ALLOC_IN_RC(l7_regP));
3894 match(iRegP);
3895
3896 format %{ %}
3897 interface(REG_INTER);
3898 %}
3899
3900 operand o7RegI() %{
3901 constraint(ALLOC_IN_RC(o7_regI));
3902 match(iRegI);
3903
3904 format %{ %}
3905 interface(REG_INTER);
3906 %}
3907
3908 operand iRegN() %{
3909 constraint(ALLOC_IN_RC(int_reg));
3910 match(RegN);
3911
3912 format %{ %}
3913 interface(REG_INTER);
3914 %}
3915
3916 // Long Register
3917 operand iRegL() %{
3918 constraint(ALLOC_IN_RC(long_reg));
3919 match(RegL);
3920
3921 format %{ %}
3922 interface(REG_INTER);
3923 %}
3924
3925 operand o2RegL() %{
3926 constraint(ALLOC_IN_RC(o2_regL));
3927 match(iRegL);
3928
3929 format %{ %}
3930 interface(REG_INTER);
3931 %}
3932
3933 operand o7RegL() %{
3934 constraint(ALLOC_IN_RC(o7_regL));
3935 match(iRegL);
3936
3937 format %{ %}
3938 interface(REG_INTER);
3939 %}
3940
3941 operand g1RegL() %{
3942 constraint(ALLOC_IN_RC(g1_regL));
3943 match(iRegL);
3944
3945 format %{ %}
3946 interface(REG_INTER);
3947 %}
3948
3949 operand g3RegL() %{
3950 constraint(ALLOC_IN_RC(g3_regL));
3951 match(iRegL);
3952
3953 format %{ %}
3954 interface(REG_INTER);
3955 %}
3956
3957 // Int Register safe
3958 // This is 64bit safe
3959 operand iRegIsafe() %{
3960 constraint(ALLOC_IN_RC(long_reg));
3961
3962 match(iRegI);
3963
3964 format %{ %}
3965 interface(REG_INTER);
3966 %}
3967
3968 // Condition Code Flag Register
3969 operand flagsReg() %{
3970 constraint(ALLOC_IN_RC(int_flags));
3971 match(RegFlags);
3972
3973 format %{ "ccr" %} // both ICC and XCC
3974 interface(REG_INTER);
3975 %}
3976
3977 // Condition Code Register, unsigned comparisons.
3978 operand flagsRegU() %{
3979 constraint(ALLOC_IN_RC(int_flags));
3980 match(RegFlags);
3981
3982 format %{ "icc_U" %}
3983 interface(REG_INTER);
3984 %}
3985
3986 // Condition Code Register, pointer comparisons.
3987 operand flagsRegP() %{
3988 constraint(ALLOC_IN_RC(int_flags));
3989 match(RegFlags);
3990
3991 #ifdef _LP64
3992 format %{ "xcc_P" %}
3993 #else
3994 format %{ "icc_P" %}
3995 #endif
3996 interface(REG_INTER);
3997 %}
3998
3999 // Condition Code Register, long comparisons.
4000 operand flagsRegL() %{
4001 constraint(ALLOC_IN_RC(int_flags));
4002 match(RegFlags);
4003
4004 format %{ "xcc_L" %}
4005 interface(REG_INTER);
4006 %}
4007
4008 // Condition Code Register, floating comparisons, unordered same as "less".
4009 operand flagsRegF() %{
4010 constraint(ALLOC_IN_RC(float_flags));
4011 match(RegFlags);
4012 match(flagsRegF0);
4013
4014 format %{ %}
4015 interface(REG_INTER);
4016 %}
4017
4018 operand flagsRegF0() %{
4019 constraint(ALLOC_IN_RC(float_flag0));
4020 match(RegFlags);
4021
4022 format %{ %}
4023 interface(REG_INTER);
4024 %}
4025
4026
4027 // Condition Code Flag Register used by long compare
4028 operand flagsReg_long_LTGE() %{
4029 constraint(ALLOC_IN_RC(int_flags));
4030 match(RegFlags);
4031 format %{ "icc_LTGE" %}
4032 interface(REG_INTER);
4033 %}
4034 operand flagsReg_long_EQNE() %{
4035 constraint(ALLOC_IN_RC(int_flags));
4036 match(RegFlags);
4037 format %{ "icc_EQNE" %}
4038 interface(REG_INTER);
4039 %}
4040 operand flagsReg_long_LEGT() %{
4041 constraint(ALLOC_IN_RC(int_flags));
4042 match(RegFlags);
4043 format %{ "icc_LEGT" %}
4044 interface(REG_INTER);
4045 %}
4046
4047
4048 operand regD() %{
4049 constraint(ALLOC_IN_RC(dflt_reg));
4050 match(RegD);
4051
4052 match(regD_low);
4053
4054 format %{ %}
4055 interface(REG_INTER);
4056 %}
4057
4058 operand regF() %{
4059 constraint(ALLOC_IN_RC(sflt_reg));
4060 match(RegF);
4061
4062 format %{ %}
4063 interface(REG_INTER);
4064 %}
4065
4066 operand regD_low() %{
4067 constraint(ALLOC_IN_RC(dflt_low_reg));
4068 match(regD);
4069
4070 format %{ %}
4071 interface(REG_INTER);
4072 %}
4073
4074 // Special Registers
4075
4076 // Method Register
4077 operand inline_cache_regP(iRegP reg) %{
4078 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4079 match(reg);
4080 format %{ %}
4081 interface(REG_INTER);
4082 %}
4083
4084 operand interpreter_method_oop_regP(iRegP reg) %{
4085 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4086 match(reg);
4087 format %{ %}
4088 interface(REG_INTER);
4089 %}
4090
4091
4092 //----------Complex Operands---------------------------------------------------
4093 // Indirect Memory Reference
4094 operand indirect(sp_ptr_RegP reg) %{
4095 constraint(ALLOC_IN_RC(sp_ptr_reg));
4096 match(reg);
4097
4098 op_cost(100);
4099 format %{ "[$reg]" %}
4100 interface(MEMORY_INTER) %{
4101 base($reg);
4102 index(0x0);
4103 scale(0x0);
4104 disp(0x0);
4105 %}
4106 %}
4107
4108 // Indirect with simm13 Offset
4109 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4110 constraint(ALLOC_IN_RC(sp_ptr_reg));
4111 match(AddP reg offset);
4112
4113 op_cost(100);
4114 format %{ "[$reg + $offset]" %}
4115 interface(MEMORY_INTER) %{
4116 base($reg);
4117 index(0x0);
4118 scale(0x0);
4119 disp($offset);
4120 %}
4121 %}
4122
4123 // Indirect with simm13 Offset minus 7
4124 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4125 constraint(ALLOC_IN_RC(sp_ptr_reg));
4126 match(AddP reg offset);
4127
4128 op_cost(100);
4129 format %{ "[$reg + $offset]" %}
4130 interface(MEMORY_INTER) %{
4131 base($reg);
4132 index(0x0);
4133 scale(0x0);
4134 disp($offset);
4135 %}
4136 %}
4137
4138 // Note: Intel has a swapped version also, like this:
4139 //operand indOffsetX(iRegI reg, immP offset) %{
4140 // constraint(ALLOC_IN_RC(int_reg));
4141 // match(AddP offset reg);
4142 //
4143 // op_cost(100);
4144 // format %{ "[$reg + $offset]" %}
4145 // interface(MEMORY_INTER) %{
4146 // base($reg);
4147 // index(0x0);
4148 // scale(0x0);
4149 // disp($offset);
4150 // %}
4151 //%}
4152 //// However, it doesn't make sense for SPARC, since
4153 // we have no particularly good way to embed oops in
4154 // single instructions.
4155
4156 // Indirect with Register Index
4157 operand indIndex(iRegP addr, iRegX index) %{
4158 constraint(ALLOC_IN_RC(ptr_reg));
4159 match(AddP addr index);
4160
4161 op_cost(100);
4162 format %{ "[$addr + $index]" %}
4163 interface(MEMORY_INTER) %{
4164 base($addr);
4165 index($index);
4166 scale(0x0);
4167 disp(0x0);
4168 %}
4169 %}
4170
4171 //----------Special Memory Operands--------------------------------------------
4172 // Stack Slot Operand - This operand is used for loading and storing temporary
4173 // values on the stack where a match requires a value to
4174 // flow through memory.
4175 operand stackSlotI(sRegI reg) %{
4176 constraint(ALLOC_IN_RC(stack_slots));
4177 op_cost(100);
4178 //match(RegI);
4179 format %{ "[$reg]" %}
4180 interface(MEMORY_INTER) %{
4181 base(0xE); // R_SP
4182 index(0x0);
4183 scale(0x0);
4184 disp($reg); // Stack Offset
4185 %}
4186 %}
4187
4188 operand stackSlotP(sRegP reg) %{
4189 constraint(ALLOC_IN_RC(stack_slots));
4190 op_cost(100);
4191 //match(RegP);
4192 format %{ "[$reg]" %}
4193 interface(MEMORY_INTER) %{
4194 base(0xE); // R_SP
4195 index(0x0);
4196 scale(0x0);
4197 disp($reg); // Stack Offset
4198 %}
4199 %}
4200
4201 operand stackSlotF(sRegF reg) %{
4202 constraint(ALLOC_IN_RC(stack_slots));
4203 op_cost(100);
4204 //match(RegF);
4205 format %{ "[$reg]" %}
4206 interface(MEMORY_INTER) %{
4207 base(0xE); // R_SP
4208 index(0x0);
4209 scale(0x0);
4210 disp($reg); // Stack Offset
4211 %}
4212 %}
4213 operand stackSlotD(sRegD reg) %{
4214 constraint(ALLOC_IN_RC(stack_slots));
4215 op_cost(100);
4216 //match(RegD);
4217 format %{ "[$reg]" %}
4218 interface(MEMORY_INTER) %{
4219 base(0xE); // R_SP
4220 index(0x0);
4221 scale(0x0);
4222 disp($reg); // Stack Offset
4223 %}
4224 %}
4225 operand stackSlotL(sRegL reg) %{
4226 constraint(ALLOC_IN_RC(stack_slots));
4227 op_cost(100);
4228 //match(RegL);
4229 format %{ "[$reg]" %}
4230 interface(MEMORY_INTER) %{
4231 base(0xE); // R_SP
4232 index(0x0);
4233 scale(0x0);
4234 disp($reg); // Stack Offset
4235 %}
4236 %}
4237
4238 // Operands for expressing Control Flow
4239 // NOTE: Label is a predefined operand which should not be redefined in
4240 // the AD file. It is generically handled within the ADLC.
4241
4242 //----------Conditional Branch Operands----------------------------------------
4243 // Comparison Op - This is the operation of the comparison, and is limited to
4244 // the following set of codes:
4245 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4246 //
4247 // Other attributes of the comparison, such as unsignedness, are specified
4248 // by the comparison instruction that sets a condition code flags register.
4249 // That result is represented by a flags operand whose subtype is appropriate
4250 // to the unsignedness (etc.) of the comparison.
4251 //
4252 // Later, the instruction which matches both the Comparison Op (a Bool) and
4253 // the flags (produced by the Cmp) specifies the coding of the comparison op
4254 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4255
4256 operand cmpOp() %{
4257 match(Bool);
4258
4259 format %{ "" %}
4260 interface(COND_INTER) %{
4261 equal(0x1);
4262 not_equal(0x9);
4263 less(0x3);
4264 greater_equal(0xB);
4265 less_equal(0x2);
4266 greater(0xA);
4267 %}
4268 %}
4269
4270 // Comparison Op, unsigned
4271 operand cmpOpU() %{
4272 match(Bool);
4273
4274 format %{ "u" %}
4275 interface(COND_INTER) %{
4276 equal(0x1);
4277 not_equal(0x9);
4278 less(0x5);
4279 greater_equal(0xD);
4280 less_equal(0x4);
4281 greater(0xC);
4282 %}
4283 %}
4284
4285 // Comparison Op, pointer (same as unsigned)
4286 operand cmpOpP() %{
4287 match(Bool);
4288
4289 format %{ "p" %}
4290 interface(COND_INTER) %{
4291 equal(0x1);
4292 not_equal(0x9);
4293 less(0x5);
4294 greater_equal(0xD);
4295 less_equal(0x4);
4296 greater(0xC);
4297 %}
4298 %}
4299
4300 // Comparison Op, branch-register encoding
4301 operand cmpOp_reg() %{
4302 match(Bool);
4303
4304 format %{ "" %}
4305 interface(COND_INTER) %{
4306 equal (0x1);
4307 not_equal (0x5);
4308 less (0x3);
4309 greater_equal(0x7);
4310 less_equal (0x2);
4311 greater (0x6);
4312 %}
4313 %}
4314
4315 // Comparison Code, floating, unordered same as less
4316 operand cmpOpF() %{
4317 match(Bool);
4318
4319 format %{ "fl" %}
4320 interface(COND_INTER) %{
4321 equal(0x9);
4322 not_equal(0x1);
4323 less(0x3);
4324 greater_equal(0xB);
4325 less_equal(0xE);
4326 greater(0x6);
4327 %}
4328 %}
4329
4330 // Used by long compare
4331 operand cmpOp_commute() %{
4332 match(Bool);
4333
4334 format %{ "" %}
4335 interface(COND_INTER) %{
4336 equal(0x1);
4337 not_equal(0x9);
4338 less(0xA);
4339 greater_equal(0x2);
4340 less_equal(0xB);
4341 greater(0x3);
4342 %}
4343 %}
4344
4345 //----------OPERAND CLASSES----------------------------------------------------
4346 // Operand Classes are groups of operands that are used to simplify
4347 // instruction definitions by not requiring the AD writer to specify separate
4348 // instructions for every form of operand when the instruction accepts
4349 // multiple operand types with the same basic encoding and format. The classic
4350 // case of this is memory operands.
4351 opclass memory( indirect, indOffset13, indIndex );
4352 opclass indIndexMemory( indIndex );
4353
4354 //----------PIPELINE-----------------------------------------------------------
4355 pipeline %{
4356
4357 //----------ATTRIBUTES---------------------------------------------------------
4358 attributes %{
4359 fixed_size_instructions; // Fixed size instructions
4360 branch_has_delay_slot; // Branch has delay slot following
4361 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4362 instruction_unit_size = 4; // An instruction is 4 bytes long
4363 instruction_fetch_unit_size = 16; // The processor fetches one line
4364 instruction_fetch_units = 1; // of 16 bytes
4365
4366 // List of nop instructions
4367 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4368 %}
4369
4370 //----------RESOURCES----------------------------------------------------------
4371 // Resources are the functional units available to the machine
4372 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4373
4374 //----------PIPELINE DESCRIPTION-----------------------------------------------
4375 // Pipeline Description specifies the stages in the machine's pipeline
4376
4377 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4378
4379 //----------PIPELINE CLASSES---------------------------------------------------
4380 // Pipeline Classes describe the stages in which input and output are
4381 // referenced by the hardware pipeline.
4382
4383 // Integer ALU reg-reg operation
4384 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4385 single_instruction;
4386 dst : E(write);
4387 src1 : R(read);
4388 src2 : R(read);
4389 IALU : R;
4390 %}
4391
4392 // Integer ALU reg-reg long operation
4393 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4394 instruction_count(2);
4395 dst : E(write);
4396 src1 : R(read);
4397 src2 : R(read);
4398 IALU : R;
4399 IALU : R;
4400 %}
4401
4402 // Integer ALU reg-reg long dependent operation
4403 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4404 instruction_count(1); multiple_bundles;
4405 dst : E(write);
4406 src1 : R(read);
4407 src2 : R(read);
4408 cr : E(write);
4409 IALU : R(2);
4410 %}
4411
4412 // Integer ALU reg-imm operaion
4413 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4414 single_instruction;
4415 dst : E(write);
4416 src1 : R(read);
4417 IALU : R;
4418 %}
4419
4420 // Integer ALU reg-reg operation with condition code
4421 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4422 single_instruction;
4423 dst : E(write);
4424 cr : E(write);
4425 src1 : R(read);
4426 src2 : R(read);
4427 IALU : R;
4428 %}
4429
4430 // Integer ALU reg-imm operation with condition code
4431 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4432 single_instruction;
4433 dst : E(write);
4434 cr : E(write);
4435 src1 : R(read);
4436 IALU : R;
4437 %}
4438
4439 // Integer ALU zero-reg operation
4440 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4441 single_instruction;
4442 dst : E(write);
4443 src2 : R(read);
4444 IALU : R;
4445 %}
4446
4447 // Integer ALU zero-reg operation with condition code only
4448 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4449 single_instruction;
4450 cr : E(write);
4451 src : R(read);
4452 IALU : R;
4453 %}
4454
4455 // Integer ALU reg-reg operation with condition code only
4456 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4457 single_instruction;
4458 cr : E(write);
4459 src1 : R(read);
4460 src2 : R(read);
4461 IALU : R;
4462 %}
4463
4464 // Integer ALU reg-imm operation with condition code only
4465 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4466 single_instruction;
4467 cr : E(write);
4468 src1 : R(read);
4469 IALU : R;
4470 %}
4471
4472 // Integer ALU reg-reg-zero operation with condition code only
4473 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4474 single_instruction;
4475 cr : E(write);
4476 src1 : R(read);
4477 src2 : R(read);
4478 IALU : R;
4479 %}
4480
4481 // Integer ALU reg-imm-zero operation with condition code only
4482 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4483 single_instruction;
4484 cr : E(write);
4485 src1 : R(read);
4486 IALU : R;
4487 %}
4488
4489 // Integer ALU reg-reg operation with condition code, src1 modified
4490 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4491 single_instruction;
4492 cr : E(write);
4493 src1 : E(write);
4494 src1 : R(read);
4495 src2 : R(read);
4496 IALU : R;
4497 %}
4498
4499 // Integer ALU reg-imm operation with condition code, src1 modified
4500 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4501 single_instruction;
4502 cr : E(write);
4503 src1 : E(write);
4504 src1 : R(read);
4505 IALU : R;
4506 %}
4507
4508 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4509 multiple_bundles;
4510 dst : E(write)+4;
4511 cr : E(write);
4512 src1 : R(read);
4513 src2 : R(read);
4514 IALU : R(3);
4515 BR : R(2);
4516 %}
4517
4518 // Integer ALU operation
4519 pipe_class ialu_none(iRegI dst) %{
4520 single_instruction;
4521 dst : E(write);
4522 IALU : R;
4523 %}
4524
4525 // Integer ALU reg operation
4526 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4527 single_instruction; may_have_no_code;
4528 dst : E(write);
4529 src : R(read);
4530 IALU : R;
4531 %}
4532
4533 // Integer ALU reg conditional operation
4534 // This instruction has a 1 cycle stall, and cannot execute
4535 // in the same cycle as the instruction setting the condition
4536 // code. We kludge this by pretending to read the condition code
4537 // 1 cycle earlier, and by marking the functional units as busy
4538 // for 2 cycles with the result available 1 cycle later than
4539 // is really the case.
4540 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4541 single_instruction;
4542 op2_out : C(write);
4543 op1 : R(read);
4544 cr : R(read); // This is really E, with a 1 cycle stall
4545 BR : R(2);
4546 MS : R(2);
4547 %}
4548
4549 #ifdef _LP64
4550 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4551 instruction_count(1); multiple_bundles;
4552 dst : C(write)+1;
4553 src : R(read)+1;
4554 IALU : R(1);
4555 BR : E(2);
4556 MS : E(2);
4557 %}
4558 #endif
4559
4560 // Integer ALU reg operation
4561 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4562 single_instruction; may_have_no_code;
4563 dst : E(write);
4564 src : R(read);
4565 IALU : R;
4566 %}
4567 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4568 single_instruction; may_have_no_code;
4569 dst : E(write);
4570 src : R(read);
4571 IALU : R;
4572 %}
4573
4574 // Two integer ALU reg operations
4575 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4576 instruction_count(2);
4577 dst : E(write);
4578 src : R(read);
4579 A0 : R;
4580 A1 : R;
4581 %}
4582
4583 // Two integer ALU reg operations
4584 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4585 instruction_count(2); may_have_no_code;
4586 dst : E(write);
4587 src : R(read);
4588 A0 : R;
4589 A1 : R;
4590 %}
4591
4592 // Integer ALU imm operation
4593 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4594 single_instruction;
4595 dst : E(write);
4596 IALU : R;
4597 %}
4598
4599 // Integer ALU reg-reg with carry operation
4600 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4601 single_instruction;
4602 dst : E(write);
4603 src1 : R(read);
4604 src2 : R(read);
4605 IALU : R;
4606 %}
4607
4608 // Integer ALU cc operation
4609 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4610 single_instruction;
4611 dst : E(write);
4612 cc : R(read);
4613 IALU : R;
4614 %}
4615
4616 // Integer ALU cc / second IALU operation
4617 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4618 instruction_count(1); multiple_bundles;
4619 dst : E(write)+1;
4620 src : R(read);
4621 IALU : R;
4622 %}
4623
4624 // Integer ALU cc / second IALU operation
4625 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4626 instruction_count(1); multiple_bundles;
4627 dst : E(write)+1;
4628 p : R(read);
4629 q : R(read);
4630 IALU : R;
4631 %}
4632
4633 // Integer ALU hi-lo-reg operation
4634 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4635 instruction_count(1); multiple_bundles;
4636 dst : E(write)+1;
4637 IALU : R(2);
4638 %}
4639
4640 // Float ALU hi-lo-reg operation (with temp)
4641 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4642 instruction_count(1); multiple_bundles;
4643 dst : E(write)+1;
4644 IALU : R(2);
4645 %}
4646
4647 // Long Constant
4648 pipe_class loadConL( iRegL dst, immL src ) %{
4649 instruction_count(2); multiple_bundles;
4650 dst : E(write)+1;
4651 IALU : R(2);
4652 IALU : R(2);
4653 %}
4654
4655 // Pointer Constant
4656 pipe_class loadConP( iRegP dst, immP src ) %{
4657 instruction_count(0); multiple_bundles;
4658 fixed_latency(6);
4659 %}
4660
4661 // Polling Address
4662 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4663 #ifdef _LP64
4664 instruction_count(0); multiple_bundles;
4665 fixed_latency(6);
4666 #else
4667 dst : E(write);
4668 IALU : R;
4669 #endif
4670 %}
4671
4672 // Long Constant small
4673 pipe_class loadConLlo( iRegL dst, immL src ) %{
4674 instruction_count(2);
4675 dst : E(write);
4676 IALU : R;
4677 IALU : R;
4678 %}
4679
4680 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4681 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4682 instruction_count(1); multiple_bundles;
4683 src : R(read);
4684 dst : M(write)+1;
4685 IALU : R;
4686 MS : E;
4687 %}
4688
4689 // Integer ALU nop operation
4690 pipe_class ialu_nop() %{
4691 single_instruction;
4692 IALU : R;
4693 %}
4694
4695 // Integer ALU nop operation
4696 pipe_class ialu_nop_A0() %{
4697 single_instruction;
4698 A0 : R;
4699 %}
4700
4701 // Integer ALU nop operation
4702 pipe_class ialu_nop_A1() %{
4703 single_instruction;
4704 A1 : R;
4705 %}
4706
4707 // Integer Multiply reg-reg operation
4708 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4709 single_instruction;
4710 dst : E(write);
4711 src1 : R(read);
4712 src2 : R(read);
4713 MS : R(5);
4714 %}
4715
4716 // Integer Multiply reg-imm operation
4717 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4718 single_instruction;
4719 dst : E(write);
4720 src1 : R(read);
4721 MS : R(5);
4722 %}
4723
4724 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4725 single_instruction;
4726 dst : E(write)+4;
4727 src1 : R(read);
4728 src2 : R(read);
4729 MS : R(6);
4730 %}
4731
4732 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4733 single_instruction;
4734 dst : E(write)+4;
4735 src1 : R(read);
4736 MS : R(6);
4737 %}
4738
4739 // Integer Divide reg-reg
4740 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4741 instruction_count(1); multiple_bundles;
4742 dst : E(write);
4743 temp : E(write);
4744 src1 : R(read);
4745 src2 : R(read);
4746 temp : R(read);
4747 MS : R(38);
4748 %}
4749
4750 // Integer Divide reg-imm
4751 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4752 instruction_count(1); multiple_bundles;
4753 dst : E(write);
4754 temp : E(write);
4755 src1 : R(read);
4756 temp : R(read);
4757 MS : R(38);
4758 %}
4759
4760 // Long Divide
4761 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4762 dst : E(write)+71;
4763 src1 : R(read);
4764 src2 : R(read)+1;
4765 MS : R(70);
4766 %}
4767
4768 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4769 dst : E(write)+71;
4770 src1 : R(read);
4771 MS : R(70);
4772 %}
4773
4774 // Floating Point Add Float
4775 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4776 single_instruction;
4777 dst : X(write);
4778 src1 : E(read);
4779 src2 : E(read);
4780 FA : R;
4781 %}
4782
4783 // Floating Point Add Double
4784 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4785 single_instruction;
4786 dst : X(write);
4787 src1 : E(read);
4788 src2 : E(read);
4789 FA : R;
4790 %}
4791
4792 // Floating Point Conditional Move based on integer flags
4793 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4794 single_instruction;
4795 dst : X(write);
4796 src : E(read);
4797 cr : R(read);
4798 FA : R(2);
4799 BR : R(2);
4800 %}
4801
4802 // Floating Point Conditional Move based on integer flags
4803 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4804 single_instruction;
4805 dst : X(write);
4806 src : E(read);
4807 cr : R(read);
4808 FA : R(2);
4809 BR : R(2);
4810 %}
4811
4812 // Floating Point Multiply Float
4813 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4814 single_instruction;
4815 dst : X(write);
4816 src1 : E(read);
4817 src2 : E(read);
4818 FM : R;
4819 %}
4820
4821 // Floating Point Multiply Double
4822 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4823 single_instruction;
4824 dst : X(write);
4825 src1 : E(read);
4826 src2 : E(read);
4827 FM : R;
4828 %}
4829
4830 // Floating Point Divide Float
4831 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4832 single_instruction;
4833 dst : X(write);
4834 src1 : E(read);
4835 src2 : E(read);
4836 FM : R;
4837 FDIV : C(14);
4838 %}
4839
4840 // Floating Point Divide Double
4841 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4842 single_instruction;
4843 dst : X(write);
4844 src1 : E(read);
4845 src2 : E(read);
4846 FM : R;
4847 FDIV : C(17);
4848 %}
4849
4850 // Floating Point Move/Negate/Abs Float
4851 pipe_class faddF_reg(regF dst, regF src) %{
4852 single_instruction;
4853 dst : W(write);
4854 src : E(read);
4855 FA : R(1);
4856 %}
4857
4858 // Floating Point Move/Negate/Abs Double
4859 pipe_class faddD_reg(regD dst, regD src) %{
4860 single_instruction;
4861 dst : W(write);
4862 src : E(read);
4863 FA : R;
4864 %}
4865
4866 // Floating Point Convert F->D
4867 pipe_class fcvtF2D(regD dst, regF src) %{
4868 single_instruction;
4869 dst : X(write);
4870 src : E(read);
4871 FA : R;
4872 %}
4873
4874 // Floating Point Convert I->D
4875 pipe_class fcvtI2D(regD dst, regF src) %{
4876 single_instruction;
4877 dst : X(write);
4878 src : E(read);
4879 FA : R;
4880 %}
4881
4882 // Floating Point Convert LHi->D
4883 pipe_class fcvtLHi2D(regD dst, regD src) %{
4884 single_instruction;
4885 dst : X(write);
4886 src : E(read);
4887 FA : R;
4888 %}
4889
4890 // Floating Point Convert L->D
4891 pipe_class fcvtL2D(regD dst, regF src) %{
4892 single_instruction;
4893 dst : X(write);
4894 src : E(read);
4895 FA : R;
4896 %}
4897
4898 // Floating Point Convert L->F
4899 pipe_class fcvtL2F(regD dst, regF src) %{
4900 single_instruction;
4901 dst : X(write);
4902 src : E(read);
4903 FA : R;
4904 %}
4905
4906 // Floating Point Convert D->F
4907 pipe_class fcvtD2F(regD dst, regF src) %{
4908 single_instruction;
4909 dst : X(write);
4910 src : E(read);
4911 FA : R;
4912 %}
4913
4914 // Floating Point Convert I->L
4915 pipe_class fcvtI2L(regD dst, regF src) %{
4916 single_instruction;
4917 dst : X(write);
4918 src : E(read);
4919 FA : R;
4920 %}
4921
4922 // Floating Point Convert D->F
4923 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4924 instruction_count(1); multiple_bundles;
4925 dst : X(write)+6;
4926 src : E(read);
4927 FA : R;
4928 %}
4929
4930 // Floating Point Convert D->L
4931 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4932 instruction_count(1); multiple_bundles;
4933 dst : X(write)+6;
4934 src : E(read);
4935 FA : R;
4936 %}
4937
4938 // Floating Point Convert F->I
4939 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4940 instruction_count(1); multiple_bundles;
4941 dst : X(write)+6;
4942 src : E(read);
4943 FA : R;
4944 %}
4945
4946 // Floating Point Convert F->L
4947 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4948 instruction_count(1); multiple_bundles;
4949 dst : X(write)+6;
4950 src : E(read);
4951 FA : R;
4952 %}
4953
4954 // Floating Point Convert I->F
4955 pipe_class fcvtI2F(regF dst, regF src) %{
4956 single_instruction;
4957 dst : X(write);
4958 src : E(read);
4959 FA : R;
4960 %}
4961
4962 // Floating Point Compare
4963 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4964 single_instruction;
4965 cr : X(write);
4966 src1 : E(read);
4967 src2 : E(read);
4968 FA : R;
4969 %}
4970
4971 // Floating Point Compare
4972 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4973 single_instruction;
4974 cr : X(write);
4975 src1 : E(read);
4976 src2 : E(read);
4977 FA : R;
4978 %}
4979
4980 // Floating Add Nop
4981 pipe_class fadd_nop() %{
4982 single_instruction;
4983 FA : R;
4984 %}
4985
4986 // Integer Store to Memory
4987 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4988 single_instruction;
4989 mem : R(read);
4990 src : C(read);
4991 MS : R;
4992 %}
4993
4994 // Integer Store to Memory
4995 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4996 single_instruction;
4997 mem : R(read);
4998 src : C(read);
4999 MS : R;
5000 %}
5001
5002 // Integer Store Zero to Memory
5003 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5004 single_instruction;
5005 mem : R(read);
5006 MS : R;
5007 %}
5008
5009 // Special Stack Slot Store
5010 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5011 single_instruction;
5012 stkSlot : R(read);
5013 src : C(read);
5014 MS : R;
5015 %}
5016
5017 // Special Stack Slot Store
5018 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5019 instruction_count(2); multiple_bundles;
5020 stkSlot : R(read);
5021 src : C(read);
5022 MS : R(2);
5023 %}
5024
5025 // Float Store
5026 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5027 single_instruction;
5028 mem : R(read);
5029 src : C(read);
5030 MS : R;
5031 %}
5032
5033 // Float Store
5034 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5035 single_instruction;
5036 mem : R(read);
5037 MS : R;
5038 %}
5039
5040 // Double Store
5041 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5042 instruction_count(1);
5043 mem : R(read);
5044 src : C(read);
5045 MS : R;
5046 %}
5047
5048 // Double Store
5049 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5050 single_instruction;
5051 mem : R(read);
5052 MS : R;
5053 %}
5054
5055 // Special Stack Slot Float Store
5056 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5057 single_instruction;
5058 stkSlot : R(read);
5059 src : C(read);
5060 MS : R;
5061 %}
5062
5063 // Special Stack Slot Double Store
5064 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5065 single_instruction;
5066 stkSlot : R(read);
5067 src : C(read);
5068 MS : R;
5069 %}
5070
5071 // Integer Load (when sign bit propagation not needed)
5072 pipe_class iload_mem(iRegI dst, memory mem) %{
5073 single_instruction;
5074 mem : R(read);
5075 dst : C(write);
5076 MS : R;
5077 %}
5078
5079 // Integer Load from stack operand
5080 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5081 single_instruction;
5082 mem : R(read);
5083 dst : C(write);
5084 MS : R;
5085 %}
5086
5087 // Integer Load (when sign bit propagation or masking is needed)
5088 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5089 single_instruction;
5090 mem : R(read);
5091 dst : M(write);
5092 MS : R;
5093 %}
5094
5095 // Float Load
5096 pipe_class floadF_mem(regF dst, memory mem) %{
5097 single_instruction;
5098 mem : R(read);
5099 dst : M(write);
5100 MS : R;
5101 %}
5102
5103 // Float Load
5104 pipe_class floadD_mem(regD dst, memory mem) %{
5105 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5106 mem : R(read);
5107 dst : M(write);
5108 MS : R;
5109 %}
5110
5111 // Float Load
5112 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5113 single_instruction;
5114 stkSlot : R(read);
5115 dst : M(write);
5116 MS : R;
5117 %}
5118
5119 // Float Load
5120 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5121 single_instruction;
5122 stkSlot : R(read);
5123 dst : M(write);
5124 MS : R;
5125 %}
5126
5127 // Memory Nop
5128 pipe_class mem_nop() %{
5129 single_instruction;
5130 MS : R;
5131 %}
5132
5133 pipe_class sethi(iRegP dst, immI src) %{
5134 single_instruction;
5135 dst : E(write);
5136 IALU : R;
5137 %}
5138
5139 pipe_class loadPollP(iRegP poll) %{
5140 single_instruction;
5141 poll : R(read);
5142 MS : R;
5143 %}
5144
5145 pipe_class br(Universe br, label labl) %{
5146 single_instruction_with_delay_slot;
5147 BR : R;
5148 %}
5149
5150 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5151 single_instruction_with_delay_slot;
5152 cr : E(read);
5153 BR : R;
5154 %}
5155
5156 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5157 single_instruction_with_delay_slot;
5158 op1 : E(read);
5159 BR : R;
5160 MS : R;
5161 %}
5162
5163 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5164 single_instruction_with_delay_slot;
5165 cr : E(read);
5166 BR : R;
5167 %}
5168
5169 pipe_class br_nop() %{
5170 single_instruction;
5171 BR : R;
5172 %}
5173
5174 pipe_class simple_call(method meth) %{
5175 instruction_count(2); multiple_bundles; force_serialization;
5176 fixed_latency(100);
5177 BR : R(1);
5178 MS : R(1);
5179 A0 : R(1);
5180 %}
5181
5182 pipe_class compiled_call(method meth) %{
5183 instruction_count(1); multiple_bundles; force_serialization;
5184 fixed_latency(100);
5185 MS : R(1);
5186 %}
5187
5188 pipe_class call(method meth) %{
5189 instruction_count(0); multiple_bundles; force_serialization;
5190 fixed_latency(100);
5191 %}
5192
5193 pipe_class tail_call(Universe ignore, label labl) %{
5194 single_instruction; has_delay_slot;
5195 fixed_latency(100);
5196 BR : R(1);
5197 MS : R(1);
5198 %}
5199
5200 pipe_class ret(Universe ignore) %{
5201 single_instruction; has_delay_slot;
5202 BR : R(1);
5203 MS : R(1);
5204 %}
5205
5206 pipe_class ret_poll(g3RegP poll) %{
5207 instruction_count(3); has_delay_slot;
5208 poll : E(read);
5209 MS : R;
5210 %}
5211
5212 // The real do-nothing guy
5213 pipe_class empty( ) %{
5214 instruction_count(0);
5215 %}
5216
5217 pipe_class long_memory_op() %{
5218 instruction_count(0); multiple_bundles; force_serialization;
5219 fixed_latency(25);
5220 MS : R(1);
5221 %}
5222
5223 // Check-cast
5224 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5225 array : R(read);
5226 match : R(read);
5227 IALU : R(2);
5228 BR : R(2);
5229 MS : R;
5230 %}
5231
5232 // Convert FPU flags into +1,0,-1
5233 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5234 src1 : E(read);
5235 src2 : E(read);
5236 dst : E(write);
5237 FA : R;
5238 MS : R(2);
5239 BR : R(2);
5240 %}
5241
5242 // Compare for p < q, and conditionally add y
5243 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5244 p : E(read);
5245 q : E(read);
5246 y : E(read);
5247 IALU : R(3)
5248 %}
5249
5250 // Perform a compare, then move conditionally in a branch delay slot.
5251 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5252 src2 : E(read);
5253 srcdst : E(read);
5254 IALU : R;
5255 BR : R;
5256 %}
5257
5258 // Define the class for the Nop node
5259 define %{
5260 MachNop = ialu_nop;
5261 %}
5262
5263 %}
5264
5265 //----------INSTRUCTIONS-------------------------------------------------------
5266
5267 //------------Special Stack Slot instructions - no match rules-----------------
5268 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5269 // No match rule to avoid chain rule match.
5270 effect(DEF dst, USE src);
5271 ins_cost(MEMORY_REF_COST);
5272 size(4);
5273 format %{ "LDF $src,$dst\t! stkI to regF" %}
5274 opcode(Assembler::ldf_op3);
5275 ins_encode(simple_form3_mem_reg(src, dst));
5276 ins_pipe(floadF_stk);
5277 %}
5278
5279 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5280 // No match rule to avoid chain rule match.
5281 effect(DEF dst, USE src);
5282 ins_cost(MEMORY_REF_COST);
5283 size(4);
5284 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5285 opcode(Assembler::lddf_op3);
5286 ins_encode(simple_form3_mem_reg(src, dst));
5287 ins_pipe(floadD_stk);
5288 %}
5289
5290 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5291 // No match rule to avoid chain rule match.
5292 effect(DEF dst, USE src);
5293 ins_cost(MEMORY_REF_COST);
5294 size(4);
5295 format %{ "STF $src,$dst\t! regF to stkI" %}
5296 opcode(Assembler::stf_op3);
5297 ins_encode(simple_form3_mem_reg(dst, src));
5298 ins_pipe(fstoreF_stk_reg);
5299 %}
5300
5301 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5302 // No match rule to avoid chain rule match.
5303 effect(DEF dst, USE src);
5304 ins_cost(MEMORY_REF_COST);
5305 size(4);
5306 format %{ "STDF $src,$dst\t! regD to stkL" %}
5307 opcode(Assembler::stdf_op3);
5308 ins_encode(simple_form3_mem_reg(dst, src));
5309 ins_pipe(fstoreD_stk_reg);
5310 %}
5311
5312 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5313 effect(DEF dst, USE src);
5314 ins_cost(MEMORY_REF_COST*2);
5315 size(8);
5316 format %{ "STW $src,$dst.hi\t! long\n\t"
5317 "STW R_G0,$dst.lo" %}
5318 opcode(Assembler::stw_op3);
5319 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5320 ins_pipe(lstoreI_stk_reg);
5321 %}
5322
5323 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5324 // No match rule to avoid chain rule match.
5325 effect(DEF dst, USE src);
5326 ins_cost(MEMORY_REF_COST);
5327 size(4);
5328 format %{ "STX $src,$dst\t! regL to stkD" %}
5329 opcode(Assembler::stx_op3);
5330 ins_encode(simple_form3_mem_reg( dst, src ) );
5331 ins_pipe(istore_stk_reg);
5332 %}
5333
5334 //---------- Chain stack slots between similar types --------
5335
5336 // Load integer from stack slot
5337 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5338 match(Set dst src);
5339 ins_cost(MEMORY_REF_COST);
5340
5341 size(4);
5342 format %{ "LDUW $src,$dst\t!stk" %}
5343 opcode(Assembler::lduw_op3);
5344 ins_encode(simple_form3_mem_reg( src, dst ) );
5345 ins_pipe(iload_mem);
5346 %}
5347
5348 // Store integer to stack slot
5349 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5350 match(Set dst src);
5351 ins_cost(MEMORY_REF_COST);
5352
5353 size(4);
5354 format %{ "STW $src,$dst\t!stk" %}
5355 opcode(Assembler::stw_op3);
5356 ins_encode(simple_form3_mem_reg( dst, src ) );
5357 ins_pipe(istore_mem_reg);
5358 %}
5359
5360 // Load long from stack slot
5361 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5362 match(Set dst src);
5363
5364 ins_cost(MEMORY_REF_COST);
5365 size(4);
5366 format %{ "LDX $src,$dst\t! long" %}
5367 opcode(Assembler::ldx_op3);
5368 ins_encode(simple_form3_mem_reg( src, dst ) );
5369 ins_pipe(iload_mem);
5370 %}
5371
5372 // Store long to stack slot
5373 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5374 match(Set dst src);
5375
5376 ins_cost(MEMORY_REF_COST);
5377 size(4);
5378 format %{ "STX $src,$dst\t! long" %}
5379 opcode(Assembler::stx_op3);
5380 ins_encode(simple_form3_mem_reg( dst, src ) );
5381 ins_pipe(istore_mem_reg);
5382 %}
5383
5384 #ifdef _LP64
5385 // Load pointer from stack slot, 64-bit encoding
5386 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5387 match(Set dst src);
5388 ins_cost(MEMORY_REF_COST);
5389 size(4);
5390 format %{ "LDX $src,$dst\t!ptr" %}
5391 opcode(Assembler::ldx_op3);
5392 ins_encode(simple_form3_mem_reg( src, dst ) );
5393 ins_pipe(iload_mem);
5394 %}
5395
5396 // Store pointer to stack slot
5397 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5398 match(Set dst src);
5399 ins_cost(MEMORY_REF_COST);
5400 size(4);
5401 format %{ "STX $src,$dst\t!ptr" %}
5402 opcode(Assembler::stx_op3);
5403 ins_encode(simple_form3_mem_reg( dst, src ) );
5404 ins_pipe(istore_mem_reg);
5405 %}
5406 #else // _LP64
5407 // Load pointer from stack slot, 32-bit encoding
5408 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5409 match(Set dst src);
5410 ins_cost(MEMORY_REF_COST);
5411 format %{ "LDUW $src,$dst\t!ptr" %}
5412 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5413 ins_encode(simple_form3_mem_reg( src, dst ) );
5414 ins_pipe(iload_mem);
5415 %}
5416
5417 // Store pointer to stack slot
5418 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5419 match(Set dst src);
5420 ins_cost(MEMORY_REF_COST);
5421 format %{ "STW $src,$dst\t!ptr" %}
5422 opcode(Assembler::stw_op3, Assembler::ldst_op);
5423 ins_encode(simple_form3_mem_reg( dst, src ) );
5424 ins_pipe(istore_mem_reg);
5425 %}
5426 #endif // _LP64
5427
5428 //------------Special Nop instructions for bundling - no match rules-----------
5429 // Nop using the A0 functional unit
5430 instruct Nop_A0() %{
5431 ins_cost(0);
5432
5433 format %{ "NOP ! Alu Pipeline" %}
5434 opcode(Assembler::or_op3, Assembler::arith_op);
5435 ins_encode( form2_nop() );
5436 ins_pipe(ialu_nop_A0);
5437 %}
5438
5439 // Nop using the A1 functional unit
5440 instruct Nop_A1( ) %{
5441 ins_cost(0);
5442
5443 format %{ "NOP ! Alu Pipeline" %}
5444 opcode(Assembler::or_op3, Assembler::arith_op);
5445 ins_encode( form2_nop() );
5446 ins_pipe(ialu_nop_A1);
5447 %}
5448
5449 // Nop using the memory functional unit
5450 instruct Nop_MS( ) %{
5451 ins_cost(0);
5452
5453 format %{ "NOP ! Memory Pipeline" %}
5454 ins_encode( emit_mem_nop );
5455 ins_pipe(mem_nop);
5456 %}
5457
5458 // Nop using the floating add functional unit
5459 instruct Nop_FA( ) %{
5460 ins_cost(0);
5461
5462 format %{ "NOP ! Floating Add Pipeline" %}
5463 ins_encode( emit_fadd_nop );
5464 ins_pipe(fadd_nop);
5465 %}
5466
5467 // Nop using the branch functional unit
5468 instruct Nop_BR( ) %{
5469 ins_cost(0);
5470
5471 format %{ "NOP ! Branch Pipeline" %}
5472 ins_encode( emit_br_nop );
5473 ins_pipe(br_nop);
5474 %}
5475
5476 //----------Load/Store/Move Instructions---------------------------------------
5477 //----------Load Instructions--------------------------------------------------
5478 // Load Byte (8bit signed)
5479 instruct loadB(iRegI dst, memory mem) %{
5480 match(Set dst (LoadB mem));
5481 ins_cost(MEMORY_REF_COST);
5482
5483 size(4);
5484 format %{ "LDSB $mem,$dst\t! byte" %}
5485 ins_encode %{
5486 __ ldsb($mem$$Address, $dst$$Register);
5487 %}
5488 ins_pipe(iload_mask_mem);
5489 %}
5490
5491 // Load Byte (8bit signed) into a Long Register
5492 instruct loadB2L(iRegL dst, memory mem) %{
5493 match(Set dst (ConvI2L (LoadB mem)));
5494 ins_cost(MEMORY_REF_COST);
5495
5496 size(4);
5497 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5498 ins_encode %{
5499 __ ldsb($mem$$Address, $dst$$Register);
5500 %}
5501 ins_pipe(iload_mask_mem);
5502 %}
5503
5504 // Load Unsigned Byte (8bit UNsigned) into an int reg
5505 instruct loadUB(iRegI dst, memory mem) %{
5506 match(Set dst (LoadUB mem));
5507 ins_cost(MEMORY_REF_COST);
5508
5509 size(4);
5510 format %{ "LDUB $mem,$dst\t! ubyte" %}
5511 ins_encode %{
5512 __ ldub($mem$$Address, $dst$$Register);
5513 %}
5514 ins_pipe(iload_mem);
5515 %}
5516
5517 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5518 instruct loadUB2L(iRegL dst, memory mem) %{
5519 match(Set dst (ConvI2L (LoadUB mem)));
5520 ins_cost(MEMORY_REF_COST);
5521
5522 size(4);
5523 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5524 ins_encode %{
5525 __ ldub($mem$$Address, $dst$$Register);
5526 %}
5527 ins_pipe(iload_mem);
5528 %}
5529
5530 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5531 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5532 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5533 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5534
5535 size(2*4);
5536 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5537 "AND $dst,$mask,$dst" %}
5538 ins_encode %{
5539 __ ldub($mem$$Address, $dst$$Register);
5540 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5541 %}
5542 ins_pipe(iload_mem);
5543 %}
5544
5545 // Load Short (16bit signed)
5546 instruct loadS(iRegI dst, memory mem) %{
5547 match(Set dst (LoadS mem));
5548 ins_cost(MEMORY_REF_COST);
5549
5550 size(4);
5551 format %{ "LDSH $mem,$dst\t! short" %}
5552 ins_encode %{
5553 __ ldsh($mem$$Address, $dst$$Register);
5554 %}
5555 ins_pipe(iload_mask_mem);
5556 %}
5557
5558 // Load Short (16 bit signed) to Byte (8 bit signed)
5559 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5560 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5561 ins_cost(MEMORY_REF_COST);
5562
5563 size(4);
5564
5565 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5566 ins_encode %{
5567 __ ldsb($mem$$Address, $dst$$Register, 1);
5568 %}
5569 ins_pipe(iload_mask_mem);
5570 %}
5571
5572 // Load Short (16bit signed) into a Long Register
5573 instruct loadS2L(iRegL dst, memory mem) %{
5574 match(Set dst (ConvI2L (LoadS mem)));
5575 ins_cost(MEMORY_REF_COST);
5576
5577 size(4);
5578 format %{ "LDSH $mem,$dst\t! short -> long" %}
5579 ins_encode %{
5580 __ ldsh($mem$$Address, $dst$$Register);
5581 %}
5582 ins_pipe(iload_mask_mem);
5583 %}
5584
5585 // Load Unsigned Short/Char (16bit UNsigned)
5586 instruct loadUS(iRegI dst, memory mem) %{
5587 match(Set dst (LoadUS mem));
5588 ins_cost(MEMORY_REF_COST);
5589
5590 size(4);
5591 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5592 ins_encode %{
5593 __ lduh($mem$$Address, $dst$$Register);
5594 %}
5595 ins_pipe(iload_mem);
5596 %}
5597
5598 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5599 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5600 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5601 ins_cost(MEMORY_REF_COST);
5602
5603 size(4);
5604 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5605 ins_encode %{
5606 __ ldsb($mem$$Address, $dst$$Register, 1);
5607 %}
5608 ins_pipe(iload_mask_mem);
5609 %}
5610
5611 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5612 instruct loadUS2L(iRegL dst, memory mem) %{
5613 match(Set dst (ConvI2L (LoadUS mem)));
5614 ins_cost(MEMORY_REF_COST);
5615
5616 size(4);
5617 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5618 ins_encode %{
5619 __ lduh($mem$$Address, $dst$$Register);
5620 %}
5621 ins_pipe(iload_mem);
5622 %}
5623
5624 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5625 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5626 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5627 ins_cost(MEMORY_REF_COST);
5628
5629 size(4);
5630 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5631 ins_encode %{
5632 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5633 %}
5634 ins_pipe(iload_mem);
5635 %}
5636
5637 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5638 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5639 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5640 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5641
5642 size(2*4);
5643 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5644 "AND $dst,$mask,$dst" %}
5645 ins_encode %{
5646 Register Rdst = $dst$$Register;
5647 __ lduh($mem$$Address, Rdst);
5648 __ and3(Rdst, $mask$$constant, Rdst);
5649 %}
5650 ins_pipe(iload_mem);
5651 %}
5652
5653 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5654 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5655 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5656 effect(TEMP dst, TEMP tmp);
5657 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5658
5659 size((3+1)*4); // set may use two instructions.
5660 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5661 "SET $mask,$tmp\n\t"
5662 "AND $dst,$tmp,$dst" %}
5663 ins_encode %{
5664 Register Rdst = $dst$$Register;
5665 Register Rtmp = $tmp$$Register;
5666 __ lduh($mem$$Address, Rdst);
5667 __ set($mask$$constant, Rtmp);
5668 __ and3(Rdst, Rtmp, Rdst);
5669 %}
5670 ins_pipe(iload_mem);
5671 %}
5672
5673 // Load Integer
5674 instruct loadI(iRegI dst, memory mem) %{
5675 match(Set dst (LoadI mem));
5676 ins_cost(MEMORY_REF_COST);
5677
5678 size(4);
5679 format %{ "LDUW $mem,$dst\t! int" %}
5680 ins_encode %{
5681 __ lduw($mem$$Address, $dst$$Register);
5682 %}
5683 ins_pipe(iload_mem);
5684 %}
5685
5686 // Load Integer to Byte (8 bit signed)
5687 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5688 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5689 ins_cost(MEMORY_REF_COST);
5690
5691 size(4);
5692
5693 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5694 ins_encode %{
5695 __ ldsb($mem$$Address, $dst$$Register, 3);
5696 %}
5697 ins_pipe(iload_mask_mem);
5698 %}
5699
5700 // Load Integer to Unsigned Byte (8 bit UNsigned)
5701 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5702 match(Set dst (AndI (LoadI mem) mask));
5703 ins_cost(MEMORY_REF_COST);
5704
5705 size(4);
5706
5707 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5708 ins_encode %{
5709 __ ldub($mem$$Address, $dst$$Register, 3);
5710 %}
5711 ins_pipe(iload_mask_mem);
5712 %}
5713
5714 // Load Integer to Short (16 bit signed)
5715 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5716 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5717 ins_cost(MEMORY_REF_COST);
5718
5719 size(4);
5720
5721 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5722 ins_encode %{
5723 __ ldsh($mem$$Address, $dst$$Register, 2);
5724 %}
5725 ins_pipe(iload_mask_mem);
5726 %}
5727
5728 // Load Integer to Unsigned Short (16 bit UNsigned)
5729 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5730 match(Set dst (AndI (LoadI mem) mask));
5731 ins_cost(MEMORY_REF_COST);
5732
5733 size(4);
5734
5735 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5736 ins_encode %{
5737 __ lduh($mem$$Address, $dst$$Register, 2);
5738 %}
5739 ins_pipe(iload_mask_mem);
5740 %}
5741
5742 // Load Integer into a Long Register
5743 instruct loadI2L(iRegL dst, memory mem) %{
5744 match(Set dst (ConvI2L (LoadI mem)));
5745 ins_cost(MEMORY_REF_COST);
5746
5747 size(4);
5748 format %{ "LDSW $mem,$dst\t! int -> long" %}
5749 ins_encode %{
5750 __ ldsw($mem$$Address, $dst$$Register);
5751 %}
5752 ins_pipe(iload_mask_mem);
5753 %}
5754
5755 // Load Integer with mask 0xFF into a Long Register
5756 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5757 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5758 ins_cost(MEMORY_REF_COST);
5759
5760 size(4);
5761 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5762 ins_encode %{
5763 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5764 %}
5765 ins_pipe(iload_mem);
5766 %}
5767
5768 // Load Integer with mask 0xFFFF into a Long Register
5769 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5770 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5771 ins_cost(MEMORY_REF_COST);
5772
5773 size(4);
5774 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5775 ins_encode %{
5776 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5777 %}
5778 ins_pipe(iload_mem);
5779 %}
5780
5781 // Load Integer with a 13-bit mask into a Long Register
5782 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5783 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5784 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5785
5786 size(2*4);
5787 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5788 "AND $dst,$mask,$dst" %}
5789 ins_encode %{
5790 Register Rdst = $dst$$Register;
5791 __ lduw($mem$$Address, Rdst);
5792 __ and3(Rdst, $mask$$constant, Rdst);
5793 %}
5794 ins_pipe(iload_mem);
5795 %}
5796
5797 // Load Integer with a 32-bit mask into a Long Register
5798 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5799 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5800 effect(TEMP dst, TEMP tmp);
5801 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5802
5803 size((3+1)*4); // set may use two instructions.
5804 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5805 "SET $mask,$tmp\n\t"
5806 "AND $dst,$tmp,$dst" %}
5807 ins_encode %{
5808 Register Rdst = $dst$$Register;
5809 Register Rtmp = $tmp$$Register;
5810 __ lduw($mem$$Address, Rdst);
5811 __ set($mask$$constant, Rtmp);
5812 __ and3(Rdst, Rtmp, Rdst);
5813 %}
5814 ins_pipe(iload_mem);
5815 %}
5816
5817 // Load Unsigned Integer into a Long Register
5818 instruct loadUI2L(iRegL dst, memory mem) %{
5819 match(Set dst (LoadUI2L mem));
5820 ins_cost(MEMORY_REF_COST);
5821
5822 size(4);
5823 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5824 ins_encode %{
5825 __ lduw($mem$$Address, $dst$$Register);
5826 %}
5827 ins_pipe(iload_mem);
5828 %}
5829
5830 // Load Long - aligned
5831 instruct loadL(iRegL dst, memory mem ) %{
5832 match(Set dst (LoadL mem));
5833 ins_cost(MEMORY_REF_COST);
5834
5835 size(4);
5836 format %{ "LDX $mem,$dst\t! long" %}
5837 ins_encode %{
5838 __ ldx($mem$$Address, $dst$$Register);
5839 %}
5840 ins_pipe(iload_mem);
5841 %}
5842
5843 // Load Long - UNaligned
5844 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5845 match(Set dst (LoadL_unaligned mem));
5846 effect(KILL tmp);
5847 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5848 size(16);
5849 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5850 "\tLDUW $mem ,$dst\n"
5851 "\tSLLX #32, $dst, $dst\n"
5852 "\tOR $dst, R_O7, $dst" %}
5853 opcode(Assembler::lduw_op3);
5854 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5855 ins_pipe(iload_mem);
5856 %}
5857
5858 // Load Aligned Packed Byte into a Double Register
5859 instruct loadA8B(regD dst, memory mem) %{
5860 match(Set dst (Load8B mem));
5861 ins_cost(MEMORY_REF_COST);
5862 size(4);
5863 format %{ "LDDF $mem,$dst\t! packed8B" %}
5864 opcode(Assembler::lddf_op3);
5865 ins_encode(simple_form3_mem_reg( mem, dst ) );
5866 ins_pipe(floadD_mem);
5867 %}
5868
5869 // Load Aligned Packed Char into a Double Register
5870 instruct loadA4C(regD dst, memory mem) %{
5871 match(Set dst (Load4C mem));
5872 ins_cost(MEMORY_REF_COST);
5873 size(4);
5874 format %{ "LDDF $mem,$dst\t! packed4C" %}
5875 opcode(Assembler::lddf_op3);
5876 ins_encode(simple_form3_mem_reg( mem, dst ) );
5877 ins_pipe(floadD_mem);
5878 %}
5879
5880 // Load Aligned Packed Short into a Double Register
5881 instruct loadA4S(regD dst, memory mem) %{
5882 match(Set dst (Load4S mem));
5883 ins_cost(MEMORY_REF_COST);
5884 size(4);
5885 format %{ "LDDF $mem,$dst\t! packed4S" %}
5886 opcode(Assembler::lddf_op3);
5887 ins_encode(simple_form3_mem_reg( mem, dst ) );
5888 ins_pipe(floadD_mem);
5889 %}
5890
5891 // Load Aligned Packed Int into a Double Register
5892 instruct loadA2I(regD dst, memory mem) %{
5893 match(Set dst (Load2I mem));
5894 ins_cost(MEMORY_REF_COST);
5895 size(4);
5896 format %{ "LDDF $mem,$dst\t! packed2I" %}
5897 opcode(Assembler::lddf_op3);
5898 ins_encode(simple_form3_mem_reg( mem, dst ) );
5899 ins_pipe(floadD_mem);
5900 %}
5901
5902 // Load Range
5903 instruct loadRange(iRegI dst, memory mem) %{
5904 match(Set dst (LoadRange mem));
5905 ins_cost(MEMORY_REF_COST);
5906
5907 size(4);
5908 format %{ "LDUW $mem,$dst\t! range" %}
5909 opcode(Assembler::lduw_op3);
5910 ins_encode(simple_form3_mem_reg( mem, dst ) );
5911 ins_pipe(iload_mem);
5912 %}
5913
5914 // Load Integer into %f register (for fitos/fitod)
5915 instruct loadI_freg(regF dst, memory mem) %{
5916 match(Set dst (LoadI mem));
5917 ins_cost(MEMORY_REF_COST);
5918 size(4);
5919
5920 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5921 opcode(Assembler::ldf_op3);
5922 ins_encode(simple_form3_mem_reg( mem, dst ) );
5923 ins_pipe(floadF_mem);
5924 %}
5925
5926 // Load Pointer
5927 instruct loadP(iRegP dst, memory mem) %{
5928 match(Set dst (LoadP mem));
5929 ins_cost(MEMORY_REF_COST);
5930 size(4);
5931
5932 #ifndef _LP64
5933 format %{ "LDUW $mem,$dst\t! ptr" %}
5934 ins_encode %{
5935 __ lduw($mem$$Address, $dst$$Register);
5936 %}
5937 #else
5938 format %{ "LDX $mem,$dst\t! ptr" %}
5939 ins_encode %{
5940 __ ldx($mem$$Address, $dst$$Register);
5941 %}
5942 #endif
5943 ins_pipe(iload_mem);
5944 %}
5945
5946 // Load Compressed Pointer
5947 instruct loadN(iRegN dst, memory mem) %{
5948 match(Set dst (LoadN mem));
5949 ins_cost(MEMORY_REF_COST);
5950 size(4);
5951
5952 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5953 ins_encode %{
5954 __ lduw($mem$$Address, $dst$$Register);
5955 %}
5956 ins_pipe(iload_mem);
5957 %}
5958
5959 // Load Klass Pointer
5960 instruct loadKlass(iRegP dst, memory mem) %{
5961 match(Set dst (LoadKlass mem));
5962 ins_cost(MEMORY_REF_COST);
5963 size(4);
5964
5965 #ifndef _LP64
5966 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5967 ins_encode %{
5968 __ lduw($mem$$Address, $dst$$Register);
5969 %}
5970 #else
5971 format %{ "LDX $mem,$dst\t! klass ptr" %}
5972 ins_encode %{
5973 __ ldx($mem$$Address, $dst$$Register);
5974 %}
5975 #endif
5976 ins_pipe(iload_mem);
5977 %}
5978
5979 // Load narrow Klass Pointer
5980 instruct loadNKlass(iRegN dst, memory mem) %{
5981 match(Set dst (LoadNKlass mem));
5982 ins_cost(MEMORY_REF_COST);
5983 size(4);
5984
5985 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5986 ins_encode %{
5987 __ lduw($mem$$Address, $dst$$Register);
5988 %}
5989 ins_pipe(iload_mem);
5990 %}
5991
5992 // Load Double
5993 instruct loadD(regD dst, memory mem) %{
5994 match(Set dst (LoadD mem));
5995 ins_cost(MEMORY_REF_COST);
5996
5997 size(4);
5998 format %{ "LDDF $mem,$dst" %}
5999 opcode(Assembler::lddf_op3);
6000 ins_encode(simple_form3_mem_reg( mem, dst ) );
6001 ins_pipe(floadD_mem);
6002 %}
6003
6004 // Load Double - UNaligned
6005 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6006 match(Set dst (LoadD_unaligned mem));
6007 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6008 size(8);
6009 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6010 "\tLDF $mem+4,$dst.lo\t!" %}
6011 opcode(Assembler::ldf_op3);
6012 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6013 ins_pipe(iload_mem);
6014 %}
6015
6016 // Load Float
6017 instruct loadF(regF dst, memory mem) %{
6018 match(Set dst (LoadF mem));
6019 ins_cost(MEMORY_REF_COST);
6020
6021 size(4);
6022 format %{ "LDF $mem,$dst" %}
6023 opcode(Assembler::ldf_op3);
6024 ins_encode(simple_form3_mem_reg( mem, dst ) );
6025 ins_pipe(floadF_mem);
6026 %}
6027
6028 // Load Constant
6029 instruct loadConI( iRegI dst, immI src ) %{
6030 match(Set dst src);
6031 ins_cost(DEFAULT_COST * 3/2);
6032 format %{ "SET $src,$dst" %}
6033 ins_encode( Set32(src, dst) );
6034 ins_pipe(ialu_hi_lo_reg);
6035 %}
6036
6037 instruct loadConI13( iRegI dst, immI13 src ) %{
6038 match(Set dst src);
6039
6040 size(4);
6041 format %{ "MOV $src,$dst" %}
6042 ins_encode( Set13( src, dst ) );
6043 ins_pipe(ialu_imm);
6044 %}
6045
6046 #ifndef _LP64
6047 instruct loadConP(iRegP dst, immP con) %{
6048 match(Set dst con);
6049 ins_cost(DEFAULT_COST * 3/2);
6050 format %{ "SET $con,$dst\t!ptr" %}
6051 ins_encode %{
6052 // [RGV] This next line should be generated from ADLC
6053 if (_opnds[1]->constant_is_oop()) {
6054 intptr_t val = $con$$constant;
6055 __ set_oop_constant((jobject) val, $dst$$Register);
6056 } else { // non-oop pointers, e.g. card mark base, heap top
6057 __ set($con$$constant, $dst$$Register);
6058 }
6059 %}
6060 ins_pipe(loadConP);
6061 %}
6062 #else
6063 instruct loadConP_set(iRegP dst, immP_set con) %{
6064 match(Set dst con);
6065 ins_cost(DEFAULT_COST * 3/2);
6066 format %{ "SET $con,$dst\t! ptr" %}
6067 ins_encode %{
6068 // [RGV] This next line should be generated from ADLC
6069 if (_opnds[1]->constant_is_oop()) {
6070 intptr_t val = $con$$constant;
6071 __ set_oop_constant((jobject) val, $dst$$Register);
6072 } else { // non-oop pointers, e.g. card mark base, heap top
6073 __ set($con$$constant, $dst$$Register);
6074 }
6075 %}
6076 ins_pipe(loadConP);
6077 %}
6078
6079 instruct loadConP_load(iRegP dst, immP_load con) %{
6080 match(Set dst con);
6081 ins_cost(MEMORY_REF_COST);
6082 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6083 ins_encode %{
6084 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6085 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6086 %}
6087 ins_pipe(loadConP);
6088 %}
6089
6090 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6091 match(Set dst con);
6092 ins_cost(DEFAULT_COST * 3/2);
6093 format %{ "SET $con,$dst\t! non-oop ptr" %}
6094 ins_encode %{
6095 __ set($con$$constant, $dst$$Register);
6096 %}
6097 ins_pipe(loadConP);
6098 %}
6099 #endif // _LP64
6100
6101 instruct loadConP0(iRegP dst, immP0 src) %{
6102 match(Set dst src);
6103
6104 size(4);
6105 format %{ "CLR $dst\t!ptr" %}
6106 ins_encode %{
6107 __ clr($dst$$Register);
6108 %}
6109 ins_pipe(ialu_imm);
6110 %}
6111
6112 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6113 match(Set dst src);
6114 ins_cost(DEFAULT_COST);
6115 format %{ "SET $src,$dst\t!ptr" %}
6116 ins_encode %{
6117 AddressLiteral polling_page(os::get_polling_page());
6118 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6119 %}
6120 ins_pipe(loadConP_poll);
6121 %}
6122
6123 instruct loadConN0(iRegN dst, immN0 src) %{
6124 match(Set dst src);
6125
6126 size(4);
6127 format %{ "CLR $dst\t! compressed NULL ptr" %}
6128 ins_encode %{
6129 __ clr($dst$$Register);
6130 %}
6131 ins_pipe(ialu_imm);
6132 %}
6133
6134 instruct loadConN(iRegN dst, immN src) %{
6135 match(Set dst src);
6136 ins_cost(DEFAULT_COST * 3/2);
6137 format %{ "SET $src,$dst\t! compressed ptr" %}
6138 ins_encode %{
6139 Register dst = $dst$$Register;
6140 __ set_narrow_oop((jobject)$src$$constant, dst);
6141 %}
6142 ins_pipe(ialu_hi_lo_reg);
6143 %}
6144
6145 // Materialize long value (predicated by immL_cheap).
6146 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6147 match(Set dst con);
6148 effect(KILL tmp);
6149 ins_cost(DEFAULT_COST * 3);
6150 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6151 ins_encode %{
6152 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6153 %}
6154 ins_pipe(loadConL);
6155 %}
6156
6157 // Load long value from constant table (predicated by immL_expensive).
6158 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6159 match(Set dst con);
6160 ins_cost(MEMORY_REF_COST);
6161 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6162 ins_encode %{
6163 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6164 __ ldx($constanttablebase, con_offset, $dst$$Register);
6165 %}
6166 ins_pipe(loadConL);
6167 %}
6168
6169 instruct loadConL0( iRegL dst, immL0 src ) %{
6170 match(Set dst src);
6171 ins_cost(DEFAULT_COST);
6172 size(4);
6173 format %{ "CLR $dst\t! long" %}
6174 ins_encode( Set13( src, dst ) );
6175 ins_pipe(ialu_imm);
6176 %}
6177
6178 instruct loadConL13( iRegL dst, immL13 src ) %{
6179 match(Set dst src);
6180 ins_cost(DEFAULT_COST * 2);
6181
6182 size(4);
6183 format %{ "MOV $src,$dst\t! long" %}
6184 ins_encode( Set13( src, dst ) );
6185 ins_pipe(ialu_imm);
6186 %}
6187
6188 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6189 match(Set dst con);
6190 effect(KILL tmp);
6191 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6192 ins_encode %{
6193 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6194 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6195 %}
6196 ins_pipe(loadConFD);
6197 %}
6198
6199 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6200 match(Set dst con);
6201 effect(KILL tmp);
6202 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6203 ins_encode %{
6204 // XXX This is a quick fix for 6833573.
6205 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6206 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6207 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6208 %}
6209 ins_pipe(loadConFD);
6210 %}
6211
6212 // Prefetch instructions.
6213 // Must be safe to execute with invalid address (cannot fault).
6214
6215 instruct prefetchr( memory mem ) %{
6216 match( PrefetchRead mem );
6217 ins_cost(MEMORY_REF_COST);
6218
6219 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6220 opcode(Assembler::prefetch_op3);
6221 ins_encode( form3_mem_prefetch_read( mem ) );
6222 ins_pipe(iload_mem);
6223 %}
6224
6225 instruct prefetchw( memory mem ) %{
6226 predicate(AllocatePrefetchStyle != 3 );
6227 match( PrefetchWrite mem );
6228 ins_cost(MEMORY_REF_COST);
6229
6230 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6231 opcode(Assembler::prefetch_op3);
6232 ins_encode( form3_mem_prefetch_write( mem ) );
6233 ins_pipe(iload_mem);
6234 %}
6235
6236 // Use BIS instruction to prefetch.
6237 instruct prefetchw_bis( memory mem ) %{
6238 predicate(AllocatePrefetchStyle == 3);
6239 match( PrefetchWrite mem );
6240 ins_cost(MEMORY_REF_COST);
6241
6242 format %{ "STXA G0,$mem\t! // Block initializing store" %}
6243 ins_encode %{
6244 Register base = as_Register($mem$$base);
6245 int disp = $mem$$disp;
6246 if (disp != 0) {
6247 __ add(base, AllocatePrefetchStepSize, base);
6248 }
6249 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
6250 %}
6251 ins_pipe(istore_mem_reg);
6252 %}
6253
6254 //----------Store Instructions-------------------------------------------------
6255 // Store Byte
6256 instruct storeB(memory mem, iRegI src) %{
6257 match(Set mem (StoreB mem src));
6258 ins_cost(MEMORY_REF_COST);
6259
6260 size(4);
6261 format %{ "STB $src,$mem\t! byte" %}
6262 opcode(Assembler::stb_op3);
6263 ins_encode(simple_form3_mem_reg( mem, src ) );
6264 ins_pipe(istore_mem_reg);
6265 %}
6266
6267 instruct storeB0(memory mem, immI0 src) %{
6268 match(Set mem (StoreB mem src));
6269 ins_cost(MEMORY_REF_COST);
6270
6271 size(4);
6272 format %{ "STB $src,$mem\t! byte" %}
6273 opcode(Assembler::stb_op3);
6274 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6275 ins_pipe(istore_mem_zero);
6276 %}
6277
6278 instruct storeCM0(memory mem, immI0 src) %{
6279 match(Set mem (StoreCM mem src));
6280 ins_cost(MEMORY_REF_COST);
6281
6282 size(4);
6283 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6284 opcode(Assembler::stb_op3);
6285 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6286 ins_pipe(istore_mem_zero);
6287 %}
6288
6289 // Store Char/Short
6290 instruct storeC(memory mem, iRegI src) %{
6291 match(Set mem (StoreC mem src));
6292 ins_cost(MEMORY_REF_COST);
6293
6294 size(4);
6295 format %{ "STH $src,$mem\t! short" %}
6296 opcode(Assembler::sth_op3);
6297 ins_encode(simple_form3_mem_reg( mem, src ) );
6298 ins_pipe(istore_mem_reg);
6299 %}
6300
6301 instruct storeC0(memory mem, immI0 src) %{
6302 match(Set mem (StoreC mem src));
6303 ins_cost(MEMORY_REF_COST);
6304
6305 size(4);
6306 format %{ "STH $src,$mem\t! short" %}
6307 opcode(Assembler::sth_op3);
6308 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6309 ins_pipe(istore_mem_zero);
6310 %}
6311
6312 // Store Integer
6313 instruct storeI(memory mem, iRegI src) %{
6314 match(Set mem (StoreI mem src));
6315 ins_cost(MEMORY_REF_COST);
6316
6317 size(4);
6318 format %{ "STW $src,$mem" %}
6319 opcode(Assembler::stw_op3);
6320 ins_encode(simple_form3_mem_reg( mem, src ) );
6321 ins_pipe(istore_mem_reg);
6322 %}
6323
6324 // Store Long
6325 instruct storeL(memory mem, iRegL src) %{
6326 match(Set mem (StoreL mem src));
6327 ins_cost(MEMORY_REF_COST);
6328 size(4);
6329 format %{ "STX $src,$mem\t! long" %}
6330 opcode(Assembler::stx_op3);
6331 ins_encode(simple_form3_mem_reg( mem, src ) );
6332 ins_pipe(istore_mem_reg);
6333 %}
6334
6335 instruct storeI0(memory mem, immI0 src) %{
6336 match(Set mem (StoreI mem src));
6337 ins_cost(MEMORY_REF_COST);
6338
6339 size(4);
6340 format %{ "STW $src,$mem" %}
6341 opcode(Assembler::stw_op3);
6342 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6343 ins_pipe(istore_mem_zero);
6344 %}
6345
6346 instruct storeL0(memory mem, immL0 src) %{
6347 match(Set mem (StoreL mem src));
6348 ins_cost(MEMORY_REF_COST);
6349
6350 size(4);
6351 format %{ "STX $src,$mem" %}
6352 opcode(Assembler::stx_op3);
6353 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6354 ins_pipe(istore_mem_zero);
6355 %}
6356
6357 // Store Integer from float register (used after fstoi)
6358 instruct storeI_Freg(memory mem, regF src) %{
6359 match(Set mem (StoreI mem src));
6360 ins_cost(MEMORY_REF_COST);
6361
6362 size(4);
6363 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6364 opcode(Assembler::stf_op3);
6365 ins_encode(simple_form3_mem_reg( mem, src ) );
6366 ins_pipe(fstoreF_mem_reg);
6367 %}
6368
6369 // Store Pointer
6370 instruct storeP(memory dst, sp_ptr_RegP src) %{
6371 match(Set dst (StoreP dst src));
6372 ins_cost(MEMORY_REF_COST);
6373 size(4);
6374
6375 #ifndef _LP64
6376 format %{ "STW $src,$dst\t! ptr" %}
6377 opcode(Assembler::stw_op3, 0, REGP_OP);
6378 #else
6379 format %{ "STX $src,$dst\t! ptr" %}
6380 opcode(Assembler::stx_op3, 0, REGP_OP);
6381 #endif
6382 ins_encode( form3_mem_reg( dst, src ) );
6383 ins_pipe(istore_mem_spORreg);
6384 %}
6385
6386 instruct storeP0(memory dst, immP0 src) %{
6387 match(Set dst (StoreP dst src));
6388 ins_cost(MEMORY_REF_COST);
6389 size(4);
6390
6391 #ifndef _LP64
6392 format %{ "STW $src,$dst\t! ptr" %}
6393 opcode(Assembler::stw_op3, 0, REGP_OP);
6394 #else
6395 format %{ "STX $src,$dst\t! ptr" %}
6396 opcode(Assembler::stx_op3, 0, REGP_OP);
6397 #endif
6398 ins_encode( form3_mem_reg( dst, R_G0 ) );
6399 ins_pipe(istore_mem_zero);
6400 %}
6401
6402 // Store Compressed Pointer
6403 instruct storeN(memory dst, iRegN src) %{
6404 match(Set dst (StoreN dst src));
6405 ins_cost(MEMORY_REF_COST);
6406 size(4);
6407
6408 format %{ "STW $src,$dst\t! compressed ptr" %}
6409 ins_encode %{
6410 Register base = as_Register($dst$$base);
6411 Register index = as_Register($dst$$index);
6412 Register src = $src$$Register;
6413 if (index != G0) {
6414 __ stw(src, base, index);
6415 } else {
6416 __ stw(src, base, $dst$$disp);
6417 }
6418 %}
6419 ins_pipe(istore_mem_spORreg);
6420 %}
6421
6422 instruct storeN0(memory dst, immN0 src) %{
6423 match(Set dst (StoreN dst src));
6424 ins_cost(MEMORY_REF_COST);
6425 size(4);
6426
6427 format %{ "STW $src,$dst\t! compressed ptr" %}
6428 ins_encode %{
6429 Register base = as_Register($dst$$base);
6430 Register index = as_Register($dst$$index);
6431 if (index != G0) {
6432 __ stw(0, base, index);
6433 } else {
6434 __ stw(0, base, $dst$$disp);
6435 }
6436 %}
6437 ins_pipe(istore_mem_zero);
6438 %}
6439
6440 // Store Double
6441 instruct storeD( memory mem, regD src) %{
6442 match(Set mem (StoreD mem src));
6443 ins_cost(MEMORY_REF_COST);
6444
6445 size(4);
6446 format %{ "STDF $src,$mem" %}
6447 opcode(Assembler::stdf_op3);
6448 ins_encode(simple_form3_mem_reg( mem, src ) );
6449 ins_pipe(fstoreD_mem_reg);
6450 %}
6451
6452 instruct storeD0( memory mem, immD0 src) %{
6453 match(Set mem (StoreD mem src));
6454 ins_cost(MEMORY_REF_COST);
6455
6456 size(4);
6457 format %{ "STX $src,$mem" %}
6458 opcode(Assembler::stx_op3);
6459 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6460 ins_pipe(fstoreD_mem_zero);
6461 %}
6462
6463 // Store Float
6464 instruct storeF( memory mem, regF src) %{
6465 match(Set mem (StoreF mem src));
6466 ins_cost(MEMORY_REF_COST);
6467
6468 size(4);
6469 format %{ "STF $src,$mem" %}
6470 opcode(Assembler::stf_op3);
6471 ins_encode(simple_form3_mem_reg( mem, src ) );
6472 ins_pipe(fstoreF_mem_reg);
6473 %}
6474
6475 instruct storeF0( memory mem, immF0 src) %{
6476 match(Set mem (StoreF mem src));
6477 ins_cost(MEMORY_REF_COST);
6478
6479 size(4);
6480 format %{ "STW $src,$mem\t! storeF0" %}
6481 opcode(Assembler::stw_op3);
6482 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6483 ins_pipe(fstoreF_mem_zero);
6484 %}
6485
6486 // Store Aligned Packed Bytes in Double register to memory
6487 instruct storeA8B(memory mem, regD src) %{
6488 match(Set mem (Store8B mem src));
6489 ins_cost(MEMORY_REF_COST);
6490 size(4);
6491 format %{ "STDF $src,$mem\t! packed8B" %}
6492 opcode(Assembler::stdf_op3);
6493 ins_encode(simple_form3_mem_reg( mem, src ) );
6494 ins_pipe(fstoreD_mem_reg);
6495 %}
6496
6497 // Convert oop pointer into compressed form
6498 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6499 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6500 match(Set dst (EncodeP src));
6501 format %{ "encode_heap_oop $src, $dst" %}
6502 ins_encode %{
6503 __ encode_heap_oop($src$$Register, $dst$$Register);
6504 %}
6505 ins_pipe(ialu_reg);
6506 %}
6507
6508 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6509 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6510 match(Set dst (EncodeP src));
6511 format %{ "encode_heap_oop_not_null $src, $dst" %}
6512 ins_encode %{
6513 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6514 %}
6515 ins_pipe(ialu_reg);
6516 %}
6517
6518 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6519 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6520 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6521 match(Set dst (DecodeN src));
6522 format %{ "decode_heap_oop $src, $dst" %}
6523 ins_encode %{
6524 __ decode_heap_oop($src$$Register, $dst$$Register);
6525 %}
6526 ins_pipe(ialu_reg);
6527 %}
6528
6529 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6530 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6531 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6532 match(Set dst (DecodeN src));
6533 format %{ "decode_heap_oop_not_null $src, $dst" %}
6534 ins_encode %{
6535 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6536 %}
6537 ins_pipe(ialu_reg);
6538 %}
6539
6540
6541 // Store Zero into Aligned Packed Bytes
6542 instruct storeA8B0(memory mem, immI0 zero) %{
6543 match(Set mem (Store8B mem zero));
6544 ins_cost(MEMORY_REF_COST);
6545 size(4);
6546 format %{ "STX $zero,$mem\t! packed8B" %}
6547 opcode(Assembler::stx_op3);
6548 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6549 ins_pipe(fstoreD_mem_zero);
6550 %}
6551
6552 // Store Aligned Packed Chars/Shorts in Double register to memory
6553 instruct storeA4C(memory mem, regD src) %{
6554 match(Set mem (Store4C mem src));
6555 ins_cost(MEMORY_REF_COST);
6556 size(4);
6557 format %{ "STDF $src,$mem\t! packed4C" %}
6558 opcode(Assembler::stdf_op3);
6559 ins_encode(simple_form3_mem_reg( mem, src ) );
6560 ins_pipe(fstoreD_mem_reg);
6561 %}
6562
6563 // Store Zero into Aligned Packed Chars/Shorts
6564 instruct storeA4C0(memory mem, immI0 zero) %{
6565 match(Set mem (Store4C mem (Replicate4C zero)));
6566 ins_cost(MEMORY_REF_COST);
6567 size(4);
6568 format %{ "STX $zero,$mem\t! packed4C" %}
6569 opcode(Assembler::stx_op3);
6570 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6571 ins_pipe(fstoreD_mem_zero);
6572 %}
6573
6574 // Store Aligned Packed Ints in Double register to memory
6575 instruct storeA2I(memory mem, regD src) %{
6576 match(Set mem (Store2I mem src));
6577 ins_cost(MEMORY_REF_COST);
6578 size(4);
6579 format %{ "STDF $src,$mem\t! packed2I" %}
6580 opcode(Assembler::stdf_op3);
6581 ins_encode(simple_form3_mem_reg( mem, src ) );
6582 ins_pipe(fstoreD_mem_reg);
6583 %}
6584
6585 // Store Zero into Aligned Packed Ints
6586 instruct storeA2I0(memory mem, immI0 zero) %{
6587 match(Set mem (Store2I mem zero));
6588 ins_cost(MEMORY_REF_COST);
6589 size(4);
6590 format %{ "STX $zero,$mem\t! packed2I" %}
6591 opcode(Assembler::stx_op3);
6592 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6593 ins_pipe(fstoreD_mem_zero);
6594 %}
6595
6596
6597 //----------MemBar Instructions-----------------------------------------------
6598 // Memory barrier flavors
6599
6600 instruct membar_acquire() %{
6601 match(MemBarAcquire);
6602 ins_cost(4*MEMORY_REF_COST);
6603
6604 size(0);
6605 format %{ "MEMBAR-acquire" %}
6606 ins_encode( enc_membar_acquire );
6607 ins_pipe(long_memory_op);
6608 %}
6609
6610 instruct membar_acquire_lock() %{
6611 match(MemBarAcquire);
6612 predicate(Matcher::prior_fast_lock(n));
6613 ins_cost(0);
6614
6615 size(0);
6616 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6617 ins_encode( );
6618 ins_pipe(empty);
6619 %}
6620
6621 instruct membar_release() %{
6622 match(MemBarRelease);
6623 ins_cost(4*MEMORY_REF_COST);
6624
6625 size(0);
6626 format %{ "MEMBAR-release" %}
6627 ins_encode( enc_membar_release );
6628 ins_pipe(long_memory_op);
6629 %}
6630
6631 instruct membar_release_lock() %{
6632 match(MemBarRelease);
6633 predicate(Matcher::post_fast_unlock(n));
6634 ins_cost(0);
6635
6636 size(0);
6637 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6638 ins_encode( );
6639 ins_pipe(empty);
6640 %}
6641
6642 instruct membar_volatile() %{
6643 match(MemBarVolatile);
6644 ins_cost(4*MEMORY_REF_COST);
6645
6646 size(4);
6647 format %{ "MEMBAR-volatile" %}
6648 ins_encode( enc_membar_volatile );
6649 ins_pipe(long_memory_op);
6650 %}
6651
6652 instruct unnecessary_membar_volatile() %{
6653 match(MemBarVolatile);
6654 predicate(Matcher::post_store_load_barrier(n));
6655 ins_cost(0);
6656
6657 size(0);
6658 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6659 ins_encode( );
6660 ins_pipe(empty);
6661 %}
6662
6663 //----------Register Move Instructions-----------------------------------------
6664 instruct roundDouble_nop(regD dst) %{
6665 match(Set dst (RoundDouble dst));
6666 ins_cost(0);
6667 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6668 ins_encode( );
6669 ins_pipe(empty);
6670 %}
6671
6672
6673 instruct roundFloat_nop(regF dst) %{
6674 match(Set dst (RoundFloat dst));
6675 ins_cost(0);
6676 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6677 ins_encode( );
6678 ins_pipe(empty);
6679 %}
6680
6681
6682 // Cast Index to Pointer for unsafe natives
6683 instruct castX2P(iRegX src, iRegP dst) %{
6684 match(Set dst (CastX2P src));
6685
6686 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6687 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6688 ins_pipe(ialu_reg);
6689 %}
6690
6691 // Cast Pointer to Index for unsafe natives
6692 instruct castP2X(iRegP src, iRegX dst) %{
6693 match(Set dst (CastP2X src));
6694
6695 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6696 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6697 ins_pipe(ialu_reg);
6698 %}
6699
6700 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6701 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6702 match(Set stkSlot src); // chain rule
6703 ins_cost(MEMORY_REF_COST);
6704 format %{ "STDF $src,$stkSlot\t!stk" %}
6705 opcode(Assembler::stdf_op3);
6706 ins_encode(simple_form3_mem_reg(stkSlot, src));
6707 ins_pipe(fstoreD_stk_reg);
6708 %}
6709
6710 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6711 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6712 match(Set dst stkSlot); // chain rule
6713 ins_cost(MEMORY_REF_COST);
6714 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6715 opcode(Assembler::lddf_op3);
6716 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6717 ins_pipe(floadD_stk);
6718 %}
6719
6720 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6721 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6722 match(Set stkSlot src); // chain rule
6723 ins_cost(MEMORY_REF_COST);
6724 format %{ "STF $src,$stkSlot\t!stk" %}
6725 opcode(Assembler::stf_op3);
6726 ins_encode(simple_form3_mem_reg(stkSlot, src));
6727 ins_pipe(fstoreF_stk_reg);
6728 %}
6729
6730 //----------Conditional Move---------------------------------------------------
6731 // Conditional move
6732 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6733 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6734 ins_cost(150);
6735 format %{ "MOV$cmp $pcc,$src,$dst" %}
6736 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6737 ins_pipe(ialu_reg);
6738 %}
6739
6740 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6741 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6742 ins_cost(140);
6743 format %{ "MOV$cmp $pcc,$src,$dst" %}
6744 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6745 ins_pipe(ialu_imm);
6746 %}
6747
6748 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6749 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6750 ins_cost(150);
6751 size(4);
6752 format %{ "MOV$cmp $icc,$src,$dst" %}
6753 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6754 ins_pipe(ialu_reg);
6755 %}
6756
6757 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6758 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6759 ins_cost(140);
6760 size(4);
6761 format %{ "MOV$cmp $icc,$src,$dst" %}
6762 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6763 ins_pipe(ialu_imm);
6764 %}
6765
6766 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6767 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6768 ins_cost(150);
6769 size(4);
6770 format %{ "MOV$cmp $icc,$src,$dst" %}
6771 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6772 ins_pipe(ialu_reg);
6773 %}
6774
6775 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6776 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6777 ins_cost(140);
6778 size(4);
6779 format %{ "MOV$cmp $icc,$src,$dst" %}
6780 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6781 ins_pipe(ialu_imm);
6782 %}
6783
6784 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6785 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6786 ins_cost(150);
6787 size(4);
6788 format %{ "MOV$cmp $fcc,$src,$dst" %}
6789 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6790 ins_pipe(ialu_reg);
6791 %}
6792
6793 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6794 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6795 ins_cost(140);
6796 size(4);
6797 format %{ "MOV$cmp $fcc,$src,$dst" %}
6798 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6799 ins_pipe(ialu_imm);
6800 %}
6801
6802 // Conditional move for RegN. Only cmov(reg,reg).
6803 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6804 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6805 ins_cost(150);
6806 format %{ "MOV$cmp $pcc,$src,$dst" %}
6807 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6808 ins_pipe(ialu_reg);
6809 %}
6810
6811 // This instruction also works with CmpN so we don't need cmovNN_reg.
6812 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6813 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6814 ins_cost(150);
6815 size(4);
6816 format %{ "MOV$cmp $icc,$src,$dst" %}
6817 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6818 ins_pipe(ialu_reg);
6819 %}
6820
6821 // This instruction also works with CmpN so we don't need cmovNN_reg.
6822 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6823 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6824 ins_cost(150);
6825 size(4);
6826 format %{ "MOV$cmp $icc,$src,$dst" %}
6827 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6828 ins_pipe(ialu_reg);
6829 %}
6830
6831 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6832 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6833 ins_cost(150);
6834 size(4);
6835 format %{ "MOV$cmp $fcc,$src,$dst" %}
6836 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6837 ins_pipe(ialu_reg);
6838 %}
6839
6840 // Conditional move
6841 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6842 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6843 ins_cost(150);
6844 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6845 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6846 ins_pipe(ialu_reg);
6847 %}
6848
6849 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6850 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6851 ins_cost(140);
6852 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6853 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6854 ins_pipe(ialu_imm);
6855 %}
6856
6857 // This instruction also works with CmpN so we don't need cmovPN_reg.
6858 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6859 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6860 ins_cost(150);
6861
6862 size(4);
6863 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6864 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6865 ins_pipe(ialu_reg);
6866 %}
6867
6868 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6869 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6870 ins_cost(150);
6871
6872 size(4);
6873 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6874 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6875 ins_pipe(ialu_reg);
6876 %}
6877
6878 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6879 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6880 ins_cost(140);
6881
6882 size(4);
6883 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6884 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6885 ins_pipe(ialu_imm);
6886 %}
6887
6888 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6889 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6890 ins_cost(140);
6891
6892 size(4);
6893 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6894 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6895 ins_pipe(ialu_imm);
6896 %}
6897
6898 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6899 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6900 ins_cost(150);
6901 size(4);
6902 format %{ "MOV$cmp $fcc,$src,$dst" %}
6903 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6904 ins_pipe(ialu_imm);
6905 %}
6906
6907 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6908 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6909 ins_cost(140);
6910 size(4);
6911 format %{ "MOV$cmp $fcc,$src,$dst" %}
6912 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6913 ins_pipe(ialu_imm);
6914 %}
6915
6916 // Conditional move
6917 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6918 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6919 ins_cost(150);
6920 opcode(0x101);
6921 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6922 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6923 ins_pipe(int_conditional_float_move);
6924 %}
6925
6926 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6927 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6928 ins_cost(150);
6929
6930 size(4);
6931 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6932 opcode(0x101);
6933 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6934 ins_pipe(int_conditional_float_move);
6935 %}
6936
6937 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6938 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6939 ins_cost(150);
6940
6941 size(4);
6942 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6943 opcode(0x101);
6944 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6945 ins_pipe(int_conditional_float_move);
6946 %}
6947
6948 // Conditional move,
6949 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6950 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6951 ins_cost(150);
6952 size(4);
6953 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6954 opcode(0x1);
6955 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6956 ins_pipe(int_conditional_double_move);
6957 %}
6958
6959 // Conditional move
6960 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6961 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6962 ins_cost(150);
6963 size(4);
6964 opcode(0x102);
6965 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6966 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6967 ins_pipe(int_conditional_double_move);
6968 %}
6969
6970 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6971 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6972 ins_cost(150);
6973
6974 size(4);
6975 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6976 opcode(0x102);
6977 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6978 ins_pipe(int_conditional_double_move);
6979 %}
6980
6981 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6982 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6983 ins_cost(150);
6984
6985 size(4);
6986 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6987 opcode(0x102);
6988 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6989 ins_pipe(int_conditional_double_move);
6990 %}
6991
6992 // Conditional move,
6993 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6994 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6995 ins_cost(150);
6996 size(4);
6997 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6998 opcode(0x2);
6999 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7000 ins_pipe(int_conditional_double_move);
7001 %}
7002
7003 // Conditional move
7004 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7005 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7006 ins_cost(150);
7007 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7008 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7009 ins_pipe(ialu_reg);
7010 %}
7011
7012 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7013 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7014 ins_cost(140);
7015 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7016 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7017 ins_pipe(ialu_imm);
7018 %}
7019
7020 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7021 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7022 ins_cost(150);
7023
7024 size(4);
7025 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7026 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7027 ins_pipe(ialu_reg);
7028 %}
7029
7030
7031 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7032 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7033 ins_cost(150);
7034
7035 size(4);
7036 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7037 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7038 ins_pipe(ialu_reg);
7039 %}
7040
7041
7042 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7043 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7044 ins_cost(150);
7045
7046 size(4);
7047 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7048 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7049 ins_pipe(ialu_reg);
7050 %}
7051
7052
7053
7054 //----------OS and Locking Instructions----------------------------------------
7055
7056 // This name is KNOWN by the ADLC and cannot be changed.
7057 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7058 // for this guy.
7059 instruct tlsLoadP(g2RegP dst) %{
7060 match(Set dst (ThreadLocal));
7061
7062 size(0);
7063 ins_cost(0);
7064 format %{ "# TLS is in G2" %}
7065 ins_encode( /*empty encoding*/ );
7066 ins_pipe(ialu_none);
7067 %}
7068
7069 instruct checkCastPP( iRegP dst ) %{
7070 match(Set dst (CheckCastPP dst));
7071
7072 size(0);
7073 format %{ "# checkcastPP of $dst" %}
7074 ins_encode( /*empty encoding*/ );
7075 ins_pipe(empty);
7076 %}
7077
7078
7079 instruct castPP( iRegP dst ) %{
7080 match(Set dst (CastPP dst));
7081 format %{ "# castPP of $dst" %}
7082 ins_encode( /*empty encoding*/ );
7083 ins_pipe(empty);
7084 %}
7085
7086 instruct castII( iRegI dst ) %{
7087 match(Set dst (CastII dst));
7088 format %{ "# castII of $dst" %}
7089 ins_encode( /*empty encoding*/ );
7090 ins_cost(0);
7091 ins_pipe(empty);
7092 %}
7093
7094 //----------Arithmetic Instructions--------------------------------------------
7095 // Addition Instructions
7096 // Register Addition
7097 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7098 match(Set dst (AddI src1 src2));
7099
7100 size(4);
7101 format %{ "ADD $src1,$src2,$dst" %}
7102 ins_encode %{
7103 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7104 %}
7105 ins_pipe(ialu_reg_reg);
7106 %}
7107
7108 // Immediate Addition
7109 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7110 match(Set dst (AddI src1 src2));
7111
7112 size(4);
7113 format %{ "ADD $src1,$src2,$dst" %}
7114 opcode(Assembler::add_op3, Assembler::arith_op);
7115 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7116 ins_pipe(ialu_reg_imm);
7117 %}
7118
7119 // Pointer Register Addition
7120 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7121 match(Set dst (AddP src1 src2));
7122
7123 size(4);
7124 format %{ "ADD $src1,$src2,$dst" %}
7125 opcode(Assembler::add_op3, Assembler::arith_op);
7126 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7127 ins_pipe(ialu_reg_reg);
7128 %}
7129
7130 // Pointer Immediate Addition
7131 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7132 match(Set dst (AddP src1 src2));
7133
7134 size(4);
7135 format %{ "ADD $src1,$src2,$dst" %}
7136 opcode(Assembler::add_op3, Assembler::arith_op);
7137 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7138 ins_pipe(ialu_reg_imm);
7139 %}
7140
7141 // Long Addition
7142 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7143 match(Set dst (AddL src1 src2));
7144
7145 size(4);
7146 format %{ "ADD $src1,$src2,$dst\t! long" %}
7147 opcode(Assembler::add_op3, Assembler::arith_op);
7148 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7149 ins_pipe(ialu_reg_reg);
7150 %}
7151
7152 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7153 match(Set dst (AddL src1 con));
7154
7155 size(4);
7156 format %{ "ADD $src1,$con,$dst" %}
7157 opcode(Assembler::add_op3, Assembler::arith_op);
7158 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7159 ins_pipe(ialu_reg_imm);
7160 %}
7161
7162 //----------Conditional_store--------------------------------------------------
7163 // Conditional-store of the updated heap-top.
7164 // Used during allocation of the shared heap.
7165 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7166
7167 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7168 instruct loadPLocked(iRegP dst, memory mem) %{
7169 match(Set dst (LoadPLocked mem));
7170 ins_cost(MEMORY_REF_COST);
7171
7172 #ifndef _LP64
7173 size(4);
7174 format %{ "LDUW $mem,$dst\t! ptr" %}
7175 opcode(Assembler::lduw_op3, 0, REGP_OP);
7176 #else
7177 format %{ "LDX $mem,$dst\t! ptr" %}
7178 opcode(Assembler::ldx_op3, 0, REGP_OP);
7179 #endif
7180 ins_encode( form3_mem_reg( mem, dst ) );
7181 ins_pipe(iload_mem);
7182 %}
7183
7184 // LoadL-locked. Same as a regular long load when used with a compare-swap
7185 instruct loadLLocked(iRegL dst, memory mem) %{
7186 match(Set dst (LoadLLocked mem));
7187 ins_cost(MEMORY_REF_COST);
7188 size(4);
7189 format %{ "LDX $mem,$dst\t! long" %}
7190 opcode(Assembler::ldx_op3);
7191 ins_encode(simple_form3_mem_reg( mem, dst ) );
7192 ins_pipe(iload_mem);
7193 %}
7194
7195 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7196 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7197 effect( KILL newval );
7198 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7199 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7200 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7201 ins_pipe( long_memory_op );
7202 %}
7203
7204 // Conditional-store of an int value.
7205 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7206 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7207 effect( KILL newval );
7208 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7209 "CMP $oldval,$newval\t\t! See if we made progress" %}
7210 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7211 ins_pipe( long_memory_op );
7212 %}
7213
7214 // Conditional-store of a long value.
7215 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7216 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7217 effect( KILL newval );
7218 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7219 "CMP $oldval,$newval\t\t! See if we made progress" %}
7220 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7221 ins_pipe( long_memory_op );
7222 %}
7223
7224 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7225
7226 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7227 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7228 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7229 format %{
7230 "MOV $newval,O7\n\t"
7231 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7232 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7233 "MOV 1,$res\n\t"
7234 "MOVne xcc,R_G0,$res"
7235 %}
7236 ins_encode( enc_casx(mem_ptr, oldval, newval),
7237 enc_lflags_ne_to_boolean(res) );
7238 ins_pipe( long_memory_op );
7239 %}
7240
7241
7242 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7243 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7244 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7245 format %{
7246 "MOV $newval,O7\n\t"
7247 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7248 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7249 "MOV 1,$res\n\t"
7250 "MOVne icc,R_G0,$res"
7251 %}
7252 ins_encode( enc_casi(mem_ptr, oldval, newval),
7253 enc_iflags_ne_to_boolean(res) );
7254 ins_pipe( long_memory_op );
7255 %}
7256
7257 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7258 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7259 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7260 format %{
7261 "MOV $newval,O7\n\t"
7262 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7263 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7264 "MOV 1,$res\n\t"
7265 "MOVne xcc,R_G0,$res"
7266 %}
7267 #ifdef _LP64
7268 ins_encode( enc_casx(mem_ptr, oldval, newval),
7269 enc_lflags_ne_to_boolean(res) );
7270 #else
7271 ins_encode( enc_casi(mem_ptr, oldval, newval),
7272 enc_iflags_ne_to_boolean(res) );
7273 #endif
7274 ins_pipe( long_memory_op );
7275 %}
7276
7277 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7278 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7279 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7280 format %{
7281 "MOV $newval,O7\n\t"
7282 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7283 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7284 "MOV 1,$res\n\t"
7285 "MOVne icc,R_G0,$res"
7286 %}
7287 ins_encode( enc_casi(mem_ptr, oldval, newval),
7288 enc_iflags_ne_to_boolean(res) );
7289 ins_pipe( long_memory_op );
7290 %}
7291
7292 //---------------------
7293 // Subtraction Instructions
7294 // Register Subtraction
7295 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7296 match(Set dst (SubI src1 src2));
7297
7298 size(4);
7299 format %{ "SUB $src1,$src2,$dst" %}
7300 opcode(Assembler::sub_op3, Assembler::arith_op);
7301 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7302 ins_pipe(ialu_reg_reg);
7303 %}
7304
7305 // Immediate Subtraction
7306 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7307 match(Set dst (SubI src1 src2));
7308
7309 size(4);
7310 format %{ "SUB $src1,$src2,$dst" %}
7311 opcode(Assembler::sub_op3, Assembler::arith_op);
7312 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7313 ins_pipe(ialu_reg_imm);
7314 %}
7315
7316 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7317 match(Set dst (SubI zero src2));
7318
7319 size(4);
7320 format %{ "NEG $src2,$dst" %}
7321 opcode(Assembler::sub_op3, Assembler::arith_op);
7322 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7323 ins_pipe(ialu_zero_reg);
7324 %}
7325
7326 // Long subtraction
7327 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7328 match(Set dst (SubL src1 src2));
7329
7330 size(4);
7331 format %{ "SUB $src1,$src2,$dst\t! long" %}
7332 opcode(Assembler::sub_op3, Assembler::arith_op);
7333 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7334 ins_pipe(ialu_reg_reg);
7335 %}
7336
7337 // Immediate Subtraction
7338 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7339 match(Set dst (SubL src1 con));
7340
7341 size(4);
7342 format %{ "SUB $src1,$con,$dst\t! long" %}
7343 opcode(Assembler::sub_op3, Assembler::arith_op);
7344 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7345 ins_pipe(ialu_reg_imm);
7346 %}
7347
7348 // Long negation
7349 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7350 match(Set dst (SubL zero src2));
7351
7352 size(4);
7353 format %{ "NEG $src2,$dst\t! long" %}
7354 opcode(Assembler::sub_op3, Assembler::arith_op);
7355 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7356 ins_pipe(ialu_zero_reg);
7357 %}
7358
7359 // Multiplication Instructions
7360 // Integer Multiplication
7361 // Register Multiplication
7362 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7363 match(Set dst (MulI src1 src2));
7364
7365 size(4);
7366 format %{ "MULX $src1,$src2,$dst" %}
7367 opcode(Assembler::mulx_op3, Assembler::arith_op);
7368 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7369 ins_pipe(imul_reg_reg);
7370 %}
7371
7372 // Immediate Multiplication
7373 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7374 match(Set dst (MulI src1 src2));
7375
7376 size(4);
7377 format %{ "MULX $src1,$src2,$dst" %}
7378 opcode(Assembler::mulx_op3, Assembler::arith_op);
7379 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7380 ins_pipe(imul_reg_imm);
7381 %}
7382
7383 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7384 match(Set dst (MulL src1 src2));
7385 ins_cost(DEFAULT_COST * 5);
7386 size(4);
7387 format %{ "MULX $src1,$src2,$dst\t! long" %}
7388 opcode(Assembler::mulx_op3, Assembler::arith_op);
7389 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7390 ins_pipe(mulL_reg_reg);
7391 %}
7392
7393 // Immediate Multiplication
7394 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7395 match(Set dst (MulL src1 src2));
7396 ins_cost(DEFAULT_COST * 5);
7397 size(4);
7398 format %{ "MULX $src1,$src2,$dst" %}
7399 opcode(Assembler::mulx_op3, Assembler::arith_op);
7400 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7401 ins_pipe(mulL_reg_imm);
7402 %}
7403
7404 // Integer Division
7405 // Register Division
7406 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7407 match(Set dst (DivI src1 src2));
7408 ins_cost((2+71)*DEFAULT_COST);
7409
7410 format %{ "SRA $src2,0,$src2\n\t"
7411 "SRA $src1,0,$src1\n\t"
7412 "SDIVX $src1,$src2,$dst" %}
7413 ins_encode( idiv_reg( src1, src2, dst ) );
7414 ins_pipe(sdiv_reg_reg);
7415 %}
7416
7417 // Immediate Division
7418 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7419 match(Set dst (DivI src1 src2));
7420 ins_cost((2+71)*DEFAULT_COST);
7421
7422 format %{ "SRA $src1,0,$src1\n\t"
7423 "SDIVX $src1,$src2,$dst" %}
7424 ins_encode( idiv_imm( src1, src2, dst ) );
7425 ins_pipe(sdiv_reg_imm);
7426 %}
7427
7428 //----------Div-By-10-Expansion------------------------------------------------
7429 // Extract hi bits of a 32x32->64 bit multiply.
7430 // Expand rule only, not matched
7431 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7432 effect( DEF dst, USE src1, USE src2 );
7433 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7434 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7435 ins_encode( enc_mul_hi(dst,src1,src2));
7436 ins_pipe(sdiv_reg_reg);
7437 %}
7438
7439 // Magic constant, reciprocal of 10
7440 instruct loadConI_x66666667(iRegIsafe dst) %{
7441 effect( DEF dst );
7442
7443 size(8);
7444 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7445 ins_encode( Set32(0x66666667, dst) );
7446 ins_pipe(ialu_hi_lo_reg);
7447 %}
7448
7449 // Register Shift Right Arithmetic Long by 32-63
7450 instruct sra_31( iRegI dst, iRegI src ) %{
7451 effect( DEF dst, USE src );
7452 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7453 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7454 ins_pipe(ialu_reg_reg);
7455 %}
7456
7457 // Arithmetic Shift Right by 8-bit immediate
7458 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7459 effect( DEF dst, USE src );
7460 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7461 opcode(Assembler::sra_op3, Assembler::arith_op);
7462 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7463 ins_pipe(ialu_reg_imm);
7464 %}
7465
7466 // Integer DIV with 10
7467 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7468 match(Set dst (DivI src div));
7469 ins_cost((6+6)*DEFAULT_COST);
7470 expand %{
7471 iRegIsafe tmp1; // Killed temps;
7472 iRegIsafe tmp2; // Killed temps;
7473 iRegI tmp3; // Killed temps;
7474 iRegI tmp4; // Killed temps;
7475 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7476 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7477 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7478 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7479 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7480 %}
7481 %}
7482
7483 // Register Long Division
7484 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7485 match(Set dst (DivL src1 src2));
7486 ins_cost(DEFAULT_COST*71);
7487 size(4);
7488 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7489 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7490 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7491 ins_pipe(divL_reg_reg);
7492 %}
7493
7494 // Register Long Division
7495 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7496 match(Set dst (DivL src1 src2));
7497 ins_cost(DEFAULT_COST*71);
7498 size(4);
7499 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7500 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7501 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7502 ins_pipe(divL_reg_imm);
7503 %}
7504
7505 // Integer Remainder
7506 // Register Remainder
7507 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7508 match(Set dst (ModI src1 src2));
7509 effect( KILL ccr, KILL temp);
7510
7511 format %{ "SREM $src1,$src2,$dst" %}
7512 ins_encode( irem_reg(src1, src2, dst, temp) );
7513 ins_pipe(sdiv_reg_reg);
7514 %}
7515
7516 // Immediate Remainder
7517 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7518 match(Set dst (ModI src1 src2));
7519 effect( KILL ccr, KILL temp);
7520
7521 format %{ "SREM $src1,$src2,$dst" %}
7522 ins_encode( irem_imm(src1, src2, dst, temp) );
7523 ins_pipe(sdiv_reg_imm);
7524 %}
7525
7526 // Register Long Remainder
7527 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7528 effect(DEF dst, USE src1, USE src2);
7529 size(4);
7530 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7531 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7532 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7533 ins_pipe(divL_reg_reg);
7534 %}
7535
7536 // Register Long Division
7537 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7538 effect(DEF dst, USE src1, USE src2);
7539 size(4);
7540 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7541 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7542 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7543 ins_pipe(divL_reg_imm);
7544 %}
7545
7546 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7547 effect(DEF dst, USE src1, USE src2);
7548 size(4);
7549 format %{ "MULX $src1,$src2,$dst\t! long" %}
7550 opcode(Assembler::mulx_op3, Assembler::arith_op);
7551 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7552 ins_pipe(mulL_reg_reg);
7553 %}
7554
7555 // Immediate Multiplication
7556 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7557 effect(DEF dst, USE src1, USE src2);
7558 size(4);
7559 format %{ "MULX $src1,$src2,$dst" %}
7560 opcode(Assembler::mulx_op3, Assembler::arith_op);
7561 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7562 ins_pipe(mulL_reg_imm);
7563 %}
7564
7565 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7566 effect(DEF dst, USE src1, USE src2);
7567 size(4);
7568 format %{ "SUB $src1,$src2,$dst\t! long" %}
7569 opcode(Assembler::sub_op3, Assembler::arith_op);
7570 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7571 ins_pipe(ialu_reg_reg);
7572 %}
7573
7574 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7575 effect(DEF dst, USE src1, USE src2);
7576 size(4);
7577 format %{ "SUB $src1,$src2,$dst\t! long" %}
7578 opcode(Assembler::sub_op3, Assembler::arith_op);
7579 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7580 ins_pipe(ialu_reg_reg);
7581 %}
7582
7583 // Register Long Remainder
7584 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7585 match(Set dst (ModL src1 src2));
7586 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7587 expand %{
7588 iRegL tmp1;
7589 iRegL tmp2;
7590 divL_reg_reg_1(tmp1, src1, src2);
7591 mulL_reg_reg_1(tmp2, tmp1, src2);
7592 subL_reg_reg_1(dst, src1, tmp2);
7593 %}
7594 %}
7595
7596 // Register Long Remainder
7597 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7598 match(Set dst (ModL src1 src2));
7599 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7600 expand %{
7601 iRegL tmp1;
7602 iRegL tmp2;
7603 divL_reg_imm13_1(tmp1, src1, src2);
7604 mulL_reg_imm13_1(tmp2, tmp1, src2);
7605 subL_reg_reg_2 (dst, src1, tmp2);
7606 %}
7607 %}
7608
7609 // Integer Shift Instructions
7610 // Register Shift Left
7611 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7612 match(Set dst (LShiftI src1 src2));
7613
7614 size(4);
7615 format %{ "SLL $src1,$src2,$dst" %}
7616 opcode(Assembler::sll_op3, Assembler::arith_op);
7617 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7618 ins_pipe(ialu_reg_reg);
7619 %}
7620
7621 // Register Shift Left Immediate
7622 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7623 match(Set dst (LShiftI src1 src2));
7624
7625 size(4);
7626 format %{ "SLL $src1,$src2,$dst" %}
7627 opcode(Assembler::sll_op3, Assembler::arith_op);
7628 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7629 ins_pipe(ialu_reg_imm);
7630 %}
7631
7632 // Register Shift Left
7633 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7634 match(Set dst (LShiftL src1 src2));
7635
7636 size(4);
7637 format %{ "SLLX $src1,$src2,$dst" %}
7638 opcode(Assembler::sllx_op3, Assembler::arith_op);
7639 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7640 ins_pipe(ialu_reg_reg);
7641 %}
7642
7643 // Register Shift Left Immediate
7644 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7645 match(Set dst (LShiftL src1 src2));
7646
7647 size(4);
7648 format %{ "SLLX $src1,$src2,$dst" %}
7649 opcode(Assembler::sllx_op3, Assembler::arith_op);
7650 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7651 ins_pipe(ialu_reg_imm);
7652 %}
7653
7654 // Register Arithmetic Shift Right
7655 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7656 match(Set dst (RShiftI src1 src2));
7657 size(4);
7658 format %{ "SRA $src1,$src2,$dst" %}
7659 opcode(Assembler::sra_op3, Assembler::arith_op);
7660 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7661 ins_pipe(ialu_reg_reg);
7662 %}
7663
7664 // Register Arithmetic Shift Right Immediate
7665 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7666 match(Set dst (RShiftI src1 src2));
7667
7668 size(4);
7669 format %{ "SRA $src1,$src2,$dst" %}
7670 opcode(Assembler::sra_op3, Assembler::arith_op);
7671 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7672 ins_pipe(ialu_reg_imm);
7673 %}
7674
7675 // Register Shift Right Arithmatic Long
7676 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7677 match(Set dst (RShiftL src1 src2));
7678
7679 size(4);
7680 format %{ "SRAX $src1,$src2,$dst" %}
7681 opcode(Assembler::srax_op3, Assembler::arith_op);
7682 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7683 ins_pipe(ialu_reg_reg);
7684 %}
7685
7686 // Register Shift Left Immediate
7687 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7688 match(Set dst (RShiftL src1 src2));
7689
7690 size(4);
7691 format %{ "SRAX $src1,$src2,$dst" %}
7692 opcode(Assembler::srax_op3, Assembler::arith_op);
7693 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7694 ins_pipe(ialu_reg_imm);
7695 %}
7696
7697 // Register Shift Right
7698 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7699 match(Set dst (URShiftI src1 src2));
7700
7701 size(4);
7702 format %{ "SRL $src1,$src2,$dst" %}
7703 opcode(Assembler::srl_op3, Assembler::arith_op);
7704 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7705 ins_pipe(ialu_reg_reg);
7706 %}
7707
7708 // Register Shift Right Immediate
7709 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7710 match(Set dst (URShiftI src1 src2));
7711
7712 size(4);
7713 format %{ "SRL $src1,$src2,$dst" %}
7714 opcode(Assembler::srl_op3, Assembler::arith_op);
7715 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7716 ins_pipe(ialu_reg_imm);
7717 %}
7718
7719 // Register Shift Right
7720 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7721 match(Set dst (URShiftL src1 src2));
7722
7723 size(4);
7724 format %{ "SRLX $src1,$src2,$dst" %}
7725 opcode(Assembler::srlx_op3, Assembler::arith_op);
7726 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7727 ins_pipe(ialu_reg_reg);
7728 %}
7729
7730 // Register Shift Right Immediate
7731 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7732 match(Set dst (URShiftL src1 src2));
7733
7734 size(4);
7735 format %{ "SRLX $src1,$src2,$dst" %}
7736 opcode(Assembler::srlx_op3, Assembler::arith_op);
7737 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7738 ins_pipe(ialu_reg_imm);
7739 %}
7740
7741 // Register Shift Right Immediate with a CastP2X
7742 #ifdef _LP64
7743 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7744 match(Set dst (URShiftL (CastP2X src1) src2));
7745 size(4);
7746 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7747 opcode(Assembler::srlx_op3, Assembler::arith_op);
7748 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7749 ins_pipe(ialu_reg_imm);
7750 %}
7751 #else
7752 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7753 match(Set dst (URShiftI (CastP2X src1) src2));
7754 size(4);
7755 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7756 opcode(Assembler::srl_op3, Assembler::arith_op);
7757 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7758 ins_pipe(ialu_reg_imm);
7759 %}
7760 #endif
7761
7762
7763 //----------Floating Point Arithmetic Instructions-----------------------------
7764
7765 // Add float single precision
7766 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7767 match(Set dst (AddF src1 src2));
7768
7769 size(4);
7770 format %{ "FADDS $src1,$src2,$dst" %}
7771 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7772 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7773 ins_pipe(faddF_reg_reg);
7774 %}
7775
7776 // Add float double precision
7777 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7778 match(Set dst (AddD src1 src2));
7779
7780 size(4);
7781 format %{ "FADDD $src1,$src2,$dst" %}
7782 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7783 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7784 ins_pipe(faddD_reg_reg);
7785 %}
7786
7787 // Sub float single precision
7788 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7789 match(Set dst (SubF src1 src2));
7790
7791 size(4);
7792 format %{ "FSUBS $src1,$src2,$dst" %}
7793 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7794 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7795 ins_pipe(faddF_reg_reg);
7796 %}
7797
7798 // Sub float double precision
7799 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7800 match(Set dst (SubD src1 src2));
7801
7802 size(4);
7803 format %{ "FSUBD $src1,$src2,$dst" %}
7804 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7805 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7806 ins_pipe(faddD_reg_reg);
7807 %}
7808
7809 // Mul float single precision
7810 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7811 match(Set dst (MulF src1 src2));
7812
7813 size(4);
7814 format %{ "FMULS $src1,$src2,$dst" %}
7815 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7816 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7817 ins_pipe(fmulF_reg_reg);
7818 %}
7819
7820 // Mul float double precision
7821 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7822 match(Set dst (MulD src1 src2));
7823
7824 size(4);
7825 format %{ "FMULD $src1,$src2,$dst" %}
7826 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7827 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7828 ins_pipe(fmulD_reg_reg);
7829 %}
7830
7831 // Div float single precision
7832 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7833 match(Set dst (DivF src1 src2));
7834
7835 size(4);
7836 format %{ "FDIVS $src1,$src2,$dst" %}
7837 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7838 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7839 ins_pipe(fdivF_reg_reg);
7840 %}
7841
7842 // Div float double precision
7843 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7844 match(Set dst (DivD src1 src2));
7845
7846 size(4);
7847 format %{ "FDIVD $src1,$src2,$dst" %}
7848 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7849 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7850 ins_pipe(fdivD_reg_reg);
7851 %}
7852
7853 // Absolute float double precision
7854 instruct absD_reg(regD dst, regD src) %{
7855 match(Set dst (AbsD src));
7856
7857 format %{ "FABSd $src,$dst" %}
7858 ins_encode(fabsd(dst, src));
7859 ins_pipe(faddD_reg);
7860 %}
7861
7862 // Absolute float single precision
7863 instruct absF_reg(regF dst, regF src) %{
7864 match(Set dst (AbsF src));
7865
7866 format %{ "FABSs $src,$dst" %}
7867 ins_encode(fabss(dst, src));
7868 ins_pipe(faddF_reg);
7869 %}
7870
7871 instruct negF_reg(regF dst, regF src) %{
7872 match(Set dst (NegF src));
7873
7874 size(4);
7875 format %{ "FNEGs $src,$dst" %}
7876 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7877 ins_encode(form3_opf_rs2F_rdF(src, dst));
7878 ins_pipe(faddF_reg);
7879 %}
7880
7881 instruct negD_reg(regD dst, regD src) %{
7882 match(Set dst (NegD src));
7883
7884 format %{ "FNEGd $src,$dst" %}
7885 ins_encode(fnegd(dst, src));
7886 ins_pipe(faddD_reg);
7887 %}
7888
7889 // Sqrt float double precision
7890 instruct sqrtF_reg_reg(regF dst, regF src) %{
7891 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7892
7893 size(4);
7894 format %{ "FSQRTS $src,$dst" %}
7895 ins_encode(fsqrts(dst, src));
7896 ins_pipe(fdivF_reg_reg);
7897 %}
7898
7899 // Sqrt float double precision
7900 instruct sqrtD_reg_reg(regD dst, regD src) %{
7901 match(Set dst (SqrtD src));
7902
7903 size(4);
7904 format %{ "FSQRTD $src,$dst" %}
7905 ins_encode(fsqrtd(dst, src));
7906 ins_pipe(fdivD_reg_reg);
7907 %}
7908
7909 //----------Logical Instructions-----------------------------------------------
7910 // And Instructions
7911 // Register And
7912 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7913 match(Set dst (AndI src1 src2));
7914
7915 size(4);
7916 format %{ "AND $src1,$src2,$dst" %}
7917 opcode(Assembler::and_op3, Assembler::arith_op);
7918 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7919 ins_pipe(ialu_reg_reg);
7920 %}
7921
7922 // Immediate And
7923 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7924 match(Set dst (AndI src1 src2));
7925
7926 size(4);
7927 format %{ "AND $src1,$src2,$dst" %}
7928 opcode(Assembler::and_op3, Assembler::arith_op);
7929 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7930 ins_pipe(ialu_reg_imm);
7931 %}
7932
7933 // Register And Long
7934 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7935 match(Set dst (AndL src1 src2));
7936
7937 ins_cost(DEFAULT_COST);
7938 size(4);
7939 format %{ "AND $src1,$src2,$dst\t! long" %}
7940 opcode(Assembler::and_op3, Assembler::arith_op);
7941 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7942 ins_pipe(ialu_reg_reg);
7943 %}
7944
7945 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7946 match(Set dst (AndL src1 con));
7947
7948 ins_cost(DEFAULT_COST);
7949 size(4);
7950 format %{ "AND $src1,$con,$dst\t! long" %}
7951 opcode(Assembler::and_op3, Assembler::arith_op);
7952 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7953 ins_pipe(ialu_reg_imm);
7954 %}
7955
7956 // Or Instructions
7957 // Register Or
7958 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7959 match(Set dst (OrI src1 src2));
7960
7961 size(4);
7962 format %{ "OR $src1,$src2,$dst" %}
7963 opcode(Assembler::or_op3, Assembler::arith_op);
7964 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7965 ins_pipe(ialu_reg_reg);
7966 %}
7967
7968 // Immediate Or
7969 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7970 match(Set dst (OrI src1 src2));
7971
7972 size(4);
7973 format %{ "OR $src1,$src2,$dst" %}
7974 opcode(Assembler::or_op3, Assembler::arith_op);
7975 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7976 ins_pipe(ialu_reg_imm);
7977 %}
7978
7979 // Register Or Long
7980 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7981 match(Set dst (OrL src1 src2));
7982
7983 ins_cost(DEFAULT_COST);
7984 size(4);
7985 format %{ "OR $src1,$src2,$dst\t! long" %}
7986 opcode(Assembler::or_op3, Assembler::arith_op);
7987 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7988 ins_pipe(ialu_reg_reg);
7989 %}
7990
7991 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7992 match(Set dst (OrL src1 con));
7993 ins_cost(DEFAULT_COST*2);
7994
7995 ins_cost(DEFAULT_COST);
7996 size(4);
7997 format %{ "OR $src1,$con,$dst\t! long" %}
7998 opcode(Assembler::or_op3, Assembler::arith_op);
7999 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8000 ins_pipe(ialu_reg_imm);
8001 %}
8002
8003 #ifndef _LP64
8004
8005 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8006 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8007 match(Set dst (OrI src1 (CastP2X src2)));
8008
8009 size(4);
8010 format %{ "OR $src1,$src2,$dst" %}
8011 opcode(Assembler::or_op3, Assembler::arith_op);
8012 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8013 ins_pipe(ialu_reg_reg);
8014 %}
8015
8016 #else
8017
8018 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8019 match(Set dst (OrL src1 (CastP2X src2)));
8020
8021 ins_cost(DEFAULT_COST);
8022 size(4);
8023 format %{ "OR $src1,$src2,$dst\t! long" %}
8024 opcode(Assembler::or_op3, Assembler::arith_op);
8025 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8026 ins_pipe(ialu_reg_reg);
8027 %}
8028
8029 #endif
8030
8031 // Xor Instructions
8032 // Register Xor
8033 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8034 match(Set dst (XorI src1 src2));
8035
8036 size(4);
8037 format %{ "XOR $src1,$src2,$dst" %}
8038 opcode(Assembler::xor_op3, Assembler::arith_op);
8039 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8040 ins_pipe(ialu_reg_reg);
8041 %}
8042
8043 // Immediate Xor
8044 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8045 match(Set dst (XorI src1 src2));
8046
8047 size(4);
8048 format %{ "XOR $src1,$src2,$dst" %}
8049 opcode(Assembler::xor_op3, Assembler::arith_op);
8050 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8051 ins_pipe(ialu_reg_imm);
8052 %}
8053
8054 // Register Xor Long
8055 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8056 match(Set dst (XorL src1 src2));
8057
8058 ins_cost(DEFAULT_COST);
8059 size(4);
8060 format %{ "XOR $src1,$src2,$dst\t! long" %}
8061 opcode(Assembler::xor_op3, Assembler::arith_op);
8062 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8063 ins_pipe(ialu_reg_reg);
8064 %}
8065
8066 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8067 match(Set dst (XorL src1 con));
8068
8069 ins_cost(DEFAULT_COST);
8070 size(4);
8071 format %{ "XOR $src1,$con,$dst\t! long" %}
8072 opcode(Assembler::xor_op3, Assembler::arith_op);
8073 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8074 ins_pipe(ialu_reg_imm);
8075 %}
8076
8077 //----------Convert to Boolean-------------------------------------------------
8078 // Nice hack for 32-bit tests but doesn't work for
8079 // 64-bit pointers.
8080 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8081 match(Set dst (Conv2B src));
8082 effect( KILL ccr );
8083 ins_cost(DEFAULT_COST*2);
8084 format %{ "CMP R_G0,$src\n\t"
8085 "ADDX R_G0,0,$dst" %}
8086 ins_encode( enc_to_bool( src, dst ) );
8087 ins_pipe(ialu_reg_ialu);
8088 %}
8089
8090 #ifndef _LP64
8091 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8092 match(Set dst (Conv2B src));
8093 effect( KILL ccr );
8094 ins_cost(DEFAULT_COST*2);
8095 format %{ "CMP R_G0,$src\n\t"
8096 "ADDX R_G0,0,$dst" %}
8097 ins_encode( enc_to_bool( src, dst ) );
8098 ins_pipe(ialu_reg_ialu);
8099 %}
8100 #else
8101 instruct convP2B( iRegI dst, iRegP src ) %{
8102 match(Set dst (Conv2B src));
8103 ins_cost(DEFAULT_COST*2);
8104 format %{ "MOV $src,$dst\n\t"
8105 "MOVRNZ $src,1,$dst" %}
8106 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8107 ins_pipe(ialu_clr_and_mover);
8108 %}
8109 #endif
8110
8111 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8112 match(Set dst (CmpLTMask src zero));
8113 effect(KILL ccr);
8114 size(4);
8115 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8116 ins_encode %{
8117 __ sra($src$$Register, 31, $dst$$Register);
8118 %}
8119 ins_pipe(ialu_reg_imm);
8120 %}
8121
8122 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8123 match(Set dst (CmpLTMask p q));
8124 effect( KILL ccr );
8125 ins_cost(DEFAULT_COST*4);
8126 format %{ "CMP $p,$q\n\t"
8127 "MOV #0,$dst\n\t"
8128 "BLT,a .+8\n\t"
8129 "MOV #-1,$dst" %}
8130 ins_encode( enc_ltmask(p,q,dst) );
8131 ins_pipe(ialu_reg_reg_ialu);
8132 %}
8133
8134 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8135 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8136 effect(KILL ccr, TEMP tmp);
8137 ins_cost(DEFAULT_COST*3);
8138
8139 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8140 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8141 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8142 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8143 ins_pipe( cadd_cmpltmask );
8144 %}
8145
8146
8147 //-----------------------------------------------------------------
8148 // Direct raw moves between float and general registers using VIS3.
8149
8150 // ins_pipe(faddF_reg);
8151 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8152 predicate(UseVIS >= 3);
8153 match(Set dst (MoveF2I src));
8154
8155 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8156 ins_encode %{
8157 __ movstouw($src$$FloatRegister, $dst$$Register);
8158 %}
8159 ins_pipe(ialu_reg_reg);
8160 %}
8161
8162 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8163 predicate(UseVIS >= 3);
8164 match(Set dst (MoveI2F src));
8165
8166 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8167 ins_encode %{
8168 __ movwtos($src$$Register, $dst$$FloatRegister);
8169 %}
8170 ins_pipe(ialu_reg_reg);
8171 %}
8172
8173 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8174 predicate(UseVIS >= 3);
8175 match(Set dst (MoveD2L src));
8176
8177 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8178 ins_encode %{
8179 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8180 %}
8181 ins_pipe(ialu_reg_reg);
8182 %}
8183
8184 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8185 predicate(UseVIS >= 3);
8186 match(Set dst (MoveL2D src));
8187
8188 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8189 ins_encode %{
8190 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8191 %}
8192 ins_pipe(ialu_reg_reg);
8193 %}
8194
8195
8196 // Raw moves between float and general registers using stack.
8197
8198 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8199 match(Set dst (MoveF2I src));
8200 effect(DEF dst, USE src);
8201 ins_cost(MEMORY_REF_COST);
8202
8203 size(4);
8204 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8205 opcode(Assembler::lduw_op3);
8206 ins_encode(simple_form3_mem_reg( src, dst ) );
8207 ins_pipe(iload_mem);
8208 %}
8209
8210 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8211 match(Set dst (MoveI2F src));
8212 effect(DEF dst, USE src);
8213 ins_cost(MEMORY_REF_COST);
8214
8215 size(4);
8216 format %{ "LDF $src,$dst\t! MoveI2F" %}
8217 opcode(Assembler::ldf_op3);
8218 ins_encode(simple_form3_mem_reg(src, dst));
8219 ins_pipe(floadF_stk);
8220 %}
8221
8222 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8223 match(Set dst (MoveD2L src));
8224 effect(DEF dst, USE src);
8225 ins_cost(MEMORY_REF_COST);
8226
8227 size(4);
8228 format %{ "LDX $src,$dst\t! MoveD2L" %}
8229 opcode(Assembler::ldx_op3);
8230 ins_encode(simple_form3_mem_reg( src, dst ) );
8231 ins_pipe(iload_mem);
8232 %}
8233
8234 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8235 match(Set dst (MoveL2D src));
8236 effect(DEF dst, USE src);
8237 ins_cost(MEMORY_REF_COST);
8238
8239 size(4);
8240 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8241 opcode(Assembler::lddf_op3);
8242 ins_encode(simple_form3_mem_reg(src, dst));
8243 ins_pipe(floadD_stk);
8244 %}
8245
8246 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8247 match(Set dst (MoveF2I src));
8248 effect(DEF dst, USE src);
8249 ins_cost(MEMORY_REF_COST);
8250
8251 size(4);
8252 format %{ "STF $src,$dst\t! MoveF2I" %}
8253 opcode(Assembler::stf_op3);
8254 ins_encode(simple_form3_mem_reg(dst, src));
8255 ins_pipe(fstoreF_stk_reg);
8256 %}
8257
8258 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8259 match(Set dst (MoveI2F src));
8260 effect(DEF dst, USE src);
8261 ins_cost(MEMORY_REF_COST);
8262
8263 size(4);
8264 format %{ "STW $src,$dst\t! MoveI2F" %}
8265 opcode(Assembler::stw_op3);
8266 ins_encode(simple_form3_mem_reg( dst, src ) );
8267 ins_pipe(istore_mem_reg);
8268 %}
8269
8270 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8271 match(Set dst (MoveD2L src));
8272 effect(DEF dst, USE src);
8273 ins_cost(MEMORY_REF_COST);
8274
8275 size(4);
8276 format %{ "STDF $src,$dst\t! MoveD2L" %}
8277 opcode(Assembler::stdf_op3);
8278 ins_encode(simple_form3_mem_reg(dst, src));
8279 ins_pipe(fstoreD_stk_reg);
8280 %}
8281
8282 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8283 match(Set dst (MoveL2D src));
8284 effect(DEF dst, USE src);
8285 ins_cost(MEMORY_REF_COST);
8286
8287 size(4);
8288 format %{ "STX $src,$dst\t! MoveL2D" %}
8289 opcode(Assembler::stx_op3);
8290 ins_encode(simple_form3_mem_reg( dst, src ) );
8291 ins_pipe(istore_mem_reg);
8292 %}
8293
8294
8295 //----------Arithmetic Conversion Instructions---------------------------------
8296 // The conversions operations are all Alpha sorted. Please keep it that way!
8297
8298 instruct convD2F_reg(regF dst, regD src) %{
8299 match(Set dst (ConvD2F src));
8300 size(4);
8301 format %{ "FDTOS $src,$dst" %}
8302 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8303 ins_encode(form3_opf_rs2D_rdF(src, dst));
8304 ins_pipe(fcvtD2F);
8305 %}
8306
8307
8308 // Convert a double to an int in a float register.
8309 // If the double is a NAN, stuff a zero in instead.
8310 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8311 effect(DEF dst, USE src, KILL fcc0);
8312 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8313 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8314 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8315 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8316 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8317 "skip:" %}
8318 ins_encode(form_d2i_helper(src,dst));
8319 ins_pipe(fcvtD2I);
8320 %}
8321
8322 instruct convD2I_stk(stackSlotI dst, regD src) %{
8323 match(Set dst (ConvD2I src));
8324 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8325 expand %{
8326 regF tmp;
8327 convD2I_helper(tmp, src);
8328 regF_to_stkI(dst, tmp);
8329 %}
8330 %}
8331
8332 instruct convD2I_reg(iRegI dst, regD src) %{
8333 predicate(UseVIS >= 3);
8334 match(Set dst (ConvD2I src));
8335 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8336 expand %{
8337 regF tmp;
8338 convD2I_helper(tmp, src);
8339 MoveF2I_reg_reg(dst, tmp);
8340 %}
8341 %}
8342
8343
8344 // Convert a double to a long in a double register.
8345 // If the double is a NAN, stuff a zero in instead.
8346 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8347 effect(DEF dst, USE src, KILL fcc0);
8348 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8349 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8350 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8351 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8352 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8353 "skip:" %}
8354 ins_encode(form_d2l_helper(src,dst));
8355 ins_pipe(fcvtD2L);
8356 %}
8357
8358 instruct convD2L_stk(stackSlotL dst, regD src) %{
8359 match(Set dst (ConvD2L src));
8360 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8361 expand %{
8362 regD tmp;
8363 convD2L_helper(tmp, src);
8364 regD_to_stkL(dst, tmp);
8365 %}
8366 %}
8367
8368 instruct convD2L_reg(iRegL dst, regD src) %{
8369 predicate(UseVIS >= 3);
8370 match(Set dst (ConvD2L src));
8371 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8372 expand %{
8373 regD tmp;
8374 convD2L_helper(tmp, src);
8375 MoveD2L_reg_reg(dst, tmp);
8376 %}
8377 %}
8378
8379
8380 instruct convF2D_reg(regD dst, regF src) %{
8381 match(Set dst (ConvF2D src));
8382 format %{ "FSTOD $src,$dst" %}
8383 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8384 ins_encode(form3_opf_rs2F_rdD(src, dst));
8385 ins_pipe(fcvtF2D);
8386 %}
8387
8388
8389 // Convert a float to an int in a float register.
8390 // If the float is a NAN, stuff a zero in instead.
8391 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8392 effect(DEF dst, USE src, KILL fcc0);
8393 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8394 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8395 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8396 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8397 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8398 "skip:" %}
8399 ins_encode(form_f2i_helper(src,dst));
8400 ins_pipe(fcvtF2I);
8401 %}
8402
8403 instruct convF2I_stk(stackSlotI dst, regF src) %{
8404 match(Set dst (ConvF2I src));
8405 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8406 expand %{
8407 regF tmp;
8408 convF2I_helper(tmp, src);
8409 regF_to_stkI(dst, tmp);
8410 %}
8411 %}
8412
8413 instruct convF2I_reg(iRegI dst, regF src) %{
8414 predicate(UseVIS >= 3);
8415 match(Set dst (ConvF2I src));
8416 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8417 expand %{
8418 regF tmp;
8419 convF2I_helper(tmp, src);
8420 MoveF2I_reg_reg(dst, tmp);
8421 %}
8422 %}
8423
8424
8425 // Convert a float to a long in a float register.
8426 // If the float is a NAN, stuff a zero in instead.
8427 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8428 effect(DEF dst, USE src, KILL fcc0);
8429 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8430 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8431 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8432 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8433 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8434 "skip:" %}
8435 ins_encode(form_f2l_helper(src,dst));
8436 ins_pipe(fcvtF2L);
8437 %}
8438
8439 instruct convF2L_stk(stackSlotL dst, regF src) %{
8440 match(Set dst (ConvF2L src));
8441 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8442 expand %{
8443 regD tmp;
8444 convF2L_helper(tmp, src);
8445 regD_to_stkL(dst, tmp);
8446 %}
8447 %}
8448
8449 instruct convF2L_reg(iRegL dst, regF src) %{
8450 predicate(UseVIS >= 3);
8451 match(Set dst (ConvF2L src));
8452 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8453 expand %{
8454 regD tmp;
8455 convF2L_helper(tmp, src);
8456 MoveD2L_reg_reg(dst, tmp);
8457 %}
8458 %}
8459
8460
8461 instruct convI2D_helper(regD dst, regF tmp) %{
8462 effect(USE tmp, DEF dst);
8463 format %{ "FITOD $tmp,$dst" %}
8464 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8465 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8466 ins_pipe(fcvtI2D);
8467 %}
8468
8469 instruct convI2D_stk(stackSlotI src, regD dst) %{
8470 match(Set dst (ConvI2D src));
8471 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8472 expand %{
8473 regF tmp;
8474 stkI_to_regF(tmp, src);
8475 convI2D_helper(dst, tmp);
8476 %}
8477 %}
8478
8479 instruct convI2D_reg(regD_low dst, iRegI src) %{
8480 predicate(UseVIS >= 3);
8481 match(Set dst (ConvI2D src));
8482 expand %{
8483 regF tmp;
8484 MoveI2F_reg_reg(tmp, src);
8485 convI2D_helper(dst, tmp);
8486 %}
8487 %}
8488
8489 instruct convI2D_mem(regD_low dst, memory mem) %{
8490 match(Set dst (ConvI2D (LoadI mem)));
8491 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8492 size(8);
8493 format %{ "LDF $mem,$dst\n\t"
8494 "FITOD $dst,$dst" %}
8495 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8496 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8497 ins_pipe(floadF_mem);
8498 %}
8499
8500
8501 instruct convI2F_helper(regF dst, regF tmp) %{
8502 effect(DEF dst, USE tmp);
8503 format %{ "FITOS $tmp,$dst" %}
8504 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8505 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8506 ins_pipe(fcvtI2F);
8507 %}
8508
8509 instruct convI2F_stk(regF dst, stackSlotI src) %{
8510 match(Set dst (ConvI2F src));
8511 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8512 expand %{
8513 regF tmp;
8514 stkI_to_regF(tmp,src);
8515 convI2F_helper(dst, tmp);
8516 %}
8517 %}
8518
8519 instruct convI2F_reg(regF dst, iRegI src) %{
8520 predicate(UseVIS >= 3);
8521 match(Set dst (ConvI2F src));
8522 ins_cost(DEFAULT_COST);
8523 expand %{
8524 regF tmp;
8525 MoveI2F_reg_reg(tmp, src);
8526 convI2F_helper(dst, tmp);
8527 %}
8528 %}
8529
8530 instruct convI2F_mem( regF dst, memory mem ) %{
8531 match(Set dst (ConvI2F (LoadI mem)));
8532 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8533 size(8);
8534 format %{ "LDF $mem,$dst\n\t"
8535 "FITOS $dst,$dst" %}
8536 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8537 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8538 ins_pipe(floadF_mem);
8539 %}
8540
8541
8542 instruct convI2L_reg(iRegL dst, iRegI src) %{
8543 match(Set dst (ConvI2L src));
8544 size(4);
8545 format %{ "SRA $src,0,$dst\t! int->long" %}
8546 opcode(Assembler::sra_op3, Assembler::arith_op);
8547 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8548 ins_pipe(ialu_reg_reg);
8549 %}
8550
8551 // Zero-extend convert int to long
8552 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8553 match(Set dst (AndL (ConvI2L src) mask) );
8554 size(4);
8555 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8556 opcode(Assembler::srl_op3, Assembler::arith_op);
8557 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8558 ins_pipe(ialu_reg_reg);
8559 %}
8560
8561 // Zero-extend long
8562 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8563 match(Set dst (AndL src mask) );
8564 size(4);
8565 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8566 opcode(Assembler::srl_op3, Assembler::arith_op);
8567 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8568 ins_pipe(ialu_reg_reg);
8569 %}
8570
8571
8572 //-----------
8573 // Long to Double conversion using V8 opcodes.
8574 // Still useful because cheetah traps and becomes
8575 // amazingly slow for some common numbers.
8576
8577 // Magic constant, 0x43300000
8578 instruct loadConI_x43300000(iRegI dst) %{
8579 effect(DEF dst);
8580 size(4);
8581 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8582 ins_encode(SetHi22(0x43300000, dst));
8583 ins_pipe(ialu_none);
8584 %}
8585
8586 // Magic constant, 0x41f00000
8587 instruct loadConI_x41f00000(iRegI dst) %{
8588 effect(DEF dst);
8589 size(4);
8590 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8591 ins_encode(SetHi22(0x41f00000, dst));
8592 ins_pipe(ialu_none);
8593 %}
8594
8595 // Construct a double from two float halves
8596 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8597 effect(DEF dst, USE src1, USE src2);
8598 size(8);
8599 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8600 "FMOVS $src2.lo,$dst.lo" %}
8601 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8602 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8603 ins_pipe(faddD_reg_reg);
8604 %}
8605
8606 // Convert integer in high half of a double register (in the lower half of
8607 // the double register file) to double
8608 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8609 effect(DEF dst, USE src);
8610 size(4);
8611 format %{ "FITOD $src,$dst" %}
8612 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8613 ins_encode(form3_opf_rs2D_rdD(src, dst));
8614 ins_pipe(fcvtLHi2D);
8615 %}
8616
8617 // Add float double precision
8618 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8619 effect(DEF dst, USE src1, USE src2);
8620 size(4);
8621 format %{ "FADDD $src1,$src2,$dst" %}
8622 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8623 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8624 ins_pipe(faddD_reg_reg);
8625 %}
8626
8627 // Sub float double precision
8628 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8629 effect(DEF dst, USE src1, USE src2);
8630 size(4);
8631 format %{ "FSUBD $src1,$src2,$dst" %}
8632 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8633 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8634 ins_pipe(faddD_reg_reg);
8635 %}
8636
8637 // Mul float double precision
8638 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8639 effect(DEF dst, USE src1, USE src2);
8640 size(4);
8641 format %{ "FMULD $src1,$src2,$dst" %}
8642 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8643 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8644 ins_pipe(fmulD_reg_reg);
8645 %}
8646
8647 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8648 match(Set dst (ConvL2D src));
8649 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8650
8651 expand %{
8652 regD_low tmpsrc;
8653 iRegI ix43300000;
8654 iRegI ix41f00000;
8655 stackSlotL lx43300000;
8656 stackSlotL lx41f00000;
8657 regD_low dx43300000;
8658 regD dx41f00000;
8659 regD tmp1;
8660 regD_low tmp2;
8661 regD tmp3;
8662 regD tmp4;
8663
8664 stkL_to_regD(tmpsrc, src);
8665
8666 loadConI_x43300000(ix43300000);
8667 loadConI_x41f00000(ix41f00000);
8668 regI_to_stkLHi(lx43300000, ix43300000);
8669 regI_to_stkLHi(lx41f00000, ix41f00000);
8670 stkL_to_regD(dx43300000, lx43300000);
8671 stkL_to_regD(dx41f00000, lx41f00000);
8672
8673 convI2D_regDHi_regD(tmp1, tmpsrc);
8674 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8675 subD_regD_regD(tmp3, tmp2, dx43300000);
8676 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8677 addD_regD_regD(dst, tmp3, tmp4);
8678 %}
8679 %}
8680
8681 // Long to Double conversion using fast fxtof
8682 instruct convL2D_helper(regD dst, regD tmp) %{
8683 effect(DEF dst, USE tmp);
8684 size(4);
8685 format %{ "FXTOD $tmp,$dst" %}
8686 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8687 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8688 ins_pipe(fcvtL2D);
8689 %}
8690
8691 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8692 predicate(VM_Version::has_fast_fxtof());
8693 match(Set dst (ConvL2D src));
8694 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8695 expand %{
8696 regD tmp;
8697 stkL_to_regD(tmp, src);
8698 convL2D_helper(dst, tmp);
8699 %}
8700 %}
8701
8702 instruct convL2D_reg(regD dst, iRegL src) %{
8703 predicate(UseVIS >= 3);
8704 match(Set dst (ConvL2D src));
8705 expand %{
8706 regD tmp;
8707 MoveL2D_reg_reg(tmp, src);
8708 convL2D_helper(dst, tmp);
8709 %}
8710 %}
8711
8712 // Long to Float conversion using fast fxtof
8713 instruct convL2F_helper(regF dst, regD tmp) %{
8714 effect(DEF dst, USE tmp);
8715 size(4);
8716 format %{ "FXTOS $tmp,$dst" %}
8717 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8718 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8719 ins_pipe(fcvtL2F);
8720 %}
8721
8722 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8723 match(Set dst (ConvL2F src));
8724 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8725 expand %{
8726 regD tmp;
8727 stkL_to_regD(tmp, src);
8728 convL2F_helper(dst, tmp);
8729 %}
8730 %}
8731
8732 instruct convL2F_reg(regF dst, iRegL src) %{
8733 predicate(UseVIS >= 3);
8734 match(Set dst (ConvL2F src));
8735 ins_cost(DEFAULT_COST);
8736 expand %{
8737 regD tmp;
8738 MoveL2D_reg_reg(tmp, src);
8739 convL2F_helper(dst, tmp);
8740 %}
8741 %}
8742
8743 //-----------
8744
8745 instruct convL2I_reg(iRegI dst, iRegL src) %{
8746 match(Set dst (ConvL2I src));
8747 #ifndef _LP64
8748 format %{ "MOV $src.lo,$dst\t! long->int" %}
8749 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8750 ins_pipe(ialu_move_reg_I_to_L);
8751 #else
8752 size(4);
8753 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8754 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8755 ins_pipe(ialu_reg);
8756 #endif
8757 %}
8758
8759 // Register Shift Right Immediate
8760 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8761 match(Set dst (ConvL2I (RShiftL src cnt)));
8762
8763 size(4);
8764 format %{ "SRAX $src,$cnt,$dst" %}
8765 opcode(Assembler::srax_op3, Assembler::arith_op);
8766 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8767 ins_pipe(ialu_reg_imm);
8768 %}
8769
8770 // Replicate scalar to packed byte values in Double register
8771 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8772 effect(DEF dst, USE src);
8773 format %{ "SLLX $src,56,$dst\n\t"
8774 "SRLX $dst, 8,O7\n\t"
8775 "OR $dst,O7,$dst\n\t"
8776 "SRLX $dst,16,O7\n\t"
8777 "OR $dst,O7,$dst\n\t"
8778 "SRLX $dst,32,O7\n\t"
8779 "OR $dst,O7,$dst\t! replicate8B" %}
8780 ins_encode( enc_repl8b(src, dst));
8781 ins_pipe(ialu_reg);
8782 %}
8783
8784 // Replicate scalar to packed byte values in Double register
8785 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8786 match(Set dst (Replicate8B src));
8787 expand %{
8788 iRegL tmp;
8789 Repl8B_reg_helper(tmp, src);
8790 regL_to_stkD(dst, tmp);
8791 %}
8792 %}
8793
8794 // Replicate scalar constant to packed byte values in Double register
8795 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
8796 match(Set dst (Replicate8B con));
8797 effect(KILL tmp);
8798 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8799 ins_encode %{
8800 // XXX This is a quick fix for 6833573.
8801 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8802 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
8803 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8804 %}
8805 ins_pipe(loadConFD);
8806 %}
8807
8808 // Replicate scalar to packed char values into stack slot
8809 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8810 effect(DEF dst, USE src);
8811 format %{ "SLLX $src,48,$dst\n\t"
8812 "SRLX $dst,16,O7\n\t"
8813 "OR $dst,O7,$dst\n\t"
8814 "SRLX $dst,32,O7\n\t"
8815 "OR $dst,O7,$dst\t! replicate4C" %}
8816 ins_encode( enc_repl4s(src, dst) );
8817 ins_pipe(ialu_reg);
8818 %}
8819
8820 // Replicate scalar to packed char values into stack slot
8821 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8822 match(Set dst (Replicate4C src));
8823 expand %{
8824 iRegL tmp;
8825 Repl4C_reg_helper(tmp, src);
8826 regL_to_stkD(dst, tmp);
8827 %}
8828 %}
8829
8830 // Replicate scalar constant to packed char values in Double register
8831 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
8832 match(Set dst (Replicate4C con));
8833 effect(KILL tmp);
8834 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8835 ins_encode %{
8836 // XXX This is a quick fix for 6833573.
8837 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8838 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8839 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8840 %}
8841 ins_pipe(loadConFD);
8842 %}
8843
8844 // Replicate scalar to packed short values into stack slot
8845 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8846 effect(DEF dst, USE src);
8847 format %{ "SLLX $src,48,$dst\n\t"
8848 "SRLX $dst,16,O7\n\t"
8849 "OR $dst,O7,$dst\n\t"
8850 "SRLX $dst,32,O7\n\t"
8851 "OR $dst,O7,$dst\t! replicate4S" %}
8852 ins_encode( enc_repl4s(src, dst) );
8853 ins_pipe(ialu_reg);
8854 %}
8855
8856 // Replicate scalar to packed short values into stack slot
8857 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8858 match(Set dst (Replicate4S src));
8859 expand %{
8860 iRegL tmp;
8861 Repl4S_reg_helper(tmp, src);
8862 regL_to_stkD(dst, tmp);
8863 %}
8864 %}
8865
8866 // Replicate scalar constant to packed short values in Double register
8867 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
8868 match(Set dst (Replicate4S con));
8869 effect(KILL tmp);
8870 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8871 ins_encode %{
8872 // XXX This is a quick fix for 6833573.
8873 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8874 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8875 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8876 %}
8877 ins_pipe(loadConFD);
8878 %}
8879
8880 // Replicate scalar to packed int values in Double register
8881 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8882 effect(DEF dst, USE src);
8883 format %{ "SLLX $src,32,$dst\n\t"
8884 "SRLX $dst,32,O7\n\t"
8885 "OR $dst,O7,$dst\t! replicate2I" %}
8886 ins_encode( enc_repl2i(src, dst));
8887 ins_pipe(ialu_reg);
8888 %}
8889
8890 // Replicate scalar to packed int values in Double register
8891 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8892 match(Set dst (Replicate2I src));
8893 expand %{
8894 iRegL tmp;
8895 Repl2I_reg_helper(tmp, src);
8896 regL_to_stkD(dst, tmp);
8897 %}
8898 %}
8899
8900 // Replicate scalar zero constant to packed int values in Double register
8901 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
8902 match(Set dst (Replicate2I con));
8903 effect(KILL tmp);
8904 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
8905 ins_encode %{
8906 // XXX This is a quick fix for 6833573.
8907 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
8908 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
8909 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8910 %}
8911 ins_pipe(loadConFD);
8912 %}
8913
8914 //----------Control Flow Instructions------------------------------------------
8915 // Compare Instructions
8916 // Compare Integers
8917 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8918 match(Set icc (CmpI op1 op2));
8919 effect( DEF icc, USE op1, USE op2 );
8920
8921 size(4);
8922 format %{ "CMP $op1,$op2" %}
8923 opcode(Assembler::subcc_op3, Assembler::arith_op);
8924 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8925 ins_pipe(ialu_cconly_reg_reg);
8926 %}
8927
8928 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8929 match(Set icc (CmpU op1 op2));
8930
8931 size(4);
8932 format %{ "CMP $op1,$op2\t! unsigned" %}
8933 opcode(Assembler::subcc_op3, Assembler::arith_op);
8934 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8935 ins_pipe(ialu_cconly_reg_reg);
8936 %}
8937
8938 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8939 match(Set icc (CmpI op1 op2));
8940 effect( DEF icc, USE op1 );
8941
8942 size(4);
8943 format %{ "CMP $op1,$op2" %}
8944 opcode(Assembler::subcc_op3, Assembler::arith_op);
8945 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8946 ins_pipe(ialu_cconly_reg_imm);
8947 %}
8948
8949 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8950 match(Set icc (CmpI (AndI op1 op2) zero));
8951
8952 size(4);
8953 format %{ "BTST $op2,$op1" %}
8954 opcode(Assembler::andcc_op3, Assembler::arith_op);
8955 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8956 ins_pipe(ialu_cconly_reg_reg_zero);
8957 %}
8958
8959 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8960 match(Set icc (CmpI (AndI op1 op2) zero));
8961
8962 size(4);
8963 format %{ "BTST $op2,$op1" %}
8964 opcode(Assembler::andcc_op3, Assembler::arith_op);
8965 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8966 ins_pipe(ialu_cconly_reg_imm_zero);
8967 %}
8968
8969 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8970 match(Set xcc (CmpL op1 op2));
8971 effect( DEF xcc, USE op1, USE op2 );
8972
8973 size(4);
8974 format %{ "CMP $op1,$op2\t\t! long" %}
8975 opcode(Assembler::subcc_op3, Assembler::arith_op);
8976 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8977 ins_pipe(ialu_cconly_reg_reg);
8978 %}
8979
8980 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8981 match(Set xcc (CmpL op1 con));
8982 effect( DEF xcc, USE op1, USE con );
8983
8984 size(4);
8985 format %{ "CMP $op1,$con\t\t! long" %}
8986 opcode(Assembler::subcc_op3, Assembler::arith_op);
8987 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8988 ins_pipe(ialu_cconly_reg_reg);
8989 %}
8990
8991 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8992 match(Set xcc (CmpL (AndL op1 op2) zero));
8993 effect( DEF xcc, USE op1, USE op2 );
8994
8995 size(4);
8996 format %{ "BTST $op1,$op2\t\t! long" %}
8997 opcode(Assembler::andcc_op3, Assembler::arith_op);
8998 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8999 ins_pipe(ialu_cconly_reg_reg);
9000 %}
9001
9002 // useful for checking the alignment of a pointer:
9003 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
9004 match(Set xcc (CmpL (AndL op1 con) zero));
9005 effect( DEF xcc, USE op1, USE con );
9006
9007 size(4);
9008 format %{ "BTST $op1,$con\t\t! long" %}
9009 opcode(Assembler::andcc_op3, Assembler::arith_op);
9010 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9011 ins_pipe(ialu_cconly_reg_reg);
9012 %}
9013
9014 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
9015 match(Set icc (CmpU op1 op2));
9016
9017 size(4);
9018 format %{ "CMP $op1,$op2\t! unsigned" %}
9019 opcode(Assembler::subcc_op3, Assembler::arith_op);
9020 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9021 ins_pipe(ialu_cconly_reg_imm);
9022 %}
9023
9024 // Compare Pointers
9025 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9026 match(Set pcc (CmpP op1 op2));
9027
9028 size(4);
9029 format %{ "CMP $op1,$op2\t! ptr" %}
9030 opcode(Assembler::subcc_op3, Assembler::arith_op);
9031 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9032 ins_pipe(ialu_cconly_reg_reg);
9033 %}
9034
9035 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9036 match(Set pcc (CmpP op1 op2));
9037
9038 size(4);
9039 format %{ "CMP $op1,$op2\t! ptr" %}
9040 opcode(Assembler::subcc_op3, Assembler::arith_op);
9041 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9042 ins_pipe(ialu_cconly_reg_imm);
9043 %}
9044
9045 // Compare Narrow oops
9046 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9047 match(Set icc (CmpN op1 op2));
9048
9049 size(4);
9050 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9051 opcode(Assembler::subcc_op3, Assembler::arith_op);
9052 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9053 ins_pipe(ialu_cconly_reg_reg);
9054 %}
9055
9056 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9057 match(Set icc (CmpN op1 op2));
9058
9059 size(4);
9060 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9061 opcode(Assembler::subcc_op3, Assembler::arith_op);
9062 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9063 ins_pipe(ialu_cconly_reg_imm);
9064 %}
9065
9066 //----------Max and Min--------------------------------------------------------
9067 // Min Instructions
9068 // Conditional move for min
9069 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9070 effect( USE_DEF op2, USE op1, USE icc );
9071
9072 size(4);
9073 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9074 opcode(Assembler::less);
9075 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9076 ins_pipe(ialu_reg_flags);
9077 %}
9078
9079 // Min Register with Register.
9080 instruct minI_eReg(iRegI op1, iRegI op2) %{
9081 match(Set op2 (MinI op1 op2));
9082 ins_cost(DEFAULT_COST*2);
9083 expand %{
9084 flagsReg icc;
9085 compI_iReg(icc,op1,op2);
9086 cmovI_reg_lt(op2,op1,icc);
9087 %}
9088 %}
9089
9090 // Max Instructions
9091 // Conditional move for max
9092 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9093 effect( USE_DEF op2, USE op1, USE icc );
9094 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9095 opcode(Assembler::greater);
9096 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9097 ins_pipe(ialu_reg_flags);
9098 %}
9099
9100 // Max Register with Register
9101 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9102 match(Set op2 (MaxI op1 op2));
9103 ins_cost(DEFAULT_COST*2);
9104 expand %{
9105 flagsReg icc;
9106 compI_iReg(icc,op1,op2);
9107 cmovI_reg_gt(op2,op1,icc);
9108 %}
9109 %}
9110
9111
9112 //----------Float Compares----------------------------------------------------
9113 // Compare floating, generate condition code
9114 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9115 match(Set fcc (CmpF src1 src2));
9116
9117 size(4);
9118 format %{ "FCMPs $fcc,$src1,$src2" %}
9119 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9120 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9121 ins_pipe(faddF_fcc_reg_reg_zero);
9122 %}
9123
9124 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9125 match(Set fcc (CmpD src1 src2));
9126
9127 size(4);
9128 format %{ "FCMPd $fcc,$src1,$src2" %}
9129 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9130 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9131 ins_pipe(faddD_fcc_reg_reg_zero);
9132 %}
9133
9134
9135 // Compare floating, generate -1,0,1
9136 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9137 match(Set dst (CmpF3 src1 src2));
9138 effect(KILL fcc0);
9139 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9140 format %{ "fcmpl $dst,$src1,$src2" %}
9141 // Primary = float
9142 opcode( true );
9143 ins_encode( floating_cmp( dst, src1, src2 ) );
9144 ins_pipe( floating_cmp );
9145 %}
9146
9147 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9148 match(Set dst (CmpD3 src1 src2));
9149 effect(KILL fcc0);
9150 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9151 format %{ "dcmpl $dst,$src1,$src2" %}
9152 // Primary = double (not float)
9153 opcode( false );
9154 ins_encode( floating_cmp( dst, src1, src2 ) );
9155 ins_pipe( floating_cmp );
9156 %}
9157
9158 //----------Branches---------------------------------------------------------
9159 // Jump
9160 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9161 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9162 match(Jump switch_val);
9163
9164 ins_cost(350);
9165
9166 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9167 "LD [O7 + $switch_val], O7\n\t"
9168 "JUMP O7"
9169 %}
9170 ins_encode %{
9171 // Calculate table address into a register.
9172 Register table_reg;
9173 Register label_reg = O7;
9174 if (constant_offset() == 0) {
9175 table_reg = $constanttablebase;
9176 } else {
9177 table_reg = O7;
9178 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9179 __ add($constanttablebase, con_offset, table_reg);
9180 }
9181
9182 // Jump to base address + switch value
9183 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9184 __ jmp(label_reg, G0);
9185 __ delayed()->nop();
9186 %}
9187 ins_pc_relative(1);
9188 ins_pipe(ialu_reg_reg);
9189 %}
9190
9191 // Direct Branch. Use V8 version with longer range.
9192 instruct branch(label labl) %{
9193 match(Goto);
9194 effect(USE labl);
9195
9196 size(8);
9197 ins_cost(BRANCH_COST);
9198 format %{ "BA $labl" %}
9199 ins_encode %{
9200 Label* L = $labl$$label;
9201 assert(L != NULL, "need Label");
9202 __ ba(*L, false);
9203 __ delayed()->nop();
9204 %}
9205 ins_pc_relative(1);
9206 ins_pipe(br);
9207 %}
9208
9209 // Conditional Direct Branch
9210 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9211 match(If cmp icc);
9212 effect(USE labl);
9213
9214 size(8);
9215 ins_cost(BRANCH_COST);
9216 format %{ "BP$cmp $icc,$labl" %}
9217 // Prim = bits 24-22, Secnd = bits 31-30
9218 ins_encode( enc_bp( labl, cmp, icc ) );
9219 ins_pc_relative(1);
9220 ins_pipe(br_cc);
9221 %}
9222
9223 // Branch-on-register tests all 64 bits. We assume that values
9224 // in 64-bit registers always remains zero or sign extended
9225 // unless our code munges the high bits. Interrupts can chop
9226 // the high order bits to zero or sign at any time.
9227 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9228 match(If cmp (CmpI op1 zero));
9229 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9230 effect(USE labl);
9231
9232 size(8);
9233 ins_cost(BRANCH_COST);
9234 format %{ "BR$cmp $op1,$labl" %}
9235 ins_encode( enc_bpr( labl, cmp, op1 ) );
9236 ins_pc_relative(1);
9237 ins_pipe(br_reg);
9238 %}
9239
9240 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9241 match(If cmp (CmpP op1 null));
9242 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9243 effect(USE labl);
9244
9245 size(8);
9246 ins_cost(BRANCH_COST);
9247 format %{ "BR$cmp $op1,$labl" %}
9248 ins_encode( enc_bpr( labl, cmp, op1 ) );
9249 ins_pc_relative(1);
9250 ins_pipe(br_reg);
9251 %}
9252
9253 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9254 match(If cmp (CmpL op1 zero));
9255 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9256 effect(USE labl);
9257
9258 size(8);
9259 ins_cost(BRANCH_COST);
9260 format %{ "BR$cmp $op1,$labl" %}
9261 ins_encode( enc_bpr( labl, cmp, op1 ) );
9262 ins_pc_relative(1);
9263 ins_pipe(br_reg);
9264 %}
9265
9266 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9267 match(If cmp icc);
9268 effect(USE labl);
9269
9270 format %{ "BP$cmp $icc,$labl" %}
9271 // Prim = bits 24-22, Secnd = bits 31-30
9272 ins_encode( enc_bp( labl, cmp, icc ) );
9273 ins_pc_relative(1);
9274 ins_pipe(br_cc);
9275 %}
9276
9277 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9278 match(If cmp pcc);
9279 effect(USE labl);
9280
9281 size(8);
9282 ins_cost(BRANCH_COST);
9283 format %{ "BP$cmp $pcc,$labl" %}
9284 ins_encode %{
9285 Label* L = $labl$$label;
9286 assert(L != NULL, "need Label");
9287 Assembler::Predict predict_taken =
9288 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9289
9290 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9291 __ delayed()->nop();
9292 %}
9293 ins_pc_relative(1);
9294 ins_pipe(br_cc);
9295 %}
9296
9297 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9298 match(If cmp fcc);
9299 effect(USE labl);
9300
9301 size(8);
9302 ins_cost(BRANCH_COST);
9303 format %{ "FBP$cmp $fcc,$labl" %}
9304 ins_encode %{
9305 Label* L = $labl$$label;
9306 assert(L != NULL, "need Label");
9307 Assembler::Predict predict_taken =
9308 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9309
9310 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9311 __ delayed()->nop();
9312 %}
9313 ins_pc_relative(1);
9314 ins_pipe(br_fcc);
9315 %}
9316
9317 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9318 match(CountedLoopEnd cmp icc);
9319 effect(USE labl);
9320
9321 size(8);
9322 ins_cost(BRANCH_COST);
9323 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9324 // Prim = bits 24-22, Secnd = bits 31-30
9325 ins_encode( enc_bp( labl, cmp, icc ) );
9326 ins_pc_relative(1);
9327 ins_pipe(br_cc);
9328 %}
9329
9330 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9331 match(CountedLoopEnd cmp icc);
9332 effect(USE labl);
9333
9334 size(8);
9335 ins_cost(BRANCH_COST);
9336 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9337 // Prim = bits 24-22, Secnd = bits 31-30
9338 ins_encode( enc_bp( labl, cmp, icc ) );
9339 ins_pc_relative(1);
9340 ins_pipe(br_cc);
9341 %}
9342
9343 // ============================================================================
9344 // Long Compare
9345 //
9346 // Currently we hold longs in 2 registers. Comparing such values efficiently
9347 // is tricky. The flavor of compare used depends on whether we are testing
9348 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9349 // The GE test is the negated LT test. The LE test can be had by commuting
9350 // the operands (yielding a GE test) and then negating; negate again for the
9351 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9352 // NE test is negated from that.
9353
9354 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9355 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9356 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9357 // are collapsed internally in the ADLC's dfa-gen code. The match for
9358 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9359 // foo match ends up with the wrong leaf. One fix is to not match both
9360 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9361 // both forms beat the trinary form of long-compare and both are very useful
9362 // on Intel which has so few registers.
9363
9364 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9365 match(If cmp xcc);
9366 effect(USE labl);
9367
9368 size(8);
9369 ins_cost(BRANCH_COST);
9370 format %{ "BP$cmp $xcc,$labl" %}
9371 ins_encode %{
9372 Label* L = $labl$$label;
9373 assert(L != NULL, "need Label");
9374 Assembler::Predict predict_taken =
9375 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9376
9377 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9378 __ delayed()->nop();
9379 %}
9380 ins_pc_relative(1);
9381 ins_pipe(br_cc);
9382 %}
9383
9384 // Manifest a CmpL3 result in an integer register. Very painful.
9385 // This is the test to avoid.
9386 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9387 match(Set dst (CmpL3 src1 src2) );
9388 effect( KILL ccr );
9389 ins_cost(6*DEFAULT_COST);
9390 size(24);
9391 format %{ "CMP $src1,$src2\t\t! long\n"
9392 "\tBLT,a,pn done\n"
9393 "\tMOV -1,$dst\t! delay slot\n"
9394 "\tBGT,a,pn done\n"
9395 "\tMOV 1,$dst\t! delay slot\n"
9396 "\tCLR $dst\n"
9397 "done:" %}
9398 ins_encode( cmpl_flag(src1,src2,dst) );
9399 ins_pipe(cmpL_reg);
9400 %}
9401
9402 // Conditional move
9403 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9404 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9405 ins_cost(150);
9406 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9407 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9408 ins_pipe(ialu_reg);
9409 %}
9410
9411 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9412 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9413 ins_cost(140);
9414 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9415 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9416 ins_pipe(ialu_imm);
9417 %}
9418
9419 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9420 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9421 ins_cost(150);
9422 format %{ "MOV$cmp $xcc,$src,$dst" %}
9423 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9424 ins_pipe(ialu_reg);
9425 %}
9426
9427 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9428 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9429 ins_cost(140);
9430 format %{ "MOV$cmp $xcc,$src,$dst" %}
9431 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9432 ins_pipe(ialu_imm);
9433 %}
9434
9435 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9436 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9437 ins_cost(150);
9438 format %{ "MOV$cmp $xcc,$src,$dst" %}
9439 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9440 ins_pipe(ialu_reg);
9441 %}
9442
9443 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9444 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9445 ins_cost(150);
9446 format %{ "MOV$cmp $xcc,$src,$dst" %}
9447 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9448 ins_pipe(ialu_reg);
9449 %}
9450
9451 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9452 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9453 ins_cost(140);
9454 format %{ "MOV$cmp $xcc,$src,$dst" %}
9455 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9456 ins_pipe(ialu_imm);
9457 %}
9458
9459 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9460 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9461 ins_cost(150);
9462 opcode(0x101);
9463 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9464 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9465 ins_pipe(int_conditional_float_move);
9466 %}
9467
9468 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9469 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9470 ins_cost(150);
9471 opcode(0x102);
9472 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9473 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9474 ins_pipe(int_conditional_float_move);
9475 %}
9476
9477 // ============================================================================
9478 // Safepoint Instruction
9479 instruct safePoint_poll(iRegP poll) %{
9480 match(SafePoint poll);
9481 effect(USE poll);
9482
9483 size(4);
9484 #ifdef _LP64
9485 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9486 #else
9487 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9488 #endif
9489 ins_encode %{
9490 __ relocate(relocInfo::poll_type);
9491 __ ld_ptr($poll$$Register, 0, G0);
9492 %}
9493 ins_pipe(loadPollP);
9494 %}
9495
9496 // ============================================================================
9497 // Call Instructions
9498 // Call Java Static Instruction
9499 instruct CallStaticJavaDirect( method meth ) %{
9500 match(CallStaticJava);
9501 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9502 effect(USE meth);
9503
9504 size(8);
9505 ins_cost(CALL_COST);
9506 format %{ "CALL,static ; NOP ==> " %}
9507 ins_encode( Java_Static_Call( meth ), call_epilog );
9508 ins_pc_relative(1);
9509 ins_pipe(simple_call);
9510 %}
9511
9512 // Call Java Static Instruction (method handle version)
9513 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9514 match(CallStaticJava);
9515 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9516 effect(USE meth, KILL l7_mh_SP_save);
9517
9518 size(8);
9519 ins_cost(CALL_COST);
9520 format %{ "CALL,static/MethodHandle" %}
9521 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9522 ins_pc_relative(1);
9523 ins_pipe(simple_call);
9524 %}
9525
9526 // Call Java Dynamic Instruction
9527 instruct CallDynamicJavaDirect( method meth ) %{
9528 match(CallDynamicJava);
9529 effect(USE meth);
9530
9531 ins_cost(CALL_COST);
9532 format %{ "SET (empty),R_G5\n\t"
9533 "CALL,dynamic ; NOP ==> " %}
9534 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9535 ins_pc_relative(1);
9536 ins_pipe(call);
9537 %}
9538
9539 // Call Runtime Instruction
9540 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9541 match(CallRuntime);
9542 effect(USE meth, KILL l7);
9543 ins_cost(CALL_COST);
9544 format %{ "CALL,runtime" %}
9545 ins_encode( Java_To_Runtime( meth ),
9546 call_epilog, adjust_long_from_native_call );
9547 ins_pc_relative(1);
9548 ins_pipe(simple_call);
9549 %}
9550
9551 // Call runtime without safepoint - same as CallRuntime
9552 instruct CallLeafDirect(method meth, l7RegP l7) %{
9553 match(CallLeaf);
9554 effect(USE meth, KILL l7);
9555 ins_cost(CALL_COST);
9556 format %{ "CALL,runtime leaf" %}
9557 ins_encode( Java_To_Runtime( meth ),
9558 call_epilog,
9559 adjust_long_from_native_call );
9560 ins_pc_relative(1);
9561 ins_pipe(simple_call);
9562 %}
9563
9564 // Call runtime without safepoint - same as CallLeaf
9565 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9566 match(CallLeafNoFP);
9567 effect(USE meth, KILL l7);
9568 ins_cost(CALL_COST);
9569 format %{ "CALL,runtime leaf nofp" %}
9570 ins_encode( Java_To_Runtime( meth ),
9571 call_epilog,
9572 adjust_long_from_native_call );
9573 ins_pc_relative(1);
9574 ins_pipe(simple_call);
9575 %}
9576
9577 // Tail Call; Jump from runtime stub to Java code.
9578 // Also known as an 'interprocedural jump'.
9579 // Target of jump will eventually return to caller.
9580 // TailJump below removes the return address.
9581 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9582 match(TailCall jump_target method_oop );
9583
9584 ins_cost(CALL_COST);
9585 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9586 ins_encode(form_jmpl(jump_target));
9587 ins_pipe(tail_call);
9588 %}
9589
9590
9591 // Return Instruction
9592 instruct Ret() %{
9593 match(Return);
9594
9595 // The epilogue node did the ret already.
9596 size(0);
9597 format %{ "! return" %}
9598 ins_encode();
9599 ins_pipe(empty);
9600 %}
9601
9602
9603 // Tail Jump; remove the return address; jump to target.
9604 // TailCall above leaves the return address around.
9605 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9606 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9607 // "restore" before this instruction (in Epilogue), we need to materialize it
9608 // in %i0.
9609 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9610 match( TailJump jump_target ex_oop );
9611 ins_cost(CALL_COST);
9612 format %{ "! discard R_O7\n\t"
9613 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9614 ins_encode(form_jmpl_set_exception_pc(jump_target));
9615 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9616 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9617 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9618 ins_pipe(tail_call);
9619 %}
9620
9621 // Create exception oop: created by stack-crawling runtime code.
9622 // Created exception is now available to this handler, and is setup
9623 // just prior to jumping to this handler. No code emitted.
9624 instruct CreateException( o0RegP ex_oop )
9625 %{
9626 match(Set ex_oop (CreateEx));
9627 ins_cost(0);
9628
9629 size(0);
9630 // use the following format syntax
9631 format %{ "! exception oop is in R_O0; no code emitted" %}
9632 ins_encode();
9633 ins_pipe(empty);
9634 %}
9635
9636
9637 // Rethrow exception:
9638 // The exception oop will come in the first argument position.
9639 // Then JUMP (not call) to the rethrow stub code.
9640 instruct RethrowException()
9641 %{
9642 match(Rethrow);
9643 ins_cost(CALL_COST);
9644
9645 // use the following format syntax
9646 format %{ "Jmp rethrow_stub" %}
9647 ins_encode(enc_rethrow);
9648 ins_pipe(tail_call);
9649 %}
9650
9651
9652 // Die now
9653 instruct ShouldNotReachHere( )
9654 %{
9655 match(Halt);
9656 ins_cost(CALL_COST);
9657
9658 size(4);
9659 // Use the following format syntax
9660 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9661 ins_encode( form2_illtrap() );
9662 ins_pipe(tail_call);
9663 %}
9664
9665 // ============================================================================
9666 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9667 // array for an instance of the superklass. Set a hidden internal cache on a
9668 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9669 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9670 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9671 match(Set index (PartialSubtypeCheck sub super));
9672 effect( KILL pcc, KILL o7 );
9673 ins_cost(DEFAULT_COST*10);
9674 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9675 ins_encode( enc_PartialSubtypeCheck() );
9676 ins_pipe(partial_subtype_check_pipe);
9677 %}
9678
9679 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9680 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9681 effect( KILL idx, KILL o7 );
9682 ins_cost(DEFAULT_COST*10);
9683 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9684 ins_encode( enc_PartialSubtypeCheck() );
9685 ins_pipe(partial_subtype_check_pipe);
9686 %}
9687
9688
9689 // ============================================================================
9690 // inlined locking and unlocking
9691
9692 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9693 match(Set pcc (FastLock object box));
9694
9695 effect(KILL scratch, TEMP scratch2);
9696 ins_cost(100);
9697
9698 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9699 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9700 ins_pipe(long_memory_op);
9701 %}
9702
9703
9704 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9705 match(Set pcc (FastUnlock object box));
9706 effect(KILL scratch, TEMP scratch2);
9707 ins_cost(100);
9708
9709 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9710 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9711 ins_pipe(long_memory_op);
9712 %}
9713
9714 // Count and Base registers are fixed because the allocator cannot
9715 // kill unknown registers. The encodings are generic.
9716 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9717 match(Set dummy (ClearArray cnt base));
9718 effect(TEMP temp, KILL ccr);
9719 ins_cost(300);
9720 format %{ "MOV $cnt,$temp\n"
9721 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9722 " BRge loop\t\t! Clearing loop\n"
9723 " STX G0,[$base+$temp]\t! delay slot" %}
9724 ins_encode( enc_Clear_Array(cnt, base, temp) );
9725 ins_pipe(long_memory_op);
9726 %}
9727
9728 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9729 o7RegI tmp, flagsReg ccr) %{
9730 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9731 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9732 ins_cost(300);
9733 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9734 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
9735 ins_pipe(long_memory_op);
9736 %}
9737
9738 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9739 o7RegI tmp, flagsReg ccr) %{
9740 match(Set result (StrEquals (Binary str1 str2) cnt));
9741 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9742 ins_cost(300);
9743 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
9744 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
9745 ins_pipe(long_memory_op);
9746 %}
9747
9748 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9749 o7RegI tmp2, flagsReg ccr) %{
9750 match(Set result (AryEq ary1 ary2));
9751 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9752 ins_cost(300);
9753 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9754 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9755 ins_pipe(long_memory_op);
9756 %}
9757
9758
9759 //---------- Zeros Count Instructions ------------------------------------------
9760
9761 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9762 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9763 match(Set dst (CountLeadingZerosI src));
9764 effect(TEMP dst, TEMP tmp, KILL cr);
9765
9766 // x |= (x >> 1);
9767 // x |= (x >> 2);
9768 // x |= (x >> 4);
9769 // x |= (x >> 8);
9770 // x |= (x >> 16);
9771 // return (WORDBITS - popc(x));
9772 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
9773 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
9774 "OR $dst,$tmp,$dst\n\t"
9775 "SRL $dst,2,$tmp\n\t"
9776 "OR $dst,$tmp,$dst\n\t"
9777 "SRL $dst,4,$tmp\n\t"
9778 "OR $dst,$tmp,$dst\n\t"
9779 "SRL $dst,8,$tmp\n\t"
9780 "OR $dst,$tmp,$dst\n\t"
9781 "SRL $dst,16,$tmp\n\t"
9782 "OR $dst,$tmp,$dst\n\t"
9783 "POPC $dst,$dst\n\t"
9784 "MOV 32,$tmp\n\t"
9785 "SUB $tmp,$dst,$dst" %}
9786 ins_encode %{
9787 Register Rdst = $dst$$Register;
9788 Register Rsrc = $src$$Register;
9789 Register Rtmp = $tmp$$Register;
9790 __ srl(Rsrc, 1, Rtmp);
9791 __ srl(Rsrc, 0, Rdst);
9792 __ or3(Rdst, Rtmp, Rdst);
9793 __ srl(Rdst, 2, Rtmp);
9794 __ or3(Rdst, Rtmp, Rdst);
9795 __ srl(Rdst, 4, Rtmp);
9796 __ or3(Rdst, Rtmp, Rdst);
9797 __ srl(Rdst, 8, Rtmp);
9798 __ or3(Rdst, Rtmp, Rdst);
9799 __ srl(Rdst, 16, Rtmp);
9800 __ or3(Rdst, Rtmp, Rdst);
9801 __ popc(Rdst, Rdst);
9802 __ mov(BitsPerInt, Rtmp);
9803 __ sub(Rtmp, Rdst, Rdst);
9804 %}
9805 ins_pipe(ialu_reg);
9806 %}
9807
9808 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
9809 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9810 match(Set dst (CountLeadingZerosL src));
9811 effect(TEMP dst, TEMP tmp, KILL cr);
9812
9813 // x |= (x >> 1);
9814 // x |= (x >> 2);
9815 // x |= (x >> 4);
9816 // x |= (x >> 8);
9817 // x |= (x >> 16);
9818 // x |= (x >> 32);
9819 // return (WORDBITS - popc(x));
9820 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
9821 "OR $src,$tmp,$dst\n\t"
9822 "SRLX $dst,2,$tmp\n\t"
9823 "OR $dst,$tmp,$dst\n\t"
9824 "SRLX $dst,4,$tmp\n\t"
9825 "OR $dst,$tmp,$dst\n\t"
9826 "SRLX $dst,8,$tmp\n\t"
9827 "OR $dst,$tmp,$dst\n\t"
9828 "SRLX $dst,16,$tmp\n\t"
9829 "OR $dst,$tmp,$dst\n\t"
9830 "SRLX $dst,32,$tmp\n\t"
9831 "OR $dst,$tmp,$dst\n\t"
9832 "POPC $dst,$dst\n\t"
9833 "MOV 64,$tmp\n\t"
9834 "SUB $tmp,$dst,$dst" %}
9835 ins_encode %{
9836 Register Rdst = $dst$$Register;
9837 Register Rsrc = $src$$Register;
9838 Register Rtmp = $tmp$$Register;
9839 __ srlx(Rsrc, 1, Rtmp);
9840 __ or3( Rsrc, Rtmp, Rdst);
9841 __ srlx(Rdst, 2, Rtmp);
9842 __ or3( Rdst, Rtmp, Rdst);
9843 __ srlx(Rdst, 4, Rtmp);
9844 __ or3( Rdst, Rtmp, Rdst);
9845 __ srlx(Rdst, 8, Rtmp);
9846 __ or3( Rdst, Rtmp, Rdst);
9847 __ srlx(Rdst, 16, Rtmp);
9848 __ or3( Rdst, Rtmp, Rdst);
9849 __ srlx(Rdst, 32, Rtmp);
9850 __ or3( Rdst, Rtmp, Rdst);
9851 __ popc(Rdst, Rdst);
9852 __ mov(BitsPerLong, Rtmp);
9853 __ sub(Rtmp, Rdst, Rdst);
9854 %}
9855 ins_pipe(ialu_reg);
9856 %}
9857
9858 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9859 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9860 match(Set dst (CountTrailingZerosI src));
9861 effect(TEMP dst, KILL cr);
9862
9863 // return popc(~x & (x - 1));
9864 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
9865 "ANDN $dst,$src,$dst\n\t"
9866 "SRL $dst,R_G0,$dst\n\t"
9867 "POPC $dst,$dst" %}
9868 ins_encode %{
9869 Register Rdst = $dst$$Register;
9870 Register Rsrc = $src$$Register;
9871 __ sub(Rsrc, 1, Rdst);
9872 __ andn(Rdst, Rsrc, Rdst);
9873 __ srl(Rdst, G0, Rdst);
9874 __ popc(Rdst, Rdst);
9875 %}
9876 ins_pipe(ialu_reg);
9877 %}
9878
9879 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9880 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9881 match(Set dst (CountTrailingZerosL src));
9882 effect(TEMP dst, KILL cr);
9883
9884 // return popc(~x & (x - 1));
9885 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
9886 "ANDN $dst,$src,$dst\n\t"
9887 "POPC $dst,$dst" %}
9888 ins_encode %{
9889 Register Rdst = $dst$$Register;
9890 Register Rsrc = $src$$Register;
9891 __ sub(Rsrc, 1, Rdst);
9892 __ andn(Rdst, Rsrc, Rdst);
9893 __ popc(Rdst, Rdst);
9894 %}
9895 ins_pipe(ialu_reg);
9896 %}
9897
9898
9899 //---------- Population Count Instructions -------------------------------------
9900
9901 instruct popCountI(iRegI dst, iRegI src) %{
9902 predicate(UsePopCountInstruction);
9903 match(Set dst (PopCountI src));
9904
9905 format %{ "POPC $src, $dst" %}
9906 ins_encode %{
9907 __ popc($src$$Register, $dst$$Register);
9908 %}
9909 ins_pipe(ialu_reg);
9910 %}
9911
9912 // Note: Long.bitCount(long) returns an int.
9913 instruct popCountL(iRegI dst, iRegL src) %{
9914 predicate(UsePopCountInstruction);
9915 match(Set dst (PopCountL src));
9916
9917 format %{ "POPC $src, $dst" %}
9918 ins_encode %{
9919 __ popc($src$$Register, $dst$$Register);
9920 %}
9921 ins_pipe(ialu_reg);
9922 %}
9923
9924
9925 // ============================================================================
9926 //------------Bytes reverse--------------------------------------------------
9927
9928 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9929 match(Set dst (ReverseBytesI src));
9930
9931 // Op cost is artificially doubled to make sure that load or store
9932 // instructions are preferred over this one which requires a spill
9933 // onto a stack slot.
9934 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9935 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9936
9937 ins_encode %{
9938 __ set($src$$disp + STACK_BIAS, O7);
9939 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9940 %}
9941 ins_pipe( iload_mem );
9942 %}
9943
9944 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9945 match(Set dst (ReverseBytesL src));
9946
9947 // Op cost is artificially doubled to make sure that load or store
9948 // instructions are preferred over this one which requires a spill
9949 // onto a stack slot.
9950 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9951 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9952
9953 ins_encode %{
9954 __ set($src$$disp + STACK_BIAS, O7);
9955 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9956 %}
9957 ins_pipe( iload_mem );
9958 %}
9959
9960 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
9961 match(Set dst (ReverseBytesUS src));
9962
9963 // Op cost is artificially doubled to make sure that load or store
9964 // instructions are preferred over this one which requires a spill
9965 // onto a stack slot.
9966 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9967 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
9968
9969 ins_encode %{
9970 // the value was spilled as an int so bias the load
9971 __ set($src$$disp + STACK_BIAS + 2, O7);
9972 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9973 %}
9974 ins_pipe( iload_mem );
9975 %}
9976
9977 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
9978 match(Set dst (ReverseBytesS src));
9979
9980 // Op cost is artificially doubled to make sure that load or store
9981 // instructions are preferred over this one which requires a spill
9982 // onto a stack slot.
9983 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9984 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
9985
9986 ins_encode %{
9987 // the value was spilled as an int so bias the load
9988 __ set($src$$disp + STACK_BIAS + 2, O7);
9989 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9990 %}
9991 ins_pipe( iload_mem );
9992 %}
9993
9994 // Load Integer reversed byte order
9995 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
9996 match(Set dst (ReverseBytesI (LoadI src)));
9997
9998 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9999 size(4);
10000 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10001
10002 ins_encode %{
10003 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10004 %}
10005 ins_pipe(iload_mem);
10006 %}
10007
10008 // Load Long - aligned and reversed
10009 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10010 match(Set dst (ReverseBytesL (LoadL src)));
10011
10012 ins_cost(MEMORY_REF_COST);
10013 size(4);
10014 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10015
10016 ins_encode %{
10017 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10018 %}
10019 ins_pipe(iload_mem);
10020 %}
10021
10022 // Load unsigned short / char reversed byte order
10023 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10024 match(Set dst (ReverseBytesUS (LoadUS src)));
10025
10026 ins_cost(MEMORY_REF_COST);
10027 size(4);
10028 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10029
10030 ins_encode %{
10031 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10032 %}
10033 ins_pipe(iload_mem);
10034 %}
10035
10036 // Load short reversed byte order
10037 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10038 match(Set dst (ReverseBytesS (LoadS src)));
10039
10040 ins_cost(MEMORY_REF_COST);
10041 size(4);
10042 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10043
10044 ins_encode %{
10045 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10046 %}
10047 ins_pipe(iload_mem);
10048 %}
10049
10050 // Store Integer reversed byte order
10051 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10052 match(Set dst (StoreI dst (ReverseBytesI src)));
10053
10054 ins_cost(MEMORY_REF_COST);
10055 size(4);
10056 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10057
10058 ins_encode %{
10059 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10060 %}
10061 ins_pipe(istore_mem_reg);
10062 %}
10063
10064 // Store Long reversed byte order
10065 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10066 match(Set dst (StoreL dst (ReverseBytesL src)));
10067
10068 ins_cost(MEMORY_REF_COST);
10069 size(4);
10070 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10071
10072 ins_encode %{
10073 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10074 %}
10075 ins_pipe(istore_mem_reg);
10076 %}
10077
10078 // Store unsighed short/char reversed byte order
10079 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10080 match(Set dst (StoreC dst (ReverseBytesUS src)));
10081
10082 ins_cost(MEMORY_REF_COST);
10083 size(4);
10084 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10085
10086 ins_encode %{
10087 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10088 %}
10089 ins_pipe(istore_mem_reg);
10090 %}
10091
10092 // Store short reversed byte order
10093 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10094 match(Set dst (StoreC dst (ReverseBytesS src)));
10095
10096 ins_cost(MEMORY_REF_COST);
10097 size(4);
10098 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10099
10100 ins_encode %{
10101 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10102 %}
10103 ins_pipe(istore_mem_reg);
10104 %}
10105
10106 //----------PEEPHOLE RULES-----------------------------------------------------
10107 // These must follow all instruction definitions as they use the names
10108 // defined in the instructions definitions.
10109 //
10110 // peepmatch ( root_instr_name [preceding_instruction]* );
10111 //
10112 // peepconstraint %{
10113 // (instruction_number.operand_name relational_op instruction_number.operand_name
10114 // [, ...] );
10115 // // instruction numbers are zero-based using left to right order in peepmatch
10116 //
10117 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10118 // // provide an instruction_number.operand_name for each operand that appears
10119 // // in the replacement instruction's match rule
10120 //
10121 // ---------VM FLAGS---------------------------------------------------------
10122 //
10123 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10124 //
10125 // Each peephole rule is given an identifying number starting with zero and
10126 // increasing by one in the order seen by the parser. An individual peephole
10127 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10128 // on the command-line.
10129 //
10130 // ---------CURRENT LIMITATIONS----------------------------------------------
10131 //
10132 // Only match adjacent instructions in same basic block
10133 // Only equality constraints
10134 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10135 // Only one replacement instruction
10136 //
10137 // ---------EXAMPLE----------------------------------------------------------
10138 //
10139 // // pertinent parts of existing instructions in architecture description
10140 // instruct movI(eRegI dst, eRegI src) %{
10141 // match(Set dst (CopyI src));
10142 // %}
10143 //
10144 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10145 // match(Set dst (AddI dst src));
10146 // effect(KILL cr);
10147 // %}
10148 //
10149 // // Change (inc mov) to lea
10150 // peephole %{
10151 // // increment preceeded by register-register move
10152 // peepmatch ( incI_eReg movI );
10153 // // require that the destination register of the increment
10154 // // match the destination register of the move
10155 // peepconstraint ( 0.dst == 1.dst );
10156 // // construct a replacement instruction that sets
10157 // // the destination to ( move's source register + one )
10158 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10159 // %}
10160 //
10161
10162 // // Change load of spilled value to only a spill
10163 // instruct storeI(memory mem, eRegI src) %{
10164 // match(Set mem (StoreI mem src));
10165 // %}
10166 //
10167 // instruct loadI(eRegI dst, memory mem) %{
10168 // match(Set dst (LoadI mem));
10169 // %}
10170 //
10171 // peephole %{
10172 // peepmatch ( loadI storeI );
10173 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10174 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10175 // %}
10176
10177 //----------SMARTSPILL RULES---------------------------------------------------
10178 // These must follow all instruction definitions as they use the names
10179 // defined in the instructions definitions.
10180 //
10181 // SPARC will probably not have any of these rules due to RISC instruction set.
10182
10183 //----------PIPELINE-----------------------------------------------------------
10184 // Rules which define the behavior of the target architectures pipeline.