1 //
2 // Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
135 // Word a in each register holds a Float, words ab hold a Double. We
136 // currently do not use the SIMD capabilities, so registers cd are
137 // unused at the moment.
138 // XMM8-XMM15 must be encoded with REX.
139 // Linux ABI: No register preserved across function calls
140 // XMM0-XMM7 might hold parameters
141 // Windows ABI: XMM6-XMM15 preserved across function calls
142 // XMM0-XMM3 might hold parameters
143
144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
146
147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
149
150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
152
153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
155
156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
158
159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
161
162 #ifdef _WIN64
163
164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
166
167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
169
170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
172
173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
175
176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
178
179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
181
182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
184
185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
187
188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
190
191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
193
194 #else
195
196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
198
199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
201
202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
204
205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
207
208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
210
211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
213
214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
216
217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
219
220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
222
223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
225
226 #endif // _WIN64
227
228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
229
230 // Specify priority of register selection within phases of register
231 // allocation. Highest priority is first. A useful heuristic is to
232 // give registers a low priority when they are required by machine
233 // instructions, like EAX and EDX on I486, and choose no-save registers
234 // before save-on-call, & save-on-call before save-on-entry. Registers
235 // which participate in fixed calling sequences should come last.
236 // Registers which are used as pairs must fall on an even boundary.
237
238 alloc_class chunk0(R10, R10_H,
239 R11, R11_H,
240 R8, R8_H,
241 R9, R9_H,
242 R12, R12_H,
243 RCX, RCX_H,
244 RBX, RBX_H,
245 RDI, RDI_H,
246 RDX, RDX_H,
247 RSI, RSI_H,
248 RAX, RAX_H,
249 RBP, RBP_H,
250 R13, R13_H,
251 R14, R14_H,
252 R15, R15_H,
253 RSP, RSP_H);
254
255 // XXX probably use 8-15 first on Linux
256 alloc_class chunk1(XMM0, XMM0_H,
257 XMM1, XMM1_H,
258 XMM2, XMM2_H,
259 XMM3, XMM3_H,
260 XMM4, XMM4_H,
261 XMM5, XMM5_H,
262 XMM6, XMM6_H,
263 XMM7, XMM7_H,
264 XMM8, XMM8_H,
265 XMM9, XMM9_H,
266 XMM10, XMM10_H,
267 XMM11, XMM11_H,
268 XMM12, XMM12_H,
269 XMM13, XMM13_H,
270 XMM14, XMM14_H,
271 XMM15, XMM15_H);
272
273 alloc_class chunk2(RFLAGS);
274
275
276 //----------Architecture Description Register Classes--------------------------
277 // Several register classes are automatically defined based upon information in
278 // this architecture description.
279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // Class for all pointer registers (including RSP)
286 reg_class any_reg(RAX, RAX_H,
287 RDX, RDX_H,
288 RBP, RBP_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 RBX, RBX_H,
293 RSP, RSP_H,
294 R8, R8_H,
295 R9, R9_H,
296 R10, R10_H,
297 R11, R11_H,
298 R12, R12_H,
299 R13, R13_H,
300 R14, R14_H,
301 R15, R15_H);
302
303 // Class for all pointer registers except RSP
304 reg_class ptr_reg(RAX, RAX_H,
305 RDX, RDX_H,
306 RBP, RBP_H,
307 RDI, RDI_H,
308 RSI, RSI_H,
309 RCX, RCX_H,
310 RBX, RBX_H,
311 R8, R8_H,
312 R9, R9_H,
313 R10, R10_H,
314 R11, R11_H,
315 R13, R13_H,
316 R14, R14_H);
317
318 // Class for all pointer registers except RAX and RSP
319 reg_class ptr_no_rax_reg(RDX, RDX_H,
320 RBP, RBP_H,
321 RDI, RDI_H,
322 RSI, RSI_H,
323 RCX, RCX_H,
324 RBX, RBX_H,
325 R8, R8_H,
326 R9, R9_H,
327 R10, R10_H,
328 R11, R11_H,
329 R13, R13_H,
330 R14, R14_H);
331
332 reg_class ptr_no_rbp_reg(RDX, RDX_H,
333 RAX, RAX_H,
334 RDI, RDI_H,
335 RSI, RSI_H,
336 RCX, RCX_H,
337 RBX, RBX_H,
338 R8, R8_H,
339 R9, R9_H,
340 R10, R10_H,
341 R11, R11_H,
342 R13, R13_H,
343 R14, R14_H);
344
345 // Class for all pointer registers except RAX, RBX and RSP
346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
347 RBP, RBP_H,
348 RDI, RDI_H,
349 RSI, RSI_H,
350 RCX, RCX_H,
351 R8, R8_H,
352 R9, R9_H,
353 R10, R10_H,
354 R11, R11_H,
355 R13, R13_H,
356 R14, R14_H);
357
358 // Singleton class for RAX pointer register
359 reg_class ptr_rax_reg(RAX, RAX_H);
360
361 // Singleton class for RBX pointer register
362 reg_class ptr_rbx_reg(RBX, RBX_H);
363
364 // Singleton class for RSI pointer register
365 reg_class ptr_rsi_reg(RSI, RSI_H);
366
367 // Singleton class for RDI pointer register
368 reg_class ptr_rdi_reg(RDI, RDI_H);
369
370 // Singleton class for RBP pointer register
371 reg_class ptr_rbp_reg(RBP, RBP_H);
372
373 // Singleton class for stack pointer
374 reg_class ptr_rsp_reg(RSP, RSP_H);
375
376 // Singleton class for TLS pointer
377 reg_class ptr_r15_reg(R15, R15_H);
378
379 // Class for all long registers (except RSP)
380 reg_class long_reg(RAX, RAX_H,
381 RDX, RDX_H,
382 RBP, RBP_H,
383 RDI, RDI_H,
384 RSI, RSI_H,
385 RCX, RCX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers except RAX, RDX (and RSP)
395 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
396 RDI, RDI_H,
397 RSI, RSI_H,
398 RCX, RCX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Class for all long registers except RCX (and RSP)
408 reg_class long_no_rcx_reg(RBP, RBP_H,
409 RDI, RDI_H,
410 RSI, RSI_H,
411 RAX, RAX_H,
412 RDX, RDX_H,
413 RBX, RBX_H,
414 R8, R8_H,
415 R9, R9_H,
416 R10, R10_H,
417 R11, R11_H,
418 R13, R13_H,
419 R14, R14_H);
420
421 // Class for all long registers except RAX (and RSP)
422 reg_class long_no_rax_reg(RBP, RBP_H,
423 RDX, RDX_H,
424 RDI, RDI_H,
425 RSI, RSI_H,
426 RCX, RCX_H,
427 RBX, RBX_H,
428 R8, R8_H,
429 R9, R9_H,
430 R10, R10_H,
431 R11, R11_H,
432 R13, R13_H,
433 R14, R14_H);
434
435 // Singleton class for RAX long register
436 reg_class long_rax_reg(RAX, RAX_H);
437
438 // Singleton class for RCX long register
439 reg_class long_rcx_reg(RCX, RCX_H);
440
441 // Singleton class for RDX long register
442 reg_class long_rdx_reg(RDX, RDX_H);
443
444 // Class for all int registers (except RSP)
445 reg_class int_reg(RAX,
446 RDX,
447 RBP,
448 RDI,
449 RSI,
450 RCX,
451 RBX,
452 R8,
453 R9,
454 R10,
455 R11,
456 R13,
457 R14);
458
459 // Class for all int registers except RCX (and RSP)
460 reg_class int_no_rcx_reg(RAX,
461 RDX,
462 RBP,
463 RDI,
464 RSI,
465 RBX,
466 R8,
467 R9,
468 R10,
469 R11,
470 R13,
471 R14);
472
473 // Class for all int registers except RAX, RDX (and RSP)
474 reg_class int_no_rax_rdx_reg(RBP,
475 RDI,
476 RSI,
477 RCX,
478 RBX,
479 R8,
480 R9,
481 R10,
482 R11,
483 R13,
484 R14);
485
486 // Singleton class for RAX int register
487 reg_class int_rax_reg(RAX);
488
489 // Singleton class for RBX int register
490 reg_class int_rbx_reg(RBX);
491
492 // Singleton class for RCX int register
493 reg_class int_rcx_reg(RCX);
494
495 // Singleton class for RCX int register
496 reg_class int_rdx_reg(RDX);
497
498 // Singleton class for RCX int register
499 reg_class int_rdi_reg(RDI);
500
501 // Singleton class for instruction pointer
502 // reg_class ip_reg(RIP);
503
504 // Singleton class for condition codes
505 reg_class int_flags(RFLAGS);
506
507 // Class for all float registers
508 reg_class float_reg(XMM0,
509 XMM1,
510 XMM2,
511 XMM3,
512 XMM4,
513 XMM5,
514 XMM6,
515 XMM7,
516 XMM8,
517 XMM9,
518 XMM10,
519 XMM11,
520 XMM12,
521 XMM13,
522 XMM14,
523 XMM15);
524
525 // Class for all double registers
526 reg_class double_reg(XMM0, XMM0_H,
527 XMM1, XMM1_H,
528 XMM2, XMM2_H,
529 XMM3, XMM3_H,
530 XMM4, XMM4_H,
531 XMM5, XMM5_H,
532 XMM6, XMM6_H,
533 XMM7, XMM7_H,
534 XMM8, XMM8_H,
535 XMM9, XMM9_H,
536 XMM10, XMM10_H,
537 XMM11, XMM11_H,
538 XMM12, XMM12_H,
539 XMM13, XMM13_H,
540 XMM14, XMM14_H,
541 XMM15, XMM15_H);
542 %}
543
544
545 //----------SOURCE BLOCK-------------------------------------------------------
546 // This is a block of C++ code which provides values, functions, and
547 // definitions necessary in the rest of the architecture description
548 source %{
549 #define RELOC_IMM64 Assembler::imm_operand
550 #define RELOC_DISP32 Assembler::disp32_operand
551
552 #define __ _masm.
553
554 static int preserve_SP_size() {
555 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
556 }
557
558 // !!!!! Special hack to get all types of calls to specify the byte offset
559 // from the start of the call to the point where the return address
560 // will point.
561 int MachCallStaticJavaNode::ret_addr_offset()
562 {
563 int offset = 5; // 5 bytes from start of call to where return address points
564 if (_method_handle_invoke)
565 offset += preserve_SP_size();
566 return offset;
567 }
568
569 int MachCallDynamicJavaNode::ret_addr_offset()
570 {
571 return 15; // 15 bytes from start of call to where return address points
572 }
573
574 // In os_cpu .ad file
575 // int MachCallRuntimeNode::ret_addr_offset()
576
577 // Indicate if the safepoint node needs the polling page as an input,
578 // it does if the polling page is more than disp32 away.
579 bool SafePointNode::needs_polling_address_input()
580 {
581 return Assembler::is_polling_page_far();
582 }
583
584 //
585 // Compute padding required for nodes which need alignment
586 //
587
588 // The address of the call instruction needs to be 4-byte aligned to
589 // ensure that it does not span a cache line so that it can be patched.
590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
591 {
592 current_offset += 1; // skip call opcode byte
593 return round_to(current_offset, alignment_required()) - current_offset;
594 }
595
596 // The address of the call instruction needs to be 4-byte aligned to
597 // ensure that it does not span a cache line so that it can be patched.
598 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
599 {
600 current_offset += preserve_SP_size(); // skip mov rbp, rsp
601 current_offset += 1; // skip call opcode byte
602 return round_to(current_offset, alignment_required()) - current_offset;
603 }
604
605 // The address of the call instruction needs to be 4-byte aligned to
606 // ensure that it does not span a cache line so that it can be patched.
607 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
608 {
609 current_offset += 11; // skip movq instruction + call opcode byte
610 return round_to(current_offset, alignment_required()) - current_offset;
611 }
612
613 #ifndef PRODUCT
614 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
615 {
616 st->print("INT3");
617 }
618 #endif
619
620 // EMIT_RM()
621 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
622 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
623 cbuf.insts()->emit_int8(c);
624 }
625
626 // EMIT_CC()
627 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
628 unsigned char c = (unsigned char) (f1 | f2);
629 cbuf.insts()->emit_int8(c);
630 }
631
632 // EMIT_OPCODE()
633 void emit_opcode(CodeBuffer &cbuf, int code) {
634 cbuf.insts()->emit_int8((unsigned char) code);
635 }
636
637 // EMIT_OPCODE() w/ relocation information
638 void emit_opcode(CodeBuffer &cbuf,
639 int code, relocInfo::relocType reloc, int offset, int format)
640 {
641 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
642 emit_opcode(cbuf, code);
643 }
644
645 // EMIT_D8()
646 void emit_d8(CodeBuffer &cbuf, int d8) {
647 cbuf.insts()->emit_int8((unsigned char) d8);
648 }
649
650 // EMIT_D16()
651 void emit_d16(CodeBuffer &cbuf, int d16) {
652 cbuf.insts()->emit_int16(d16);
653 }
654
655 // EMIT_D32()
656 void emit_d32(CodeBuffer &cbuf, int d32) {
657 cbuf.insts()->emit_int32(d32);
658 }
659
660 // EMIT_D64()
661 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
662 cbuf.insts()->emit_int64(d64);
663 }
664
665 // emit 32 bit value and construct relocation entry from relocInfo::relocType
666 void emit_d32_reloc(CodeBuffer& cbuf,
667 int d32,
668 relocInfo::relocType reloc,
669 int format)
670 {
671 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
672 cbuf.relocate(cbuf.insts_mark(), reloc, format);
673 cbuf.insts()->emit_int32(d32);
674 }
675
676 // emit 32 bit value and construct relocation entry from RelocationHolder
677 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
678 #ifdef ASSERT
679 if (rspec.reloc()->type() == relocInfo::oop_type &&
680 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
681 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
682 }
683 #endif
684 cbuf.relocate(cbuf.insts_mark(), rspec, format);
685 cbuf.insts()->emit_int32(d32);
686 }
687
688 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
689 address next_ip = cbuf.insts_end() + 4;
690 emit_d32_reloc(cbuf, (int) (addr - next_ip),
691 external_word_Relocation::spec(addr),
692 RELOC_DISP32);
693 }
694
695
696 // emit 64 bit value and construct relocation entry from relocInfo::relocType
697 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
698 cbuf.relocate(cbuf.insts_mark(), reloc, format);
699 cbuf.insts()->emit_int64(d64);
700 }
701
702 // emit 64 bit value and construct relocation entry from RelocationHolder
703 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
704 #ifdef ASSERT
705 if (rspec.reloc()->type() == relocInfo::oop_type &&
706 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
707 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
708 "cannot embed scavengable oops in code");
709 }
710 #endif
711 cbuf.relocate(cbuf.insts_mark(), rspec, format);
712 cbuf.insts()->emit_int64(d64);
713 }
714
715 // Access stack slot for load or store
716 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
717 {
718 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
719 if (-0x80 <= disp && disp < 0x80) {
720 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
721 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
722 emit_d8(cbuf, disp); // Displacement // R/M byte
723 } else {
724 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
725 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
726 emit_d32(cbuf, disp); // Displacement // R/M byte
727 }
728 }
729
730 // rRegI ereg, memory mem) %{ // emit_reg_mem
731 void encode_RegMem(CodeBuffer &cbuf,
732 int reg,
733 int base, int index, int scale, int disp, bool disp_is_oop)
734 {
735 assert(!disp_is_oop, "cannot have disp");
736 int regenc = reg & 7;
737 int baseenc = base & 7;
738 int indexenc = index & 7;
739
740 // There is no index & no scale, use form without SIB byte
741 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
742 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
743 if (disp == 0 && base != RBP_enc && base != R13_enc) {
744 emit_rm(cbuf, 0x0, regenc, baseenc); // *
745 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
746 // If 8-bit displacement, mode 0x1
747 emit_rm(cbuf, 0x1, regenc, baseenc); // *
748 emit_d8(cbuf, disp);
749 } else {
750 // If 32-bit displacement
751 if (base == -1) { // Special flag for absolute address
752 emit_rm(cbuf, 0x0, regenc, 0x5); // *
753 if (disp_is_oop) {
754 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
755 } else {
756 emit_d32(cbuf, disp);
757 }
758 } else {
759 // Normal base + offset
760 emit_rm(cbuf, 0x2, regenc, baseenc); // *
761 if (disp_is_oop) {
762 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
763 } else {
764 emit_d32(cbuf, disp);
765 }
766 }
767 }
768 } else {
769 // Else, encode with the SIB byte
770 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
771 if (disp == 0 && base != RBP_enc && base != R13_enc) {
772 // If no displacement
773 emit_rm(cbuf, 0x0, regenc, 0x4); // *
774 emit_rm(cbuf, scale, indexenc, baseenc);
775 } else {
776 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
777 // If 8-bit displacement, mode 0x1
778 emit_rm(cbuf, 0x1, regenc, 0x4); // *
779 emit_rm(cbuf, scale, indexenc, baseenc);
780 emit_d8(cbuf, disp);
781 } else {
782 // If 32-bit displacement
783 if (base == 0x04 ) {
784 emit_rm(cbuf, 0x2, regenc, 0x4);
785 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
786 } else {
787 emit_rm(cbuf, 0x2, regenc, 0x4);
788 emit_rm(cbuf, scale, indexenc, baseenc); // *
789 }
790 if (disp_is_oop) {
791 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
792 } else {
793 emit_d32(cbuf, disp);
794 }
795 }
796 }
797 }
798 }
799
800 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
801 {
802 if (dstenc != srcenc) {
803 if (dstenc < 8) {
804 if (srcenc >= 8) {
805 emit_opcode(cbuf, Assembler::REX_B);
806 srcenc -= 8;
807 }
808 } else {
809 if (srcenc < 8) {
810 emit_opcode(cbuf, Assembler::REX_R);
811 } else {
812 emit_opcode(cbuf, Assembler::REX_RB);
813 srcenc -= 8;
814 }
815 dstenc -= 8;
816 }
817
818 emit_opcode(cbuf, 0x8B);
819 emit_rm(cbuf, 0x3, dstenc, srcenc);
820 }
821 }
822
823 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
824 if( dst_encoding == src_encoding ) {
825 // reg-reg copy, use an empty encoding
826 } else {
827 MacroAssembler _masm(&cbuf);
828
829 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
830 }
831 }
832
833 // This could be in MacroAssembler but it's fairly C2 specific
834 void emit_cmpfp_fixup(MacroAssembler& _masm) {
835 Label exit;
836 __ jccb(Assembler::noParity, exit);
837 __ pushf();
838 __ andq(Address(rsp, 0), 0xffffff2b);
839 __ popf();
840 __ bind(exit);
841 __ nop(); // (target for branch to avoid branch to branch)
842 }
843
844
845 //=============================================================================
846 const bool Matcher::constant_table_absolute_addressing = true;
847 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
848
849 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
850 // Empty encoding
851 }
852
853 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
854 return 0;
855 }
856
857 #ifndef PRODUCT
858 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
859 st->print("# MachConstantBaseNode (empty encoding)");
860 }
861 #endif
862
863
864 //=============================================================================
865 #ifndef PRODUCT
866 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
867 {
868 Compile* C = ra_->C;
869
870 int framesize = C->frame_slots() << LogBytesPerInt;
871 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
872 // Remove wordSize for return adr already pushed
873 // and another for the RBP we are going to save
874 framesize -= 2*wordSize;
875 bool need_nop = true;
876
877 // Calls to C2R adapters often do not accept exceptional returns.
878 // We require that their callers must bang for them. But be
879 // careful, because some VM calls (such as call site linkage) can
880 // use several kilobytes of stack. But the stack safety zone should
881 // account for that. See bugs 4446381, 4468289, 4497237.
882 if (C->need_stack_bang(framesize)) {
883 st->print_cr("# stack bang"); st->print("\t");
884 need_nop = false;
885 }
886 st->print_cr("pushq rbp"); st->print("\t");
887
888 if (VerifyStackAtCalls) {
889 // Majik cookie to verify stack depth
890 st->print_cr("pushq 0xffffffffbadb100d"
891 "\t# Majik cookie for stack depth check");
892 st->print("\t");
893 framesize -= wordSize; // Remove 2 for cookie
894 need_nop = false;
895 }
896
897 if (framesize) {
898 st->print("subq rsp, #%d\t# Create frame", framesize);
899 if (framesize < 0x80 && need_nop) {
900 st->print("\n\tnop\t# nop for patch_verified_entry");
901 }
902 }
903 }
904 #endif
905
906 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
907 {
908 Compile* C = ra_->C;
909
910 // WARNING: Initial instruction MUST be 5 bytes or longer so that
911 // NativeJump::patch_verified_entry will be able to patch out the entry
912 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
913 // depth is ok at 5 bytes, the frame allocation can be either 3 or
914 // 6 bytes. So if we don't do the fldcw or the push then we must
915 // use the 6 byte frame allocation even if we have no frame. :-(
916 // If method sets FPU control word do it now
917
918 int framesize = C->frame_slots() << LogBytesPerInt;
919 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
920 // Remove wordSize for return adr already pushed
921 // and another for the RBP we are going to save
922 framesize -= 2*wordSize;
923 bool need_nop = true;
924
925 // Calls to C2R adapters often do not accept exceptional returns.
926 // We require that their callers must bang for them. But be
927 // careful, because some VM calls (such as call site linkage) can
928 // use several kilobytes of stack. But the stack safety zone should
929 // account for that. See bugs 4446381, 4468289, 4497237.
930 if (C->need_stack_bang(framesize)) {
931 MacroAssembler masm(&cbuf);
932 masm.generate_stack_overflow_check(framesize);
933 need_nop = false;
934 }
935
936 // We always push rbp so that on return to interpreter rbp will be
937 // restored correctly and we can correct the stack.
938 emit_opcode(cbuf, 0x50 | RBP_enc);
939
940 if (VerifyStackAtCalls) {
941 // Majik cookie to verify stack depth
942 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
943 emit_d32(cbuf, 0xbadb100d);
944 framesize -= wordSize; // Remove 2 for cookie
945 need_nop = false;
946 }
947
948 if (framesize) {
949 emit_opcode(cbuf, Assembler::REX_W);
950 if (framesize < 0x80) {
951 emit_opcode(cbuf, 0x83); // sub SP,#framesize
952 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
953 emit_d8(cbuf, framesize);
954 if (need_nop) {
955 emit_opcode(cbuf, 0x90); // nop
956 }
957 } else {
958 emit_opcode(cbuf, 0x81); // sub SP,#framesize
959 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
960 emit_d32(cbuf, framesize);
961 }
962 }
963
964 C->set_frame_complete(cbuf.insts_size());
965
966 #ifdef ASSERT
967 if (VerifyStackAtCalls) {
968 Label L;
969 MacroAssembler masm(&cbuf);
970 masm.push(rax);
971 masm.mov(rax, rsp);
972 masm.andptr(rax, StackAlignmentInBytes-1);
973 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
974 masm.pop(rax);
975 masm.jcc(Assembler::equal, L);
976 masm.stop("Stack is not properly aligned!");
977 masm.bind(L);
978 }
979 #endif
980 }
981
982 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
983 {
984 return MachNode::size(ra_); // too many variables; just compute it
985 // the hard way
986 }
987
988 int MachPrologNode::reloc() const
989 {
990 return 0; // a large enough number
991 }
992
993 //=============================================================================
994 #ifndef PRODUCT
995 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
996 {
997 Compile* C = ra_->C;
998 int framesize = C->frame_slots() << LogBytesPerInt;
999 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1000 // Remove word for return adr already pushed
1001 // and RBP
1002 framesize -= 2*wordSize;
1003
1004 if (framesize) {
1005 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
1006 st->print("\t");
1007 }
1008
1009 st->print_cr("popq rbp");
1010 if (do_polling() && C->is_method_compilation()) {
1011 st->print("\t");
1012 if (Assembler::is_polling_page_far()) {
1013 st->print_cr("movq rscratch1, #polling_page_address\n\t"
1014 "testl rax, [rscratch1]\t"
1015 "# Safepoint: poll for GC");
1016 } else {
1017 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
1018 "# Safepoint: poll for GC");
1019 }
1020 }
1021 }
1022 #endif
1023
1024 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1025 {
1026 Compile* C = ra_->C;
1027 int framesize = C->frame_slots() << LogBytesPerInt;
1028 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1029 // Remove word for return adr already pushed
1030 // and RBP
1031 framesize -= 2*wordSize;
1032
1033 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
1034
1035 if (framesize) {
1036 emit_opcode(cbuf, Assembler::REX_W);
1037 if (framesize < 0x80) {
1038 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
1039 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1040 emit_d8(cbuf, framesize);
1041 } else {
1042 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1043 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1044 emit_d32(cbuf, framesize);
1045 }
1046 }
1047
1048 // popq rbp
1049 emit_opcode(cbuf, 0x58 | RBP_enc);
1050
1051 if (do_polling() && C->is_method_compilation()) {
1052 MacroAssembler _masm(&cbuf);
1053 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1054 if (Assembler::is_polling_page_far()) {
1055 __ lea(rscratch1, polling_page);
1056 __ relocate(relocInfo::poll_return_type);
1057 __ testl(rax, Address(rscratch1, 0));
1058 } else {
1059 __ testl(rax, polling_page);
1060 }
1061 }
1062 }
1063
1064 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1065 {
1066 return MachNode::size(ra_); // too many variables; just compute it
1067 // the hard way
1068 }
1069
1070 int MachEpilogNode::reloc() const
1071 {
1072 return 2; // a large enough number
1073 }
1074
1075 const Pipeline* MachEpilogNode::pipeline() const
1076 {
1077 return MachNode::pipeline_class();
1078 }
1079
1080 int MachEpilogNode::safepoint_offset() const
1081 {
1082 return 0;
1083 }
1084
1085 //=============================================================================
1086
1087 enum RC {
1088 rc_bad,
1089 rc_int,
1090 rc_float,
1091 rc_stack
1092 };
1093
1094 static enum RC rc_class(OptoReg::Name reg)
1095 {
1096 if( !OptoReg::is_valid(reg) ) return rc_bad;
1097
1098 if (OptoReg::is_stack(reg)) return rc_stack;
1099
1100 VMReg r = OptoReg::as_VMReg(reg);
1101
1102 if (r->is_Register()) return rc_int;
1103
1104 assert(r->is_XMMRegister(), "must be");
1105 return rc_float;
1106 }
1107
1108 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1109 PhaseRegAlloc* ra_,
1110 bool do_size,
1111 outputStream* st) const
1112 {
1113
1114 // Get registers to move
1115 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1116 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1117 OptoReg::Name dst_second = ra_->get_reg_second(this);
1118 OptoReg::Name dst_first = ra_->get_reg_first(this);
1119
1120 enum RC src_second_rc = rc_class(src_second);
1121 enum RC src_first_rc = rc_class(src_first);
1122 enum RC dst_second_rc = rc_class(dst_second);
1123 enum RC dst_first_rc = rc_class(dst_first);
1124
1125 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1126 "must move at least 1 register" );
1127
1128 if (src_first == dst_first && src_second == dst_second) {
1129 // Self copy, no move
1130 return 0;
1131 } else if (src_first_rc == rc_stack) {
1132 // mem ->
1133 if (dst_first_rc == rc_stack) {
1134 // mem -> mem
1135 assert(src_second != dst_first, "overlap");
1136 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1137 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1138 // 64-bit
1139 int src_offset = ra_->reg2offset(src_first);
1140 int dst_offset = ra_->reg2offset(dst_first);
1141 if (cbuf) {
1142 emit_opcode(*cbuf, 0xFF);
1143 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
1144
1145 emit_opcode(*cbuf, 0x8F);
1146 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
1147
1148 #ifndef PRODUCT
1149 } else if (!do_size) {
1150 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1151 "popq [rsp + #%d]",
1152 src_offset,
1153 dst_offset);
1154 #endif
1155 }
1156 return
1157 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
1158 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
1159 } else {
1160 // 32-bit
1161 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1162 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1163 // No pushl/popl, so:
1164 int src_offset = ra_->reg2offset(src_first);
1165 int dst_offset = ra_->reg2offset(dst_first);
1166 if (cbuf) {
1167 emit_opcode(*cbuf, Assembler::REX_W);
1168 emit_opcode(*cbuf, 0x89);
1169 emit_opcode(*cbuf, 0x44);
1170 emit_opcode(*cbuf, 0x24);
1171 emit_opcode(*cbuf, 0xF8);
1172
1173 emit_opcode(*cbuf, 0x8B);
1174 encode_RegMem(*cbuf,
1175 RAX_enc,
1176 RSP_enc, 0x4, 0, src_offset,
1177 false);
1178
1179 emit_opcode(*cbuf, 0x89);
1180 encode_RegMem(*cbuf,
1181 RAX_enc,
1182 RSP_enc, 0x4, 0, dst_offset,
1183 false);
1184
1185 emit_opcode(*cbuf, Assembler::REX_W);
1186 emit_opcode(*cbuf, 0x8B);
1187 emit_opcode(*cbuf, 0x44);
1188 emit_opcode(*cbuf, 0x24);
1189 emit_opcode(*cbuf, 0xF8);
1190
1191 #ifndef PRODUCT
1192 } else if (!do_size) {
1193 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1194 "movl rax, [rsp + #%d]\n\t"
1195 "movl [rsp + #%d], rax\n\t"
1196 "movq rax, [rsp - #8]",
1197 src_offset,
1198 dst_offset);
1199 #endif
1200 }
1201 return
1202 5 + // movq
1203 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
1204 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
1205 5; // movq
1206 }
1207 } else if (dst_first_rc == rc_int) {
1208 // mem -> gpr
1209 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1210 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1211 // 64-bit
1212 int offset = ra_->reg2offset(src_first);
1213 if (cbuf) {
1214 if (Matcher::_regEncode[dst_first] < 8) {
1215 emit_opcode(*cbuf, Assembler::REX_W);
1216 } else {
1217 emit_opcode(*cbuf, Assembler::REX_WR);
1218 }
1219 emit_opcode(*cbuf, 0x8B);
1220 encode_RegMem(*cbuf,
1221 Matcher::_regEncode[dst_first],
1222 RSP_enc, 0x4, 0, offset,
1223 false);
1224 #ifndef PRODUCT
1225 } else if (!do_size) {
1226 st->print("movq %s, [rsp + #%d]\t# spill",
1227 Matcher::regName[dst_first],
1228 offset);
1229 #endif
1230 }
1231 return
1232 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1233 } else {
1234 // 32-bit
1235 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1236 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1237 int offset = ra_->reg2offset(src_first);
1238 if (cbuf) {
1239 if (Matcher::_regEncode[dst_first] >= 8) {
1240 emit_opcode(*cbuf, Assembler::REX_R);
1241 }
1242 emit_opcode(*cbuf, 0x8B);
1243 encode_RegMem(*cbuf,
1244 Matcher::_regEncode[dst_first],
1245 RSP_enc, 0x4, 0, offset,
1246 false);
1247 #ifndef PRODUCT
1248 } else if (!do_size) {
1249 st->print("movl %s, [rsp + #%d]\t# spill",
1250 Matcher::regName[dst_first],
1251 offset);
1252 #endif
1253 }
1254 return
1255 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1256 ((Matcher::_regEncode[dst_first] < 8)
1257 ? 3
1258 : 4); // REX
1259 }
1260 } else if (dst_first_rc == rc_float) {
1261 // mem-> xmm
1262 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1263 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1264 // 64-bit
1265 int offset = ra_->reg2offset(src_first);
1266 if (cbuf) {
1267 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1268 if (Matcher::_regEncode[dst_first] >= 8) {
1269 emit_opcode(*cbuf, Assembler::REX_R);
1270 }
1271 emit_opcode(*cbuf, 0x0F);
1272 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1273 encode_RegMem(*cbuf,
1274 Matcher::_regEncode[dst_first],
1275 RSP_enc, 0x4, 0, offset,
1276 false);
1277 #ifndef PRODUCT
1278 } else if (!do_size) {
1279 st->print("%s %s, [rsp + #%d]\t# spill",
1280 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1281 Matcher::regName[dst_first],
1282 offset);
1283 #endif
1284 }
1285 return
1286 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1287 ((Matcher::_regEncode[dst_first] < 8)
1288 ? 5
1289 : 6); // REX
1290 } else {
1291 // 32-bit
1292 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1293 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1294 int offset = ra_->reg2offset(src_first);
1295 if (cbuf) {
1296 emit_opcode(*cbuf, 0xF3);
1297 if (Matcher::_regEncode[dst_first] >= 8) {
1298 emit_opcode(*cbuf, Assembler::REX_R);
1299 }
1300 emit_opcode(*cbuf, 0x0F);
1301 emit_opcode(*cbuf, 0x10);
1302 encode_RegMem(*cbuf,
1303 Matcher::_regEncode[dst_first],
1304 RSP_enc, 0x4, 0, offset,
1305 false);
1306 #ifndef PRODUCT
1307 } else if (!do_size) {
1308 st->print("movss %s, [rsp + #%d]\t# spill",
1309 Matcher::regName[dst_first],
1310 offset);
1311 #endif
1312 }
1313 return
1314 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1315 ((Matcher::_regEncode[dst_first] < 8)
1316 ? 5
1317 : 6); // REX
1318 }
1319 }
1320 } else if (src_first_rc == rc_int) {
1321 // gpr ->
1322 if (dst_first_rc == rc_stack) {
1323 // gpr -> mem
1324 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1325 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1326 // 64-bit
1327 int offset = ra_->reg2offset(dst_first);
1328 if (cbuf) {
1329 if (Matcher::_regEncode[src_first] < 8) {
1330 emit_opcode(*cbuf, Assembler::REX_W);
1331 } else {
1332 emit_opcode(*cbuf, Assembler::REX_WR);
1333 }
1334 emit_opcode(*cbuf, 0x89);
1335 encode_RegMem(*cbuf,
1336 Matcher::_regEncode[src_first],
1337 RSP_enc, 0x4, 0, offset,
1338 false);
1339 #ifndef PRODUCT
1340 } else if (!do_size) {
1341 st->print("movq [rsp + #%d], %s\t# spill",
1342 offset,
1343 Matcher::regName[src_first]);
1344 #endif
1345 }
1346 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1347 } else {
1348 // 32-bit
1349 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1350 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1351 int offset = ra_->reg2offset(dst_first);
1352 if (cbuf) {
1353 if (Matcher::_regEncode[src_first] >= 8) {
1354 emit_opcode(*cbuf, Assembler::REX_R);
1355 }
1356 emit_opcode(*cbuf, 0x89);
1357 encode_RegMem(*cbuf,
1358 Matcher::_regEncode[src_first],
1359 RSP_enc, 0x4, 0, offset,
1360 false);
1361 #ifndef PRODUCT
1362 } else if (!do_size) {
1363 st->print("movl [rsp + #%d], %s\t# spill",
1364 offset,
1365 Matcher::regName[src_first]);
1366 #endif
1367 }
1368 return
1369 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1370 ((Matcher::_regEncode[src_first] < 8)
1371 ? 3
1372 : 4); // REX
1373 }
1374 } else if (dst_first_rc == rc_int) {
1375 // gpr -> gpr
1376 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1377 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1378 // 64-bit
1379 if (cbuf) {
1380 if (Matcher::_regEncode[dst_first] < 8) {
1381 if (Matcher::_regEncode[src_first] < 8) {
1382 emit_opcode(*cbuf, Assembler::REX_W);
1383 } else {
1384 emit_opcode(*cbuf, Assembler::REX_WB);
1385 }
1386 } else {
1387 if (Matcher::_regEncode[src_first] < 8) {
1388 emit_opcode(*cbuf, Assembler::REX_WR);
1389 } else {
1390 emit_opcode(*cbuf, Assembler::REX_WRB);
1391 }
1392 }
1393 emit_opcode(*cbuf, 0x8B);
1394 emit_rm(*cbuf, 0x3,
1395 Matcher::_regEncode[dst_first] & 7,
1396 Matcher::_regEncode[src_first] & 7);
1397 #ifndef PRODUCT
1398 } else if (!do_size) {
1399 st->print("movq %s, %s\t# spill",
1400 Matcher::regName[dst_first],
1401 Matcher::regName[src_first]);
1402 #endif
1403 }
1404 return 3; // REX
1405 } else {
1406 // 32-bit
1407 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1408 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1409 if (cbuf) {
1410 if (Matcher::_regEncode[dst_first] < 8) {
1411 if (Matcher::_regEncode[src_first] >= 8) {
1412 emit_opcode(*cbuf, Assembler::REX_B);
1413 }
1414 } else {
1415 if (Matcher::_regEncode[src_first] < 8) {
1416 emit_opcode(*cbuf, Assembler::REX_R);
1417 } else {
1418 emit_opcode(*cbuf, Assembler::REX_RB);
1419 }
1420 }
1421 emit_opcode(*cbuf, 0x8B);
1422 emit_rm(*cbuf, 0x3,
1423 Matcher::_regEncode[dst_first] & 7,
1424 Matcher::_regEncode[src_first] & 7);
1425 #ifndef PRODUCT
1426 } else if (!do_size) {
1427 st->print("movl %s, %s\t# spill",
1428 Matcher::regName[dst_first],
1429 Matcher::regName[src_first]);
1430 #endif
1431 }
1432 return
1433 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1434 ? 2
1435 : 3; // REX
1436 }
1437 } else if (dst_first_rc == rc_float) {
1438 // gpr -> xmm
1439 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1440 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1441 // 64-bit
1442 if (cbuf) {
1443 emit_opcode(*cbuf, 0x66);
1444 if (Matcher::_regEncode[dst_first] < 8) {
1445 if (Matcher::_regEncode[src_first] < 8) {
1446 emit_opcode(*cbuf, Assembler::REX_W);
1447 } else {
1448 emit_opcode(*cbuf, Assembler::REX_WB);
1449 }
1450 } else {
1451 if (Matcher::_regEncode[src_first] < 8) {
1452 emit_opcode(*cbuf, Assembler::REX_WR);
1453 } else {
1454 emit_opcode(*cbuf, Assembler::REX_WRB);
1455 }
1456 }
1457 emit_opcode(*cbuf, 0x0F);
1458 emit_opcode(*cbuf, 0x6E);
1459 emit_rm(*cbuf, 0x3,
1460 Matcher::_regEncode[dst_first] & 7,
1461 Matcher::_regEncode[src_first] & 7);
1462 #ifndef PRODUCT
1463 } else if (!do_size) {
1464 st->print("movdq %s, %s\t# spill",
1465 Matcher::regName[dst_first],
1466 Matcher::regName[src_first]);
1467 #endif
1468 }
1469 return 5; // REX
1470 } else {
1471 // 32-bit
1472 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1473 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1474 if (cbuf) {
1475 emit_opcode(*cbuf, 0x66);
1476 if (Matcher::_regEncode[dst_first] < 8) {
1477 if (Matcher::_regEncode[src_first] >= 8) {
1478 emit_opcode(*cbuf, Assembler::REX_B);
1479 }
1480 } else {
1481 if (Matcher::_regEncode[src_first] < 8) {
1482 emit_opcode(*cbuf, Assembler::REX_R);
1483 } else {
1484 emit_opcode(*cbuf, Assembler::REX_RB);
1485 }
1486 }
1487 emit_opcode(*cbuf, 0x0F);
1488 emit_opcode(*cbuf, 0x6E);
1489 emit_rm(*cbuf, 0x3,
1490 Matcher::_regEncode[dst_first] & 7,
1491 Matcher::_regEncode[src_first] & 7);
1492 #ifndef PRODUCT
1493 } else if (!do_size) {
1494 st->print("movdl %s, %s\t# spill",
1495 Matcher::regName[dst_first],
1496 Matcher::regName[src_first]);
1497 #endif
1498 }
1499 return
1500 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1501 ? 4
1502 : 5; // REX
1503 }
1504 }
1505 } else if (src_first_rc == rc_float) {
1506 // xmm ->
1507 if (dst_first_rc == rc_stack) {
1508 // xmm -> mem
1509 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1510 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1511 // 64-bit
1512 int offset = ra_->reg2offset(dst_first);
1513 if (cbuf) {
1514 emit_opcode(*cbuf, 0xF2);
1515 if (Matcher::_regEncode[src_first] >= 8) {
1516 emit_opcode(*cbuf, Assembler::REX_R);
1517 }
1518 emit_opcode(*cbuf, 0x0F);
1519 emit_opcode(*cbuf, 0x11);
1520 encode_RegMem(*cbuf,
1521 Matcher::_regEncode[src_first],
1522 RSP_enc, 0x4, 0, offset,
1523 false);
1524 #ifndef PRODUCT
1525 } else if (!do_size) {
1526 st->print("movsd [rsp + #%d], %s\t# spill",
1527 offset,
1528 Matcher::regName[src_first]);
1529 #endif
1530 }
1531 return
1532 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1533 ((Matcher::_regEncode[src_first] < 8)
1534 ? 5
1535 : 6); // REX
1536 } else {
1537 // 32-bit
1538 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1539 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1540 int offset = ra_->reg2offset(dst_first);
1541 if (cbuf) {
1542 emit_opcode(*cbuf, 0xF3);
1543 if (Matcher::_regEncode[src_first] >= 8) {
1544 emit_opcode(*cbuf, Assembler::REX_R);
1545 }
1546 emit_opcode(*cbuf, 0x0F);
1547 emit_opcode(*cbuf, 0x11);
1548 encode_RegMem(*cbuf,
1549 Matcher::_regEncode[src_first],
1550 RSP_enc, 0x4, 0, offset,
1551 false);
1552 #ifndef PRODUCT
1553 } else if (!do_size) {
1554 st->print("movss [rsp + #%d], %s\t# spill",
1555 offset,
1556 Matcher::regName[src_first]);
1557 #endif
1558 }
1559 return
1560 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1561 ((Matcher::_regEncode[src_first] < 8)
1562 ? 5
1563 : 6); // REX
1564 }
1565 } else if (dst_first_rc == rc_int) {
1566 // xmm -> gpr
1567 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1568 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1569 // 64-bit
1570 if (cbuf) {
1571 emit_opcode(*cbuf, 0x66);
1572 if (Matcher::_regEncode[dst_first] < 8) {
1573 if (Matcher::_regEncode[src_first] < 8) {
1574 emit_opcode(*cbuf, Assembler::REX_W);
1575 } else {
1576 emit_opcode(*cbuf, Assembler::REX_WR); // attention!
1577 }
1578 } else {
1579 if (Matcher::_regEncode[src_first] < 8) {
1580 emit_opcode(*cbuf, Assembler::REX_WB); // attention!
1581 } else {
1582 emit_opcode(*cbuf, Assembler::REX_WRB);
1583 }
1584 }
1585 emit_opcode(*cbuf, 0x0F);
1586 emit_opcode(*cbuf, 0x7E);
1587 emit_rm(*cbuf, 0x3,
1588 Matcher::_regEncode[src_first] & 7,
1589 Matcher::_regEncode[dst_first] & 7);
1590 #ifndef PRODUCT
1591 } else if (!do_size) {
1592 st->print("movdq %s, %s\t# spill",
1593 Matcher::regName[dst_first],
1594 Matcher::regName[src_first]);
1595 #endif
1596 }
1597 return 5; // REX
1598 } else {
1599 // 32-bit
1600 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1601 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1602 if (cbuf) {
1603 emit_opcode(*cbuf, 0x66);
1604 if (Matcher::_regEncode[dst_first] < 8) {
1605 if (Matcher::_regEncode[src_first] >= 8) {
1606 emit_opcode(*cbuf, Assembler::REX_R); // attention!
1607 }
1608 } else {
1609 if (Matcher::_regEncode[src_first] < 8) {
1610 emit_opcode(*cbuf, Assembler::REX_B); // attention!
1611 } else {
1612 emit_opcode(*cbuf, Assembler::REX_RB);
1613 }
1614 }
1615 emit_opcode(*cbuf, 0x0F);
1616 emit_opcode(*cbuf, 0x7E);
1617 emit_rm(*cbuf, 0x3,
1618 Matcher::_regEncode[src_first] & 7,
1619 Matcher::_regEncode[dst_first] & 7);
1620 #ifndef PRODUCT
1621 } else if (!do_size) {
1622 st->print("movdl %s, %s\t# spill",
1623 Matcher::regName[dst_first],
1624 Matcher::regName[src_first]);
1625 #endif
1626 }
1627 return
1628 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1629 ? 4
1630 : 5; // REX
1631 }
1632 } else if (dst_first_rc == rc_float) {
1633 // xmm -> xmm
1634 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1635 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1636 // 64-bit
1637 if (cbuf) {
1638 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
1639 if (Matcher::_regEncode[dst_first] < 8) {
1640 if (Matcher::_regEncode[src_first] >= 8) {
1641 emit_opcode(*cbuf, Assembler::REX_B);
1642 }
1643 } else {
1644 if (Matcher::_regEncode[src_first] < 8) {
1645 emit_opcode(*cbuf, Assembler::REX_R);
1646 } else {
1647 emit_opcode(*cbuf, Assembler::REX_RB);
1648 }
1649 }
1650 emit_opcode(*cbuf, 0x0F);
1651 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
1652 emit_rm(*cbuf, 0x3,
1653 Matcher::_regEncode[dst_first] & 7,
1654 Matcher::_regEncode[src_first] & 7);
1655 #ifndef PRODUCT
1656 } else if (!do_size) {
1657 st->print("%s %s, %s\t# spill",
1658 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1659 Matcher::regName[dst_first],
1660 Matcher::regName[src_first]);
1661 #endif
1662 }
1663 return
1664 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1665 ? 4
1666 : 5; // REX
1667 } else {
1668 // 32-bit
1669 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1670 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1671 if (cbuf) {
1672 if (!UseXmmRegToRegMoveAll)
1673 emit_opcode(*cbuf, 0xF3);
1674 if (Matcher::_regEncode[dst_first] < 8) {
1675 if (Matcher::_regEncode[src_first] >= 8) {
1676 emit_opcode(*cbuf, Assembler::REX_B);
1677 }
1678 } else {
1679 if (Matcher::_regEncode[src_first] < 8) {
1680 emit_opcode(*cbuf, Assembler::REX_R);
1681 } else {
1682 emit_opcode(*cbuf, Assembler::REX_RB);
1683 }
1684 }
1685 emit_opcode(*cbuf, 0x0F);
1686 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
1687 emit_rm(*cbuf, 0x3,
1688 Matcher::_regEncode[dst_first] & 7,
1689 Matcher::_regEncode[src_first] & 7);
1690 #ifndef PRODUCT
1691 } else if (!do_size) {
1692 st->print("%s %s, %s\t# spill",
1693 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1694 Matcher::regName[dst_first],
1695 Matcher::regName[src_first]);
1696 #endif
1697 }
1698 return
1699 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1700 ? (UseXmmRegToRegMoveAll ? 3 : 4)
1701 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
1702 }
1703 }
1704 }
1705
1706 assert(0," foo ");
1707 Unimplemented();
1708
1709 return 0;
1710 }
1711
1712 #ifndef PRODUCT
1713 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
1714 {
1715 implementation(NULL, ra_, false, st);
1716 }
1717 #endif
1718
1719 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
1720 {
1721 implementation(&cbuf, ra_, false, NULL);
1722 }
1723
1724 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
1725 {
1726 return implementation(NULL, ra_, true, NULL);
1727 }
1728
1729 //=============================================================================
1730 #ifndef PRODUCT
1731 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
1732 {
1733 st->print("nop \t# %d bytes pad for loops and calls", _count);
1734 }
1735 #endif
1736
1737 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
1738 {
1739 MacroAssembler _masm(&cbuf);
1740 __ nop(_count);
1741 }
1742
1743 uint MachNopNode::size(PhaseRegAlloc*) const
1744 {
1745 return _count;
1746 }
1747
1748
1749 //=============================================================================
1750 #ifndef PRODUCT
1751 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1752 {
1753 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1754 int reg = ra_->get_reg_first(this);
1755 st->print("leaq %s, [rsp + #%d]\t# box lock",
1756 Matcher::regName[reg], offset);
1757 }
1758 #endif
1759
1760 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1761 {
1762 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1763 int reg = ra_->get_encode(this);
1764 if (offset >= 0x80) {
1765 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1766 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1767 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1768 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1769 emit_d32(cbuf, offset);
1770 } else {
1771 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1772 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1773 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1774 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1775 emit_d8(cbuf, offset);
1776 }
1777 }
1778
1779 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1780 {
1781 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1782 return (offset < 0x80) ? 5 : 8; // REX
1783 }
1784
1785 //=============================================================================
1786
1787 // emit call stub, compiled java to interpreter
1788 void emit_java_to_interp(CodeBuffer& cbuf)
1789 {
1790 // Stub is fixed up when the corresponding call is converted from
1791 // calling compiled code to calling interpreted code.
1792 // movq rbx, 0
1793 // jmp -5 # to self
1794
1795 address mark = cbuf.insts_mark(); // get mark within main instrs section
1796
1797 // Note that the code buffer's insts_mark is always relative to insts.
1798 // That's why we must use the macroassembler to generate a stub.
1799 MacroAssembler _masm(&cbuf);
1800
1801 address base =
1802 __ start_a_stub(Compile::MAX_stubs_size);
1803 if (base == NULL) return; // CodeBuffer::expand failed
1804 // static stub relocation stores the instruction address of the call
1805 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
1806 // static stub relocation also tags the methodOop in the code-stream.
1807 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
1808 // This is recognized as unresolved by relocs/nativeinst/ic code
1809 __ jump(RuntimeAddress(__ pc()));
1810
1811 // Update current stubs pointer and restore insts_end.
1812 __ end_a_stub();
1813 }
1814
1815 // size of call stub, compiled java to interpretor
1816 uint size_java_to_interp()
1817 {
1818 return 15; // movq (1+1+8); jmp (1+4)
1819 }
1820
1821 // relocation entries for call stub, compiled java to interpretor
1822 uint reloc_java_to_interp()
1823 {
1824 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1825 }
1826
1827 //=============================================================================
1828 #ifndef PRODUCT
1829 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1830 {
1831 if (UseCompressedOops) {
1832 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1833 if (Universe::narrow_oop_shift() != 0) {
1834 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
1835 }
1836 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1837 } else {
1838 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1839 "# Inline cache check");
1840 }
1841 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1842 st->print_cr("\tnop\t# nops to align entry point");
1843 }
1844 #endif
1845
1846 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1847 {
1848 MacroAssembler masm(&cbuf);
1849 uint insts_size = cbuf.insts_size();
1850 if (UseCompressedOops) {
1851 masm.load_klass(rscratch1, j_rarg0);
1852 masm.cmpptr(rax, rscratch1);
1853 } else {
1854 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1855 }
1856
1857 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1858
1859 /* WARNING these NOPs are critical so that verified entry point is properly
1860 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1861 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1862 if (OptoBreakpoint) {
1863 // Leave space for int3
1864 nops_cnt -= 1;
1865 }
1866 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1867 if (nops_cnt > 0)
1868 masm.nop(nops_cnt);
1869 }
1870
1871 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1872 {
1873 return MachNode::size(ra_); // too many variables; just compute it
1874 // the hard way
1875 }
1876
1877
1878 //=============================================================================
1879 uint size_exception_handler()
1880 {
1881 // NativeCall instruction size is the same as NativeJump.
1882 // Note that this value is also credited (in output.cpp) to
1883 // the size of the code section.
1884 return NativeJump::instruction_size;
1885 }
1886
1887 // Emit exception handler code.
1888 int emit_exception_handler(CodeBuffer& cbuf)
1889 {
1890
1891 // Note that the code buffer's insts_mark is always relative to insts.
1892 // That's why we must use the macroassembler to generate a handler.
1893 MacroAssembler _masm(&cbuf);
1894 address base =
1895 __ start_a_stub(size_exception_handler());
1896 if (base == NULL) return 0; // CodeBuffer::expand failed
1897 int offset = __ offset();
1898 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1899 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1900 __ end_a_stub();
1901 return offset;
1902 }
1903
1904 uint size_deopt_handler()
1905 {
1906 // three 5 byte instructions
1907 return 15;
1908 }
1909
1910 // Emit deopt handler code.
1911 int emit_deopt_handler(CodeBuffer& cbuf)
1912 {
1913
1914 // Note that the code buffer's insts_mark is always relative to insts.
1915 // That's why we must use the macroassembler to generate a handler.
1916 MacroAssembler _masm(&cbuf);
1917 address base =
1918 __ start_a_stub(size_deopt_handler());
1919 if (base == NULL) return 0; // CodeBuffer::expand failed
1920 int offset = __ offset();
1921 address the_pc = (address) __ pc();
1922 Label next;
1923 // push a "the_pc" on the stack without destroying any registers
1924 // as they all may be live.
1925
1926 // push address of "next"
1927 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1928 __ bind(next);
1929 // adjust it so it matches "the_pc"
1930 __ subptr(Address(rsp, 0), __ offset() - offset);
1931 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1932 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1933 __ end_a_stub();
1934 return offset;
1935 }
1936
1937
1938 const bool Matcher::match_rule_supported(int opcode) {
1939 if (!has_match_rule(opcode))
1940 return false;
1941
1942 return true; // Per default match rules are supported.
1943 }
1944
1945 int Matcher::regnum_to_fpu_offset(int regnum)
1946 {
1947 return regnum - 32; // The FP registers are in the second chunk
1948 }
1949
1950 // This is UltraSparc specific, true just means we have fast l2f conversion
1951 const bool Matcher::convL2FSupported(void) {
1952 return true;
1953 }
1954
1955 // Vector width in bytes
1956 const uint Matcher::vector_width_in_bytes(void) {
1957 return 8;
1958 }
1959
1960 // Vector ideal reg
1961 const uint Matcher::vector_ideal_reg(void) {
1962 return Op_RegD;
1963 }
1964
1965 // Is this branch offset short enough that a short branch can be used?
1966 //
1967 // NOTE: If the platform does not provide any short branch variants, then
1968 // this method should return false for offset 0.
1969 bool Matcher::is_short_branch_offset(int rule, int offset) {
1970 // the short version of jmpConUCF2 contains multiple branches,
1971 // making the reach slightly less
1972 if (rule == jmpConUCF2_rule)
1973 return (-126 <= offset && offset <= 125);
1974 return (-128 <= offset && offset <= 127);
1975 }
1976
1977 const bool Matcher::isSimpleConstant64(jlong value) {
1978 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1979 //return value == (int) value; // Cf. storeImmL and immL32.
1980
1981 // Probably always true, even if a temp register is required.
1982 return true;
1983 }
1984
1985 // The ecx parameter to rep stosq for the ClearArray node is in words.
1986 const bool Matcher::init_array_count_is_in_bytes = false;
1987
1988 // Threshold size for cleararray.
1989 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1990
1991 // Should the Matcher clone shifts on addressing modes, expecting them
1992 // to be subsumed into complex addressing expressions or compute them
1993 // into registers? True for Intel but false for most RISCs
1994 const bool Matcher::clone_shift_expressions = true;
1995
1996 // Do we need to mask the count passed to shift instructions or does
1997 // the cpu only look at the lower 5/6 bits anyway?
1998 const bool Matcher::need_masked_shift_count = false;
1999
2000 bool Matcher::narrow_oop_use_complex_address() {
2001 assert(UseCompressedOops, "only for compressed oops code");
2002 return (LogMinObjAlignmentInBytes <= 3);
2003 }
2004
2005 // Is it better to copy float constants, or load them directly from
2006 // memory? Intel can load a float constant from a direct address,
2007 // requiring no extra registers. Most RISCs will have to materialize
2008 // an address into a register first, so they would do better to copy
2009 // the constant from stack.
2010 const bool Matcher::rematerialize_float_constants = true; // XXX
2011
2012 // If CPU can load and store mis-aligned doubles directly then no
2013 // fixup is needed. Else we split the double into 2 integer pieces
2014 // and move it piece-by-piece. Only happens when passing doubles into
2015 // C code as the Java calling convention forces doubles to be aligned.
2016 const bool Matcher::misaligned_doubles_ok = true;
2017
2018 // No-op on amd64
2019 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
2020
2021 // Advertise here if the CPU requires explicit rounding operations to
2022 // implement the UseStrictFP mode.
2023 const bool Matcher::strict_fp_requires_explicit_rounding = true;
2024
2025 // Are floats conerted to double when stored to stack during deoptimization?
2026 // On x64 it is stored without convertion so we can use normal access.
2027 bool Matcher::float_in_double() { return false; }
2028
2029 // Do ints take an entire long register or just half?
2030 const bool Matcher::int_in_long = true;
2031
2032 // Return whether or not this register is ever used as an argument.
2033 // This function is used on startup to build the trampoline stubs in
2034 // generateOptoStub. Registers not mentioned will be killed by the VM
2035 // call in the trampoline, and arguments in those registers not be
2036 // available to the callee.
2037 bool Matcher::can_be_java_arg(int reg)
2038 {
2039 return
2040 reg == RDI_num || reg == RDI_H_num ||
2041 reg == RSI_num || reg == RSI_H_num ||
2042 reg == RDX_num || reg == RDX_H_num ||
2043 reg == RCX_num || reg == RCX_H_num ||
2044 reg == R8_num || reg == R8_H_num ||
2045 reg == R9_num || reg == R9_H_num ||
2046 reg == R12_num || reg == R12_H_num ||
2047 reg == XMM0_num || reg == XMM0_H_num ||
2048 reg == XMM1_num || reg == XMM1_H_num ||
2049 reg == XMM2_num || reg == XMM2_H_num ||
2050 reg == XMM3_num || reg == XMM3_H_num ||
2051 reg == XMM4_num || reg == XMM4_H_num ||
2052 reg == XMM5_num || reg == XMM5_H_num ||
2053 reg == XMM6_num || reg == XMM6_H_num ||
2054 reg == XMM7_num || reg == XMM7_H_num;
2055 }
2056
2057 bool Matcher::is_spillable_arg(int reg)
2058 {
2059 return can_be_java_arg(reg);
2060 }
2061
2062 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2063 // In 64 bit mode a code which use multiply when
2064 // devisor is constant is faster than hardware
2065 // DIV instruction (it uses MulHiL).
2066 return false;
2067 }
2068
2069 // Register for DIVI projection of divmodI
2070 RegMask Matcher::divI_proj_mask() {
2071 return INT_RAX_REG_mask;
2072 }
2073
2074 // Register for MODI projection of divmodI
2075 RegMask Matcher::modI_proj_mask() {
2076 return INT_RDX_REG_mask;
2077 }
2078
2079 // Register for DIVL projection of divmodL
2080 RegMask Matcher::divL_proj_mask() {
2081 return LONG_RAX_REG_mask;
2082 }
2083
2084 // Register for MODL projection of divmodL
2085 RegMask Matcher::modL_proj_mask() {
2086 return LONG_RDX_REG_mask;
2087 }
2088
2089 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2090 return PTR_RBP_REG_mask;
2091 }
2092
2093 static Address build_address(int b, int i, int s, int d) {
2094 Register index = as_Register(i);
2095 Address::ScaleFactor scale = (Address::ScaleFactor)s;
2096 if (index == rsp) {
2097 index = noreg;
2098 scale = Address::no_scale;
2099 }
2100 Address addr(as_Register(b), index, scale, d);
2101 return addr;
2102 }
2103
2104 %}
2105
2106 //----------ENCODING BLOCK-----------------------------------------------------
2107 // This block specifies the encoding classes used by the compiler to
2108 // output byte streams. Encoding classes are parameterized macros
2109 // used by Machine Instruction Nodes in order to generate the bit
2110 // encoding of the instruction. Operands specify their base encoding
2111 // interface with the interface keyword. There are currently
2112 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2113 // COND_INTER. REG_INTER causes an operand to generate a function
2114 // which returns its register number when queried. CONST_INTER causes
2115 // an operand to generate a function which returns the value of the
2116 // constant when queried. MEMORY_INTER causes an operand to generate
2117 // four functions which return the Base Register, the Index Register,
2118 // the Scale Value, and the Offset Value of the operand when queried.
2119 // COND_INTER causes an operand to generate six functions which return
2120 // the encoding code (ie - encoding bits for the instruction)
2121 // associated with each basic boolean condition for a conditional
2122 // instruction.
2123 //
2124 // Instructions specify two basic values for encoding. Again, a
2125 // function is available to check if the constant displacement is an
2126 // oop. They use the ins_encode keyword to specify their encoding
2127 // classes (which must be a sequence of enc_class names, and their
2128 // parameters, specified in the encoding block), and they use the
2129 // opcode keyword to specify, in order, their primary, secondary, and
2130 // tertiary opcode. Only the opcode sections which a particular
2131 // instruction needs for encoding need to be specified.
2132 encode %{
2133 // Build emit functions for each basic byte or larger field in the
2134 // intel encoding scheme (opcode, rm, sib, immediate), and call them
2135 // from C++ code in the enc_class source block. Emit functions will
2136 // live in the main source block for now. In future, we can
2137 // generalize this by adding a syntax that specifies the sizes of
2138 // fields in an order, so that the adlc can build the emit functions
2139 // automagically
2140
2141 // Emit primary opcode
2142 enc_class OpcP
2143 %{
2144 emit_opcode(cbuf, $primary);
2145 %}
2146
2147 // Emit secondary opcode
2148 enc_class OpcS
2149 %{
2150 emit_opcode(cbuf, $secondary);
2151 %}
2152
2153 // Emit tertiary opcode
2154 enc_class OpcT
2155 %{
2156 emit_opcode(cbuf, $tertiary);
2157 %}
2158
2159 // Emit opcode directly
2160 enc_class Opcode(immI d8)
2161 %{
2162 emit_opcode(cbuf, $d8$$constant);
2163 %}
2164
2165 // Emit size prefix
2166 enc_class SizePrefix
2167 %{
2168 emit_opcode(cbuf, 0x66);
2169 %}
2170
2171 enc_class reg(rRegI reg)
2172 %{
2173 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
2174 %}
2175
2176 enc_class reg_reg(rRegI dst, rRegI src)
2177 %{
2178 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2179 %}
2180
2181 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
2182 %{
2183 emit_opcode(cbuf, $opcode$$constant);
2184 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2185 %}
2186
2187 enc_class cmpfp_fixup() %{
2188 MacroAssembler _masm(&cbuf);
2189 emit_cmpfp_fixup(_masm);
2190 %}
2191
2192 enc_class cmpfp3(rRegI dst)
2193 %{
2194 int dstenc = $dst$$reg;
2195
2196 // movl $dst, -1
2197 if (dstenc >= 8) {
2198 emit_opcode(cbuf, Assembler::REX_B);
2199 }
2200 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2201 emit_d32(cbuf, -1);
2202
2203 // jp,s done
2204 emit_opcode(cbuf, 0x7A);
2205 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
2206
2207 // jb,s done
2208 emit_opcode(cbuf, 0x72);
2209 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2210
2211 // setne $dst
2212 if (dstenc >= 4) {
2213 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2214 }
2215 emit_opcode(cbuf, 0x0F);
2216 emit_opcode(cbuf, 0x95);
2217 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2218
2219 // movzbl $dst, $dst
2220 if (dstenc >= 4) {
2221 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2222 }
2223 emit_opcode(cbuf, 0x0F);
2224 emit_opcode(cbuf, 0xB6);
2225 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2226 %}
2227
2228 enc_class cdql_enc(no_rax_rdx_RegI div)
2229 %{
2230 // Full implementation of Java idiv and irem; checks for
2231 // special case as described in JVM spec., p.243 & p.271.
2232 //
2233 // normal case special case
2234 //
2235 // input : rax: dividend min_int
2236 // reg: divisor -1
2237 //
2238 // output: rax: quotient (= rax idiv reg) min_int
2239 // rdx: remainder (= rax irem reg) 0
2240 //
2241 // Code sequnce:
2242 //
2243 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
2244 // 5: 75 07/08 jne e <normal>
2245 // 7: 33 d2 xor %edx,%edx
2246 // [div >= 8 -> offset + 1]
2247 // [REX_B]
2248 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
2249 // c: 74 03/04 je 11 <done>
2250 // 000000000000000e <normal>:
2251 // e: 99 cltd
2252 // [div >= 8 -> offset + 1]
2253 // [REX_B]
2254 // f: f7 f9 idiv $div
2255 // 0000000000000011 <done>:
2256
2257 // cmp $0x80000000,%eax
2258 emit_opcode(cbuf, 0x3d);
2259 emit_d8(cbuf, 0x00);
2260 emit_d8(cbuf, 0x00);
2261 emit_d8(cbuf, 0x00);
2262 emit_d8(cbuf, 0x80);
2263
2264 // jne e <normal>
2265 emit_opcode(cbuf, 0x75);
2266 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
2267
2268 // xor %edx,%edx
2269 emit_opcode(cbuf, 0x33);
2270 emit_d8(cbuf, 0xD2);
2271
2272 // cmp $0xffffffffffffffff,%ecx
2273 if ($div$$reg >= 8) {
2274 emit_opcode(cbuf, Assembler::REX_B);
2275 }
2276 emit_opcode(cbuf, 0x83);
2277 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2278 emit_d8(cbuf, 0xFF);
2279
2280 // je 11 <done>
2281 emit_opcode(cbuf, 0x74);
2282 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
2283
2284 // <normal>
2285 // cltd
2286 emit_opcode(cbuf, 0x99);
2287
2288 // idivl (note: must be emitted by the user of this rule)
2289 // <done>
2290 %}
2291
2292 enc_class cdqq_enc(no_rax_rdx_RegL div)
2293 %{
2294 // Full implementation of Java ldiv and lrem; checks for
2295 // special case as described in JVM spec., p.243 & p.271.
2296 //
2297 // normal case special case
2298 //
2299 // input : rax: dividend min_long
2300 // reg: divisor -1
2301 //
2302 // output: rax: quotient (= rax idiv reg) min_long
2303 // rdx: remainder (= rax irem reg) 0
2304 //
2305 // Code sequnce:
2306 //
2307 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
2308 // 7: 00 00 80
2309 // a: 48 39 d0 cmp %rdx,%rax
2310 // d: 75 08 jne 17 <normal>
2311 // f: 33 d2 xor %edx,%edx
2312 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
2313 // 15: 74 05 je 1c <done>
2314 // 0000000000000017 <normal>:
2315 // 17: 48 99 cqto
2316 // 19: 48 f7 f9 idiv $div
2317 // 000000000000001c <done>:
2318
2319 // mov $0x8000000000000000,%rdx
2320 emit_opcode(cbuf, Assembler::REX_W);
2321 emit_opcode(cbuf, 0xBA);
2322 emit_d8(cbuf, 0x00);
2323 emit_d8(cbuf, 0x00);
2324 emit_d8(cbuf, 0x00);
2325 emit_d8(cbuf, 0x00);
2326 emit_d8(cbuf, 0x00);
2327 emit_d8(cbuf, 0x00);
2328 emit_d8(cbuf, 0x00);
2329 emit_d8(cbuf, 0x80);
2330
2331 // cmp %rdx,%rax
2332 emit_opcode(cbuf, Assembler::REX_W);
2333 emit_opcode(cbuf, 0x39);
2334 emit_d8(cbuf, 0xD0);
2335
2336 // jne 17 <normal>
2337 emit_opcode(cbuf, 0x75);
2338 emit_d8(cbuf, 0x08);
2339
2340 // xor %edx,%edx
2341 emit_opcode(cbuf, 0x33);
2342 emit_d8(cbuf, 0xD2);
2343
2344 // cmp $0xffffffffffffffff,$div
2345 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
2346 emit_opcode(cbuf, 0x83);
2347 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2348 emit_d8(cbuf, 0xFF);
2349
2350 // je 1e <done>
2351 emit_opcode(cbuf, 0x74);
2352 emit_d8(cbuf, 0x05);
2353
2354 // <normal>
2355 // cqto
2356 emit_opcode(cbuf, Assembler::REX_W);
2357 emit_opcode(cbuf, 0x99);
2358
2359 // idivq (note: must be emitted by the user of this rule)
2360 // <done>
2361 %}
2362
2363 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2364 enc_class OpcSE(immI imm)
2365 %{
2366 // Emit primary opcode and set sign-extend bit
2367 // Check for 8-bit immediate, and set sign extend bit in opcode
2368 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2369 emit_opcode(cbuf, $primary | 0x02);
2370 } else {
2371 // 32-bit immediate
2372 emit_opcode(cbuf, $primary);
2373 }
2374 %}
2375
2376 enc_class OpcSErm(rRegI dst, immI imm)
2377 %{
2378 // OpcSEr/m
2379 int dstenc = $dst$$reg;
2380 if (dstenc >= 8) {
2381 emit_opcode(cbuf, Assembler::REX_B);
2382 dstenc -= 8;
2383 }
2384 // Emit primary opcode and set sign-extend bit
2385 // Check for 8-bit immediate, and set sign extend bit in opcode
2386 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2387 emit_opcode(cbuf, $primary | 0x02);
2388 } else {
2389 // 32-bit immediate
2390 emit_opcode(cbuf, $primary);
2391 }
2392 // Emit r/m byte with secondary opcode, after primary opcode.
2393 emit_rm(cbuf, 0x3, $secondary, dstenc);
2394 %}
2395
2396 enc_class OpcSErm_wide(rRegL dst, immI imm)
2397 %{
2398 // OpcSEr/m
2399 int dstenc = $dst$$reg;
2400 if (dstenc < 8) {
2401 emit_opcode(cbuf, Assembler::REX_W);
2402 } else {
2403 emit_opcode(cbuf, Assembler::REX_WB);
2404 dstenc -= 8;
2405 }
2406 // Emit primary opcode and set sign-extend bit
2407 // Check for 8-bit immediate, and set sign extend bit in opcode
2408 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2409 emit_opcode(cbuf, $primary | 0x02);
2410 } else {
2411 // 32-bit immediate
2412 emit_opcode(cbuf, $primary);
2413 }
2414 // Emit r/m byte with secondary opcode, after primary opcode.
2415 emit_rm(cbuf, 0x3, $secondary, dstenc);
2416 %}
2417
2418 enc_class Con8or32(immI imm)
2419 %{
2420 // Check for 8-bit immediate, and set sign extend bit in opcode
2421 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2422 $$$emit8$imm$$constant;
2423 } else {
2424 // 32-bit immediate
2425 $$$emit32$imm$$constant;
2426 }
2427 %}
2428
2429 enc_class Lbl(label labl)
2430 %{
2431 // GOTO
2432 Label* l = $labl$$label;
2433 assert(l != NULL, "need Label");
2434 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0);
2435 %}
2436
2437 enc_class LblShort(label labl)
2438 %{
2439 // GOTO
2440 Label* l = $labl$$label;
2441 assert(l != NULL, "need Label");
2442 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
2443 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
2444 emit_d8(cbuf, disp);
2445 %}
2446
2447 enc_class opc2_reg(rRegI dst)
2448 %{
2449 // BSWAP
2450 emit_cc(cbuf, $secondary, $dst$$reg);
2451 %}
2452
2453 enc_class opc3_reg(rRegI dst)
2454 %{
2455 // BSWAP
2456 emit_cc(cbuf, $tertiary, $dst$$reg);
2457 %}
2458
2459 enc_class reg_opc(rRegI div)
2460 %{
2461 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2462 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2463 %}
2464
2465 enc_class Jcc(cmpOp cop, label labl)
2466 %{
2467 // JCC
2468 Label* l = $labl$$label;
2469 assert(l != NULL, "need Label");
2470 $$$emit8$primary;
2471 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2472 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0);
2473 %}
2474
2475 enc_class JccShort (cmpOp cop, label labl)
2476 %{
2477 // JCC
2478 Label *l = $labl$$label;
2479 assert(l != NULL, "need Label");
2480 emit_cc(cbuf, $primary, $cop$$cmpcode);
2481 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
2482 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
2483 emit_d8(cbuf, disp);
2484 %}
2485
2486 enc_class enc_cmov(cmpOp cop)
2487 %{
2488 // CMOV
2489 $$$emit8$primary;
2490 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2491 %}
2492
2493 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
2494 %{
2495 // Invert sense of branch from sense of cmov
2496 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
2497 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
2498 ? (UseXmmRegToRegMoveAll ? 3 : 4)
2499 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
2500 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
2501 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
2502 if ($dst$$reg < 8) {
2503 if ($src$$reg >= 8) {
2504 emit_opcode(cbuf, Assembler::REX_B);
2505 }
2506 } else {
2507 if ($src$$reg < 8) {
2508 emit_opcode(cbuf, Assembler::REX_R);
2509 } else {
2510 emit_opcode(cbuf, Assembler::REX_RB);
2511 }
2512 }
2513 emit_opcode(cbuf, 0x0F);
2514 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
2515 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2516 %}
2517
2518 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
2519 %{
2520 // Invert sense of branch from sense of cmov
2521 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
2522 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
2523
2524 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
2525 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
2526 if ($dst$$reg < 8) {
2527 if ($src$$reg >= 8) {
2528 emit_opcode(cbuf, Assembler::REX_B);
2529 }
2530 } else {
2531 if ($src$$reg < 8) {
2532 emit_opcode(cbuf, Assembler::REX_R);
2533 } else {
2534 emit_opcode(cbuf, Assembler::REX_RB);
2535 }
2536 }
2537 emit_opcode(cbuf, 0x0F);
2538 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
2539 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2540 %}
2541
2542 enc_class enc_PartialSubtypeCheck()
2543 %{
2544 Register Rrdi = as_Register(RDI_enc); // result register
2545 Register Rrax = as_Register(RAX_enc); // super class
2546 Register Rrcx = as_Register(RCX_enc); // killed
2547 Register Rrsi = as_Register(RSI_enc); // sub class
2548 Label miss;
2549 const bool set_cond_codes = true;
2550
2551 MacroAssembler _masm(&cbuf);
2552 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2553 NULL, &miss,
2554 /*set_cond_codes:*/ true);
2555 if ($primary) {
2556 __ xorptr(Rrdi, Rrdi);
2557 }
2558 __ bind(miss);
2559 %}
2560
2561 enc_class Java_To_Interpreter(method meth)
2562 %{
2563 // CALL Java_To_Interpreter
2564 // This is the instruction starting address for relocation info.
2565 cbuf.set_insts_mark();
2566 $$$emit8$primary;
2567 // CALL directly to the runtime
2568 emit_d32_reloc(cbuf,
2569 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2570 runtime_call_Relocation::spec(),
2571 RELOC_DISP32);
2572 %}
2573
2574 enc_class preserve_SP %{
2575 debug_only(int off0 = cbuf.insts_size());
2576 MacroAssembler _masm(&cbuf);
2577 // RBP is preserved across all calls, even compiled calls.
2578 // Use it to preserve RSP in places where the callee might change the SP.
2579 __ movptr(rbp_mh_SP_save, rsp);
2580 debug_only(int off1 = cbuf.insts_size());
2581 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
2582 %}
2583
2584 enc_class restore_SP %{
2585 MacroAssembler _masm(&cbuf);
2586 __ movptr(rsp, rbp_mh_SP_save);
2587 %}
2588
2589 enc_class Java_Static_Call(method meth)
2590 %{
2591 // JAVA STATIC CALL
2592 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2593 // determine who we intended to call.
2594 cbuf.set_insts_mark();
2595 $$$emit8$primary;
2596
2597 if (!_method) {
2598 emit_d32_reloc(cbuf,
2599 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2600 runtime_call_Relocation::spec(),
2601 RELOC_DISP32);
2602 } else if (_optimized_virtual) {
2603 emit_d32_reloc(cbuf,
2604 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2605 opt_virtual_call_Relocation::spec(),
2606 RELOC_DISP32);
2607 } else {
2608 emit_d32_reloc(cbuf,
2609 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2610 static_call_Relocation::spec(),
2611 RELOC_DISP32);
2612 }
2613 if (_method) {
2614 // Emit stub for static call
2615 emit_java_to_interp(cbuf);
2616 }
2617 %}
2618
2619 enc_class Java_Dynamic_Call(method meth)
2620 %{
2621 // JAVA DYNAMIC CALL
2622 // !!!!!
2623 // Generate "movq rax, -1", placeholder instruction to load oop-info
2624 // emit_call_dynamic_prologue( cbuf );
2625 cbuf.set_insts_mark();
2626
2627 // movq rax, -1
2628 emit_opcode(cbuf, Assembler::REX_W);
2629 emit_opcode(cbuf, 0xB8 | RAX_enc);
2630 emit_d64_reloc(cbuf,
2631 (int64_t) Universe::non_oop_word(),
2632 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
2633 address virtual_call_oop_addr = cbuf.insts_mark();
2634 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2635 // who we intended to call.
2636 cbuf.set_insts_mark();
2637 $$$emit8$primary;
2638 emit_d32_reloc(cbuf,
2639 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2640 virtual_call_Relocation::spec(virtual_call_oop_addr),
2641 RELOC_DISP32);
2642 %}
2643
2644 enc_class Java_Compiled_Call(method meth)
2645 %{
2646 // JAVA COMPILED CALL
2647 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
2648
2649 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2650 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2651
2652 // callq *disp(%rax)
2653 cbuf.set_insts_mark();
2654 $$$emit8$primary;
2655 if (disp < 0x80) {
2656 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2657 emit_d8(cbuf, disp); // Displacement
2658 } else {
2659 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2660 emit_d32(cbuf, disp); // Displacement
2661 }
2662 %}
2663
2664 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2665 %{
2666 // SAL, SAR, SHR
2667 int dstenc = $dst$$reg;
2668 if (dstenc >= 8) {
2669 emit_opcode(cbuf, Assembler::REX_B);
2670 dstenc -= 8;
2671 }
2672 $$$emit8$primary;
2673 emit_rm(cbuf, 0x3, $secondary, dstenc);
2674 $$$emit8$shift$$constant;
2675 %}
2676
2677 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2678 %{
2679 // SAL, SAR, SHR
2680 int dstenc = $dst$$reg;
2681 if (dstenc < 8) {
2682 emit_opcode(cbuf, Assembler::REX_W);
2683 } else {
2684 emit_opcode(cbuf, Assembler::REX_WB);
2685 dstenc -= 8;
2686 }
2687 $$$emit8$primary;
2688 emit_rm(cbuf, 0x3, $secondary, dstenc);
2689 $$$emit8$shift$$constant;
2690 %}
2691
2692 enc_class load_immI(rRegI dst, immI src)
2693 %{
2694 int dstenc = $dst$$reg;
2695 if (dstenc >= 8) {
2696 emit_opcode(cbuf, Assembler::REX_B);
2697 dstenc -= 8;
2698 }
2699 emit_opcode(cbuf, 0xB8 | dstenc);
2700 $$$emit32$src$$constant;
2701 %}
2702
2703 enc_class load_immL(rRegL dst, immL src)
2704 %{
2705 int dstenc = $dst$$reg;
2706 if (dstenc < 8) {
2707 emit_opcode(cbuf, Assembler::REX_W);
2708 } else {
2709 emit_opcode(cbuf, Assembler::REX_WB);
2710 dstenc -= 8;
2711 }
2712 emit_opcode(cbuf, 0xB8 | dstenc);
2713 emit_d64(cbuf, $src$$constant);
2714 %}
2715
2716 enc_class load_immUL32(rRegL dst, immUL32 src)
2717 %{
2718 // same as load_immI, but this time we care about zeroes in the high word
2719 int dstenc = $dst$$reg;
2720 if (dstenc >= 8) {
2721 emit_opcode(cbuf, Assembler::REX_B);
2722 dstenc -= 8;
2723 }
2724 emit_opcode(cbuf, 0xB8 | dstenc);
2725 $$$emit32$src$$constant;
2726 %}
2727
2728 enc_class load_immL32(rRegL dst, immL32 src)
2729 %{
2730 int dstenc = $dst$$reg;
2731 if (dstenc < 8) {
2732 emit_opcode(cbuf, Assembler::REX_W);
2733 } else {
2734 emit_opcode(cbuf, Assembler::REX_WB);
2735 dstenc -= 8;
2736 }
2737 emit_opcode(cbuf, 0xC7);
2738 emit_rm(cbuf, 0x03, 0x00, dstenc);
2739 $$$emit32$src$$constant;
2740 %}
2741
2742 enc_class load_immP31(rRegP dst, immP32 src)
2743 %{
2744 // same as load_immI, but this time we care about zeroes in the high word
2745 int dstenc = $dst$$reg;
2746 if (dstenc >= 8) {
2747 emit_opcode(cbuf, Assembler::REX_B);
2748 dstenc -= 8;
2749 }
2750 emit_opcode(cbuf, 0xB8 | dstenc);
2751 $$$emit32$src$$constant;
2752 %}
2753
2754 enc_class load_immP(rRegP dst, immP src)
2755 %{
2756 int dstenc = $dst$$reg;
2757 if (dstenc < 8) {
2758 emit_opcode(cbuf, Assembler::REX_W);
2759 } else {
2760 emit_opcode(cbuf, Assembler::REX_WB);
2761 dstenc -= 8;
2762 }
2763 emit_opcode(cbuf, 0xB8 | dstenc);
2764 // This next line should be generated from ADLC
2765 if ($src->constant_is_oop()) {
2766 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
2767 } else {
2768 emit_d64(cbuf, $src$$constant);
2769 }
2770 %}
2771
2772 // Encode a reg-reg copy. If it is useless, then empty encoding.
2773 enc_class enc_copy(rRegI dst, rRegI src)
2774 %{
2775 encode_copy(cbuf, $dst$$reg, $src$$reg);
2776 %}
2777
2778 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2779 enc_class enc_CopyXD( RegD dst, RegD src ) %{
2780 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2781 %}
2782
2783 enc_class enc_copy_always(rRegI dst, rRegI src)
2784 %{
2785 int srcenc = $src$$reg;
2786 int dstenc = $dst$$reg;
2787
2788 if (dstenc < 8) {
2789 if (srcenc >= 8) {
2790 emit_opcode(cbuf, Assembler::REX_B);
2791 srcenc -= 8;
2792 }
2793 } else {
2794 if (srcenc < 8) {
2795 emit_opcode(cbuf, Assembler::REX_R);
2796 } else {
2797 emit_opcode(cbuf, Assembler::REX_RB);
2798 srcenc -= 8;
2799 }
2800 dstenc -= 8;
2801 }
2802
2803 emit_opcode(cbuf, 0x8B);
2804 emit_rm(cbuf, 0x3, dstenc, srcenc);
2805 %}
2806
2807 enc_class enc_copy_wide(rRegL dst, rRegL src)
2808 %{
2809 int srcenc = $src$$reg;
2810 int dstenc = $dst$$reg;
2811
2812 if (dstenc != srcenc) {
2813 if (dstenc < 8) {
2814 if (srcenc < 8) {
2815 emit_opcode(cbuf, Assembler::REX_W);
2816 } else {
2817 emit_opcode(cbuf, Assembler::REX_WB);
2818 srcenc -= 8;
2819 }
2820 } else {
2821 if (srcenc < 8) {
2822 emit_opcode(cbuf, Assembler::REX_WR);
2823 } else {
2824 emit_opcode(cbuf, Assembler::REX_WRB);
2825 srcenc -= 8;
2826 }
2827 dstenc -= 8;
2828 }
2829 emit_opcode(cbuf, 0x8B);
2830 emit_rm(cbuf, 0x3, dstenc, srcenc);
2831 }
2832 %}
2833
2834 enc_class Con32(immI src)
2835 %{
2836 // Output immediate
2837 $$$emit32$src$$constant;
2838 %}
2839
2840 enc_class Con64(immL src)
2841 %{
2842 // Output immediate
2843 emit_d64($src$$constant);
2844 %}
2845
2846 enc_class Con32F_as_bits(immF src)
2847 %{
2848 // Output Float immediate bits
2849 jfloat jf = $src$$constant;
2850 jint jf_as_bits = jint_cast(jf);
2851 emit_d32(cbuf, jf_as_bits);
2852 %}
2853
2854 enc_class Con16(immI src)
2855 %{
2856 // Output immediate
2857 $$$emit16$src$$constant;
2858 %}
2859
2860 // How is this different from Con32??? XXX
2861 enc_class Con_d32(immI src)
2862 %{
2863 emit_d32(cbuf,$src$$constant);
2864 %}
2865
2866 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2867 // Output immediate memory reference
2868 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2869 emit_d32(cbuf, 0x00);
2870 %}
2871
2872 enc_class lock_prefix()
2873 %{
2874 if (os::is_MP()) {
2875 emit_opcode(cbuf, 0xF0); // lock
2876 }
2877 %}
2878
2879 enc_class REX_mem(memory mem)
2880 %{
2881 if ($mem$$base >= 8) {
2882 if ($mem$$index < 8) {
2883 emit_opcode(cbuf, Assembler::REX_B);
2884 } else {
2885 emit_opcode(cbuf, Assembler::REX_XB);
2886 }
2887 } else {
2888 if ($mem$$index >= 8) {
2889 emit_opcode(cbuf, Assembler::REX_X);
2890 }
2891 }
2892 %}
2893
2894 enc_class REX_mem_wide(memory mem)
2895 %{
2896 if ($mem$$base >= 8) {
2897 if ($mem$$index < 8) {
2898 emit_opcode(cbuf, Assembler::REX_WB);
2899 } else {
2900 emit_opcode(cbuf, Assembler::REX_WXB);
2901 }
2902 } else {
2903 if ($mem$$index < 8) {
2904 emit_opcode(cbuf, Assembler::REX_W);
2905 } else {
2906 emit_opcode(cbuf, Assembler::REX_WX);
2907 }
2908 }
2909 %}
2910
2911 // for byte regs
2912 enc_class REX_breg(rRegI reg)
2913 %{
2914 if ($reg$$reg >= 4) {
2915 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2916 }
2917 %}
2918
2919 // for byte regs
2920 enc_class REX_reg_breg(rRegI dst, rRegI src)
2921 %{
2922 if ($dst$$reg < 8) {
2923 if ($src$$reg >= 4) {
2924 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2925 }
2926 } else {
2927 if ($src$$reg < 8) {
2928 emit_opcode(cbuf, Assembler::REX_R);
2929 } else {
2930 emit_opcode(cbuf, Assembler::REX_RB);
2931 }
2932 }
2933 %}
2934
2935 // for byte regs
2936 enc_class REX_breg_mem(rRegI reg, memory mem)
2937 %{
2938 if ($reg$$reg < 8) {
2939 if ($mem$$base < 8) {
2940 if ($mem$$index >= 8) {
2941 emit_opcode(cbuf, Assembler::REX_X);
2942 } else if ($reg$$reg >= 4) {
2943 emit_opcode(cbuf, Assembler::REX);
2944 }
2945 } else {
2946 if ($mem$$index < 8) {
2947 emit_opcode(cbuf, Assembler::REX_B);
2948 } else {
2949 emit_opcode(cbuf, Assembler::REX_XB);
2950 }
2951 }
2952 } else {
2953 if ($mem$$base < 8) {
2954 if ($mem$$index < 8) {
2955 emit_opcode(cbuf, Assembler::REX_R);
2956 } else {
2957 emit_opcode(cbuf, Assembler::REX_RX);
2958 }
2959 } else {
2960 if ($mem$$index < 8) {
2961 emit_opcode(cbuf, Assembler::REX_RB);
2962 } else {
2963 emit_opcode(cbuf, Assembler::REX_RXB);
2964 }
2965 }
2966 }
2967 %}
2968
2969 enc_class REX_reg(rRegI reg)
2970 %{
2971 if ($reg$$reg >= 8) {
2972 emit_opcode(cbuf, Assembler::REX_B);
2973 }
2974 %}
2975
2976 enc_class REX_reg_wide(rRegI reg)
2977 %{
2978 if ($reg$$reg < 8) {
2979 emit_opcode(cbuf, Assembler::REX_W);
2980 } else {
2981 emit_opcode(cbuf, Assembler::REX_WB);
2982 }
2983 %}
2984
2985 enc_class REX_reg_reg(rRegI dst, rRegI src)
2986 %{
2987 if ($dst$$reg < 8) {
2988 if ($src$$reg >= 8) {
2989 emit_opcode(cbuf, Assembler::REX_B);
2990 }
2991 } else {
2992 if ($src$$reg < 8) {
2993 emit_opcode(cbuf, Assembler::REX_R);
2994 } else {
2995 emit_opcode(cbuf, Assembler::REX_RB);
2996 }
2997 }
2998 %}
2999
3000 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
3001 %{
3002 if ($dst$$reg < 8) {
3003 if ($src$$reg < 8) {
3004 emit_opcode(cbuf, Assembler::REX_W);
3005 } else {
3006 emit_opcode(cbuf, Assembler::REX_WB);
3007 }
3008 } else {
3009 if ($src$$reg < 8) {
3010 emit_opcode(cbuf, Assembler::REX_WR);
3011 } else {
3012 emit_opcode(cbuf, Assembler::REX_WRB);
3013 }
3014 }
3015 %}
3016
3017 enc_class REX_reg_mem(rRegI reg, memory mem)
3018 %{
3019 if ($reg$$reg < 8) {
3020 if ($mem$$base < 8) {
3021 if ($mem$$index >= 8) {
3022 emit_opcode(cbuf, Assembler::REX_X);
3023 }
3024 } else {
3025 if ($mem$$index < 8) {
3026 emit_opcode(cbuf, Assembler::REX_B);
3027 } else {
3028 emit_opcode(cbuf, Assembler::REX_XB);
3029 }
3030 }
3031 } else {
3032 if ($mem$$base < 8) {
3033 if ($mem$$index < 8) {
3034 emit_opcode(cbuf, Assembler::REX_R);
3035 } else {
3036 emit_opcode(cbuf, Assembler::REX_RX);
3037 }
3038 } else {
3039 if ($mem$$index < 8) {
3040 emit_opcode(cbuf, Assembler::REX_RB);
3041 } else {
3042 emit_opcode(cbuf, Assembler::REX_RXB);
3043 }
3044 }
3045 }
3046 %}
3047
3048 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
3049 %{
3050 if ($reg$$reg < 8) {
3051 if ($mem$$base < 8) {
3052 if ($mem$$index < 8) {
3053 emit_opcode(cbuf, Assembler::REX_W);
3054 } else {
3055 emit_opcode(cbuf, Assembler::REX_WX);
3056 }
3057 } else {
3058 if ($mem$$index < 8) {
3059 emit_opcode(cbuf, Assembler::REX_WB);
3060 } else {
3061 emit_opcode(cbuf, Assembler::REX_WXB);
3062 }
3063 }
3064 } else {
3065 if ($mem$$base < 8) {
3066 if ($mem$$index < 8) {
3067 emit_opcode(cbuf, Assembler::REX_WR);
3068 } else {
3069 emit_opcode(cbuf, Assembler::REX_WRX);
3070 }
3071 } else {
3072 if ($mem$$index < 8) {
3073 emit_opcode(cbuf, Assembler::REX_WRB);
3074 } else {
3075 emit_opcode(cbuf, Assembler::REX_WRXB);
3076 }
3077 }
3078 }
3079 %}
3080
3081 enc_class reg_mem(rRegI ereg, memory mem)
3082 %{
3083 // High registers handle in encode_RegMem
3084 int reg = $ereg$$reg;
3085 int base = $mem$$base;
3086 int index = $mem$$index;
3087 int scale = $mem$$scale;
3088 int disp = $mem$$disp;
3089 bool disp_is_oop = $mem->disp_is_oop();
3090
3091 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
3092 %}
3093
3094 enc_class RM_opc_mem(immI rm_opcode, memory mem)
3095 %{
3096 int rm_byte_opcode = $rm_opcode$$constant;
3097
3098 // High registers handle in encode_RegMem
3099 int base = $mem$$base;
3100 int index = $mem$$index;
3101 int scale = $mem$$scale;
3102 int displace = $mem$$disp;
3103
3104 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
3105 // working with static
3106 // globals
3107 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
3108 disp_is_oop);
3109 %}
3110
3111 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
3112 %{
3113 int reg_encoding = $dst$$reg;
3114 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
3115 int index = 0x04; // 0x04 indicates no index
3116 int scale = 0x00; // 0x00 indicates no scale
3117 int displace = $src1$$constant; // 0x00 indicates no displacement
3118 bool disp_is_oop = false;
3119 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
3120 disp_is_oop);
3121 %}
3122
3123 enc_class neg_reg(rRegI dst)
3124 %{
3125 int dstenc = $dst$$reg;
3126 if (dstenc >= 8) {
3127 emit_opcode(cbuf, Assembler::REX_B);
3128 dstenc -= 8;
3129 }
3130 // NEG $dst
3131 emit_opcode(cbuf, 0xF7);
3132 emit_rm(cbuf, 0x3, 0x03, dstenc);
3133 %}
3134
3135 enc_class neg_reg_wide(rRegI dst)
3136 %{
3137 int dstenc = $dst$$reg;
3138 if (dstenc < 8) {
3139 emit_opcode(cbuf, Assembler::REX_W);
3140 } else {
3141 emit_opcode(cbuf, Assembler::REX_WB);
3142 dstenc -= 8;
3143 }
3144 // NEG $dst
3145 emit_opcode(cbuf, 0xF7);
3146 emit_rm(cbuf, 0x3, 0x03, dstenc);
3147 %}
3148
3149 enc_class setLT_reg(rRegI dst)
3150 %{
3151 int dstenc = $dst$$reg;
3152 if (dstenc >= 8) {
3153 emit_opcode(cbuf, Assembler::REX_B);
3154 dstenc -= 8;
3155 } else if (dstenc >= 4) {
3156 emit_opcode(cbuf, Assembler::REX);
3157 }
3158 // SETLT $dst
3159 emit_opcode(cbuf, 0x0F);
3160 emit_opcode(cbuf, 0x9C);
3161 emit_rm(cbuf, 0x3, 0x0, dstenc);
3162 %}
3163
3164 enc_class setNZ_reg(rRegI dst)
3165 %{
3166 int dstenc = $dst$$reg;
3167 if (dstenc >= 8) {
3168 emit_opcode(cbuf, Assembler::REX_B);
3169 dstenc -= 8;
3170 } else if (dstenc >= 4) {
3171 emit_opcode(cbuf, Assembler::REX);
3172 }
3173 // SETNZ $dst
3174 emit_opcode(cbuf, 0x0F);
3175 emit_opcode(cbuf, 0x95);
3176 emit_rm(cbuf, 0x3, 0x0, dstenc);
3177 %}
3178
3179
3180 // Compare the lonogs and set -1, 0, or 1 into dst
3181 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
3182 %{
3183 int src1enc = $src1$$reg;
3184 int src2enc = $src2$$reg;
3185 int dstenc = $dst$$reg;
3186
3187 // cmpq $src1, $src2
3188 if (src1enc < 8) {
3189 if (src2enc < 8) {
3190 emit_opcode(cbuf, Assembler::REX_W);
3191 } else {
3192 emit_opcode(cbuf, Assembler::REX_WB);
3193 }
3194 } else {
3195 if (src2enc < 8) {
3196 emit_opcode(cbuf, Assembler::REX_WR);
3197 } else {
3198 emit_opcode(cbuf, Assembler::REX_WRB);
3199 }
3200 }
3201 emit_opcode(cbuf, 0x3B);
3202 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
3203
3204 // movl $dst, -1
3205 if (dstenc >= 8) {
3206 emit_opcode(cbuf, Assembler::REX_B);
3207 }
3208 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
3209 emit_d32(cbuf, -1);
3210
3211 // jl,s done
3212 emit_opcode(cbuf, 0x7C);
3213 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
3214
3215 // setne $dst
3216 if (dstenc >= 4) {
3217 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
3218 }
3219 emit_opcode(cbuf, 0x0F);
3220 emit_opcode(cbuf, 0x95);
3221 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
3222
3223 // movzbl $dst, $dst
3224 if (dstenc >= 4) {
3225 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
3226 }
3227 emit_opcode(cbuf, 0x0F);
3228 emit_opcode(cbuf, 0xB6);
3229 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
3230 %}
3231
3232 enc_class Push_ResultXD(regD dst) %{
3233 int dstenc = $dst$$reg;
3234
3235 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
3236
3237 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
3238 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
3239 if (dstenc >= 8) {
3240 emit_opcode(cbuf, Assembler::REX_R);
3241 }
3242 emit_opcode (cbuf, 0x0F );
3243 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
3244 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
3245
3246 // add rsp,8
3247 emit_opcode(cbuf, Assembler::REX_W);
3248 emit_opcode(cbuf,0x83);
3249 emit_rm(cbuf,0x3, 0x0, RSP_enc);
3250 emit_d8(cbuf,0x08);
3251 %}
3252
3253 enc_class Push_SrcXD(regD src) %{
3254 int srcenc = $src$$reg;
3255
3256 // subq rsp,#8
3257 emit_opcode(cbuf, Assembler::REX_W);
3258 emit_opcode(cbuf, 0x83);
3259 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3260 emit_d8(cbuf, 0x8);
3261
3262 // movsd [rsp],src
3263 emit_opcode(cbuf, 0xF2);
3264 if (srcenc >= 8) {
3265 emit_opcode(cbuf, Assembler::REX_R);
3266 }
3267 emit_opcode(cbuf, 0x0F);
3268 emit_opcode(cbuf, 0x11);
3269 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
3270
3271 // fldd [rsp]
3272 emit_opcode(cbuf, 0x66);
3273 emit_opcode(cbuf, 0xDD);
3274 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
3275 %}
3276
3277
3278 enc_class movq_ld(regD dst, memory mem) %{
3279 MacroAssembler _masm(&cbuf);
3280 __ movq($dst$$XMMRegister, $mem$$Address);
3281 %}
3282
3283 enc_class movq_st(memory mem, regD src) %{
3284 MacroAssembler _masm(&cbuf);
3285 __ movq($mem$$Address, $src$$XMMRegister);
3286 %}
3287
3288 enc_class pshufd_8x8(regF dst, regF src) %{
3289 MacroAssembler _masm(&cbuf);
3290
3291 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3292 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3293 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3294 %}
3295
3296 enc_class pshufd_4x16(regF dst, regF src) %{
3297 MacroAssembler _masm(&cbuf);
3298
3299 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3300 %}
3301
3302 enc_class pshufd(regD dst, regD src, int mode) %{
3303 MacroAssembler _masm(&cbuf);
3304
3305 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3306 %}
3307
3308 enc_class pxor(regD dst, regD src) %{
3309 MacroAssembler _masm(&cbuf);
3310
3311 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3312 %}
3313
3314 enc_class mov_i2x(regD dst, rRegI src) %{
3315 MacroAssembler _masm(&cbuf);
3316
3317 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3318 %}
3319
3320 // obj: object to lock
3321 // box: box address (header location) -- killed
3322 // tmp: rax -- killed
3323 // scr: rbx -- killed
3324 //
3325 // What follows is a direct transliteration of fast_lock() and fast_unlock()
3326 // from i486.ad. See that file for comments.
3327 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
3328 // use the shorter encoding. (Movl clears the high-order 32-bits).
3329
3330
3331 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
3332 %{
3333 Register objReg = as_Register((int)$obj$$reg);
3334 Register boxReg = as_Register((int)$box$$reg);
3335 Register tmpReg = as_Register($tmp$$reg);
3336 Register scrReg = as_Register($scr$$reg);
3337 MacroAssembler masm(&cbuf);
3338
3339 // Verify uniqueness of register assignments -- necessary but not sufficient
3340 assert (objReg != boxReg && objReg != tmpReg &&
3341 objReg != scrReg && tmpReg != scrReg, "invariant") ;
3342
3343 if (_counters != NULL) {
3344 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3345 }
3346 if (EmitSync & 1) {
3347 // Without cast to int32_t a movptr will destroy r10 which is typically obj
3348 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
3349 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
3350 } else
3351 if (EmitSync & 2) {
3352 Label DONE_LABEL;
3353 if (UseBiasedLocking) {
3354 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3355 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3356 }
3357 // QQQ was movl...
3358 masm.movptr(tmpReg, 0x1);
3359 masm.orptr(tmpReg, Address(objReg, 0));
3360 masm.movptr(Address(boxReg, 0), tmpReg);
3361 if (os::is_MP()) {
3362 masm.lock();
3363 }
3364 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3365 masm.jcc(Assembler::equal, DONE_LABEL);
3366
3367 // Recursive locking
3368 masm.subptr(tmpReg, rsp);
3369 masm.andptr(tmpReg, 7 - os::vm_page_size());
3370 masm.movptr(Address(boxReg, 0), tmpReg);
3371
3372 masm.bind(DONE_LABEL);
3373 masm.nop(); // avoid branch to branch
3374 } else {
3375 Label DONE_LABEL, IsInflated, Egress;
3376
3377 masm.movptr(tmpReg, Address(objReg, 0)) ;
3378 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
3379 masm.jcc (Assembler::notZero, IsInflated) ;
3380
3381 // it's stack-locked, biased or neutral
3382 // TODO: optimize markword triage order to reduce the number of
3383 // conditional branches in the most common cases.
3384 // Beware -- there's a subtle invariant that fetch of the markword
3385 // at [FETCH], below, will never observe a biased encoding (*101b).
3386 // If this invariant is not held we'll suffer exclusion (safety) failure.
3387
3388 if (UseBiasedLocking && !UseOptoBiasInlining) {
3389 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
3390 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3391 }
3392
3393 // was q will it destroy high?
3394 masm.orl (tmpReg, 1) ;
3395 masm.movptr(Address(boxReg, 0), tmpReg) ;
3396 if (os::is_MP()) { masm.lock(); }
3397 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3398 if (_counters != NULL) {
3399 masm.cond_inc32(Assembler::equal,
3400 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3401 }
3402 masm.jcc (Assembler::equal, DONE_LABEL);
3403
3404 // Recursive locking
3405 masm.subptr(tmpReg, rsp);
3406 masm.andptr(tmpReg, 7 - os::vm_page_size());
3407 masm.movptr(Address(boxReg, 0), tmpReg);
3408 if (_counters != NULL) {
3409 masm.cond_inc32(Assembler::equal,
3410 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3411 }
3412 masm.jmp (DONE_LABEL) ;
3413
3414 masm.bind (IsInflated) ;
3415 // It's inflated
3416
3417 // TODO: someday avoid the ST-before-CAS penalty by
3418 // relocating (deferring) the following ST.
3419 // We should also think about trying a CAS without having
3420 // fetched _owner. If the CAS is successful we may
3421 // avoid an RTO->RTS upgrade on the $line.
3422 // Without cast to int32_t a movptr will destroy r10 which is typically obj
3423 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
3424
3425 masm.mov (boxReg, tmpReg) ;
3426 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3427 masm.testptr(tmpReg, tmpReg) ;
3428 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3429
3430 // It's inflated and appears unlocked
3431 if (os::is_MP()) { masm.lock(); }
3432 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3433 // Intentional fall-through into DONE_LABEL ...
3434
3435 masm.bind (DONE_LABEL) ;
3436 masm.nop () ; // avoid jmp to jmp
3437 }
3438 %}
3439
3440 // obj: object to unlock
3441 // box: box address (displaced header location), killed
3442 // RBX: killed tmp; cannot be obj nor box
3443 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
3444 %{
3445
3446 Register objReg = as_Register($obj$$reg);
3447 Register boxReg = as_Register($box$$reg);
3448 Register tmpReg = as_Register($tmp$$reg);
3449 MacroAssembler masm(&cbuf);
3450
3451 if (EmitSync & 4) {
3452 masm.cmpptr(rsp, 0) ;
3453 } else
3454 if (EmitSync & 8) {
3455 Label DONE_LABEL;
3456 if (UseBiasedLocking) {
3457 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3458 }
3459
3460 // Check whether the displaced header is 0
3461 //(=> recursive unlock)
3462 masm.movptr(tmpReg, Address(boxReg, 0));
3463 masm.testptr(tmpReg, tmpReg);
3464 masm.jcc(Assembler::zero, DONE_LABEL);
3465
3466 // If not recursive lock, reset the header to displaced header
3467 if (os::is_MP()) {
3468 masm.lock();
3469 }
3470 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3471 masm.bind(DONE_LABEL);
3472 masm.nop(); // avoid branch to branch
3473 } else {
3474 Label DONE_LABEL, Stacked, CheckSucc ;
3475
3476 if (UseBiasedLocking && !UseOptoBiasInlining) {
3477 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3478 }
3479
3480 masm.movptr(tmpReg, Address(objReg, 0)) ;
3481 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
3482 masm.jcc (Assembler::zero, DONE_LABEL) ;
3483 masm.testl (tmpReg, 0x02) ;
3484 masm.jcc (Assembler::zero, Stacked) ;
3485
3486 // It's inflated
3487 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3488 masm.xorptr(boxReg, r15_thread) ;
3489 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3490 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3491 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3492 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3493 masm.jcc (Assembler::notZero, CheckSucc) ;
3494 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3495 masm.jmp (DONE_LABEL) ;
3496
3497 if ((EmitSync & 65536) == 0) {
3498 Label LSuccess, LGoSlowPath ;
3499 masm.bind (CheckSucc) ;
3500 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3501 masm.jcc (Assembler::zero, LGoSlowPath) ;
3502
3503 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
3504 // the explicit ST;MEMBAR combination, but masm doesn't currently support
3505 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
3506 // are all faster when the write buffer is populated.
3507 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3508 if (os::is_MP()) {
3509 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
3510 }
3511 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3512 masm.jcc (Assembler::notZero, LSuccess) ;
3513
3514 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
3515 if (os::is_MP()) { masm.lock(); }
3516 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3517 masm.jcc (Assembler::notEqual, LSuccess) ;
3518 // Intentional fall-through into slow-path
3519
3520 masm.bind (LGoSlowPath) ;
3521 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3522 masm.jmp (DONE_LABEL) ;
3523
3524 masm.bind (LSuccess) ;
3525 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
3526 masm.jmp (DONE_LABEL) ;
3527 }
3528
3529 masm.bind (Stacked) ;
3530 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
3531 if (os::is_MP()) { masm.lock(); }
3532 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3533
3534 if (EmitSync & 65536) {
3535 masm.bind (CheckSucc) ;
3536 }
3537 masm.bind(DONE_LABEL);
3538 if (EmitSync & 32768) {
3539 masm.nop(); // avoid branch to branch
3540 }
3541 }
3542 %}
3543
3544
3545 enc_class enc_rethrow()
3546 %{
3547 cbuf.set_insts_mark();
3548 emit_opcode(cbuf, 0xE9); // jmp entry
3549 emit_d32_reloc(cbuf,
3550 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
3551 runtime_call_Relocation::spec(),
3552 RELOC_DISP32);
3553 %}
3554
3555 enc_class absF_encoding(regF dst)
3556 %{
3557 int dstenc = $dst$$reg;
3558 address signmask_address = (address) StubRoutines::x86::float_sign_mask();
3559
3560 cbuf.set_insts_mark();
3561 if (dstenc >= 8) {
3562 emit_opcode(cbuf, Assembler::REX_R);
3563 dstenc -= 8;
3564 }
3565 // XXX reg_mem doesn't support RIP-relative addressing yet
3566 emit_opcode(cbuf, 0x0F);
3567 emit_opcode(cbuf, 0x54);
3568 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3569 emit_d32_reloc(cbuf, signmask_address);
3570 %}
3571
3572 enc_class absD_encoding(regD dst)
3573 %{
3574 int dstenc = $dst$$reg;
3575 address signmask_address = (address) StubRoutines::x86::double_sign_mask();
3576
3577 cbuf.set_insts_mark();
3578 emit_opcode(cbuf, 0x66);
3579 if (dstenc >= 8) {
3580 emit_opcode(cbuf, Assembler::REX_R);
3581 dstenc -= 8;
3582 }
3583 // XXX reg_mem doesn't support RIP-relative addressing yet
3584 emit_opcode(cbuf, 0x0F);
3585 emit_opcode(cbuf, 0x54);
3586 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3587 emit_d32_reloc(cbuf, signmask_address);
3588 %}
3589
3590 enc_class negF_encoding(regF dst)
3591 %{
3592 int dstenc = $dst$$reg;
3593 address signflip_address = (address) StubRoutines::x86::float_sign_flip();
3594
3595 cbuf.set_insts_mark();
3596 if (dstenc >= 8) {
3597 emit_opcode(cbuf, Assembler::REX_R);
3598 dstenc -= 8;
3599 }
3600 // XXX reg_mem doesn't support RIP-relative addressing yet
3601 emit_opcode(cbuf, 0x0F);
3602 emit_opcode(cbuf, 0x57);
3603 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3604 emit_d32_reloc(cbuf, signflip_address);
3605 %}
3606
3607 enc_class negD_encoding(regD dst)
3608 %{
3609 int dstenc = $dst$$reg;
3610 address signflip_address = (address) StubRoutines::x86::double_sign_flip();
3611
3612 cbuf.set_insts_mark();
3613 emit_opcode(cbuf, 0x66);
3614 if (dstenc >= 8) {
3615 emit_opcode(cbuf, Assembler::REX_R);
3616 dstenc -= 8;
3617 }
3618 // XXX reg_mem doesn't support RIP-relative addressing yet
3619 emit_opcode(cbuf, 0x0F);
3620 emit_opcode(cbuf, 0x57);
3621 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3622 emit_d32_reloc(cbuf, signflip_address);
3623 %}
3624
3625 enc_class f2i_fixup(rRegI dst, regF src)
3626 %{
3627 int dstenc = $dst$$reg;
3628 int srcenc = $src$$reg;
3629
3630 // cmpl $dst, #0x80000000
3631 if (dstenc >= 8) {
3632 emit_opcode(cbuf, Assembler::REX_B);
3633 }
3634 emit_opcode(cbuf, 0x81);
3635 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
3636 emit_d32(cbuf, 0x80000000);
3637
3638 // jne,s done
3639 emit_opcode(cbuf, 0x75);
3640 if (srcenc < 8 && dstenc < 8) {
3641 emit_d8(cbuf, 0xF);
3642 } else if (srcenc >= 8 && dstenc >= 8) {
3643 emit_d8(cbuf, 0x11);
3644 } else {
3645 emit_d8(cbuf, 0x10);
3646 }
3647
3648 // subq rsp, #8
3649 emit_opcode(cbuf, Assembler::REX_W);
3650 emit_opcode(cbuf, 0x83);
3651 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3652 emit_d8(cbuf, 8);
3653
3654 // movss [rsp], $src
3655 emit_opcode(cbuf, 0xF3);
3656 if (srcenc >= 8) {
3657 emit_opcode(cbuf, Assembler::REX_R);
3658 }
3659 emit_opcode(cbuf, 0x0F);
3660 emit_opcode(cbuf, 0x11);
3661 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
3662
3663 // call f2i_fixup
3664 cbuf.set_insts_mark();
3665 emit_opcode(cbuf, 0xE8);
3666 emit_d32_reloc(cbuf,
3667 (int)
3668 (StubRoutines::x86::f2i_fixup() - cbuf.insts_end() - 4),
3669 runtime_call_Relocation::spec(),
3670 RELOC_DISP32);
3671
3672 // popq $dst
3673 if (dstenc >= 8) {
3674 emit_opcode(cbuf, Assembler::REX_B);
3675 }
3676 emit_opcode(cbuf, 0x58 | (dstenc & 7));
3677
3678 // done:
3679 %}
3680
3681 enc_class f2l_fixup(rRegL dst, regF src)
3682 %{
3683 int dstenc = $dst$$reg;
3684 int srcenc = $src$$reg;
3685 address const_address = (address) StubRoutines::x86::double_sign_flip();
3686
3687 // cmpq $dst, [0x8000000000000000]
3688 cbuf.set_insts_mark();
3689 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
3690 emit_opcode(cbuf, 0x39);
3691 // XXX reg_mem doesn't support RIP-relative addressing yet
3692 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
3693 emit_d32_reloc(cbuf, const_address);
3694
3695
3696 // jne,s done
3697 emit_opcode(cbuf, 0x75);
3698 if (srcenc < 8 && dstenc < 8) {
3699 emit_d8(cbuf, 0xF);
3700 } else if (srcenc >= 8 && dstenc >= 8) {
3701 emit_d8(cbuf, 0x11);
3702 } else {
3703 emit_d8(cbuf, 0x10);
3704 }
3705
3706 // subq rsp, #8
3707 emit_opcode(cbuf, Assembler::REX_W);
3708 emit_opcode(cbuf, 0x83);
3709 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3710 emit_d8(cbuf, 8);
3711
3712 // movss [rsp], $src
3713 emit_opcode(cbuf, 0xF3);
3714 if (srcenc >= 8) {
3715 emit_opcode(cbuf, Assembler::REX_R);
3716 }
3717 emit_opcode(cbuf, 0x0F);
3718 emit_opcode(cbuf, 0x11);
3719 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
3720
3721 // call f2l_fixup
3722 cbuf.set_insts_mark();
3723 emit_opcode(cbuf, 0xE8);
3724 emit_d32_reloc(cbuf,
3725 (int)
3726 (StubRoutines::x86::f2l_fixup() - cbuf.insts_end() - 4),
3727 runtime_call_Relocation::spec(),
3728 RELOC_DISP32);
3729
3730 // popq $dst
3731 if (dstenc >= 8) {
3732 emit_opcode(cbuf, Assembler::REX_B);
3733 }
3734 emit_opcode(cbuf, 0x58 | (dstenc & 7));
3735
3736 // done:
3737 %}
3738
3739 enc_class d2i_fixup(rRegI dst, regD src)
3740 %{
3741 int dstenc = $dst$$reg;
3742 int srcenc = $src$$reg;
3743
3744 // cmpl $dst, #0x80000000
3745 if (dstenc >= 8) {
3746 emit_opcode(cbuf, Assembler::REX_B);
3747 }
3748 emit_opcode(cbuf, 0x81);
3749 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
3750 emit_d32(cbuf, 0x80000000);
3751
3752 // jne,s done
3753 emit_opcode(cbuf, 0x75);
3754 if (srcenc < 8 && dstenc < 8) {
3755 emit_d8(cbuf, 0xF);
3756 } else if (srcenc >= 8 && dstenc >= 8) {
3757 emit_d8(cbuf, 0x11);
3758 } else {
3759 emit_d8(cbuf, 0x10);
3760 }
3761
3762 // subq rsp, #8
3763 emit_opcode(cbuf, Assembler::REX_W);
3764 emit_opcode(cbuf, 0x83);
3765 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3766 emit_d8(cbuf, 8);
3767
3768 // movsd [rsp], $src
3769 emit_opcode(cbuf, 0xF2);
3770 if (srcenc >= 8) {
3771 emit_opcode(cbuf, Assembler::REX_R);
3772 }
3773 emit_opcode(cbuf, 0x0F);
3774 emit_opcode(cbuf, 0x11);
3775 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
3776
3777 // call d2i_fixup
3778 cbuf.set_insts_mark();
3779 emit_opcode(cbuf, 0xE8);
3780 emit_d32_reloc(cbuf,
3781 (int)
3782 (StubRoutines::x86::d2i_fixup() - cbuf.insts_end() - 4),
3783 runtime_call_Relocation::spec(),
3784 RELOC_DISP32);
3785
3786 // popq $dst
3787 if (dstenc >= 8) {
3788 emit_opcode(cbuf, Assembler::REX_B);
3789 }
3790 emit_opcode(cbuf, 0x58 | (dstenc & 7));
3791
3792 // done:
3793 %}
3794
3795 enc_class d2l_fixup(rRegL dst, regD src)
3796 %{
3797 int dstenc = $dst$$reg;
3798 int srcenc = $src$$reg;
3799 address const_address = (address) StubRoutines::x86::double_sign_flip();
3800
3801 // cmpq $dst, [0x8000000000000000]
3802 cbuf.set_insts_mark();
3803 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
3804 emit_opcode(cbuf, 0x39);
3805 // XXX reg_mem doesn't support RIP-relative addressing yet
3806 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
3807 emit_d32_reloc(cbuf, const_address);
3808
3809
3810 // jne,s done
3811 emit_opcode(cbuf, 0x75);
3812 if (srcenc < 8 && dstenc < 8) {
3813 emit_d8(cbuf, 0xF);
3814 } else if (srcenc >= 8 && dstenc >= 8) {
3815 emit_d8(cbuf, 0x11);
3816 } else {
3817 emit_d8(cbuf, 0x10);
3818 }
3819
3820 // subq rsp, #8
3821 emit_opcode(cbuf, Assembler::REX_W);
3822 emit_opcode(cbuf, 0x83);
3823 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3824 emit_d8(cbuf, 8);
3825
3826 // movsd [rsp], $src
3827 emit_opcode(cbuf, 0xF2);
3828 if (srcenc >= 8) {
3829 emit_opcode(cbuf, Assembler::REX_R);
3830 }
3831 emit_opcode(cbuf, 0x0F);
3832 emit_opcode(cbuf, 0x11);
3833 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
3834
3835 // call d2l_fixup
3836 cbuf.set_insts_mark();
3837 emit_opcode(cbuf, 0xE8);
3838 emit_d32_reloc(cbuf,
3839 (int)
3840 (StubRoutines::x86::d2l_fixup() - cbuf.insts_end() - 4),
3841 runtime_call_Relocation::spec(),
3842 RELOC_DISP32);
3843
3844 // popq $dst
3845 if (dstenc >= 8) {
3846 emit_opcode(cbuf, Assembler::REX_B);
3847 }
3848 emit_opcode(cbuf, 0x58 | (dstenc & 7));
3849
3850 // done:
3851 %}
3852 %}
3853
3854
3855
3856 //----------FRAME--------------------------------------------------------------
3857 // Definition of frame structure and management information.
3858 //
3859 // S T A C K L A Y O U T Allocators stack-slot number
3860 // | (to get allocators register number
3861 // G Owned by | | v add OptoReg::stack0())
3862 // r CALLER | |
3863 // o | +--------+ pad to even-align allocators stack-slot
3864 // w V | pad0 | numbers; owned by CALLER
3865 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3866 // h ^ | in | 5
3867 // | | args | 4 Holes in incoming args owned by SELF
3868 // | | | | 3
3869 // | | +--------+
3870 // V | | old out| Empty on Intel, window on Sparc
3871 // | old |preserve| Must be even aligned.
3872 // | SP-+--------+----> Matcher::_old_SP, even aligned
3873 // | | in | 3 area for Intel ret address
3874 // Owned by |preserve| Empty on Sparc.
3875 // SELF +--------+
3876 // | | pad2 | 2 pad to align old SP
3877 // | +--------+ 1
3878 // | | locks | 0
3879 // | +--------+----> OptoReg::stack0(), even aligned
3880 // | | pad1 | 11 pad to align new SP
3881 // | +--------+
3882 // | | | 10
3883 // | | spills | 9 spills
3884 // V | | 8 (pad0 slot for callee)
3885 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3886 // ^ | out | 7
3887 // | | args | 6 Holes in outgoing args owned by CALLEE
3888 // Owned by +--------+
3889 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3890 // | new |preserve| Must be even-aligned.
3891 // | SP-+--------+----> Matcher::_new_SP, even aligned
3892 // | | |
3893 //
3894 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3895 // known from SELF's arguments and the Java calling convention.
3896 // Region 6-7 is determined per call site.
3897 // Note 2: If the calling convention leaves holes in the incoming argument
3898 // area, those holes are owned by SELF. Holes in the outgoing area
3899 // are owned by the CALLEE. Holes should not be nessecary in the
3900 // incoming area, as the Java calling convention is completely under
3901 // the control of the AD file. Doubles can be sorted and packed to
3902 // avoid holes. Holes in the outgoing arguments may be nessecary for
3903 // varargs C calling conventions.
3904 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3905 // even aligned with pad0 as needed.
3906 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3907 // region 6-11 is even aligned; it may be padded out more so that
3908 // the region from SP to FP meets the minimum stack alignment.
3909 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
3910 // alignment. Region 11, pad1, may be dynamically extended so that
3911 // SP meets the minimum alignment.
3912
3913 frame
3914 %{
3915 // What direction does stack grow in (assumed to be same for C & Java)
3916 stack_direction(TOWARDS_LOW);
3917
3918 // These three registers define part of the calling convention
3919 // between compiled code and the interpreter.
3920 inline_cache_reg(RAX); // Inline Cache Register
3921 interpreter_method_oop_reg(RBX); // Method Oop Register when
3922 // calling interpreter
3923
3924 // Optional: name the operand used by cisc-spilling to access
3925 // [stack_pointer + offset]
3926 cisc_spilling_operand_name(indOffset32);
3927
3928 // Number of stack slots consumed by locking an object
3929 sync_stack_slots(2);
3930
3931 // Compiled code's Frame Pointer
3932 frame_pointer(RSP);
3933
3934 // Interpreter stores its frame pointer in a register which is
3935 // stored to the stack by I2CAdaptors.
3936 // I2CAdaptors convert from interpreted java to compiled java.
3937 interpreter_frame_pointer(RBP);
3938
3939 // Stack alignment requirement
3940 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
3941
3942 // Number of stack slots between incoming argument block and the start of
3943 // a new frame. The PROLOG must add this many slots to the stack. The
3944 // EPILOG must remove this many slots. amd64 needs two slots for
3945 // return address.
3946 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
3947
3948 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3949 // for calls to C. Supports the var-args backing area for register parms.
3950 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
3951
3952 // The after-PROLOG location of the return address. Location of
3953 // return address specifies a type (REG or STACK) and a number
3954 // representing the register number (i.e. - use a register name) or
3955 // stack slot.
3956 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3957 // Otherwise, it is above the locks and verification slot and alignment word
3958 return_addr(STACK - 2 +
3959 round_to(2 + 2 * VerifyStackAtCalls +
3960 Compile::current()->fixed_slots(),
3961 WordsPerLong * 2));
3962
3963 // Body of function which returns an integer array locating
3964 // arguments either in registers or in stack slots. Passed an array
3965 // of ideal registers called "sig" and a "length" count. Stack-slot
3966 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3967 // arguments for a CALLEE. Incoming stack arguments are
3968 // automatically biased by the preserve_stack_slots field above.
3969
3970 calling_convention
3971 %{
3972 // No difference between ingoing/outgoing just pass false
3973 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3974 %}
3975
3976 c_calling_convention
3977 %{
3978 // This is obviously always outgoing
3979 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3980 %}
3981
3982 // Location of compiled Java return values. Same as C for now.
3983 return_value
3984 %{
3985 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
3986 "only return normal values");
3987
3988 static const int lo[Op_RegL + 1] = {
3989 0,
3990 0,
3991 RAX_num, // Op_RegN
3992 RAX_num, // Op_RegI
3993 RAX_num, // Op_RegP
3994 XMM0_num, // Op_RegF
3995 XMM0_num, // Op_RegD
3996 RAX_num // Op_RegL
3997 };
3998 static const int hi[Op_RegL + 1] = {
3999 0,
4000 0,
4001 OptoReg::Bad, // Op_RegN
4002 OptoReg::Bad, // Op_RegI
4003 RAX_H_num, // Op_RegP
4004 OptoReg::Bad, // Op_RegF
4005 XMM0_H_num, // Op_RegD
4006 RAX_H_num // Op_RegL
4007 };
4008 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type");
4009 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
4010 %}
4011 %}
4012
4013 //----------ATTRIBUTES---------------------------------------------------------
4014 //----------Operand Attributes-------------------------------------------------
4015 op_attrib op_cost(0); // Required cost attribute
4016
4017 //----------Instruction Attributes---------------------------------------------
4018 ins_attrib ins_cost(100); // Required cost attribute
4019 ins_attrib ins_size(8); // Required size attribute (in bits)
4020 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4021 ins_attrib ins_short_branch(0); // Required flag: is this instruction
4022 // a non-matching short branch variant
4023 // of some long branch?
4024 ins_attrib ins_alignment(1); // Required alignment attribute (must
4025 // be a power of 2) specifies the
4026 // alignment that some part of the
4027 // instruction (not necessarily the
4028 // start) requires. If > 1, a
4029 // compute_padding() function must be
4030 // provided for the instruction
4031
4032 //----------OPERANDS-----------------------------------------------------------
4033 // Operand definitions must precede instruction definitions for correct parsing
4034 // in the ADLC because operands constitute user defined types which are used in
4035 // instruction definitions.
4036
4037 //----------Simple Operands----------------------------------------------------
4038 // Immediate Operands
4039 // Integer Immediate
4040 operand immI()
4041 %{
4042 match(ConI);
4043
4044 op_cost(10);
4045 format %{ %}
4046 interface(CONST_INTER);
4047 %}
4048
4049 // Constant for test vs zero
4050 operand immI0()
4051 %{
4052 predicate(n->get_int() == 0);
4053 match(ConI);
4054
4055 op_cost(0);
4056 format %{ %}
4057 interface(CONST_INTER);
4058 %}
4059
4060 // Constant for increment
4061 operand immI1()
4062 %{
4063 predicate(n->get_int() == 1);
4064 match(ConI);
4065
4066 op_cost(0);
4067 format %{ %}
4068 interface(CONST_INTER);
4069 %}
4070
4071 // Constant for decrement
4072 operand immI_M1()
4073 %{
4074 predicate(n->get_int() == -1);
4075 match(ConI);
4076
4077 op_cost(0);
4078 format %{ %}
4079 interface(CONST_INTER);
4080 %}
4081
4082 // Valid scale values for addressing modes
4083 operand immI2()
4084 %{
4085 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4086 match(ConI);
4087
4088 format %{ %}
4089 interface(CONST_INTER);
4090 %}
4091
4092 operand immI8()
4093 %{
4094 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
4095 match(ConI);
4096
4097 op_cost(5);
4098 format %{ %}
4099 interface(CONST_INTER);
4100 %}
4101
4102 operand immI16()
4103 %{
4104 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4105 match(ConI);
4106
4107 op_cost(10);
4108 format %{ %}
4109 interface(CONST_INTER);
4110 %}
4111
4112 // Constant for long shifts
4113 operand immI_32()
4114 %{
4115 predicate( n->get_int() == 32 );
4116 match(ConI);
4117
4118 op_cost(0);
4119 format %{ %}
4120 interface(CONST_INTER);
4121 %}
4122
4123 // Constant for long shifts
4124 operand immI_64()
4125 %{
4126 predicate( n->get_int() == 64 );
4127 match(ConI);
4128
4129 op_cost(0);
4130 format %{ %}
4131 interface(CONST_INTER);
4132 %}
4133
4134 // Pointer Immediate
4135 operand immP()
4136 %{
4137 match(ConP);
4138
4139 op_cost(10);
4140 format %{ %}
4141 interface(CONST_INTER);
4142 %}
4143
4144 // NULL Pointer Immediate
4145 operand immP0()
4146 %{
4147 predicate(n->get_ptr() == 0);
4148 match(ConP);
4149
4150 op_cost(5);
4151 format %{ %}
4152 interface(CONST_INTER);
4153 %}
4154
4155 operand immP_poll() %{
4156 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
4157 match(ConP);
4158
4159 // formats are generated automatically for constants and base registers
4160 format %{ %}
4161 interface(CONST_INTER);
4162 %}
4163
4164 // Pointer Immediate
4165 operand immN() %{
4166 match(ConN);
4167
4168 op_cost(10);
4169 format %{ %}
4170 interface(CONST_INTER);
4171 %}
4172
4173 // NULL Pointer Immediate
4174 operand immN0() %{
4175 predicate(n->get_narrowcon() == 0);
4176 match(ConN);
4177
4178 op_cost(5);
4179 format %{ %}
4180 interface(CONST_INTER);
4181 %}
4182
4183 operand immP31()
4184 %{
4185 predicate(!n->as_Type()->type()->isa_oopptr()
4186 && (n->get_ptr() >> 31) == 0);
4187 match(ConP);
4188
4189 op_cost(5);
4190 format %{ %}
4191 interface(CONST_INTER);
4192 %}
4193
4194
4195 // Long Immediate
4196 operand immL()
4197 %{
4198 match(ConL);
4199
4200 op_cost(20);
4201 format %{ %}
4202 interface(CONST_INTER);
4203 %}
4204
4205 // Long Immediate 8-bit
4206 operand immL8()
4207 %{
4208 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
4209 match(ConL);
4210
4211 op_cost(5);
4212 format %{ %}
4213 interface(CONST_INTER);
4214 %}
4215
4216 // Long Immediate 32-bit unsigned
4217 operand immUL32()
4218 %{
4219 predicate(n->get_long() == (unsigned int) (n->get_long()));
4220 match(ConL);
4221
4222 op_cost(10);
4223 format %{ %}
4224 interface(CONST_INTER);
4225 %}
4226
4227 // Long Immediate 32-bit signed
4228 operand immL32()
4229 %{
4230 predicate(n->get_long() == (int) (n->get_long()));
4231 match(ConL);
4232
4233 op_cost(15);
4234 format %{ %}
4235 interface(CONST_INTER);
4236 %}
4237
4238 // Long Immediate zero
4239 operand immL0()
4240 %{
4241 predicate(n->get_long() == 0L);
4242 match(ConL);
4243
4244 op_cost(10);
4245 format %{ %}
4246 interface(CONST_INTER);
4247 %}
4248
4249 // Constant for increment
4250 operand immL1()
4251 %{
4252 predicate(n->get_long() == 1);
4253 match(ConL);
4254
4255 format %{ %}
4256 interface(CONST_INTER);
4257 %}
4258
4259 // Constant for decrement
4260 operand immL_M1()
4261 %{
4262 predicate(n->get_long() == -1);
4263 match(ConL);
4264
4265 format %{ %}
4266 interface(CONST_INTER);
4267 %}
4268
4269 // Long Immediate: the value 10
4270 operand immL10()
4271 %{
4272 predicate(n->get_long() == 10);
4273 match(ConL);
4274
4275 format %{ %}
4276 interface(CONST_INTER);
4277 %}
4278
4279 // Long immediate from 0 to 127.
4280 // Used for a shorter form of long mul by 10.
4281 operand immL_127()
4282 %{
4283 predicate(0 <= n->get_long() && n->get_long() < 0x80);
4284 match(ConL);
4285
4286 op_cost(10);
4287 format %{ %}
4288 interface(CONST_INTER);
4289 %}
4290
4291 // Long Immediate: low 32-bit mask
4292 operand immL_32bits()
4293 %{
4294 predicate(n->get_long() == 0xFFFFFFFFL);
4295 match(ConL);
4296 op_cost(20);
4297
4298 format %{ %}
4299 interface(CONST_INTER);
4300 %}
4301
4302 // Float Immediate zero
4303 operand immF0()
4304 %{
4305 predicate(jint_cast(n->getf()) == 0);
4306 match(ConF);
4307
4308 op_cost(5);
4309 format %{ %}
4310 interface(CONST_INTER);
4311 %}
4312
4313 // Float Immediate
4314 operand immF()
4315 %{
4316 match(ConF);
4317
4318 op_cost(15);
4319 format %{ %}
4320 interface(CONST_INTER);
4321 %}
4322
4323 // Double Immediate zero
4324 operand immD0()
4325 %{
4326 predicate(jlong_cast(n->getd()) == 0);
4327 match(ConD);
4328
4329 op_cost(5);
4330 format %{ %}
4331 interface(CONST_INTER);
4332 %}
4333
4334 // Double Immediate
4335 operand immD()
4336 %{
4337 match(ConD);
4338
4339 op_cost(15);
4340 format %{ %}
4341 interface(CONST_INTER);
4342 %}
4343
4344 // Immediates for special shifts (sign extend)
4345
4346 // Constants for increment
4347 operand immI_16()
4348 %{
4349 predicate(n->get_int() == 16);
4350 match(ConI);
4351
4352 format %{ %}
4353 interface(CONST_INTER);
4354 %}
4355
4356 operand immI_24()
4357 %{
4358 predicate(n->get_int() == 24);
4359 match(ConI);
4360
4361 format %{ %}
4362 interface(CONST_INTER);
4363 %}
4364
4365 // Constant for byte-wide masking
4366 operand immI_255()
4367 %{
4368 predicate(n->get_int() == 255);
4369 match(ConI);
4370
4371 format %{ %}
4372 interface(CONST_INTER);
4373 %}
4374
4375 // Constant for short-wide masking
4376 operand immI_65535()
4377 %{
4378 predicate(n->get_int() == 65535);
4379 match(ConI);
4380
4381 format %{ %}
4382 interface(CONST_INTER);
4383 %}
4384
4385 // Constant for byte-wide masking
4386 operand immL_255()
4387 %{
4388 predicate(n->get_long() == 255);
4389 match(ConL);
4390
4391 format %{ %}
4392 interface(CONST_INTER);
4393 %}
4394
4395 // Constant for short-wide masking
4396 operand immL_65535()
4397 %{
4398 predicate(n->get_long() == 65535);
4399 match(ConL);
4400
4401 format %{ %}
4402 interface(CONST_INTER);
4403 %}
4404
4405 // Register Operands
4406 // Integer Register
4407 operand rRegI()
4408 %{
4409 constraint(ALLOC_IN_RC(int_reg));
4410 match(RegI);
4411
4412 match(rax_RegI);
4413 match(rbx_RegI);
4414 match(rcx_RegI);
4415 match(rdx_RegI);
4416 match(rdi_RegI);
4417
4418 format %{ %}
4419 interface(REG_INTER);
4420 %}
4421
4422 // Special Registers
4423 operand rax_RegI()
4424 %{
4425 constraint(ALLOC_IN_RC(int_rax_reg));
4426 match(RegI);
4427 match(rRegI);
4428
4429 format %{ "RAX" %}
4430 interface(REG_INTER);
4431 %}
4432
4433 // Special Registers
4434 operand rbx_RegI()
4435 %{
4436 constraint(ALLOC_IN_RC(int_rbx_reg));
4437 match(RegI);
4438 match(rRegI);
4439
4440 format %{ "RBX" %}
4441 interface(REG_INTER);
4442 %}
4443
4444 operand rcx_RegI()
4445 %{
4446 constraint(ALLOC_IN_RC(int_rcx_reg));
4447 match(RegI);
4448 match(rRegI);
4449
4450 format %{ "RCX" %}
4451 interface(REG_INTER);
4452 %}
4453
4454 operand rdx_RegI()
4455 %{
4456 constraint(ALLOC_IN_RC(int_rdx_reg));
4457 match(RegI);
4458 match(rRegI);
4459
4460 format %{ "RDX" %}
4461 interface(REG_INTER);
4462 %}
4463
4464 operand rdi_RegI()
4465 %{
4466 constraint(ALLOC_IN_RC(int_rdi_reg));
4467 match(RegI);
4468 match(rRegI);
4469
4470 format %{ "RDI" %}
4471 interface(REG_INTER);
4472 %}
4473
4474 operand no_rcx_RegI()
4475 %{
4476 constraint(ALLOC_IN_RC(int_no_rcx_reg));
4477 match(RegI);
4478 match(rax_RegI);
4479 match(rbx_RegI);
4480 match(rdx_RegI);
4481 match(rdi_RegI);
4482
4483 format %{ %}
4484 interface(REG_INTER);
4485 %}
4486
4487 operand no_rax_rdx_RegI()
4488 %{
4489 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
4490 match(RegI);
4491 match(rbx_RegI);
4492 match(rcx_RegI);
4493 match(rdi_RegI);
4494
4495 format %{ %}
4496 interface(REG_INTER);
4497 %}
4498
4499 // Pointer Register
4500 operand any_RegP()
4501 %{
4502 constraint(ALLOC_IN_RC(any_reg));
4503 match(RegP);
4504 match(rax_RegP);
4505 match(rbx_RegP);
4506 match(rdi_RegP);
4507 match(rsi_RegP);
4508 match(rbp_RegP);
4509 match(r15_RegP);
4510 match(rRegP);
4511
4512 format %{ %}
4513 interface(REG_INTER);
4514 %}
4515
4516 operand rRegP()
4517 %{
4518 constraint(ALLOC_IN_RC(ptr_reg));
4519 match(RegP);
4520 match(rax_RegP);
4521 match(rbx_RegP);
4522 match(rdi_RegP);
4523 match(rsi_RegP);
4524 match(rbp_RegP);
4525 match(r15_RegP); // See Q&A below about r15_RegP.
4526
4527 format %{ %}
4528 interface(REG_INTER);
4529 %}
4530
4531 operand rRegN() %{
4532 constraint(ALLOC_IN_RC(int_reg));
4533 match(RegN);
4534
4535 format %{ %}
4536 interface(REG_INTER);
4537 %}
4538
4539 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
4540 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
4541 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
4542 // The output of an instruction is controlled by the allocator, which respects
4543 // register class masks, not match rules. Unless an instruction mentions
4544 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
4545 // by the allocator as an input.
4546
4547 operand no_rax_RegP()
4548 %{
4549 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
4550 match(RegP);
4551 match(rbx_RegP);
4552 match(rsi_RegP);
4553 match(rdi_RegP);
4554
4555 format %{ %}
4556 interface(REG_INTER);
4557 %}
4558
4559 operand no_rbp_RegP()
4560 %{
4561 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
4562 match(RegP);
4563 match(rbx_RegP);
4564 match(rsi_RegP);
4565 match(rdi_RegP);
4566
4567 format %{ %}
4568 interface(REG_INTER);
4569 %}
4570
4571 operand no_rax_rbx_RegP()
4572 %{
4573 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
4574 match(RegP);
4575 match(rsi_RegP);
4576 match(rdi_RegP);
4577
4578 format %{ %}
4579 interface(REG_INTER);
4580 %}
4581
4582 // Special Registers
4583 // Return a pointer value
4584 operand rax_RegP()
4585 %{
4586 constraint(ALLOC_IN_RC(ptr_rax_reg));
4587 match(RegP);
4588 match(rRegP);
4589
4590 format %{ %}
4591 interface(REG_INTER);
4592 %}
4593
4594 // Special Registers
4595 // Return a compressed pointer value
4596 operand rax_RegN()
4597 %{
4598 constraint(ALLOC_IN_RC(int_rax_reg));
4599 match(RegN);
4600 match(rRegN);
4601
4602 format %{ %}
4603 interface(REG_INTER);
4604 %}
4605
4606 // Used in AtomicAdd
4607 operand rbx_RegP()
4608 %{
4609 constraint(ALLOC_IN_RC(ptr_rbx_reg));
4610 match(RegP);
4611 match(rRegP);
4612
4613 format %{ %}
4614 interface(REG_INTER);
4615 %}
4616
4617 operand rsi_RegP()
4618 %{
4619 constraint(ALLOC_IN_RC(ptr_rsi_reg));
4620 match(RegP);
4621 match(rRegP);
4622
4623 format %{ %}
4624 interface(REG_INTER);
4625 %}
4626
4627 // Used in rep stosq
4628 operand rdi_RegP()
4629 %{
4630 constraint(ALLOC_IN_RC(ptr_rdi_reg));
4631 match(RegP);
4632 match(rRegP);
4633
4634 format %{ %}
4635 interface(REG_INTER);
4636 %}
4637
4638 operand rbp_RegP()
4639 %{
4640 constraint(ALLOC_IN_RC(ptr_rbp_reg));
4641 match(RegP);
4642 match(rRegP);
4643
4644 format %{ %}
4645 interface(REG_INTER);
4646 %}
4647
4648 operand r15_RegP()
4649 %{
4650 constraint(ALLOC_IN_RC(ptr_r15_reg));
4651 match(RegP);
4652 match(rRegP);
4653
4654 format %{ %}
4655 interface(REG_INTER);
4656 %}
4657
4658 operand rRegL()
4659 %{
4660 constraint(ALLOC_IN_RC(long_reg));
4661 match(RegL);
4662 match(rax_RegL);
4663 match(rdx_RegL);
4664
4665 format %{ %}
4666 interface(REG_INTER);
4667 %}
4668
4669 // Special Registers
4670 operand no_rax_rdx_RegL()
4671 %{
4672 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
4673 match(RegL);
4674 match(rRegL);
4675
4676 format %{ %}
4677 interface(REG_INTER);
4678 %}
4679
4680 operand no_rax_RegL()
4681 %{
4682 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
4683 match(RegL);
4684 match(rRegL);
4685 match(rdx_RegL);
4686
4687 format %{ %}
4688 interface(REG_INTER);
4689 %}
4690
4691 operand no_rcx_RegL()
4692 %{
4693 constraint(ALLOC_IN_RC(long_no_rcx_reg));
4694 match(RegL);
4695 match(rRegL);
4696
4697 format %{ %}
4698 interface(REG_INTER);
4699 %}
4700
4701 operand rax_RegL()
4702 %{
4703 constraint(ALLOC_IN_RC(long_rax_reg));
4704 match(RegL);
4705 match(rRegL);
4706
4707 format %{ "RAX" %}
4708 interface(REG_INTER);
4709 %}
4710
4711 operand rcx_RegL()
4712 %{
4713 constraint(ALLOC_IN_RC(long_rcx_reg));
4714 match(RegL);
4715 match(rRegL);
4716
4717 format %{ %}
4718 interface(REG_INTER);
4719 %}
4720
4721 operand rdx_RegL()
4722 %{
4723 constraint(ALLOC_IN_RC(long_rdx_reg));
4724 match(RegL);
4725 match(rRegL);
4726
4727 format %{ %}
4728 interface(REG_INTER);
4729 %}
4730
4731 // Flags register, used as output of compare instructions
4732 operand rFlagsReg()
4733 %{
4734 constraint(ALLOC_IN_RC(int_flags));
4735 match(RegFlags);
4736
4737 format %{ "RFLAGS" %}
4738 interface(REG_INTER);
4739 %}
4740
4741 // Flags register, used as output of FLOATING POINT compare instructions
4742 operand rFlagsRegU()
4743 %{
4744 constraint(ALLOC_IN_RC(int_flags));
4745 match(RegFlags);
4746
4747 format %{ "RFLAGS_U" %}
4748 interface(REG_INTER);
4749 %}
4750
4751 operand rFlagsRegUCF() %{
4752 constraint(ALLOC_IN_RC(int_flags));
4753 match(RegFlags);
4754 predicate(false);
4755
4756 format %{ "RFLAGS_U_CF" %}
4757 interface(REG_INTER);
4758 %}
4759
4760 // Float register operands
4761 operand regF()
4762 %{
4763 constraint(ALLOC_IN_RC(float_reg));
4764 match(RegF);
4765
4766 format %{ %}
4767 interface(REG_INTER);
4768 %}
4769
4770 // Double register operands
4771 operand regD()
4772 %{
4773 constraint(ALLOC_IN_RC(double_reg));
4774 match(RegD);
4775
4776 format %{ %}
4777 interface(REG_INTER);
4778 %}
4779
4780
4781 //----------Memory Operands----------------------------------------------------
4782 // Direct Memory Operand
4783 // operand direct(immP addr)
4784 // %{
4785 // match(addr);
4786
4787 // format %{ "[$addr]" %}
4788 // interface(MEMORY_INTER) %{
4789 // base(0xFFFFFFFF);
4790 // index(0x4);
4791 // scale(0x0);
4792 // disp($addr);
4793 // %}
4794 // %}
4795
4796 // Indirect Memory Operand
4797 operand indirect(any_RegP reg)
4798 %{
4799 constraint(ALLOC_IN_RC(ptr_reg));
4800 match(reg);
4801
4802 format %{ "[$reg]" %}
4803 interface(MEMORY_INTER) %{
4804 base($reg);
4805 index(0x4);
4806 scale(0x0);
4807 disp(0x0);
4808 %}
4809 %}
4810
4811 // Indirect Memory Plus Short Offset Operand
4812 operand indOffset8(any_RegP reg, immL8 off)
4813 %{
4814 constraint(ALLOC_IN_RC(ptr_reg));
4815 match(AddP reg off);
4816
4817 format %{ "[$reg + $off (8-bit)]" %}
4818 interface(MEMORY_INTER) %{
4819 base($reg);
4820 index(0x4);
4821 scale(0x0);
4822 disp($off);
4823 %}
4824 %}
4825
4826 // Indirect Memory Plus Long Offset Operand
4827 operand indOffset32(any_RegP reg, immL32 off)
4828 %{
4829 constraint(ALLOC_IN_RC(ptr_reg));
4830 match(AddP reg off);
4831
4832 format %{ "[$reg + $off (32-bit)]" %}
4833 interface(MEMORY_INTER) %{
4834 base($reg);
4835 index(0x4);
4836 scale(0x0);
4837 disp($off);
4838 %}
4839 %}
4840
4841 // Indirect Memory Plus Index Register Plus Offset Operand
4842 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
4843 %{
4844 constraint(ALLOC_IN_RC(ptr_reg));
4845 match(AddP (AddP reg lreg) off);
4846
4847 op_cost(10);
4848 format %{"[$reg + $off + $lreg]" %}
4849 interface(MEMORY_INTER) %{
4850 base($reg);
4851 index($lreg);
4852 scale(0x0);
4853 disp($off);
4854 %}
4855 %}
4856
4857 // Indirect Memory Plus Index Register Plus Offset Operand
4858 operand indIndex(any_RegP reg, rRegL lreg)
4859 %{
4860 constraint(ALLOC_IN_RC(ptr_reg));
4861 match(AddP reg lreg);
4862
4863 op_cost(10);
4864 format %{"[$reg + $lreg]" %}
4865 interface(MEMORY_INTER) %{
4866 base($reg);
4867 index($lreg);
4868 scale(0x0);
4869 disp(0x0);
4870 %}
4871 %}
4872
4873 // Indirect Memory Times Scale Plus Index Register
4874 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
4875 %{
4876 constraint(ALLOC_IN_RC(ptr_reg));
4877 match(AddP reg (LShiftL lreg scale));
4878
4879 op_cost(10);
4880 format %{"[$reg + $lreg << $scale]" %}
4881 interface(MEMORY_INTER) %{
4882 base($reg);
4883 index($lreg);
4884 scale($scale);
4885 disp(0x0);
4886 %}
4887 %}
4888
4889 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4890 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
4891 %{
4892 constraint(ALLOC_IN_RC(ptr_reg));
4893 match(AddP (AddP reg (LShiftL lreg scale)) off);
4894
4895 op_cost(10);
4896 format %{"[$reg + $off + $lreg << $scale]" %}
4897 interface(MEMORY_INTER) %{
4898 base($reg);
4899 index($lreg);
4900 scale($scale);
4901 disp($off);
4902 %}
4903 %}
4904
4905 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4906 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
4907 %{
4908 constraint(ALLOC_IN_RC(ptr_reg));
4909 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4910 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
4911
4912 op_cost(10);
4913 format %{"[$reg + $off + $idx << $scale]" %}
4914 interface(MEMORY_INTER) %{
4915 base($reg);
4916 index($idx);
4917 scale($scale);
4918 disp($off);
4919 %}
4920 %}
4921
4922 // Indirect Narrow Oop Plus Offset Operand
4923 // Note: x86 architecture doesn't support "scale * index + offset" without a base
4924 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
4925 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
4926 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
4927 constraint(ALLOC_IN_RC(ptr_reg));
4928 match(AddP (DecodeN reg) off);
4929
4930 op_cost(10);
4931 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
4932 interface(MEMORY_INTER) %{
4933 base(0xc); // R12
4934 index($reg);
4935 scale(0x3);
4936 disp($off);
4937 %}
4938 %}
4939
4940 // Indirect Memory Operand
4941 operand indirectNarrow(rRegN reg)
4942 %{
4943 predicate(Universe::narrow_oop_shift() == 0);
4944 constraint(ALLOC_IN_RC(ptr_reg));
4945 match(DecodeN reg);
4946
4947 format %{ "[$reg]" %}
4948 interface(MEMORY_INTER) %{
4949 base($reg);
4950 index(0x4);
4951 scale(0x0);
4952 disp(0x0);
4953 %}
4954 %}
4955
4956 // Indirect Memory Plus Short Offset Operand
4957 operand indOffset8Narrow(rRegN reg, immL8 off)
4958 %{
4959 predicate(Universe::narrow_oop_shift() == 0);
4960 constraint(ALLOC_IN_RC(ptr_reg));
4961 match(AddP (DecodeN reg) off);
4962
4963 format %{ "[$reg + $off (8-bit)]" %}
4964 interface(MEMORY_INTER) %{
4965 base($reg);
4966 index(0x4);
4967 scale(0x0);
4968 disp($off);
4969 %}
4970 %}
4971
4972 // Indirect Memory Plus Long Offset Operand
4973 operand indOffset32Narrow(rRegN reg, immL32 off)
4974 %{
4975 predicate(Universe::narrow_oop_shift() == 0);
4976 constraint(ALLOC_IN_RC(ptr_reg));
4977 match(AddP (DecodeN reg) off);
4978
4979 format %{ "[$reg + $off (32-bit)]" %}
4980 interface(MEMORY_INTER) %{
4981 base($reg);
4982 index(0x4);
4983 scale(0x0);
4984 disp($off);
4985 %}
4986 %}
4987
4988 // Indirect Memory Plus Index Register Plus Offset Operand
4989 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4990 %{
4991 predicate(Universe::narrow_oop_shift() == 0);
4992 constraint(ALLOC_IN_RC(ptr_reg));
4993 match(AddP (AddP (DecodeN reg) lreg) off);
4994
4995 op_cost(10);
4996 format %{"[$reg + $off + $lreg]" %}
4997 interface(MEMORY_INTER) %{
4998 base($reg);
4999 index($lreg);
5000 scale(0x0);
5001 disp($off);
5002 %}
5003 %}
5004
5005 // Indirect Memory Plus Index Register Plus Offset Operand
5006 operand indIndexNarrow(rRegN reg, rRegL lreg)
5007 %{
5008 predicate(Universe::narrow_oop_shift() == 0);
5009 constraint(ALLOC_IN_RC(ptr_reg));
5010 match(AddP (DecodeN reg) lreg);
5011
5012 op_cost(10);
5013 format %{"[$reg + $lreg]" %}
5014 interface(MEMORY_INTER) %{
5015 base($reg);
5016 index($lreg);
5017 scale(0x0);
5018 disp(0x0);
5019 %}
5020 %}
5021
5022 // Indirect Memory Times Scale Plus Index Register
5023 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
5024 %{
5025 predicate(Universe::narrow_oop_shift() == 0);
5026 constraint(ALLOC_IN_RC(ptr_reg));
5027 match(AddP (DecodeN reg) (LShiftL lreg scale));
5028
5029 op_cost(10);
5030 format %{"[$reg + $lreg << $scale]" %}
5031 interface(MEMORY_INTER) %{
5032 base($reg);
5033 index($lreg);
5034 scale($scale);
5035 disp(0x0);
5036 %}
5037 %}
5038
5039 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5040 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
5041 %{
5042 predicate(Universe::narrow_oop_shift() == 0);
5043 constraint(ALLOC_IN_RC(ptr_reg));
5044 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
5045
5046 op_cost(10);
5047 format %{"[$reg + $off + $lreg << $scale]" %}
5048 interface(MEMORY_INTER) %{
5049 base($reg);
5050 index($lreg);
5051 scale($scale);
5052 disp($off);
5053 %}
5054 %}
5055
5056 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
5057 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
5058 %{
5059 constraint(ALLOC_IN_RC(ptr_reg));
5060 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5061 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
5062
5063 op_cost(10);
5064 format %{"[$reg + $off + $idx << $scale]" %}
5065 interface(MEMORY_INTER) %{
5066 base($reg);
5067 index($idx);
5068 scale($scale);
5069 disp($off);
5070 %}
5071 %}
5072
5073
5074 //----------Special Memory Operands--------------------------------------------
5075 // Stack Slot Operand - This operand is used for loading and storing temporary
5076 // values on the stack where a match requires a value to
5077 // flow through memory.
5078 operand stackSlotP(sRegP reg)
5079 %{
5080 constraint(ALLOC_IN_RC(stack_slots));
5081 // No match rule because this operand is only generated in matching
5082
5083 format %{ "[$reg]" %}
5084 interface(MEMORY_INTER) %{
5085 base(0x4); // RSP
5086 index(0x4); // No Index
5087 scale(0x0); // No Scale
5088 disp($reg); // Stack Offset
5089 %}
5090 %}
5091
5092 operand stackSlotI(sRegI reg)
5093 %{
5094 constraint(ALLOC_IN_RC(stack_slots));
5095 // No match rule because this operand is only generated in matching
5096
5097 format %{ "[$reg]" %}
5098 interface(MEMORY_INTER) %{
5099 base(0x4); // RSP
5100 index(0x4); // No Index
5101 scale(0x0); // No Scale
5102 disp($reg); // Stack Offset
5103 %}
5104 %}
5105
5106 operand stackSlotF(sRegF reg)
5107 %{
5108 constraint(ALLOC_IN_RC(stack_slots));
5109 // No match rule because this operand is only generated in matching
5110
5111 format %{ "[$reg]" %}
5112 interface(MEMORY_INTER) %{
5113 base(0x4); // RSP
5114 index(0x4); // No Index
5115 scale(0x0); // No Scale
5116 disp($reg); // Stack Offset
5117 %}
5118 %}
5119
5120 operand stackSlotD(sRegD reg)
5121 %{
5122 constraint(ALLOC_IN_RC(stack_slots));
5123 // No match rule because this operand is only generated in matching
5124
5125 format %{ "[$reg]" %}
5126 interface(MEMORY_INTER) %{
5127 base(0x4); // RSP
5128 index(0x4); // No Index
5129 scale(0x0); // No Scale
5130 disp($reg); // Stack Offset
5131 %}
5132 %}
5133 operand stackSlotL(sRegL reg)
5134 %{
5135 constraint(ALLOC_IN_RC(stack_slots));
5136 // No match rule because this operand is only generated in matching
5137
5138 format %{ "[$reg]" %}
5139 interface(MEMORY_INTER) %{
5140 base(0x4); // RSP
5141 index(0x4); // No Index
5142 scale(0x0); // No Scale
5143 disp($reg); // Stack Offset
5144 %}
5145 %}
5146
5147 //----------Conditional Branch Operands----------------------------------------
5148 // Comparison Op - This is the operation of the comparison, and is limited to
5149 // the following set of codes:
5150 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5151 //
5152 // Other attributes of the comparison, such as unsignedness, are specified
5153 // by the comparison instruction that sets a condition code flags register.
5154 // That result is represented by a flags operand whose subtype is appropriate
5155 // to the unsignedness (etc.) of the comparison.
5156 //
5157 // Later, the instruction which matches both the Comparison Op (a Bool) and
5158 // the flags (produced by the Cmp) specifies the coding of the comparison op
5159 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5160
5161 // Comparision Code
5162 operand cmpOp()
5163 %{
5164 match(Bool);
5165
5166 format %{ "" %}
5167 interface(COND_INTER) %{
5168 equal(0x4, "e");
5169 not_equal(0x5, "ne");
5170 less(0xC, "l");
5171 greater_equal(0xD, "ge");
5172 less_equal(0xE, "le");
5173 greater(0xF, "g");
5174 %}
5175 %}
5176
5177 // Comparison Code, unsigned compare. Used by FP also, with
5178 // C2 (unordered) turned into GT or LT already. The other bits
5179 // C0 and C3 are turned into Carry & Zero flags.
5180 operand cmpOpU()
5181 %{
5182 match(Bool);
5183
5184 format %{ "" %}
5185 interface(COND_INTER) %{
5186 equal(0x4, "e");
5187 not_equal(0x5, "ne");
5188 less(0x2, "b");
5189 greater_equal(0x3, "nb");
5190 less_equal(0x6, "be");
5191 greater(0x7, "nbe");
5192 %}
5193 %}
5194
5195
5196 // Floating comparisons that don't require any fixup for the unordered case
5197 operand cmpOpUCF() %{
5198 match(Bool);
5199 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5200 n->as_Bool()->_test._test == BoolTest::ge ||
5201 n->as_Bool()->_test._test == BoolTest::le ||
5202 n->as_Bool()->_test._test == BoolTest::gt);
5203 format %{ "" %}
5204 interface(COND_INTER) %{
5205 equal(0x4, "e");
5206 not_equal(0x5, "ne");
5207 less(0x2, "b");
5208 greater_equal(0x3, "nb");
5209 less_equal(0x6, "be");
5210 greater(0x7, "nbe");
5211 %}
5212 %}
5213
5214
5215 // Floating comparisons that can be fixed up with extra conditional jumps
5216 operand cmpOpUCF2() %{
5217 match(Bool);
5218 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5219 n->as_Bool()->_test._test == BoolTest::eq);
5220 format %{ "" %}
5221 interface(COND_INTER) %{
5222 equal(0x4, "e");
5223 not_equal(0x5, "ne");
5224 less(0x2, "b");
5225 greater_equal(0x3, "nb");
5226 less_equal(0x6, "be");
5227 greater(0x7, "nbe");
5228 %}
5229 %}
5230
5231
5232 //----------OPERAND CLASSES----------------------------------------------------
5233 // Operand Classes are groups of operands that are used as to simplify
5234 // instruction definitions by not requiring the AD writer to specify separate
5235 // instructions for every form of operand when the instruction accepts
5236 // multiple operand types with the same basic encoding and format. The classic
5237 // case of this is memory operands.
5238
5239 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
5240 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
5241 indCompressedOopOffset,
5242 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
5243 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
5244 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
5245
5246 //----------PIPELINE-----------------------------------------------------------
5247 // Rules which define the behavior of the target architectures pipeline.
5248 pipeline %{
5249
5250 //----------ATTRIBUTES---------------------------------------------------------
5251 attributes %{
5252 variable_size_instructions; // Fixed size instructions
5253 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5254 instruction_unit_size = 1; // An instruction is 1 bytes long
5255 instruction_fetch_unit_size = 16; // The processor fetches one line
5256 instruction_fetch_units = 1; // of 16 bytes
5257
5258 // List of nop instructions
5259 nops( MachNop );
5260 %}
5261
5262 //----------RESOURCES----------------------------------------------------------
5263 // Resources are the functional units available to the machine
5264
5265 // Generic P2/P3 pipeline
5266 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5267 // 3 instructions decoded per cycle.
5268 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5269 // 3 ALU op, only ALU0 handles mul instructions.
5270 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5271 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
5272 BR, FPU,
5273 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
5274
5275 //----------PIPELINE DESCRIPTION-----------------------------------------------
5276 // Pipeline Description specifies the stages in the machine's pipeline
5277
5278 // Generic P2/P3 pipeline
5279 pipe_desc(S0, S1, S2, S3, S4, S5);
5280
5281 //----------PIPELINE CLASSES---------------------------------------------------
5282 // Pipeline Classes describe the stages in which input and output are
5283 // referenced by the hardware pipeline.
5284
5285 // Naming convention: ialu or fpu
5286 // Then: _reg
5287 // Then: _reg if there is a 2nd register
5288 // Then: _long if it's a pair of instructions implementing a long
5289 // Then: _fat if it requires the big decoder
5290 // Or: _mem if it requires the big decoder and a memory unit.
5291
5292 // Integer ALU reg operation
5293 pipe_class ialu_reg(rRegI dst)
5294 %{
5295 single_instruction;
5296 dst : S4(write);
5297 dst : S3(read);
5298 DECODE : S0; // any decoder
5299 ALU : S3; // any alu
5300 %}
5301
5302 // Long ALU reg operation
5303 pipe_class ialu_reg_long(rRegL dst)
5304 %{
5305 instruction_count(2);
5306 dst : S4(write);
5307 dst : S3(read);
5308 DECODE : S0(2); // any 2 decoders
5309 ALU : S3(2); // both alus
5310 %}
5311
5312 // Integer ALU reg operation using big decoder
5313 pipe_class ialu_reg_fat(rRegI dst)
5314 %{
5315 single_instruction;
5316 dst : S4(write);
5317 dst : S3(read);
5318 D0 : S0; // big decoder only
5319 ALU : S3; // any alu
5320 %}
5321
5322 // Long ALU reg operation using big decoder
5323 pipe_class ialu_reg_long_fat(rRegL dst)
5324 %{
5325 instruction_count(2);
5326 dst : S4(write);
5327 dst : S3(read);
5328 D0 : S0(2); // big decoder only; twice
5329 ALU : S3(2); // any 2 alus
5330 %}
5331
5332 // Integer ALU reg-reg operation
5333 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
5334 %{
5335 single_instruction;
5336 dst : S4(write);
5337 src : S3(read);
5338 DECODE : S0; // any decoder
5339 ALU : S3; // any alu
5340 %}
5341
5342 // Long ALU reg-reg operation
5343 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
5344 %{
5345 instruction_count(2);
5346 dst : S4(write);
5347 src : S3(read);
5348 DECODE : S0(2); // any 2 decoders
5349 ALU : S3(2); // both alus
5350 %}
5351
5352 // Integer ALU reg-reg operation
5353 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
5354 %{
5355 single_instruction;
5356 dst : S4(write);
5357 src : S3(read);
5358 D0 : S0; // big decoder only
5359 ALU : S3; // any alu
5360 %}
5361
5362 // Long ALU reg-reg operation
5363 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
5364 %{
5365 instruction_count(2);
5366 dst : S4(write);
5367 src : S3(read);
5368 D0 : S0(2); // big decoder only; twice
5369 ALU : S3(2); // both alus
5370 %}
5371
5372 // Integer ALU reg-mem operation
5373 pipe_class ialu_reg_mem(rRegI dst, memory mem)
5374 %{
5375 single_instruction;
5376 dst : S5(write);
5377 mem : S3(read);
5378 D0 : S0; // big decoder only
5379 ALU : S4; // any alu
5380 MEM : S3; // any mem
5381 %}
5382
5383 // Integer mem operation (prefetch)
5384 pipe_class ialu_mem(memory mem)
5385 %{
5386 single_instruction;
5387 mem : S3(read);
5388 D0 : S0; // big decoder only
5389 MEM : S3; // any mem
5390 %}
5391
5392 // Integer Store to Memory
5393 pipe_class ialu_mem_reg(memory mem, rRegI src)
5394 %{
5395 single_instruction;
5396 mem : S3(read);
5397 src : S5(read);
5398 D0 : S0; // big decoder only
5399 ALU : S4; // any alu
5400 MEM : S3;
5401 %}
5402
5403 // // Long Store to Memory
5404 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
5405 // %{
5406 // instruction_count(2);
5407 // mem : S3(read);
5408 // src : S5(read);
5409 // D0 : S0(2); // big decoder only; twice
5410 // ALU : S4(2); // any 2 alus
5411 // MEM : S3(2); // Both mems
5412 // %}
5413
5414 // Integer Store to Memory
5415 pipe_class ialu_mem_imm(memory mem)
5416 %{
5417 single_instruction;
5418 mem : S3(read);
5419 D0 : S0; // big decoder only
5420 ALU : S4; // any alu
5421 MEM : S3;
5422 %}
5423
5424 // Integer ALU0 reg-reg operation
5425 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
5426 %{
5427 single_instruction;
5428 dst : S4(write);
5429 src : S3(read);
5430 D0 : S0; // Big decoder only
5431 ALU0 : S3; // only alu0
5432 %}
5433
5434 // Integer ALU0 reg-mem operation
5435 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
5436 %{
5437 single_instruction;
5438 dst : S5(write);
5439 mem : S3(read);
5440 D0 : S0; // big decoder only
5441 ALU0 : S4; // ALU0 only
5442 MEM : S3; // any mem
5443 %}
5444
5445 // Integer ALU reg-reg operation
5446 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
5447 %{
5448 single_instruction;
5449 cr : S4(write);
5450 src1 : S3(read);
5451 src2 : S3(read);
5452 DECODE : S0; // any decoder
5453 ALU : S3; // any alu
5454 %}
5455
5456 // Integer ALU reg-imm operation
5457 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
5458 %{
5459 single_instruction;
5460 cr : S4(write);
5461 src1 : S3(read);
5462 DECODE : S0; // any decoder
5463 ALU : S3; // any alu
5464 %}
5465
5466 // Integer ALU reg-mem operation
5467 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
5468 %{
5469 single_instruction;
5470 cr : S4(write);
5471 src1 : S3(read);
5472 src2 : S3(read);
5473 D0 : S0; // big decoder only
5474 ALU : S4; // any alu
5475 MEM : S3;
5476 %}
5477
5478 // Conditional move reg-reg
5479 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
5480 %{
5481 instruction_count(4);
5482 y : S4(read);
5483 q : S3(read);
5484 p : S3(read);
5485 DECODE : S0(4); // any decoder
5486 %}
5487
5488 // Conditional move reg-reg
5489 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
5490 %{
5491 single_instruction;
5492 dst : S4(write);
5493 src : S3(read);
5494 cr : S3(read);
5495 DECODE : S0; // any decoder
5496 %}
5497
5498 // Conditional move reg-mem
5499 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
5500 %{
5501 single_instruction;
5502 dst : S4(write);
5503 src : S3(read);
5504 cr : S3(read);
5505 DECODE : S0; // any decoder
5506 MEM : S3;
5507 %}
5508
5509 // Conditional move reg-reg long
5510 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
5511 %{
5512 single_instruction;
5513 dst : S4(write);
5514 src : S3(read);
5515 cr : S3(read);
5516 DECODE : S0(2); // any 2 decoders
5517 %}
5518
5519 // XXX
5520 // // Conditional move double reg-reg
5521 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
5522 // %{
5523 // single_instruction;
5524 // dst : S4(write);
5525 // src : S3(read);
5526 // cr : S3(read);
5527 // DECODE : S0; // any decoder
5528 // %}
5529
5530 // Float reg-reg operation
5531 pipe_class fpu_reg(regD dst)
5532 %{
5533 instruction_count(2);
5534 dst : S3(read);
5535 DECODE : S0(2); // any 2 decoders
5536 FPU : S3;
5537 %}
5538
5539 // Float reg-reg operation
5540 pipe_class fpu_reg_reg(regD dst, regD src)
5541 %{
5542 instruction_count(2);
5543 dst : S4(write);
5544 src : S3(read);
5545 DECODE : S0(2); // any 2 decoders
5546 FPU : S3;
5547 %}
5548
5549 // Float reg-reg operation
5550 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
5551 %{
5552 instruction_count(3);
5553 dst : S4(write);
5554 src1 : S3(read);
5555 src2 : S3(read);
5556 DECODE : S0(3); // any 3 decoders
5557 FPU : S3(2);
5558 %}
5559
5560 // Float reg-reg operation
5561 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
5562 %{
5563 instruction_count(4);
5564 dst : S4(write);
5565 src1 : S3(read);
5566 src2 : S3(read);
5567 src3 : S3(read);
5568 DECODE : S0(4); // any 3 decoders
5569 FPU : S3(2);
5570 %}
5571
5572 // Float reg-reg operation
5573 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
5574 %{
5575 instruction_count(4);
5576 dst : S4(write);
5577 src1 : S3(read);
5578 src2 : S3(read);
5579 src3 : S3(read);
5580 DECODE : S1(3); // any 3 decoders
5581 D0 : S0; // Big decoder only
5582 FPU : S3(2);
5583 MEM : S3;
5584 %}
5585
5586 // Float reg-mem operation
5587 pipe_class fpu_reg_mem(regD dst, memory mem)
5588 %{
5589 instruction_count(2);
5590 dst : S5(write);
5591 mem : S3(read);
5592 D0 : S0; // big decoder only
5593 DECODE : S1; // any decoder for FPU POP
5594 FPU : S4;
5595 MEM : S3; // any mem
5596 %}
5597
5598 // Float reg-mem operation
5599 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
5600 %{
5601 instruction_count(3);
5602 dst : S5(write);
5603 src1 : S3(read);
5604 mem : S3(read);
5605 D0 : S0; // big decoder only
5606 DECODE : S1(2); // any decoder for FPU POP
5607 FPU : S4;
5608 MEM : S3; // any mem
5609 %}
5610
5611 // Float mem-reg operation
5612 pipe_class fpu_mem_reg(memory mem, regD src)
5613 %{
5614 instruction_count(2);
5615 src : S5(read);
5616 mem : S3(read);
5617 DECODE : S0; // any decoder for FPU PUSH
5618 D0 : S1; // big decoder only
5619 FPU : S4;
5620 MEM : S3; // any mem
5621 %}
5622
5623 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
5624 %{
5625 instruction_count(3);
5626 src1 : S3(read);
5627 src2 : S3(read);
5628 mem : S3(read);
5629 DECODE : S0(2); // any decoder for FPU PUSH
5630 D0 : S1; // big decoder only
5631 FPU : S4;
5632 MEM : S3; // any mem
5633 %}
5634
5635 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
5636 %{
5637 instruction_count(3);
5638 src1 : S3(read);
5639 src2 : S3(read);
5640 mem : S4(read);
5641 DECODE : S0; // any decoder for FPU PUSH
5642 D0 : S0(2); // big decoder only
5643 FPU : S4;
5644 MEM : S3(2); // any mem
5645 %}
5646
5647 pipe_class fpu_mem_mem(memory dst, memory src1)
5648 %{
5649 instruction_count(2);
5650 src1 : S3(read);
5651 dst : S4(read);
5652 D0 : S0(2); // big decoder only
5653 MEM : S3(2); // any mem
5654 %}
5655
5656 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
5657 %{
5658 instruction_count(3);
5659 src1 : S3(read);
5660 src2 : S3(read);
5661 dst : S4(read);
5662 D0 : S0(3); // big decoder only
5663 FPU : S4;
5664 MEM : S3(3); // any mem
5665 %}
5666
5667 pipe_class fpu_mem_reg_con(memory mem, regD src1)
5668 %{
5669 instruction_count(3);
5670 src1 : S4(read);
5671 mem : S4(read);
5672 DECODE : S0; // any decoder for FPU PUSH
5673 D0 : S0(2); // big decoder only
5674 FPU : S4;
5675 MEM : S3(2); // any mem
5676 %}
5677
5678 // Float load constant
5679 pipe_class fpu_reg_con(regD dst)
5680 %{
5681 instruction_count(2);
5682 dst : S5(write);
5683 D0 : S0; // big decoder only for the load
5684 DECODE : S1; // any decoder for FPU POP
5685 FPU : S4;
5686 MEM : S3; // any mem
5687 %}
5688
5689 // Float load constant
5690 pipe_class fpu_reg_reg_con(regD dst, regD src)
5691 %{
5692 instruction_count(3);
5693 dst : S5(write);
5694 src : S3(read);
5695 D0 : S0; // big decoder only for the load
5696 DECODE : S1(2); // any decoder for FPU POP
5697 FPU : S4;
5698 MEM : S3; // any mem
5699 %}
5700
5701 // UnConditional branch
5702 pipe_class pipe_jmp(label labl)
5703 %{
5704 single_instruction;
5705 BR : S3;
5706 %}
5707
5708 // Conditional branch
5709 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
5710 %{
5711 single_instruction;
5712 cr : S1(read);
5713 BR : S3;
5714 %}
5715
5716 // Allocation idiom
5717 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
5718 %{
5719 instruction_count(1); force_serialization;
5720 fixed_latency(6);
5721 heap_ptr : S3(read);
5722 DECODE : S0(3);
5723 D0 : S2;
5724 MEM : S3;
5725 ALU : S3(2);
5726 dst : S5(write);
5727 BR : S5;
5728 %}
5729
5730 // Generic big/slow expanded idiom
5731 pipe_class pipe_slow()
5732 %{
5733 instruction_count(10); multiple_bundles; force_serialization;
5734 fixed_latency(100);
5735 D0 : S0(2);
5736 MEM : S3(2);
5737 %}
5738
5739 // The real do-nothing guy
5740 pipe_class empty()
5741 %{
5742 instruction_count(0);
5743 %}
5744
5745 // Define the class for the Nop node
5746 define
5747 %{
5748 MachNop = empty;
5749 %}
5750
5751 %}
5752
5753 //----------INSTRUCTIONS-------------------------------------------------------
5754 //
5755 // match -- States which machine-independent subtree may be replaced
5756 // by this instruction.
5757 // ins_cost -- The estimated cost of this instruction is used by instruction
5758 // selection to identify a minimum cost tree of machine
5759 // instructions that matches a tree of machine-independent
5760 // instructions.
5761 // format -- A string providing the disassembly for this instruction.
5762 // The value of an instruction's operand may be inserted
5763 // by referring to it with a '$' prefix.
5764 // opcode -- Three instruction opcodes may be provided. These are referred
5765 // to within an encode class as $primary, $secondary, and $tertiary
5766 // rrspectively. The primary opcode is commonly used to
5767 // indicate the type of machine instruction, while secondary
5768 // and tertiary are often used for prefix options or addressing
5769 // modes.
5770 // ins_encode -- A list of encode classes with parameters. The encode class
5771 // name must have been defined in an 'enc_class' specification
5772 // in the encode section of the architecture description.
5773
5774
5775 //----------Load/Store/Move Instructions---------------------------------------
5776 //----------Load Instructions--------------------------------------------------
5777
5778 // Load Byte (8 bit signed)
5779 instruct loadB(rRegI dst, memory mem)
5780 %{
5781 match(Set dst (LoadB mem));
5782
5783 ins_cost(125);
5784 format %{ "movsbl $dst, $mem\t# byte" %}
5785
5786 ins_encode %{
5787 __ movsbl($dst$$Register, $mem$$Address);
5788 %}
5789
5790 ins_pipe(ialu_reg_mem);
5791 %}
5792
5793 // Load Byte (8 bit signed) into Long Register
5794 instruct loadB2L(rRegL dst, memory mem)
5795 %{
5796 match(Set dst (ConvI2L (LoadB mem)));
5797
5798 ins_cost(125);
5799 format %{ "movsbq $dst, $mem\t# byte -> long" %}
5800
5801 ins_encode %{
5802 __ movsbq($dst$$Register, $mem$$Address);
5803 %}
5804
5805 ins_pipe(ialu_reg_mem);
5806 %}
5807
5808 // Load Unsigned Byte (8 bit UNsigned)
5809 instruct loadUB(rRegI dst, memory mem)
5810 %{
5811 match(Set dst (LoadUB mem));
5812
5813 ins_cost(125);
5814 format %{ "movzbl $dst, $mem\t# ubyte" %}
5815
5816 ins_encode %{
5817 __ movzbl($dst$$Register, $mem$$Address);
5818 %}
5819
5820 ins_pipe(ialu_reg_mem);
5821 %}
5822
5823 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5824 instruct loadUB2L(rRegL dst, memory mem)
5825 %{
5826 match(Set dst (ConvI2L (LoadUB mem)));
5827
5828 ins_cost(125);
5829 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
5830
5831 ins_encode %{
5832 __ movzbq($dst$$Register, $mem$$Address);
5833 %}
5834
5835 ins_pipe(ialu_reg_mem);
5836 %}
5837
5838 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
5839 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
5840 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5841 effect(KILL cr);
5842
5843 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
5844 "andl $dst, $mask" %}
5845 ins_encode %{
5846 Register Rdst = $dst$$Register;
5847 __ movzbq(Rdst, $mem$$Address);
5848 __ andl(Rdst, $mask$$constant);
5849 %}
5850 ins_pipe(ialu_reg_mem);
5851 %}
5852
5853 // Load Short (16 bit signed)
5854 instruct loadS(rRegI dst, memory mem)
5855 %{
5856 match(Set dst (LoadS mem));
5857
5858 ins_cost(125);
5859 format %{ "movswl $dst, $mem\t# short" %}
5860
5861 ins_encode %{
5862 __ movswl($dst$$Register, $mem$$Address);
5863 %}
5864
5865 ins_pipe(ialu_reg_mem);
5866 %}
5867
5868 // Load Short (16 bit signed) to Byte (8 bit signed)
5869 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5870 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5871
5872 ins_cost(125);
5873 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5874 ins_encode %{
5875 __ movsbl($dst$$Register, $mem$$Address);
5876 %}
5877 ins_pipe(ialu_reg_mem);
5878 %}
5879
5880 // Load Short (16 bit signed) into Long Register
5881 instruct loadS2L(rRegL dst, memory mem)
5882 %{
5883 match(Set dst (ConvI2L (LoadS mem)));
5884
5885 ins_cost(125);
5886 format %{ "movswq $dst, $mem\t# short -> long" %}
5887
5888 ins_encode %{
5889 __ movswq($dst$$Register, $mem$$Address);
5890 %}
5891
5892 ins_pipe(ialu_reg_mem);
5893 %}
5894
5895 // Load Unsigned Short/Char (16 bit UNsigned)
5896 instruct loadUS(rRegI dst, memory mem)
5897 %{
5898 match(Set dst (LoadUS mem));
5899
5900 ins_cost(125);
5901 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5902
5903 ins_encode %{
5904 __ movzwl($dst$$Register, $mem$$Address);
5905 %}
5906
5907 ins_pipe(ialu_reg_mem);
5908 %}
5909
5910 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5911 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5912 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5913
5914 ins_cost(125);
5915 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5916 ins_encode %{
5917 __ movsbl($dst$$Register, $mem$$Address);
5918 %}
5919 ins_pipe(ialu_reg_mem);
5920 %}
5921
5922 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5923 instruct loadUS2L(rRegL dst, memory mem)
5924 %{
5925 match(Set dst (ConvI2L (LoadUS mem)));
5926
5927 ins_cost(125);
5928 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5929
5930 ins_encode %{
5931 __ movzwq($dst$$Register, $mem$$Address);
5932 %}
5933
5934 ins_pipe(ialu_reg_mem);
5935 %}
5936
5937 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5938 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5939 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5940
5941 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5942 ins_encode %{
5943 __ movzbq($dst$$Register, $mem$$Address);
5944 %}
5945 ins_pipe(ialu_reg_mem);
5946 %}
5947
5948 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
5949 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
5950 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5951 effect(KILL cr);
5952
5953 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5954 "andl $dst, $mask" %}
5955 ins_encode %{
5956 Register Rdst = $dst$$Register;
5957 __ movzwq(Rdst, $mem$$Address);
5958 __ andl(Rdst, $mask$$constant);
5959 %}
5960 ins_pipe(ialu_reg_mem);
5961 %}
5962
5963 // Load Integer
5964 instruct loadI(rRegI dst, memory mem)
5965 %{
5966 match(Set dst (LoadI mem));
5967
5968 ins_cost(125);
5969 format %{ "movl $dst, $mem\t# int" %}
5970
5971 ins_encode %{
5972 __ movl($dst$$Register, $mem$$Address);
5973 %}
5974
5975 ins_pipe(ialu_reg_mem);
5976 %}
5977
5978 // Load Integer (32 bit signed) to Byte (8 bit signed)
5979 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5980 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5981
5982 ins_cost(125);
5983 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5984 ins_encode %{
5985 __ movsbl($dst$$Register, $mem$$Address);
5986 %}
5987 ins_pipe(ialu_reg_mem);
5988 %}
5989
5990 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5991 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5992 match(Set dst (AndI (LoadI mem) mask));
5993
5994 ins_cost(125);
5995 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5996 ins_encode %{
5997 __ movzbl($dst$$Register, $mem$$Address);
5998 %}
5999 ins_pipe(ialu_reg_mem);
6000 %}
6001
6002 // Load Integer (32 bit signed) to Short (16 bit signed)
6003 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6004 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6005
6006 ins_cost(125);
6007 format %{ "movswl $dst, $mem\t# int -> short" %}
6008 ins_encode %{
6009 __ movswl($dst$$Register, $mem$$Address);
6010 %}
6011 ins_pipe(ialu_reg_mem);
6012 %}
6013
6014 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6015 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6016 match(Set dst (AndI (LoadI mem) mask));
6017
6018 ins_cost(125);
6019 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
6020 ins_encode %{
6021 __ movzwl($dst$$Register, $mem$$Address);
6022 %}
6023 ins_pipe(ialu_reg_mem);
6024 %}
6025
6026 // Load Integer into Long Register
6027 instruct loadI2L(rRegL dst, memory mem)
6028 %{
6029 match(Set dst (ConvI2L (LoadI mem)));
6030
6031 ins_cost(125);
6032 format %{ "movslq $dst, $mem\t# int -> long" %}
6033
6034 ins_encode %{
6035 __ movslq($dst$$Register, $mem$$Address);
6036 %}
6037
6038 ins_pipe(ialu_reg_mem);
6039 %}
6040
6041 // Load Integer with mask 0xFF into Long Register
6042 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
6043 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6044
6045 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
6046 ins_encode %{
6047 __ movzbq($dst$$Register, $mem$$Address);
6048 %}
6049 ins_pipe(ialu_reg_mem);
6050 %}
6051
6052 // Load Integer with mask 0xFFFF into Long Register
6053 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
6054 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6055
6056 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
6057 ins_encode %{
6058 __ movzwq($dst$$Register, $mem$$Address);
6059 %}
6060 ins_pipe(ialu_reg_mem);
6061 %}
6062
6063 // Load Integer with a 32-bit mask into Long Register
6064 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
6065 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6066 effect(KILL cr);
6067
6068 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
6069 "andl $dst, $mask" %}
6070 ins_encode %{
6071 Register Rdst = $dst$$Register;
6072 __ movl(Rdst, $mem$$Address);
6073 __ andl(Rdst, $mask$$constant);
6074 %}
6075 ins_pipe(ialu_reg_mem);
6076 %}
6077
6078 // Load Unsigned Integer into Long Register
6079 instruct loadUI2L(rRegL dst, memory mem)
6080 %{
6081 match(Set dst (LoadUI2L mem));
6082
6083 ins_cost(125);
6084 format %{ "movl $dst, $mem\t# uint -> long" %}
6085
6086 ins_encode %{
6087 __ movl($dst$$Register, $mem$$Address);
6088 %}
6089
6090 ins_pipe(ialu_reg_mem);
6091 %}
6092
6093 // Load Long
6094 instruct loadL(rRegL dst, memory mem)
6095 %{
6096 match(Set dst (LoadL mem));
6097
6098 ins_cost(125);
6099 format %{ "movq $dst, $mem\t# long" %}
6100
6101 ins_encode %{
6102 __ movq($dst$$Register, $mem$$Address);
6103 %}
6104
6105 ins_pipe(ialu_reg_mem); // XXX
6106 %}
6107
6108 // Load Range
6109 instruct loadRange(rRegI dst, memory mem)
6110 %{
6111 match(Set dst (LoadRange mem));
6112
6113 ins_cost(125); // XXX
6114 format %{ "movl $dst, $mem\t# range" %}
6115 opcode(0x8B);
6116 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
6117 ins_pipe(ialu_reg_mem);
6118 %}
6119
6120 // Load Pointer
6121 instruct loadP(rRegP dst, memory mem)
6122 %{
6123 match(Set dst (LoadP mem));
6124
6125 ins_cost(125); // XXX
6126 format %{ "movq $dst, $mem\t# ptr" %}
6127 opcode(0x8B);
6128 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6129 ins_pipe(ialu_reg_mem); // XXX
6130 %}
6131
6132 // Load Compressed Pointer
6133 instruct loadN(rRegN dst, memory mem)
6134 %{
6135 match(Set dst (LoadN mem));
6136
6137 ins_cost(125); // XXX
6138 format %{ "movl $dst, $mem\t# compressed ptr" %}
6139 ins_encode %{
6140 __ movl($dst$$Register, $mem$$Address);
6141 %}
6142 ins_pipe(ialu_reg_mem); // XXX
6143 %}
6144
6145
6146 // Load Klass Pointer
6147 instruct loadKlass(rRegP dst, memory mem)
6148 %{
6149 match(Set dst (LoadKlass mem));
6150
6151 ins_cost(125); // XXX
6152 format %{ "movq $dst, $mem\t# class" %}
6153 opcode(0x8B);
6154 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6155 ins_pipe(ialu_reg_mem); // XXX
6156 %}
6157
6158 // Load narrow Klass Pointer
6159 instruct loadNKlass(rRegN dst, memory mem)
6160 %{
6161 match(Set dst (LoadNKlass mem));
6162
6163 ins_cost(125); // XXX
6164 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
6165 ins_encode %{
6166 __ movl($dst$$Register, $mem$$Address);
6167 %}
6168 ins_pipe(ialu_reg_mem); // XXX
6169 %}
6170
6171 // Load Float
6172 instruct loadF(regF dst, memory mem)
6173 %{
6174 match(Set dst (LoadF mem));
6175
6176 ins_cost(145); // XXX
6177 format %{ "movss $dst, $mem\t# float" %}
6178 opcode(0xF3, 0x0F, 0x10);
6179 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6180 ins_pipe(pipe_slow); // XXX
6181 %}
6182
6183 // Load Double
6184 instruct loadD_partial(regD dst, memory mem)
6185 %{
6186 predicate(!UseXmmLoadAndClearUpper);
6187 match(Set dst (LoadD mem));
6188
6189 ins_cost(145); // XXX
6190 format %{ "movlpd $dst, $mem\t# double" %}
6191 opcode(0x66, 0x0F, 0x12);
6192 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6193 ins_pipe(pipe_slow); // XXX
6194 %}
6195
6196 instruct loadD(regD dst, memory mem)
6197 %{
6198 predicate(UseXmmLoadAndClearUpper);
6199 match(Set dst (LoadD mem));
6200
6201 ins_cost(145); // XXX
6202 format %{ "movsd $dst, $mem\t# double" %}
6203 opcode(0xF2, 0x0F, 0x10);
6204 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6205 ins_pipe(pipe_slow); // XXX
6206 %}
6207
6208 // Load Aligned Packed Byte to XMM register
6209 instruct loadA8B(regD dst, memory mem) %{
6210 match(Set dst (Load8B mem));
6211 ins_cost(125);
6212 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6213 ins_encode( movq_ld(dst, mem));
6214 ins_pipe( pipe_slow );
6215 %}
6216
6217 // Load Aligned Packed Short to XMM register
6218 instruct loadA4S(regD dst, memory mem) %{
6219 match(Set dst (Load4S mem));
6220 ins_cost(125);
6221 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6222 ins_encode( movq_ld(dst, mem));
6223 ins_pipe( pipe_slow );
6224 %}
6225
6226 // Load Aligned Packed Char to XMM register
6227 instruct loadA4C(regD dst, memory mem) %{
6228 match(Set dst (Load4C mem));
6229 ins_cost(125);
6230 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6231 ins_encode( movq_ld(dst, mem));
6232 ins_pipe( pipe_slow );
6233 %}
6234
6235 // Load Aligned Packed Integer to XMM register
6236 instruct load2IU(regD dst, memory mem) %{
6237 match(Set dst (Load2I mem));
6238 ins_cost(125);
6239 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6240 ins_encode( movq_ld(dst, mem));
6241 ins_pipe( pipe_slow );
6242 %}
6243
6244 // Load Aligned Packed Single to XMM
6245 instruct loadA2F(regD dst, memory mem) %{
6246 match(Set dst (Load2F mem));
6247 ins_cost(145);
6248 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6249 ins_encode( movq_ld(dst, mem));
6250 ins_pipe( pipe_slow );
6251 %}
6252
6253 // Load Effective Address
6254 instruct leaP8(rRegP dst, indOffset8 mem)
6255 %{
6256 match(Set dst mem);
6257
6258 ins_cost(110); // XXX
6259 format %{ "leaq $dst, $mem\t# ptr 8" %}
6260 opcode(0x8D);
6261 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6262 ins_pipe(ialu_reg_reg_fat);
6263 %}
6264
6265 instruct leaP32(rRegP dst, indOffset32 mem)
6266 %{
6267 match(Set dst mem);
6268
6269 ins_cost(110);
6270 format %{ "leaq $dst, $mem\t# ptr 32" %}
6271 opcode(0x8D);
6272 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6273 ins_pipe(ialu_reg_reg_fat);
6274 %}
6275
6276 // instruct leaPIdx(rRegP dst, indIndex mem)
6277 // %{
6278 // match(Set dst mem);
6279
6280 // ins_cost(110);
6281 // format %{ "leaq $dst, $mem\t# ptr idx" %}
6282 // opcode(0x8D);
6283 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6284 // ins_pipe(ialu_reg_reg_fat);
6285 // %}
6286
6287 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
6288 %{
6289 match(Set dst mem);
6290
6291 ins_cost(110);
6292 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
6293 opcode(0x8D);
6294 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6295 ins_pipe(ialu_reg_reg_fat);
6296 %}
6297
6298 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
6299 %{
6300 match(Set dst mem);
6301
6302 ins_cost(110);
6303 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
6304 opcode(0x8D);
6305 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6306 ins_pipe(ialu_reg_reg_fat);
6307 %}
6308
6309 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
6310 %{
6311 match(Set dst mem);
6312
6313 ins_cost(110);
6314 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
6315 opcode(0x8D);
6316 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6317 ins_pipe(ialu_reg_reg_fat);
6318 %}
6319
6320 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
6321 %{
6322 match(Set dst mem);
6323
6324 ins_cost(110);
6325 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
6326 opcode(0x8D);
6327 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6328 ins_pipe(ialu_reg_reg_fat);
6329 %}
6330
6331 // Load Effective Address which uses Narrow (32-bits) oop
6332 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
6333 %{
6334 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
6335 match(Set dst mem);
6336
6337 ins_cost(110);
6338 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
6339 opcode(0x8D);
6340 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6341 ins_pipe(ialu_reg_reg_fat);
6342 %}
6343
6344 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
6345 %{
6346 predicate(Universe::narrow_oop_shift() == 0);
6347 match(Set dst mem);
6348
6349 ins_cost(110); // XXX
6350 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
6351 opcode(0x8D);
6352 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6353 ins_pipe(ialu_reg_reg_fat);
6354 %}
6355
6356 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
6357 %{
6358 predicate(Universe::narrow_oop_shift() == 0);
6359 match(Set dst mem);
6360
6361 ins_cost(110);
6362 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
6363 opcode(0x8D);
6364 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6365 ins_pipe(ialu_reg_reg_fat);
6366 %}
6367
6368 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
6369 %{
6370 predicate(Universe::narrow_oop_shift() == 0);
6371 match(Set dst mem);
6372
6373 ins_cost(110);
6374 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
6375 opcode(0x8D);
6376 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6377 ins_pipe(ialu_reg_reg_fat);
6378 %}
6379
6380 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
6381 %{
6382 predicate(Universe::narrow_oop_shift() == 0);
6383 match(Set dst mem);
6384
6385 ins_cost(110);
6386 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
6387 opcode(0x8D);
6388 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6389 ins_pipe(ialu_reg_reg_fat);
6390 %}
6391
6392 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
6393 %{
6394 predicate(Universe::narrow_oop_shift() == 0);
6395 match(Set dst mem);
6396
6397 ins_cost(110);
6398 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
6399 opcode(0x8D);
6400 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6401 ins_pipe(ialu_reg_reg_fat);
6402 %}
6403
6404 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
6405 %{
6406 predicate(Universe::narrow_oop_shift() == 0);
6407 match(Set dst mem);
6408
6409 ins_cost(110);
6410 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
6411 opcode(0x8D);
6412 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6413 ins_pipe(ialu_reg_reg_fat);
6414 %}
6415
6416 instruct loadConI(rRegI dst, immI src)
6417 %{
6418 match(Set dst src);
6419
6420 format %{ "movl $dst, $src\t# int" %}
6421 ins_encode(load_immI(dst, src));
6422 ins_pipe(ialu_reg_fat); // XXX
6423 %}
6424
6425 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
6426 %{
6427 match(Set dst src);
6428 effect(KILL cr);
6429
6430 ins_cost(50);
6431 format %{ "xorl $dst, $dst\t# int" %}
6432 opcode(0x33); /* + rd */
6433 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6434 ins_pipe(ialu_reg);
6435 %}
6436
6437 instruct loadConL(rRegL dst, immL src)
6438 %{
6439 match(Set dst src);
6440
6441 ins_cost(150);
6442 format %{ "movq $dst, $src\t# long" %}
6443 ins_encode(load_immL(dst, src));
6444 ins_pipe(ialu_reg);
6445 %}
6446
6447 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
6448 %{
6449 match(Set dst src);
6450 effect(KILL cr);
6451
6452 ins_cost(50);
6453 format %{ "xorl $dst, $dst\t# long" %}
6454 opcode(0x33); /* + rd */
6455 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6456 ins_pipe(ialu_reg); // XXX
6457 %}
6458
6459 instruct loadConUL32(rRegL dst, immUL32 src)
6460 %{
6461 match(Set dst src);
6462
6463 ins_cost(60);
6464 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
6465 ins_encode(load_immUL32(dst, src));
6466 ins_pipe(ialu_reg);
6467 %}
6468
6469 instruct loadConL32(rRegL dst, immL32 src)
6470 %{
6471 match(Set dst src);
6472
6473 ins_cost(70);
6474 format %{ "movq $dst, $src\t# long (32-bit)" %}
6475 ins_encode(load_immL32(dst, src));
6476 ins_pipe(ialu_reg);
6477 %}
6478
6479 instruct loadConP(rRegP dst, immP con) %{
6480 match(Set dst con);
6481
6482 format %{ "movq $dst, $con\t# ptr" %}
6483 ins_encode(load_immP(dst, con));
6484 ins_pipe(ialu_reg_fat); // XXX
6485 %}
6486
6487 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
6488 %{
6489 match(Set dst src);
6490 effect(KILL cr);
6491
6492 ins_cost(50);
6493 format %{ "xorl $dst, $dst\t# ptr" %}
6494 opcode(0x33); /* + rd */
6495 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6496 ins_pipe(ialu_reg);
6497 %}
6498
6499 instruct loadConP_poll(rRegP dst, immP_poll src) %{
6500 match(Set dst src);
6501 format %{ "movq $dst, $src\t!ptr" %}
6502 ins_encode %{
6503 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
6504 __ lea($dst$$Register, polling_page);
6505 %}
6506 ins_pipe(ialu_reg_fat);
6507 %}
6508
6509 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
6510 %{
6511 match(Set dst src);
6512 effect(KILL cr);
6513
6514 ins_cost(60);
6515 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
6516 ins_encode(load_immP31(dst, src));
6517 ins_pipe(ialu_reg);
6518 %}
6519
6520 instruct loadConF(regF dst, immF con) %{
6521 match(Set dst con);
6522 ins_cost(125);
6523 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
6524 ins_encode %{
6525 __ movflt($dst$$XMMRegister, $constantaddress($con));
6526 %}
6527 ins_pipe(pipe_slow);
6528 %}
6529
6530 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
6531 match(Set dst src);
6532 effect(KILL cr);
6533 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
6534 ins_encode %{
6535 __ xorq($dst$$Register, $dst$$Register);
6536 %}
6537 ins_pipe(ialu_reg);
6538 %}
6539
6540 instruct loadConN(rRegN dst, immN src) %{
6541 match(Set dst src);
6542
6543 ins_cost(125);
6544 format %{ "movl $dst, $src\t# compressed ptr" %}
6545 ins_encode %{
6546 address con = (address)$src$$constant;
6547 if (con == NULL) {
6548 ShouldNotReachHere();
6549 } else {
6550 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
6551 }
6552 %}
6553 ins_pipe(ialu_reg_fat); // XXX
6554 %}
6555
6556 instruct loadConF0(regF dst, immF0 src)
6557 %{
6558 match(Set dst src);
6559 ins_cost(100);
6560
6561 format %{ "xorps $dst, $dst\t# float 0.0" %}
6562 opcode(0x0F, 0x57);
6563 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
6564 ins_pipe(pipe_slow);
6565 %}
6566
6567 // Use the same format since predicate() can not be used here.
6568 instruct loadConD(regD dst, immD con) %{
6569 match(Set dst con);
6570 ins_cost(125);
6571 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
6572 ins_encode %{
6573 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6574 %}
6575 ins_pipe(pipe_slow);
6576 %}
6577
6578 instruct loadConD0(regD dst, immD0 src)
6579 %{
6580 match(Set dst src);
6581 ins_cost(100);
6582
6583 format %{ "xorpd $dst, $dst\t# double 0.0" %}
6584 opcode(0x66, 0x0F, 0x57);
6585 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst));
6586 ins_pipe(pipe_slow);
6587 %}
6588
6589 instruct loadSSI(rRegI dst, stackSlotI src)
6590 %{
6591 match(Set dst src);
6592
6593 ins_cost(125);
6594 format %{ "movl $dst, $src\t# int stk" %}
6595 opcode(0x8B);
6596 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6597 ins_pipe(ialu_reg_mem);
6598 %}
6599
6600 instruct loadSSL(rRegL dst, stackSlotL src)
6601 %{
6602 match(Set dst src);
6603
6604 ins_cost(125);
6605 format %{ "movq $dst, $src\t# long stk" %}
6606 opcode(0x8B);
6607 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6608 ins_pipe(ialu_reg_mem);
6609 %}
6610
6611 instruct loadSSP(rRegP dst, stackSlotP src)
6612 %{
6613 match(Set dst src);
6614
6615 ins_cost(125);
6616 format %{ "movq $dst, $src\t# ptr stk" %}
6617 opcode(0x8B);
6618 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6619 ins_pipe(ialu_reg_mem);
6620 %}
6621
6622 instruct loadSSF(regF dst, stackSlotF src)
6623 %{
6624 match(Set dst src);
6625
6626 ins_cost(125);
6627 format %{ "movss $dst, $src\t# float stk" %}
6628 opcode(0xF3, 0x0F, 0x10);
6629 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
6630 ins_pipe(pipe_slow); // XXX
6631 %}
6632
6633 // Use the same format since predicate() can not be used here.
6634 instruct loadSSD(regD dst, stackSlotD src)
6635 %{
6636 match(Set dst src);
6637
6638 ins_cost(125);
6639 format %{ "movsd $dst, $src\t# double stk" %}
6640 ins_encode %{
6641 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
6642 %}
6643 ins_pipe(pipe_slow); // XXX
6644 %}
6645
6646 // Prefetch instructions.
6647 // Must be safe to execute with invalid address (cannot fault).
6648
6649 instruct prefetchr( memory mem ) %{
6650 predicate(ReadPrefetchInstr==3);
6651 match(PrefetchRead mem);
6652 ins_cost(125);
6653
6654 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
6655 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */
6656 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6657 ins_pipe(ialu_mem);
6658 %}
6659
6660 instruct prefetchrNTA( memory mem ) %{
6661 predicate(ReadPrefetchInstr==0);
6662 match(PrefetchRead mem);
6663 ins_cost(125);
6664
6665 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
6666 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6667 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6668 ins_pipe(ialu_mem);
6669 %}
6670
6671 instruct prefetchrT0( memory mem ) %{
6672 predicate(ReadPrefetchInstr==1);
6673 match(PrefetchRead mem);
6674 ins_cost(125);
6675
6676 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
6677 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6678 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6679 ins_pipe(ialu_mem);
6680 %}
6681
6682 instruct prefetchrT2( memory mem ) %{
6683 predicate(ReadPrefetchInstr==2);
6684 match(PrefetchRead mem);
6685 ins_cost(125);
6686
6687 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
6688 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6689 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6690 ins_pipe(ialu_mem);
6691 %}
6692
6693 instruct prefetchw( memory mem ) %{
6694 predicate(AllocatePrefetchInstr==3);
6695 match(PrefetchWrite mem);
6696 ins_cost(125);
6697
6698 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %}
6699 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
6700 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6701 ins_pipe(ialu_mem);
6702 %}
6703
6704 instruct prefetchwNTA( memory mem ) %{
6705 predicate(AllocatePrefetchInstr==0);
6706 match(PrefetchWrite mem);
6707 ins_cost(125);
6708
6709 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
6710 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6711 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6712 ins_pipe(ialu_mem);
6713 %}
6714
6715 instruct prefetchwT0( memory mem ) %{
6716 predicate(AllocatePrefetchInstr==1);
6717 match(PrefetchWrite mem);
6718 ins_cost(125);
6719
6720 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %}
6721 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6722 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6723 ins_pipe(ialu_mem);
6724 %}
6725
6726 instruct prefetchwT2( memory mem ) %{
6727 predicate(AllocatePrefetchInstr==2);
6728 match(PrefetchWrite mem);
6729 ins_cost(125);
6730
6731 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %}
6732 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6733 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6734 ins_pipe(ialu_mem);
6735 %}
6736
6737 //----------Store Instructions-------------------------------------------------
6738
6739 // Store Byte
6740 instruct storeB(memory mem, rRegI src)
6741 %{
6742 match(Set mem (StoreB mem src));
6743
6744 ins_cost(125); // XXX
6745 format %{ "movb $mem, $src\t# byte" %}
6746 opcode(0x88);
6747 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6748 ins_pipe(ialu_mem_reg);
6749 %}
6750
6751 // Store Char/Short
6752 instruct storeC(memory mem, rRegI src)
6753 %{
6754 match(Set mem (StoreC mem src));
6755
6756 ins_cost(125); // XXX
6757 format %{ "movw $mem, $src\t# char/short" %}
6758 opcode(0x89);
6759 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6760 ins_pipe(ialu_mem_reg);
6761 %}
6762
6763 // Store Integer
6764 instruct storeI(memory mem, rRegI src)
6765 %{
6766 match(Set mem (StoreI mem src));
6767
6768 ins_cost(125); // XXX
6769 format %{ "movl $mem, $src\t# int" %}
6770 opcode(0x89);
6771 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6772 ins_pipe(ialu_mem_reg);
6773 %}
6774
6775 // Store Long
6776 instruct storeL(memory mem, rRegL src)
6777 %{
6778 match(Set mem (StoreL mem src));
6779
6780 ins_cost(125); // XXX
6781 format %{ "movq $mem, $src\t# long" %}
6782 opcode(0x89);
6783 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6784 ins_pipe(ialu_mem_reg); // XXX
6785 %}
6786
6787 // Store Pointer
6788 instruct storeP(memory mem, any_RegP src)
6789 %{
6790 match(Set mem (StoreP mem src));
6791
6792 ins_cost(125); // XXX
6793 format %{ "movq $mem, $src\t# ptr" %}
6794 opcode(0x89);
6795 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6796 ins_pipe(ialu_mem_reg);
6797 %}
6798
6799 instruct storeImmP0(memory mem, immP0 zero)
6800 %{
6801 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6802 match(Set mem (StoreP mem zero));
6803
6804 ins_cost(125); // XXX
6805 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6806 ins_encode %{
6807 __ movq($mem$$Address, r12);
6808 %}
6809 ins_pipe(ialu_mem_reg);
6810 %}
6811
6812 // Store NULL Pointer, mark word, or other simple pointer constant.
6813 instruct storeImmP(memory mem, immP31 src)
6814 %{
6815 match(Set mem (StoreP mem src));
6816
6817 ins_cost(150); // XXX
6818 format %{ "movq $mem, $src\t# ptr" %}
6819 opcode(0xC7); /* C7 /0 */
6820 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6821 ins_pipe(ialu_mem_imm);
6822 %}
6823
6824 // Store Compressed Pointer
6825 instruct storeN(memory mem, rRegN src)
6826 %{
6827 match(Set mem (StoreN mem src));
6828
6829 ins_cost(125); // XXX
6830 format %{ "movl $mem, $src\t# compressed ptr" %}
6831 ins_encode %{
6832 __ movl($mem$$Address, $src$$Register);
6833 %}
6834 ins_pipe(ialu_mem_reg);
6835 %}
6836
6837 instruct storeImmN0(memory mem, immN0 zero)
6838 %{
6839 predicate(Universe::narrow_oop_base() == NULL);
6840 match(Set mem (StoreN mem zero));
6841
6842 ins_cost(125); // XXX
6843 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6844 ins_encode %{
6845 __ movl($mem$$Address, r12);
6846 %}
6847 ins_pipe(ialu_mem_reg);
6848 %}
6849
6850 instruct storeImmN(memory mem, immN src)
6851 %{
6852 match(Set mem (StoreN mem src));
6853
6854 ins_cost(150); // XXX
6855 format %{ "movl $mem, $src\t# compressed ptr" %}
6856 ins_encode %{
6857 address con = (address)$src$$constant;
6858 if (con == NULL) {
6859 __ movl($mem$$Address, (int32_t)0);
6860 } else {
6861 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6862 }
6863 %}
6864 ins_pipe(ialu_mem_imm);
6865 %}
6866
6867 // Store Integer Immediate
6868 instruct storeImmI0(memory mem, immI0 zero)
6869 %{
6870 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6871 match(Set mem (StoreI mem zero));
6872
6873 ins_cost(125); // XXX
6874 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6875 ins_encode %{
6876 __ movl($mem$$Address, r12);
6877 %}
6878 ins_pipe(ialu_mem_reg);
6879 %}
6880
6881 instruct storeImmI(memory mem, immI src)
6882 %{
6883 match(Set mem (StoreI mem src));
6884
6885 ins_cost(150);
6886 format %{ "movl $mem, $src\t# int" %}
6887 opcode(0xC7); /* C7 /0 */
6888 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6889 ins_pipe(ialu_mem_imm);
6890 %}
6891
6892 // Store Long Immediate
6893 instruct storeImmL0(memory mem, immL0 zero)
6894 %{
6895 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6896 match(Set mem (StoreL mem zero));
6897
6898 ins_cost(125); // XXX
6899 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6900 ins_encode %{
6901 __ movq($mem$$Address, r12);
6902 %}
6903 ins_pipe(ialu_mem_reg);
6904 %}
6905
6906 instruct storeImmL(memory mem, immL32 src)
6907 %{
6908 match(Set mem (StoreL mem src));
6909
6910 ins_cost(150);
6911 format %{ "movq $mem, $src\t# long" %}
6912 opcode(0xC7); /* C7 /0 */
6913 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6914 ins_pipe(ialu_mem_imm);
6915 %}
6916
6917 // Store Short/Char Immediate
6918 instruct storeImmC0(memory mem, immI0 zero)
6919 %{
6920 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6921 match(Set mem (StoreC mem zero));
6922
6923 ins_cost(125); // XXX
6924 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6925 ins_encode %{
6926 __ movw($mem$$Address, r12);
6927 %}
6928 ins_pipe(ialu_mem_reg);
6929 %}
6930
6931 instruct storeImmI16(memory mem, immI16 src)
6932 %{
6933 predicate(UseStoreImmI16);
6934 match(Set mem (StoreC mem src));
6935
6936 ins_cost(150);
6937 format %{ "movw $mem, $src\t# short/char" %}
6938 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6939 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6940 ins_pipe(ialu_mem_imm);
6941 %}
6942
6943 // Store Byte Immediate
6944 instruct storeImmB0(memory mem, immI0 zero)
6945 %{
6946 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6947 match(Set mem (StoreB mem zero));
6948
6949 ins_cost(125); // XXX
6950 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6951 ins_encode %{
6952 __ movb($mem$$Address, r12);
6953 %}
6954 ins_pipe(ialu_mem_reg);
6955 %}
6956
6957 instruct storeImmB(memory mem, immI8 src)
6958 %{
6959 match(Set mem (StoreB mem src));
6960
6961 ins_cost(150); // XXX
6962 format %{ "movb $mem, $src\t# byte" %}
6963 opcode(0xC6); /* C6 /0 */
6964 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6965 ins_pipe(ialu_mem_imm);
6966 %}
6967
6968 // Store Aligned Packed Byte XMM register to memory
6969 instruct storeA8B(memory mem, regD src) %{
6970 match(Set mem (Store8B mem src));
6971 ins_cost(145);
6972 format %{ "MOVQ $mem,$src\t! packed8B" %}
6973 ins_encode( movq_st(mem, src));
6974 ins_pipe( pipe_slow );
6975 %}
6976
6977 // Store Aligned Packed Char/Short XMM register to memory
6978 instruct storeA4C(memory mem, regD src) %{
6979 match(Set mem (Store4C mem src));
6980 ins_cost(145);
6981 format %{ "MOVQ $mem,$src\t! packed4C" %}
6982 ins_encode( movq_st(mem, src));
6983 ins_pipe( pipe_slow );
6984 %}
6985
6986 // Store Aligned Packed Integer XMM register to memory
6987 instruct storeA2I(memory mem, regD src) %{
6988 match(Set mem (Store2I mem src));
6989 ins_cost(145);
6990 format %{ "MOVQ $mem,$src\t! packed2I" %}
6991 ins_encode( movq_st(mem, src));
6992 ins_pipe( pipe_slow );
6993 %}
6994
6995 // Store CMS card-mark Immediate
6996 instruct storeImmCM0_reg(memory mem, immI0 zero)
6997 %{
6998 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6999 match(Set mem (StoreCM mem zero));
7000
7001 ins_cost(125); // XXX
7002 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
7003 ins_encode %{
7004 __ movb($mem$$Address, r12);
7005 %}
7006 ins_pipe(ialu_mem_reg);
7007 %}
7008
7009 instruct storeImmCM0(memory mem, immI0 src)
7010 %{
7011 match(Set mem (StoreCM mem src));
7012
7013 ins_cost(150); // XXX
7014 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
7015 opcode(0xC6); /* C6 /0 */
7016 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
7017 ins_pipe(ialu_mem_imm);
7018 %}
7019
7020 // Store Aligned Packed Single Float XMM register to memory
7021 instruct storeA2F(memory mem, regD src) %{
7022 match(Set mem (Store2F mem src));
7023 ins_cost(145);
7024 format %{ "MOVQ $mem,$src\t! packed2F" %}
7025 ins_encode( movq_st(mem, src));
7026 ins_pipe( pipe_slow );
7027 %}
7028
7029 // Store Float
7030 instruct storeF(memory mem, regF src)
7031 %{
7032 match(Set mem (StoreF mem src));
7033
7034 ins_cost(95); // XXX
7035 format %{ "movss $mem, $src\t# float" %}
7036 opcode(0xF3, 0x0F, 0x11);
7037 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
7038 ins_pipe(pipe_slow); // XXX
7039 %}
7040
7041 // Store immediate Float value (it is faster than store from XMM register)
7042 instruct storeF0(memory mem, immF0 zero)
7043 %{
7044 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
7045 match(Set mem (StoreF mem zero));
7046
7047 ins_cost(25); // XXX
7048 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
7049 ins_encode %{
7050 __ movl($mem$$Address, r12);
7051 %}
7052 ins_pipe(ialu_mem_reg);
7053 %}
7054
7055 instruct storeF_imm(memory mem, immF src)
7056 %{
7057 match(Set mem (StoreF mem src));
7058
7059 ins_cost(50);
7060 format %{ "movl $mem, $src\t# float" %}
7061 opcode(0xC7); /* C7 /0 */
7062 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
7063 ins_pipe(ialu_mem_imm);
7064 %}
7065
7066 // Store Double
7067 instruct storeD(memory mem, regD src)
7068 %{
7069 match(Set mem (StoreD mem src));
7070
7071 ins_cost(95); // XXX
7072 format %{ "movsd $mem, $src\t# double" %}
7073 opcode(0xF2, 0x0F, 0x11);
7074 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
7075 ins_pipe(pipe_slow); // XXX
7076 %}
7077
7078 // Store immediate double 0.0 (it is faster than store from XMM register)
7079 instruct storeD0_imm(memory mem, immD0 src)
7080 %{
7081 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
7082 match(Set mem (StoreD mem src));
7083
7084 ins_cost(50);
7085 format %{ "movq $mem, $src\t# double 0." %}
7086 opcode(0xC7); /* C7 /0 */
7087 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
7088 ins_pipe(ialu_mem_imm);
7089 %}
7090
7091 instruct storeD0(memory mem, immD0 zero)
7092 %{
7093 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
7094 match(Set mem (StoreD mem zero));
7095
7096 ins_cost(25); // XXX
7097 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
7098 ins_encode %{
7099 __ movq($mem$$Address, r12);
7100 %}
7101 ins_pipe(ialu_mem_reg);
7102 %}
7103
7104 instruct storeSSI(stackSlotI dst, rRegI src)
7105 %{
7106 match(Set dst src);
7107
7108 ins_cost(100);
7109 format %{ "movl $dst, $src\t# int stk" %}
7110 opcode(0x89);
7111 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7112 ins_pipe( ialu_mem_reg );
7113 %}
7114
7115 instruct storeSSL(stackSlotL dst, rRegL src)
7116 %{
7117 match(Set dst src);
7118
7119 ins_cost(100);
7120 format %{ "movq $dst, $src\t# long stk" %}
7121 opcode(0x89);
7122 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7123 ins_pipe(ialu_mem_reg);
7124 %}
7125
7126 instruct storeSSP(stackSlotP dst, rRegP src)
7127 %{
7128 match(Set dst src);
7129
7130 ins_cost(100);
7131 format %{ "movq $dst, $src\t# ptr stk" %}
7132 opcode(0x89);
7133 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7134 ins_pipe(ialu_mem_reg);
7135 %}
7136
7137 instruct storeSSF(stackSlotF dst, regF src)
7138 %{
7139 match(Set dst src);
7140
7141 ins_cost(95); // XXX
7142 format %{ "movss $dst, $src\t# float stk" %}
7143 opcode(0xF3, 0x0F, 0x11);
7144 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
7145 ins_pipe(pipe_slow); // XXX
7146 %}
7147
7148 instruct storeSSD(stackSlotD dst, regD src)
7149 %{
7150 match(Set dst src);
7151
7152 ins_cost(95); // XXX
7153 format %{ "movsd $dst, $src\t# double stk" %}
7154 opcode(0xF2, 0x0F, 0x11);
7155 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
7156 ins_pipe(pipe_slow); // XXX
7157 %}
7158
7159 //----------BSWAP Instructions-------------------------------------------------
7160 instruct bytes_reverse_int(rRegI dst) %{
7161 match(Set dst (ReverseBytesI dst));
7162
7163 format %{ "bswapl $dst" %}
7164 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
7165 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
7166 ins_pipe( ialu_reg );
7167 %}
7168
7169 instruct bytes_reverse_long(rRegL dst) %{
7170 match(Set dst (ReverseBytesL dst));
7171
7172 format %{ "bswapq $dst" %}
7173
7174 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
7175 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
7176 ins_pipe( ialu_reg);
7177 %}
7178
7179 instruct bytes_reverse_unsigned_short(rRegI dst) %{
7180 match(Set dst (ReverseBytesUS dst));
7181
7182 format %{ "bswapl $dst\n\t"
7183 "shrl $dst,16\n\t" %}
7184 ins_encode %{
7185 __ bswapl($dst$$Register);
7186 __ shrl($dst$$Register, 16);
7187 %}
7188 ins_pipe( ialu_reg );
7189 %}
7190
7191 instruct bytes_reverse_short(rRegI dst) %{
7192 match(Set dst (ReverseBytesS dst));
7193
7194 format %{ "bswapl $dst\n\t"
7195 "sar $dst,16\n\t" %}
7196 ins_encode %{
7197 __ bswapl($dst$$Register);
7198 __ sarl($dst$$Register, 16);
7199 %}
7200 ins_pipe( ialu_reg );
7201 %}
7202
7203 //---------- Zeros Count Instructions ------------------------------------------
7204
7205 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
7206 predicate(UseCountLeadingZerosInstruction);
7207 match(Set dst (CountLeadingZerosI src));
7208 effect(KILL cr);
7209
7210 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
7211 ins_encode %{
7212 __ lzcntl($dst$$Register, $src$$Register);
7213 %}
7214 ins_pipe(ialu_reg);
7215 %}
7216
7217 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
7218 predicate(!UseCountLeadingZerosInstruction);
7219 match(Set dst (CountLeadingZerosI src));
7220 effect(KILL cr);
7221
7222 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
7223 "jnz skip\n\t"
7224 "movl $dst, -1\n"
7225 "skip:\n\t"
7226 "negl $dst\n\t"
7227 "addl $dst, 31" %}
7228 ins_encode %{
7229 Register Rdst = $dst$$Register;
7230 Register Rsrc = $src$$Register;
7231 Label skip;
7232 __ bsrl(Rdst, Rsrc);
7233 __ jccb(Assembler::notZero, skip);
7234 __ movl(Rdst, -1);
7235 __ bind(skip);
7236 __ negl(Rdst);
7237 __ addl(Rdst, BitsPerInt - 1);
7238 %}
7239 ins_pipe(ialu_reg);
7240 %}
7241
7242 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
7243 predicate(UseCountLeadingZerosInstruction);
7244 match(Set dst (CountLeadingZerosL src));
7245 effect(KILL cr);
7246
7247 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
7248 ins_encode %{
7249 __ lzcntq($dst$$Register, $src$$Register);
7250 %}
7251 ins_pipe(ialu_reg);
7252 %}
7253
7254 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
7255 predicate(!UseCountLeadingZerosInstruction);
7256 match(Set dst (CountLeadingZerosL src));
7257 effect(KILL cr);
7258
7259 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
7260 "jnz skip\n\t"
7261 "movl $dst, -1\n"
7262 "skip:\n\t"
7263 "negl $dst\n\t"
7264 "addl $dst, 63" %}
7265 ins_encode %{
7266 Register Rdst = $dst$$Register;
7267 Register Rsrc = $src$$Register;
7268 Label skip;
7269 __ bsrq(Rdst, Rsrc);
7270 __ jccb(Assembler::notZero, skip);
7271 __ movl(Rdst, -1);
7272 __ bind(skip);
7273 __ negl(Rdst);
7274 __ addl(Rdst, BitsPerLong - 1);
7275 %}
7276 ins_pipe(ialu_reg);
7277 %}
7278
7279 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
7280 match(Set dst (CountTrailingZerosI src));
7281 effect(KILL cr);
7282
7283 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
7284 "jnz done\n\t"
7285 "movl $dst, 32\n"
7286 "done:" %}
7287 ins_encode %{
7288 Register Rdst = $dst$$Register;
7289 Label done;
7290 __ bsfl(Rdst, $src$$Register);
7291 __ jccb(Assembler::notZero, done);
7292 __ movl(Rdst, BitsPerInt);
7293 __ bind(done);
7294 %}
7295 ins_pipe(ialu_reg);
7296 %}
7297
7298 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
7299 match(Set dst (CountTrailingZerosL src));
7300 effect(KILL cr);
7301
7302 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
7303 "jnz done\n\t"
7304 "movl $dst, 64\n"
7305 "done:" %}
7306 ins_encode %{
7307 Register Rdst = $dst$$Register;
7308 Label done;
7309 __ bsfq(Rdst, $src$$Register);
7310 __ jccb(Assembler::notZero, done);
7311 __ movl(Rdst, BitsPerLong);
7312 __ bind(done);
7313 %}
7314 ins_pipe(ialu_reg);
7315 %}
7316
7317
7318 //---------- Population Count Instructions -------------------------------------
7319
7320 instruct popCountI(rRegI dst, rRegI src) %{
7321 predicate(UsePopCountInstruction);
7322 match(Set dst (PopCountI src));
7323
7324 format %{ "popcnt $dst, $src" %}
7325 ins_encode %{
7326 __ popcntl($dst$$Register, $src$$Register);
7327 %}
7328 ins_pipe(ialu_reg);
7329 %}
7330
7331 instruct popCountI_mem(rRegI dst, memory mem) %{
7332 predicate(UsePopCountInstruction);
7333 match(Set dst (PopCountI (LoadI mem)));
7334
7335 format %{ "popcnt $dst, $mem" %}
7336 ins_encode %{
7337 __ popcntl($dst$$Register, $mem$$Address);
7338 %}
7339 ins_pipe(ialu_reg);
7340 %}
7341
7342 // Note: Long.bitCount(long) returns an int.
7343 instruct popCountL(rRegI dst, rRegL src) %{
7344 predicate(UsePopCountInstruction);
7345 match(Set dst (PopCountL src));
7346
7347 format %{ "popcnt $dst, $src" %}
7348 ins_encode %{
7349 __ popcntq($dst$$Register, $src$$Register);
7350 %}
7351 ins_pipe(ialu_reg);
7352 %}
7353
7354 // Note: Long.bitCount(long) returns an int.
7355 instruct popCountL_mem(rRegI dst, memory mem) %{
7356 predicate(UsePopCountInstruction);
7357 match(Set dst (PopCountL (LoadL mem)));
7358
7359 format %{ "popcnt $dst, $mem" %}
7360 ins_encode %{
7361 __ popcntq($dst$$Register, $mem$$Address);
7362 %}
7363 ins_pipe(ialu_reg);
7364 %}
7365
7366
7367 //----------MemBar Instructions-----------------------------------------------
7368 // Memory barrier flavors
7369
7370 instruct membar_acquire()
7371 %{
7372 match(MemBarAcquire);
7373 ins_cost(0);
7374
7375 size(0);
7376 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7377 ins_encode();
7378 ins_pipe(empty);
7379 %}
7380
7381 instruct membar_acquire_lock()
7382 %{
7383 match(MemBarAcquire);
7384 predicate(Matcher::prior_fast_lock(n));
7385 ins_cost(0);
7386
7387 size(0);
7388 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7389 ins_encode();
7390 ins_pipe(empty);
7391 %}
7392
7393 instruct membar_release()
7394 %{
7395 match(MemBarRelease);
7396 ins_cost(0);
7397
7398 size(0);
7399 format %{ "MEMBAR-release ! (empty encoding)" %}
7400 ins_encode();
7401 ins_pipe(empty);
7402 %}
7403
7404 instruct membar_release_lock()
7405 %{
7406 match(MemBarRelease);
7407 predicate(Matcher::post_fast_unlock(n));
7408 ins_cost(0);
7409
7410 size(0);
7411 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7412 ins_encode();
7413 ins_pipe(empty);
7414 %}
7415
7416 instruct membar_volatile(rFlagsReg cr) %{
7417 match(MemBarVolatile);
7418 effect(KILL cr);
7419 ins_cost(400);
7420
7421 format %{
7422 $$template
7423 if (os::is_MP()) {
7424 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
7425 } else {
7426 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7427 }
7428 %}
7429 ins_encode %{
7430 __ membar(Assembler::StoreLoad);
7431 %}
7432 ins_pipe(pipe_slow);
7433 %}
7434
7435 instruct unnecessary_membar_volatile()
7436 %{
7437 match(MemBarVolatile);
7438 predicate(Matcher::post_store_load_barrier(n));
7439 ins_cost(0);
7440
7441 size(0);
7442 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7443 ins_encode();
7444 ins_pipe(empty);
7445 %}
7446
7447 //----------Move Instructions--------------------------------------------------
7448
7449 instruct castX2P(rRegP dst, rRegL src)
7450 %{
7451 match(Set dst (CastX2P src));
7452
7453 format %{ "movq $dst, $src\t# long->ptr" %}
7454 ins_encode(enc_copy_wide(dst, src));
7455 ins_pipe(ialu_reg_reg); // XXX
7456 %}
7457
7458 instruct castP2X(rRegL dst, rRegP src)
7459 %{
7460 match(Set dst (CastP2X src));
7461
7462 format %{ "movq $dst, $src\t# ptr -> long" %}
7463 ins_encode(enc_copy_wide(dst, src));
7464 ins_pipe(ialu_reg_reg); // XXX
7465 %}
7466
7467
7468 // Convert oop pointer into compressed form
7469 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
7470 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
7471 match(Set dst (EncodeP src));
7472 effect(KILL cr);
7473 format %{ "encode_heap_oop $dst,$src" %}
7474 ins_encode %{
7475 Register s = $src$$Register;
7476 Register d = $dst$$Register;
7477 if (s != d) {
7478 __ movq(d, s);
7479 }
7480 __ encode_heap_oop(d);
7481 %}
7482 ins_pipe(ialu_reg_long);
7483 %}
7484
7485 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
7486 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
7487 match(Set dst (EncodeP src));
7488 effect(KILL cr);
7489 format %{ "encode_heap_oop_not_null $dst,$src" %}
7490 ins_encode %{
7491 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
7492 %}
7493 ins_pipe(ialu_reg_long);
7494 %}
7495
7496 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
7497 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
7498 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
7499 match(Set dst (DecodeN src));
7500 effect(KILL cr);
7501 format %{ "decode_heap_oop $dst,$src" %}
7502 ins_encode %{
7503 Register s = $src$$Register;
7504 Register d = $dst$$Register;
7505 if (s != d) {
7506 __ movq(d, s);
7507 }
7508 __ decode_heap_oop(d);
7509 %}
7510 ins_pipe(ialu_reg_long);
7511 %}
7512
7513 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
7514 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
7515 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
7516 match(Set dst (DecodeN src));
7517 effect(KILL cr);
7518 format %{ "decode_heap_oop_not_null $dst,$src" %}
7519 ins_encode %{
7520 Register s = $src$$Register;
7521 Register d = $dst$$Register;
7522 if (s != d) {
7523 __ decode_heap_oop_not_null(d, s);
7524 } else {
7525 __ decode_heap_oop_not_null(d);
7526 }
7527 %}
7528 ins_pipe(ialu_reg_long);
7529 %}
7530
7531
7532 //----------Conditional Move---------------------------------------------------
7533 // Jump
7534 // dummy instruction for generating temp registers
7535 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
7536 match(Jump (LShiftL switch_val shift));
7537 ins_cost(350);
7538 predicate(false);
7539 effect(TEMP dest);
7540
7541 format %{ "leaq $dest, [$constantaddress]\n\t"
7542 "jmp [$dest + $switch_val << $shift]\n\t" %}
7543 ins_encode %{
7544 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7545 // to do that and the compiler is using that register as one it can allocate.
7546 // So we build it all by hand.
7547 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
7548 // ArrayAddress dispatch(table, index);
7549 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
7550 __ lea($dest$$Register, $constantaddress);
7551 __ jmp(dispatch);
7552 %}
7553 ins_pipe(pipe_jmp);
7554 ins_pc_relative(1);
7555 %}
7556
7557 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
7558 match(Jump (AddL (LShiftL switch_val shift) offset));
7559 ins_cost(350);
7560 effect(TEMP dest);
7561
7562 format %{ "leaq $dest, [$constantaddress]\n\t"
7563 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
7564 ins_encode %{
7565 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7566 // to do that and the compiler is using that register as one it can allocate.
7567 // So we build it all by hand.
7568 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
7569 // ArrayAddress dispatch(table, index);
7570 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
7571 __ lea($dest$$Register, $constantaddress);
7572 __ jmp(dispatch);
7573 %}
7574 ins_pipe(pipe_jmp);
7575 ins_pc_relative(1);
7576 %}
7577
7578 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
7579 match(Jump switch_val);
7580 ins_cost(350);
7581 effect(TEMP dest);
7582
7583 format %{ "leaq $dest, [$constantaddress]\n\t"
7584 "jmp [$dest + $switch_val]\n\t" %}
7585 ins_encode %{
7586 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7587 // to do that and the compiler is using that register as one it can allocate.
7588 // So we build it all by hand.
7589 // Address index(noreg, switch_reg, Address::times_1);
7590 // ArrayAddress dispatch(table, index);
7591 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
7592 __ lea($dest$$Register, $constantaddress);
7593 __ jmp(dispatch);
7594 %}
7595 ins_pipe(pipe_jmp);
7596 ins_pc_relative(1);
7597 %}
7598
7599 // Conditional move
7600 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
7601 %{
7602 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7603
7604 ins_cost(200); // XXX
7605 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7606 opcode(0x0F, 0x40);
7607 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7608 ins_pipe(pipe_cmov_reg);
7609 %}
7610
7611 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
7612 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7613
7614 ins_cost(200); // XXX
7615 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7616 opcode(0x0F, 0x40);
7617 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7618 ins_pipe(pipe_cmov_reg);
7619 %}
7620
7621 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
7622 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7623 ins_cost(200);
7624 expand %{
7625 cmovI_regU(cop, cr, dst, src);
7626 %}
7627 %}
7628
7629 // Conditional move
7630 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7631 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7632
7633 ins_cost(250); // XXX
7634 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7635 opcode(0x0F, 0x40);
7636 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7637 ins_pipe(pipe_cmov_mem);
7638 %}
7639
7640 // Conditional move
7641 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7642 %{
7643 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7644
7645 ins_cost(250); // XXX
7646 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7647 opcode(0x0F, 0x40);
7648 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7649 ins_pipe(pipe_cmov_mem);
7650 %}
7651
7652 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7653 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7654 ins_cost(250);
7655 expand %{
7656 cmovI_memU(cop, cr, dst, src);
7657 %}
7658 %}
7659
7660 // Conditional move
7661 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7662 %{
7663 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7664
7665 ins_cost(200); // XXX
7666 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7667 opcode(0x0F, 0x40);
7668 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7669 ins_pipe(pipe_cmov_reg);
7670 %}
7671
7672 // Conditional move
7673 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7674 %{
7675 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7676
7677 ins_cost(200); // XXX
7678 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7679 opcode(0x0F, 0x40);
7680 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7681 ins_pipe(pipe_cmov_reg);
7682 %}
7683
7684 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7685 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7686 ins_cost(200);
7687 expand %{
7688 cmovN_regU(cop, cr, dst, src);
7689 %}
7690 %}
7691
7692 // Conditional move
7693 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7694 %{
7695 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7696
7697 ins_cost(200); // XXX
7698 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7699 opcode(0x0F, 0x40);
7700 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7701 ins_pipe(pipe_cmov_reg); // XXX
7702 %}
7703
7704 // Conditional move
7705 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7706 %{
7707 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7708
7709 ins_cost(200); // XXX
7710 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7711 opcode(0x0F, 0x40);
7712 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7713 ins_pipe(pipe_cmov_reg); // XXX
7714 %}
7715
7716 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7717 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7718 ins_cost(200);
7719 expand %{
7720 cmovP_regU(cop, cr, dst, src);
7721 %}
7722 %}
7723
7724 // DISABLED: Requires the ADLC to emit a bottom_type call that
7725 // correctly meets the two pointer arguments; one is an incoming
7726 // register but the other is a memory operand. ALSO appears to
7727 // be buggy with implicit null checks.
7728 //
7729 //// Conditional move
7730 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7731 //%{
7732 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7733 // ins_cost(250);
7734 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7735 // opcode(0x0F,0x40);
7736 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7737 // ins_pipe( pipe_cmov_mem );
7738 //%}
7739 //
7740 //// Conditional move
7741 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7742 //%{
7743 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7744 // ins_cost(250);
7745 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7746 // opcode(0x0F,0x40);
7747 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7748 // ins_pipe( pipe_cmov_mem );
7749 //%}
7750
7751 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7752 %{
7753 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7754
7755 ins_cost(200); // XXX
7756 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7757 opcode(0x0F, 0x40);
7758 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7759 ins_pipe(pipe_cmov_reg); // XXX
7760 %}
7761
7762 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7763 %{
7764 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7765
7766 ins_cost(200); // XXX
7767 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7768 opcode(0x0F, 0x40);
7769 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7770 ins_pipe(pipe_cmov_mem); // XXX
7771 %}
7772
7773 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7774 %{
7775 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7776
7777 ins_cost(200); // XXX
7778 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7779 opcode(0x0F, 0x40);
7780 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7781 ins_pipe(pipe_cmov_reg); // XXX
7782 %}
7783
7784 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7785 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7786 ins_cost(200);
7787 expand %{
7788 cmovL_regU(cop, cr, dst, src);
7789 %}
7790 %}
7791
7792 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7793 %{
7794 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7795
7796 ins_cost(200); // XXX
7797 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7798 opcode(0x0F, 0x40);
7799 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7800 ins_pipe(pipe_cmov_mem); // XXX
7801 %}
7802
7803 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7804 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7805 ins_cost(200);
7806 expand %{
7807 cmovL_memU(cop, cr, dst, src);
7808 %}
7809 %}
7810
7811 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7812 %{
7813 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7814
7815 ins_cost(200); // XXX
7816 format %{ "jn$cop skip\t# signed cmove float\n\t"
7817 "movss $dst, $src\n"
7818 "skip:" %}
7819 ins_encode(enc_cmovf_branch(cop, dst, src));
7820 ins_pipe(pipe_slow);
7821 %}
7822
7823 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7824 // %{
7825 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7826
7827 // ins_cost(200); // XXX
7828 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7829 // "movss $dst, $src\n"
7830 // "skip:" %}
7831 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7832 // ins_pipe(pipe_slow);
7833 // %}
7834
7835 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7836 %{
7837 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7838
7839 ins_cost(200); // XXX
7840 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7841 "movss $dst, $src\n"
7842 "skip:" %}
7843 ins_encode(enc_cmovf_branch(cop, dst, src));
7844 ins_pipe(pipe_slow);
7845 %}
7846
7847 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7848 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7849 ins_cost(200);
7850 expand %{
7851 cmovF_regU(cop, cr, dst, src);
7852 %}
7853 %}
7854
7855 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7856 %{
7857 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7858
7859 ins_cost(200); // XXX
7860 format %{ "jn$cop skip\t# signed cmove double\n\t"
7861 "movsd $dst, $src\n"
7862 "skip:" %}
7863 ins_encode(enc_cmovd_branch(cop, dst, src));
7864 ins_pipe(pipe_slow);
7865 %}
7866
7867 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7868 %{
7869 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7870
7871 ins_cost(200); // XXX
7872 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7873 "movsd $dst, $src\n"
7874 "skip:" %}
7875 ins_encode(enc_cmovd_branch(cop, dst, src));
7876 ins_pipe(pipe_slow);
7877 %}
7878
7879 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7880 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7881 ins_cost(200);
7882 expand %{
7883 cmovD_regU(cop, cr, dst, src);
7884 %}
7885 %}
7886
7887 //----------Arithmetic Instructions--------------------------------------------
7888 //----------Addition Instructions----------------------------------------------
7889
7890 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7891 %{
7892 match(Set dst (AddI dst src));
7893 effect(KILL cr);
7894
7895 format %{ "addl $dst, $src\t# int" %}
7896 opcode(0x03);
7897 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7898 ins_pipe(ialu_reg_reg);
7899 %}
7900
7901 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7902 %{
7903 match(Set dst (AddI dst src));
7904 effect(KILL cr);
7905
7906 format %{ "addl $dst, $src\t# int" %}
7907 opcode(0x81, 0x00); /* /0 id */
7908 ins_encode(OpcSErm(dst, src), Con8or32(src));
7909 ins_pipe( ialu_reg );
7910 %}
7911
7912 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7913 %{
7914 match(Set dst (AddI dst (LoadI src)));
7915 effect(KILL cr);
7916
7917 ins_cost(125); // XXX
7918 format %{ "addl $dst, $src\t# int" %}
7919 opcode(0x03);
7920 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7921 ins_pipe(ialu_reg_mem);
7922 %}
7923
7924 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7925 %{
7926 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7927 effect(KILL cr);
7928
7929 ins_cost(150); // XXX
7930 format %{ "addl $dst, $src\t# int" %}
7931 opcode(0x01); /* Opcode 01 /r */
7932 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7933 ins_pipe(ialu_mem_reg);
7934 %}
7935
7936 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7937 %{
7938 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7939 effect(KILL cr);
7940
7941 ins_cost(125); // XXX
7942 format %{ "addl $dst, $src\t# int" %}
7943 opcode(0x81); /* Opcode 81 /0 id */
7944 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7945 ins_pipe(ialu_mem_imm);
7946 %}
7947
7948 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7949 %{
7950 predicate(UseIncDec);
7951 match(Set dst (AddI dst src));
7952 effect(KILL cr);
7953
7954 format %{ "incl $dst\t# int" %}
7955 opcode(0xFF, 0x00); // FF /0
7956 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7957 ins_pipe(ialu_reg);
7958 %}
7959
7960 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7961 %{
7962 predicate(UseIncDec);
7963 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7964 effect(KILL cr);
7965
7966 ins_cost(125); // XXX
7967 format %{ "incl $dst\t# int" %}
7968 opcode(0xFF); /* Opcode FF /0 */
7969 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7970 ins_pipe(ialu_mem_imm);
7971 %}
7972
7973 // XXX why does that use AddI
7974 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7975 %{
7976 predicate(UseIncDec);
7977 match(Set dst (AddI dst src));
7978 effect(KILL cr);
7979
7980 format %{ "decl $dst\t# int" %}
7981 opcode(0xFF, 0x01); // FF /1
7982 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7983 ins_pipe(ialu_reg);
7984 %}
7985
7986 // XXX why does that use AddI
7987 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7988 %{
7989 predicate(UseIncDec);
7990 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7991 effect(KILL cr);
7992
7993 ins_cost(125); // XXX
7994 format %{ "decl $dst\t# int" %}
7995 opcode(0xFF); /* Opcode FF /1 */
7996 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7997 ins_pipe(ialu_mem_imm);
7998 %}
7999
8000 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
8001 %{
8002 match(Set dst (AddI src0 src1));
8003
8004 ins_cost(110);
8005 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
8006 opcode(0x8D); /* 0x8D /r */
8007 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
8008 ins_pipe(ialu_reg_reg);
8009 %}
8010
8011 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8012 %{
8013 match(Set dst (AddL dst src));
8014 effect(KILL cr);
8015
8016 format %{ "addq $dst, $src\t# long" %}
8017 opcode(0x03);
8018 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8019 ins_pipe(ialu_reg_reg);
8020 %}
8021
8022 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
8023 %{
8024 match(Set dst (AddL dst src));
8025 effect(KILL cr);
8026
8027 format %{ "addq $dst, $src\t# long" %}
8028 opcode(0x81, 0x00); /* /0 id */
8029 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8030 ins_pipe( ialu_reg );
8031 %}
8032
8033 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8034 %{
8035 match(Set dst (AddL dst (LoadL src)));
8036 effect(KILL cr);
8037
8038 ins_cost(125); // XXX
8039 format %{ "addq $dst, $src\t# long" %}
8040 opcode(0x03);
8041 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8042 ins_pipe(ialu_reg_mem);
8043 %}
8044
8045 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8046 %{
8047 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
8048 effect(KILL cr);
8049
8050 ins_cost(150); // XXX
8051 format %{ "addq $dst, $src\t# long" %}
8052 opcode(0x01); /* Opcode 01 /r */
8053 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8054 ins_pipe(ialu_mem_reg);
8055 %}
8056
8057 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8058 %{
8059 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
8060 effect(KILL cr);
8061
8062 ins_cost(125); // XXX
8063 format %{ "addq $dst, $src\t# long" %}
8064 opcode(0x81); /* Opcode 81 /0 id */
8065 ins_encode(REX_mem_wide(dst),
8066 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
8067 ins_pipe(ialu_mem_imm);
8068 %}
8069
8070 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
8071 %{
8072 predicate(UseIncDec);
8073 match(Set dst (AddL dst src));
8074 effect(KILL cr);
8075
8076 format %{ "incq $dst\t# long" %}
8077 opcode(0xFF, 0x00); // FF /0
8078 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8079 ins_pipe(ialu_reg);
8080 %}
8081
8082 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
8083 %{
8084 predicate(UseIncDec);
8085 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
8086 effect(KILL cr);
8087
8088 ins_cost(125); // XXX
8089 format %{ "incq $dst\t# long" %}
8090 opcode(0xFF); /* Opcode FF /0 */
8091 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
8092 ins_pipe(ialu_mem_imm);
8093 %}
8094
8095 // XXX why does that use AddL
8096 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
8097 %{
8098 predicate(UseIncDec);
8099 match(Set dst (AddL dst src));
8100 effect(KILL cr);
8101
8102 format %{ "decq $dst\t# long" %}
8103 opcode(0xFF, 0x01); // FF /1
8104 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8105 ins_pipe(ialu_reg);
8106 %}
8107
8108 // XXX why does that use AddL
8109 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
8110 %{
8111 predicate(UseIncDec);
8112 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
8113 effect(KILL cr);
8114
8115 ins_cost(125); // XXX
8116 format %{ "decq $dst\t# long" %}
8117 opcode(0xFF); /* Opcode FF /1 */
8118 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
8119 ins_pipe(ialu_mem_imm);
8120 %}
8121
8122 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
8123 %{
8124 match(Set dst (AddL src0 src1));
8125
8126 ins_cost(110);
8127 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
8128 opcode(0x8D); /* 0x8D /r */
8129 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
8130 ins_pipe(ialu_reg_reg);
8131 %}
8132
8133 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
8134 %{
8135 match(Set dst (AddP dst src));
8136 effect(KILL cr);
8137
8138 format %{ "addq $dst, $src\t# ptr" %}
8139 opcode(0x03);
8140 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8141 ins_pipe(ialu_reg_reg);
8142 %}
8143
8144 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
8145 %{
8146 match(Set dst (AddP dst src));
8147 effect(KILL cr);
8148
8149 format %{ "addq $dst, $src\t# ptr" %}
8150 opcode(0x81, 0x00); /* /0 id */
8151 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8152 ins_pipe( ialu_reg );
8153 %}
8154
8155 // XXX addP mem ops ????
8156
8157 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
8158 %{
8159 match(Set dst (AddP src0 src1));
8160
8161 ins_cost(110);
8162 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
8163 opcode(0x8D); /* 0x8D /r */
8164 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
8165 ins_pipe(ialu_reg_reg);
8166 %}
8167
8168 instruct checkCastPP(rRegP dst)
8169 %{
8170 match(Set dst (CheckCastPP dst));
8171
8172 size(0);
8173 format %{ "# checkcastPP of $dst" %}
8174 ins_encode(/* empty encoding */);
8175 ins_pipe(empty);
8176 %}
8177
8178 instruct castPP(rRegP dst)
8179 %{
8180 match(Set dst (CastPP dst));
8181
8182 size(0);
8183 format %{ "# castPP of $dst" %}
8184 ins_encode(/* empty encoding */);
8185 ins_pipe(empty);
8186 %}
8187
8188 instruct castII(rRegI dst)
8189 %{
8190 match(Set dst (CastII dst));
8191
8192 size(0);
8193 format %{ "# castII of $dst" %}
8194 ins_encode(/* empty encoding */);
8195 ins_cost(0);
8196 ins_pipe(empty);
8197 %}
8198
8199 // LoadP-locked same as a regular LoadP when used with compare-swap
8200 instruct loadPLocked(rRegP dst, memory mem)
8201 %{
8202 match(Set dst (LoadPLocked mem));
8203
8204 ins_cost(125); // XXX
8205 format %{ "movq $dst, $mem\t# ptr locked" %}
8206 opcode(0x8B);
8207 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
8208 ins_pipe(ialu_reg_mem); // XXX
8209 %}
8210
8211 // LoadL-locked - same as a regular LoadL when used with compare-swap
8212 instruct loadLLocked(rRegL dst, memory mem)
8213 %{
8214 match(Set dst (LoadLLocked mem));
8215
8216 ins_cost(125); // XXX
8217 format %{ "movq $dst, $mem\t# long locked" %}
8218 opcode(0x8B);
8219 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
8220 ins_pipe(ialu_reg_mem); // XXX
8221 %}
8222
8223 // Conditional-store of the updated heap-top.
8224 // Used during allocation of the shared heap.
8225 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8226
8227 instruct storePConditional(memory heap_top_ptr,
8228 rax_RegP oldval, rRegP newval,
8229 rFlagsReg cr)
8230 %{
8231 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8232
8233 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
8234 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
8235 opcode(0x0F, 0xB1);
8236 ins_encode(lock_prefix,
8237 REX_reg_mem_wide(newval, heap_top_ptr),
8238 OpcP, OpcS,
8239 reg_mem(newval, heap_top_ptr));
8240 ins_pipe(pipe_cmpxchg);
8241 %}
8242
8243 // Conditional-store of an int value.
8244 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
8245 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
8246 %{
8247 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8248 effect(KILL oldval);
8249
8250 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
8251 opcode(0x0F, 0xB1);
8252 ins_encode(lock_prefix,
8253 REX_reg_mem(newval, mem),
8254 OpcP, OpcS,
8255 reg_mem(newval, mem));
8256 ins_pipe(pipe_cmpxchg);
8257 %}
8258
8259 // Conditional-store of a long value.
8260 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
8261 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
8262 %{
8263 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8264 effect(KILL oldval);
8265
8266 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
8267 opcode(0x0F, 0xB1);
8268 ins_encode(lock_prefix,
8269 REX_reg_mem_wide(newval, mem),
8270 OpcP, OpcS,
8271 reg_mem(newval, mem));
8272 ins_pipe(pipe_cmpxchg);
8273 %}
8274
8275
8276 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8277 instruct compareAndSwapP(rRegI res,
8278 memory mem_ptr,
8279 rax_RegP oldval, rRegP newval,
8280 rFlagsReg cr)
8281 %{
8282 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8283 effect(KILL cr, KILL oldval);
8284
8285 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8286 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8287 "sete $res\n\t"
8288 "movzbl $res, $res" %}
8289 opcode(0x0F, 0xB1);
8290 ins_encode(lock_prefix,
8291 REX_reg_mem_wide(newval, mem_ptr),
8292 OpcP, OpcS,
8293 reg_mem(newval, mem_ptr),
8294 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8295 REX_reg_breg(res, res), // movzbl
8296 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8297 ins_pipe( pipe_cmpxchg );
8298 %}
8299
8300 instruct compareAndSwapL(rRegI res,
8301 memory mem_ptr,
8302 rax_RegL oldval, rRegL newval,
8303 rFlagsReg cr)
8304 %{
8305 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8306 effect(KILL cr, KILL oldval);
8307
8308 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8309 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8310 "sete $res\n\t"
8311 "movzbl $res, $res" %}
8312 opcode(0x0F, 0xB1);
8313 ins_encode(lock_prefix,
8314 REX_reg_mem_wide(newval, mem_ptr),
8315 OpcP, OpcS,
8316 reg_mem(newval, mem_ptr),
8317 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8318 REX_reg_breg(res, res), // movzbl
8319 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8320 ins_pipe( pipe_cmpxchg );
8321 %}
8322
8323 instruct compareAndSwapI(rRegI res,
8324 memory mem_ptr,
8325 rax_RegI oldval, rRegI newval,
8326 rFlagsReg cr)
8327 %{
8328 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8329 effect(KILL cr, KILL oldval);
8330
8331 format %{ "cmpxchgl $mem_ptr,$newval\t# "
8332 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8333 "sete $res\n\t"
8334 "movzbl $res, $res" %}
8335 opcode(0x0F, 0xB1);
8336 ins_encode(lock_prefix,
8337 REX_reg_mem(newval, mem_ptr),
8338 OpcP, OpcS,
8339 reg_mem(newval, mem_ptr),
8340 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8341 REX_reg_breg(res, res), // movzbl
8342 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8343 ins_pipe( pipe_cmpxchg );
8344 %}
8345
8346
8347 instruct compareAndSwapN(rRegI res,
8348 memory mem_ptr,
8349 rax_RegN oldval, rRegN newval,
8350 rFlagsReg cr) %{
8351 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
8352 effect(KILL cr, KILL oldval);
8353
8354 format %{ "cmpxchgl $mem_ptr,$newval\t# "
8355 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8356 "sete $res\n\t"
8357 "movzbl $res, $res" %}
8358 opcode(0x0F, 0xB1);
8359 ins_encode(lock_prefix,
8360 REX_reg_mem(newval, mem_ptr),
8361 OpcP, OpcS,
8362 reg_mem(newval, mem_ptr),
8363 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8364 REX_reg_breg(res, res), // movzbl
8365 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8366 ins_pipe( pipe_cmpxchg );
8367 %}
8368
8369 //----------Subtraction Instructions-------------------------------------------
8370
8371 // Integer Subtraction Instructions
8372 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8373 %{
8374 match(Set dst (SubI dst src));
8375 effect(KILL cr);
8376
8377 format %{ "subl $dst, $src\t# int" %}
8378 opcode(0x2B);
8379 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8380 ins_pipe(ialu_reg_reg);
8381 %}
8382
8383 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8384 %{
8385 match(Set dst (SubI dst src));
8386 effect(KILL cr);
8387
8388 format %{ "subl $dst, $src\t# int" %}
8389 opcode(0x81, 0x05); /* Opcode 81 /5 */
8390 ins_encode(OpcSErm(dst, src), Con8or32(src));
8391 ins_pipe(ialu_reg);
8392 %}
8393
8394 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8395 %{
8396 match(Set dst (SubI dst (LoadI src)));
8397 effect(KILL cr);
8398
8399 ins_cost(125);
8400 format %{ "subl $dst, $src\t# int" %}
8401 opcode(0x2B);
8402 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8403 ins_pipe(ialu_reg_mem);
8404 %}
8405
8406 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8407 %{
8408 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8409 effect(KILL cr);
8410
8411 ins_cost(150);
8412 format %{ "subl $dst, $src\t# int" %}
8413 opcode(0x29); /* Opcode 29 /r */
8414 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8415 ins_pipe(ialu_mem_reg);
8416 %}
8417
8418 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8419 %{
8420 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8421 effect(KILL cr);
8422
8423 ins_cost(125); // XXX
8424 format %{ "subl $dst, $src\t# int" %}
8425 opcode(0x81); /* Opcode 81 /5 id */
8426 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8427 ins_pipe(ialu_mem_imm);
8428 %}
8429
8430 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8431 %{
8432 match(Set dst (SubL dst src));
8433 effect(KILL cr);
8434
8435 format %{ "subq $dst, $src\t# long" %}
8436 opcode(0x2B);
8437 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8438 ins_pipe(ialu_reg_reg);
8439 %}
8440
8441 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8442 %{
8443 match(Set dst (SubL dst src));
8444 effect(KILL cr);
8445
8446 format %{ "subq $dst, $src\t# long" %}
8447 opcode(0x81, 0x05); /* Opcode 81 /5 */
8448 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8449 ins_pipe(ialu_reg);
8450 %}
8451
8452 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8453 %{
8454 match(Set dst (SubL dst (LoadL src)));
8455 effect(KILL cr);
8456
8457 ins_cost(125);
8458 format %{ "subq $dst, $src\t# long" %}
8459 opcode(0x2B);
8460 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8461 ins_pipe(ialu_reg_mem);
8462 %}
8463
8464 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8465 %{
8466 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8467 effect(KILL cr);
8468
8469 ins_cost(150);
8470 format %{ "subq $dst, $src\t# long" %}
8471 opcode(0x29); /* Opcode 29 /r */
8472 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8473 ins_pipe(ialu_mem_reg);
8474 %}
8475
8476 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8477 %{
8478 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8479 effect(KILL cr);
8480
8481 ins_cost(125); // XXX
8482 format %{ "subq $dst, $src\t# long" %}
8483 opcode(0x81); /* Opcode 81 /5 id */
8484 ins_encode(REX_mem_wide(dst),
8485 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8486 ins_pipe(ialu_mem_imm);
8487 %}
8488
8489 // Subtract from a pointer
8490 // XXX hmpf???
8491 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8492 %{
8493 match(Set dst (AddP dst (SubI zero src)));
8494 effect(KILL cr);
8495
8496 format %{ "subq $dst, $src\t# ptr - int" %}
8497 opcode(0x2B);
8498 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8499 ins_pipe(ialu_reg_reg);
8500 %}
8501
8502 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8503 %{
8504 match(Set dst (SubI zero dst));
8505 effect(KILL cr);
8506
8507 format %{ "negl $dst\t# int" %}
8508 opcode(0xF7, 0x03); // Opcode F7 /3
8509 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8510 ins_pipe(ialu_reg);
8511 %}
8512
8513 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8514 %{
8515 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8516 effect(KILL cr);
8517
8518 format %{ "negl $dst\t# int" %}
8519 opcode(0xF7, 0x03); // Opcode F7 /3
8520 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8521 ins_pipe(ialu_reg);
8522 %}
8523
8524 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8525 %{
8526 match(Set dst (SubL zero dst));
8527 effect(KILL cr);
8528
8529 format %{ "negq $dst\t# long" %}
8530 opcode(0xF7, 0x03); // Opcode F7 /3
8531 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8532 ins_pipe(ialu_reg);
8533 %}
8534
8535 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8536 %{
8537 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8538 effect(KILL cr);
8539
8540 format %{ "negq $dst\t# long" %}
8541 opcode(0xF7, 0x03); // Opcode F7 /3
8542 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8543 ins_pipe(ialu_reg);
8544 %}
8545
8546
8547 //----------Multiplication/Division Instructions-------------------------------
8548 // Integer Multiplication Instructions
8549 // Multiply Register
8550
8551 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8552 %{
8553 match(Set dst (MulI dst src));
8554 effect(KILL cr);
8555
8556 ins_cost(300);
8557 format %{ "imull $dst, $src\t# int" %}
8558 opcode(0x0F, 0xAF);
8559 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8560 ins_pipe(ialu_reg_reg_alu0);
8561 %}
8562
8563 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8564 %{
8565 match(Set dst (MulI src imm));
8566 effect(KILL cr);
8567
8568 ins_cost(300);
8569 format %{ "imull $dst, $src, $imm\t# int" %}
8570 opcode(0x69); /* 69 /r id */
8571 ins_encode(REX_reg_reg(dst, src),
8572 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8573 ins_pipe(ialu_reg_reg_alu0);
8574 %}
8575
8576 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8577 %{
8578 match(Set dst (MulI dst (LoadI src)));
8579 effect(KILL cr);
8580
8581 ins_cost(350);
8582 format %{ "imull $dst, $src\t# int" %}
8583 opcode(0x0F, 0xAF);
8584 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8585 ins_pipe(ialu_reg_mem_alu0);
8586 %}
8587
8588 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8589 %{
8590 match(Set dst (MulI (LoadI src) imm));
8591 effect(KILL cr);
8592
8593 ins_cost(300);
8594 format %{ "imull $dst, $src, $imm\t# int" %}
8595 opcode(0x69); /* 69 /r id */
8596 ins_encode(REX_reg_mem(dst, src),
8597 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8598 ins_pipe(ialu_reg_mem_alu0);
8599 %}
8600
8601 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8602 %{
8603 match(Set dst (MulL dst src));
8604 effect(KILL cr);
8605
8606 ins_cost(300);
8607 format %{ "imulq $dst, $src\t# long" %}
8608 opcode(0x0F, 0xAF);
8609 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8610 ins_pipe(ialu_reg_reg_alu0);
8611 %}
8612
8613 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8614 %{
8615 match(Set dst (MulL src imm));
8616 effect(KILL cr);
8617
8618 ins_cost(300);
8619 format %{ "imulq $dst, $src, $imm\t# long" %}
8620 opcode(0x69); /* 69 /r id */
8621 ins_encode(REX_reg_reg_wide(dst, src),
8622 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8623 ins_pipe(ialu_reg_reg_alu0);
8624 %}
8625
8626 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8627 %{
8628 match(Set dst (MulL dst (LoadL src)));
8629 effect(KILL cr);
8630
8631 ins_cost(350);
8632 format %{ "imulq $dst, $src\t# long" %}
8633 opcode(0x0F, 0xAF);
8634 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8635 ins_pipe(ialu_reg_mem_alu0);
8636 %}
8637
8638 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8639 %{
8640 match(Set dst (MulL (LoadL src) imm));
8641 effect(KILL cr);
8642
8643 ins_cost(300);
8644 format %{ "imulq $dst, $src, $imm\t# long" %}
8645 opcode(0x69); /* 69 /r id */
8646 ins_encode(REX_reg_mem_wide(dst, src),
8647 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8648 ins_pipe(ialu_reg_mem_alu0);
8649 %}
8650
8651 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8652 %{
8653 match(Set dst (MulHiL src rax));
8654 effect(USE_KILL rax, KILL cr);
8655
8656 ins_cost(300);
8657 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8658 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8659 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8660 ins_pipe(ialu_reg_reg_alu0);
8661 %}
8662
8663 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8664 rFlagsReg cr)
8665 %{
8666 match(Set rax (DivI rax div));
8667 effect(KILL rdx, KILL cr);
8668
8669 ins_cost(30*100+10*100); // XXX
8670 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8671 "jne,s normal\n\t"
8672 "xorl rdx, rdx\n\t"
8673 "cmpl $div, -1\n\t"
8674 "je,s done\n"
8675 "normal: cdql\n\t"
8676 "idivl $div\n"
8677 "done:" %}
8678 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8679 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8680 ins_pipe(ialu_reg_reg_alu0);
8681 %}
8682
8683 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8684 rFlagsReg cr)
8685 %{
8686 match(Set rax (DivL rax div));
8687 effect(KILL rdx, KILL cr);
8688
8689 ins_cost(30*100+10*100); // XXX
8690 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8691 "cmpq rax, rdx\n\t"
8692 "jne,s normal\n\t"
8693 "xorl rdx, rdx\n\t"
8694 "cmpq $div, -1\n\t"
8695 "je,s done\n"
8696 "normal: cdqq\n\t"
8697 "idivq $div\n"
8698 "done:" %}
8699 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8700 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8701 ins_pipe(ialu_reg_reg_alu0);
8702 %}
8703
8704 // Integer DIVMOD with Register, both quotient and mod results
8705 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8706 rFlagsReg cr)
8707 %{
8708 match(DivModI rax div);
8709 effect(KILL cr);
8710
8711 ins_cost(30*100+10*100); // XXX
8712 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8713 "jne,s normal\n\t"
8714 "xorl rdx, rdx\n\t"
8715 "cmpl $div, -1\n\t"
8716 "je,s done\n"
8717 "normal: cdql\n\t"
8718 "idivl $div\n"
8719 "done:" %}
8720 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8721 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8722 ins_pipe(pipe_slow);
8723 %}
8724
8725 // Long DIVMOD with Register, both quotient and mod results
8726 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8727 rFlagsReg cr)
8728 %{
8729 match(DivModL rax div);
8730 effect(KILL cr);
8731
8732 ins_cost(30*100+10*100); // XXX
8733 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8734 "cmpq rax, rdx\n\t"
8735 "jne,s normal\n\t"
8736 "xorl rdx, rdx\n\t"
8737 "cmpq $div, -1\n\t"
8738 "je,s done\n"
8739 "normal: cdqq\n\t"
8740 "idivq $div\n"
8741 "done:" %}
8742 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8743 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8744 ins_pipe(pipe_slow);
8745 %}
8746
8747 //----------- DivL-By-Constant-Expansions--------------------------------------
8748 // DivI cases are handled by the compiler
8749
8750 // Magic constant, reciprocal of 10
8751 instruct loadConL_0x6666666666666667(rRegL dst)
8752 %{
8753 effect(DEF dst);
8754
8755 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8756 ins_encode(load_immL(dst, 0x6666666666666667));
8757 ins_pipe(ialu_reg);
8758 %}
8759
8760 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8761 %{
8762 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8763
8764 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8765 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8766 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8767 ins_pipe(ialu_reg_reg_alu0);
8768 %}
8769
8770 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8771 %{
8772 effect(USE_DEF dst, KILL cr);
8773
8774 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8775 opcode(0xC1, 0x7); /* C1 /7 ib */
8776 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8777 ins_pipe(ialu_reg);
8778 %}
8779
8780 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8781 %{
8782 effect(USE_DEF dst, KILL cr);
8783
8784 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8785 opcode(0xC1, 0x7); /* C1 /7 ib */
8786 ins_encode(reg_opc_imm_wide(dst, 0x2));
8787 ins_pipe(ialu_reg);
8788 %}
8789
8790 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8791 %{
8792 match(Set dst (DivL src div));
8793
8794 ins_cost((5+8)*100);
8795 expand %{
8796 rax_RegL rax; // Killed temp
8797 rFlagsReg cr; // Killed
8798 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8799 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8800 sarL_rReg_63(src, cr); // sarq src, 63
8801 sarL_rReg_2(dst, cr); // sarq rdx, 2
8802 subL_rReg(dst, src, cr); // subl rdx, src
8803 %}
8804 %}
8805
8806 //-----------------------------------------------------------------------------
8807
8808 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8809 rFlagsReg cr)
8810 %{
8811 match(Set rdx (ModI rax div));
8812 effect(KILL rax, KILL cr);
8813
8814 ins_cost(300); // XXX
8815 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8816 "jne,s normal\n\t"
8817 "xorl rdx, rdx\n\t"
8818 "cmpl $div, -1\n\t"
8819 "je,s done\n"
8820 "normal: cdql\n\t"
8821 "idivl $div\n"
8822 "done:" %}
8823 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8824 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8825 ins_pipe(ialu_reg_reg_alu0);
8826 %}
8827
8828 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8829 rFlagsReg cr)
8830 %{
8831 match(Set rdx (ModL rax div));
8832 effect(KILL rax, KILL cr);
8833
8834 ins_cost(300); // XXX
8835 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8836 "cmpq rax, rdx\n\t"
8837 "jne,s normal\n\t"
8838 "xorl rdx, rdx\n\t"
8839 "cmpq $div, -1\n\t"
8840 "je,s done\n"
8841 "normal: cdqq\n\t"
8842 "idivq $div\n"
8843 "done:" %}
8844 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8845 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8846 ins_pipe(ialu_reg_reg_alu0);
8847 %}
8848
8849 // Integer Shift Instructions
8850 // Shift Left by one
8851 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8852 %{
8853 match(Set dst (LShiftI dst shift));
8854 effect(KILL cr);
8855
8856 format %{ "sall $dst, $shift" %}
8857 opcode(0xD1, 0x4); /* D1 /4 */
8858 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8859 ins_pipe(ialu_reg);
8860 %}
8861
8862 // Shift Left by one
8863 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8864 %{
8865 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8866 effect(KILL cr);
8867
8868 format %{ "sall $dst, $shift\t" %}
8869 opcode(0xD1, 0x4); /* D1 /4 */
8870 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8871 ins_pipe(ialu_mem_imm);
8872 %}
8873
8874 // Shift Left by 8-bit immediate
8875 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8876 %{
8877 match(Set dst (LShiftI dst shift));
8878 effect(KILL cr);
8879
8880 format %{ "sall $dst, $shift" %}
8881 opcode(0xC1, 0x4); /* C1 /4 ib */
8882 ins_encode(reg_opc_imm(dst, shift));
8883 ins_pipe(ialu_reg);
8884 %}
8885
8886 // Shift Left by 8-bit immediate
8887 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8888 %{
8889 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8890 effect(KILL cr);
8891
8892 format %{ "sall $dst, $shift" %}
8893 opcode(0xC1, 0x4); /* C1 /4 ib */
8894 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8895 ins_pipe(ialu_mem_imm);
8896 %}
8897
8898 // Shift Left by variable
8899 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8900 %{
8901 match(Set dst (LShiftI dst shift));
8902 effect(KILL cr);
8903
8904 format %{ "sall $dst, $shift" %}
8905 opcode(0xD3, 0x4); /* D3 /4 */
8906 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8907 ins_pipe(ialu_reg_reg);
8908 %}
8909
8910 // Shift Left by variable
8911 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8912 %{
8913 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8914 effect(KILL cr);
8915
8916 format %{ "sall $dst, $shift" %}
8917 opcode(0xD3, 0x4); /* D3 /4 */
8918 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8919 ins_pipe(ialu_mem_reg);
8920 %}
8921
8922 // Arithmetic shift right by one
8923 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8924 %{
8925 match(Set dst (RShiftI dst shift));
8926 effect(KILL cr);
8927
8928 format %{ "sarl $dst, $shift" %}
8929 opcode(0xD1, 0x7); /* D1 /7 */
8930 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8931 ins_pipe(ialu_reg);
8932 %}
8933
8934 // Arithmetic shift right by one
8935 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8936 %{
8937 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8938 effect(KILL cr);
8939
8940 format %{ "sarl $dst, $shift" %}
8941 opcode(0xD1, 0x7); /* D1 /7 */
8942 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8943 ins_pipe(ialu_mem_imm);
8944 %}
8945
8946 // Arithmetic Shift Right by 8-bit immediate
8947 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8948 %{
8949 match(Set dst (RShiftI dst shift));
8950 effect(KILL cr);
8951
8952 format %{ "sarl $dst, $shift" %}
8953 opcode(0xC1, 0x7); /* C1 /7 ib */
8954 ins_encode(reg_opc_imm(dst, shift));
8955 ins_pipe(ialu_mem_imm);
8956 %}
8957
8958 // Arithmetic Shift Right by 8-bit immediate
8959 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8960 %{
8961 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8962 effect(KILL cr);
8963
8964 format %{ "sarl $dst, $shift" %}
8965 opcode(0xC1, 0x7); /* C1 /7 ib */
8966 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8967 ins_pipe(ialu_mem_imm);
8968 %}
8969
8970 // Arithmetic Shift Right by variable
8971 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8972 %{
8973 match(Set dst (RShiftI dst shift));
8974 effect(KILL cr);
8975
8976 format %{ "sarl $dst, $shift" %}
8977 opcode(0xD3, 0x7); /* D3 /7 */
8978 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8979 ins_pipe(ialu_reg_reg);
8980 %}
8981
8982 // Arithmetic Shift Right by variable
8983 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8984 %{
8985 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8986 effect(KILL cr);
8987
8988 format %{ "sarl $dst, $shift" %}
8989 opcode(0xD3, 0x7); /* D3 /7 */
8990 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8991 ins_pipe(ialu_mem_reg);
8992 %}
8993
8994 // Logical shift right by one
8995 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8996 %{
8997 match(Set dst (URShiftI dst shift));
8998 effect(KILL cr);
8999
9000 format %{ "shrl $dst, $shift" %}
9001 opcode(0xD1, 0x5); /* D1 /5 */
9002 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9003 ins_pipe(ialu_reg);
9004 %}
9005
9006 // Logical shift right by one
9007 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9008 %{
9009 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9010 effect(KILL cr);
9011
9012 format %{ "shrl $dst, $shift" %}
9013 opcode(0xD1, 0x5); /* D1 /5 */
9014 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
9015 ins_pipe(ialu_mem_imm);
9016 %}
9017
9018 // Logical Shift Right by 8-bit immediate
9019 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9020 %{
9021 match(Set dst (URShiftI dst shift));
9022 effect(KILL cr);
9023
9024 format %{ "shrl $dst, $shift" %}
9025 opcode(0xC1, 0x5); /* C1 /5 ib */
9026 ins_encode(reg_opc_imm(dst, shift));
9027 ins_pipe(ialu_reg);
9028 %}
9029
9030 // Logical Shift Right by 8-bit immediate
9031 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9032 %{
9033 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9034 effect(KILL cr);
9035
9036 format %{ "shrl $dst, $shift" %}
9037 opcode(0xC1, 0x5); /* C1 /5 ib */
9038 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
9039 ins_pipe(ialu_mem_imm);
9040 %}
9041
9042 // Logical Shift Right by variable
9043 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9044 %{
9045 match(Set dst (URShiftI dst shift));
9046 effect(KILL cr);
9047
9048 format %{ "shrl $dst, $shift" %}
9049 opcode(0xD3, 0x5); /* D3 /5 */
9050 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9051 ins_pipe(ialu_reg_reg);
9052 %}
9053
9054 // Logical Shift Right by variable
9055 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9056 %{
9057 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9058 effect(KILL cr);
9059
9060 format %{ "shrl $dst, $shift" %}
9061 opcode(0xD3, 0x5); /* D3 /5 */
9062 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
9063 ins_pipe(ialu_mem_reg);
9064 %}
9065
9066 // Long Shift Instructions
9067 // Shift Left by one
9068 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9069 %{
9070 match(Set dst (LShiftL dst shift));
9071 effect(KILL cr);
9072
9073 format %{ "salq $dst, $shift" %}
9074 opcode(0xD1, 0x4); /* D1 /4 */
9075 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9076 ins_pipe(ialu_reg);
9077 %}
9078
9079 // Shift Left by one
9080 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9081 %{
9082 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9083 effect(KILL cr);
9084
9085 format %{ "salq $dst, $shift" %}
9086 opcode(0xD1, 0x4); /* D1 /4 */
9087 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9088 ins_pipe(ialu_mem_imm);
9089 %}
9090
9091 // Shift Left by 8-bit immediate
9092 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9093 %{
9094 match(Set dst (LShiftL dst shift));
9095 effect(KILL cr);
9096
9097 format %{ "salq $dst, $shift" %}
9098 opcode(0xC1, 0x4); /* C1 /4 ib */
9099 ins_encode(reg_opc_imm_wide(dst, shift));
9100 ins_pipe(ialu_reg);
9101 %}
9102
9103 // Shift Left by 8-bit immediate
9104 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9105 %{
9106 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9107 effect(KILL cr);
9108
9109 format %{ "salq $dst, $shift" %}
9110 opcode(0xC1, 0x4); /* C1 /4 ib */
9111 ins_encode(REX_mem_wide(dst), OpcP,
9112 RM_opc_mem(secondary, dst), Con8or32(shift));
9113 ins_pipe(ialu_mem_imm);
9114 %}
9115
9116 // Shift Left by variable
9117 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9118 %{
9119 match(Set dst (LShiftL dst shift));
9120 effect(KILL cr);
9121
9122 format %{ "salq $dst, $shift" %}
9123 opcode(0xD3, 0x4); /* D3 /4 */
9124 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9125 ins_pipe(ialu_reg_reg);
9126 %}
9127
9128 // Shift Left by variable
9129 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9130 %{
9131 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9132 effect(KILL cr);
9133
9134 format %{ "salq $dst, $shift" %}
9135 opcode(0xD3, 0x4); /* D3 /4 */
9136 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9137 ins_pipe(ialu_mem_reg);
9138 %}
9139
9140 // Arithmetic shift right by one
9141 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9142 %{
9143 match(Set dst (RShiftL dst shift));
9144 effect(KILL cr);
9145
9146 format %{ "sarq $dst, $shift" %}
9147 opcode(0xD1, 0x7); /* D1 /7 */
9148 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9149 ins_pipe(ialu_reg);
9150 %}
9151
9152 // Arithmetic shift right by one
9153 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9154 %{
9155 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9156 effect(KILL cr);
9157
9158 format %{ "sarq $dst, $shift" %}
9159 opcode(0xD1, 0x7); /* D1 /7 */
9160 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9161 ins_pipe(ialu_mem_imm);
9162 %}
9163
9164 // Arithmetic Shift Right by 8-bit immediate
9165 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9166 %{
9167 match(Set dst (RShiftL dst shift));
9168 effect(KILL cr);
9169
9170 format %{ "sarq $dst, $shift" %}
9171 opcode(0xC1, 0x7); /* C1 /7 ib */
9172 ins_encode(reg_opc_imm_wide(dst, shift));
9173 ins_pipe(ialu_mem_imm);
9174 %}
9175
9176 // Arithmetic Shift Right by 8-bit immediate
9177 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9178 %{
9179 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9180 effect(KILL cr);
9181
9182 format %{ "sarq $dst, $shift" %}
9183 opcode(0xC1, 0x7); /* C1 /7 ib */
9184 ins_encode(REX_mem_wide(dst), OpcP,
9185 RM_opc_mem(secondary, dst), Con8or32(shift));
9186 ins_pipe(ialu_mem_imm);
9187 %}
9188
9189 // Arithmetic Shift Right by variable
9190 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9191 %{
9192 match(Set dst (RShiftL dst shift));
9193 effect(KILL cr);
9194
9195 format %{ "sarq $dst, $shift" %}
9196 opcode(0xD3, 0x7); /* D3 /7 */
9197 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9198 ins_pipe(ialu_reg_reg);
9199 %}
9200
9201 // Arithmetic Shift Right by variable
9202 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9203 %{
9204 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9205 effect(KILL cr);
9206
9207 format %{ "sarq $dst, $shift" %}
9208 opcode(0xD3, 0x7); /* D3 /7 */
9209 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9210 ins_pipe(ialu_mem_reg);
9211 %}
9212
9213 // Logical shift right by one
9214 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9215 %{
9216 match(Set dst (URShiftL dst shift));
9217 effect(KILL cr);
9218
9219 format %{ "shrq $dst, $shift" %}
9220 opcode(0xD1, 0x5); /* D1 /5 */
9221 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
9222 ins_pipe(ialu_reg);
9223 %}
9224
9225 // Logical shift right by one
9226 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9227 %{
9228 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9229 effect(KILL cr);
9230
9231 format %{ "shrq $dst, $shift" %}
9232 opcode(0xD1, 0x5); /* D1 /5 */
9233 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9234 ins_pipe(ialu_mem_imm);
9235 %}
9236
9237 // Logical Shift Right by 8-bit immediate
9238 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9239 %{
9240 match(Set dst (URShiftL dst shift));
9241 effect(KILL cr);
9242
9243 format %{ "shrq $dst, $shift" %}
9244 opcode(0xC1, 0x5); /* C1 /5 ib */
9245 ins_encode(reg_opc_imm_wide(dst, shift));
9246 ins_pipe(ialu_reg);
9247 %}
9248
9249
9250 // Logical Shift Right by 8-bit immediate
9251 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9252 %{
9253 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9254 effect(KILL cr);
9255
9256 format %{ "shrq $dst, $shift" %}
9257 opcode(0xC1, 0x5); /* C1 /5 ib */
9258 ins_encode(REX_mem_wide(dst), OpcP,
9259 RM_opc_mem(secondary, dst), Con8or32(shift));
9260 ins_pipe(ialu_mem_imm);
9261 %}
9262
9263 // Logical Shift Right by variable
9264 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9265 %{
9266 match(Set dst (URShiftL dst shift));
9267 effect(KILL cr);
9268
9269 format %{ "shrq $dst, $shift" %}
9270 opcode(0xD3, 0x5); /* D3 /5 */
9271 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9272 ins_pipe(ialu_reg_reg);
9273 %}
9274
9275 // Logical Shift Right by variable
9276 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9277 %{
9278 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9279 effect(KILL cr);
9280
9281 format %{ "shrq $dst, $shift" %}
9282 opcode(0xD3, 0x5); /* D3 /5 */
9283 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9284 ins_pipe(ialu_mem_reg);
9285 %}
9286
9287 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9288 // This idiom is used by the compiler for the i2b bytecode.
9289 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9290 %{
9291 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9292
9293 format %{ "movsbl $dst, $src\t# i2b" %}
9294 opcode(0x0F, 0xBE);
9295 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9296 ins_pipe(ialu_reg_reg);
9297 %}
9298
9299 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9300 // This idiom is used by the compiler the i2s bytecode.
9301 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9302 %{
9303 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9304
9305 format %{ "movswl $dst, $src\t# i2s" %}
9306 opcode(0x0F, 0xBF);
9307 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9308 ins_pipe(ialu_reg_reg);
9309 %}
9310
9311 // ROL/ROR instructions
9312
9313 // ROL expand
9314 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9315 effect(KILL cr, USE_DEF dst);
9316
9317 format %{ "roll $dst" %}
9318 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9319 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9320 ins_pipe(ialu_reg);
9321 %}
9322
9323 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9324 effect(USE_DEF dst, USE shift, KILL cr);
9325
9326 format %{ "roll $dst, $shift" %}
9327 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9328 ins_encode( reg_opc_imm(dst, shift) );
9329 ins_pipe(ialu_reg);
9330 %}
9331
9332 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9333 %{
9334 effect(USE_DEF dst, USE shift, KILL cr);
9335
9336 format %{ "roll $dst, $shift" %}
9337 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9338 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9339 ins_pipe(ialu_reg_reg);
9340 %}
9341 // end of ROL expand
9342
9343 // Rotate Left by one
9344 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9345 %{
9346 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9347
9348 expand %{
9349 rolI_rReg_imm1(dst, cr);
9350 %}
9351 %}
9352
9353 // Rotate Left by 8-bit immediate
9354 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9355 %{
9356 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9357 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9358
9359 expand %{
9360 rolI_rReg_imm8(dst, lshift, cr);
9361 %}
9362 %}
9363
9364 // Rotate Left by variable
9365 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9366 %{
9367 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9368
9369 expand %{
9370 rolI_rReg_CL(dst, shift, cr);
9371 %}
9372 %}
9373
9374 // Rotate Left by variable
9375 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9376 %{
9377 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9378
9379 expand %{
9380 rolI_rReg_CL(dst, shift, cr);
9381 %}
9382 %}
9383
9384 // ROR expand
9385 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9386 %{
9387 effect(USE_DEF dst, KILL cr);
9388
9389 format %{ "rorl $dst" %}
9390 opcode(0xD1, 0x1); /* D1 /1 */
9391 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9392 ins_pipe(ialu_reg);
9393 %}
9394
9395 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9396 %{
9397 effect(USE_DEF dst, USE shift, KILL cr);
9398
9399 format %{ "rorl $dst, $shift" %}
9400 opcode(0xC1, 0x1); /* C1 /1 ib */
9401 ins_encode(reg_opc_imm(dst, shift));
9402 ins_pipe(ialu_reg);
9403 %}
9404
9405 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9406 %{
9407 effect(USE_DEF dst, USE shift, KILL cr);
9408
9409 format %{ "rorl $dst, $shift" %}
9410 opcode(0xD3, 0x1); /* D3 /1 */
9411 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9412 ins_pipe(ialu_reg_reg);
9413 %}
9414 // end of ROR expand
9415
9416 // Rotate Right by one
9417 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9418 %{
9419 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9420
9421 expand %{
9422 rorI_rReg_imm1(dst, cr);
9423 %}
9424 %}
9425
9426 // Rotate Right by 8-bit immediate
9427 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9428 %{
9429 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9430 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9431
9432 expand %{
9433 rorI_rReg_imm8(dst, rshift, cr);
9434 %}
9435 %}
9436
9437 // Rotate Right by variable
9438 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9439 %{
9440 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9441
9442 expand %{
9443 rorI_rReg_CL(dst, shift, cr);
9444 %}
9445 %}
9446
9447 // Rotate Right by variable
9448 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9449 %{
9450 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9451
9452 expand %{
9453 rorI_rReg_CL(dst, shift, cr);
9454 %}
9455 %}
9456
9457 // for long rotate
9458 // ROL expand
9459 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9460 effect(USE_DEF dst, KILL cr);
9461
9462 format %{ "rolq $dst" %}
9463 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9464 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9465 ins_pipe(ialu_reg);
9466 %}
9467
9468 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9469 effect(USE_DEF dst, USE shift, KILL cr);
9470
9471 format %{ "rolq $dst, $shift" %}
9472 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9473 ins_encode( reg_opc_imm_wide(dst, shift) );
9474 ins_pipe(ialu_reg);
9475 %}
9476
9477 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9478 %{
9479 effect(USE_DEF dst, USE shift, KILL cr);
9480
9481 format %{ "rolq $dst, $shift" %}
9482 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9483 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9484 ins_pipe(ialu_reg_reg);
9485 %}
9486 // end of ROL expand
9487
9488 // Rotate Left by one
9489 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9490 %{
9491 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9492
9493 expand %{
9494 rolL_rReg_imm1(dst, cr);
9495 %}
9496 %}
9497
9498 // Rotate Left by 8-bit immediate
9499 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9500 %{
9501 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9502 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9503
9504 expand %{
9505 rolL_rReg_imm8(dst, lshift, cr);
9506 %}
9507 %}
9508
9509 // Rotate Left by variable
9510 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9511 %{
9512 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9513
9514 expand %{
9515 rolL_rReg_CL(dst, shift, cr);
9516 %}
9517 %}
9518
9519 // Rotate Left by variable
9520 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9521 %{
9522 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9523
9524 expand %{
9525 rolL_rReg_CL(dst, shift, cr);
9526 %}
9527 %}
9528
9529 // ROR expand
9530 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9531 %{
9532 effect(USE_DEF dst, KILL cr);
9533
9534 format %{ "rorq $dst" %}
9535 opcode(0xD1, 0x1); /* D1 /1 */
9536 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9537 ins_pipe(ialu_reg);
9538 %}
9539
9540 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9541 %{
9542 effect(USE_DEF dst, USE shift, KILL cr);
9543
9544 format %{ "rorq $dst, $shift" %}
9545 opcode(0xC1, 0x1); /* C1 /1 ib */
9546 ins_encode(reg_opc_imm_wide(dst, shift));
9547 ins_pipe(ialu_reg);
9548 %}
9549
9550 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9551 %{
9552 effect(USE_DEF dst, USE shift, KILL cr);
9553
9554 format %{ "rorq $dst, $shift" %}
9555 opcode(0xD3, 0x1); /* D3 /1 */
9556 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9557 ins_pipe(ialu_reg_reg);
9558 %}
9559 // end of ROR expand
9560
9561 // Rotate Right by one
9562 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9563 %{
9564 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9565
9566 expand %{
9567 rorL_rReg_imm1(dst, cr);
9568 %}
9569 %}
9570
9571 // Rotate Right by 8-bit immediate
9572 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9573 %{
9574 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9575 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9576
9577 expand %{
9578 rorL_rReg_imm8(dst, rshift, cr);
9579 %}
9580 %}
9581
9582 // Rotate Right by variable
9583 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9584 %{
9585 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9586
9587 expand %{
9588 rorL_rReg_CL(dst, shift, cr);
9589 %}
9590 %}
9591
9592 // Rotate Right by variable
9593 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9594 %{
9595 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9596
9597 expand %{
9598 rorL_rReg_CL(dst, shift, cr);
9599 %}
9600 %}
9601
9602 // Logical Instructions
9603
9604 // Integer Logical Instructions
9605
9606 // And Instructions
9607 // And Register with Register
9608 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9609 %{
9610 match(Set dst (AndI dst src));
9611 effect(KILL cr);
9612
9613 format %{ "andl $dst, $src\t# int" %}
9614 opcode(0x23);
9615 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9616 ins_pipe(ialu_reg_reg);
9617 %}
9618
9619 // And Register with Immediate 255
9620 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9621 %{
9622 match(Set dst (AndI dst src));
9623
9624 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9625 opcode(0x0F, 0xB6);
9626 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9627 ins_pipe(ialu_reg);
9628 %}
9629
9630 // And Register with Immediate 255 and promote to long
9631 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9632 %{
9633 match(Set dst (ConvI2L (AndI src mask)));
9634
9635 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9636 opcode(0x0F, 0xB6);
9637 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9638 ins_pipe(ialu_reg);
9639 %}
9640
9641 // And Register with Immediate 65535
9642 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9643 %{
9644 match(Set dst (AndI dst src));
9645
9646 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9647 opcode(0x0F, 0xB7);
9648 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9649 ins_pipe(ialu_reg);
9650 %}
9651
9652 // And Register with Immediate 65535 and promote to long
9653 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9654 %{
9655 match(Set dst (ConvI2L (AndI src mask)));
9656
9657 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9658 opcode(0x0F, 0xB7);
9659 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9660 ins_pipe(ialu_reg);
9661 %}
9662
9663 // And Register with Immediate
9664 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9665 %{
9666 match(Set dst (AndI dst src));
9667 effect(KILL cr);
9668
9669 format %{ "andl $dst, $src\t# int" %}
9670 opcode(0x81, 0x04); /* Opcode 81 /4 */
9671 ins_encode(OpcSErm(dst, src), Con8or32(src));
9672 ins_pipe(ialu_reg);
9673 %}
9674
9675 // And Register with Memory
9676 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9677 %{
9678 match(Set dst (AndI dst (LoadI src)));
9679 effect(KILL cr);
9680
9681 ins_cost(125);
9682 format %{ "andl $dst, $src\t# int" %}
9683 opcode(0x23);
9684 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9685 ins_pipe(ialu_reg_mem);
9686 %}
9687
9688 // And Memory with Register
9689 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9690 %{
9691 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9692 effect(KILL cr);
9693
9694 ins_cost(150);
9695 format %{ "andl $dst, $src\t# int" %}
9696 opcode(0x21); /* Opcode 21 /r */
9697 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9698 ins_pipe(ialu_mem_reg);
9699 %}
9700
9701 // And Memory with Immediate
9702 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9703 %{
9704 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9705 effect(KILL cr);
9706
9707 ins_cost(125);
9708 format %{ "andl $dst, $src\t# int" %}
9709 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9710 ins_encode(REX_mem(dst), OpcSE(src),
9711 RM_opc_mem(secondary, dst), Con8or32(src));
9712 ins_pipe(ialu_mem_imm);
9713 %}
9714
9715 // Or Instructions
9716 // Or Register with Register
9717 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9718 %{
9719 match(Set dst (OrI dst src));
9720 effect(KILL cr);
9721
9722 format %{ "orl $dst, $src\t# int" %}
9723 opcode(0x0B);
9724 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9725 ins_pipe(ialu_reg_reg);
9726 %}
9727
9728 // Or Register with Immediate
9729 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9730 %{
9731 match(Set dst (OrI dst src));
9732 effect(KILL cr);
9733
9734 format %{ "orl $dst, $src\t# int" %}
9735 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9736 ins_encode(OpcSErm(dst, src), Con8or32(src));
9737 ins_pipe(ialu_reg);
9738 %}
9739
9740 // Or Register with Memory
9741 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9742 %{
9743 match(Set dst (OrI dst (LoadI src)));
9744 effect(KILL cr);
9745
9746 ins_cost(125);
9747 format %{ "orl $dst, $src\t# int" %}
9748 opcode(0x0B);
9749 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9750 ins_pipe(ialu_reg_mem);
9751 %}
9752
9753 // Or Memory with Register
9754 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9755 %{
9756 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9757 effect(KILL cr);
9758
9759 ins_cost(150);
9760 format %{ "orl $dst, $src\t# int" %}
9761 opcode(0x09); /* Opcode 09 /r */
9762 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9763 ins_pipe(ialu_mem_reg);
9764 %}
9765
9766 // Or Memory with Immediate
9767 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9768 %{
9769 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9770 effect(KILL cr);
9771
9772 ins_cost(125);
9773 format %{ "orl $dst, $src\t# int" %}
9774 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9775 ins_encode(REX_mem(dst), OpcSE(src),
9776 RM_opc_mem(secondary, dst), Con8or32(src));
9777 ins_pipe(ialu_mem_imm);
9778 %}
9779
9780 // Xor Instructions
9781 // Xor Register with Register
9782 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9783 %{
9784 match(Set dst (XorI dst src));
9785 effect(KILL cr);
9786
9787 format %{ "xorl $dst, $src\t# int" %}
9788 opcode(0x33);
9789 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9790 ins_pipe(ialu_reg_reg);
9791 %}
9792
9793 // Xor Register with Immediate -1
9794 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9795 match(Set dst (XorI dst imm));
9796
9797 format %{ "not $dst" %}
9798 ins_encode %{
9799 __ notl($dst$$Register);
9800 %}
9801 ins_pipe(ialu_reg);
9802 %}
9803
9804 // Xor Register with Immediate
9805 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9806 %{
9807 match(Set dst (XorI dst src));
9808 effect(KILL cr);
9809
9810 format %{ "xorl $dst, $src\t# int" %}
9811 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9812 ins_encode(OpcSErm(dst, src), Con8or32(src));
9813 ins_pipe(ialu_reg);
9814 %}
9815
9816 // Xor Register with Memory
9817 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9818 %{
9819 match(Set dst (XorI dst (LoadI src)));
9820 effect(KILL cr);
9821
9822 ins_cost(125);
9823 format %{ "xorl $dst, $src\t# int" %}
9824 opcode(0x33);
9825 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9826 ins_pipe(ialu_reg_mem);
9827 %}
9828
9829 // Xor Memory with Register
9830 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9831 %{
9832 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9833 effect(KILL cr);
9834
9835 ins_cost(150);
9836 format %{ "xorl $dst, $src\t# int" %}
9837 opcode(0x31); /* Opcode 31 /r */
9838 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9839 ins_pipe(ialu_mem_reg);
9840 %}
9841
9842 // Xor Memory with Immediate
9843 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9844 %{
9845 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9846 effect(KILL cr);
9847
9848 ins_cost(125);
9849 format %{ "xorl $dst, $src\t# int" %}
9850 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9851 ins_encode(REX_mem(dst), OpcSE(src),
9852 RM_opc_mem(secondary, dst), Con8or32(src));
9853 ins_pipe(ialu_mem_imm);
9854 %}
9855
9856
9857 // Long Logical Instructions
9858
9859 // And Instructions
9860 // And Register with Register
9861 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9862 %{
9863 match(Set dst (AndL dst src));
9864 effect(KILL cr);
9865
9866 format %{ "andq $dst, $src\t# long" %}
9867 opcode(0x23);
9868 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9869 ins_pipe(ialu_reg_reg);
9870 %}
9871
9872 // And Register with Immediate 255
9873 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9874 %{
9875 match(Set dst (AndL dst src));
9876
9877 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9878 opcode(0x0F, 0xB6);
9879 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9880 ins_pipe(ialu_reg);
9881 %}
9882
9883 // And Register with Immediate 65535
9884 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9885 %{
9886 match(Set dst (AndL dst src));
9887
9888 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9889 opcode(0x0F, 0xB7);
9890 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9891 ins_pipe(ialu_reg);
9892 %}
9893
9894 // And Register with Immediate
9895 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9896 %{
9897 match(Set dst (AndL dst src));
9898 effect(KILL cr);
9899
9900 format %{ "andq $dst, $src\t# long" %}
9901 opcode(0x81, 0x04); /* Opcode 81 /4 */
9902 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9903 ins_pipe(ialu_reg);
9904 %}
9905
9906 // And Register with Memory
9907 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9908 %{
9909 match(Set dst (AndL dst (LoadL src)));
9910 effect(KILL cr);
9911
9912 ins_cost(125);
9913 format %{ "andq $dst, $src\t# long" %}
9914 opcode(0x23);
9915 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9916 ins_pipe(ialu_reg_mem);
9917 %}
9918
9919 // And Memory with Register
9920 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9921 %{
9922 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9923 effect(KILL cr);
9924
9925 ins_cost(150);
9926 format %{ "andq $dst, $src\t# long" %}
9927 opcode(0x21); /* Opcode 21 /r */
9928 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9929 ins_pipe(ialu_mem_reg);
9930 %}
9931
9932 // And Memory with Immediate
9933 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9934 %{
9935 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9936 effect(KILL cr);
9937
9938 ins_cost(125);
9939 format %{ "andq $dst, $src\t# long" %}
9940 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9941 ins_encode(REX_mem_wide(dst), OpcSE(src),
9942 RM_opc_mem(secondary, dst), Con8or32(src));
9943 ins_pipe(ialu_mem_imm);
9944 %}
9945
9946 // Or Instructions
9947 // Or Register with Register
9948 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9949 %{
9950 match(Set dst (OrL dst src));
9951 effect(KILL cr);
9952
9953 format %{ "orq $dst, $src\t# long" %}
9954 opcode(0x0B);
9955 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9956 ins_pipe(ialu_reg_reg);
9957 %}
9958
9959 // Use any_RegP to match R15 (TLS register) without spilling.
9960 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9961 match(Set dst (OrL dst (CastP2X src)));
9962 effect(KILL cr);
9963
9964 format %{ "orq $dst, $src\t# long" %}
9965 opcode(0x0B);
9966 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9967 ins_pipe(ialu_reg_reg);
9968 %}
9969
9970
9971 // Or Register with Immediate
9972 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9973 %{
9974 match(Set dst (OrL dst src));
9975 effect(KILL cr);
9976
9977 format %{ "orq $dst, $src\t# long" %}
9978 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9979 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9980 ins_pipe(ialu_reg);
9981 %}
9982
9983 // Or Register with Memory
9984 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9985 %{
9986 match(Set dst (OrL dst (LoadL src)));
9987 effect(KILL cr);
9988
9989 ins_cost(125);
9990 format %{ "orq $dst, $src\t# long" %}
9991 opcode(0x0B);
9992 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9993 ins_pipe(ialu_reg_mem);
9994 %}
9995
9996 // Or Memory with Register
9997 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9998 %{
9999 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10000 effect(KILL cr);
10001
10002 ins_cost(150);
10003 format %{ "orq $dst, $src\t# long" %}
10004 opcode(0x09); /* Opcode 09 /r */
10005 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10006 ins_pipe(ialu_mem_reg);
10007 %}
10008
10009 // Or Memory with Immediate
10010 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10011 %{
10012 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10013 effect(KILL cr);
10014
10015 ins_cost(125);
10016 format %{ "orq $dst, $src\t# long" %}
10017 opcode(0x81, 0x1); /* Opcode 81 /1 id */
10018 ins_encode(REX_mem_wide(dst), OpcSE(src),
10019 RM_opc_mem(secondary, dst), Con8or32(src));
10020 ins_pipe(ialu_mem_imm);
10021 %}
10022
10023 // Xor Instructions
10024 // Xor Register with Register
10025 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10026 %{
10027 match(Set dst (XorL dst src));
10028 effect(KILL cr);
10029
10030 format %{ "xorq $dst, $src\t# long" %}
10031 opcode(0x33);
10032 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10033 ins_pipe(ialu_reg_reg);
10034 %}
10035
10036 // Xor Register with Immediate -1
10037 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10038 match(Set dst (XorL dst imm));
10039
10040 format %{ "notq $dst" %}
10041 ins_encode %{
10042 __ notq($dst$$Register);
10043 %}
10044 ins_pipe(ialu_reg);
10045 %}
10046
10047 // Xor Register with Immediate
10048 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10049 %{
10050 match(Set dst (XorL dst src));
10051 effect(KILL cr);
10052
10053 format %{ "xorq $dst, $src\t# long" %}
10054 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10055 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10056 ins_pipe(ialu_reg);
10057 %}
10058
10059 // Xor Register with Memory
10060 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10061 %{
10062 match(Set dst (XorL dst (LoadL src)));
10063 effect(KILL cr);
10064
10065 ins_cost(125);
10066 format %{ "xorq $dst, $src\t# long" %}
10067 opcode(0x33);
10068 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10069 ins_pipe(ialu_reg_mem);
10070 %}
10071
10072 // Xor Memory with Register
10073 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10074 %{
10075 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10076 effect(KILL cr);
10077
10078 ins_cost(150);
10079 format %{ "xorq $dst, $src\t# long" %}
10080 opcode(0x31); /* Opcode 31 /r */
10081 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10082 ins_pipe(ialu_mem_reg);
10083 %}
10084
10085 // Xor Memory with Immediate
10086 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10087 %{
10088 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10089 effect(KILL cr);
10090
10091 ins_cost(125);
10092 format %{ "xorq $dst, $src\t# long" %}
10093 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10094 ins_encode(REX_mem_wide(dst), OpcSE(src),
10095 RM_opc_mem(secondary, dst), Con8or32(src));
10096 ins_pipe(ialu_mem_imm);
10097 %}
10098
10099 // Convert Int to Boolean
10100 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10101 %{
10102 match(Set dst (Conv2B src));
10103 effect(KILL cr);
10104
10105 format %{ "testl $src, $src\t# ci2b\n\t"
10106 "setnz $dst\n\t"
10107 "movzbl $dst, $dst" %}
10108 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10109 setNZ_reg(dst),
10110 REX_reg_breg(dst, dst), // movzbl
10111 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10112 ins_pipe(pipe_slow); // XXX
10113 %}
10114
10115 // Convert Pointer to Boolean
10116 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10117 %{
10118 match(Set dst (Conv2B src));
10119 effect(KILL cr);
10120
10121 format %{ "testq $src, $src\t# cp2b\n\t"
10122 "setnz $dst\n\t"
10123 "movzbl $dst, $dst" %}
10124 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10125 setNZ_reg(dst),
10126 REX_reg_breg(dst, dst), // movzbl
10127 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10128 ins_pipe(pipe_slow); // XXX
10129 %}
10130
10131 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10132 %{
10133 match(Set dst (CmpLTMask p q));
10134 effect(KILL cr);
10135
10136 ins_cost(400); // XXX
10137 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10138 "setlt $dst\n\t"
10139 "movzbl $dst, $dst\n\t"
10140 "negl $dst" %}
10141 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10142 setLT_reg(dst),
10143 REX_reg_breg(dst, dst), // movzbl
10144 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10145 neg_reg(dst));
10146 ins_pipe(pipe_slow);
10147 %}
10148
10149 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10150 %{
10151 match(Set dst (CmpLTMask dst zero));
10152 effect(KILL cr);
10153
10154 ins_cost(100); // XXX
10155 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10156 opcode(0xC1, 0x7); /* C1 /7 ib */
10157 ins_encode(reg_opc_imm(dst, 0x1F));
10158 ins_pipe(ialu_reg);
10159 %}
10160
10161
10162 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rRegI tmp, rFlagsReg cr)
10163 %{
10164 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10165 effect(TEMP tmp, KILL cr);
10166
10167 ins_cost(400); // XXX
10168 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
10169 "sbbl $tmp, $tmp\n\t"
10170 "andl $tmp, $y\n\t"
10171 "addl $p, $tmp" %}
10172 ins_encode %{
10173 Register Rp = $p$$Register;
10174 Register Rq = $q$$Register;
10175 Register Ry = $y$$Register;
10176 Register Rt = $tmp$$Register;
10177 __ subl(Rp, Rq);
10178 __ sbbl(Rt, Rt);
10179 __ andl(Rt, Ry);
10180 __ addl(Rp, Rt);
10181 %}
10182 ins_pipe(pipe_cmplt);
10183 %}
10184
10185 //---------- FP Instructions------------------------------------------------
10186
10187 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10188 %{
10189 match(Set cr (CmpF src1 src2));
10190
10191 ins_cost(145);
10192 format %{ "ucomiss $src1, $src2\n\t"
10193 "jnp,s exit\n\t"
10194 "pushfq\t# saw NaN, set CF\n\t"
10195 "andq [rsp], #0xffffff2b\n\t"
10196 "popfq\n"
10197 "exit: nop\t# avoid branch to branch" %}
10198 opcode(0x0F, 0x2E);
10199 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
10200 cmpfp_fixup);
10201 ins_pipe(pipe_slow);
10202 %}
10203
10204 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10205 match(Set cr (CmpF src1 src2));
10206
10207 ins_cost(145);
10208 format %{ "ucomiss $src1, $src2" %}
10209 ins_encode %{
10210 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10211 %}
10212 ins_pipe(pipe_slow);
10213 %}
10214
10215 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10216 %{
10217 match(Set cr (CmpF src1 (LoadF src2)));
10218
10219 ins_cost(145);
10220 format %{ "ucomiss $src1, $src2\n\t"
10221 "jnp,s exit\n\t"
10222 "pushfq\t# saw NaN, set CF\n\t"
10223 "andq [rsp], #0xffffff2b\n\t"
10224 "popfq\n"
10225 "exit: nop\t# avoid branch to branch" %}
10226 opcode(0x0F, 0x2E);
10227 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
10228 cmpfp_fixup);
10229 ins_pipe(pipe_slow);
10230 %}
10231
10232 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10233 match(Set cr (CmpF src1 (LoadF src2)));
10234
10235 ins_cost(100);
10236 format %{ "ucomiss $src1, $src2" %}
10237 opcode(0x0F, 0x2E);
10238 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2));
10239 ins_pipe(pipe_slow);
10240 %}
10241
10242 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10243 match(Set cr (CmpF src con));
10244
10245 ins_cost(145);
10246 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10247 "jnp,s exit\n\t"
10248 "pushfq\t# saw NaN, set CF\n\t"
10249 "andq [rsp], #0xffffff2b\n\t"
10250 "popfq\n"
10251 "exit: nop\t# avoid branch to branch" %}
10252 ins_encode %{
10253 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10254 emit_cmpfp_fixup(_masm);
10255 %}
10256 ins_pipe(pipe_slow);
10257 %}
10258
10259 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10260 match(Set cr (CmpF src con));
10261 ins_cost(100);
10262 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10263 ins_encode %{
10264 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10265 %}
10266 ins_pipe(pipe_slow);
10267 %}
10268
10269 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10270 %{
10271 match(Set cr (CmpD src1 src2));
10272
10273 ins_cost(145);
10274 format %{ "ucomisd $src1, $src2\n\t"
10275 "jnp,s exit\n\t"
10276 "pushfq\t# saw NaN, set CF\n\t"
10277 "andq [rsp], #0xffffff2b\n\t"
10278 "popfq\n"
10279 "exit: nop\t# avoid branch to branch" %}
10280 opcode(0x66, 0x0F, 0x2E);
10281 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
10282 cmpfp_fixup);
10283 ins_pipe(pipe_slow);
10284 %}
10285
10286 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10287 match(Set cr (CmpD src1 src2));
10288
10289 ins_cost(100);
10290 format %{ "ucomisd $src1, $src2 test" %}
10291 ins_encode %{
10292 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10293 %}
10294 ins_pipe(pipe_slow);
10295 %}
10296
10297 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10298 %{
10299 match(Set cr (CmpD src1 (LoadD src2)));
10300
10301 ins_cost(145);
10302 format %{ "ucomisd $src1, $src2\n\t"
10303 "jnp,s exit\n\t"
10304 "pushfq\t# saw NaN, set CF\n\t"
10305 "andq [rsp], #0xffffff2b\n\t"
10306 "popfq\n"
10307 "exit: nop\t# avoid branch to branch" %}
10308 opcode(0x66, 0x0F, 0x2E);
10309 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
10310 cmpfp_fixup);
10311 ins_pipe(pipe_slow);
10312 %}
10313
10314 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10315 match(Set cr (CmpD src1 (LoadD src2)));
10316
10317 ins_cost(100);
10318 format %{ "ucomisd $src1, $src2" %}
10319 opcode(0x66, 0x0F, 0x2E);
10320 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2));
10321 ins_pipe(pipe_slow);
10322 %}
10323
10324 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10325 match(Set cr (CmpD src con));
10326
10327 ins_cost(145);
10328 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10329 "jnp,s exit\n\t"
10330 "pushfq\t# saw NaN, set CF\n\t"
10331 "andq [rsp], #0xffffff2b\n\t"
10332 "popfq\n"
10333 "exit: nop\t# avoid branch to branch" %}
10334 ins_encode %{
10335 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10336 emit_cmpfp_fixup(_masm);
10337 %}
10338 ins_pipe(pipe_slow);
10339 %}
10340
10341 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10342 match(Set cr (CmpD src con));
10343 ins_cost(100);
10344 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10345 ins_encode %{
10346 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10347 %}
10348 ins_pipe(pipe_slow);
10349 %}
10350
10351 // Compare into -1,0,1
10352 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10353 %{
10354 match(Set dst (CmpF3 src1 src2));
10355 effect(KILL cr);
10356
10357 ins_cost(275);
10358 format %{ "ucomiss $src1, $src2\n\t"
10359 "movl $dst, #-1\n\t"
10360 "jp,s done\n\t"
10361 "jb,s done\n\t"
10362 "setne $dst\n\t"
10363 "movzbl $dst, $dst\n"
10364 "done:" %}
10365
10366 opcode(0x0F, 0x2E);
10367 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
10368 cmpfp3(dst));
10369 ins_pipe(pipe_slow);
10370 %}
10371
10372 // Compare into -1,0,1
10373 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10374 %{
10375 match(Set dst (CmpF3 src1 (LoadF src2)));
10376 effect(KILL cr);
10377
10378 ins_cost(275);
10379 format %{ "ucomiss $src1, $src2\n\t"
10380 "movl $dst, #-1\n\t"
10381 "jp,s done\n\t"
10382 "jb,s done\n\t"
10383 "setne $dst\n\t"
10384 "movzbl $dst, $dst\n"
10385 "done:" %}
10386
10387 opcode(0x0F, 0x2E);
10388 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
10389 cmpfp3(dst));
10390 ins_pipe(pipe_slow);
10391 %}
10392
10393 // Compare into -1,0,1
10394 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10395 match(Set dst (CmpF3 src con));
10396 effect(KILL cr);
10397
10398 ins_cost(275);
10399 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10400 "movl $dst, #-1\n\t"
10401 "jp,s done\n\t"
10402 "jb,s done\n\t"
10403 "setne $dst\n\t"
10404 "movzbl $dst, $dst\n"
10405 "done:" %}
10406 ins_encode %{
10407 Label L_done;
10408 Register Rdst = $dst$$Register;
10409 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10410 __ movl(Rdst, -1);
10411 __ jcc(Assembler::parity, L_done);
10412 __ jcc(Assembler::below, L_done);
10413 __ setb(Assembler::notEqual, Rdst);
10414 __ movzbl(Rdst, Rdst);
10415 __ bind(L_done);
10416 %}
10417 ins_pipe(pipe_slow);
10418 %}
10419
10420 // Compare into -1,0,1
10421 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10422 %{
10423 match(Set dst (CmpD3 src1 src2));
10424 effect(KILL cr);
10425
10426 ins_cost(275);
10427 format %{ "ucomisd $src1, $src2\n\t"
10428 "movl $dst, #-1\n\t"
10429 "jp,s done\n\t"
10430 "jb,s done\n\t"
10431 "setne $dst\n\t"
10432 "movzbl $dst, $dst\n"
10433 "done:" %}
10434
10435 opcode(0x66, 0x0F, 0x2E);
10436 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
10437 cmpfp3(dst));
10438 ins_pipe(pipe_slow);
10439 %}
10440
10441 // Compare into -1,0,1
10442 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10443 %{
10444 match(Set dst (CmpD3 src1 (LoadD src2)));
10445 effect(KILL cr);
10446
10447 ins_cost(275);
10448 format %{ "ucomisd $src1, $src2\n\t"
10449 "movl $dst, #-1\n\t"
10450 "jp,s done\n\t"
10451 "jb,s done\n\t"
10452 "setne $dst\n\t"
10453 "movzbl $dst, $dst\n"
10454 "done:" %}
10455
10456 opcode(0x66, 0x0F, 0x2E);
10457 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
10458 cmpfp3(dst));
10459 ins_pipe(pipe_slow);
10460 %}
10461
10462 // Compare into -1,0,1
10463 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10464 match(Set dst (CmpD3 src con));
10465 effect(KILL cr);
10466
10467 ins_cost(275);
10468 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10469 "movl $dst, #-1\n\t"
10470 "jp,s done\n\t"
10471 "jb,s done\n\t"
10472 "setne $dst\n\t"
10473 "movzbl $dst, $dst\n"
10474 "done:" %}
10475 ins_encode %{
10476 Register Rdst = $dst$$Register;
10477 Label L_done;
10478 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10479 __ movl(Rdst, -1);
10480 __ jcc(Assembler::parity, L_done);
10481 __ jcc(Assembler::below, L_done);
10482 __ setb(Assembler::notEqual, Rdst);
10483 __ movzbl(Rdst, Rdst);
10484 __ bind(L_done);
10485 %}
10486 ins_pipe(pipe_slow);
10487 %}
10488
10489 instruct addF_reg(regF dst, regF src)
10490 %{
10491 match(Set dst (AddF dst src));
10492
10493 format %{ "addss $dst, $src" %}
10494 ins_cost(150); // XXX
10495 opcode(0xF3, 0x0F, 0x58);
10496 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10497 ins_pipe(pipe_slow);
10498 %}
10499
10500 instruct addF_mem(regF dst, memory src)
10501 %{
10502 match(Set dst (AddF dst (LoadF src)));
10503
10504 format %{ "addss $dst, $src" %}
10505 ins_cost(150); // XXX
10506 opcode(0xF3, 0x0F, 0x58);
10507 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10508 ins_pipe(pipe_slow);
10509 %}
10510
10511 instruct addF_imm(regF dst, immF con) %{
10512 match(Set dst (AddF dst con));
10513 format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
10514 ins_cost(150); // XXX
10515 ins_encode %{
10516 __ addss($dst$$XMMRegister, $constantaddress($con));
10517 %}
10518 ins_pipe(pipe_slow);
10519 %}
10520
10521 instruct addD_reg(regD dst, regD src)
10522 %{
10523 match(Set dst (AddD dst src));
10524
10525 format %{ "addsd $dst, $src" %}
10526 ins_cost(150); // XXX
10527 opcode(0xF2, 0x0F, 0x58);
10528 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10529 ins_pipe(pipe_slow);
10530 %}
10531
10532 instruct addD_mem(regD dst, memory src)
10533 %{
10534 match(Set dst (AddD dst (LoadD src)));
10535
10536 format %{ "addsd $dst, $src" %}
10537 ins_cost(150); // XXX
10538 opcode(0xF2, 0x0F, 0x58);
10539 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10540 ins_pipe(pipe_slow);
10541 %}
10542
10543 instruct addD_imm(regD dst, immD con) %{
10544 match(Set dst (AddD dst con));
10545 format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
10546 ins_cost(150); // XXX
10547 ins_encode %{
10548 __ addsd($dst$$XMMRegister, $constantaddress($con));
10549 %}
10550 ins_pipe(pipe_slow);
10551 %}
10552
10553 instruct subF_reg(regF dst, regF src)
10554 %{
10555 match(Set dst (SubF dst src));
10556
10557 format %{ "subss $dst, $src" %}
10558 ins_cost(150); // XXX
10559 opcode(0xF3, 0x0F, 0x5C);
10560 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10561 ins_pipe(pipe_slow);
10562 %}
10563
10564 instruct subF_mem(regF dst, memory src)
10565 %{
10566 match(Set dst (SubF dst (LoadF src)));
10567
10568 format %{ "subss $dst, $src" %}
10569 ins_cost(150); // XXX
10570 opcode(0xF3, 0x0F, 0x5C);
10571 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10572 ins_pipe(pipe_slow);
10573 %}
10574
10575 instruct subF_imm(regF dst, immF con) %{
10576 match(Set dst (SubF dst con));
10577 format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
10578 ins_cost(150); // XXX
10579 ins_encode %{
10580 __ subss($dst$$XMMRegister, $constantaddress($con));
10581 %}
10582 ins_pipe(pipe_slow);
10583 %}
10584
10585 instruct subD_reg(regD dst, regD src)
10586 %{
10587 match(Set dst (SubD dst src));
10588
10589 format %{ "subsd $dst, $src" %}
10590 ins_cost(150); // XXX
10591 opcode(0xF2, 0x0F, 0x5C);
10592 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10593 ins_pipe(pipe_slow);
10594 %}
10595
10596 instruct subD_mem(regD dst, memory src)
10597 %{
10598 match(Set dst (SubD dst (LoadD src)));
10599
10600 format %{ "subsd $dst, $src" %}
10601 ins_cost(150); // XXX
10602 opcode(0xF2, 0x0F, 0x5C);
10603 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10604 ins_pipe(pipe_slow);
10605 %}
10606
10607 instruct subD_imm(regD dst, immD con) %{
10608 match(Set dst (SubD dst con));
10609 format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
10610 ins_cost(150); // XXX
10611 ins_encode %{
10612 __ subsd($dst$$XMMRegister, $constantaddress($con));
10613 %}
10614 ins_pipe(pipe_slow);
10615 %}
10616
10617 instruct mulF_reg(regF dst, regF src)
10618 %{
10619 match(Set dst (MulF dst src));
10620
10621 format %{ "mulss $dst, $src" %}
10622 ins_cost(150); // XXX
10623 opcode(0xF3, 0x0F, 0x59);
10624 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10625 ins_pipe(pipe_slow);
10626 %}
10627
10628 instruct mulF_mem(regF dst, memory src)
10629 %{
10630 match(Set dst (MulF dst (LoadF src)));
10631
10632 format %{ "mulss $dst, $src" %}
10633 ins_cost(150); // XXX
10634 opcode(0xF3, 0x0F, 0x59);
10635 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10636 ins_pipe(pipe_slow);
10637 %}
10638
10639 instruct mulF_imm(regF dst, immF con) %{
10640 match(Set dst (MulF dst con));
10641 format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
10642 ins_cost(150); // XXX
10643 ins_encode %{
10644 __ mulss($dst$$XMMRegister, $constantaddress($con));
10645 %}
10646 ins_pipe(pipe_slow);
10647 %}
10648
10649 instruct mulD_reg(regD dst, regD src)
10650 %{
10651 match(Set dst (MulD dst src));
10652
10653 format %{ "mulsd $dst, $src" %}
10654 ins_cost(150); // XXX
10655 opcode(0xF2, 0x0F, 0x59);
10656 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10657 ins_pipe(pipe_slow);
10658 %}
10659
10660 instruct mulD_mem(regD dst, memory src)
10661 %{
10662 match(Set dst (MulD dst (LoadD src)));
10663
10664 format %{ "mulsd $dst, $src" %}
10665 ins_cost(150); // XXX
10666 opcode(0xF2, 0x0F, 0x59);
10667 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10668 ins_pipe(pipe_slow);
10669 %}
10670
10671 instruct mulD_imm(regD dst, immD con) %{
10672 match(Set dst (MulD dst con));
10673 format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
10674 ins_cost(150); // XXX
10675 ins_encode %{
10676 __ mulsd($dst$$XMMRegister, $constantaddress($con));
10677 %}
10678 ins_pipe(pipe_slow);
10679 %}
10680
10681 instruct divF_reg(regF dst, regF src)
10682 %{
10683 match(Set dst (DivF dst src));
10684
10685 format %{ "divss $dst, $src" %}
10686 ins_cost(150); // XXX
10687 opcode(0xF3, 0x0F, 0x5E);
10688 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10689 ins_pipe(pipe_slow);
10690 %}
10691
10692 instruct divF_mem(regF dst, memory src)
10693 %{
10694 match(Set dst (DivF dst (LoadF src)));
10695
10696 format %{ "divss $dst, $src" %}
10697 ins_cost(150); // XXX
10698 opcode(0xF3, 0x0F, 0x5E);
10699 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10700 ins_pipe(pipe_slow);
10701 %}
10702
10703 instruct divF_imm(regF dst, immF con) %{
10704 match(Set dst (DivF dst con));
10705 format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
10706 ins_cost(150); // XXX
10707 ins_encode %{
10708 __ divss($dst$$XMMRegister, $constantaddress($con));
10709 %}
10710 ins_pipe(pipe_slow);
10711 %}
10712
10713 instruct divD_reg(regD dst, regD src)
10714 %{
10715 match(Set dst (DivD dst src));
10716
10717 format %{ "divsd $dst, $src" %}
10718 ins_cost(150); // XXX
10719 opcode(0xF2, 0x0F, 0x5E);
10720 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10721 ins_pipe(pipe_slow);
10722 %}
10723
10724 instruct divD_mem(regD dst, memory src)
10725 %{
10726 match(Set dst (DivD dst (LoadD src)));
10727
10728 format %{ "divsd $dst, $src" %}
10729 ins_cost(150); // XXX
10730 opcode(0xF2, 0x0F, 0x5E);
10731 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10732 ins_pipe(pipe_slow);
10733 %}
10734
10735 instruct divD_imm(regD dst, immD con) %{
10736 match(Set dst (DivD dst con));
10737 format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
10738 ins_cost(150); // XXX
10739 ins_encode %{
10740 __ divsd($dst$$XMMRegister, $constantaddress($con));
10741 %}
10742 ins_pipe(pipe_slow);
10743 %}
10744
10745 instruct sqrtF_reg(regF dst, regF src)
10746 %{
10747 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10748
10749 format %{ "sqrtss $dst, $src" %}
10750 ins_cost(150); // XXX
10751 opcode(0xF3, 0x0F, 0x51);
10752 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10753 ins_pipe(pipe_slow);
10754 %}
10755
10756 instruct sqrtF_mem(regF dst, memory src)
10757 %{
10758 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
10759
10760 format %{ "sqrtss $dst, $src" %}
10761 ins_cost(150); // XXX
10762 opcode(0xF3, 0x0F, 0x51);
10763 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10764 ins_pipe(pipe_slow);
10765 %}
10766
10767 instruct sqrtF_imm(regF dst, immF con) %{
10768 match(Set dst (ConvD2F (SqrtD (ConvF2D con))));
10769 format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
10770 ins_cost(150); // XXX
10771 ins_encode %{
10772 __ sqrtss($dst$$XMMRegister, $constantaddress($con));
10773 %}
10774 ins_pipe(pipe_slow);
10775 %}
10776
10777 instruct sqrtD_reg(regD dst, regD src)
10778 %{
10779 match(Set dst (SqrtD src));
10780
10781 format %{ "sqrtsd $dst, $src" %}
10782 ins_cost(150); // XXX
10783 opcode(0xF2, 0x0F, 0x51);
10784 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10785 ins_pipe(pipe_slow);
10786 %}
10787
10788 instruct sqrtD_mem(regD dst, memory src)
10789 %{
10790 match(Set dst (SqrtD (LoadD src)));
10791
10792 format %{ "sqrtsd $dst, $src" %}
10793 ins_cost(150); // XXX
10794 opcode(0xF2, 0x0F, 0x51);
10795 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10796 ins_pipe(pipe_slow);
10797 %}
10798
10799 instruct sqrtD_imm(regD dst, immD con) %{
10800 match(Set dst (SqrtD con));
10801 format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
10802 ins_cost(150); // XXX
10803 ins_encode %{
10804 __ sqrtsd($dst$$XMMRegister, $constantaddress($con));
10805 %}
10806 ins_pipe(pipe_slow);
10807 %}
10808
10809 instruct absF_reg(regF dst)
10810 %{
10811 match(Set dst (AbsF dst));
10812
10813 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
10814 ins_encode(absF_encoding(dst));
10815 ins_pipe(pipe_slow);
10816 %}
10817
10818 instruct absD_reg(regD dst)
10819 %{
10820 match(Set dst (AbsD dst));
10821
10822 format %{ "andpd $dst, [0x7fffffffffffffff]\t"
10823 "# abs double by sign masking" %}
10824 ins_encode(absD_encoding(dst));
10825 ins_pipe(pipe_slow);
10826 %}
10827
10828 instruct negF_reg(regF dst)
10829 %{
10830 match(Set dst (NegF dst));
10831
10832 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
10833 ins_encode(negF_encoding(dst));
10834 ins_pipe(pipe_slow);
10835 %}
10836
10837 instruct negD_reg(regD dst)
10838 %{
10839 match(Set dst (NegD dst));
10840
10841 format %{ "xorpd $dst, [0x8000000000000000]\t"
10842 "# neg double by sign flipping" %}
10843 ins_encode(negD_encoding(dst));
10844 ins_pipe(pipe_slow);
10845 %}
10846
10847 // -----------Trig and Trancendental Instructions------------------------------
10848 instruct cosD_reg(regD dst) %{
10849 match(Set dst (CosD dst));
10850
10851 format %{ "dcos $dst\n\t" %}
10852 opcode(0xD9, 0xFF);
10853 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10854 ins_pipe( pipe_slow );
10855 %}
10856
10857 instruct sinD_reg(regD dst) %{
10858 match(Set dst (SinD dst));
10859
10860 format %{ "dsin $dst\n\t" %}
10861 opcode(0xD9, 0xFE);
10862 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10863 ins_pipe( pipe_slow );
10864 %}
10865
10866 instruct tanD_reg(regD dst) %{
10867 match(Set dst (TanD dst));
10868
10869 format %{ "dtan $dst\n\t" %}
10870 ins_encode( Push_SrcXD(dst),
10871 Opcode(0xD9), Opcode(0xF2), //fptan
10872 Opcode(0xDD), Opcode(0xD8), //fstp st
10873 Push_ResultXD(dst) );
10874 ins_pipe( pipe_slow );
10875 %}
10876
10877 instruct log10D_reg(regD dst) %{
10878 // The source and result Double operands in XMM registers
10879 match(Set dst (Log10D dst));
10880 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10881 // fyl2x ; compute log_10(2) * log_2(x)
10882 format %{ "fldlg2\t\t\t#Log10\n\t"
10883 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
10884 %}
10885 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
10886 Push_SrcXD(dst),
10887 Opcode(0xD9), Opcode(0xF1), // fyl2x
10888 Push_ResultXD(dst));
10889
10890 ins_pipe( pipe_slow );
10891 %}
10892
10893 instruct logD_reg(regD dst) %{
10894 // The source and result Double operands in XMM registers
10895 match(Set dst (LogD dst));
10896 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10897 // fyl2x ; compute log_e(2) * log_2(x)
10898 format %{ "fldln2\t\t\t#Log_e\n\t"
10899 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
10900 %}
10901 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10902 Push_SrcXD(dst),
10903 Opcode(0xD9), Opcode(0xF1), // fyl2x
10904 Push_ResultXD(dst));
10905 ins_pipe( pipe_slow );
10906 %}
10907
10908
10909
10910 //----------Arithmetic Conversion Instructions---------------------------------
10911
10912 instruct roundFloat_nop(regF dst)
10913 %{
10914 match(Set dst (RoundFloat dst));
10915
10916 ins_cost(0);
10917 ins_encode();
10918 ins_pipe(empty);
10919 %}
10920
10921 instruct roundDouble_nop(regD dst)
10922 %{
10923 match(Set dst (RoundDouble dst));
10924
10925 ins_cost(0);
10926 ins_encode();
10927 ins_pipe(empty);
10928 %}
10929
10930 instruct convF2D_reg_reg(regD dst, regF src)
10931 %{
10932 match(Set dst (ConvF2D src));
10933
10934 format %{ "cvtss2sd $dst, $src" %}
10935 opcode(0xF3, 0x0F, 0x5A);
10936 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10937 ins_pipe(pipe_slow); // XXX
10938 %}
10939
10940 instruct convF2D_reg_mem(regD dst, memory src)
10941 %{
10942 match(Set dst (ConvF2D (LoadF src)));
10943
10944 format %{ "cvtss2sd $dst, $src" %}
10945 opcode(0xF3, 0x0F, 0x5A);
10946 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10947 ins_pipe(pipe_slow); // XXX
10948 %}
10949
10950 instruct convD2F_reg_reg(regF dst, regD src)
10951 %{
10952 match(Set dst (ConvD2F src));
10953
10954 format %{ "cvtsd2ss $dst, $src" %}
10955 opcode(0xF2, 0x0F, 0x5A);
10956 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10957 ins_pipe(pipe_slow); // XXX
10958 %}
10959
10960 instruct convD2F_reg_mem(regF dst, memory src)
10961 %{
10962 match(Set dst (ConvD2F (LoadD src)));
10963
10964 format %{ "cvtsd2ss $dst, $src" %}
10965 opcode(0xF2, 0x0F, 0x5A);
10966 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10967 ins_pipe(pipe_slow); // XXX
10968 %}
10969
10970 // XXX do mem variants
10971 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10972 %{
10973 match(Set dst (ConvF2I src));
10974 effect(KILL cr);
10975
10976 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10977 "cmpl $dst, #0x80000000\n\t"
10978 "jne,s done\n\t"
10979 "subq rsp, #8\n\t"
10980 "movss [rsp], $src\n\t"
10981 "call f2i_fixup\n\t"
10982 "popq $dst\n"
10983 "done: "%}
10984 opcode(0xF3, 0x0F, 0x2C);
10985 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
10986 f2i_fixup(dst, src));
10987 ins_pipe(pipe_slow);
10988 %}
10989
10990 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10991 %{
10992 match(Set dst (ConvF2L src));
10993 effect(KILL cr);
10994
10995 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10996 "cmpq $dst, [0x8000000000000000]\n\t"
10997 "jne,s done\n\t"
10998 "subq rsp, #8\n\t"
10999 "movss [rsp], $src\n\t"
11000 "call f2l_fixup\n\t"
11001 "popq $dst\n"
11002 "done: "%}
11003 opcode(0xF3, 0x0F, 0x2C);
11004 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
11005 f2l_fixup(dst, src));
11006 ins_pipe(pipe_slow);
11007 %}
11008
11009 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
11010 %{
11011 match(Set dst (ConvD2I src));
11012 effect(KILL cr);
11013
11014 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
11015 "cmpl $dst, #0x80000000\n\t"
11016 "jne,s done\n\t"
11017 "subq rsp, #8\n\t"
11018 "movsd [rsp], $src\n\t"
11019 "call d2i_fixup\n\t"
11020 "popq $dst\n"
11021 "done: "%}
11022 opcode(0xF2, 0x0F, 0x2C);
11023 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
11024 d2i_fixup(dst, src));
11025 ins_pipe(pipe_slow);
11026 %}
11027
11028 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
11029 %{
11030 match(Set dst (ConvD2L src));
11031 effect(KILL cr);
11032
11033 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
11034 "cmpq $dst, [0x8000000000000000]\n\t"
11035 "jne,s done\n\t"
11036 "subq rsp, #8\n\t"
11037 "movsd [rsp], $src\n\t"
11038 "call d2l_fixup\n\t"
11039 "popq $dst\n"
11040 "done: "%}
11041 opcode(0xF2, 0x0F, 0x2C);
11042 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
11043 d2l_fixup(dst, src));
11044 ins_pipe(pipe_slow);
11045 %}
11046
11047 instruct convI2F_reg_reg(regF dst, rRegI src)
11048 %{
11049 predicate(!UseXmmI2F);
11050 match(Set dst (ConvI2F src));
11051
11052 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11053 opcode(0xF3, 0x0F, 0x2A);
11054 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
11055 ins_pipe(pipe_slow); // XXX
11056 %}
11057
11058 instruct convI2F_reg_mem(regF dst, memory src)
11059 %{
11060 match(Set dst (ConvI2F (LoadI src)));
11061
11062 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11063 opcode(0xF3, 0x0F, 0x2A);
11064 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11065 ins_pipe(pipe_slow); // XXX
11066 %}
11067
11068 instruct convI2D_reg_reg(regD dst, rRegI src)
11069 %{
11070 predicate(!UseXmmI2D);
11071 match(Set dst (ConvI2D src));
11072
11073 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11074 opcode(0xF2, 0x0F, 0x2A);
11075 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
11076 ins_pipe(pipe_slow); // XXX
11077 %}
11078
11079 instruct convI2D_reg_mem(regD dst, memory src)
11080 %{
11081 match(Set dst (ConvI2D (LoadI src)));
11082
11083 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11084 opcode(0xF2, 0x0F, 0x2A);
11085 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11086 ins_pipe(pipe_slow); // XXX
11087 %}
11088
11089 instruct convXI2F_reg(regF dst, rRegI src)
11090 %{
11091 predicate(UseXmmI2F);
11092 match(Set dst (ConvI2F src));
11093
11094 format %{ "movdl $dst, $src\n\t"
11095 "cvtdq2psl $dst, $dst\t# i2f" %}
11096 ins_encode %{
11097 __ movdl($dst$$XMMRegister, $src$$Register);
11098 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11099 %}
11100 ins_pipe(pipe_slow); // XXX
11101 %}
11102
11103 instruct convXI2D_reg(regD dst, rRegI src)
11104 %{
11105 predicate(UseXmmI2D);
11106 match(Set dst (ConvI2D src));
11107
11108 format %{ "movdl $dst, $src\n\t"
11109 "cvtdq2pdl $dst, $dst\t# i2d" %}
11110 ins_encode %{
11111 __ movdl($dst$$XMMRegister, $src$$Register);
11112 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11113 %}
11114 ins_pipe(pipe_slow); // XXX
11115 %}
11116
11117 instruct convL2F_reg_reg(regF dst, rRegL src)
11118 %{
11119 match(Set dst (ConvL2F src));
11120
11121 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11122 opcode(0xF3, 0x0F, 0x2A);
11123 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
11124 ins_pipe(pipe_slow); // XXX
11125 %}
11126
11127 instruct convL2F_reg_mem(regF dst, memory src)
11128 %{
11129 match(Set dst (ConvL2F (LoadL src)));
11130
11131 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11132 opcode(0xF3, 0x0F, 0x2A);
11133 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
11134 ins_pipe(pipe_slow); // XXX
11135 %}
11136
11137 instruct convL2D_reg_reg(regD dst, rRegL src)
11138 %{
11139 match(Set dst (ConvL2D src));
11140
11141 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11142 opcode(0xF2, 0x0F, 0x2A);
11143 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
11144 ins_pipe(pipe_slow); // XXX
11145 %}
11146
11147 instruct convL2D_reg_mem(regD dst, memory src)
11148 %{
11149 match(Set dst (ConvL2D (LoadL src)));
11150
11151 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11152 opcode(0xF2, 0x0F, 0x2A);
11153 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
11154 ins_pipe(pipe_slow); // XXX
11155 %}
11156
11157 instruct convI2L_reg_reg(rRegL dst, rRegI src)
11158 %{
11159 match(Set dst (ConvI2L src));
11160
11161 ins_cost(125);
11162 format %{ "movslq $dst, $src\t# i2l" %}
11163 ins_encode %{
11164 __ movslq($dst$$Register, $src$$Register);
11165 %}
11166 ins_pipe(ialu_reg_reg);
11167 %}
11168
11169 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
11170 // %{
11171 // match(Set dst (ConvI2L src));
11172 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
11173 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
11174 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
11175 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
11176 // ((const TypeNode*) n)->type()->is_long()->_lo ==
11177 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
11178
11179 // format %{ "movl $dst, $src\t# unsigned i2l" %}
11180 // ins_encode(enc_copy(dst, src));
11181 // // opcode(0x63); // needs REX.W
11182 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
11183 // ins_pipe(ialu_reg_reg);
11184 // %}
11185
11186 // Zero-extend convert int to long
11187 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
11188 %{
11189 match(Set dst (AndL (ConvI2L src) mask));
11190
11191 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11192 ins_encode(enc_copy(dst, src));
11193 ins_pipe(ialu_reg_reg);
11194 %}
11195
11196 // Zero-extend convert int to long
11197 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
11198 %{
11199 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
11200
11201 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11202 opcode(0x8B);
11203 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
11204 ins_pipe(ialu_reg_mem);
11205 %}
11206
11207 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
11208 %{
11209 match(Set dst (AndL src mask));
11210
11211 format %{ "movl $dst, $src\t# zero-extend long" %}
11212 ins_encode(enc_copy_always(dst, src));
11213 ins_pipe(ialu_reg_reg);
11214 %}
11215
11216 instruct convL2I_reg_reg(rRegI dst, rRegL src)
11217 %{
11218 match(Set dst (ConvL2I src));
11219
11220 format %{ "movl $dst, $src\t# l2i" %}
11221 ins_encode(enc_copy_always(dst, src));
11222 ins_pipe(ialu_reg_reg);
11223 %}
11224
11225
11226 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11227 match(Set dst (MoveF2I src));
11228 effect(DEF dst, USE src);
11229
11230 ins_cost(125);
11231 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
11232 opcode(0x8B);
11233 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
11234 ins_pipe(ialu_reg_mem);
11235 %}
11236
11237 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11238 match(Set dst (MoveI2F src));
11239 effect(DEF dst, USE src);
11240
11241 ins_cost(125);
11242 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
11243 opcode(0xF3, 0x0F, 0x10);
11244 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11245 ins_pipe(pipe_slow);
11246 %}
11247
11248 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
11249 match(Set dst (MoveD2L src));
11250 effect(DEF dst, USE src);
11251
11252 ins_cost(125);
11253 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
11254 opcode(0x8B);
11255 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
11256 ins_pipe(ialu_reg_mem);
11257 %}
11258
11259 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
11260 predicate(!UseXmmLoadAndClearUpper);
11261 match(Set dst (MoveL2D src));
11262 effect(DEF dst, USE src);
11263
11264 ins_cost(125);
11265 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
11266 opcode(0x66, 0x0F, 0x12);
11267 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11268 ins_pipe(pipe_slow);
11269 %}
11270
11271 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11272 predicate(UseXmmLoadAndClearUpper);
11273 match(Set dst (MoveL2D src));
11274 effect(DEF dst, USE src);
11275
11276 ins_cost(125);
11277 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
11278 opcode(0xF2, 0x0F, 0x10);
11279 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11280 ins_pipe(pipe_slow);
11281 %}
11282
11283
11284 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11285 match(Set dst (MoveF2I src));
11286 effect(DEF dst, USE src);
11287
11288 ins_cost(95); // XXX
11289 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
11290 opcode(0xF3, 0x0F, 0x11);
11291 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
11292 ins_pipe(pipe_slow);
11293 %}
11294
11295 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11296 match(Set dst (MoveI2F src));
11297 effect(DEF dst, USE src);
11298
11299 ins_cost(100);
11300 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
11301 opcode(0x89);
11302 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
11303 ins_pipe( ialu_mem_reg );
11304 %}
11305
11306 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11307 match(Set dst (MoveD2L src));
11308 effect(DEF dst, USE src);
11309
11310 ins_cost(95); // XXX
11311 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
11312 opcode(0xF2, 0x0F, 0x11);
11313 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
11314 ins_pipe(pipe_slow);
11315 %}
11316
11317 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
11318 match(Set dst (MoveL2D src));
11319 effect(DEF dst, USE src);
11320
11321 ins_cost(100);
11322 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
11323 opcode(0x89);
11324 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
11325 ins_pipe(ialu_mem_reg);
11326 %}
11327
11328 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
11329 match(Set dst (MoveF2I src));
11330 effect(DEF dst, USE src);
11331 ins_cost(85);
11332 format %{ "movd $dst,$src\t# MoveF2I" %}
11333 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %}
11334 ins_pipe( pipe_slow );
11335 %}
11336
11337 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
11338 match(Set dst (MoveD2L src));
11339 effect(DEF dst, USE src);
11340 ins_cost(85);
11341 format %{ "movd $dst,$src\t# MoveD2L" %}
11342 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %}
11343 ins_pipe( pipe_slow );
11344 %}
11345
11346 // The next instructions have long latency and use Int unit. Set high cost.
11347 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11348 match(Set dst (MoveI2F src));
11349 effect(DEF dst, USE src);
11350 ins_cost(300);
11351 format %{ "movd $dst,$src\t# MoveI2F" %}
11352 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %}
11353 ins_pipe( pipe_slow );
11354 %}
11355
11356 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11357 match(Set dst (MoveL2D src));
11358 effect(DEF dst, USE src);
11359 ins_cost(300);
11360 format %{ "movd $dst,$src\t# MoveL2D" %}
11361 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %}
11362 ins_pipe( pipe_slow );
11363 %}
11364
11365 // Replicate scalar to packed byte (1 byte) values in xmm
11366 instruct Repl8B_reg(regD dst, regD src) %{
11367 match(Set dst (Replicate8B src));
11368 format %{ "MOVDQA $dst,$src\n\t"
11369 "PUNPCKLBW $dst,$dst\n\t"
11370 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11371 ins_encode( pshufd_8x8(dst, src));
11372 ins_pipe( pipe_slow );
11373 %}
11374
11375 // Replicate scalar to packed byte (1 byte) values in xmm
11376 instruct Repl8B_rRegI(regD dst, rRegI src) %{
11377 match(Set dst (Replicate8B src));
11378 format %{ "MOVD $dst,$src\n\t"
11379 "PUNPCKLBW $dst,$dst\n\t"
11380 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11381 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
11382 ins_pipe( pipe_slow );
11383 %}
11384
11385 // Replicate scalar zero to packed byte (1 byte) values in xmm
11386 instruct Repl8B_immI0(regD dst, immI0 zero) %{
11387 match(Set dst (Replicate8B zero));
11388 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11389 ins_encode( pxor(dst, dst));
11390 ins_pipe( fpu_reg_reg );
11391 %}
11392
11393 // Replicate scalar to packed shore (2 byte) values in xmm
11394 instruct Repl4S_reg(regD dst, regD src) %{
11395 match(Set dst (Replicate4S src));
11396 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11397 ins_encode( pshufd_4x16(dst, src));
11398 ins_pipe( fpu_reg_reg );
11399 %}
11400
11401 // Replicate scalar to packed shore (2 byte) values in xmm
11402 instruct Repl4S_rRegI(regD dst, rRegI src) %{
11403 match(Set dst (Replicate4S src));
11404 format %{ "MOVD $dst,$src\n\t"
11405 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11406 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11407 ins_pipe( fpu_reg_reg );
11408 %}
11409
11410 // Replicate scalar zero to packed short (2 byte) values in xmm
11411 instruct Repl4S_immI0(regD dst, immI0 zero) %{
11412 match(Set dst (Replicate4S zero));
11413 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11414 ins_encode( pxor(dst, dst));
11415 ins_pipe( fpu_reg_reg );
11416 %}
11417
11418 // Replicate scalar to packed char (2 byte) values in xmm
11419 instruct Repl4C_reg(regD dst, regD src) %{
11420 match(Set dst (Replicate4C src));
11421 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11422 ins_encode( pshufd_4x16(dst, src));
11423 ins_pipe( fpu_reg_reg );
11424 %}
11425
11426 // Replicate scalar to packed char (2 byte) values in xmm
11427 instruct Repl4C_rRegI(regD dst, rRegI src) %{
11428 match(Set dst (Replicate4C src));
11429 format %{ "MOVD $dst,$src\n\t"
11430 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11431 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11432 ins_pipe( fpu_reg_reg );
11433 %}
11434
11435 // Replicate scalar zero to packed char (2 byte) values in xmm
11436 instruct Repl4C_immI0(regD dst, immI0 zero) %{
11437 match(Set dst (Replicate4C zero));
11438 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11439 ins_encode( pxor(dst, dst));
11440 ins_pipe( fpu_reg_reg );
11441 %}
11442
11443 // Replicate scalar to packed integer (4 byte) values in xmm
11444 instruct Repl2I_reg(regD dst, regD src) %{
11445 match(Set dst (Replicate2I src));
11446 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11447 ins_encode( pshufd(dst, src, 0x00));
11448 ins_pipe( fpu_reg_reg );
11449 %}
11450
11451 // Replicate scalar to packed integer (4 byte) values in xmm
11452 instruct Repl2I_rRegI(regD dst, rRegI src) %{
11453 match(Set dst (Replicate2I src));
11454 format %{ "MOVD $dst,$src\n\t"
11455 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11456 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
11457 ins_pipe( fpu_reg_reg );
11458 %}
11459
11460 // Replicate scalar zero to packed integer (2 byte) values in xmm
11461 instruct Repl2I_immI0(regD dst, immI0 zero) %{
11462 match(Set dst (Replicate2I zero));
11463 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11464 ins_encode( pxor(dst, dst));
11465 ins_pipe( fpu_reg_reg );
11466 %}
11467
11468 // Replicate scalar to packed single precision floating point values in xmm
11469 instruct Repl2F_reg(regD dst, regD src) %{
11470 match(Set dst (Replicate2F src));
11471 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11472 ins_encode( pshufd(dst, src, 0xe0));
11473 ins_pipe( fpu_reg_reg );
11474 %}
11475
11476 // Replicate scalar to packed single precision floating point values in xmm
11477 instruct Repl2F_regF(regD dst, regF src) %{
11478 match(Set dst (Replicate2F src));
11479 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11480 ins_encode( pshufd(dst, src, 0xe0));
11481 ins_pipe( fpu_reg_reg );
11482 %}
11483
11484 // Replicate scalar to packed single precision floating point values in xmm
11485 instruct Repl2F_immF0(regD dst, immF0 zero) %{
11486 match(Set dst (Replicate2F zero));
11487 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11488 ins_encode( pxor(dst, dst));
11489 ins_pipe( fpu_reg_reg );
11490 %}
11491
11492
11493 // =======================================================================
11494 // fast clearing of an array
11495 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
11496 rFlagsReg cr)
11497 %{
11498 match(Set dummy (ClearArray cnt base));
11499 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11500
11501 format %{ "xorl rax, rax\t# ClearArray:\n\t"
11502 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
11503 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
11504 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
11505 ins_pipe(pipe_slow);
11506 %}
11507
11508 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11509 rax_RegI result, regD tmp1, rFlagsReg cr)
11510 %{
11511 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11512 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11513
11514 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11515 ins_encode %{
11516 __ string_compare($str1$$Register, $str2$$Register,
11517 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11518 $tmp1$$XMMRegister);
11519 %}
11520 ins_pipe( pipe_slow );
11521 %}
11522
11523 // fast search of substring with known size.
11524 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11525 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11526 %{
11527 predicate(UseSSE42Intrinsics);
11528 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11529 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11530
11531 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11532 ins_encode %{
11533 int icnt2 = (int)$int_cnt2$$constant;
11534 if (icnt2 >= 8) {
11535 // IndexOf for constant substrings with size >= 8 elements
11536 // which don't need to be loaded through stack.
11537 __ string_indexofC8($str1$$Register, $str2$$Register,
11538 $cnt1$$Register, $cnt2$$Register,
11539 icnt2, $result$$Register,
11540 $vec$$XMMRegister, $tmp$$Register);
11541 } else {
11542 // Small strings are loaded through stack if they cross page boundary.
11543 __ string_indexof($str1$$Register, $str2$$Register,
11544 $cnt1$$Register, $cnt2$$Register,
11545 icnt2, $result$$Register,
11546 $vec$$XMMRegister, $tmp$$Register);
11547 }
11548 %}
11549 ins_pipe( pipe_slow );
11550 %}
11551
11552 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11553 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
11554 %{
11555 predicate(UseSSE42Intrinsics);
11556 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11557 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11558
11559 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11560 ins_encode %{
11561 __ string_indexof($str1$$Register, $str2$$Register,
11562 $cnt1$$Register, $cnt2$$Register,
11563 (-1), $result$$Register,
11564 $vec$$XMMRegister, $tmp$$Register);
11565 %}
11566 ins_pipe( pipe_slow );
11567 %}
11568
11569 // fast string equals
11570 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11571 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11572 %{
11573 match(Set result (StrEquals (Binary str1 str2) cnt));
11574 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11575
11576 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11577 ins_encode %{
11578 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11579 $cnt$$Register, $result$$Register, $tmp3$$Register,
11580 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11581 %}
11582 ins_pipe( pipe_slow );
11583 %}
11584
11585 // fast array equals
11586 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11587 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11588 %{
11589 match(Set result (AryEq ary1 ary2));
11590 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11591 //ins_cost(300);
11592
11593 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11594 ins_encode %{
11595 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11596 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11597 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11598 %}
11599 ins_pipe( pipe_slow );
11600 %}
11601
11602 //----------Control Flow Instructions------------------------------------------
11603 // Signed compare Instructions
11604
11605 // XXX more variants!!
11606 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11607 %{
11608 match(Set cr (CmpI op1 op2));
11609 effect(DEF cr, USE op1, USE op2);
11610
11611 format %{ "cmpl $op1, $op2" %}
11612 opcode(0x3B); /* Opcode 3B /r */
11613 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11614 ins_pipe(ialu_cr_reg_reg);
11615 %}
11616
11617 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11618 %{
11619 match(Set cr (CmpI op1 op2));
11620
11621 format %{ "cmpl $op1, $op2" %}
11622 opcode(0x81, 0x07); /* Opcode 81 /7 */
11623 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11624 ins_pipe(ialu_cr_reg_imm);
11625 %}
11626
11627 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11628 %{
11629 match(Set cr (CmpI op1 (LoadI op2)));
11630
11631 ins_cost(500); // XXX
11632 format %{ "cmpl $op1, $op2" %}
11633 opcode(0x3B); /* Opcode 3B /r */
11634 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11635 ins_pipe(ialu_cr_reg_mem);
11636 %}
11637
11638 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11639 %{
11640 match(Set cr (CmpI src zero));
11641
11642 format %{ "testl $src, $src" %}
11643 opcode(0x85);
11644 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11645 ins_pipe(ialu_cr_reg_imm);
11646 %}
11647
11648 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11649 %{
11650 match(Set cr (CmpI (AndI src con) zero));
11651
11652 format %{ "testl $src, $con" %}
11653 opcode(0xF7, 0x00);
11654 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11655 ins_pipe(ialu_cr_reg_imm);
11656 %}
11657
11658 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11659 %{
11660 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11661
11662 format %{ "testl $src, $mem" %}
11663 opcode(0x85);
11664 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11665 ins_pipe(ialu_cr_reg_mem);
11666 %}
11667
11668 // Unsigned compare Instructions; really, same as signed except they
11669 // produce an rFlagsRegU instead of rFlagsReg.
11670 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11671 %{
11672 match(Set cr (CmpU op1 op2));
11673
11674 format %{ "cmpl $op1, $op2\t# unsigned" %}
11675 opcode(0x3B); /* Opcode 3B /r */
11676 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11677 ins_pipe(ialu_cr_reg_reg);
11678 %}
11679
11680 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11681 %{
11682 match(Set cr (CmpU op1 op2));
11683
11684 format %{ "cmpl $op1, $op2\t# unsigned" %}
11685 opcode(0x81,0x07); /* Opcode 81 /7 */
11686 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11687 ins_pipe(ialu_cr_reg_imm);
11688 %}
11689
11690 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11691 %{
11692 match(Set cr (CmpU op1 (LoadI op2)));
11693
11694 ins_cost(500); // XXX
11695 format %{ "cmpl $op1, $op2\t# unsigned" %}
11696 opcode(0x3B); /* Opcode 3B /r */
11697 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11698 ins_pipe(ialu_cr_reg_mem);
11699 %}
11700
11701 // // // Cisc-spilled version of cmpU_rReg
11702 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11703 // //%{
11704 // // match(Set cr (CmpU (LoadI op1) op2));
11705 // //
11706 // // format %{ "CMPu $op1,$op2" %}
11707 // // ins_cost(500);
11708 // // opcode(0x39); /* Opcode 39 /r */
11709 // // ins_encode( OpcP, reg_mem( op1, op2) );
11710 // //%}
11711
11712 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11713 %{
11714 match(Set cr (CmpU src zero));
11715
11716 format %{ "testl $src, $src\t# unsigned" %}
11717 opcode(0x85);
11718 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11719 ins_pipe(ialu_cr_reg_imm);
11720 %}
11721
11722 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11723 %{
11724 match(Set cr (CmpP op1 op2));
11725
11726 format %{ "cmpq $op1, $op2\t# ptr" %}
11727 opcode(0x3B); /* Opcode 3B /r */
11728 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11729 ins_pipe(ialu_cr_reg_reg);
11730 %}
11731
11732 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11733 %{
11734 match(Set cr (CmpP op1 (LoadP op2)));
11735
11736 ins_cost(500); // XXX
11737 format %{ "cmpq $op1, $op2\t# ptr" %}
11738 opcode(0x3B); /* Opcode 3B /r */
11739 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11740 ins_pipe(ialu_cr_reg_mem);
11741 %}
11742
11743 // // // Cisc-spilled version of cmpP_rReg
11744 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11745 // //%{
11746 // // match(Set cr (CmpP (LoadP op1) op2));
11747 // //
11748 // // format %{ "CMPu $op1,$op2" %}
11749 // // ins_cost(500);
11750 // // opcode(0x39); /* Opcode 39 /r */
11751 // // ins_encode( OpcP, reg_mem( op1, op2) );
11752 // //%}
11753
11754 // XXX this is generalized by compP_rReg_mem???
11755 // Compare raw pointer (used in out-of-heap check).
11756 // Only works because non-oop pointers must be raw pointers
11757 // and raw pointers have no anti-dependencies.
11758 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11759 %{
11760 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
11761 match(Set cr (CmpP op1 (LoadP op2)));
11762
11763 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11764 opcode(0x3B); /* Opcode 3B /r */
11765 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11766 ins_pipe(ialu_cr_reg_mem);
11767 %}
11768
11769 // This will generate a signed flags result. This should be OK since
11770 // any compare to a zero should be eq/neq.
11771 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11772 %{
11773 match(Set cr (CmpP src zero));
11774
11775 format %{ "testq $src, $src\t# ptr" %}
11776 opcode(0x85);
11777 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11778 ins_pipe(ialu_cr_reg_imm);
11779 %}
11780
11781 // This will generate a signed flags result. This should be OK since
11782 // any compare to a zero should be eq/neq.
11783 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11784 %{
11785 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11786 match(Set cr (CmpP (LoadP op) zero));
11787
11788 ins_cost(500); // XXX
11789 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11790 opcode(0xF7); /* Opcode F7 /0 */
11791 ins_encode(REX_mem_wide(op),
11792 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11793 ins_pipe(ialu_cr_reg_imm);
11794 %}
11795
11796 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11797 %{
11798 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
11799 match(Set cr (CmpP (LoadP mem) zero));
11800
11801 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11802 ins_encode %{
11803 __ cmpq(r12, $mem$$Address);
11804 %}
11805 ins_pipe(ialu_cr_reg_mem);
11806 %}
11807
11808 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11809 %{
11810 match(Set cr (CmpN op1 op2));
11811
11812 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11813 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11814 ins_pipe(ialu_cr_reg_reg);
11815 %}
11816
11817 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11818 %{
11819 match(Set cr (CmpN src (LoadN mem)));
11820
11821 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11822 ins_encode %{
11823 __ cmpl($src$$Register, $mem$$Address);
11824 %}
11825 ins_pipe(ialu_cr_reg_mem);
11826 %}
11827
11828 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11829 match(Set cr (CmpN op1 op2));
11830
11831 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11832 ins_encode %{
11833 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11834 %}
11835 ins_pipe(ialu_cr_reg_imm);
11836 %}
11837
11838 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11839 %{
11840 match(Set cr (CmpN src (LoadN mem)));
11841
11842 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11843 ins_encode %{
11844 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11845 %}
11846 ins_pipe(ialu_cr_reg_mem);
11847 %}
11848
11849 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11850 match(Set cr (CmpN src zero));
11851
11852 format %{ "testl $src, $src\t# compressed ptr" %}
11853 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11854 ins_pipe(ialu_cr_reg_imm);
11855 %}
11856
11857 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11858 %{
11859 predicate(Universe::narrow_oop_base() != NULL);
11860 match(Set cr (CmpN (LoadN mem) zero));
11861
11862 ins_cost(500); // XXX
11863 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11864 ins_encode %{
11865 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11866 %}
11867 ins_pipe(ialu_cr_reg_mem);
11868 %}
11869
11870 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11871 %{
11872 predicate(Universe::narrow_oop_base() == NULL);
11873 match(Set cr (CmpN (LoadN mem) zero));
11874
11875 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11876 ins_encode %{
11877 __ cmpl(r12, $mem$$Address);
11878 %}
11879 ins_pipe(ialu_cr_reg_mem);
11880 %}
11881
11882 // Yanked all unsigned pointer compare operations.
11883 // Pointer compares are done with CmpP which is already unsigned.
11884
11885 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11886 %{
11887 match(Set cr (CmpL op1 op2));
11888
11889 format %{ "cmpq $op1, $op2" %}
11890 opcode(0x3B); /* Opcode 3B /r */
11891 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11892 ins_pipe(ialu_cr_reg_reg);
11893 %}
11894
11895 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11896 %{
11897 match(Set cr (CmpL op1 op2));
11898
11899 format %{ "cmpq $op1, $op2" %}
11900 opcode(0x81, 0x07); /* Opcode 81 /7 */
11901 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11902 ins_pipe(ialu_cr_reg_imm);
11903 %}
11904
11905 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11906 %{
11907 match(Set cr (CmpL op1 (LoadL op2)));
11908
11909 format %{ "cmpq $op1, $op2" %}
11910 opcode(0x3B); /* Opcode 3B /r */
11911 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11912 ins_pipe(ialu_cr_reg_mem);
11913 %}
11914
11915 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11916 %{
11917 match(Set cr (CmpL src zero));
11918
11919 format %{ "testq $src, $src" %}
11920 opcode(0x85);
11921 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11922 ins_pipe(ialu_cr_reg_imm);
11923 %}
11924
11925 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11926 %{
11927 match(Set cr (CmpL (AndL src con) zero));
11928
11929 format %{ "testq $src, $con\t# long" %}
11930 opcode(0xF7, 0x00);
11931 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11932 ins_pipe(ialu_cr_reg_imm);
11933 %}
11934
11935 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11936 %{
11937 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11938
11939 format %{ "testq $src, $mem" %}
11940 opcode(0x85);
11941 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11942 ins_pipe(ialu_cr_reg_mem);
11943 %}
11944
11945 // Manifest a CmpL result in an integer register. Very painful.
11946 // This is the test to avoid.
11947 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11948 %{
11949 match(Set dst (CmpL3 src1 src2));
11950 effect(KILL flags);
11951
11952 ins_cost(275); // XXX
11953 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11954 "movl $dst, -1\n\t"
11955 "jl,s done\n\t"
11956 "setne $dst\n\t"
11957 "movzbl $dst, $dst\n\t"
11958 "done:" %}
11959 ins_encode(cmpl3_flag(src1, src2, dst));
11960 ins_pipe(pipe_slow);
11961 %}
11962
11963 //----------Max and Min--------------------------------------------------------
11964 // Min Instructions
11965
11966 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11967 %{
11968 effect(USE_DEF dst, USE src, USE cr);
11969
11970 format %{ "cmovlgt $dst, $src\t# min" %}
11971 opcode(0x0F, 0x4F);
11972 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11973 ins_pipe(pipe_cmov_reg);
11974 %}
11975
11976
11977 instruct minI_rReg(rRegI dst, rRegI src)
11978 %{
11979 match(Set dst (MinI dst src));
11980
11981 ins_cost(200);
11982 expand %{
11983 rFlagsReg cr;
11984 compI_rReg(cr, dst, src);
11985 cmovI_reg_g(dst, src, cr);
11986 %}
11987 %}
11988
11989 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11990 %{
11991 effect(USE_DEF dst, USE src, USE cr);
11992
11993 format %{ "cmovllt $dst, $src\t# max" %}
11994 opcode(0x0F, 0x4C);
11995 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11996 ins_pipe(pipe_cmov_reg);
11997 %}
11998
11999
12000 instruct maxI_rReg(rRegI dst, rRegI src)
12001 %{
12002 match(Set dst (MaxI dst src));
12003
12004 ins_cost(200);
12005 expand %{
12006 rFlagsReg cr;
12007 compI_rReg(cr, dst, src);
12008 cmovI_reg_l(dst, src, cr);
12009 %}
12010 %}
12011
12012 // ============================================================================
12013 // Branch Instructions
12014
12015 // Jump Direct - Label defines a relative address from JMP+1
12016 instruct jmpDir(label labl)
12017 %{
12018 match(Goto);
12019 effect(USE labl);
12020
12021 ins_cost(300);
12022 format %{ "jmp $labl" %}
12023 size(5);
12024 opcode(0xE9);
12025 ins_encode(OpcP, Lbl(labl));
12026 ins_pipe(pipe_jmp);
12027 ins_pc_relative(1);
12028 %}
12029
12030 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12031 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12032 %{
12033 match(If cop cr);
12034 effect(USE labl);
12035
12036 ins_cost(300);
12037 format %{ "j$cop $labl" %}
12038 size(6);
12039 opcode(0x0F, 0x80);
12040 ins_encode(Jcc(cop, labl));
12041 ins_pipe(pipe_jcc);
12042 ins_pc_relative(1);
12043 %}
12044
12045 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12046 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12047 %{
12048 match(CountedLoopEnd cop cr);
12049 effect(USE labl);
12050
12051 ins_cost(300);
12052 format %{ "j$cop $labl\t# loop end" %}
12053 size(6);
12054 opcode(0x0F, 0x80);
12055 ins_encode(Jcc(cop, labl));
12056 ins_pipe(pipe_jcc);
12057 ins_pc_relative(1);
12058 %}
12059
12060 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12061 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12062 match(CountedLoopEnd cop cmp);
12063 effect(USE labl);
12064
12065 ins_cost(300);
12066 format %{ "j$cop,u $labl\t# loop end" %}
12067 size(6);
12068 opcode(0x0F, 0x80);
12069 ins_encode(Jcc(cop, labl));
12070 ins_pipe(pipe_jcc);
12071 ins_pc_relative(1);
12072 %}
12073
12074 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12075 match(CountedLoopEnd cop cmp);
12076 effect(USE labl);
12077
12078 ins_cost(200);
12079 format %{ "j$cop,u $labl\t# loop end" %}
12080 size(6);
12081 opcode(0x0F, 0x80);
12082 ins_encode(Jcc(cop, labl));
12083 ins_pipe(pipe_jcc);
12084 ins_pc_relative(1);
12085 %}
12086
12087 // Jump Direct Conditional - using unsigned comparison
12088 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12089 match(If cop cmp);
12090 effect(USE labl);
12091
12092 ins_cost(300);
12093 format %{ "j$cop,u $labl" %}
12094 size(6);
12095 opcode(0x0F, 0x80);
12096 ins_encode(Jcc(cop, labl));
12097 ins_pipe(pipe_jcc);
12098 ins_pc_relative(1);
12099 %}
12100
12101 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12102 match(If cop cmp);
12103 effect(USE labl);
12104
12105 ins_cost(200);
12106 format %{ "j$cop,u $labl" %}
12107 size(6);
12108 opcode(0x0F, 0x80);
12109 ins_encode(Jcc(cop, labl));
12110 ins_pipe(pipe_jcc);
12111 ins_pc_relative(1);
12112 %}
12113
12114 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12115 match(If cop cmp);
12116 effect(USE labl);
12117
12118 ins_cost(200);
12119 format %{ $$template
12120 if ($cop$$cmpcode == Assembler::notEqual) {
12121 $$emit$$"jp,u $labl\n\t"
12122 $$emit$$"j$cop,u $labl"
12123 } else {
12124 $$emit$$"jp,u done\n\t"
12125 $$emit$$"j$cop,u $labl\n\t"
12126 $$emit$$"done:"
12127 }
12128 %}
12129 size(12);
12130 opcode(0x0F, 0x80);
12131 ins_encode %{
12132 Label* l = $labl$$label;
12133 assert(l != NULL, "need Label");
12134 $$$emit8$primary;
12135 emit_cc(cbuf, $secondary, Assembler::parity);
12136 int parity_disp = -1;
12137 if ($cop$$cmpcode == Assembler::notEqual) {
12138 // the two jumps 6 bytes apart so the jump distances are too
12139 parity_disp = l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0;
12140 } else if ($cop$$cmpcode == Assembler::equal) {
12141 parity_disp = 6;
12142 } else {
12143 ShouldNotReachHere();
12144 }
12145 emit_d32(cbuf, parity_disp);
12146 $$$emit8$primary;
12147 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12148 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0;
12149 emit_d32(cbuf, disp);
12150 %}
12151 ins_pipe(pipe_jcc);
12152 ins_pc_relative(1);
12153 %}
12154
12155 // ============================================================================
12156 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12157 // superklass array for an instance of the superklass. Set a hidden
12158 // internal cache on a hit (cache is checked with exposed code in
12159 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12160 // encoding ALSO sets flags.
12161
12162 instruct partialSubtypeCheck(rdi_RegP result,
12163 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12164 rFlagsReg cr)
12165 %{
12166 match(Set result (PartialSubtypeCheck sub super));
12167 effect(KILL rcx, KILL cr);
12168
12169 ins_cost(1100); // slightly larger than the next version
12170 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
12171 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
12172 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
12173 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12174 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12175 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
12176 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12177 "miss:\t" %}
12178
12179 opcode(0x1); // Force a XOR of RDI
12180 ins_encode(enc_PartialSubtypeCheck());
12181 ins_pipe(pipe_slow);
12182 %}
12183
12184 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12185 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12186 immP0 zero,
12187 rdi_RegP result)
12188 %{
12189 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12190 effect(KILL rcx, KILL result);
12191
12192 ins_cost(1000);
12193 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
12194 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
12195 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
12196 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12197 "jne,s miss\t\t# Missed: flags nz\n\t"
12198 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
12199 "miss:\t" %}
12200
12201 opcode(0x0); // No need to XOR RDI
12202 ins_encode(enc_PartialSubtypeCheck());
12203 ins_pipe(pipe_slow);
12204 %}
12205
12206 // ============================================================================
12207 // Branch Instructions -- short offset versions
12208 //
12209 // These instructions are used to replace jumps of a long offset (the default
12210 // match) with jumps of a shorter offset. These instructions are all tagged
12211 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12212 // match rules in general matching. Instead, the ADLC generates a conversion
12213 // method in the MachNode which can be used to do in-place replacement of the
12214 // long variant with the shorter variant. The compiler will determine if a
12215 // branch can be taken by the is_short_branch_offset() predicate in the machine
12216 // specific code section of the file.
12217
12218 // Jump Direct - Label defines a relative address from JMP+1
12219 instruct jmpDir_short(label labl) %{
12220 match(Goto);
12221 effect(USE labl);
12222
12223 ins_cost(300);
12224 format %{ "jmp,s $labl" %}
12225 size(2);
12226 opcode(0xEB);
12227 ins_encode(OpcP, LblShort(labl));
12228 ins_pipe(pipe_jmp);
12229 ins_pc_relative(1);
12230 ins_short_branch(1);
12231 %}
12232
12233 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12234 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12235 match(If cop cr);
12236 effect(USE labl);
12237
12238 ins_cost(300);
12239 format %{ "j$cop,s $labl" %}
12240 size(2);
12241 opcode(0x70);
12242 ins_encode(JccShort(cop, labl));
12243 ins_pipe(pipe_jcc);
12244 ins_pc_relative(1);
12245 ins_short_branch(1);
12246 %}
12247
12248 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12249 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12250 match(CountedLoopEnd cop cr);
12251 effect(USE labl);
12252
12253 ins_cost(300);
12254 format %{ "j$cop,s $labl\t# loop end" %}
12255 size(2);
12256 opcode(0x70);
12257 ins_encode(JccShort(cop, labl));
12258 ins_pipe(pipe_jcc);
12259 ins_pc_relative(1);
12260 ins_short_branch(1);
12261 %}
12262
12263 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12264 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12265 match(CountedLoopEnd cop cmp);
12266 effect(USE labl);
12267
12268 ins_cost(300);
12269 format %{ "j$cop,us $labl\t# loop end" %}
12270 size(2);
12271 opcode(0x70);
12272 ins_encode(JccShort(cop, labl));
12273 ins_pipe(pipe_jcc);
12274 ins_pc_relative(1);
12275 ins_short_branch(1);
12276 %}
12277
12278 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12279 match(CountedLoopEnd cop cmp);
12280 effect(USE labl);
12281
12282 ins_cost(300);
12283 format %{ "j$cop,us $labl\t# loop end" %}
12284 size(2);
12285 opcode(0x70);
12286 ins_encode(JccShort(cop, labl));
12287 ins_pipe(pipe_jcc);
12288 ins_pc_relative(1);
12289 ins_short_branch(1);
12290 %}
12291
12292 // Jump Direct Conditional - using unsigned comparison
12293 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12294 match(If cop cmp);
12295 effect(USE labl);
12296
12297 ins_cost(300);
12298 format %{ "j$cop,us $labl" %}
12299 size(2);
12300 opcode(0x70);
12301 ins_encode(JccShort(cop, labl));
12302 ins_pipe(pipe_jcc);
12303 ins_pc_relative(1);
12304 ins_short_branch(1);
12305 %}
12306
12307 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12308 match(If cop cmp);
12309 effect(USE labl);
12310
12311 ins_cost(300);
12312 format %{ "j$cop,us $labl" %}
12313 size(2);
12314 opcode(0x70);
12315 ins_encode(JccShort(cop, labl));
12316 ins_pipe(pipe_jcc);
12317 ins_pc_relative(1);
12318 ins_short_branch(1);
12319 %}
12320
12321 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12322 match(If cop cmp);
12323 effect(USE labl);
12324
12325 ins_cost(300);
12326 format %{ $$template
12327 if ($cop$$cmpcode == Assembler::notEqual) {
12328 $$emit$$"jp,u,s $labl\n\t"
12329 $$emit$$"j$cop,u,s $labl"
12330 } else {
12331 $$emit$$"jp,u,s done\n\t"
12332 $$emit$$"j$cop,u,s $labl\n\t"
12333 $$emit$$"done:"
12334 }
12335 %}
12336 size(4);
12337 opcode(0x70);
12338 ins_encode %{
12339 Label* l = $labl$$label;
12340 assert(l != NULL, "need Label");
12341 emit_cc(cbuf, $primary, Assembler::parity);
12342 int parity_disp = -1;
12343 if ($cop$$cmpcode == Assembler::notEqual) {
12344 parity_disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
12345 } else if ($cop$$cmpcode == Assembler::equal) {
12346 parity_disp = 2;
12347 } else {
12348 ShouldNotReachHere();
12349 }
12350 emit_d8(cbuf, parity_disp);
12351 emit_cc(cbuf, $primary, $cop$$cmpcode);
12352 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
12353 emit_d8(cbuf, disp);
12354 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
12355 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
12356 %}
12357 ins_pipe(pipe_jcc);
12358 ins_pc_relative(1);
12359 ins_short_branch(1);
12360 %}
12361
12362 // ============================================================================
12363 // inlined locking and unlocking
12364
12365 instruct cmpFastLock(rFlagsReg cr,
12366 rRegP object, rRegP box, rax_RegI tmp, rRegP scr)
12367 %{
12368 match(Set cr (FastLock object box));
12369 effect(TEMP tmp, TEMP scr);
12370
12371 ins_cost(300);
12372 format %{ "fastlock $object,$box,$tmp,$scr" %}
12373 ins_encode(Fast_Lock(object, box, tmp, scr));
12374 ins_pipe(pipe_slow);
12375 ins_pc_relative(1);
12376 %}
12377
12378 instruct cmpFastUnlock(rFlagsReg cr,
12379 rRegP object, rax_RegP box, rRegP tmp)
12380 %{
12381 match(Set cr (FastUnlock object box));
12382 effect(TEMP tmp);
12383
12384 ins_cost(300);
12385 format %{ "fastunlock $object, $box, $tmp" %}
12386 ins_encode(Fast_Unlock(object, box, tmp));
12387 ins_pipe(pipe_slow);
12388 ins_pc_relative(1);
12389 %}
12390
12391
12392 // ============================================================================
12393 // Safepoint Instructions
12394 instruct safePoint_poll(rFlagsReg cr)
12395 %{
12396 predicate(!Assembler::is_polling_page_far());
12397 match(SafePoint);
12398 effect(KILL cr);
12399
12400 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12401 "# Safepoint: poll for GC" %}
12402 ins_cost(125);
12403 ins_encode %{
12404 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12405 __ testl(rax, addr);
12406 %}
12407 ins_pipe(ialu_reg_mem);
12408 %}
12409
12410 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12411 %{
12412 predicate(Assembler::is_polling_page_far());
12413 match(SafePoint poll);
12414 effect(KILL cr, USE poll);
12415
12416 format %{ "testl rax, [$poll]\t"
12417 "# Safepoint: poll for GC" %}
12418 ins_cost(125);
12419 ins_encode %{
12420 __ relocate(relocInfo::poll_type);
12421 __ testl(rax, Address($poll$$Register, 0));
12422 %}
12423 ins_pipe(ialu_reg_mem);
12424 %}
12425
12426 // ============================================================================
12427 // Procedure Call/Return Instructions
12428 // Call Java Static Instruction
12429 // Note: If this code changes, the corresponding ret_addr_offset() and
12430 // compute_padding() functions will have to be adjusted.
12431 instruct CallStaticJavaDirect(method meth) %{
12432 match(CallStaticJava);
12433 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
12434 effect(USE meth);
12435
12436 ins_cost(300);
12437 format %{ "call,static " %}
12438 opcode(0xE8); /* E8 cd */
12439 ins_encode(Java_Static_Call(meth), call_epilog);
12440 ins_pipe(pipe_slow);
12441 ins_pc_relative(1);
12442 ins_alignment(4);
12443 %}
12444
12445 // Call Java Static Instruction (method handle version)
12446 // Note: If this code changes, the corresponding ret_addr_offset() and
12447 // compute_padding() functions will have to be adjusted.
12448 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
12449 match(CallStaticJava);
12450 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
12451 effect(USE meth);
12452 // RBP is saved by all callees (for interpreter stack correction).
12453 // We use it here for a similar purpose, in {preserve,restore}_SP.
12454
12455 ins_cost(300);
12456 format %{ "call,static/MethodHandle " %}
12457 opcode(0xE8); /* E8 cd */
12458 ins_encode(preserve_SP,
12459 Java_Static_Call(meth),
12460 restore_SP,
12461 call_epilog);
12462 ins_pipe(pipe_slow);
12463 ins_pc_relative(1);
12464 ins_alignment(4);
12465 %}
12466
12467 // Call Java Dynamic Instruction
12468 // Note: If this code changes, the corresponding ret_addr_offset() and
12469 // compute_padding() functions will have to be adjusted.
12470 instruct CallDynamicJavaDirect(method meth)
12471 %{
12472 match(CallDynamicJava);
12473 effect(USE meth);
12474
12475 ins_cost(300);
12476 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12477 "call,dynamic " %}
12478 opcode(0xE8); /* E8 cd */
12479 ins_encode(Java_Dynamic_Call(meth), call_epilog);
12480 ins_pipe(pipe_slow);
12481 ins_pc_relative(1);
12482 ins_alignment(4);
12483 %}
12484
12485 // Call Runtime Instruction
12486 instruct CallRuntimeDirect(method meth)
12487 %{
12488 match(CallRuntime);
12489 effect(USE meth);
12490
12491 ins_cost(300);
12492 format %{ "call,runtime " %}
12493 opcode(0xE8); /* E8 cd */
12494 ins_encode(Java_To_Runtime(meth));
12495 ins_pipe(pipe_slow);
12496 ins_pc_relative(1);
12497 %}
12498
12499 // Call runtime without safepoint
12500 instruct CallLeafDirect(method meth)
12501 %{
12502 match(CallLeaf);
12503 effect(USE meth);
12504
12505 ins_cost(300);
12506 format %{ "call_leaf,runtime " %}
12507 opcode(0xE8); /* E8 cd */
12508 ins_encode(Java_To_Runtime(meth));
12509 ins_pipe(pipe_slow);
12510 ins_pc_relative(1);
12511 %}
12512
12513 // Call runtime without safepoint
12514 instruct CallLeafNoFPDirect(method meth)
12515 %{
12516 match(CallLeafNoFP);
12517 effect(USE meth);
12518
12519 ins_cost(300);
12520 format %{ "call_leaf_nofp,runtime " %}
12521 opcode(0xE8); /* E8 cd */
12522 ins_encode(Java_To_Runtime(meth));
12523 ins_pipe(pipe_slow);
12524 ins_pc_relative(1);
12525 %}
12526
12527 // Return Instruction
12528 // Remove the return address & jump to it.
12529 // Notice: We always emit a nop after a ret to make sure there is room
12530 // for safepoint patching
12531 instruct Ret()
12532 %{
12533 match(Return);
12534
12535 format %{ "ret" %}
12536 opcode(0xC3);
12537 ins_encode(OpcP);
12538 ins_pipe(pipe_jmp);
12539 %}
12540
12541 // Tail Call; Jump from runtime stub to Java code.
12542 // Also known as an 'interprocedural jump'.
12543 // Target of jump will eventually return to caller.
12544 // TailJump below removes the return address.
12545 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12546 %{
12547 match(TailCall jump_target method_oop);
12548
12549 ins_cost(300);
12550 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12551 opcode(0xFF, 0x4); /* Opcode FF /4 */
12552 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12553 ins_pipe(pipe_jmp);
12554 %}
12555
12556 // Tail Jump; remove the return address; jump to target.
12557 // TailCall above leaves the return address around.
12558 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12559 %{
12560 match(TailJump jump_target ex_oop);
12561
12562 ins_cost(300);
12563 format %{ "popq rdx\t# pop return address\n\t"
12564 "jmp $jump_target" %}
12565 opcode(0xFF, 0x4); /* Opcode FF /4 */
12566 ins_encode(Opcode(0x5a), // popq rdx
12567 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12568 ins_pipe(pipe_jmp);
12569 %}
12570
12571 // Create exception oop: created by stack-crawling runtime code.
12572 // Created exception is now available to this handler, and is setup
12573 // just prior to jumping to this handler. No code emitted.
12574 instruct CreateException(rax_RegP ex_oop)
12575 %{
12576 match(Set ex_oop (CreateEx));
12577
12578 size(0);
12579 // use the following format syntax
12580 format %{ "# exception oop is in rax; no code emitted" %}
12581 ins_encode();
12582 ins_pipe(empty);
12583 %}
12584
12585 // Rethrow exception:
12586 // The exception oop will come in the first argument position.
12587 // Then JUMP (not call) to the rethrow stub code.
12588 instruct RethrowException()
12589 %{
12590 match(Rethrow);
12591
12592 // use the following format syntax
12593 format %{ "jmp rethrow_stub" %}
12594 ins_encode(enc_rethrow);
12595 ins_pipe(pipe_jmp);
12596 %}
12597
12598
12599 //----------PEEPHOLE RULES-----------------------------------------------------
12600 // These must follow all instruction definitions as they use the names
12601 // defined in the instructions definitions.
12602 //
12603 // peepmatch ( root_instr_name [preceding_instruction]* );
12604 //
12605 // peepconstraint %{
12606 // (instruction_number.operand_name relational_op instruction_number.operand_name
12607 // [, ...] );
12608 // // instruction numbers are zero-based using left to right order in peepmatch
12609 //
12610 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12611 // // provide an instruction_number.operand_name for each operand that appears
12612 // // in the replacement instruction's match rule
12613 //
12614 // ---------VM FLAGS---------------------------------------------------------
12615 //
12616 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12617 //
12618 // Each peephole rule is given an identifying number starting with zero and
12619 // increasing by one in the order seen by the parser. An individual peephole
12620 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12621 // on the command-line.
12622 //
12623 // ---------CURRENT LIMITATIONS----------------------------------------------
12624 //
12625 // Only match adjacent instructions in same basic block
12626 // Only equality constraints
12627 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12628 // Only one replacement instruction
12629 //
12630 // ---------EXAMPLE----------------------------------------------------------
12631 //
12632 // // pertinent parts of existing instructions in architecture description
12633 // instruct movI(rRegI dst, rRegI src)
12634 // %{
12635 // match(Set dst (CopyI src));
12636 // %}
12637 //
12638 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12639 // %{
12640 // match(Set dst (AddI dst src));
12641 // effect(KILL cr);
12642 // %}
12643 //
12644 // // Change (inc mov) to lea
12645 // peephole %{
12646 // // increment preceeded by register-register move
12647 // peepmatch ( incI_rReg movI );
12648 // // require that the destination register of the increment
12649 // // match the destination register of the move
12650 // peepconstraint ( 0.dst == 1.dst );
12651 // // construct a replacement instruction that sets
12652 // // the destination to ( move's source register + one )
12653 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12654 // %}
12655 //
12656
12657 // Implementation no longer uses movX instructions since
12658 // machine-independent system no longer uses CopyX nodes.
12659 //
12660 // peephole
12661 // %{
12662 // peepmatch (incI_rReg movI);
12663 // peepconstraint (0.dst == 1.dst);
12664 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12665 // %}
12666
12667 // peephole
12668 // %{
12669 // peepmatch (decI_rReg movI);
12670 // peepconstraint (0.dst == 1.dst);
12671 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12672 // %}
12673
12674 // peephole
12675 // %{
12676 // peepmatch (addI_rReg_imm movI);
12677 // peepconstraint (0.dst == 1.dst);
12678 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12679 // %}
12680
12681 // peephole
12682 // %{
12683 // peepmatch (incL_rReg movL);
12684 // peepconstraint (0.dst == 1.dst);
12685 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12686 // %}
12687
12688 // peephole
12689 // %{
12690 // peepmatch (decL_rReg movL);
12691 // peepconstraint (0.dst == 1.dst);
12692 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12693 // %}
12694
12695 // peephole
12696 // %{
12697 // peepmatch (addL_rReg_imm movL);
12698 // peepconstraint (0.dst == 1.dst);
12699 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12700 // %}
12701
12702 // peephole
12703 // %{
12704 // peepmatch (addP_rReg_imm movP);
12705 // peepconstraint (0.dst == 1.dst);
12706 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12707 // %}
12708
12709 // // Change load of spilled value to only a spill
12710 // instruct storeI(memory mem, rRegI src)
12711 // %{
12712 // match(Set mem (StoreI mem src));
12713 // %}
12714 //
12715 // instruct loadI(rRegI dst, memory mem)
12716 // %{
12717 // match(Set dst (LoadI mem));
12718 // %}
12719 //
12720
12721 peephole
12722 %{
12723 peepmatch (loadI storeI);
12724 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12725 peepreplace (storeI(1.mem 1.mem 1.src));
12726 %}
12727
12728 peephole
12729 %{
12730 peepmatch (loadL storeL);
12731 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12732 peepreplace (storeL(1.mem 1.mem 1.src));
12733 %}
12734
12735 //----------SMARTSPILL RULES---------------------------------------------------
12736 // These must follow all instruction definitions as they use the names
12737 // defined in the instructions definitions.