src/cpu/sparc/vm/assembler_sparc.cpp
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src/cpu/sparc/vm/assembler_sparc.cpp

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  83 static const char* argumentNames[][2] = {
  84   {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},
  85   {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},
  86   {"A(n>9)","P(n>9)"}
  87 };
  88 
  89 const char* Argument::name() const {
  90   int nofArgs = sizeof argumentNames / sizeof argumentNames[0];
  91   int num = number();
  92   if (num >= nofArgs)  num = nofArgs - 1;
  93   return argumentNames[num][is_in() ? 1 : 0];
  94 }
  95 
  96 void Assembler::print_instruction(int inst) {
  97   const char* s;
  98   switch (inv_op(inst)) {
  99   default:         s = "????"; break;
 100   case call_op:    s = "call"; break;
 101   case branch_op:
 102     switch (inv_op2(inst)) {
 103       case bpr_op2:    s = "bpr";  break;
 104       case fb_op2:     s = "fb";   break;
 105       case fbp_op2:    s = "fbp";  break;
 106       case br_op2:     s = "br";   break;
 107       case bp_op2:     s = "bp";   break;
 108       case cb_op2:     s = "cb";   break;








 109       default:         s = "????"; break;
 110     }
 111   }
 112   ::tty->print("%s", s);
 113 }
 114 
 115 
 116 // Patch instruction inst at offset inst_pos to refer to dest_pos
 117 // and return the resulting instruction.
 118 // We should have pcs, not offsets, but since all is relative, it will work out
 119 // OK.
 120 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) {
 121 
 122   int m; // mask for displacement field
 123   int v; // new value for displacement field
 124   const int word_aligned_ones = -4;
 125   switch (inv_op(inst)) {
 126   default: ShouldNotReachHere();
 127   case call_op:    m = wdisp(word_aligned_ones, 0, 30);  v = wdisp(dest_pos, inst_pos, 30); break;
 128   case branch_op:
 129     switch (inv_op2(inst)) {
 130       case bpr_op2:    m = wdisp16(word_aligned_ones, 0);      v = wdisp16(dest_pos, inst_pos);     break;
 131       case fbp_op2:    m = wdisp(  word_aligned_ones, 0, 19);  v = wdisp(  dest_pos, inst_pos, 19); break;
 132       case bp_op2:     m = wdisp(  word_aligned_ones, 0, 19);  v = wdisp(  dest_pos, inst_pos, 19); break;
 133       case fb_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;
 134       case br_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;
 135       case cb_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;










 136       default: ShouldNotReachHere();
 137     }
 138   }
 139   return  inst & ~m  |  v;
 140 }
 141 
 142 // Return the offset of the branch destionation of instruction inst
 143 // at offset pos.
 144 // Should have pcs, but since all is relative, it works out.
 145 int Assembler::branch_destination(int inst, int pos) {
 146   int r;
 147   switch (inv_op(inst)) {
 148   default: ShouldNotReachHere();
 149   case call_op:        r = inv_wdisp(inst, pos, 30);  break;
 150   case branch_op:
 151     switch (inv_op2(inst)) {
 152       case bpr_op2:    r = inv_wdisp16(inst, pos);    break;
 153       case fbp_op2:    r = inv_wdisp(  inst, pos, 19);  break;
 154       case bp_op2:     r = inv_wdisp(  inst, pos, 19);  break;
 155       case fb_op2:     r = inv_wdisp(  inst, pos, 22);  break;
 156       case br_op2:     r = inv_wdisp(  inst, pos, 22);  break;
 157       case cb_op2:     r = inv_wdisp(  inst, pos, 22);  break;








 158       default: ShouldNotReachHere();
 159     }
 160   }
 161   return r;
 162 }
 163 
 164 int AbstractAssembler::code_fill_byte() {
 165   return 0x00;                  // illegal instruction 0x00000000
 166 }
 167 
 168 Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) {
 169   switch (in) {
 170   case rc_z:   return equal;
 171   case rc_lez: return lessEqual;
 172   case rc_lz:  return less;
 173   case rc_nz:  return notEqual;
 174   case rc_gz:  return greater;
 175   case rc_gez: return greaterEqual;
 176   default:
 177     ShouldNotReachHere();


 951   }
 952 }
 953 
 954 
 955 // %%% maybe get rid of [re]set_last_Java_frame
 956 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) {
 957   assert_not_delayed();
 958   Address flags(G2_thread, JavaThread::frame_anchor_offset() +
 959                            JavaFrameAnchor::flags_offset());
 960   Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset());
 961 
 962   // Always set last_Java_pc and flags first because once last_Java_sp is visible
 963   // has_last_Java_frame is true and users will look at the rest of the fields.
 964   // (Note: flags should always be zero before we get here so doesn't need to be set.)
 965 
 966 #ifdef ASSERT
 967   // Verify that flags was zeroed on return to Java
 968   Label PcOk;
 969   save_frame(0);                // to avoid clobbering O0
 970   ld_ptr(pc_addr, L0);
 971   tst(L0);
 972 #ifdef _LP64
 973   brx(Assembler::zero, false, Assembler::pt, PcOk);
 974 #else
 975   br(Assembler::zero, false, Assembler::pt, PcOk);
 976 #endif // _LP64
 977   delayed() -> nop();
 978   stop("last_Java_pc not zeroed before leaving Java");
 979   bind(PcOk);
 980 
 981   // Verify that flags was zeroed on return to Java
 982   Label FlagsOk;
 983   ld(flags, L0);
 984   tst(L0);
 985   br(Assembler::zero, false, Assembler::pt, FlagsOk);
 986   delayed() -> restore();
 987   stop("flags not zeroed before leaving Java");
 988   bind(FlagsOk);
 989 #endif /* ASSERT */
 990   //
 991   // When returning from calling out from Java mode the frame anchor's last_Java_pc
 992   // will always be set to NULL. It is set here so that if we are doing a call to
 993   // native (not VM) that we capture the known pc and don't have to rely on the
 994   // native call having a standard frame linkage where we can find the pc.
 995 
 996   if (last_Java_pc->is_valid()) {
 997     st_ptr(last_Java_pc, pc_addr);
 998   }
 999 
1000 #ifdef _LP64
1001 #ifdef ASSERT
1002   // Make sure that we have an odd stack
1003   Label StackOk;
1004   andcc(last_java_sp, 0x01, G0);
1005   br(Assembler::notZero, false, Assembler::pt, StackOk);
1006   delayed() -> nop();
1007   stop("Stack Not Biased in set_last_Java_frame");
1008   bind(StackOk);
1009 #endif // ASSERT
1010   assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame");
1011   add( last_java_sp, STACK_BIAS, G4_scratch );
1012   st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset());
1013 #else
1014   st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset());
1015 #endif // _LP64
1016 }
1017 
1018 void MacroAssembler::reset_last_Java_frame(void) {
1019   assert_not_delayed();
1020 
1021   Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset());
1022   Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
1023   Address flags  (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
1024 
1025 #ifdef ASSERT
1026   // check that it WAS previously set


1082   set(badHeapWordVal, G3);
1083   set(badHeapWordVal, G4);
1084   set(badHeapWordVal, G5);
1085 #endif
1086 
1087   // get oop result if there is one and reset the value in the thread
1088   if (oop_result->is_valid()) {
1089     get_vm_result(oop_result);
1090   }
1091 }
1092 
1093 void MacroAssembler::check_and_forward_exception(Register scratch_reg)
1094 {
1095   Label L;
1096 
1097   check_and_handle_popframe(scratch_reg);
1098   check_and_handle_earlyret(scratch_reg);
1099 
1100   Address exception_addr(G2_thread, Thread::pending_exception_offset());
1101   ld_ptr(exception_addr, scratch_reg);
1102   br_null(scratch_reg,false,pt,L);
1103   delayed()->nop();
1104   // we use O7 linkage so that forward_exception_entry has the issuing PC
1105   call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
1106   delayed()->nop();
1107   bind(L);
1108 }
1109 
1110 
1111 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) {
1112 }
1113 
1114 
1115 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) {
1116 }
1117 
1118 
1119 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1120   call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
1121 }
1122 
1123 


1857     Register O2_adr   = O2;
1858     Register O3_accum = O3;
1859     inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum);
1860   }
1861 
1862   Register O2_mask = O2;
1863   Register O3_bits = O3;
1864   Register O4_temp = O4;
1865 
1866   // mark lower end of faulting range
1867   assert(_verify_oop_implicit_branch[0] == NULL, "set once");
1868   _verify_oop_implicit_branch[0] = pc();
1869 
1870   // We can't check the mark oop because it could be in the process of
1871   // locking or unlocking while this is running.
1872   set(Universe::verify_oop_mask (), O2_mask);
1873   set(Universe::verify_oop_bits (), O3_bits);
1874 
1875   // assert((obj & oop_mask) == oop_bits);
1876   and3(O0_obj, O2_mask, O4_temp);
1877   cmp(O4_temp, O3_bits);
1878   brx(notEqual, false, pn, null_or_fail);
1879   delayed()->nop();
1880 
1881   if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) {
1882     // the null_or_fail case is useless; must test for null separately
1883     br_null(O0_obj, false, pn, succeed);
1884     delayed()->nop();
1885   }
1886 
1887   // Check the klassOop of this object for being in the right area of memory.
1888   // Cannot do the load in the delay above slot in case O0 is null
1889   load_klass(O0_obj, O0_obj);
1890   // assert((klass & klass_mask) == klass_bits);
1891   if( Universe::verify_klass_mask() != Universe::verify_oop_mask() )
1892     set(Universe::verify_klass_mask(), O2_mask);
1893   if( Universe::verify_klass_bits() != Universe::verify_oop_bits() )
1894     set(Universe::verify_klass_bits(), O3_bits);
1895   and3(O0_obj, O2_mask, O4_temp);
1896   cmp(O4_temp, O3_bits);
1897   brx(notEqual, false, pn, fail);
1898   delayed()->nop();
1899   // Check the klass's klass
1900   load_klass(O0_obj, O0_obj);
1901   and3(O0_obj, O2_mask, O4_temp);
1902   cmp(O4_temp, O3_bits);
1903   brx(notEqual, false, pn, fail);
1904   delayed()->wrccr( O5_save_flags ); // Restore CCR's
1905 
1906   // mark upper end of faulting range
1907   _verify_oop_implicit_branch[1] = pc();
1908 
1909   //-----------------------
1910   // all tests pass
1911   bind(succeed);
1912 
1913   // Restore prior 64-bit registers
1914   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0);
1915   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1);
1916   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2);
1917   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3);
1918   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4);


2105   save(SP, Rresult, SP);
2106 }
2107 
2108 
2109 // ---------------------------------------------------------
2110 Assembler::RCondition cond2rcond(Assembler::Condition c) {
2111   switch (c) {
2112     /*case zero: */
2113     case Assembler::equal:        return Assembler::rc_z;
2114     case Assembler::lessEqual:    return Assembler::rc_lez;
2115     case Assembler::less:         return Assembler::rc_lz;
2116     /*case notZero:*/
2117     case Assembler::notEqual:     return Assembler::rc_nz;
2118     case Assembler::greater:      return Assembler::rc_gz;
2119     case Assembler::greaterEqual: return Assembler::rc_gez;
2120   }
2121   ShouldNotReachHere();
2122   return Assembler::rc_z;
2123 }
2124 
2125 // compares register with zero and branches.  NOT FOR USE WITH 64-bit POINTERS
2126 void MacroAssembler::br_zero( Condition c, bool a, Predict p, Register s1, Label& L) {
2127   tst(s1);
2128   br (c, a, p, L);
2129 }
2130 
2131 
2132 // Compares a pointer register with zero and branches on null.
2133 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
2134 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) {
2135   assert_not_delayed();
2136 #ifdef _LP64
2137   bpr( rc_z, a, p, s1, L );
2138 #else
2139   tst(s1);
2140   br ( zero, a, p, L );
2141 #endif
2142 }
2143 
2144 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) {
2145   assert_not_delayed();
2146 #ifdef _LP64
2147   bpr( rc_nz, a, p, s1, L );
2148 #else
2149   tst(s1);
2150   br ( notZero, a, p, L );
2151 #endif
2152 }
2153 
2154 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,
2155                                      Register s1, address d,
2156                                      relocInfo::relocType rt ) {

2157   if (VM_Version::v9_instructions_work()) {
2158     bpr(rc, a, p, s1, d, rt);
2159   } else {
2160     tst(s1);
2161     br(reg_cond_to_cc_cond(rc), a, p, d, rt);
2162   }
2163 }
2164 
2165 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,
2166                                      Register s1, Label& L ) {

2167   if (VM_Version::v9_instructions_work()) {
2168     bpr(rc, a, p, s1, L);
2169   } else {
2170     tst(s1);
2171     br(reg_cond_to_cc_cond(rc), a, p, L);
2172   }
2173 }
2174 

2175 




















































































2176 // instruction sequences factored across compiler & interpreter
2177 
2178 
2179 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low,
2180                            Register Rb_hi, Register Rb_low,
2181                            Register Rresult) {
2182 
2183   Label check_low_parts, done;
2184 
2185   cmp(Ra_hi, Rb_hi );  // compare hi parts
2186   br(equal, true, pt, check_low_parts);
2187   delayed()->cmp(Ra_low, Rb_low); // test low parts
2188 
2189   // And, with an unsigned comparison, it does not matter if the numbers
2190   // are negative or not.
2191   // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff.
2192   // The second one is bigger (unsignedly).
2193 
2194   // Other notes:  The first move in each triplet can be unconditional
2195   // (and therefore probably prefetchable).
2196   // And the equals case for the high part does not need testing,
2197   // since that triplet is reached only after finding the high halves differ.
2198 
2199   if (VM_Version::v9_instructions_work()) {
2200 
2201                                     mov  (                     -1, Rresult);
2202     ba( false, done );  delayed()-> movcc(greater, false, icc,  1, Rresult);
2203   }
2204   else {
2205     br(less,    true, pt, done); delayed()-> set(-1, Rresult);
2206     br(greater, true, pt, done); delayed()-> set( 1, Rresult);
2207   }
2208 
2209   bind( check_low_parts );
2210 
2211   if (VM_Version::v9_instructions_work()) {
2212     mov(                               -1, Rresult);
2213     movcc(equal,           false, icc,  0, Rresult);
2214     movcc(greaterUnsigned, false, icc,  1, Rresult);
2215   }
2216   else {
2217                                                     set(-1, Rresult);
2218     br(equal,           true, pt, done); delayed()->set( 0, Rresult);
2219     br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult);
2220   }
2221   bind( done );
2222 }
2223 
2224 void MacroAssembler::lneg( Register Rhi, Register Rlow ) {
2225   subcc(  G0, Rlow, Rlow );
2226   subc(   G0, Rhi,  Rhi  );
2227 }
2228 
2229 void MacroAssembler::lshl( Register Rin_high,  Register Rin_low,
2230                            Register Rcount,
2231                            Register Rout_high, Register Rout_low,
2232                            Register Rtemp ) {
2233 
2234 
2235   Register Ralt_count = Rtemp;
2236   Register Rxfer_bits = Rtemp;
2237 
2238   assert( Ralt_count != Rin_high
2239       &&  Ralt_count != Rin_low
2240       &&  Ralt_count != Rcount
2241       &&  Rxfer_bits != Rin_low
2242       &&  Rxfer_bits != Rin_high
2243       &&  Rxfer_bits != Rcount
2244       &&  Rxfer_bits != Rout_low
2245       &&  Rout_low   != Rin_high,
2246         "register alias checks");
2247 
2248   Label big_shift, done;
2249 
2250   // This code can be optimized to use the 64 bit shifts in V9.
2251   // Here we use the 32 bit shifts.
2252 
2253   and3( Rcount,         0x3f,           Rcount);     // take least significant 6 bits
2254   subcc(Rcount,         31,             Ralt_count);
2255   br(greater, true, pn, big_shift);
2256   delayed()->
2257   dec(Ralt_count);
2258 
2259   // shift < 32 bits, Ralt_count = Rcount-31
2260 
2261   // We get the transfer bits by shifting right by 32-count the low
2262   // register. This is done by shifting right by 31-count and then by one
2263   // more to take care of the special (rare) case where count is zero
2264   // (shifting by 32 would not work).
2265 
2266   neg(  Ralt_count                                 );
2267 
2268   // The order of the next two instructions is critical in the case where
2269   // Rin and Rout are the same and should not be reversed.
2270 
2271   srl(  Rin_low,        Ralt_count,     Rxfer_bits ); // shift right by 31-count
2272   if (Rcount != Rout_low) {
2273     sll(        Rin_low,        Rcount,         Rout_low   ); // low half
2274   }
2275   sll(  Rin_high,       Rcount,         Rout_high  );
2276   if (Rcount == Rout_low) {
2277     sll(        Rin_low,        Rcount,         Rout_low   ); // low half
2278   }
2279   srl(  Rxfer_bits,     1,              Rxfer_bits ); // shift right by one more
2280   ba (false, done);
2281   delayed()->
2282   or3(  Rout_high,      Rxfer_bits,     Rout_high);   // new hi value: or in shifted old hi part and xfer from low
2283 
2284   // shift >= 32 bits, Ralt_count = Rcount-32
2285   bind(big_shift);
2286   sll(  Rin_low,        Ralt_count,     Rout_high  );
2287   clr(  Rout_low                                   );
2288 
2289   bind(done);
2290 }
2291 
2292 
2293 void MacroAssembler::lshr( Register Rin_high,  Register Rin_low,
2294                            Register Rcount,
2295                            Register Rout_high, Register Rout_low,
2296                            Register Rtemp ) {
2297 
2298   Register Ralt_count = Rtemp;
2299   Register Rxfer_bits = Rtemp;
2300 
2301   assert( Ralt_count != Rin_high
2302       &&  Ralt_count != Rin_low
2303       &&  Ralt_count != Rcount
2304       &&  Rxfer_bits != Rin_low
2305       &&  Rxfer_bits != Rin_high
2306       &&  Rxfer_bits != Rcount
2307       &&  Rxfer_bits != Rout_high
2308       &&  Rout_high  != Rin_low,
2309         "register alias checks");
2310 
2311   Label big_shift, done;
2312 
2313   // This code can be optimized to use the 64 bit shifts in V9.
2314   // Here we use the 32 bit shifts.
2315 
2316   and3( Rcount,         0x3f,           Rcount);     // take least significant 6 bits
2317   subcc(Rcount,         31,             Ralt_count);
2318   br(greater, true, pn, big_shift);
2319   delayed()->dec(Ralt_count);
2320 
2321   // shift < 32 bits, Ralt_count = Rcount-31
2322 
2323   // We get the transfer bits by shifting left by 32-count the high
2324   // register. This is done by shifting left by 31-count and then by one
2325   // more to take care of the special (rare) case where count is zero
2326   // (shifting by 32 would not work).
2327 
2328   neg(  Ralt_count                                  );
2329   if (Rcount != Rout_low) {
2330     srl(        Rin_low,        Rcount,         Rout_low    );
2331   }
2332 
2333   // The order of the next two instructions is critical in the case where
2334   // Rin and Rout are the same and should not be reversed.
2335 
2336   sll(  Rin_high,       Ralt_count,     Rxfer_bits  ); // shift left by 31-count
2337   sra(  Rin_high,       Rcount,         Rout_high   ); // high half
2338   sll(  Rxfer_bits,     1,              Rxfer_bits  ); // shift left by one more
2339   if (Rcount == Rout_low) {
2340     srl(        Rin_low,        Rcount,         Rout_low    );
2341   }
2342   ba (false, done);
2343   delayed()->
2344   or3(  Rout_low,       Rxfer_bits,     Rout_low    ); // new low value: or shifted old low part and xfer from high
2345 
2346   // shift >= 32 bits, Ralt_count = Rcount-32
2347   bind(big_shift);
2348 
2349   sra(  Rin_high,       Ralt_count,     Rout_low    );
2350   sra(  Rin_high,       31,             Rout_high   ); // sign into hi
2351 
2352   bind( done );
2353 }
2354 
2355 
2356 
2357 void MacroAssembler::lushr( Register Rin_high,  Register Rin_low,
2358                             Register Rcount,
2359                             Register Rout_high, Register Rout_low,
2360                             Register Rtemp ) {
2361 
2362   Register Ralt_count = Rtemp;
2363   Register Rxfer_bits = Rtemp;
2364 
2365   assert( Ralt_count != Rin_high
2366       &&  Ralt_count != Rin_low
2367       &&  Ralt_count != Rcount
2368       &&  Rxfer_bits != Rin_low
2369       &&  Rxfer_bits != Rin_high
2370       &&  Rxfer_bits != Rcount


2372       &&  Rout_high  != Rin_low,
2373         "register alias checks");
2374 
2375   Label big_shift, done;
2376 
2377   // This code can be optimized to use the 64 bit shifts in V9.
2378   // Here we use the 32 bit shifts.
2379 
2380   and3( Rcount,         0x3f,           Rcount);     // take least significant 6 bits
2381   subcc(Rcount,         31,             Ralt_count);
2382   br(greater, true, pn, big_shift);
2383   delayed()->dec(Ralt_count);
2384 
2385   // shift < 32 bits, Ralt_count = Rcount-31
2386 
2387   // We get the transfer bits by shifting left by 32-count the high
2388   // register. This is done by shifting left by 31-count and then by one
2389   // more to take care of the special (rare) case where count is zero
2390   // (shifting by 32 would not work).
2391 
2392   neg(  Ralt_count                                  );
2393   if (Rcount != Rout_low) {
2394     srl(        Rin_low,        Rcount,         Rout_low    );
2395   }
2396 
2397   // The order of the next two instructions is critical in the case where
2398   // Rin and Rout are the same and should not be reversed.
2399 
2400   sll(  Rin_high,       Ralt_count,     Rxfer_bits  ); // shift left by 31-count
2401   srl(  Rin_high,       Rcount,         Rout_high   ); // high half
2402   sll(  Rxfer_bits,     1,              Rxfer_bits  ); // shift left by one more
2403   if (Rcount == Rout_low) {
2404     srl(        Rin_low,        Rcount,         Rout_low    );
2405   }
2406   ba (false, done);
2407   delayed()->
2408   or3(  Rout_low,       Rxfer_bits,     Rout_low    ); // new low value: or shifted old low part and xfer from high
2409 
2410   // shift >= 32 bits, Ralt_count = Rcount-32
2411   bind(big_shift);
2412 
2413   srl(  Rin_high,       Ralt_count,     Rout_low    );
2414   clr(  Rout_high                                   );
2415 
2416   bind( done );
2417 }
2418 
2419 #ifdef _LP64
2420 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) {
2421   cmp(Ra, Rb);
2422   mov(                       -1, Rresult);
2423   movcc(equal,   false, xcc,  0, Rresult);
2424   movcc(greater, false, xcc,  1, Rresult);
2425 }
2426 #endif
2427 
2428 
2429 void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) {
2430   switch (size_in_bytes) {
2431   case  8:  ld_long(src, dst); break;
2432   case  4:  ld(     src, dst); break;
2433   case  2:  is_signed ? ldsh(src, dst) : lduh(src, dst); break;
2434   case  1:  is_signed ? ldsb(src, dst) : ldub(src, dst); break;
2435   default:  ShouldNotReachHere();
2436   }
2437 }
2438 
2439 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) {
2440   switch (size_in_bytes) {
2441   case  8:  st_long(src, dst); break;
2442   case  4:  st(     src, dst); break;
2443   case  2:  sth(    src, dst); break;
2444   case  1:  stb(    src, dst); break;
2445   default:  ShouldNotReachHere();
2446   }
2447 }
2448 
2449 
2450 void MacroAssembler::float_cmp( bool is_float, int unordered_result,
2451                                 FloatRegister Fa, FloatRegister Fb,
2452                                 Register Rresult) {
2453 
2454   fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb);
2455 
2456   Condition lt = unordered_result == -1 ? f_unorderedOrLess    : f_less;
2457   Condition eq =                          f_equal;
2458   Condition gt = unordered_result ==  1 ? f_unorderedOrGreater : f_greater;
2459 
2460   if (VM_Version::v9_instructions_work()) {
2461 
2462     mov(                   -1, Rresult );
2463     movcc( eq, true, fcc0,  0, Rresult );
2464     movcc( gt, true, fcc0,  1, Rresult );
2465 
2466   } else {
2467     Label done;
2468 
2469                                          set( -1, Rresult );
2470     //fb(lt, true, pn, done); delayed()->set( -1, Rresult );
2471     fb( eq, true, pn, done);  delayed()->set(  0, Rresult );
2472     fb( gt, true, pn, done);  delayed()->set(  1, Rresult );
2473 
2474     bind (done);
2475   }
2476 }
2477 
2478 
2479 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2480 {
2481   if (VM_Version::v9_instructions_work()) {
2482     Assembler::fneg(w, s, d);
2483   } else {
2484     if (w == FloatRegisterImpl::S) {


2651     if (top_reg_after_save == L1) {
2652       ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save);
2653     }
2654 
2655     if (ptr_reg_after_save == L2) {
2656       ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save);
2657     }
2658 
2659     Label(retry_get_lock);
2660     Label(not_same);
2661     Label(dont_yield);
2662 
2663     assert(lock_addr, "lock_address should be non null for v8");
2664     set((intptr_t)lock_addr, lock_ptr_reg);
2665     // Initialize yield counter
2666     mov(G0,yield_reg);
2667     mov(G0, yieldall_reg);
2668     set(StubRoutines::Sparc::locked, lock_reg);
2669 
2670     bind(retry_get_lock);
2671     cmp(yield_reg, V8AtomicOperationUnderLockSpinCount);
2672     br(Assembler::less, false, Assembler::pt, dont_yield);
2673     delayed()->nop();
2674 
2675     if(use_call_vm) {
2676       Untested("Need to verify global reg consistancy");
2677       call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg);
2678     } else {
2679       // Save the regs and make space for a C call
2680       save(SP, -96, SP);
2681       save_all_globals_into_locals();
2682       call(CAST_FROM_FN_PTR(address,os::yield_all));
2683       delayed()->mov(yieldall_reg, O0);
2684       restore_globals_from_locals();
2685       restore();
2686     }
2687 
2688     // reset the counter
2689     mov(G0,yield_reg);
2690     add(yieldall_reg, 1, yieldall_reg);
2691 
2692     bind(dont_yield);
2693     // try to get lock
2694     swap(lock_ptr_reg, 0, lock_reg);
2695 
2696     // did we get the lock?
2697     cmp(lock_reg, StubRoutines::Sparc::unlocked);
2698     br(Assembler::notEqual, true, Assembler::pn, retry_get_lock);
2699     delayed()->add(yield_reg,1,yield_reg);
2700 
2701     // yes, got lock.  do we have the same top?
2702     ld(top_ptr_reg_after_save, 0, value_reg);
2703     cmp(value_reg, top_reg_after_save);
2704     br(Assembler::notEqual, false, Assembler::pn, not_same);
2705     delayed()->nop();
2706 
2707     // yes, same top.
2708     st(ptr_reg_after_save, top_ptr_reg_after_save, 0);
2709     membar(Assembler::StoreStore);
2710 
2711     bind(not_same);
2712     mov(value_reg, ptr_reg_after_save);
2713     st(lock_reg, lock_ptr_reg, 0); // unlock
2714 
2715     restore();
2716   }
2717 }
2718 
2719 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
2720                                                       Register tmp,
2721                                                       int offset) {
2722   intptr_t value = *delayed_value_addr;
2723   if (value != 0)
2724     return RegisterOrConstant(value + offset);
2725 


2935                                          Register super_klass,
2936                                          Register temp_reg,
2937                                          Register temp2_reg,
2938                                          Label& L_success) {
2939   Label L_failure, L_pop_to_failure;
2940   check_klass_subtype_fast_path(sub_klass, super_klass,
2941                                 temp_reg, temp2_reg,
2942                                 &L_success, &L_failure, NULL);
2943   Register sub_2 = sub_klass;
2944   Register sup_2 = super_klass;
2945   if (!sub_2->is_global())  sub_2 = L0;
2946   if (!sup_2->is_global())  sup_2 = L1;
2947 
2948   save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
2949   check_klass_subtype_slow_path(sub_2, sup_2,
2950                                 L2, L3, L4, L5,
2951                                 NULL, &L_pop_to_failure);
2952 
2953   // on success:
2954   restore();
2955   ba(false, L_success);
2956   delayed()->nop();
2957 
2958   // on failure:
2959   bind(L_pop_to_failure);
2960   restore();
2961   bind(L_failure);
2962 }
2963 
2964 
2965 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
2966                                                    Register super_klass,
2967                                                    Register temp_reg,
2968                                                    Register temp2_reg,
2969                                                    Label* L_success,
2970                                                    Label* L_failure,
2971                                                    Label* L_slow_path,
2972                                         RegisterOrConstant super_check_offset,
2973                                         Register instanceof_hack) {
2974   int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
2975                    Klass::secondary_super_cache_offset_in_bytes());
2976   int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
2977                     Klass::super_check_offset_offset_in_bytes());
2978 
2979   bool must_load_sco  = (super_check_offset.constant_or_zero() == -1);
2980   bool need_slow_path = (must_load_sco ||
2981                          super_check_offset.constant_or_zero() == sco_offset);
2982 
2983   assert_different_registers(sub_klass, super_klass, temp_reg);
2984   if (super_check_offset.is_register()) {
2985     assert_different_registers(sub_klass, super_klass, temp_reg,
2986                                super_check_offset.as_register());
2987   } else if (must_load_sco) {
2988     assert(temp2_reg != noreg, "supply either a temp or a register offset");
2989   }
2990 
2991   Label L_fallthrough;
2992   int label_nulls = 0;
2993   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
2994   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
2995   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
2996   assert(label_nulls <= 1 || instanceof_hack != noreg ||
2997          (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
2998          "at most one NULL in the batch, usually");
2999 
3000   // Support for the instanceof hack, which uses delay slots to
3001   // set a destination register to zero or one.
3002   bool do_bool_sets = (instanceof_hack != noreg);
3003 #define BOOL_SET(bool_value)                            \
3004   if (do_bool_sets && bool_value >= 0)                  \
3005     set(bool_value, instanceof_hack)
3006 #define DELAYED_BOOL_SET(bool_value)                    \
3007   if (do_bool_sets && bool_value >= 0)                  \
3008     delayed()->set(bool_value, instanceof_hack);        \
3009   else delayed()->nop()
3010   // Hacked ba(), which may only be used just before L_fallthrough.
3011 #define FINAL_JUMP(label, bool_value)                   \
3012   if (&(label) == &L_fallthrough) {                     \
3013     BOOL_SET(bool_value);                               \
3014   } else {                                              \
3015     ba((do_bool_sets && bool_value >= 0), label);       \
3016     DELAYED_BOOL_SET(bool_value);                       \
3017   }
3018 
3019   // If the pointers are equal, we are done (e.g., String[] elements).
3020   // This self-check enables sharing of secondary supertype arrays among
3021   // non-primary types such as array-of-interface.  Otherwise, each such
3022   // type would need its own customized SSA.
3023   // We move this check to the front of the fast path because many
3024   // type checks are in fact trivially successful in this manner,
3025   // so we get a nicely predicted branch right at the start of the check.
3026   cmp(super_klass, sub_klass);
3027   brx(Assembler::equal, do_bool_sets, Assembler::pn, *L_success);
3028   DELAYED_BOOL_SET(1);
3029 
3030   // Check the supertype display:
3031   if (must_load_sco) {
3032     // The super check offset is always positive...
3033     lduw(super_klass, sco_offset, temp2_reg);
3034     super_check_offset = RegisterOrConstant(temp2_reg);
3035     // super_check_offset is register.
3036     assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register());
3037   }
3038   ld_ptr(sub_klass, super_check_offset, temp_reg);
3039   cmp(super_klass, temp_reg);
3040 
3041   // This check has worked decisively for primary supers.
3042   // Secondary supers are sought in the super_cache ('super_cache_addr').
3043   // (Secondary supers are interfaces and very deeply nested subtypes.)
3044   // This works in the same check above because of a tricky aliasing
3045   // between the super_cache and the primary super display elements.
3046   // (The 'super_check_addr' can address either, as the case requires.)
3047   // Note that the cache is updated below if it does not help us find
3048   // what we need immediately.
3049   // So if it was a primary super, we can just fail immediately.
3050   // Otherwise, it's the slow path for us (no success at this point).
3051 






3052   if (super_check_offset.is_register()) {
3053     brx(Assembler::equal, do_bool_sets, Assembler::pn, *L_success);
3054     delayed(); if (do_bool_sets)  BOOL_SET(1);
3055     // if !do_bool_sets, sneak the next cmp into the delay slot:
3056     cmp(super_check_offset.as_register(), sc_offset);
3057 
3058     if (L_failure == &L_fallthrough) {
3059       brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_slow_path);
3060       delayed()->nop();
3061       BOOL_SET(0);  // fallthrough on failure
3062     } else {
3063       brx(Assembler::notEqual, do_bool_sets, Assembler::pn, *L_failure);
3064       DELAYED_BOOL_SET(0);
3065       FINAL_JUMP(*L_slow_path, -1);  // -1 => vanilla delay slot
3066     }
3067   } else if (super_check_offset.as_constant() == sc_offset) {
3068     // Need a slow path; fast failure is impossible.
3069     if (L_slow_path == &L_fallthrough) {
3070       brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_success);
3071       DELAYED_BOOL_SET(1);
3072     } else {
3073       brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path);
3074       delayed()->nop();
3075       FINAL_JUMP(*L_success, 1);
3076     }
3077   } else {
3078     // No slow path; it's a fast decision.
3079     if (L_failure == &L_fallthrough) {
3080       brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_success);
3081       DELAYED_BOOL_SET(1);
3082       BOOL_SET(0);
3083     } else {
3084       brx(Assembler::notEqual, do_bool_sets, Assembler::pn, *L_failure);
3085       DELAYED_BOOL_SET(0);
3086       FINAL_JUMP(*L_success, 1);
3087     }
3088   }
3089 
3090   bind(L_fallthrough);
3091 
3092 #undef final_jump
3093 #undef bool_set
3094 #undef DELAYED_BOOL_SET
3095 #undef final_jump
3096 }
3097 
3098 
3099 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
3100                                                    Register super_klass,
3101                                                    Register count_temp,
3102                                                    Register scan_temp,
3103                                                    Register scratch_reg,
3104                                                    Register coop_reg,
3105                                                    Label* L_success,
3106                                                    Label* L_failure) {
3107   assert_different_registers(sub_klass, super_klass,
3108                              count_temp, scan_temp, scratch_reg, coop_reg);
3109 
3110   Label L_fallthrough, L_loop;
3111   int label_nulls = 0;
3112   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
3113   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
3114   assert(label_nulls <= 1, "at most one NULL in the batch");
3115 


3168     // Don't use load_heap_oop; we don't want to decode the element.
3169     lduw(   scan_temp, elem_offset, scratch_reg );
3170   } else {
3171     ld_ptr( scan_temp, elem_offset, scratch_reg );
3172   }
3173 
3174   // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
3175   cmp(scratch_reg, search_key);
3176 
3177   // A miss means we are NOT a subtype and need to keep looping
3178   brx(Assembler::notEqual, false, Assembler::pn, L_loop);
3179   delayed()->deccc(count_temp); // decrement trip counter in delay slot
3180 
3181   // Falling out the bottom means we found a hit; we ARE a subtype
3182   if (decode_super_klass) decode_heap_oop(super_klass);
3183 
3184   // Success.  Cache the super we found and proceed in triumph.
3185   st_ptr(super_klass, sub_klass, sc_offset);
3186 
3187   if (L_success != &L_fallthrough) {
3188     ba(false, *L_success);
3189     delayed()->nop();
3190   }
3191 
3192   bind(L_fallthrough);
3193 }
3194 
3195 
3196 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
3197                                               Register temp_reg,
3198                                               Label& wrong_method_type) {
3199   assert_different_registers(mtype_reg, mh_reg, temp_reg);
3200   // compare method type against that of the receiver
3201   RegisterOrConstant mhtype_offset = delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg);
3202   load_heap_oop(mh_reg, mhtype_offset, temp_reg);
3203   cmp(temp_reg, mtype_reg);
3204   br(Assembler::notEqual, false, Assembler::pn, wrong_method_type);
3205   delayed()->nop();
3206 }
3207 
3208 
3209 // A method handle has a "vmslots" field which gives the size of its
3210 // argument list in JVM stack slots.  This field is either located directly
3211 // in every method handle, or else is indirectly accessed through the
3212 // method handle's MethodType.  This macro hides the distinction.
3213 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
3214                                                 Register temp_reg) {
3215   assert_different_registers(vmslots_reg, mh_reg, temp_reg);
3216   // load mh.type.form.vmslots
3217   if (java_lang_invoke_MethodHandle::vmslots_offset_in_bytes() != 0) {
3218     // hoist vmslots into every mh to avoid dependent load chain
3219     ld(           Address(mh_reg,    delayed_value(java_lang_invoke_MethodHandle::vmslots_offset_in_bytes, temp_reg)),   vmslots_reg);
3220   } else {
3221     Register temp2_reg = vmslots_reg;
3222     load_heap_oop(Address(mh_reg,    delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg)),      temp2_reg);
3223     load_heap_oop(Address(temp2_reg, delayed_value(java_lang_invoke_MethodType::form_offset_in_bytes, temp_reg)),        temp2_reg);
3224     ld(           Address(temp2_reg, delayed_value(java_lang_invoke_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)), vmslots_reg);
3225   }


3278                                           Register temp_reg,
3279                                           Label& done, Label* slow_case,
3280                                           BiasedLockingCounters* counters) {
3281   assert(UseBiasedLocking, "why call this otherwise?");
3282 
3283   if (PrintBiasedLockingStatistics) {
3284     assert_different_registers(obj_reg, mark_reg, temp_reg, O7);
3285     if (counters == NULL)
3286       counters = BiasedLocking::counters();
3287   }
3288 
3289   Label cas_label;
3290 
3291   // Biased locking
3292   // See whether the lock is currently biased toward our thread and
3293   // whether the epoch is still valid
3294   // Note that the runtime guarantees sufficient alignment of JavaThread
3295   // pointers to allow age to be placed into low bits
3296   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
3297   and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3298   cmp(temp_reg, markOopDesc::biased_lock_pattern);
3299   brx(Assembler::notEqual, false, Assembler::pn, cas_label);
3300   delayed()->nop();
3301 
3302   load_klass(obj_reg, temp_reg);
3303   ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3304   or3(G2_thread, temp_reg, temp_reg);
3305   xor3(mark_reg, temp_reg, temp_reg);
3306   andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg);
3307   if (counters != NULL) {
3308     cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg);
3309     // Reload mark_reg as we may need it later
3310     ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg);
3311   }
3312   brx(Assembler::equal, true, Assembler::pt, done);
3313   delayed()->nop();
3314 
3315   Label try_revoke_bias;
3316   Label try_rebias;
3317   Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
3318   assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3319 
3320   // At this point we know that the header has the bias pattern and


3347   // fails we will go in to the runtime to revoke the object's bias.
3348   // Note that we first construct the presumed unbiased header so we
3349   // don't accidentally blow away another thread's valid bias.
3350   delayed()->and3(mark_reg,
3351                   markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place,
3352                   mark_reg);
3353   or3(G2_thread, mark_reg, temp_reg);
3354   casn(mark_addr.base(), mark_reg, temp_reg);
3355   // If the biasing toward our thread failed, this means that
3356   // another thread succeeded in biasing it toward itself and we
3357   // need to revoke that bias. The revocation will occur in the
3358   // interpreter runtime in the slow case.
3359   cmp(mark_reg, temp_reg);
3360   if (counters != NULL) {
3361     cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg);
3362   }
3363   if (slow_case != NULL) {
3364     brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3365     delayed()->nop();
3366   }
3367   br(Assembler::always, false, Assembler::pt, done);
3368   delayed()->nop();
3369 
3370   bind(try_rebias);
3371   // At this point we know the epoch has expired, meaning that the
3372   // current "bias owner", if any, is actually invalid. Under these
3373   // circumstances _only_, we are allowed to use the current header's
3374   // value as the comparison value when doing the cas to acquire the
3375   // bias in the current epoch. In other words, we allow transfer of
3376   // the bias from one thread to another directly in this situation.
3377   //
3378   // FIXME: due to a lack of registers we currently blow away the age
3379   // bits in this situation. Should attempt to preserve them.
3380   load_klass(obj_reg, temp_reg);
3381   ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3382   or3(G2_thread, temp_reg, temp_reg);
3383   casn(mark_addr.base(), mark_reg, temp_reg);
3384   // If the biasing toward our thread failed, this means that
3385   // another thread succeeded in biasing it toward itself and we
3386   // need to revoke that bias. The revocation will occur in the
3387   // interpreter runtime in the slow case.
3388   cmp(mark_reg, temp_reg);
3389   if (counters != NULL) {
3390     cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg);
3391   }
3392   if (slow_case != NULL) {
3393     brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3394     delayed()->nop();
3395   }
3396   br(Assembler::always, false, Assembler::pt, done);
3397   delayed()->nop();
3398 
3399   bind(try_revoke_bias);
3400   // The prototype mark in the klass doesn't have the bias bit set any
3401   // more, indicating that objects of this data type are not supposed
3402   // to be biased any more. We are going to try to reset the mark of
3403   // this object to the prototype value and fall through to the
3404   // CAS-based locking scheme. Note that if our CAS fails, it means
3405   // that another thread raced us for the privilege of revoking the
3406   // bias of this particular object, so it's okay to continue in the
3407   // normal locking code.
3408   //
3409   // FIXME: due to a lack of registers we currently blow away the age
3410   // bits in this situation. Should attempt to preserve them.
3411   load_klass(obj_reg, temp_reg);
3412   ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3413   casn(mark_addr.base(), mark_reg, temp_reg);
3414   // Fall through to the normal CAS-based lock, because no matter what
3415   // the result of the above CAS, some thread must have succeeded in
3416   // removing the bias bit from the object's header.
3417   if (counters != NULL) {


3428   // Note: we do not have to check the thread ID for two reasons.
3429   // First, the interpreter checks for IllegalMonitorStateException at
3430   // a higher level. Second, if the bias was revoked while we held the
3431   // lock, the object could not be rebiased toward another thread, so
3432   // the bias bit would be clear.
3433   ld_ptr(mark_addr, temp_reg);
3434   and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3435   cmp(temp_reg, markOopDesc::biased_lock_pattern);
3436   brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done);
3437   delayed();
3438   if (!allow_delay_slot_filling) {
3439     nop();
3440   }
3441 }
3442 
3443 
3444 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by
3445 // Solaris/SPARC's "as".  Another apt name would be cas_ptr()
3446 
3447 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) {
3448   casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()) ;
3449 }
3450 
3451 
3452 
3453 // compiler_lock_object() and compiler_unlock_object() are direct transliterations
3454 // of i486.ad fast_lock() and fast_unlock().  See those methods for detailed comments.
3455 // The code could be tightened up considerably.
3456 //
3457 // box->dhw disposition - post-conditions at DONE_LABEL.
3458 // -   Successful inflated lock:  box->dhw != 0.
3459 //     Any non-zero value suffices.
3460 //     Consider G2_thread, rsp, boxReg, or unused_mark()
3461 // -   Successful Stack-lock: box->dhw == mark.
3462 //     box->dhw must contain the displaced mark word value
3463 // -   Failure -- icc.ZFlag == 0 and box->dhw is undefined.
3464 //     The slow-path fast_enter() and slow_enter() operators
3465 //     are responsible for setting box->dhw = NonZero (typically ::unused_mark).
3466 // -   Biased: box->dhw is undefined
3467 //
3468 // SPARC refworkload performance - specifically jetstream and scimark - are
3469 // extremely sensitive to the size of the code emitted by compiler_lock_object
3470 // and compiler_unlock_object.  Critically, the key factor is code size, not path
3471 // length.  (Simply experiments to pad CLO with unexecuted NOPs demonstrte the
3472 // effect).
3473 
3474 
3475 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark,
3476                                           Register Rbox, Register Rscratch,
3477                                           BiasedLockingCounters* counters,
3478                                           bool try_bias) {
3479    Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3480 
3481    verify_oop(Roop);
3482    Label done ;
3483 
3484    if (counters != NULL) {
3485      inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch);
3486    }
3487 
3488    if (EmitSync & 1) {
3489      mov    (3, Rscratch) ;
3490      st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3491      cmp    (SP, G0) ;
3492      return ;
3493    }
3494 
3495    if (EmitSync & 2) {
3496 
3497      // Fetch object's markword
3498      ld_ptr(mark_addr, Rmark);
3499 
3500      if (try_bias) {
3501         biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3502      }
3503 
3504      // Save Rbox in Rscratch to be used for the cas operation
3505      mov(Rbox, Rscratch);
3506 
3507      // set Rmark to markOop | markOopDesc::unlocked_value
3508      or3(Rmark, markOopDesc::unlocked_value, Rmark);
3509 
3510      // Initialize the box.  (Must happen before we update the object mark!)
3511      st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3512 
3513      // compare object markOop with Rmark and if equal exchange Rscratch with object markOop
3514      assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3515      casx_under_lock(mark_addr.base(), Rmark, Rscratch,
3516         (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3517 
3518      // if compare/exchange succeeded we found an unlocked object and we now have locked it
3519      // hence we are done
3520      cmp(Rmark, Rscratch);
3521 #ifdef _LP64
3522      sub(Rscratch, STACK_BIAS, Rscratch);
3523 #endif
3524      brx(Assembler::equal, false, Assembler::pt, done);
3525      delayed()->sub(Rscratch, SP, Rscratch);  //pull next instruction into delay slot
3526 
3527      // we did not find an unlocked object so see if this is a recursive case
3528      // sub(Rscratch, SP, Rscratch);
3529      assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3530      andcc(Rscratch, 0xfffff003, Rscratch);
3531      st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3532      bind (done) ;
3533      return ;
3534    }
3535 
3536    Label Egress ;
3537 
3538    if (EmitSync & 256) {
3539       Label IsInflated ;
3540 
3541       ld_ptr (mark_addr, Rmark);           // fetch obj->mark
3542       // Triage: biased, stack-locked, neutral, inflated
3543       if (try_bias) {
3544         biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3545         // Invariant: if control reaches this point in the emitted stream
3546         // then Rmark has not been modified.
3547       }
3548 
3549       // Store mark into displaced mark field in the on-stack basic-lock "box"
3550       // Critically, this must happen before the CAS
3551       // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty.
3552       st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3553       andcc  (Rmark, 2, G0) ;
3554       brx    (Assembler::notZero, false, Assembler::pn, IsInflated) ;
3555       delayed() ->
3556 
3557       // Try stack-lock acquisition.
3558       // Beware: the 1st instruction is in a delay slot
3559       mov    (Rbox,  Rscratch);
3560       or3    (Rmark, markOopDesc::unlocked_value, Rmark);
3561       assert (mark_addr.disp() == 0, "cas must take a zero displacement");
3562       casn   (mark_addr.base(), Rmark, Rscratch) ;
3563       cmp    (Rmark, Rscratch);
3564       brx    (Assembler::equal, false, Assembler::pt, done);
3565       delayed()->sub(Rscratch, SP, Rscratch);
3566 
3567       // Stack-lock attempt failed - check for recursive stack-lock.
3568       // See the comments below about how we might remove this case.
3569 #ifdef _LP64
3570       sub    (Rscratch, STACK_BIAS, Rscratch);
3571 #endif
3572       assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3573       andcc  (Rscratch, 0xfffff003, Rscratch);
3574       br     (Assembler::always, false, Assembler::pt, done) ;
3575       delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3576 
3577       bind   (IsInflated) ;
3578       if (EmitSync & 64) {
3579          // If m->owner != null goto IsLocked
3580          // Pessimistic form: Test-and-CAS vs CAS
3581          // The optimistic form avoids RTS->RTO cache line upgrades.
3582          ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3583          andcc  (Rscratch, Rscratch, G0) ;
3584          brx    (Assembler::notZero, false, Assembler::pn, done) ;
3585          delayed()->nop() ;
3586          // m->owner == null : it's unlocked.
3587       }
3588 
3589       // Try to CAS m->owner from null to Self
3590       // Invariant: if we acquire the lock then _recursions should be 0.
3591       add    (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3592       mov    (G2_thread, Rscratch) ;
3593       casn   (Rmark, G0, Rscratch) ;
3594       cmp    (Rscratch, G0) ;
3595       // Intentional fall-through into done
3596    } else {
3597       // Aggressively avoid the Store-before-CAS penalty
3598       // Defer the store into box->dhw until after the CAS
3599       Label IsInflated, Recursive ;
3600 
3601 // Anticipate CAS -- Avoid RTS->RTO upgrade
3602 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ;
3603 
3604       ld_ptr (mark_addr, Rmark);           // fetch obj->mark
3605       // Triage: biased, stack-locked, neutral, inflated
3606 
3607       if (try_bias) {
3608         biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3609         // Invariant: if control reaches this point in the emitted stream
3610         // then Rmark has not been modified.
3611       }
3612       andcc  (Rmark, 2, G0) ;
3613       brx    (Assembler::notZero, false, Assembler::pn, IsInflated) ;
3614       delayed()->                         // Beware - dangling delay-slot
3615 
3616       // Try stack-lock acquisition.
3617       // Transiently install BUSY (0) encoding in the mark word.
3618       // if the CAS of 0 into the mark was successful then we execute:
3619       //   ST box->dhw  = mark   -- save fetched mark in on-stack basiclock box
3620       //   ST obj->mark = box    -- overwrite transient 0 value
3621       // This presumes TSO, of course.
3622 
3623       mov    (0, Rscratch) ;
3624       or3    (Rmark, markOopDesc::unlocked_value, Rmark);
3625       assert (mark_addr.disp() == 0, "cas must take a zero displacement");
3626       casn   (mark_addr.base(), Rmark, Rscratch) ;
3627 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ;
3628       cmp    (Rscratch, Rmark) ;
3629       brx    (Assembler::notZero, false, Assembler::pn, Recursive) ;
3630       delayed() ->
3631         st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3632       if (counters != NULL) {
3633         cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3634       }
3635       br     (Assembler::always, false, Assembler::pt, done);
3636       delayed() ->
3637         st_ptr (Rbox, mark_addr) ;
3638 
3639       bind   (Recursive) ;
3640       // Stack-lock attempt failed - check for recursive stack-lock.
3641       // Tests show that we can remove the recursive case with no impact
3642       // on refworkload 0.83.  If we need to reduce the size of the code
3643       // emitted by compiler_lock_object() the recursive case is perfect
3644       // candidate.
3645       //
3646       // A more extreme idea is to always inflate on stack-lock recursion.
3647       // This lets us eliminate the recursive checks in compiler_lock_object
3648       // and compiler_unlock_object and the (box->dhw == 0) encoding.
3649       // A brief experiment - requiring changes to synchronizer.cpp, interpreter,
3650       // and showed a performance *increase*.  In the same experiment I eliminated
3651       // the fast-path stack-lock code from the interpreter and always passed
3652       // control to the "slow" operators in synchronizer.cpp.
3653 
3654       // RScratch contains the fetched obj->mark value from the failed CASN.
3655 #ifdef _LP64
3656       sub    (Rscratch, STACK_BIAS, Rscratch);
3657 #endif
3658       sub(Rscratch, SP, Rscratch);
3659       assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3660       andcc  (Rscratch, 0xfffff003, Rscratch);
3661       if (counters != NULL) {
3662         // Accounting needs the Rscratch register
3663         st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3664         cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3665         br     (Assembler::always, false, Assembler::pt, done) ;
3666         delayed()->nop() ;
3667       } else {
3668         br     (Assembler::always, false, Assembler::pt, done) ;
3669         delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3670       }
3671 
3672       bind   (IsInflated) ;
3673       if (EmitSync & 64) {
3674          // If m->owner != null goto IsLocked
3675          // Test-and-CAS vs CAS
3676          // Pessimistic form avoids futile (doomed) CAS attempts
3677          // The optimistic form avoids RTS->RTO cache line upgrades.
3678          ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3679          andcc  (Rscratch, Rscratch, G0) ;
3680          brx    (Assembler::notZero, false, Assembler::pn, done) ;
3681          delayed()->nop() ;
3682          // m->owner == null : it's unlocked.
3683       }
3684 
3685       // Try to CAS m->owner from null to Self
3686       // Invariant: if we acquire the lock then _recursions should be 0.
3687       add    (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3688       mov    (G2_thread, Rscratch) ;
3689       casn   (Rmark, G0, Rscratch) ;
3690       cmp    (Rscratch, G0) ;
3691       // ST box->displaced_header = NonZero.
3692       // Any non-zero value suffices:
3693       //    unused_mark(), G2_thread, RBox, RScratch, rsp, etc.
3694       st_ptr (Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes());
3695       // Intentional fall-through into done
3696    }
3697 
3698    bind   (done) ;
3699 }
3700 
3701 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark,
3702                                             Register Rbox, Register Rscratch,
3703                                             bool try_bias) {
3704    Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3705 
3706    Label done ;
3707 
3708    if (EmitSync & 4) {
3709      cmp  (SP, G0) ;
3710      return ;
3711    }
3712 
3713    if (EmitSync & 8) {
3714      if (try_bias) {
3715         biased_locking_exit(mark_addr, Rscratch, done);
3716      }
3717 
3718      // Test first if it is a fast recursive unlock
3719      ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark);
3720      cmp(Rmark, G0);
3721      brx(Assembler::equal, false, Assembler::pt, done);
3722      delayed()->nop();
3723 
3724      // Check if it is still a light weight lock, this is is true if we see
3725      // the stack address of the basicLock in the markOop of the object
3726      assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3727      casx_under_lock(mark_addr.base(), Rbox, Rmark,
3728        (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3729      br (Assembler::always, false, Assembler::pt, done);
3730      delayed()->cmp(Rbox, Rmark);
3731      bind (done) ;
3732      return ;
3733    }
3734 
3735    // Beware ... If the aggregate size of the code emitted by CLO and CUO is
3736    // is too large performance rolls abruptly off a cliff.
3737    // This could be related to inlining policies, code cache management, or
3738    // I$ effects.
3739    Label LStacked ;
3740 
3741    if (try_bias) {
3742       // TODO: eliminate redundant LDs of obj->mark
3743       biased_locking_exit(mark_addr, Rscratch, done);
3744    }
3745 
3746    ld_ptr (Roop, oopDesc::mark_offset_in_bytes(), Rmark) ;
3747    ld_ptr (Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch);
3748    andcc  (Rscratch, Rscratch, G0);
3749    brx    (Assembler::zero, false, Assembler::pn, done);
3750    delayed()-> nop() ;      // consider: relocate fetch of mark, above, into this DS
3751    andcc  (Rmark, 2, G0) ;
3752    brx    (Assembler::zero, false, Assembler::pt, LStacked) ;
3753    delayed()-> nop() ;
3754 
3755    // It's inflated
3756    // Conceptually we need a #loadstore|#storestore "release" MEMBAR before
3757    // the ST of 0 into _owner which releases the lock.  This prevents loads
3758    // and stores within the critical section from reordering (floating)
3759    // past the store that releases the lock.  But TSO is a strong memory model
3760    // and that particular flavor of barrier is a noop, so we can safely elide it.
3761    // Note that we use 1-0 locking by default for the inflated case.  We
3762    // close the resultant (and rare) race by having contented threads in
3763    // monitorenter periodically poll _owner.
3764    ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3765    ld_ptr (Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox);
3766    xor3   (Rscratch, G2_thread, Rscratch) ;
3767    orcc   (Rbox, Rscratch, Rbox) ;
3768    brx    (Assembler::notZero, false, Assembler::pn, done) ;
3769    delayed()->
3770    ld_ptr (Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch);
3771    ld_ptr (Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox);
3772    orcc   (Rbox, Rscratch, G0) ;
3773    if (EmitSync & 65536) {
3774       Label LSucc ;
3775       brx    (Assembler::notZero, false, Assembler::pn, LSucc) ;
3776       delayed()->nop() ;
3777       br     (Assembler::always, false, Assembler::pt, done) ;
3778       delayed()->
3779       st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3780 
3781       bind   (LSucc) ;
3782       st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3783       if (os::is_MP()) { membar (StoreLoad) ; }
3784       ld_ptr (Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch);
3785       andcc  (Rscratch, Rscratch, G0) ;
3786       brx    (Assembler::notZero, false, Assembler::pt, done) ;
3787       delayed()-> andcc (G0, G0, G0) ;
3788       add    (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3789       mov    (G2_thread, Rscratch) ;
3790       casn   (Rmark, G0, Rscratch) ;
3791       cmp    (Rscratch, G0) ;
3792       // invert icc.zf and goto done
3793       brx    (Assembler::notZero, false, Assembler::pt, done) ;
3794       delayed() -> cmp (G0, G0) ;
3795       br     (Assembler::always, false, Assembler::pt, done);
3796       delayed() -> cmp (G0, 1) ;
3797    } else {
3798       brx    (Assembler::notZero, false, Assembler::pn, done) ;
3799       delayed()->nop() ;
3800       br     (Assembler::always, false, Assembler::pt, done) ;
3801       delayed()->
3802       st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3803    }
3804 
3805    bind   (LStacked) ;
3806    // Consider: we could replace the expensive CAS in the exit
3807    // path with a simple ST of the displaced mark value fetched from
3808    // the on-stack basiclock box.  That admits a race where a thread T2
3809    // in the slow lock path -- inflating with monitor M -- could race a
3810    // thread T1 in the fast unlock path, resulting in a missed wakeup for T2.
3811    // More precisely T1 in the stack-lock unlock path could "stomp" the
3812    // inflated mark value M installed by T2, resulting in an orphan
3813    // object monitor M and T2 becoming stranded.  We can remedy that situation
3814    // by having T2 periodically poll the object's mark word using timed wait
3815    // operations.  If T2 discovers that a stomp has occurred it vacates
3816    // the monitor M and wakes any other threads stranded on the now-orphan M.
3817    // In addition the monitor scavenger, which performs deflation,
3818    // would also need to check for orpan monitors and stranded threads.
3819    //
3820    // Finally, inflation is also used when T2 needs to assign a hashCode
3821    // to O and O is stack-locked by T1.  The "stomp" race could cause
3822    // an assigned hashCode value to be lost.  We can avoid that condition
3823    // and provide the necessary hashCode stability invariants by ensuring
3824    // that hashCode generation is idempotent between copying GCs.
3825    // For example we could compute the hashCode of an object O as
3826    // O's heap address XOR some high quality RNG value that is refreshed
3827    // at GC-time.  The monitor scavenger would install the hashCode
3828    // found in any orphan monitors.  Again, the mechanism admits a
3829    // lost-update "stomp" WAW race but detects and recovers as needed.
3830    //
3831    // A prototype implementation showed excellent results, although
3832    // the scavenger and timeout code was rather involved.
3833 
3834    casn   (mark_addr.base(), Rbox, Rscratch) ;
3835    cmp    (Rbox, Rscratch);
3836    // Intentional fall through into done ...
3837 
3838    bind   (done) ;
3839 }
3840 
3841 
3842 
3843 void MacroAssembler::print_CPU_state() {
3844   // %%%%% need to implement this
3845 }
3846 
3847 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
3848   // %%%%% need to implement this
3849 }
3850 
3851 void MacroAssembler::push_IU_state() {
3852   // %%%%% need to implement this
3853 }
3854 
3855 
3856 void MacroAssembler::pop_IU_state() {
3857   // %%%%% need to implement this
3858 }


3874 
3875 
3876 void MacroAssembler::pop_CPU_state() {
3877   // %%%%% need to implement this
3878 }
3879 
3880 
3881 
3882 void MacroAssembler::verify_tlab() {
3883 #ifdef ASSERT
3884   if (UseTLAB && VerifyOops) {
3885     Label next, next2, ok;
3886     Register t1 = L0;
3887     Register t2 = L1;
3888     Register t3 = L2;
3889 
3890     save_frame(0);
3891     ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3892     ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2);
3893     or3(t1, t2, t3);
3894     cmp(t1, t2);
3895     br(Assembler::greaterEqual, false, Assembler::pn, next);
3896     delayed()->nop();
3897     stop("assert(top >= start)");
3898     should_not_reach_here();
3899 
3900     bind(next);
3901     ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3902     ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2);
3903     or3(t3, t2, t3);
3904     cmp(t1, t2);
3905     br(Assembler::lessEqual, false, Assembler::pn, next2);
3906     delayed()->nop();
3907     stop("assert(top <= end)");
3908     should_not_reach_here();
3909 
3910     bind(next2);
3911     and3(t3, MinObjAlignmentInBytesMask, t3);
3912     cmp(t3, 0);
3913     br(Assembler::lessEqual, false, Assembler::pn, ok);
3914     delayed()->nop();
3915     stop("assert(aligned)");
3916     should_not_reach_here();
3917 
3918     bind(ok);
3919     restore();
3920   }
3921 #endif
3922 }
3923 
3924 
3925 void MacroAssembler::eden_allocate(
3926   Register obj,                        // result: pointer to object after successful allocation
3927   Register var_size_in_bytes,          // object size in bytes if unknown at compile time; invalid otherwise
3928   int      con_size_in_bytes,          // object size in bytes if   known at compile time
3929   Register t1,                         // temp register
3930   Register t2,                         // temp register
3931   Label&   slow_case                   // continuation point if fast allocation fails
3932 ){
3933   // make sure arguments make sense
3934   assert_different_registers(obj, var_size_in_bytes, t1, t2);
3935   assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size");
3936   assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3937 
3938   if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
3939     // No allocation in the shared eden.
3940     br(Assembler::always, false, Assembler::pt, slow_case);
3941     delayed()->nop();
3942   } else {
3943     // get eden boundaries
3944     // note: we need both top & top_addr!
3945     const Register top_addr = t1;
3946     const Register end      = t2;
3947 
3948     CollectedHeap* ch = Universe::heap();
3949     set((intx)ch->top_addr(), top_addr);
3950     intx delta = (intx)ch->end_addr() - (intx)ch->top_addr();
3951     ld_ptr(top_addr, delta, end);
3952     ld_ptr(top_addr, 0, obj);
3953 
3954     // try to allocate
3955     Label retry;
3956     bind(retry);
3957 #ifdef ASSERT
3958     // make sure eden top is properly aligned
3959     {
3960       Label L;
3961       btst(MinObjAlignmentInBytesMask, obj);


4055     bind(L);
4056   }
4057 #endif // ASSERT
4058 
4059   // update the tlab top pointer
4060   st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
4061   verify_tlab();
4062 }
4063 
4064 
4065 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
4066   Register top = O0;
4067   Register t1 = G1;
4068   Register t2 = G3;
4069   Register t3 = O1;
4070   assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */);
4071   Label do_refill, discard_tlab;
4072 
4073   if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
4074     // No allocation in the shared eden.
4075     br(Assembler::always, false, Assembler::pt, slow_case);
4076     delayed()->nop();
4077   }
4078 
4079   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top);
4080   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1);
4081   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2);
4082 
4083   // calculate amount of free space
4084   sub(t1, top, t1);
4085   srl_ptr(t1, LogHeapWordSize, t1);
4086 
4087   // Retain tlab and allocate object in shared space if
4088   // the amount free in the tlab is too large to discard.
4089   cmp(t1, t2);
4090   brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab);
4091 
4092   // increment waste limit to prevent getting stuck on this slow path
4093   delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2);
4094   st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
4095   if (TLABStats) {
4096     // increment number of slow_allocations
4097     ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2);
4098     add(t2, 1, t2);
4099     stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()));
4100   }
4101   br(Assembler::always, false, Assembler::pt, try_eden);
4102   delayed()->nop();
4103 
4104   bind(discard_tlab);
4105   if (TLABStats) {
4106     // increment number of refills
4107     ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2);
4108     add(t2, 1, t2);
4109     stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()));
4110     // accumulate wastage
4111     ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2);
4112     add(t2, t1, t2);
4113     stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
4114   }
4115 
4116   // if tlab is currently allocated (top or end != null) then
4117   // fill [top, end + alignment_reserve) with array object
4118   br_null(top, false, Assembler::pn, do_refill);
4119   delayed()->nop();
4120 
4121   set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2);
4122   st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word
4123   // set klass to intArrayKlass
4124   sub(t1, typeArrayOopDesc::header_size(T_INT), t1);
4125   add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1);
4126   sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1);
4127   st(t1, top, arrayOopDesc::length_offset_in_bytes());
4128   set((intptr_t)Universe::intArrayKlassObj_addr(), t2);
4129   ld_ptr(t2, 0, t2);
4130   // store klass last.  concurrent gcs assumes klass length is valid if
4131   // klass field is not null.
4132   store_klass(t2, top);
4133   verify_oop(top);
4134 
4135   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1);
4136   sub(top, t1, t1); // size of tlab's allocated portion
4137   incr_allocated_bytes(t1, t2, t3);
4138 
4139   // refill the tlab with an eden allocation
4140   bind(do_refill);
4141   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1);
4142   sll_ptr(t1, LogHeapWordSize, t1);
4143   // allocate new tlab, address returned in top
4144   eden_allocate(top, t1, 0, t2, t3, slow_case);
4145 
4146   st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset()));
4147   st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
4148 #ifdef ASSERT
4149   // check that tlab_size (t1) is still valid
4150   {
4151     Label ok;
4152     ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2);
4153     sll_ptr(t2, LogHeapWordSize, t2);
4154     cmp(t1, t2);
4155     br(Assembler::equal, false, Assembler::pt, ok);
4156     delayed()->nop();
4157     stop("assert(t1 == tlab_size)");
4158     should_not_reach_here();
4159 
4160     bind(ok);
4161   }
4162 #endif // ASSERT
4163   add(top, t1, top); // t1 is tlab_size
4164   sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top);
4165   st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset()));
4166   verify_tlab();
4167   br(Assembler::always, false, Assembler::pt, retry);
4168   delayed()->nop();
4169 }
4170 
4171 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes,
4172                                           Register t1, Register t2) {
4173   // Bump total bytes allocated by this thread
4174   assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch
4175   assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2);
4176   // v8 support has gone the way of the dodo
4177   ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1);
4178   add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1);
4179   stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset()));
4180 }
4181 
4182 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
4183   switch (cond) {
4184     // Note some conditions are synonyms for others
4185     case Assembler::never:                return Assembler::always;
4186     case Assembler::zero:                 return Assembler::notZero;
4187     case Assembler::lessEqual:            return Assembler::greater;
4188     case Assembler::less:                 return Assembler::greaterEqual;


4273     set((-i*offset)+STACK_BIAS, Rscratch);
4274     st(G0, Rtsp, Rscratch);
4275   }
4276 }
4277 
4278 ///////////////////////////////////////////////////////////////////////////////////
4279 #ifndef SERIALGC
4280 
4281 static address satb_log_enqueue_with_frame = NULL;
4282 static u_char* satb_log_enqueue_with_frame_end = NULL;
4283 
4284 static address satb_log_enqueue_frameless = NULL;
4285 static u_char* satb_log_enqueue_frameless_end = NULL;
4286 
4287 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions?
4288 
4289 static void generate_satb_log_enqueue(bool with_frame) {
4290   BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize);
4291   CodeBuffer buf(bb);
4292   MacroAssembler masm(&buf);
4293   address start = masm.pc();



4294   Register pre_val;
4295 
4296   Label refill, restart;
4297   if (with_frame) {
4298     masm.save_frame(0);
4299     pre_val = I0;  // Was O0 before the save.
4300   } else {
4301     pre_val = O0;
4302   }
4303   int satb_q_index_byte_offset =
4304     in_bytes(JavaThread::satb_mark_queue_offset() +
4305              PtrQueue::byte_offset_of_index());
4306   int satb_q_buf_byte_offset =
4307     in_bytes(JavaThread::satb_mark_queue_offset() +
4308              PtrQueue::byte_offset_of_buf());
4309   assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) &&
4310          in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t),
4311          "check sizes in assembly below");
4312 
4313   masm.bind(restart);
4314   masm.ld_ptr(G2_thread, satb_q_index_byte_offset, L0);
4315 
4316   masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, L0, refill);
4317   // If the branch is taken, no harm in executing this in the delay slot.
4318   masm.delayed()->ld_ptr(G2_thread, satb_q_buf_byte_offset, L1);
4319   masm.sub(L0, oopSize, L0);
4320 
4321   masm.st_ptr(pre_val, L1, L0);  // [_buf + index] := I0
4322   if (!with_frame) {
4323     // Use return-from-leaf
4324     masm.retl();
4325     masm.delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset);
4326   } else {
4327     // Not delayed.
4328     masm.st_ptr(L0, G2_thread, satb_q_index_byte_offset);
4329   }
4330   if (with_frame) {
4331     masm.ret();
4332     masm.delayed()->restore();
4333   }
4334   masm.bind(refill);
4335 
4336   address handle_zero =
4337     CAST_FROM_FN_PTR(address,
4338                      &SATBMarkQueueSet::handle_zero_index_for_thread);
4339   // This should be rare enough that we can afford to save all the
4340   // scratch registers that the calling context might be using.
4341   masm.mov(G1_scratch, L0);
4342   masm.mov(G3_scratch, L1);
4343   masm.mov(G4, L2);
4344   // We need the value of O0 above (for the write into the buffer), so we
4345   // save and restore it.
4346   masm.mov(O0, L3);
4347   // Since the call will overwrite O7, we save and restore that, as well.
4348   masm.mov(O7, L4);
4349   masm.call_VM_leaf(L5, handle_zero, G2_thread);
4350   masm.mov(L0, G1_scratch);
4351   masm.mov(L1, G3_scratch);
4352   masm.mov(L2, G4);
4353   masm.mov(L3, O0);
4354   masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4355   masm.delayed()->mov(L4, O7);
4356 
4357   if (with_frame) {
4358     satb_log_enqueue_with_frame = start;
4359     satb_log_enqueue_with_frame_end = masm.pc();
4360   } else {
4361     satb_log_enqueue_frameless = start;
4362     satb_log_enqueue_frameless_end = masm.pc();
4363   }


4364 }
4365 
4366 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) {
4367   if (with_frame) {
4368     if (satb_log_enqueue_with_frame == 0) {
4369       generate_satb_log_enqueue(with_frame);
4370       assert(satb_log_enqueue_with_frame != 0, "postcondition.");
4371       if (G1SATBPrintStubs) {
4372         tty->print_cr("Generated with-frame satb enqueue:");
4373         Disassembler::decode((u_char*)satb_log_enqueue_with_frame,
4374                              satb_log_enqueue_with_frame_end,
4375                              tty);
4376       }
4377     }
4378   } else {
4379     if (satb_log_enqueue_frameless == 0) {
4380       generate_satb_log_enqueue(with_frame);
4381       assert(satb_log_enqueue_frameless != 0, "postcondition.");
4382       if (G1SATBPrintStubs) {
4383         tty->print_cr("Generated frameless satb enqueue:");


4409     assert(pre_val == noreg, "check this code");
4410   }
4411 
4412   // Is marking active?
4413   if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4414     ld(G2,
4415        in_bytes(JavaThread::satb_mark_queue_offset() +
4416                 PtrQueue::byte_offset_of_active()),
4417        tmp);
4418   } else {
4419     guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1,
4420               "Assumption");
4421     ldsb(G2,
4422          in_bytes(JavaThread::satb_mark_queue_offset() +
4423                   PtrQueue::byte_offset_of_active()),
4424          tmp);
4425   }
4426 
4427   // Check on whether to annul.
4428   br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered);
4429   delayed() -> nop();
4430 
4431   // Do we need to load the previous value?
4432   if (obj != noreg) {
4433     // Load the previous value...
4434     if (index == noreg) {
4435       if (Assembler::is_simm13(offset)) {
4436         load_heap_oop(obj, offset, tmp);
4437       } else {
4438         set(offset, tmp);
4439         load_heap_oop(obj, tmp, tmp);
4440       }
4441     } else {
4442       load_heap_oop(obj, index, tmp);
4443     }
4444     // Previous value has been loaded into tmp
4445     pre_val = tmp;
4446   }
4447 
4448   assert(pre_val != noreg, "must have a real register");
4449 
4450   // Is the previous value null?
4451   // Check on whether to annul.
4452   br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, pre_val, filtered);
4453   delayed() -> nop();
4454 
4455   // OK, it's not filtered, so we'll need to call enqueue.  In the normal
4456   // case, pre_val will be a scratch G-reg, but there are some cases in
4457   // which it's an O-reg.  In the first case, do a normal call.  In the
4458   // latter, do a save here and call the frameless version.
4459 
4460   guarantee(pre_val->is_global() || pre_val->is_out(),
4461             "Or we need to think harder.");
4462 
4463   if (pre_val->is_global() && !preserve_o_regs) {
4464     generate_satb_log_enqueue_if_necessary(true); // with frame
4465 
4466     call(satb_log_enqueue_with_frame);
4467     delayed()->mov(pre_val, O0);
4468   } else {
4469     generate_satb_log_enqueue_if_necessary(false); // frameless
4470 
4471     save_frame(0);
4472     call(satb_log_enqueue_frameless);
4473     delayed()->mov(pre_val->after_save(), O0);


4501     tty->print_cr("%d potential CT writes: %5.2f%% filtered\n"
4502                   "   (%5.2f%% intra-HR, %5.2f%% null).",
4503                   num_ct_writes,
4504                   100.0*(float)num_ct_writes_filtered/(float)num_ct_writes,
4505                   100.0*(float)num_ct_writes_filtered_in_hr/
4506                   (float)num_ct_writes,
4507                   100.0*(float)num_ct_writes_filtered_null/
4508                   (float)num_ct_writes);
4509   }
4510   return Thread::current();
4511 }
4512 
4513 static address dirty_card_log_enqueue = 0;
4514 static u_char* dirty_card_log_enqueue_end = 0;
4515 
4516 // This gets to assume that o0 contains the object address.
4517 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) {
4518   BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2);
4519   CodeBuffer buf(bb);
4520   MacroAssembler masm(&buf);
4521   address start = masm.pc();

4522 
4523   Label not_already_dirty, restart, refill;
4524 
4525 #ifdef _LP64
4526   masm.srlx(O0, CardTableModRefBS::card_shift, O0);
4527 #else
4528   masm.srl(O0, CardTableModRefBS::card_shift, O0);
4529 #endif
4530   AddressLiteral addrlit(byte_map_base);
4531   masm.set(addrlit, O1); // O1 := <card table base>
4532   masm.ldub(O0, O1, O2); // O2 := [O0 + O1]
4533 
4534   masm.br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt,
4535                       O2, not_already_dirty);
4536   // Get O1 + O2 into a reg by itself -- useful in the take-the-branch
4537   // case, harmless if not.
4538   masm.delayed()->add(O0, O1, O3);
4539 
4540   // We didn't take the branch, so we're already dirty: return.
4541   // Use return-from-leaf
4542   masm.retl();
4543   masm.delayed()->nop();
4544 
4545   // Not dirty.
4546   masm.bind(not_already_dirty);
4547   // First, dirty it.
4548   masm.stb(G0, O3, G0);  // [cardPtr] := 0  (i.e., dirty).
4549   int dirty_card_q_index_byte_offset =
4550     in_bytes(JavaThread::dirty_card_queue_offset() +
4551              PtrQueue::byte_offset_of_index());
4552   int dirty_card_q_buf_byte_offset =
4553     in_bytes(JavaThread::dirty_card_queue_offset() +
4554              PtrQueue::byte_offset_of_buf());
4555   masm.bind(restart);
4556   masm.ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0);
4557 
4558   masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn,
4559                       L0, refill);
4560   // If the branch is taken, no harm in executing this in the delay slot.
4561   masm.delayed()->ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1);
4562   masm.sub(L0, oopSize, L0);
4563 
4564   masm.st_ptr(O3, L1, L0);  // [_buf + index] := I0
4565   // Use return-from-leaf
4566   masm.retl();
4567   masm.delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset);
4568 
4569   masm.bind(refill);
4570   address handle_zero =
4571     CAST_FROM_FN_PTR(address,
4572                      &DirtyCardQueueSet::handle_zero_index_for_thread);
4573   // This should be rare enough that we can afford to save all the
4574   // scratch registers that the calling context might be using.
4575   masm.mov(G1_scratch, L3);
4576   masm.mov(G3_scratch, L5);
4577   // We need the value of O3 above (for the write into the buffer), so we
4578   // save and restore it.
4579   masm.mov(O3, L6);
4580   // Since the call will overwrite O7, we save and restore that, as well.
4581   masm.mov(O7, L4);
4582 
4583   masm.call_VM_leaf(L7_thread_cache, handle_zero, G2_thread);
4584   masm.mov(L3, G1_scratch);
4585   masm.mov(L5, G3_scratch);
4586   masm.mov(L6, O3);
4587   masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4588   masm.delayed()->mov(L4, O7);
4589 
4590   dirty_card_log_enqueue = start;
4591   dirty_card_log_enqueue_end = masm.pc();
4592   // XXX Should have a guarantee here about not going off the end!
4593   // Does it already do so?  Do an experiment...



4594 }
4595 
4596 static inline void
4597 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) {
4598   if (dirty_card_log_enqueue == 0) {
4599     generate_dirty_card_log_enqueue(byte_map_base);
4600     assert(dirty_card_log_enqueue != 0, "postcondition.");
4601     if (G1SATBPrintStubs) {
4602       tty->print_cr("Generated dirty_card enqueue:");
4603       Disassembler::decode((u_char*)dirty_card_log_enqueue,
4604                            dirty_card_log_enqueue_end,
4605                            tty);
4606     }
4607   }
4608 }
4609 
4610 
4611 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
4612 
4613   Label filtered;


4886 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
4887                                         Register limit, Register result,
4888                                         Register chr1, Register chr2, Label& Ldone) {
4889   Label Lvector, Lloop;
4890   assert(chr1 == result, "should be the same");
4891 
4892   // Note: limit contains number of bytes (2*char_elements) != 0.
4893   andcc(limit, 0x2, chr1); // trailing character ?
4894   br(Assembler::zero, false, Assembler::pt, Lvector);
4895   delayed()->nop();
4896 
4897   // compare the trailing char
4898   sub(limit, sizeof(jchar), limit);
4899   lduh(ary1, limit, chr1);
4900   lduh(ary2, limit, chr2);
4901   cmp(chr1, chr2);
4902   br(Assembler::notEqual, true, Assembler::pt, Ldone);
4903   delayed()->mov(G0, result);     // not equal
4904 
4905   // only one char ?
4906   br_on_reg_cond(rc_z, true, Assembler::pn, limit, Ldone);
4907   delayed()->add(G0, 1, result); // zero-length arrays are equal
4908 
4909   // word by word compare, dont't need alignment check
4910   bind(Lvector);
4911   // Shift ary1 and ary2 to the end of the arrays, negate limit
4912   add(ary1, limit, ary1);
4913   add(ary2, limit, ary2);
4914   neg(limit, limit);
4915 
4916   lduw(ary1, limit, chr1);
4917   bind(Lloop);
4918   lduw(ary2, limit, chr2);
4919   cmp(chr1, chr2);
4920   br(Assembler::notEqual, true, Assembler::pt, Ldone);
4921   delayed()->mov(G0, result);     // not equal
4922   inccc(limit, 2*sizeof(jchar));
4923   // annul LDUW if branch is not taken to prevent access past end of array
4924   br(Assembler::notZero, true, Assembler::pt, Lloop);
4925   delayed()->lduw(ary1, limit, chr1); // hoisted
4926 


  83 static const char* argumentNames[][2] = {
  84   {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},
  85   {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},
  86   {"A(n>9)","P(n>9)"}
  87 };
  88 
  89 const char* Argument::name() const {
  90   int nofArgs = sizeof argumentNames / sizeof argumentNames[0];
  91   int num = number();
  92   if (num >= nofArgs)  num = nofArgs - 1;
  93   return argumentNames[num][is_in() ? 1 : 0];
  94 }
  95 
  96 void Assembler::print_instruction(int inst) {
  97   const char* s;
  98   switch (inv_op(inst)) {
  99   default:         s = "????"; break;
 100   case call_op:    s = "call"; break;
 101   case branch_op:
 102     switch (inv_op2(inst)) {

 103       case fb_op2:     s = "fb";   break;
 104       case fbp_op2:    s = "fbp";  break;
 105       case br_op2:     s = "br";   break;
 106       case bp_op2:     s = "bp";   break;
 107       case cb_op2:     s = "cb";   break;
 108       case bpr_op2: {
 109         if (is_cbcond(inst)) {
 110           s = is_cxb(inst) ? "cxb" : "cwb";
 111         } else {
 112           s = "bpr";
 113         }
 114         break;
 115       }
 116       default:         s = "????"; break;
 117     }
 118   }
 119   ::tty->print("%s", s);
 120 }
 121 
 122 
 123 // Patch instruction inst at offset inst_pos to refer to dest_pos
 124 // and return the resulting instruction.
 125 // We should have pcs, not offsets, but since all is relative, it will work out
 126 // OK.
 127 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) {
 128 
 129   int m; // mask for displacement field
 130   int v; // new value for displacement field
 131   const int word_aligned_ones = -4;
 132   switch (inv_op(inst)) {
 133   default: ShouldNotReachHere();
 134   case call_op:    m = wdisp(word_aligned_ones, 0, 30);  v = wdisp(dest_pos, inst_pos, 30); break;
 135   case branch_op:
 136     switch (inv_op2(inst)) {

 137       case fbp_op2:    m = wdisp(  word_aligned_ones, 0, 19);  v = wdisp(  dest_pos, inst_pos, 19); break;
 138       case bp_op2:     m = wdisp(  word_aligned_ones, 0, 19);  v = wdisp(  dest_pos, inst_pos, 19); break;
 139       case fb_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;
 140       case br_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;
 141       case cb_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;
 142       case bpr_op2: {
 143         if (is_cbcond(inst)) {
 144           m = wdisp10(word_aligned_ones, 0);
 145           v = wdisp10(dest_pos, inst_pos);
 146         } else {
 147           m = wdisp16(word_aligned_ones, 0);
 148           v = wdisp16(dest_pos, inst_pos);
 149         }
 150         break;
 151       }
 152       default: ShouldNotReachHere();
 153     }
 154   }
 155   return  inst & ~m  |  v;
 156 }
 157 
 158 // Return the offset of the branch destionation of instruction inst
 159 // at offset pos.
 160 // Should have pcs, but since all is relative, it works out.
 161 int Assembler::branch_destination(int inst, int pos) {
 162   int r;
 163   switch (inv_op(inst)) {
 164   default: ShouldNotReachHere();
 165   case call_op:        r = inv_wdisp(inst, pos, 30);  break;
 166   case branch_op:
 167     switch (inv_op2(inst)) {

 168       case fbp_op2:    r = inv_wdisp(  inst, pos, 19);  break;
 169       case bp_op2:     r = inv_wdisp(  inst, pos, 19);  break;
 170       case fb_op2:     r = inv_wdisp(  inst, pos, 22);  break;
 171       case br_op2:     r = inv_wdisp(  inst, pos, 22);  break;
 172       case cb_op2:     r = inv_wdisp(  inst, pos, 22);  break;
 173       case bpr_op2: {
 174         if (is_cbcond(inst)) {
 175           r = inv_wdisp10(inst, pos);
 176         } else {
 177           r = inv_wdisp16(inst, pos);
 178         }
 179         break;
 180       }
 181       default: ShouldNotReachHere();
 182     }
 183   }
 184   return r;
 185 }
 186 
 187 int AbstractAssembler::code_fill_byte() {
 188   return 0x00;                  // illegal instruction 0x00000000
 189 }
 190 
 191 Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) {
 192   switch (in) {
 193   case rc_z:   return equal;
 194   case rc_lez: return lessEqual;
 195   case rc_lz:  return less;
 196   case rc_nz:  return notEqual;
 197   case rc_gz:  return greater;
 198   case rc_gez: return greaterEqual;
 199   default:
 200     ShouldNotReachHere();


 974   }
 975 }
 976 
 977 
 978 // %%% maybe get rid of [re]set_last_Java_frame
 979 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) {
 980   assert_not_delayed();
 981   Address flags(G2_thread, JavaThread::frame_anchor_offset() +
 982                            JavaFrameAnchor::flags_offset());
 983   Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset());
 984 
 985   // Always set last_Java_pc and flags first because once last_Java_sp is visible
 986   // has_last_Java_frame is true and users will look at the rest of the fields.
 987   // (Note: flags should always be zero before we get here so doesn't need to be set.)
 988 
 989 #ifdef ASSERT
 990   // Verify that flags was zeroed on return to Java
 991   Label PcOk;
 992   save_frame(0);                // to avoid clobbering O0
 993   ld_ptr(pc_addr, L0);
 994   br_null_short(L0, Assembler::pt, PcOk);






 995   stop("last_Java_pc not zeroed before leaving Java");
 996   bind(PcOk);
 997 
 998   // Verify that flags was zeroed on return to Java
 999   Label FlagsOk;
1000   ld(flags, L0);
1001   tst(L0);
1002   br(Assembler::zero, false, Assembler::pt, FlagsOk);
1003   delayed() -> restore();
1004   stop("flags not zeroed before leaving Java");
1005   bind(FlagsOk);
1006 #endif /* ASSERT */
1007   //
1008   // When returning from calling out from Java mode the frame anchor's last_Java_pc
1009   // will always be set to NULL. It is set here so that if we are doing a call to
1010   // native (not VM) that we capture the known pc and don't have to rely on the
1011   // native call having a standard frame linkage where we can find the pc.
1012 
1013   if (last_Java_pc->is_valid()) {
1014     st_ptr(last_Java_pc, pc_addr);
1015   }
1016 
1017 #ifdef _LP64
1018 #ifdef ASSERT
1019   // Make sure that we have an odd stack
1020   Label StackOk;
1021   andcc(last_java_sp, 0x01, G0);
1022   br(Assembler::notZero, false, Assembler::pt, StackOk);
1023   delayed()->nop();
1024   stop("Stack Not Biased in set_last_Java_frame");
1025   bind(StackOk);
1026 #endif // ASSERT
1027   assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame");
1028   add( last_java_sp, STACK_BIAS, G4_scratch );
1029   st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset());
1030 #else
1031   st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset());
1032 #endif // _LP64
1033 }
1034 
1035 void MacroAssembler::reset_last_Java_frame(void) {
1036   assert_not_delayed();
1037 
1038   Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset());
1039   Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
1040   Address flags  (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
1041 
1042 #ifdef ASSERT
1043   // check that it WAS previously set


1099   set(badHeapWordVal, G3);
1100   set(badHeapWordVal, G4);
1101   set(badHeapWordVal, G5);
1102 #endif
1103 
1104   // get oop result if there is one and reset the value in the thread
1105   if (oop_result->is_valid()) {
1106     get_vm_result(oop_result);
1107   }
1108 }
1109 
1110 void MacroAssembler::check_and_forward_exception(Register scratch_reg)
1111 {
1112   Label L;
1113 
1114   check_and_handle_popframe(scratch_reg);
1115   check_and_handle_earlyret(scratch_reg);
1116 
1117   Address exception_addr(G2_thread, Thread::pending_exception_offset());
1118   ld_ptr(exception_addr, scratch_reg);
1119   br_null_short(scratch_reg, pt, L);

1120   // we use O7 linkage so that forward_exception_entry has the issuing PC
1121   call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
1122   delayed()->nop();
1123   bind(L);
1124 }
1125 
1126 
1127 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) {
1128 }
1129 
1130 
1131 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) {
1132 }
1133 
1134 
1135 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1136   call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
1137 }
1138 
1139 


1873     Register O2_adr   = O2;
1874     Register O3_accum = O3;
1875     inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum);
1876   }
1877 
1878   Register O2_mask = O2;
1879   Register O3_bits = O3;
1880   Register O4_temp = O4;
1881 
1882   // mark lower end of faulting range
1883   assert(_verify_oop_implicit_branch[0] == NULL, "set once");
1884   _verify_oop_implicit_branch[0] = pc();
1885 
1886   // We can't check the mark oop because it could be in the process of
1887   // locking or unlocking while this is running.
1888   set(Universe::verify_oop_mask (), O2_mask);
1889   set(Universe::verify_oop_bits (), O3_bits);
1890 
1891   // assert((obj & oop_mask) == oop_bits);
1892   and3(O0_obj, O2_mask, O4_temp);
1893   cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, null_or_fail);


1894 
1895   if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) {
1896     // the null_or_fail case is useless; must test for null separately
1897     br_null_short(O0_obj, pn, succeed);

1898   }
1899 
1900   // Check the klassOop of this object for being in the right area of memory.
1901   // Cannot do the load in the delay above slot in case O0 is null
1902   load_klass(O0_obj, O0_obj);
1903   // assert((klass & klass_mask) == klass_bits);
1904   if( Universe::verify_klass_mask() != Universe::verify_oop_mask() )
1905     set(Universe::verify_klass_mask(), O2_mask);
1906   if( Universe::verify_klass_bits() != Universe::verify_oop_bits() )
1907     set(Universe::verify_klass_bits(), O3_bits);
1908   and3(O0_obj, O2_mask, O4_temp);
1909   cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, fail);


1910   // Check the klass's klass
1911   load_klass(O0_obj, O0_obj);
1912   and3(O0_obj, O2_mask, O4_temp);
1913   cmp(O4_temp, O3_bits);
1914   brx(notEqual, false, pn, fail);
1915   delayed()->wrccr( O5_save_flags ); // Restore CCR's
1916 
1917   // mark upper end of faulting range
1918   _verify_oop_implicit_branch[1] = pc();
1919 
1920   //-----------------------
1921   // all tests pass
1922   bind(succeed);
1923 
1924   // Restore prior 64-bit registers
1925   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0);
1926   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1);
1927   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2);
1928   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3);
1929   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4);


2116   save(SP, Rresult, SP);
2117 }
2118 
2119 
2120 // ---------------------------------------------------------
2121 Assembler::RCondition cond2rcond(Assembler::Condition c) {
2122   switch (c) {
2123     /*case zero: */
2124     case Assembler::equal:        return Assembler::rc_z;
2125     case Assembler::lessEqual:    return Assembler::rc_lez;
2126     case Assembler::less:         return Assembler::rc_lz;
2127     /*case notZero:*/
2128     case Assembler::notEqual:     return Assembler::rc_nz;
2129     case Assembler::greater:      return Assembler::rc_gz;
2130     case Assembler::greaterEqual: return Assembler::rc_gez;
2131   }
2132   ShouldNotReachHere();
2133   return Assembler::rc_z;
2134 }
2135 
2136 // compares (32 bit) register with zero and branches.  NOT FOR USE WITH 64-bit POINTERS
2137 void MacroAssembler::cmp_zero_and_br(Condition c, Register s1, Label& L, bool a, Predict p) {
2138   tst(s1);
2139   br (c, a, p, L);
2140 }
2141 

2142 // Compares a pointer register with zero and branches on null.
2143 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
2144 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) {
2145   assert_not_delayed();
2146 #ifdef _LP64
2147   bpr( rc_z, a, p, s1, L );
2148 #else
2149   tst(s1);
2150   br ( zero, a, p, L );
2151 #endif
2152 }
2153 
2154 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) {
2155   assert_not_delayed();
2156 #ifdef _LP64
2157   bpr( rc_nz, a, p, s1, L );
2158 #else
2159   tst(s1);
2160   br ( notZero, a, p, L );
2161 #endif
2162 }
2163 
2164 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,
2165                                      Register s1, address d,
2166                                      relocInfo::relocType rt ) {
2167   assert_not_delayed();
2168   if (VM_Version::v9_instructions_work()) {
2169     bpr(rc, a, p, s1, d, rt);
2170   } else {
2171     tst(s1);
2172     br(reg_cond_to_cc_cond(rc), a, p, d, rt);
2173   }
2174 }
2175 
2176 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,
2177                                      Register s1, Label& L ) {
2178   assert_not_delayed();
2179   if (VM_Version::v9_instructions_work()) {
2180     bpr(rc, a, p, s1, L);
2181   } else {
2182     tst(s1);
2183     br(reg_cond_to_cc_cond(rc), a, p, L);
2184   }
2185 }
2186 
2187 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
2188 
2189 // Compare integer (32 bit) values (icc only).
2190 void MacroAssembler::cmp_and_br_short(Register s1, Register s2, Condition c,
2191                                       Predict p, Label& L) {
2192   assert_not_delayed();
2193   if (use_cbcond(L)) {
2194     Assembler::cbcond(c, icc, s1, s2, L);
2195   } else {
2196     cmp(s1, s2);
2197     br(c, false, p, L);
2198     delayed()->nop();
2199   }
2200 }
2201 
2202 // Compare integer (32 bit) values (icc only).
2203 void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c,
2204                                       Predict p, Label& L) {
2205   assert_not_delayed();
2206   if (is_simm(simm13a,5) && use_cbcond(L)) {
2207     Assembler::cbcond(c, icc, s1, simm13a, L);
2208   } else {
2209     cmp(s1, simm13a);
2210     br(c, false, p, L);
2211     delayed()->nop();
2212   }
2213 }
2214 
2215 // Branch that tests xcc in LP64 and icc in !LP64
2216 void MacroAssembler::cmp_and_brx_short(Register s1, Register s2, Condition c,
2217                                        Predict p, Label& L) {
2218   assert_not_delayed();
2219   if (use_cbcond(L)) {
2220     Assembler::cbcond(c, ptr_cc, s1, s2, L);
2221   } else {
2222     cmp(s1, s2);
2223     brx(c, false, p, L);
2224     delayed()->nop();
2225   }
2226 }
2227 
2228 // Branch that tests xcc in LP64 and icc in !LP64
2229 void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c,
2230                                        Predict p, Label& L) {
2231   assert_not_delayed();
2232   if (is_simm(simm13a,5) && use_cbcond(L)) {
2233     Assembler::cbcond(c, ptr_cc, s1, simm13a, L);
2234   } else {
2235     cmp(s1, simm13a);
2236     brx(c, false, p, L);
2237     delayed()->nop();
2238   }
2239 }
2240 
2241 // Short branch version for compares a pointer with zero.
2242 
2243 void MacroAssembler::br_null_short(Register s1, Predict p, Label& L) {
2244   assert_not_delayed();
2245   if (use_cbcond(L)) {
2246     Assembler::cbcond(zero, ptr_cc, s1, 0, L);
2247     return;
2248   }
2249   br_null(s1, false, p, L);
2250   delayed()->nop();
2251 }
2252 
2253 void MacroAssembler::br_notnull_short(Register s1, Predict p, Label& L) {
2254   assert_not_delayed();
2255   if (use_cbcond(L)) {
2256     Assembler::cbcond(notZero, ptr_cc, s1, 0, L);
2257     return;
2258   }
2259   br_notnull(s1, false, p, L);
2260   delayed()->nop();
2261 }
2262 
2263 // Unconditional short branch
2264 void MacroAssembler::ba_short(Label& L) {
2265   if (use_cbcond(L)) {
2266     Assembler::cbcond(equal, icc, G0, G0, L);
2267     return;
2268   }
2269   br(always, false, pt, L);
2270   delayed()->nop();
2271 }
2272 
2273 // instruction sequences factored across compiler & interpreter
2274 
2275 
2276 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low,
2277                            Register Rb_hi, Register Rb_low,
2278                            Register Rresult) {
2279 
2280   Label check_low_parts, done;
2281 
2282   cmp(Ra_hi, Rb_hi );  // compare hi parts
2283   br(equal, true, pt, check_low_parts);
2284   delayed()->cmp(Ra_low, Rb_low); // test low parts
2285 
2286   // And, with an unsigned comparison, it does not matter if the numbers
2287   // are negative or not.
2288   // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff.
2289   // The second one is bigger (unsignedly).
2290 
2291   // Other notes:  The first move in each triplet can be unconditional
2292   // (and therefore probably prefetchable).
2293   // And the equals case for the high part does not need testing,
2294   // since that triplet is reached only after finding the high halves differ.
2295 
2296   if (VM_Version::v9_instructions_work()) {
2297     mov(-1, Rresult);
2298     ba(done);  delayed()-> movcc(greater, false, icc,  1, Rresult);
2299   } else {


2300     br(less,    true, pt, done); delayed()-> set(-1, Rresult);
2301     br(greater, true, pt, done); delayed()-> set( 1, Rresult);
2302   }
2303 
2304   bind( check_low_parts );
2305 
2306   if (VM_Version::v9_instructions_work()) {
2307     mov(                               -1, Rresult);
2308     movcc(equal,           false, icc,  0, Rresult);
2309     movcc(greaterUnsigned, false, icc,  1, Rresult);
2310   } else {

2311     set(-1, Rresult);
2312     br(equal,           true, pt, done); delayed()->set( 0, Rresult);
2313     br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult);
2314   }
2315   bind( done );
2316 }
2317 
2318 void MacroAssembler::lneg( Register Rhi, Register Rlow ) {
2319   subcc(  G0, Rlow, Rlow );
2320   subc(   G0, Rhi,  Rhi  );
2321 }
2322 
2323 void MacroAssembler::lshl( Register Rin_high,  Register Rin_low,
2324                            Register Rcount,
2325                            Register Rout_high, Register Rout_low,
2326                            Register Rtemp ) {
2327 
2328 
2329   Register Ralt_count = Rtemp;
2330   Register Rxfer_bits = Rtemp;
2331 
2332   assert( Ralt_count != Rin_high
2333       &&  Ralt_count != Rin_low
2334       &&  Ralt_count != Rcount
2335       &&  Rxfer_bits != Rin_low
2336       &&  Rxfer_bits != Rin_high
2337       &&  Rxfer_bits != Rcount
2338       &&  Rxfer_bits != Rout_low
2339       &&  Rout_low   != Rin_high,
2340         "register alias checks");
2341 
2342   Label big_shift, done;
2343 
2344   // This code can be optimized to use the 64 bit shifts in V9.
2345   // Here we use the 32 bit shifts.
2346 
2347   and3( Rcount, 0x3f, Rcount);     // take least significant 6 bits
2348   subcc(Rcount,   31, Ralt_count);
2349   br(greater, true, pn, big_shift);
2350   delayed()->dec(Ralt_count);

2351 
2352   // shift < 32 bits, Ralt_count = Rcount-31
2353 
2354   // We get the transfer bits by shifting right by 32-count the low
2355   // register. This is done by shifting right by 31-count and then by one
2356   // more to take care of the special (rare) case where count is zero
2357   // (shifting by 32 would not work).
2358 
2359   neg(Ralt_count);
2360 
2361   // The order of the next two instructions is critical in the case where
2362   // Rin and Rout are the same and should not be reversed.
2363 
2364   srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count
2365   if (Rcount != Rout_low) {
2366     sll(Rin_low, Rcount, Rout_low); // low half
2367   }
2368   sll(Rin_high, Rcount, Rout_high);
2369   if (Rcount == Rout_low) {
2370     sll(Rin_low, Rcount, Rout_low); // low half
2371   }
2372   srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more
2373   ba(done);
2374   delayed()->or3(Rout_high, Rxfer_bits, Rout_high);   // new hi value: or in shifted old hi part and xfer from low

2375 
2376   // shift >= 32 bits, Ralt_count = Rcount-32
2377   bind(big_shift);
2378   sll(Rin_low, Ralt_count, Rout_high  );
2379   clr(Rout_low);
2380 
2381   bind(done);
2382 }
2383 
2384 
2385 void MacroAssembler::lshr( Register Rin_high,  Register Rin_low,
2386                            Register Rcount,
2387                            Register Rout_high, Register Rout_low,
2388                            Register Rtemp ) {
2389 
2390   Register Ralt_count = Rtemp;
2391   Register Rxfer_bits = Rtemp;
2392 
2393   assert( Ralt_count != Rin_high
2394       &&  Ralt_count != Rin_low
2395       &&  Ralt_count != Rcount
2396       &&  Rxfer_bits != Rin_low
2397       &&  Rxfer_bits != Rin_high
2398       &&  Rxfer_bits != Rcount
2399       &&  Rxfer_bits != Rout_high
2400       &&  Rout_high  != Rin_low,
2401         "register alias checks");
2402 
2403   Label big_shift, done;
2404 
2405   // This code can be optimized to use the 64 bit shifts in V9.
2406   // Here we use the 32 bit shifts.
2407 
2408   and3( Rcount, 0x3f, Rcount);     // take least significant 6 bits
2409   subcc(Rcount,   31, Ralt_count);
2410   br(greater, true, pn, big_shift);
2411   delayed()->dec(Ralt_count);
2412 
2413   // shift < 32 bits, Ralt_count = Rcount-31
2414 
2415   // We get the transfer bits by shifting left by 32-count the high
2416   // register. This is done by shifting left by 31-count and then by one
2417   // more to take care of the special (rare) case where count is zero
2418   // (shifting by 32 would not work).
2419 
2420   neg(Ralt_count);
2421   if (Rcount != Rout_low) {
2422     srl(Rin_low, Rcount, Rout_low);
2423   }
2424 
2425   // The order of the next two instructions is critical in the case where
2426   // Rin and Rout are the same and should not be reversed.
2427 
2428   sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
2429   sra(Rin_high,     Rcount, Rout_high ); // high half
2430   sll(Rxfer_bits,        1, Rxfer_bits); // shift left by one more
2431   if (Rcount == Rout_low) {
2432     srl(Rin_low, Rcount, Rout_low);
2433   }
2434   ba(done);
2435   delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high

2436 
2437   // shift >= 32 bits, Ralt_count = Rcount-32
2438   bind(big_shift);
2439 
2440   sra(Rin_high, Ralt_count, Rout_low);
2441   sra(Rin_high,         31, Rout_high); // sign into hi
2442 
2443   bind( done );
2444 }
2445 
2446 
2447 
2448 void MacroAssembler::lushr( Register Rin_high,  Register Rin_low,
2449                             Register Rcount,
2450                             Register Rout_high, Register Rout_low,
2451                             Register Rtemp ) {
2452 
2453   Register Ralt_count = Rtemp;
2454   Register Rxfer_bits = Rtemp;
2455 
2456   assert( Ralt_count != Rin_high
2457       &&  Ralt_count != Rin_low
2458       &&  Ralt_count != Rcount
2459       &&  Rxfer_bits != Rin_low
2460       &&  Rxfer_bits != Rin_high
2461       &&  Rxfer_bits != Rcount


2463       &&  Rout_high  != Rin_low,
2464         "register alias checks");
2465 
2466   Label big_shift, done;
2467 
2468   // This code can be optimized to use the 64 bit shifts in V9.
2469   // Here we use the 32 bit shifts.
2470 
2471   and3( Rcount, 0x3f, Rcount);     // take least significant 6 bits
2472   subcc(Rcount,   31, Ralt_count);
2473   br(greater, true, pn, big_shift);
2474   delayed()->dec(Ralt_count);
2475 
2476   // shift < 32 bits, Ralt_count = Rcount-31
2477 
2478   // We get the transfer bits by shifting left by 32-count the high
2479   // register. This is done by shifting left by 31-count and then by one
2480   // more to take care of the special (rare) case where count is zero
2481   // (shifting by 32 would not work).
2482 
2483   neg(Ralt_count);
2484   if (Rcount != Rout_low) {
2485     srl(Rin_low, Rcount, Rout_low);
2486   }
2487 
2488   // The order of the next two instructions is critical in the case where
2489   // Rin and Rout are the same and should not be reversed.
2490 
2491   sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
2492   srl(Rin_high,     Rcount, Rout_high ); // high half
2493   sll(Rxfer_bits,        1, Rxfer_bits); // shift left by one more
2494   if (Rcount == Rout_low) {
2495     srl(Rin_low, Rcount, Rout_low);
2496   }
2497   ba(done);
2498   delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high

2499 
2500   // shift >= 32 bits, Ralt_count = Rcount-32
2501   bind(big_shift);
2502 
2503   srl(Rin_high, Ralt_count, Rout_low);
2504   clr(Rout_high);
2505 
2506   bind( done );
2507 }
2508 
2509 #ifdef _LP64
2510 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) {
2511   cmp(Ra, Rb);
2512   mov(-1, Rresult);
2513   movcc(equal,   false, xcc,  0, Rresult);
2514   movcc(greater, false, xcc,  1, Rresult);
2515 }
2516 #endif
2517 
2518 
2519 void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) {
2520   switch (size_in_bytes) {
2521   case  8:  ld_long(src, dst); break;
2522   case  4:  ld(     src, dst); break;
2523   case  2:  is_signed ? ldsh(src, dst) : lduh(src, dst); break;
2524   case  1:  is_signed ? ldsb(src, dst) : ldub(src, dst); break;
2525   default:  ShouldNotReachHere();
2526   }
2527 }
2528 
2529 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) {
2530   switch (size_in_bytes) {
2531   case  8:  st_long(src, dst); break;
2532   case  4:  st(     src, dst); break;
2533   case  2:  sth(    src, dst); break;
2534   case  1:  stb(    src, dst); break;
2535   default:  ShouldNotReachHere();
2536   }
2537 }
2538 
2539 
2540 void MacroAssembler::float_cmp( bool is_float, int unordered_result,
2541                                 FloatRegister Fa, FloatRegister Fb,
2542                                 Register Rresult) {
2543 
2544   fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb);
2545 
2546   Condition lt = unordered_result == -1 ? f_unorderedOrLess    : f_less;
2547   Condition eq =                          f_equal;
2548   Condition gt = unordered_result ==  1 ? f_unorderedOrGreater : f_greater;
2549 
2550   if (VM_Version::v9_instructions_work()) {
2551 
2552     mov(-1, Rresult);
2553     movcc(eq, true, fcc0, 0, Rresult);
2554     movcc(gt, true, fcc0, 1, Rresult);
2555 
2556   } else {
2557     Label done;
2558 
2559     set( -1, Rresult );
2560     //fb(lt, true, pn, done); delayed()->set( -1, Rresult );
2561     fb( eq, true, pn, done);  delayed()->set(  0, Rresult );
2562     fb( gt, true, pn, done);  delayed()->set(  1, Rresult );
2563 
2564     bind (done);
2565   }
2566 }
2567 
2568 
2569 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2570 {
2571   if (VM_Version::v9_instructions_work()) {
2572     Assembler::fneg(w, s, d);
2573   } else {
2574     if (w == FloatRegisterImpl::S) {


2741     if (top_reg_after_save == L1) {
2742       ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save);
2743     }
2744 
2745     if (ptr_reg_after_save == L2) {
2746       ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save);
2747     }
2748 
2749     Label(retry_get_lock);
2750     Label(not_same);
2751     Label(dont_yield);
2752 
2753     assert(lock_addr, "lock_address should be non null for v8");
2754     set((intptr_t)lock_addr, lock_ptr_reg);
2755     // Initialize yield counter
2756     mov(G0,yield_reg);
2757     mov(G0, yieldall_reg);
2758     set(StubRoutines::Sparc::locked, lock_reg);
2759 
2760     bind(retry_get_lock);
2761     cmp_and_br_short(yield_reg, V8AtomicOperationUnderLockSpinCount, Assembler::less, Assembler::pt, dont_yield);


2762 
2763     if(use_call_vm) {
2764       Untested("Need to verify global reg consistancy");
2765       call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg);
2766     } else {
2767       // Save the regs and make space for a C call
2768       save(SP, -96, SP);
2769       save_all_globals_into_locals();
2770       call(CAST_FROM_FN_PTR(address,os::yield_all));
2771       delayed()->mov(yieldall_reg, O0);
2772       restore_globals_from_locals();
2773       restore();
2774     }
2775 
2776     // reset the counter
2777     mov(G0,yield_reg);
2778     add(yieldall_reg, 1, yieldall_reg);
2779 
2780     bind(dont_yield);
2781     // try to get lock
2782     swap(lock_ptr_reg, 0, lock_reg);
2783 
2784     // did we get the lock?
2785     cmp(lock_reg, StubRoutines::Sparc::unlocked);
2786     br(Assembler::notEqual, true, Assembler::pn, retry_get_lock);
2787     delayed()->add(yield_reg,1,yield_reg);
2788 
2789     // yes, got lock.  do we have the same top?
2790     ld(top_ptr_reg_after_save, 0, value_reg);
2791     cmp_and_br_short(value_reg, top_reg_after_save, Assembler::notEqual, Assembler::pn, not_same);


2792 
2793     // yes, same top.
2794     st(ptr_reg_after_save, top_ptr_reg_after_save, 0);
2795     membar(Assembler::StoreStore);
2796 
2797     bind(not_same);
2798     mov(value_reg, ptr_reg_after_save);
2799     st(lock_reg, lock_ptr_reg, 0); // unlock
2800 
2801     restore();
2802   }
2803 }
2804 
2805 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
2806                                                       Register tmp,
2807                                                       int offset) {
2808   intptr_t value = *delayed_value_addr;
2809   if (value != 0)
2810     return RegisterOrConstant(value + offset);
2811 


3021                                          Register super_klass,
3022                                          Register temp_reg,
3023                                          Register temp2_reg,
3024                                          Label& L_success) {
3025   Label L_failure, L_pop_to_failure;
3026   check_klass_subtype_fast_path(sub_klass, super_klass,
3027                                 temp_reg, temp2_reg,
3028                                 &L_success, &L_failure, NULL);
3029   Register sub_2 = sub_klass;
3030   Register sup_2 = super_klass;
3031   if (!sub_2->is_global())  sub_2 = L0;
3032   if (!sup_2->is_global())  sup_2 = L1;
3033 
3034   save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
3035   check_klass_subtype_slow_path(sub_2, sup_2,
3036                                 L2, L3, L4, L5,
3037                                 NULL, &L_pop_to_failure);
3038 
3039   // on success:
3040   restore();
3041   ba_short(L_success);

3042 
3043   // on failure:
3044   bind(L_pop_to_failure);
3045   restore();
3046   bind(L_failure);
3047 }
3048 
3049 
3050 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3051                                                    Register super_klass,
3052                                                    Register temp_reg,
3053                                                    Register temp2_reg,
3054                                                    Label* L_success,
3055                                                    Label* L_failure,
3056                                                    Label* L_slow_path,
3057                                         RegisterOrConstant super_check_offset) {

3058   int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
3059                    Klass::secondary_super_cache_offset_in_bytes());
3060   int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
3061                     Klass::super_check_offset_offset_in_bytes());
3062 
3063   bool must_load_sco  = (super_check_offset.constant_or_zero() == -1);
3064   bool need_slow_path = (must_load_sco ||
3065                          super_check_offset.constant_or_zero() == sco_offset);
3066 
3067   assert_different_registers(sub_klass, super_klass, temp_reg);
3068   if (super_check_offset.is_register()) {
3069     assert_different_registers(sub_klass, super_klass, temp_reg,
3070                                super_check_offset.as_register());
3071   } else if (must_load_sco) {
3072     assert(temp2_reg != noreg, "supply either a temp or a register offset");
3073   }
3074 
3075   Label L_fallthrough;
3076   int label_nulls = 0;
3077   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
3078   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
3079   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3080   assert(label_nulls <= 1 ||
3081          (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
3082          "at most one NULL in the batch, usually");
3083 



















3084   // If the pointers are equal, we are done (e.g., String[] elements).
3085   // This self-check enables sharing of secondary supertype arrays among
3086   // non-primary types such as array-of-interface.  Otherwise, each such
3087   // type would need its own customized SSA.
3088   // We move this check to the front of the fast path because many
3089   // type checks are in fact trivially successful in this manner,
3090   // so we get a nicely predicted branch right at the start of the check.
3091   cmp(super_klass, sub_klass);
3092   brx(Assembler::equal, false, Assembler::pn, *L_success);
3093   delayed()->nop();
3094 
3095   // Check the supertype display:
3096   if (must_load_sco) {
3097     // The super check offset is always positive...
3098     lduw(super_klass, sco_offset, temp2_reg);
3099     super_check_offset = RegisterOrConstant(temp2_reg);
3100     // super_check_offset is register.
3101     assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register());
3102   }
3103   ld_ptr(sub_klass, super_check_offset, temp_reg);
3104   cmp(super_klass, temp_reg);
3105 
3106   // This check has worked decisively for primary supers.
3107   // Secondary supers are sought in the super_cache ('super_cache_addr').
3108   // (Secondary supers are interfaces and very deeply nested subtypes.)
3109   // This works in the same check above because of a tricky aliasing
3110   // between the super_cache and the primary super display elements.
3111   // (The 'super_check_addr' can address either, as the case requires.)
3112   // Note that the cache is updated below if it does not help us find
3113   // what we need immediately.
3114   // So if it was a primary super, we can just fail immediately.
3115   // Otherwise, it's the slow path for us (no success at this point).
3116 
3117   // Hacked ba(), which may only be used just before L_fallthrough.
3118 #define FINAL_JUMP(label)            \
3119   if (&(label) != &L_fallthrough) {  \
3120     ba(label);  delayed()->nop();    \
3121   }
3122 
3123   if (super_check_offset.is_register()) {
3124     brx(Assembler::equal, false, Assembler::pn, *L_success);
3125     delayed()->cmp(super_check_offset.as_register(), sc_offset);


3126 
3127     if (L_failure == &L_fallthrough) {
3128       brx(Assembler::equal, false, Assembler::pt, *L_slow_path);
3129       delayed()->nop();

3130     } else {
3131       brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
3132       delayed()->nop();
3133       FINAL_JUMP(*L_slow_path);
3134     }
3135   } else if (super_check_offset.as_constant() == sc_offset) {
3136     // Need a slow path; fast failure is impossible.
3137     if (L_slow_path == &L_fallthrough) {
3138       brx(Assembler::equal, false, Assembler::pt, *L_success);
3139       delayed()->nop();
3140     } else {
3141       brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path);
3142       delayed()->nop();
3143       FINAL_JUMP(*L_success);
3144     }
3145   } else {
3146     // No slow path; it's a fast decision.
3147     if (L_failure == &L_fallthrough) {
3148       brx(Assembler::equal, false, Assembler::pt, *L_success);
3149       delayed()->nop();

3150     } else {
3151       brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
3152       delayed()->nop();
3153       FINAL_JUMP(*L_success);
3154     }
3155   }
3156 
3157   bind(L_fallthrough);
3158 
3159 #undef FINAL_JUMP



3160 }
3161 
3162 
3163 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
3164                                                    Register super_klass,
3165                                                    Register count_temp,
3166                                                    Register scan_temp,
3167                                                    Register scratch_reg,
3168                                                    Register coop_reg,
3169                                                    Label* L_success,
3170                                                    Label* L_failure) {
3171   assert_different_registers(sub_klass, super_klass,
3172                              count_temp, scan_temp, scratch_reg, coop_reg);
3173 
3174   Label L_fallthrough, L_loop;
3175   int label_nulls = 0;
3176   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
3177   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
3178   assert(label_nulls <= 1, "at most one NULL in the batch");
3179 


3232     // Don't use load_heap_oop; we don't want to decode the element.
3233     lduw(   scan_temp, elem_offset, scratch_reg );
3234   } else {
3235     ld_ptr( scan_temp, elem_offset, scratch_reg );
3236   }
3237 
3238   // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
3239   cmp(scratch_reg, search_key);
3240 
3241   // A miss means we are NOT a subtype and need to keep looping
3242   brx(Assembler::notEqual, false, Assembler::pn, L_loop);
3243   delayed()->deccc(count_temp); // decrement trip counter in delay slot
3244 
3245   // Falling out the bottom means we found a hit; we ARE a subtype
3246   if (decode_super_klass) decode_heap_oop(super_klass);
3247 
3248   // Success.  Cache the super we found and proceed in triumph.
3249   st_ptr(super_klass, sub_klass, sc_offset);
3250 
3251   if (L_success != &L_fallthrough) {
3252     ba(*L_success);
3253     delayed()->nop();
3254   }
3255 
3256   bind(L_fallthrough);
3257 }
3258 
3259 
3260 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
3261                                               Register temp_reg,
3262                                               Label& wrong_method_type) {
3263   assert_different_registers(mtype_reg, mh_reg, temp_reg);
3264   // compare method type against that of the receiver
3265   RegisterOrConstant mhtype_offset = delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg);
3266   load_heap_oop(mh_reg, mhtype_offset, temp_reg);
3267   cmp_and_brx_short(temp_reg, mtype_reg, Assembler::notEqual, Assembler::pn, wrong_method_type);


3268 }
3269 
3270 
3271 // A method handle has a "vmslots" field which gives the size of its
3272 // argument list in JVM stack slots.  This field is either located directly
3273 // in every method handle, or else is indirectly accessed through the
3274 // method handle's MethodType.  This macro hides the distinction.
3275 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
3276                                                 Register temp_reg) {
3277   assert_different_registers(vmslots_reg, mh_reg, temp_reg);
3278   // load mh.type.form.vmslots
3279   if (java_lang_invoke_MethodHandle::vmslots_offset_in_bytes() != 0) {
3280     // hoist vmslots into every mh to avoid dependent load chain
3281     ld(           Address(mh_reg,    delayed_value(java_lang_invoke_MethodHandle::vmslots_offset_in_bytes, temp_reg)),   vmslots_reg);
3282   } else {
3283     Register temp2_reg = vmslots_reg;
3284     load_heap_oop(Address(mh_reg,    delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg)),      temp2_reg);
3285     load_heap_oop(Address(temp2_reg, delayed_value(java_lang_invoke_MethodType::form_offset_in_bytes, temp_reg)),        temp2_reg);
3286     ld(           Address(temp2_reg, delayed_value(java_lang_invoke_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)), vmslots_reg);
3287   }


3340                                           Register temp_reg,
3341                                           Label& done, Label* slow_case,
3342                                           BiasedLockingCounters* counters) {
3343   assert(UseBiasedLocking, "why call this otherwise?");
3344 
3345   if (PrintBiasedLockingStatistics) {
3346     assert_different_registers(obj_reg, mark_reg, temp_reg, O7);
3347     if (counters == NULL)
3348       counters = BiasedLocking::counters();
3349   }
3350 
3351   Label cas_label;
3352 
3353   // Biased locking
3354   // See whether the lock is currently biased toward our thread and
3355   // whether the epoch is still valid
3356   // Note that the runtime guarantees sufficient alignment of JavaThread
3357   // pointers to allow age to be placed into low bits
3358   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
3359   and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3360   cmp_and_brx_short(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, Assembler::pn, cas_label);


3361 
3362   load_klass(obj_reg, temp_reg);
3363   ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3364   or3(G2_thread, temp_reg, temp_reg);
3365   xor3(mark_reg, temp_reg, temp_reg);
3366   andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg);
3367   if (counters != NULL) {
3368     cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg);
3369     // Reload mark_reg as we may need it later
3370     ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg);
3371   }
3372   brx(Assembler::equal, true, Assembler::pt, done);
3373   delayed()->nop();
3374 
3375   Label try_revoke_bias;
3376   Label try_rebias;
3377   Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
3378   assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3379 
3380   // At this point we know that the header has the bias pattern and


3407   // fails we will go in to the runtime to revoke the object's bias.
3408   // Note that we first construct the presumed unbiased header so we
3409   // don't accidentally blow away another thread's valid bias.
3410   delayed()->and3(mark_reg,
3411                   markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place,
3412                   mark_reg);
3413   or3(G2_thread, mark_reg, temp_reg);
3414   casn(mark_addr.base(), mark_reg, temp_reg);
3415   // If the biasing toward our thread failed, this means that
3416   // another thread succeeded in biasing it toward itself and we
3417   // need to revoke that bias. The revocation will occur in the
3418   // interpreter runtime in the slow case.
3419   cmp(mark_reg, temp_reg);
3420   if (counters != NULL) {
3421     cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg);
3422   }
3423   if (slow_case != NULL) {
3424     brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3425     delayed()->nop();
3426   }
3427   ba_short(done);

3428 
3429   bind(try_rebias);
3430   // At this point we know the epoch has expired, meaning that the
3431   // current "bias owner", if any, is actually invalid. Under these
3432   // circumstances _only_, we are allowed to use the current header's
3433   // value as the comparison value when doing the cas to acquire the
3434   // bias in the current epoch. In other words, we allow transfer of
3435   // the bias from one thread to another directly in this situation.
3436   //
3437   // FIXME: due to a lack of registers we currently blow away the age
3438   // bits in this situation. Should attempt to preserve them.
3439   load_klass(obj_reg, temp_reg);
3440   ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3441   or3(G2_thread, temp_reg, temp_reg);
3442   casn(mark_addr.base(), mark_reg, temp_reg);
3443   // If the biasing toward our thread failed, this means that
3444   // another thread succeeded in biasing it toward itself and we
3445   // need to revoke that bias. The revocation will occur in the
3446   // interpreter runtime in the slow case.
3447   cmp(mark_reg, temp_reg);
3448   if (counters != NULL) {
3449     cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg);
3450   }
3451   if (slow_case != NULL) {
3452     brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3453     delayed()->nop();
3454   }
3455   ba_short(done);

3456 
3457   bind(try_revoke_bias);
3458   // The prototype mark in the klass doesn't have the bias bit set any
3459   // more, indicating that objects of this data type are not supposed
3460   // to be biased any more. We are going to try to reset the mark of
3461   // this object to the prototype value and fall through to the
3462   // CAS-based locking scheme. Note that if our CAS fails, it means
3463   // that another thread raced us for the privilege of revoking the
3464   // bias of this particular object, so it's okay to continue in the
3465   // normal locking code.
3466   //
3467   // FIXME: due to a lack of registers we currently blow away the age
3468   // bits in this situation. Should attempt to preserve them.
3469   load_klass(obj_reg, temp_reg);
3470   ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3471   casn(mark_addr.base(), mark_reg, temp_reg);
3472   // Fall through to the normal CAS-based lock, because no matter what
3473   // the result of the above CAS, some thread must have succeeded in
3474   // removing the bias bit from the object's header.
3475   if (counters != NULL) {


3486   // Note: we do not have to check the thread ID for two reasons.
3487   // First, the interpreter checks for IllegalMonitorStateException at
3488   // a higher level. Second, if the bias was revoked while we held the
3489   // lock, the object could not be rebiased toward another thread, so
3490   // the bias bit would be clear.
3491   ld_ptr(mark_addr, temp_reg);
3492   and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3493   cmp(temp_reg, markOopDesc::biased_lock_pattern);
3494   brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done);
3495   delayed();
3496   if (!allow_delay_slot_filling) {
3497     nop();
3498   }
3499 }
3500 
3501 
3502 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by
3503 // Solaris/SPARC's "as".  Another apt name would be cas_ptr()
3504 
3505 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) {
3506   casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3507 }
3508 
3509 
3510 
3511 // compiler_lock_object() and compiler_unlock_object() are direct transliterations
3512 // of i486.ad fast_lock() and fast_unlock().  See those methods for detailed comments.
3513 // The code could be tightened up considerably.
3514 //
3515 // box->dhw disposition - post-conditions at DONE_LABEL.
3516 // -   Successful inflated lock:  box->dhw != 0.
3517 //     Any non-zero value suffices.
3518 //     Consider G2_thread, rsp, boxReg, or unused_mark()
3519 // -   Successful Stack-lock: box->dhw == mark.
3520 //     box->dhw must contain the displaced mark word value
3521 // -   Failure -- icc.ZFlag == 0 and box->dhw is undefined.
3522 //     The slow-path fast_enter() and slow_enter() operators
3523 //     are responsible for setting box->dhw = NonZero (typically ::unused_mark).
3524 // -   Biased: box->dhw is undefined
3525 //
3526 // SPARC refworkload performance - specifically jetstream and scimark - are
3527 // extremely sensitive to the size of the code emitted by compiler_lock_object
3528 // and compiler_unlock_object.  Critically, the key factor is code size, not path
3529 // length.  (Simply experiments to pad CLO with unexecuted NOPs demonstrte the
3530 // effect).
3531 
3532 
3533 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark,
3534                                           Register Rbox, Register Rscratch,
3535                                           BiasedLockingCounters* counters,
3536                                           bool try_bias) {
3537    Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3538 
3539    verify_oop(Roop);
3540    Label done ;
3541 
3542    if (counters != NULL) {
3543      inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch);
3544    }
3545 
3546    if (EmitSync & 1) {
3547      mov(3, Rscratch);
3548      st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3549      cmp(SP, G0);
3550      return ;
3551    }
3552 
3553    if (EmitSync & 2) {
3554 
3555      // Fetch object's markword
3556      ld_ptr(mark_addr, Rmark);
3557 
3558      if (try_bias) {
3559         biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3560      }
3561 
3562      // Save Rbox in Rscratch to be used for the cas operation
3563      mov(Rbox, Rscratch);
3564 
3565      // set Rmark to markOop | markOopDesc::unlocked_value
3566      or3(Rmark, markOopDesc::unlocked_value, Rmark);
3567 
3568      // Initialize the box.  (Must happen before we update the object mark!)
3569      st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3570 
3571      // compare object markOop with Rmark and if equal exchange Rscratch with object markOop
3572      assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3573      casx_under_lock(mark_addr.base(), Rmark, Rscratch,
3574         (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3575 
3576      // if compare/exchange succeeded we found an unlocked object and we now have locked it
3577      // hence we are done
3578      cmp(Rmark, Rscratch);
3579 #ifdef _LP64
3580      sub(Rscratch, STACK_BIAS, Rscratch);
3581 #endif
3582      brx(Assembler::equal, false, Assembler::pt, done);
3583      delayed()->sub(Rscratch, SP, Rscratch);  //pull next instruction into delay slot
3584 
3585      // we did not find an unlocked object so see if this is a recursive case
3586      // sub(Rscratch, SP, Rscratch);
3587      assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3588      andcc(Rscratch, 0xfffff003, Rscratch);
3589      st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3590      bind (done);
3591      return ;
3592    }
3593 
3594    Label Egress ;
3595 
3596    if (EmitSync & 256) {
3597       Label IsInflated ;
3598 
3599       ld_ptr(mark_addr, Rmark);           // fetch obj->mark
3600       // Triage: biased, stack-locked, neutral, inflated
3601       if (try_bias) {
3602         biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3603         // Invariant: if control reaches this point in the emitted stream
3604         // then Rmark has not been modified.
3605       }
3606 
3607       // Store mark into displaced mark field in the on-stack basic-lock "box"
3608       // Critically, this must happen before the CAS
3609       // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty.
3610       st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3611       andcc(Rmark, 2, G0);
3612       brx(Assembler::notZero, false, Assembler::pn, IsInflated);
3613       delayed()->
3614 
3615       // Try stack-lock acquisition.
3616       // Beware: the 1st instruction is in a delay slot
3617       mov(Rbox,  Rscratch);
3618       or3(Rmark, markOopDesc::unlocked_value, Rmark);
3619       assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3620       casn(mark_addr.base(), Rmark, Rscratch);
3621       cmp(Rmark, Rscratch);
3622       brx(Assembler::equal, false, Assembler::pt, done);
3623       delayed()->sub(Rscratch, SP, Rscratch);
3624 
3625       // Stack-lock attempt failed - check for recursive stack-lock.
3626       // See the comments below about how we might remove this case.
3627 #ifdef _LP64
3628       sub(Rscratch, STACK_BIAS, Rscratch);
3629 #endif
3630       assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3631       andcc(Rscratch, 0xfffff003, Rscratch);
3632       br(Assembler::always, false, Assembler::pt, done);
3633       delayed()-> st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3634 
3635       bind(IsInflated);
3636       if (EmitSync & 64) {
3637          // If m->owner != null goto IsLocked
3638          // Pessimistic form: Test-and-CAS vs CAS
3639          // The optimistic form avoids RTS->RTO cache line upgrades.
3640          ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3641          andcc(Rscratch, Rscratch, G0);
3642          brx(Assembler::notZero, false, Assembler::pn, done);
3643          delayed()->nop();
3644          // m->owner == null : it's unlocked.
3645       }
3646 
3647       // Try to CAS m->owner from null to Self
3648       // Invariant: if we acquire the lock then _recursions should be 0.
3649       add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
3650       mov(G2_thread, Rscratch);
3651       casn(Rmark, G0, Rscratch);
3652       cmp(Rscratch, G0);
3653       // Intentional fall-through into done
3654    } else {
3655       // Aggressively avoid the Store-before-CAS penalty
3656       // Defer the store into box->dhw until after the CAS
3657       Label IsInflated, Recursive ;
3658 
3659 // Anticipate CAS -- Avoid RTS->RTO upgrade
3660 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads);
3661 
3662       ld_ptr(mark_addr, Rmark);           // fetch obj->mark
3663       // Triage: biased, stack-locked, neutral, inflated
3664 
3665       if (try_bias) {
3666         biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3667         // Invariant: if control reaches this point in the emitted stream
3668         // then Rmark has not been modified.
3669       }
3670       andcc(Rmark, 2, G0);
3671       brx(Assembler::notZero, false, Assembler::pn, IsInflated);
3672       delayed()->                         // Beware - dangling delay-slot
3673 
3674       // Try stack-lock acquisition.
3675       // Transiently install BUSY (0) encoding in the mark word.
3676       // if the CAS of 0 into the mark was successful then we execute:
3677       //   ST box->dhw  = mark   -- save fetched mark in on-stack basiclock box
3678       //   ST obj->mark = box    -- overwrite transient 0 value
3679       // This presumes TSO, of course.
3680 
3681       mov(0, Rscratch);
3682       or3(Rmark, markOopDesc::unlocked_value, Rmark);
3683       assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3684       casn(mark_addr.base(), Rmark, Rscratch);
3685 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads);
3686       cmp(Rscratch, Rmark);
3687       brx(Assembler::notZero, false, Assembler::pn, Recursive);
3688       delayed()->st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());

3689       if (counters != NULL) {
3690         cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3691       }
3692       ba(done);
3693       delayed()->st_ptr(Rbox, mark_addr);

3694 
3695       bind(Recursive);
3696       // Stack-lock attempt failed - check for recursive stack-lock.
3697       // Tests show that we can remove the recursive case with no impact
3698       // on refworkload 0.83.  If we need to reduce the size of the code
3699       // emitted by compiler_lock_object() the recursive case is perfect
3700       // candidate.
3701       //
3702       // A more extreme idea is to always inflate on stack-lock recursion.
3703       // This lets us eliminate the recursive checks in compiler_lock_object
3704       // and compiler_unlock_object and the (box->dhw == 0) encoding.
3705       // A brief experiment - requiring changes to synchronizer.cpp, interpreter,
3706       // and showed a performance *increase*.  In the same experiment I eliminated
3707       // the fast-path stack-lock code from the interpreter and always passed
3708       // control to the "slow" operators in synchronizer.cpp.
3709 
3710       // RScratch contains the fetched obj->mark value from the failed CASN.
3711 #ifdef _LP64
3712       sub(Rscratch, STACK_BIAS, Rscratch);
3713 #endif
3714       sub(Rscratch, SP, Rscratch);
3715       assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3716       andcc(Rscratch, 0xfffff003, Rscratch);
3717       if (counters != NULL) {
3718         // Accounting needs the Rscratch register
3719         st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3720         cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3721         ba_short(done);

3722       } else {
3723         ba(done);
3724         delayed()->st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3725       }
3726 
3727       bind   (IsInflated);
3728       if (EmitSync & 64) {
3729          // If m->owner != null goto IsLocked
3730          // Test-and-CAS vs CAS
3731          // Pessimistic form avoids futile (doomed) CAS attempts
3732          // The optimistic form avoids RTS->RTO cache line upgrades.
3733          ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3734          andcc(Rscratch, Rscratch, G0);
3735          brx(Assembler::notZero, false, Assembler::pn, done);
3736          delayed()->nop();
3737          // m->owner == null : it's unlocked.
3738       }
3739 
3740       // Try to CAS m->owner from null to Self
3741       // Invariant: if we acquire the lock then _recursions should be 0.
3742       add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
3743       mov(G2_thread, Rscratch);
3744       casn(Rmark, G0, Rscratch);
3745       cmp(Rscratch, G0);
3746       // ST box->displaced_header = NonZero.
3747       // Any non-zero value suffices:
3748       //    unused_mark(), G2_thread, RBox, RScratch, rsp, etc.
3749       st_ptr(Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes());
3750       // Intentional fall-through into done
3751    }
3752 
3753    bind   (done);
3754 }
3755 
3756 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark,
3757                                             Register Rbox, Register Rscratch,
3758                                             bool try_bias) {
3759    Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3760 
3761    Label done ;
3762 
3763    if (EmitSync & 4) {
3764      cmp(SP, G0);
3765      return ;
3766    }
3767 
3768    if (EmitSync & 8) {
3769      if (try_bias) {
3770         biased_locking_exit(mark_addr, Rscratch, done);
3771      }
3772 
3773      // Test first if it is a fast recursive unlock
3774      ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark);
3775      br_null_short(Rmark, Assembler::pt, done);


3776 
3777      // Check if it is still a light weight lock, this is is true if we see
3778      // the stack address of the basicLock in the markOop of the object
3779      assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3780      casx_under_lock(mark_addr.base(), Rbox, Rmark,
3781        (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3782      ba(done);
3783      delayed()->cmp(Rbox, Rmark);
3784      bind(done);
3785      return ;
3786    }
3787 
3788    // Beware ... If the aggregate size of the code emitted by CLO and CUO is
3789    // is too large performance rolls abruptly off a cliff.
3790    // This could be related to inlining policies, code cache management, or
3791    // I$ effects.
3792    Label LStacked ;
3793 
3794    if (try_bias) {
3795       // TODO: eliminate redundant LDs of obj->mark
3796       biased_locking_exit(mark_addr, Rscratch, done);
3797    }
3798 
3799    ld_ptr(Roop, oopDesc::mark_offset_in_bytes(), Rmark);
3800    ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch);
3801    andcc(Rscratch, Rscratch, G0);
3802    brx(Assembler::zero, false, Assembler::pn, done);
3803    delayed()->nop();      // consider: relocate fetch of mark, above, into this DS
3804    andcc(Rmark, 2, G0);
3805    brx(Assembler::zero, false, Assembler::pt, LStacked);
3806    delayed()->nop();
3807 
3808    // It's inflated
3809    // Conceptually we need a #loadstore|#storestore "release" MEMBAR before
3810    // the ST of 0 into _owner which releases the lock.  This prevents loads
3811    // and stores within the critical section from reordering (floating)
3812    // past the store that releases the lock.  But TSO is a strong memory model
3813    // and that particular flavor of barrier is a noop, so we can safely elide it.
3814    // Note that we use 1-0 locking by default for the inflated case.  We
3815    // close the resultant (and rare) race by having contented threads in
3816    // monitorenter periodically poll _owner.
3817    ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3818    ld_ptr(Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox);
3819    xor3(Rscratch, G2_thread, Rscratch);
3820    orcc(Rbox, Rscratch, Rbox);
3821    brx(Assembler::notZero, false, Assembler::pn, done);
3822    delayed()->
3823    ld_ptr(Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch);
3824    ld_ptr(Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox);
3825    orcc(Rbox, Rscratch, G0);
3826    if (EmitSync & 65536) {
3827       Label LSucc ;
3828       brx(Assembler::notZero, false, Assembler::pn, LSucc);
3829       delayed()->nop();
3830       ba(done);
3831       delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);

3832 
3833       bind(LSucc);
3834       st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3835       if (os::is_MP()) { membar (StoreLoad); }
3836       ld_ptr(Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch);
3837       andcc(Rscratch, Rscratch, G0);
3838       brx(Assembler::notZero, false, Assembler::pt, done);
3839       delayed()->andcc(G0, G0, G0);
3840       add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
3841       mov(G2_thread, Rscratch);
3842       casn(Rmark, G0, Rscratch);

3843       // invert icc.zf and goto done
3844       br_notnull(Rscratch, false, Assembler::pt, done);
3845       delayed()->cmp(G0, G0);
3846       ba(done);
3847       delayed()->cmp(G0, 1);
3848    } else {
3849       brx(Assembler::notZero, false, Assembler::pn, done);
3850       delayed()->nop();
3851       ba(done);
3852       delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);

3853    }
3854 
3855    bind   (LStacked);
3856    // Consider: we could replace the expensive CAS in the exit
3857    // path with a simple ST of the displaced mark value fetched from
3858    // the on-stack basiclock box.  That admits a race where a thread T2
3859    // in the slow lock path -- inflating with monitor M -- could race a
3860    // thread T1 in the fast unlock path, resulting in a missed wakeup for T2.
3861    // More precisely T1 in the stack-lock unlock path could "stomp" the
3862    // inflated mark value M installed by T2, resulting in an orphan
3863    // object monitor M and T2 becoming stranded.  We can remedy that situation
3864    // by having T2 periodically poll the object's mark word using timed wait
3865    // operations.  If T2 discovers that a stomp has occurred it vacates
3866    // the monitor M and wakes any other threads stranded on the now-orphan M.
3867    // In addition the monitor scavenger, which performs deflation,
3868    // would also need to check for orpan monitors and stranded threads.
3869    //
3870    // Finally, inflation is also used when T2 needs to assign a hashCode
3871    // to O and O is stack-locked by T1.  The "stomp" race could cause
3872    // an assigned hashCode value to be lost.  We can avoid that condition
3873    // and provide the necessary hashCode stability invariants by ensuring
3874    // that hashCode generation is idempotent between copying GCs.
3875    // For example we could compute the hashCode of an object O as
3876    // O's heap address XOR some high quality RNG value that is refreshed
3877    // at GC-time.  The monitor scavenger would install the hashCode
3878    // found in any orphan monitors.  Again, the mechanism admits a
3879    // lost-update "stomp" WAW race but detects and recovers as needed.
3880    //
3881    // A prototype implementation showed excellent results, although
3882    // the scavenger and timeout code was rather involved.
3883 
3884    casn(mark_addr.base(), Rbox, Rscratch);
3885    cmp(Rbox, Rscratch);
3886    // Intentional fall through into done ...
3887 
3888    bind(done);
3889 }
3890 
3891 
3892 
3893 void MacroAssembler::print_CPU_state() {
3894   // %%%%% need to implement this
3895 }
3896 
3897 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
3898   // %%%%% need to implement this
3899 }
3900 
3901 void MacroAssembler::push_IU_state() {
3902   // %%%%% need to implement this
3903 }
3904 
3905 
3906 void MacroAssembler::pop_IU_state() {
3907   // %%%%% need to implement this
3908 }


3924 
3925 
3926 void MacroAssembler::pop_CPU_state() {
3927   // %%%%% need to implement this
3928 }
3929 
3930 
3931 
3932 void MacroAssembler::verify_tlab() {
3933 #ifdef ASSERT
3934   if (UseTLAB && VerifyOops) {
3935     Label next, next2, ok;
3936     Register t1 = L0;
3937     Register t2 = L1;
3938     Register t3 = L2;
3939 
3940     save_frame(0);
3941     ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3942     ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2);
3943     or3(t1, t2, t3);
3944     cmp_and_br_short(t1, t2, Assembler::greaterEqual, Assembler::pn, next);


3945     stop("assert(top >= start)");
3946     should_not_reach_here();
3947 
3948     bind(next);
3949     ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3950     ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2);
3951     or3(t3, t2, t3);
3952     cmp_and_br_short(t1, t2, Assembler::lessEqual, Assembler::pn, next2);


3953     stop("assert(top <= end)");
3954     should_not_reach_here();
3955 
3956     bind(next2);
3957     and3(t3, MinObjAlignmentInBytesMask, t3);
3958     cmp_and_br_short(t3, 0, Assembler::lessEqual, Assembler::pn, ok);


3959     stop("assert(aligned)");
3960     should_not_reach_here();
3961 
3962     bind(ok);
3963     restore();
3964   }
3965 #endif
3966 }
3967 
3968 
3969 void MacroAssembler::eden_allocate(
3970   Register obj,                        // result: pointer to object after successful allocation
3971   Register var_size_in_bytes,          // object size in bytes if unknown at compile time; invalid otherwise
3972   int      con_size_in_bytes,          // object size in bytes if   known at compile time
3973   Register t1,                         // temp register
3974   Register t2,                         // temp register
3975   Label&   slow_case                   // continuation point if fast allocation fails
3976 ){
3977   // make sure arguments make sense
3978   assert_different_registers(obj, var_size_in_bytes, t1, t2);
3979   assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size");
3980   assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3981 
3982   if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
3983     // No allocation in the shared eden.
3984     ba_short(slow_case);

3985   } else {
3986     // get eden boundaries
3987     // note: we need both top & top_addr!
3988     const Register top_addr = t1;
3989     const Register end      = t2;
3990 
3991     CollectedHeap* ch = Universe::heap();
3992     set((intx)ch->top_addr(), top_addr);
3993     intx delta = (intx)ch->end_addr() - (intx)ch->top_addr();
3994     ld_ptr(top_addr, delta, end);
3995     ld_ptr(top_addr, 0, obj);
3996 
3997     // try to allocate
3998     Label retry;
3999     bind(retry);
4000 #ifdef ASSERT
4001     // make sure eden top is properly aligned
4002     {
4003       Label L;
4004       btst(MinObjAlignmentInBytesMask, obj);


4098     bind(L);
4099   }
4100 #endif // ASSERT
4101 
4102   // update the tlab top pointer
4103   st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
4104   verify_tlab();
4105 }
4106 
4107 
4108 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
4109   Register top = O0;
4110   Register t1 = G1;
4111   Register t2 = G3;
4112   Register t3 = O1;
4113   assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */);
4114   Label do_refill, discard_tlab;
4115 
4116   if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
4117     // No allocation in the shared eden.
4118     ba_short(slow_case);

4119   }
4120 
4121   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top);
4122   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1);
4123   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2);
4124 
4125   // calculate amount of free space
4126   sub(t1, top, t1);
4127   srl_ptr(t1, LogHeapWordSize, t1);
4128 
4129   // Retain tlab and allocate object in shared space if
4130   // the amount free in the tlab is too large to discard.
4131   cmp(t1, t2);
4132   brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab);
4133 
4134   // increment waste limit to prevent getting stuck on this slow path
4135   delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2);
4136   st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
4137   if (TLABStats) {
4138     // increment number of slow_allocations
4139     ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2);
4140     add(t2, 1, t2);
4141     stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()));
4142   }
4143   ba_short(try_eden);

4144 
4145   bind(discard_tlab);
4146   if (TLABStats) {
4147     // increment number of refills
4148     ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2);
4149     add(t2, 1, t2);
4150     stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()));
4151     // accumulate wastage
4152     ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2);
4153     add(t2, t1, t2);
4154     stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
4155   }
4156 
4157   // if tlab is currently allocated (top or end != null) then
4158   // fill [top, end + alignment_reserve) with array object
4159   br_null_short(top, Assembler::pn, do_refill);

4160 
4161   set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2);
4162   st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word
4163   // set klass to intArrayKlass
4164   sub(t1, typeArrayOopDesc::header_size(T_INT), t1);
4165   add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1);
4166   sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1);
4167   st(t1, top, arrayOopDesc::length_offset_in_bytes());
4168   set((intptr_t)Universe::intArrayKlassObj_addr(), t2);
4169   ld_ptr(t2, 0, t2);
4170   // store klass last.  concurrent gcs assumes klass length is valid if
4171   // klass field is not null.
4172   store_klass(t2, top);
4173   verify_oop(top);
4174 
4175   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1);
4176   sub(top, t1, t1); // size of tlab's allocated portion
4177   incr_allocated_bytes(t1, t2, t3);
4178 
4179   // refill the tlab with an eden allocation
4180   bind(do_refill);
4181   ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1);
4182   sll_ptr(t1, LogHeapWordSize, t1);
4183   // allocate new tlab, address returned in top
4184   eden_allocate(top, t1, 0, t2, t3, slow_case);
4185 
4186   st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset()));
4187   st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
4188 #ifdef ASSERT
4189   // check that tlab_size (t1) is still valid
4190   {
4191     Label ok;
4192     ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2);
4193     sll_ptr(t2, LogHeapWordSize, t2);
4194     cmp_and_br_short(t1, t2, Assembler::equal, Assembler::pt, ok);


4195     stop("assert(t1 == tlab_size)");
4196     should_not_reach_here();
4197 
4198     bind(ok);
4199   }
4200 #endif // ASSERT
4201   add(top, t1, top); // t1 is tlab_size
4202   sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top);
4203   st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset()));
4204   verify_tlab();
4205   ba_short(retry);

4206 }
4207 
4208 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes,
4209                                           Register t1, Register t2) {
4210   // Bump total bytes allocated by this thread
4211   assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch
4212   assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2);
4213   // v8 support has gone the way of the dodo
4214   ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1);
4215   add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1);
4216   stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset()));
4217 }
4218 
4219 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
4220   switch (cond) {
4221     // Note some conditions are synonyms for others
4222     case Assembler::never:                return Assembler::always;
4223     case Assembler::zero:                 return Assembler::notZero;
4224     case Assembler::lessEqual:            return Assembler::greater;
4225     case Assembler::less:                 return Assembler::greaterEqual;


4310     set((-i*offset)+STACK_BIAS, Rscratch);
4311     st(G0, Rtsp, Rscratch);
4312   }
4313 }
4314 
4315 ///////////////////////////////////////////////////////////////////////////////////
4316 #ifndef SERIALGC
4317 
4318 static address satb_log_enqueue_with_frame = NULL;
4319 static u_char* satb_log_enqueue_with_frame_end = NULL;
4320 
4321 static address satb_log_enqueue_frameless = NULL;
4322 static u_char* satb_log_enqueue_frameless_end = NULL;
4323 
4324 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions?
4325 
4326 static void generate_satb_log_enqueue(bool with_frame) {
4327   BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize);
4328   CodeBuffer buf(bb);
4329   MacroAssembler masm(&buf);
4330 
4331 #define __ masm.
4332 
4333   address start = __ pc();
4334   Register pre_val;
4335 
4336   Label refill, restart;
4337   if (with_frame) {
4338     __ save_frame(0);
4339     pre_val = I0;  // Was O0 before the save.
4340   } else {
4341     pre_val = O0;
4342   }
4343   int satb_q_index_byte_offset =
4344     in_bytes(JavaThread::satb_mark_queue_offset() +
4345              PtrQueue::byte_offset_of_index());
4346   int satb_q_buf_byte_offset =
4347     in_bytes(JavaThread::satb_mark_queue_offset() +
4348              PtrQueue::byte_offset_of_buf());
4349   assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) &&
4350          in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t),
4351          "check sizes in assembly below");
4352 
4353   __ bind(restart);
4354   __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0);
4355 
4356   __ br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, L0, refill);
4357   // If the branch is taken, no harm in executing this in the delay slot.
4358   __ delayed()->ld_ptr(G2_thread, satb_q_buf_byte_offset, L1);
4359   __ sub(L0, oopSize, L0);
4360 
4361   __ st_ptr(pre_val, L1, L0);  // [_buf + index] := I0
4362   if (!with_frame) {
4363     // Use return-from-leaf
4364     __ retl();
4365     __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset);
4366   } else {
4367     // Not delayed.
4368     __ st_ptr(L0, G2_thread, satb_q_index_byte_offset);
4369   }
4370   if (with_frame) {
4371     __ ret();
4372     __ delayed()->restore();
4373   }
4374   __ bind(refill);
4375 
4376   address handle_zero =
4377     CAST_FROM_FN_PTR(address,
4378                      &SATBMarkQueueSet::handle_zero_index_for_thread);
4379   // This should be rare enough that we can afford to save all the
4380   // scratch registers that the calling context might be using.
4381   __ mov(G1_scratch, L0);
4382   __ mov(G3_scratch, L1);
4383   __ mov(G4, L2);
4384   // We need the value of O0 above (for the write into the buffer), so we
4385   // save and restore it.
4386   __ mov(O0, L3);
4387   // Since the call will overwrite O7, we save and restore that, as well.
4388   __ mov(O7, L4);
4389   __ call_VM_leaf(L5, handle_zero, G2_thread);
4390   __ mov(L0, G1_scratch);
4391   __ mov(L1, G3_scratch);
4392   __ mov(L2, G4);
4393   __ mov(L3, O0);
4394   __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4395   __ delayed()->mov(L4, O7);
4396 
4397   if (with_frame) {
4398     satb_log_enqueue_with_frame = start;
4399     satb_log_enqueue_with_frame_end = __ pc();
4400   } else {
4401     satb_log_enqueue_frameless = start;
4402     satb_log_enqueue_frameless_end = __ pc();
4403   }
4404 
4405 #undef __
4406 }
4407 
4408 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) {
4409   if (with_frame) {
4410     if (satb_log_enqueue_with_frame == 0) {
4411       generate_satb_log_enqueue(with_frame);
4412       assert(satb_log_enqueue_with_frame != 0, "postcondition.");
4413       if (G1SATBPrintStubs) {
4414         tty->print_cr("Generated with-frame satb enqueue:");
4415         Disassembler::decode((u_char*)satb_log_enqueue_with_frame,
4416                              satb_log_enqueue_with_frame_end,
4417                              tty);
4418       }
4419     }
4420   } else {
4421     if (satb_log_enqueue_frameless == 0) {
4422       generate_satb_log_enqueue(with_frame);
4423       assert(satb_log_enqueue_frameless != 0, "postcondition.");
4424       if (G1SATBPrintStubs) {
4425         tty->print_cr("Generated frameless satb enqueue:");


4451     assert(pre_val == noreg, "check this code");
4452   }
4453 
4454   // Is marking active?
4455   if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4456     ld(G2,
4457        in_bytes(JavaThread::satb_mark_queue_offset() +
4458                 PtrQueue::byte_offset_of_active()),
4459        tmp);
4460   } else {
4461     guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1,
4462               "Assumption");
4463     ldsb(G2,
4464          in_bytes(JavaThread::satb_mark_queue_offset() +
4465                   PtrQueue::byte_offset_of_active()),
4466          tmp);
4467   }
4468 
4469   // Check on whether to annul.
4470   br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered);
4471   delayed()->nop();
4472 
4473   // Do we need to load the previous value?
4474   if (obj != noreg) {
4475     // Load the previous value...
4476     if (index == noreg) {
4477       if (Assembler::is_simm13(offset)) {
4478         load_heap_oop(obj, offset, tmp);
4479       } else {
4480         set(offset, tmp);
4481         load_heap_oop(obj, tmp, tmp);
4482       }
4483     } else {
4484       load_heap_oop(obj, index, tmp);
4485     }
4486     // Previous value has been loaded into tmp
4487     pre_val = tmp;
4488   }
4489 
4490   assert(pre_val != noreg, "must have a real register");
4491 
4492   // Is the previous value null?
4493   // Check on whether to annul.
4494   br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, pre_val, filtered);
4495   delayed()->nop();
4496 
4497   // OK, it's not filtered, so we'll need to call enqueue.  In the normal
4498   // case, pre_val will be a scratch G-reg, but there are some cases in
4499   // which it's an O-reg.  In the first case, do a normal call.  In the
4500   // latter, do a save here and call the frameless version.
4501 
4502   guarantee(pre_val->is_global() || pre_val->is_out(),
4503             "Or we need to think harder.");
4504 
4505   if (pre_val->is_global() && !preserve_o_regs) {
4506     generate_satb_log_enqueue_if_necessary(true); // with frame
4507 
4508     call(satb_log_enqueue_with_frame);
4509     delayed()->mov(pre_val, O0);
4510   } else {
4511     generate_satb_log_enqueue_if_necessary(false); // frameless
4512 
4513     save_frame(0);
4514     call(satb_log_enqueue_frameless);
4515     delayed()->mov(pre_val->after_save(), O0);


4543     tty->print_cr("%d potential CT writes: %5.2f%% filtered\n"
4544                   "   (%5.2f%% intra-HR, %5.2f%% null).",
4545                   num_ct_writes,
4546                   100.0*(float)num_ct_writes_filtered/(float)num_ct_writes,
4547                   100.0*(float)num_ct_writes_filtered_in_hr/
4548                   (float)num_ct_writes,
4549                   100.0*(float)num_ct_writes_filtered_null/
4550                   (float)num_ct_writes);
4551   }
4552   return Thread::current();
4553 }
4554 
4555 static address dirty_card_log_enqueue = 0;
4556 static u_char* dirty_card_log_enqueue_end = 0;
4557 
4558 // This gets to assume that o0 contains the object address.
4559 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) {
4560   BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2);
4561   CodeBuffer buf(bb);
4562   MacroAssembler masm(&buf);
4563 #define __ masm.
4564   address start = __ pc();
4565 
4566   Label not_already_dirty, restart, refill;
4567 
4568 #ifdef _LP64
4569   __ srlx(O0, CardTableModRefBS::card_shift, O0);
4570 #else
4571   __ srl(O0, CardTableModRefBS::card_shift, O0);
4572 #endif
4573   AddressLiteral addrlit(byte_map_base);
4574   __ set(addrlit, O1); // O1 := <card table base>
4575   __ ldub(O0, O1, O2); // O2 := [O0 + O1]
4576 
4577   __ br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt,
4578                       O2, not_already_dirty);
4579   // Get O1 + O2 into a reg by itself -- useful in the take-the-branch
4580   // case, harmless if not.
4581   __ delayed()->add(O0, O1, O3);
4582 
4583   // We didn't take the branch, so we're already dirty: return.
4584   // Use return-from-leaf
4585   __ retl();
4586   __ delayed()->nop();
4587 
4588   // Not dirty.
4589   __ bind(not_already_dirty);
4590   // First, dirty it.
4591   __ stb(G0, O3, G0);  // [cardPtr] := 0  (i.e., dirty).
4592   int dirty_card_q_index_byte_offset =
4593     in_bytes(JavaThread::dirty_card_queue_offset() +
4594              PtrQueue::byte_offset_of_index());
4595   int dirty_card_q_buf_byte_offset =
4596     in_bytes(JavaThread::dirty_card_queue_offset() +
4597              PtrQueue::byte_offset_of_buf());
4598   __ bind(restart);
4599   __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0);
4600 
4601   __ br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn,
4602                       L0, refill);
4603   // If the branch is taken, no harm in executing this in the delay slot.
4604   __ delayed()->ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1);
4605   __ sub(L0, oopSize, L0);
4606 
4607   __ st_ptr(O3, L1, L0);  // [_buf + index] := I0
4608   // Use return-from-leaf
4609   __ retl();
4610   __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset);
4611 
4612   __ bind(refill);
4613   address handle_zero =
4614     CAST_FROM_FN_PTR(address,
4615                      &DirtyCardQueueSet::handle_zero_index_for_thread);
4616   // This should be rare enough that we can afford to save all the
4617   // scratch registers that the calling context might be using.
4618   __ mov(G1_scratch, L3);
4619   __ mov(G3_scratch, L5);
4620   // We need the value of O3 above (for the write into the buffer), so we
4621   // save and restore it.
4622   __ mov(O3, L6);
4623   // Since the call will overwrite O7, we save and restore that, as well.
4624   __ mov(O7, L4);
4625 
4626   __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread);
4627   __ mov(L3, G1_scratch);
4628   __ mov(L5, G3_scratch);
4629   __ mov(L6, O3);
4630   __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4631   __ delayed()->mov(L4, O7);
4632 
4633   dirty_card_log_enqueue = start;
4634   dirty_card_log_enqueue_end = __ pc();
4635   // XXX Should have a guarantee here about not going off the end!
4636   // Does it already do so?  Do an experiment...
4637 
4638 #undef __
4639 
4640 }
4641 
4642 static inline void
4643 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) {
4644   if (dirty_card_log_enqueue == 0) {
4645     generate_dirty_card_log_enqueue(byte_map_base);
4646     assert(dirty_card_log_enqueue != 0, "postcondition.");
4647     if (G1SATBPrintStubs) {
4648       tty->print_cr("Generated dirty_card enqueue:");
4649       Disassembler::decode((u_char*)dirty_card_log_enqueue,
4650                            dirty_card_log_enqueue_end,
4651                            tty);
4652     }
4653   }
4654 }
4655 
4656 
4657 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
4658 
4659   Label filtered;


4932 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
4933                                         Register limit, Register result,
4934                                         Register chr1, Register chr2, Label& Ldone) {
4935   Label Lvector, Lloop;
4936   assert(chr1 == result, "should be the same");
4937 
4938   // Note: limit contains number of bytes (2*char_elements) != 0.
4939   andcc(limit, 0x2, chr1); // trailing character ?
4940   br(Assembler::zero, false, Assembler::pt, Lvector);
4941   delayed()->nop();
4942 
4943   // compare the trailing char
4944   sub(limit, sizeof(jchar), limit);
4945   lduh(ary1, limit, chr1);
4946   lduh(ary2, limit, chr2);
4947   cmp(chr1, chr2);
4948   br(Assembler::notEqual, true, Assembler::pt, Ldone);
4949   delayed()->mov(G0, result);     // not equal
4950 
4951   // only one char ?
4952   bpr(rc_z, true, Assembler::pn, limit, Ldone);
4953   delayed()->add(G0, 1, result); // zero-length arrays are equal
4954 
4955   // word by word compare, dont't need alignment check
4956   bind(Lvector);
4957   // Shift ary1 and ary2 to the end of the arrays, negate limit
4958   add(ary1, limit, ary1);
4959   add(ary2, limit, ary2);
4960   neg(limit, limit);
4961 
4962   lduw(ary1, limit, chr1);
4963   bind(Lloop);
4964   lduw(ary2, limit, chr2);
4965   cmp(chr1, chr2);
4966   br(Assembler::notEqual, true, Assembler::pt, Ldone);
4967   delayed()->mov(G0, result);     // not equal
4968   inccc(limit, 2*sizeof(jchar));
4969   // annul LDUW if branch is not taken to prevent access past end of array
4970   br(Assembler::notZero, true, Assembler::pt, Lloop);
4971   delayed()->lduw(ary1, limit, chr1); // hoisted
4972 
src/cpu/sparc/vm/assembler_sparc.cpp
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