1 /*
   2  * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
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  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  24 
  25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
  26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
  27 
  28 class BiasedLockingCounters;
  29 
  30 // <sys/trap.h> promises that the system will not use traps 16-31
  31 #define ST_RESERVED_FOR_USER_0 0x10
  32 
  33 /* Written: David Ungar 4/19/97 */
  34 
  35 // Contains all the definitions needed for sparc assembly code generation.
  36 
  37 // Register aliases for parts of the system:
  38 
  39 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
  40 // across context switches in V8+ ABI.  Of course, there are no 64 bit regs
  41 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
  42 
  43 // g2-g4 are scratch registers called "application globals".  Their
  44 // meaning is reserved to the "compilation system"--which means us!
  45 // They are are not supposed to be touched by ordinary C code, although
  46 // highly-optimized C code might steal them for temps.  They are safe
  47 // across thread switches, and the ABI requires that they be safe
  48 // across function calls.
  49 //
  50 // g1 and g3 are touched by more modules.  V8 allows g1 to be clobbered
  51 // across func calls, and V8+ also allows g5 to be clobbered across
  52 // func calls.  Also, g1 and g5 can get touched while doing shared
  53 // library loading.
  54 //
  55 // We must not touch g7 (it is the thread-self register) and g6 is
  56 // reserved for certain tools.  g0, of course, is always zero.
  57 //
  58 // (Sources:  SunSoft Compilers Group, thread library engineers.)
  59 
  60 // %%%% The interpreter should be revisited to reduce global scratch regs.
  61 
  62 // This global always holds the current JavaThread pointer:
  63 
  64 REGISTER_DECLARATION(Register, G2_thread , G2);
  65 REGISTER_DECLARATION(Register, G6_heapbase , G6);
  66 
  67 // The following globals are part of the Java calling convention:
  68 
  69 REGISTER_DECLARATION(Register, G5_method             , G5);
  70 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
  71 REGISTER_DECLARATION(Register, G5_inline_cache_reg   , G5_method);
  72 
  73 // The following globals are used for the new C1 & interpreter calling convention:
  74 REGISTER_DECLARATION(Register, Gargs        , G4); // pointing to the last argument
  75 
  76 // This local is used to preserve G2_thread in the interpreter and in stubs:
  77 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
  78 
  79 // These globals are used as scratch registers in the interpreter:
  80 
  81 REGISTER_DECLARATION(Register, Gframe_size   , G1); // SAME REG as G1_scratch
  82 REGISTER_DECLARATION(Register, G1_scratch    , G1); // also SAME
  83 REGISTER_DECLARATION(Register, G3_scratch    , G3);
  84 REGISTER_DECLARATION(Register, G4_scratch    , G4);
  85 
  86 // These globals are used as short-lived scratch registers in the compiler:
  87 
  88 REGISTER_DECLARATION(Register, Gtemp  , G5);
  89 
  90 // JSR 292 fixed register usages:
  91 REGISTER_DECLARATION(Register, G5_method_type        , G5);
  92 REGISTER_DECLARATION(Register, G3_method_handle      , G3);
  93 REGISTER_DECLARATION(Register, L7_mh_SP_save         , L7);
  94 
  95 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
  96 // because a single patchable "set" instruction (NativeMovConstReg,
  97 // or NativeMovConstPatching for compiler1) instruction
  98 // serves to set up either quantity, depending on whether the compiled
  99 // call site is an inline cache or is megamorphic.  See the function
 100 // CompiledIC::set_to_megamorphic.
 101 //
 102 // If a inline cache targets an interpreted method, then the
 103 // G5 register will be used twice during the call.  First,
 104 // the call site will be patched to load a compiledICHolder
 105 // into G5. (This is an ordered pair of ic_klass, method.)
 106 // The c2i adapter will first check the ic_klass, then load
 107 // G5_method with the method part of the pair just before
 108 // jumping into the interpreter.
 109 //
 110 // Note that G5_method is only the method-self for the interpreter,
 111 // and is logically unrelated to G5_megamorphic_method.
 112 //
 113 // Invariants on G2_thread (the JavaThread pointer):
 114 //  - it should not be used for any other purpose anywhere
 115 //  - it must be re-initialized by StubRoutines::call_stub()
 116 //  - it must be preserved around every use of call_VM
 117 
 118 // We can consider using g2/g3/g4 to cache more values than the
 119 // JavaThread, such as the card-marking base or perhaps pointers into
 120 // Eden.  It's something of a waste to use them as scratch temporaries,
 121 // since they are not supposed to be volatile.  (Of course, if we find
 122 // that Java doesn't benefit from application globals, then we can just
 123 // use them as ordinary temporaries.)
 124 //
 125 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
 126 // it makes sense to use them routinely for procedure linkage,
 127 // whenever the On registers are not applicable.  Examples:  G5_method,
 128 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
 129 // stubs.  This means that compiler stubs, etc., should be kept to a
 130 // maximum of two or three G-register arguments.
 131 
 132 
 133 // stub frames
 134 
 135 REGISTER_DECLARATION(Register, Lentry_args      , L0); // pointer to args passed to callee (interpreter) not stub itself
 136 
 137 // Interpreter frames
 138 
 139 #ifdef CC_INTERP
 140 REGISTER_DECLARATION(Register, Lstate           , L0); // interpreter state object pointer
 141 REGISTER_DECLARATION(Register, L1_scratch       , L1); // scratch
 142 REGISTER_DECLARATION(Register, Lmirror          , L1); // mirror (for native methods only)
 143 REGISTER_DECLARATION(Register, L2_scratch       , L2);
 144 REGISTER_DECLARATION(Register, L3_scratch       , L3);
 145 REGISTER_DECLARATION(Register, L4_scratch       , L4);
 146 REGISTER_DECLARATION(Register, Lscratch         , L5); // C1 uses
 147 REGISTER_DECLARATION(Register, Lscratch2        , L6); // C1 uses
 148 REGISTER_DECLARATION(Register, L7_scratch       , L7); // constant pool cache
 149 REGISTER_DECLARATION(Register, O5_savedSP       , O5);
 150 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
 151                                                        // a copy SP, so in 64-bit it's a biased value.  The bias
 152                                                        // is added and removed as needed in the frame code.
 153 // Interface to signature handler
 154 REGISTER_DECLARATION(Register, Llocals          , L7); // pointer to locals for signature handler
 155 REGISTER_DECLARATION(Register, Lmethod          , L6); // methodOop when calling signature handler
 156 
 157 #else
 158 REGISTER_DECLARATION(Register, Lesp             , L0); // expression stack pointer
 159 REGISTER_DECLARATION(Register, Lbcp             , L1); // pointer to next bytecode
 160 REGISTER_DECLARATION(Register, Lmethod          , L2);
 161 REGISTER_DECLARATION(Register, Llocals          , L3);
 162 REGISTER_DECLARATION(Register, Largs            , L3); // pointer to locals for signature handler
 163                                                        // must match Llocals in asm interpreter
 164 REGISTER_DECLARATION(Register, Lmonitors        , L4);
 165 REGISTER_DECLARATION(Register, Lbyte_code       , L5);
 166 // When calling out from the interpreter we record SP so that we can remove any extra stack
 167 // space allocated during adapter transitions. This register is only live from the point
 168 // of the call until we return.
 169 REGISTER_DECLARATION(Register, Llast_SP         , L5);
 170 REGISTER_DECLARATION(Register, Lscratch         , L5);
 171 REGISTER_DECLARATION(Register, Lscratch2        , L6);
 172 REGISTER_DECLARATION(Register, LcpoolCache      , L6); // constant pool cache
 173 
 174 REGISTER_DECLARATION(Register, O5_savedSP       , O5);
 175 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
 176                                                        // a copy SP, so in 64-bit it's a biased value.  The bias
 177                                                        // is added and removed as needed in the frame code.
 178 REGISTER_DECLARATION(Register, IdispatchTables  , I4); // Base address of the bytecode dispatch tables
 179 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
 180 REGISTER_DECLARATION(Register, ImethodDataPtr   , I2); // Pointer to the current method data
 181 #endif /* CC_INTERP */
 182 
 183 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
 184 //       the interpreter code. If Lscratch2 needs to be used for some
 185 //       purpose than LcpoolCache should be restore after that for
 186 //       the interpreter to work right
 187 // (These assignments must be compatible with L7_thread_cache; see above.)
 188 
 189 // Since Lbcp points into the middle of the method object,
 190 // it is temporarily converted into a "bcx" during GC.
 191 
 192 // Exception processing
 193 // These registers are passed into exception handlers.
 194 // All exception handlers require the exception object being thrown.
 195 // In addition, an nmethod's exception handler must be passed
 196 // the address of the call site within the nmethod, to allow
 197 // proper selection of the applicable catch block.
 198 // (Interpreter frames use their own bcp() for this purpose.)
 199 //
 200 // The Oissuing_pc value is not always needed.  When jumping to a
 201 // handler that is known to be interpreted, the Oissuing_pc value can be
 202 // omitted.  An actual catch block in compiled code receives (from its
 203 // nmethod's exception handler) the thrown exception in the Oexception,
 204 // but it doesn't need the Oissuing_pc.
 205 //
 206 // If an exception handler (either interpreted or compiled)
 207 // discovers there is no applicable catch block, it updates
 208 // the Oissuing_pc to the continuation PC of its own caller,
 209 // pops back to that caller's stack frame, and executes that
 210 // caller's exception handler.  Obviously, this process will
 211 // iterate until the control stack is popped back to a method
 212 // containing an applicable catch block.  A key invariant is
 213 // that the Oissuing_pc value is always a value local to
 214 // the method whose exception handler is currently executing.
 215 //
 216 // Note:  The issuing PC value is __not__ a raw return address (I7 value).
 217 // It is a "return pc", the address __following__ the call.
 218 // Raw return addresses are converted to issuing PCs by frame::pc(),
 219 // or by stubs.  Issuing PCs can be used directly with PC range tables.
 220 //
 221 REGISTER_DECLARATION(Register, Oexception  , O0); // exception being thrown
 222 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
 223 
 224 
 225 // These must occur after the declarations above
 226 #ifndef DONT_USE_REGISTER_DEFINES
 227 
 228 #define Gthread             AS_REGISTER(Register, Gthread)
 229 #define Gmethod             AS_REGISTER(Register, Gmethod)
 230 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
 231 #define Ginline_cache_reg   AS_REGISTER(Register, Ginline_cache_reg)
 232 #define Gargs               AS_REGISTER(Register, Gargs)
 233 #define Lthread_cache       AS_REGISTER(Register, Lthread_cache)
 234 #define Gframe_size         AS_REGISTER(Register, Gframe_size)
 235 #define Gtemp               AS_REGISTER(Register, Gtemp)
 236 
 237 #ifdef CC_INTERP
 238 #define Lstate              AS_REGISTER(Register, Lstate)
 239 #define Lesp                AS_REGISTER(Register, Lesp)
 240 #define L1_scratch          AS_REGISTER(Register, L1_scratch)
 241 #define Lmirror             AS_REGISTER(Register, Lmirror)
 242 #define L2_scratch          AS_REGISTER(Register, L2_scratch)
 243 #define L3_scratch          AS_REGISTER(Register, L3_scratch)
 244 #define L4_scratch          AS_REGISTER(Register, L4_scratch)
 245 #define Lscratch            AS_REGISTER(Register, Lscratch)
 246 #define Lscratch2           AS_REGISTER(Register, Lscratch2)
 247 #define L7_scratch          AS_REGISTER(Register, L7_scratch)
 248 #define Ostate              AS_REGISTER(Register, Ostate)
 249 #else
 250 #define Lesp                AS_REGISTER(Register, Lesp)
 251 #define Lbcp                AS_REGISTER(Register, Lbcp)
 252 #define Lmethod             AS_REGISTER(Register, Lmethod)
 253 #define Llocals             AS_REGISTER(Register, Llocals)
 254 #define Lmonitors           AS_REGISTER(Register, Lmonitors)
 255 #define Lbyte_code          AS_REGISTER(Register, Lbyte_code)
 256 #define Lscratch            AS_REGISTER(Register, Lscratch)
 257 #define Lscratch2           AS_REGISTER(Register, Lscratch2)
 258 #define LcpoolCache         AS_REGISTER(Register, LcpoolCache)
 259 #endif /* ! CC_INTERP */
 260 
 261 #define Lentry_args         AS_REGISTER(Register, Lentry_args)
 262 #define I5_savedSP          AS_REGISTER(Register, I5_savedSP)
 263 #define O5_savedSP          AS_REGISTER(Register, O5_savedSP)
 264 #define IdispatchAddress    AS_REGISTER(Register, IdispatchAddress)
 265 #define ImethodDataPtr      AS_REGISTER(Register, ImethodDataPtr)
 266 #define IdispatchTables     AS_REGISTER(Register, IdispatchTables)
 267 
 268 #define Oexception          AS_REGISTER(Register, Oexception)
 269 #define Oissuing_pc         AS_REGISTER(Register, Oissuing_pc)
 270 
 271 
 272 #endif
 273 
 274 // Address is an abstraction used to represent a memory location.
 275 //
 276 // Note: A register location is represented via a Register, not
 277 //       via an address for efficiency & simplicity reasons.
 278 
 279 class Address VALUE_OBJ_CLASS_SPEC {
 280  private:
 281   Register           _base;           // Base register.
 282   RegisterOrConstant _index_or_disp;  // Index register or constant displacement.
 283   RelocationHolder   _rspec;
 284 
 285  public:
 286   Address() : _base(noreg), _index_or_disp(noreg) {}
 287 
 288   Address(Register base, RegisterOrConstant index_or_disp)
 289     : _base(base),
 290       _index_or_disp(index_or_disp) {
 291   }
 292 
 293   Address(Register base, Register index)
 294     : _base(base),
 295       _index_or_disp(index) {
 296   }
 297 
 298   Address(Register base, int disp)
 299     : _base(base),
 300       _index_or_disp(disp) {
 301   }
 302 
 303 #ifdef ASSERT
 304   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 305   Address(Register base, ByteSize disp)
 306     : _base(base),
 307       _index_or_disp(in_bytes(disp)) {
 308   }
 309 #endif
 310 
 311   // accessors
 312   Register base()             const { return _base; }
 313   Register index()            const { return _index_or_disp.as_register(); }
 314   int      disp()             const { return _index_or_disp.as_constant(); }
 315 
 316   bool     has_index()        const { return _index_or_disp.is_register(); }
 317   bool     has_disp()         const { return _index_or_disp.is_constant(); }
 318 
 319   bool     uses(Register reg) const { return base() == reg || (has_index() && index() == reg); }
 320 
 321   const relocInfo::relocType rtype() { return _rspec.type(); }
 322   const RelocationHolder&    rspec() { return _rspec; }
 323 
 324   RelocationHolder rspec(int offset) const {
 325     return offset == 0 ? _rspec : _rspec.plus(offset);
 326   }
 327 
 328   inline bool is_simm13(int offset = 0);  // check disp+offset for overflow
 329 
 330   Address plus_disp(int plusdisp) const {     // bump disp by a small amount
 331     assert(_index_or_disp.is_constant(), "must have a displacement");
 332     Address a(base(), disp() + plusdisp);
 333     return a;
 334   }
 335   bool is_same_address(Address a) const {
 336     // disregard _rspec
 337     return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp());
 338   }
 339 
 340   Address after_save() const {
 341     Address a = (*this);
 342     a._base = a._base->after_save();
 343     return a;
 344   }
 345 
 346   Address after_restore() const {
 347     Address a = (*this);
 348     a._base = a._base->after_restore();
 349     return a;
 350   }
 351 
 352   // Convert the raw encoding form into the form expected by the
 353   // constructor for Address.
 354   static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
 355 
 356   friend class Assembler;
 357 };
 358 
 359 
 360 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
 361  private:
 362   address          _address;
 363   RelocationHolder _rspec;
 364 
 365   RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
 366     switch (rtype) {
 367     case relocInfo::external_word_type:
 368       return external_word_Relocation::spec(addr);
 369     case relocInfo::internal_word_type:
 370       return internal_word_Relocation::spec(addr);
 371 #ifdef _LP64
 372     case relocInfo::opt_virtual_call_type:
 373       return opt_virtual_call_Relocation::spec();
 374     case relocInfo::static_call_type:
 375       return static_call_Relocation::spec();
 376     case relocInfo::runtime_call_type:
 377       return runtime_call_Relocation::spec();
 378 #endif
 379     case relocInfo::none:
 380       return RelocationHolder();
 381     default:
 382       ShouldNotReachHere();
 383       return RelocationHolder();
 384     }
 385   }
 386 
 387  protected:
 388   // creation
 389   AddressLiteral() : _address(NULL), _rspec(NULL) {}
 390 
 391  public:
 392   AddressLiteral(address addr, RelocationHolder const& rspec)
 393     : _address(addr),
 394       _rspec(rspec) {}
 395 
 396   // Some constructors to avoid casting at the call site.
 397   AddressLiteral(jobject obj, RelocationHolder const& rspec)
 398     : _address((address) obj),
 399       _rspec(rspec) {}
 400 
 401   AddressLiteral(intptr_t value, RelocationHolder const& rspec)
 402     : _address((address) value),
 403       _rspec(rspec) {}
 404 
 405   AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
 406     : _address((address) addr),
 407     _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 408 
 409   // Some constructors to avoid casting at the call site.
 410   AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
 411     : _address((address) addr),
 412     _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 413 
 414   AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
 415     : _address((address) addr),
 416       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 417 
 418   AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
 419     : _address((address) addr),
 420       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 421 
 422   AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
 423     : _address((address) addr),
 424       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 425 
 426   AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
 427     : _address((address) addr),
 428       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 429 
 430   AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
 431     : _address((address) addr),
 432       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 433 
 434 #ifdef _LP64
 435   // 32-bit complains about a multiple declaration for int*.
 436   AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
 437     : _address((address) addr),
 438       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 439 #endif
 440 
 441   AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none)
 442     : _address((address) addr),
 443       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 444 
 445   AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
 446     : _address((address) addr),
 447       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 448 
 449   AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
 450     : _address((address) addr),
 451       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 452 
 453   AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
 454     : _address((address) addr),
 455       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 456 
 457   intptr_t value() const { return (intptr_t) _address; }
 458   int      low10() const;
 459 
 460   const relocInfo::relocType rtype() const { return _rspec.type(); }
 461   const RelocationHolder&    rspec() const { return _rspec; }
 462 
 463   RelocationHolder rspec(int offset) const {
 464     return offset == 0 ? _rspec : _rspec.plus(offset);
 465   }
 466 };
 467 
 468 // Convenience classes
 469 class ExternalAddress: public AddressLiteral {
 470  private:
 471   static relocInfo::relocType reloc_for_target(address target) {
 472     // Sometimes ExternalAddress is used for values which aren't
 473     // exactly addresses, like the card table base.
 474     // external_word_type can't be used for values in the first page
 475     // so just skip the reloc in that case.
 476     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 477   }
 478 
 479  public:
 480   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(          target)) {}
 481   ExternalAddress(oop*    target) : AddressLiteral(target, reloc_for_target((address) target)) {}
 482 };
 483 
 484 inline Address RegisterImpl::address_in_saved_window() const {
 485    return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
 486 }
 487 
 488 
 489 
 490 // Argument is an abstraction used to represent an outgoing
 491 // actual argument or an incoming formal parameter, whether
 492 // it resides in memory or in a register, in a manner consistent
 493 // with the SPARC Application Binary Interface, or ABI.  This is
 494 // often referred to as the native or C calling convention.
 495 
 496 class Argument VALUE_OBJ_CLASS_SPEC {
 497  private:
 498   int _number;
 499   bool _is_in;
 500 
 501  public:
 502 #ifdef _LP64
 503   enum {
 504     n_register_parameters = 6,          // only 6 registers may contain integer parameters
 505     n_float_register_parameters = 16    // Can have up to 16 floating registers
 506   };
 507 #else
 508   enum {
 509     n_register_parameters = 6           // only 6 registers may contain integer parameters
 510   };
 511 #endif
 512 
 513   // creation
 514   Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
 515 
 516   int  number() const  { return _number;  }
 517   bool is_in()  const  { return _is_in;   }
 518   bool is_out() const  { return !is_in(); }
 519 
 520   Argument successor() const  { return Argument(number() + 1, is_in()); }
 521   Argument as_in()     const  { return Argument(number(), true ); }
 522   Argument as_out()    const  { return Argument(number(), false); }
 523 
 524   // locating register-based arguments:
 525   bool is_register() const { return _number < n_register_parameters; }
 526 
 527 #ifdef _LP64
 528   // locating Floating Point register-based arguments:
 529   bool is_float_register() const { return _number < n_float_register_parameters; }
 530 
 531   FloatRegister as_float_register() const {
 532     assert(is_float_register(), "must be a register argument");
 533     return as_FloatRegister(( number() *2 ) + 1);
 534   }
 535   FloatRegister as_double_register() const {
 536     assert(is_float_register(), "must be a register argument");
 537     return as_FloatRegister(( number() *2 ));
 538   }
 539 #endif
 540 
 541   Register as_register() const {
 542     assert(is_register(), "must be a register argument");
 543     return is_in() ? as_iRegister(number()) : as_oRegister(number());
 544   }
 545 
 546   // locating memory-based arguments
 547   Address as_address() const {
 548     assert(!is_register(), "must be a memory argument");
 549     return address_in_frame();
 550   }
 551 
 552   // When applied to a register-based argument, give the corresponding address
 553   // into the 6-word area "into which callee may store register arguments"
 554   // (This is a different place than the corresponding register-save area location.)
 555   Address address_in_frame() const;
 556 
 557   // debugging
 558   const char* name() const;
 559 
 560   friend class Assembler;
 561 };
 562 
 563 
 564 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
 565 // level; i.e., what you write
 566 // is what you get. The Assembler is generating code into a CodeBuffer.
 567 
 568 class Assembler : public AbstractAssembler  {
 569  protected:
 570 
 571   static void print_instruction(int inst);
 572   static int  patched_branch(int dest_pos, int inst, int inst_pos);
 573   static int  branch_destination(int inst, int pos);
 574 
 575 
 576   friend class AbstractAssembler;
 577   friend class AddressLiteral;
 578 
 579   // code patchers need various routines like inv_wdisp()
 580   friend class NativeInstruction;
 581   friend class NativeGeneralJump;
 582   friend class Relocation;
 583   friend class Label;
 584 
 585  public:
 586   // op carries format info; see page 62 & 267
 587 
 588   enum ops {
 589     call_op   = 1, // fmt 1
 590     branch_op = 0, // also sethi (fmt2)
 591     arith_op  = 2, // fmt 3, arith & misc
 592     ldst_op   = 3  // fmt 3, load/store
 593   };
 594 
 595   enum op2s {
 596     bpr_op2   = 3,
 597     fb_op2    = 6,
 598     fbp_op2   = 5,
 599     br_op2    = 2,
 600     bp_op2    = 1,
 601     cb_op2    = 7, // V8
 602     sethi_op2 = 4
 603   };
 604 
 605   enum op3s {
 606     // selected op3s
 607     add_op3      = 0x00,
 608     and_op3      = 0x01,
 609     or_op3       = 0x02,
 610     xor_op3      = 0x03,
 611     sub_op3      = 0x04,
 612     andn_op3     = 0x05,
 613     orn_op3      = 0x06,
 614     xnor_op3     = 0x07,
 615     addc_op3     = 0x08,
 616     mulx_op3     = 0x09,
 617     umul_op3     = 0x0a,
 618     smul_op3     = 0x0b,
 619     subc_op3     = 0x0c,
 620     udivx_op3    = 0x0d,
 621     udiv_op3     = 0x0e,
 622     sdiv_op3     = 0x0f,
 623 
 624     addcc_op3    = 0x10,
 625     andcc_op3    = 0x11,
 626     orcc_op3     = 0x12,
 627     xorcc_op3    = 0x13,
 628     subcc_op3    = 0x14,
 629     andncc_op3   = 0x15,
 630     orncc_op3    = 0x16,
 631     xnorcc_op3   = 0x17,
 632     addccc_op3   = 0x18,
 633     umulcc_op3   = 0x1a,
 634     smulcc_op3   = 0x1b,
 635     subccc_op3   = 0x1c,
 636     udivcc_op3   = 0x1e,
 637     sdivcc_op3   = 0x1f,
 638 
 639     taddcc_op3   = 0x20,
 640     tsubcc_op3   = 0x21,
 641     taddcctv_op3 = 0x22,
 642     tsubcctv_op3 = 0x23,
 643     mulscc_op3   = 0x24,
 644     sll_op3      = 0x25,
 645     sllx_op3     = 0x25,
 646     srl_op3      = 0x26,
 647     srlx_op3     = 0x26,
 648     sra_op3      = 0x27,
 649     srax_op3     = 0x27,
 650     rdreg_op3    = 0x28,
 651     membar_op3   = 0x28,
 652 
 653     flushw_op3   = 0x2b,
 654     movcc_op3    = 0x2c,
 655     sdivx_op3    = 0x2d,
 656     popc_op3     = 0x2e,
 657     movr_op3     = 0x2f,
 658 
 659     sir_op3      = 0x30,
 660     wrreg_op3    = 0x30,
 661     saved_op3    = 0x31,
 662 
 663     fpop1_op3    = 0x34,
 664     fpop2_op3    = 0x35,
 665     impdep1_op3  = 0x36,
 666     impdep2_op3  = 0x37,
 667     jmpl_op3     = 0x38,
 668     rett_op3     = 0x39,
 669     trap_op3     = 0x3a,
 670     flush_op3    = 0x3b,
 671     save_op3     = 0x3c,
 672     restore_op3  = 0x3d,
 673     done_op3     = 0x3e,
 674     retry_op3    = 0x3e,
 675 
 676     lduw_op3     = 0x00,
 677     ldub_op3     = 0x01,
 678     lduh_op3     = 0x02,
 679     ldd_op3      = 0x03,
 680     stw_op3      = 0x04,
 681     stb_op3      = 0x05,
 682     sth_op3      = 0x06,
 683     std_op3      = 0x07,
 684     ldsw_op3     = 0x08,
 685     ldsb_op3     = 0x09,
 686     ldsh_op3     = 0x0a,
 687     ldx_op3      = 0x0b,
 688 
 689     ldstub_op3   = 0x0d,
 690     stx_op3      = 0x0e,
 691     swap_op3     = 0x0f,
 692 
 693     stwa_op3     = 0x14,
 694     stxa_op3     = 0x1e,
 695 
 696     ldf_op3      = 0x20,
 697     ldfsr_op3    = 0x21,
 698     ldqf_op3     = 0x22,
 699     lddf_op3     = 0x23,
 700     stf_op3      = 0x24,
 701     stfsr_op3    = 0x25,
 702     stqf_op3     = 0x26,
 703     stdf_op3     = 0x27,
 704 
 705     prefetch_op3 = 0x2d,
 706 
 707 
 708     ldc_op3      = 0x30,
 709     ldcsr_op3    = 0x31,
 710     lddc_op3     = 0x33,
 711     stc_op3      = 0x34,
 712     stcsr_op3    = 0x35,
 713     stdcq_op3    = 0x36,
 714     stdc_op3     = 0x37,
 715 
 716     casa_op3     = 0x3c,
 717     casxa_op3    = 0x3e,
 718 
 719     mftoi_op3    = 0x36,
 720 
 721     alt_bit_op3  = 0x10,
 722      cc_bit_op3  = 0x10
 723   };
 724 
 725   enum opfs {
 726     // selected opfs
 727     fmovs_opf   = 0x01,
 728     fmovd_opf   = 0x02,
 729 
 730     fnegs_opf   = 0x05,
 731     fnegd_opf   = 0x06,
 732 
 733     fadds_opf   = 0x41,
 734     faddd_opf   = 0x42,
 735     fsubs_opf   = 0x45,
 736     fsubd_opf   = 0x46,
 737 
 738     fmuls_opf   = 0x49,
 739     fmuld_opf   = 0x4a,
 740     fdivs_opf   = 0x4d,
 741     fdivd_opf   = 0x4e,
 742 
 743     fcmps_opf   = 0x51,
 744     fcmpd_opf   = 0x52,
 745 
 746     fstox_opf   = 0x81,
 747     fdtox_opf   = 0x82,
 748     fxtos_opf   = 0x84,
 749     fxtod_opf   = 0x88,
 750     fitos_opf   = 0xc4,
 751     fdtos_opf   = 0xc6,
 752     fitod_opf   = 0xc8,
 753     fstod_opf   = 0xc9,
 754     fstoi_opf   = 0xd1,
 755     fdtoi_opf   = 0xd2,
 756 
 757     mdtox_opf   = 0x110,
 758     mstouw_opf  = 0x111,
 759     mstosw_opf  = 0x113,
 760     mxtod_opf   = 0x118,
 761     mwtos_opf   = 0x119
 762   };
 763 
 764   enum RCondition {  rc_z = 1,  rc_lez = 2,  rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez  };
 765 
 766   enum Condition {
 767      // for FBfcc & FBPfcc instruction
 768     f_never                     = 0,
 769     f_notEqual                  = 1,
 770     f_notZero                   = 1,
 771     f_lessOrGreater             = 2,
 772     f_unorderedOrLess           = 3,
 773     f_less                      = 4,
 774     f_unorderedOrGreater        = 5,
 775     f_greater                   = 6,
 776     f_unordered                 = 7,
 777     f_always                    = 8,
 778     f_equal                     = 9,
 779     f_zero                      = 9,
 780     f_unorderedOrEqual          = 10,
 781     f_greaterOrEqual            = 11,
 782     f_unorderedOrGreaterOrEqual = 12,
 783     f_lessOrEqual               = 13,
 784     f_unorderedOrLessOrEqual    = 14,
 785     f_ordered                   = 15,
 786 
 787     // V8 coproc, pp 123 v8 manual
 788 
 789     cp_always  = 8,
 790     cp_never   = 0,
 791     cp_3       = 7,
 792     cp_2       = 6,
 793     cp_2or3    = 5,
 794     cp_1       = 4,
 795     cp_1or3    = 3,
 796     cp_1or2    = 2,
 797     cp_1or2or3 = 1,
 798     cp_0       = 9,
 799     cp_0or3    = 10,
 800     cp_0or2    = 11,
 801     cp_0or2or3 = 12,
 802     cp_0or1    = 13,
 803     cp_0or1or3 = 14,
 804     cp_0or1or2 = 15,
 805 
 806 
 807     // for integers
 808 
 809     never                 =  0,
 810     equal                 =  1,
 811     zero                  =  1,
 812     lessEqual             =  2,
 813     less                  =  3,
 814     lessEqualUnsigned     =  4,
 815     lessUnsigned          =  5,
 816     carrySet              =  5,
 817     negative              =  6,
 818     overflowSet           =  7,
 819     always                =  8,
 820     notEqual              =  9,
 821     notZero               =  9,
 822     greater               =  10,
 823     greaterEqual          =  11,
 824     greaterUnsigned       =  12,
 825     greaterEqualUnsigned  =  13,
 826     carryClear            =  13,
 827     positive              =  14,
 828     overflowClear         =  15
 829   };
 830 
 831   enum CC {
 832     icc  = 0,  xcc  = 2,
 833     // ptr_cc is the correct condition code for a pointer or intptr_t:
 834     ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
 835     fcc0 = 0,  fcc1 = 1, fcc2 = 2, fcc3 = 3
 836   };
 837 
 838   enum PrefetchFcn {
 839     severalReads = 0,  oneRead = 1,  severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
 840   };
 841 
 842  public:
 843   // Helper functions for groups of instructions
 844 
 845   enum Predict { pt = 1, pn = 0 }; // pt = predict taken
 846 
 847   enum Membar_mask_bits { // page 184, v9
 848     StoreStore = 1 << 3,
 849     LoadStore  = 1 << 2,
 850     StoreLoad  = 1 << 1,
 851     LoadLoad   = 1 << 0,
 852 
 853     Sync       = 1 << 6,
 854     MemIssue   = 1 << 5,
 855     Lookaside  = 1 << 4
 856   };
 857 
 858   // test if x is within signed immediate range for nbits
 859   static bool is_simm(intptr_t x, int nbits) { return -( intptr_t(1) << nbits-1 )  <= x   &&   x  <  ( intptr_t(1) << nbits-1 ); }
 860 
 861   // test if -4096 <= x <= 4095
 862   static bool is_simm13(intptr_t x) { return is_simm(x, 13); }
 863 
 864   static bool is_in_wdisp_range(address a, address b, int nbits) {
 865     intptr_t d = intptr_t(b) - intptr_t(a);
 866     return is_simm(d, nbits + 2);
 867   }
 868 
 869   address target_distance(Label& L) {
 870     // Assembler::target(L) should be called only when
 871     // a branch instruction is emitted since non-bound
 872     // labels record current pc() as a branch address.
 873     if (L.is_bound()) return target(L);
 874     // Return current address for non-bound labels.
 875     return pc();
 876   }
 877 
 878   // test if label is in simm16 range in words (wdisp16).
 879   bool is_in_wdisp16_range(Label& L) {
 880     return is_in_wdisp_range(target_distance(L), pc(), 16);
 881   }
 882   // test if the distance between two addresses fits in simm30 range in words
 883   static bool is_in_wdisp30_range(address a, address b) {
 884     return is_in_wdisp_range(a, b, 30);
 885   }
 886 
 887   enum ASIs { // page 72, v9
 888     ASI_PRIMARY        = 0x80,
 889     ASI_PRIMARY_LITTLE = 0x88
 890     // add more from book as needed
 891   };
 892 
 893  protected:
 894   // helpers
 895 
 896   // x is supposed to fit in a field "nbits" wide
 897   // and be sign-extended. Check the range.
 898 
 899   static void assert_signed_range(intptr_t x, int nbits) {
 900     assert(nbits == 32 || (-(1 << nbits-1) <= x  &&  x < ( 1 << nbits-1)),
 901            err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
 902   }
 903 
 904   static void assert_signed_word_disp_range(intptr_t x, int nbits) {
 905     assert( (x & 3) == 0, "not word aligned");
 906     assert_signed_range(x, nbits + 2);
 907   }
 908 
 909   static void assert_unsigned_const(int x, int nbits) {
 910     assert( juint(x)  <  juint(1 << nbits), "unsigned constant out of range");
 911   }
 912 
 913   // fields: note bits numbered from LSB = 0,
 914   //  fields known by inclusive bit range
 915 
 916   static int fmask(juint hi_bit, juint lo_bit) {
 917     assert( hi_bit >= lo_bit  &&  0 <= lo_bit  &&  hi_bit < 32, "bad bits");
 918     return (1 << ( hi_bit-lo_bit + 1 )) - 1;
 919   }
 920 
 921   // inverse of u_field
 922 
 923   static int inv_u_field(int x, int hi_bit, int lo_bit) {
 924     juint r = juint(x) >> lo_bit;
 925     r &= fmask( hi_bit, lo_bit);
 926     return int(r);
 927   }
 928 
 929 
 930   // signed version: extract from field and sign-extend
 931 
 932   static int inv_s_field(int x, int hi_bit, int lo_bit) {
 933     int sign_shift = 31 - hi_bit;
 934     return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
 935   }
 936 
 937   // given a field that ranges from hi_bit to lo_bit (inclusive,
 938   // LSB = 0), and an unsigned value for the field,
 939   // shift it into the field
 940 
 941 #ifdef ASSERT
 942   static int u_field(int x, int hi_bit, int lo_bit) {
 943     assert( ( x & ~fmask(hi_bit, lo_bit))  == 0,
 944             "value out of range");
 945     int r = x << lo_bit;
 946     assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
 947     return r;
 948   }
 949 #else
 950   // make sure this is inlined as it will reduce code size significantly
 951   #define u_field(x, hi_bit, lo_bit)   ((x) << (lo_bit))
 952 #endif
 953 
 954   static int inv_op(  int x ) { return inv_u_field(x, 31, 30); }
 955   static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
 956   static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
 957   static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
 958 
 959   static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
 960 
 961   static Register inv_rd(  int x ) { return as_Register(inv_u_field(x, 29, 25)); }
 962   static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
 963   static Register inv_rs2( int x ) { return as_Register(inv_u_field(x,  4,  0)); }
 964 
 965   static int op(       int         x)  { return  u_field(x,             31, 30); }
 966   static int rd(       Register    r)  { return  u_field(r->encoding(), 29, 25); }
 967   static int fcn(      int         x)  { return  u_field(x,             29, 25); }
 968   static int op3(      int         x)  { return  u_field(x,             24, 19); }
 969   static int rs1(      Register    r)  { return  u_field(r->encoding(), 18, 14); }
 970   static int rs2(      Register    r)  { return  u_field(r->encoding(),  4,  0); }
 971   static int annul(    bool        a)  { return  u_field(a ? 1 : 0,     29, 29); }
 972   static int cond(     int         x)  { return  u_field(x,             28, 25); }
 973   static int cond_mov( int         x)  { return  u_field(x,             17, 14); }
 974   static int rcond(    RCondition  x)  { return  u_field(x,             12, 10); }
 975   static int op2(      int         x)  { return  u_field(x,             24, 22); }
 976   static int predict(  bool        p)  { return  u_field(p ? 1 : 0,     19, 19); }
 977   static int branchcc( CC       fcca)  { return  u_field(fcca,          21, 20); }
 978   static int cmpcc(    CC       fcca)  { return  u_field(fcca,          26, 25); }
 979   static int imm_asi(  int         x)  { return  u_field(x,             12,  5); }
 980   static int immed(    bool        i)  { return  u_field(i ? 1 : 0,     13, 13); }
 981   static int opf_low6( int         w)  { return  u_field(w,             10,  5); }
 982   static int opf_low5( int         w)  { return  u_field(w,              9,  5); }
 983   static int trapcc(   CC         cc)  { return  u_field(cc,            12, 11); }
 984   static int sx(       int         i)  { return  u_field(i,             12, 12); } // shift x=1 means 64-bit
 985   static int opf(      int         x)  { return  u_field(x,             13,  5); }
 986 
 987   static bool is_cbcond( int x ) {
 988     return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
 989             inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
 990   }
 991   static bool is_cxb( int x ) {
 992     assert(is_cbcond(x), "wrong instruction");
 993     return (x & (1<<21)) != 0;
 994   }
 995   static int cond_cbcond( int         x)  { return  u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
 996   static int inv_cond_cbcond(int      x)  {
 997     assert(is_cbcond(x), "wrong instruction");
 998     return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
 999   }
1000 
1001   static int opf_cc(   CC          c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
1002   static int mov_cc(   CC          c, bool useFloat ) { return u_field(useFloat ? 0 : 1,  18, 18) | u_field(c, 12, 11); }
1003 
1004   static int fd( FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
1005   static int fs1(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
1006   static int fs2(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa),  4,  0); };
1007 
1008   // some float instructions use this encoding on the op3 field
1009   static int alt_op3(int op, FloatRegisterImpl::Width w) {
1010     int r;
1011     switch(w) {
1012      case FloatRegisterImpl::S: r = op + 0;  break;
1013      case FloatRegisterImpl::D: r = op + 3;  break;
1014      case FloatRegisterImpl::Q: r = op + 2;  break;
1015      default: ShouldNotReachHere(); break;
1016     }
1017     return op3(r);
1018   }
1019 
1020 
1021   // compute inverse of simm
1022   static int inv_simm(int x, int nbits) {
1023     return (int)(x << (32 - nbits)) >> (32 - nbits);
1024   }
1025 
1026   static int inv_simm13( int x ) { return inv_simm(x, 13); }
1027 
1028   // signed immediate, in low bits, nbits long
1029   static int simm(int x, int nbits) {
1030     assert_signed_range(x, nbits);
1031     return x  &  (( 1 << nbits ) - 1);
1032   }
1033 
1034   // compute inverse of wdisp16
1035   static intptr_t inv_wdisp16(int x, intptr_t pos) {
1036     int lo = x & (( 1 << 14 ) - 1);
1037     int hi = (x >> 20) & 3;
1038     if (hi >= 2) hi |= ~1;
1039     return (((hi << 14) | lo) << 2) + pos;
1040   }
1041 
1042   // word offset, 14 bits at LSend, 2 bits at B21, B20
1043   static int wdisp16(intptr_t x, intptr_t off) {
1044     intptr_t xx = x - off;
1045     assert_signed_word_disp_range(xx, 16);
1046     int r =  (xx >> 2) & ((1 << 14) - 1)
1047            |  (  ( (xx>>(2+14)) & 3 )  <<  20 );
1048     assert( inv_wdisp16(r, off) == x,  "inverse is not inverse");
1049     return r;
1050   }
1051 
1052   // compute inverse of wdisp10
1053   static intptr_t inv_wdisp10(int x, intptr_t pos) {
1054     assert(is_cbcond(x), "wrong instruction");
1055     int lo = inv_u_field(x, 12, 5);
1056     int hi = (x >> 19) & 3;
1057     if (hi >= 2) hi |= ~1;
1058     return (((hi << 8) | lo) << 2) + pos;
1059   }
1060 
1061   // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
1062   static int wdisp10(intptr_t x, intptr_t off) {
1063     assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
1064     intptr_t xx = x - off;
1065     assert_signed_word_disp_range(xx, 10);
1066     int r =  ( ( (xx >>  2   ) & ((1 << 8) - 1) ) <<  5 )
1067            | ( ( (xx >> (2+8)) & 3              ) << 19 );
1068     // Have to fake cbcond instruction to pass assert in inv_wdisp10()
1069     assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x,  "inverse is not inverse");
1070     return r;
1071   }
1072 
1073   // word displacement in low-order nbits bits
1074 
1075   static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
1076     int pre_sign_extend = x & (( 1 << nbits ) - 1);
1077     int r =  pre_sign_extend >= ( 1 << (nbits-1) )
1078        ?   pre_sign_extend | ~(( 1 << nbits ) - 1)
1079        :   pre_sign_extend;
1080     return (r << 2) + pos;
1081   }
1082 
1083   static int wdisp( intptr_t x, intptr_t off, int nbits ) {
1084     intptr_t xx = x - off;
1085     assert_signed_word_disp_range(xx, nbits);
1086     int r =  (xx >> 2) & (( 1 << nbits ) - 1);
1087     assert( inv_wdisp( r, off, nbits )  ==  x, "inverse not inverse");
1088     return r;
1089   }
1090 
1091 
1092   // Extract the top 32 bits in a 64 bit word
1093   static int32_t hi32( int64_t x ) {
1094     int32_t r = int32_t( (uint64_t)x >> 32 );
1095     return r;
1096   }
1097 
1098   // given a sethi instruction, extract the constant, left-justified
1099   static int inv_hi22( int x ) {
1100     return x << 10;
1101   }
1102 
1103   // create an imm22 field, given a 32-bit left-justified constant
1104   static int hi22( int x ) {
1105     int r = int( juint(x) >> 10 );
1106     assert( (r & ~((1 << 22) - 1))  ==  0, "just checkin'");
1107     return r;
1108   }
1109 
1110   // create a low10 __value__ (not a field) for a given a 32-bit constant
1111   static int low10( int x ) {
1112     return x & ((1 << 10) - 1);
1113   }
1114 
1115   // instruction only in VIS3
1116   static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
1117 
1118   // instruction only in v9
1119   static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
1120 
1121   // instruction only in v8
1122   static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
1123 
1124   // instruction deprecated in v9
1125   static void v9_dep()  { } // do nothing for now
1126 
1127   // some float instructions only exist for single prec. on v8
1128   static void v8_s_only(FloatRegisterImpl::Width w)  { if (w != FloatRegisterImpl::S)  v9_only(); }
1129 
1130   // v8 has no CC field
1131   static void v8_no_cc(CC cc)  { if (cc)  v9_only(); }
1132 
1133  protected:
1134   // Simple delay-slot scheme:
1135   // In order to check the programmer, the assembler keeps track of deley slots.
1136   // It forbids CTIs in delay slots (conservative, but should be OK).
1137   // Also, when putting an instruction into a delay slot, you must say
1138   // asm->delayed()->add(...), in order to check that you don't omit
1139   // delay-slot instructions.
1140   // To implement this, we use a simple FSA
1141 
1142 #ifdef ASSERT
1143   #define CHECK_DELAY
1144 #endif
1145 #ifdef CHECK_DELAY
1146   enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
1147 #endif
1148 
1149  public:
1150   // Tells assembler next instruction must NOT be in delay slot.
1151   // Use at start of multinstruction macros.
1152   void assert_not_delayed() {
1153     // This is a separate overloading to avoid creation of string constants
1154     // in non-asserted code--with some compilers this pollutes the object code.
1155 #ifdef CHECK_DELAY
1156     assert_not_delayed("next instruction should not be a delay slot");
1157 #endif
1158   }
1159   void assert_not_delayed(const char* msg) {
1160 #ifdef CHECK_DELAY
1161     assert(delay_state == no_delay, msg);
1162 #endif
1163   }
1164 
1165  protected:
1166   // Delay slot helpers
1167   // cti is called when emitting control-transfer instruction,
1168   // BEFORE doing the emitting.
1169   // Only effective when assertion-checking is enabled.
1170   void cti() {
1171 #ifdef CHECK_DELAY
1172     assert_not_delayed("cti should not be in delay slot");
1173 #endif
1174   }
1175 
1176   // called when emitting cti with a delay slot, AFTER emitting
1177   void has_delay_slot() {
1178 #ifdef CHECK_DELAY
1179     assert_not_delayed("just checking");
1180     delay_state = at_delay_slot;
1181 #endif
1182   }
1183 
1184   // cbcond instruction should not be generated one after an other
1185   bool cbcond_before() {
1186     if (offset() == 0) return false; // it is first instruction
1187     int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
1188     return is_cbcond(x);
1189   }
1190 
1191   void no_cbcond_before() {
1192     assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
1193   }
1194 
1195   bool use_cbcond(Label& L) {
1196     if (!UseCBCond || cbcond_before()) return false;
1197     intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
1198     assert( (x & 3) == 0, "not word aligned");
1199     return is_simm(x, 12);
1200   }
1201 
1202 public:
1203   // Tells assembler you know that next instruction is delayed
1204   Assembler* delayed() {
1205 #ifdef CHECK_DELAY
1206     assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
1207     delay_state = filling_delay_slot;
1208 #endif
1209     return this;
1210   }
1211 
1212   void flush() {
1213 #ifdef CHECK_DELAY
1214     assert ( delay_state == no_delay, "ending code with a delay slot");
1215 #endif
1216     AbstractAssembler::flush();
1217   }
1218 
1219   inline void emit_long(int);  // shadows AbstractAssembler::emit_long
1220   inline void emit_data(int x) { emit_long(x); }
1221   inline void emit_data(int, RelocationHolder const&);
1222   inline void emit_data(int, relocInfo::relocType rtype);
1223   // helper for above fcns
1224   inline void check_delay();
1225 
1226 
1227  public:
1228   // instructions, refer to page numbers in the SPARC Architecture Manual, V9
1229 
1230   // pp 135 (addc was addx in v8)
1231 
1232   inline void add(Register s1, Register s2, Register d );
1233   inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1234   inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1235   inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1236   inline void add(const Address& a, Register d, int offset = 0);
1237 
1238   void addcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1239   void addcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1240   void addc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | rs2(s2) ); }
1241   void addc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1242   void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1243   void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1244 
1245 
1246   // pp 136
1247 
1248   inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
1249   inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
1250 
1251  protected: // use MacroAssembler::br instead
1252 
1253   // pp 138
1254 
1255   inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1256   inline void fb( Condition c, bool a, Label& L );
1257 
1258   // pp 141
1259 
1260   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1261   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1262 
1263   // pp 144
1264 
1265   inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1266   inline void br( Condition c, bool a, Label& L );
1267 
1268   // pp 146
1269 
1270   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1271   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1272 
1273   // pp 121 (V8)
1274 
1275   inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1276   inline void cb( Condition c, bool a, Label& L );
1277 
1278   // compare and branch
1279   inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
1280   inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
1281 
1282   // pp 149
1283 
1284   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
1285   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
1286 
1287  public:
1288 
1289   // pp 150
1290 
1291   // These instructions compare the contents of s2 with the contents of
1292   // memory at address in s1. If the values are equal, the contents of memory
1293   // at address s1 is swapped with the data in d. If the values are not equal,
1294   // the the contents of memory at s1 is loaded into d, without the swap.
1295 
1296   void casa(  Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1297   void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1298 
1299   // pp 152
1300 
1301   void udiv(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | rs2(s2)); }
1302   void udiv(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1303   void sdiv(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | rs2(s2)); }
1304   void sdiv(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1305   void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1306   void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1307   void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1308   void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1309 
1310   // pp 155
1311 
1312   void done()  { v9_only();  cti();  emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); }
1313   void retry() { v9_only();  cti();  emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); }
1314 
1315   // pp 156
1316 
1317   void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
1318   void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
1319 
1320   // pp 157
1321 
1322   void fcmp(  FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
1323   void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
1324 
1325   // pp 159
1326 
1327   void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
1328   void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_long( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
1329 
1330   // pp 160
1331 
1332   void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
1333 
1334   // pp 161
1335 
1336   void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
1337   void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
1338 
1339   // pp 162
1340 
1341   void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
1342 
1343   void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
1344 
1345   // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
1346   // on v8 to do negation of single, double and quad precision floats.
1347 
1348   void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) |  opf(0x05) | fs2(sd, w)); }
1349 
1350   void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
1351 
1352   // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
1353   // on v8 to do abs operation on single/double/quad precision floats.
1354 
1355   void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
1356 
1357   // pp 163
1358 
1359   void fmul( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x48 + w)         | fs2(s2, w)); }
1360   void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw,  FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
1361   void fdiv( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x4c + w)         | fs2(s2, w)); }
1362 
1363   // pp 164
1364 
1365   void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
1366 
1367   // pp 165
1368 
1369   inline void flush( Register s1, Register s2 );
1370   inline void flush( Register s1, int simm13a);
1371 
1372   // pp 167
1373 
1374   void flushw() { v9_only();  emit_long( op(arith_op) | op3(flushw_op3) ); }
1375 
1376   // pp 168
1377 
1378   void illtrap( int const22a) { if (const22a != 0) v9_only();  emit_long( op(branch_op) | u_field(const22a, 21, 0) ); }
1379   // v8 unimp == illtrap(0)
1380 
1381   // pp 169
1382 
1383   void impdep1( int id1, int const19a ) { v9_only();  emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
1384   void impdep2( int id1, int const19a ) { v9_only();  emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
1385 
1386   // pp 149 (v8)
1387 
1388   void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only();  emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1389   void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only();  emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1390 
1391   // pp 170
1392 
1393   void jmpl( Register s1, Register s2, Register d );
1394   void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1395 
1396   // 171
1397 
1398   inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
1399   inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
1400   inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
1401 
1402   inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
1403 
1404 
1405   inline void ldfsr(  Register s1, Register s2 );
1406   inline void ldfsr(  Register s1, int simm13a);
1407   inline void ldxfsr( Register s1, Register s2 );
1408   inline void ldxfsr( Register s1, int simm13a);
1409 
1410   // pp 94 (v8)
1411 
1412   inline void ldc(   Register s1, Register s2, int crd );
1413   inline void ldc(   Register s1, int simm13a, int crd);
1414   inline void lddc(  Register s1, Register s2, int crd );
1415   inline void lddc(  Register s1, int simm13a, int crd);
1416   inline void ldcsr( Register s1, Register s2, int crd );
1417   inline void ldcsr( Register s1, int simm13a, int crd);
1418 
1419 
1420   // 173
1421 
1422   void ldfa(  FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1423   void ldfa(  FloatRegisterImpl::Width w, Register s1, int simm13a,         FloatRegister d ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1424 
1425   // pp 175, lduw is ld on v8
1426 
1427   inline void ldsb(  Register s1, Register s2, Register d );
1428   inline void ldsb(  Register s1, int simm13a, Register d);
1429   inline void ldsh(  Register s1, Register s2, Register d );
1430   inline void ldsh(  Register s1, int simm13a, Register d);
1431   inline void ldsw(  Register s1, Register s2, Register d );
1432   inline void ldsw(  Register s1, int simm13a, Register d);
1433   inline void ldub(  Register s1, Register s2, Register d );
1434   inline void ldub(  Register s1, int simm13a, Register d);
1435   inline void lduh(  Register s1, Register s2, Register d );
1436   inline void lduh(  Register s1, int simm13a, Register d);
1437   inline void lduw(  Register s1, Register s2, Register d );
1438   inline void lduw(  Register s1, int simm13a, Register d);
1439   inline void ldx(   Register s1, Register s2, Register d );
1440   inline void ldx(   Register s1, int simm13a, Register d);
1441   inline void ld(    Register s1, Register s2, Register d );
1442   inline void ld(    Register s1, int simm13a, Register d);
1443   inline void ldd(   Register s1, Register s2, Register d );
1444   inline void ldd(   Register s1, int simm13a, Register d);
1445 
1446 #ifdef ASSERT
1447   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
1448   inline void ld(    Register s1, ByteSize simm13a, Register d);
1449 #endif
1450 
1451   inline void ldsb(const Address& a, Register d, int offset = 0);
1452   inline void ldsh(const Address& a, Register d, int offset = 0);
1453   inline void ldsw(const Address& a, Register d, int offset = 0);
1454   inline void ldub(const Address& a, Register d, int offset = 0);
1455   inline void lduh(const Address& a, Register d, int offset = 0);
1456   inline void lduw(const Address& a, Register d, int offset = 0);
1457   inline void ldx( const Address& a, Register d, int offset = 0);
1458   inline void ld(  const Address& a, Register d, int offset = 0);
1459   inline void ldd( const Address& a, Register d, int offset = 0);
1460 
1461   inline void ldub(  Register s1, RegisterOrConstant s2, Register d );
1462   inline void ldsb(  Register s1, RegisterOrConstant s2, Register d );
1463   inline void lduh(  Register s1, RegisterOrConstant s2, Register d );
1464   inline void ldsh(  Register s1, RegisterOrConstant s2, Register d );
1465   inline void lduw(  Register s1, RegisterOrConstant s2, Register d );
1466   inline void ldsw(  Register s1, RegisterOrConstant s2, Register d );
1467   inline void ldx(   Register s1, RegisterOrConstant s2, Register d );
1468   inline void ld(    Register s1, RegisterOrConstant s2, Register d );
1469   inline void ldd(   Register s1, RegisterOrConstant s2, Register d );
1470 
1471   // pp 177
1472 
1473   void ldsba(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1474   void ldsba(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1475   void ldsha(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1476   void ldsha(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1477   void ldswa(  Register s1, Register s2, int ia, Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1478   void ldswa(  Register s1, int simm13a,         Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1479   void lduba(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1480   void lduba(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1481   void lduha(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1482   void lduha(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1483   void lduwa(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1484   void lduwa(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1485   void ldxa(   Register s1, Register s2, int ia, Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1486   void ldxa(   Register s1, int simm13a,         Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1487   void ldda(   Register s1, Register s2, int ia, Register d ) { v9_dep();   emit_long( op(ldst_op) | rd(d) | op3(ldd_op3  | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1488   void ldda(   Register s1, int simm13a,         Register d ) { v9_dep();   emit_long( op(ldst_op) | rd(d) | op3(ldd_op3  | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1489 
1490   // pp 179
1491 
1492   inline void ldstub(  Register s1, Register s2, Register d );
1493   inline void ldstub(  Register s1, int simm13a, Register d);
1494 
1495   // pp 180
1496 
1497   void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1498   void ldstuba( Register s1, int simm13a,         Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1499 
1500   // pp 181
1501 
1502   void and3(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | rs2(s2) ); }
1503   void and3(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1504   void andcc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1505   void andcc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1506   void andn(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | rs2(s2) ); }
1507   void andn(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1508   void andn(    Register s1, RegisterOrConstant s2, Register d);
1509   void andncc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1510   void andncc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1511   void or3(     Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | rs2(s2) ); }
1512   void or3(     Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1513   void orcc(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1514   void orcc(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1515   void orn(     Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
1516   void orn(     Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1517   void orncc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1518   void orncc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1519   void xor3(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | rs2(s2) ); }
1520   void xor3(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1521   void xorcc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1522   void xorcc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1523   void xnor(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3             ) | rs1(s1) | rs2(s2) ); }
1524   void xnor(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1525   void xnorcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1526   void xnorcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1527 
1528   // pp 183
1529 
1530   void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
1531 
1532   // pp 185
1533 
1534   void fmov( FloatRegisterImpl::Width w, Condition c,  bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
1535 
1536   // pp 189
1537 
1538   void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1,  FloatRegister s2, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
1539 
1540   // pp 191
1541 
1542   void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
1543   void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
1544 
1545   // pp 195
1546 
1547   void movr( RCondition c, Register s1, Register s2,  Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
1548   void movr( RCondition c, Register s1, int simm10a,  Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
1549 
1550   // pp 196
1551 
1552   void mulx(  Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
1553   void mulx(  Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1554   void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
1555   void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1556   void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
1557   void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1558 
1559   // pp 197
1560 
1561   void umul(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | rs2(s2) ); }
1562   void umul(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1563   void smul(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | rs2(s2) ); }
1564   void smul(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1565   void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1566   void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1567   void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1568   void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1569 
1570   // pp 199
1571 
1572   void mulscc(   Register s1, Register s2, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
1573   void mulscc(   Register s1, int simm13a, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1574 
1575   // pp 201
1576 
1577   void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); }
1578 
1579 
1580   // pp 202
1581 
1582   void popc( Register s,  Register d) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1583   void popc( int simm13a, Register d) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1584 
1585   // pp 203
1586 
1587   void prefetch(   Register s1, Register s2,         PrefetchFcn f);
1588   void prefetch(   Register s1, int simm13a,         PrefetchFcn f);
1589   void prefetcha(  Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only();  emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1590   void prefetcha(  Register s1, int simm13a,         PrefetchFcn f ) { v9_only();  emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1591 
1592   inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
1593 
1594   // pp 208
1595 
1596   // not implementing read privileged register
1597 
1598   inline void rdy(    Register d) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1599   inline void rdccr(  Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1600   inline void rdasi(  Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
1601   inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
1602   inline void rdpc(   Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
1603   inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
1604 
1605   // pp 213
1606 
1607   inline void rett( Register s1, Register s2);
1608   inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1609 
1610   // pp 214
1611 
1612   void save(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
1613   void save(    Register s1, int simm13a, Register d ) {
1614     // make sure frame is at least large enough for the register save area
1615     assert(-simm13a >= 16 * wordSize, "frame too small");
1616     emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
1617   }
1618 
1619   void restore( Register s1 = G0,  Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
1620   void restore( Register s1,       int simm13a,      Register d      ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1621 
1622   // pp 216
1623 
1624   void saved()    { v9_only();  emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); }
1625   void restored() { v9_only();  emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); }
1626 
1627   // pp 217
1628 
1629   inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1630   // pp 218
1631 
1632   void sll(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1633   void sll(  Register s1, int imm5a,   Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1634   void srl(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1635   void srl(  Register s1, int imm5a,   Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1636   void sra(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1637   void sra(  Register s1, int imm5a,   Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1638 
1639   void sllx( Register s1, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1640   void sllx( Register s1, int imm6a,   Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1641   void srlx( Register s1, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1642   void srlx( Register s1, int imm6a,   Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1643   void srax( Register s1, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1644   void srax( Register s1, int imm6a,   Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1645 
1646   // pp 220
1647 
1648   void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
1649 
1650   // pp 221
1651 
1652   void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
1653 
1654   // pp 222
1655 
1656   inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
1657   inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1658   inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1659   inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
1660 
1661   inline void stfsr(  Register s1, Register s2 );
1662   inline void stfsr(  Register s1, int simm13a);
1663   inline void stxfsr( Register s1, Register s2 );
1664   inline void stxfsr( Register s1, int simm13a);
1665 
1666   //  pp 224
1667 
1668   void stfa(  FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1669   void stfa(  FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a         ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1670 
1671   // p 226
1672 
1673   inline void stb(  Register d, Register s1, Register s2 );
1674   inline void stb(  Register d, Register s1, int simm13a);
1675   inline void sth(  Register d, Register s1, Register s2 );
1676   inline void sth(  Register d, Register s1, int simm13a);
1677   inline void stw(  Register d, Register s1, Register s2 );
1678   inline void stw(  Register d, Register s1, int simm13a);
1679   inline void st(   Register d, Register s1, Register s2 );
1680   inline void st(   Register d, Register s1, int simm13a);
1681   inline void stx(  Register d, Register s1, Register s2 );
1682   inline void stx(  Register d, Register s1, int simm13a);
1683   inline void std(  Register d, Register s1, Register s2 );
1684   inline void std(  Register d, Register s1, int simm13a);
1685 
1686 #ifdef ASSERT
1687   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
1688   inline void st(   Register d, Register s1, ByteSize simm13a);
1689 #endif
1690 
1691   inline void stb(  Register d, const Address& a, int offset = 0 );
1692   inline void sth(  Register d, const Address& a, int offset = 0 );
1693   inline void stw(  Register d, const Address& a, int offset = 0 );
1694   inline void stx(  Register d, const Address& a, int offset = 0 );
1695   inline void st(   Register d, const Address& a, int offset = 0 );
1696   inline void std(  Register d, const Address& a, int offset = 0 );
1697 
1698   inline void stb(  Register d, Register s1, RegisterOrConstant s2 );
1699   inline void sth(  Register d, Register s1, RegisterOrConstant s2 );
1700   inline void stw(  Register d, Register s1, RegisterOrConstant s2 );
1701   inline void stx(  Register d, Register s1, RegisterOrConstant s2 );
1702   inline void std(  Register d, Register s1, RegisterOrConstant s2 );
1703   inline void st(   Register d, Register s1, RegisterOrConstant s2 );
1704 
1705   // pp 177
1706 
1707   void stba(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1708   void stba(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1709   void stha(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1710   void stha(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1711   void stwa(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1712   void stwa(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1713   void stxa(  Register d, Register s1, Register s2, int ia ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1714   void stxa(  Register d, Register s1, int simm13a         ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1715   void stda(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1716   void stda(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1717 
1718   // pp 97 (v8)
1719 
1720   inline void stc(   int crd, Register s1, Register s2 );
1721   inline void stc(   int crd, Register s1, int simm13a);
1722   inline void stdc(  int crd, Register s1, Register s2 );
1723   inline void stdc(  int crd, Register s1, int simm13a);
1724   inline void stcsr( int crd, Register s1, Register s2 );
1725   inline void stcsr( int crd, Register s1, int simm13a);
1726   inline void stdcq( int crd, Register s1, Register s2 );
1727   inline void stdcq( int crd, Register s1, int simm13a);
1728 
1729   // pp 230
1730 
1731   void sub(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | rs2(s2) ); }
1732   void sub(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1733 
1734   // Note: offset is added to s2.
1735   inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1736 
1737   void subcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1738   void subcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1739   void subc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | rs2(s2) ); }
1740   void subc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1741   void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1742   void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1743 
1744   // pp 231
1745 
1746   inline void swap( Register s1, Register s2, Register d );
1747   inline void swap( Register s1, int simm13a, Register d);
1748   inline void swap( Address& a,               Register d, int offset = 0 );
1749 
1750   // pp 232
1751 
1752   void swapa(   Register s1, Register s2, int ia, Register d ) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1753   void swapa(   Register s1, int simm13a,         Register d ) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1754 
1755   // pp 234, note op in book is wrong, see pp 268
1756 
1757   void taddcc(    Register s1, Register s2, Register d ) {            emit_long( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | rs2(s2) ); }
1758   void taddcc(    Register s1, int simm13a, Register d ) {            emit_long( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1759   void taddcctv(  Register s1, Register s2, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
1760   void taddcctv(  Register s1, int simm13a, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1761 
1762   // pp 235
1763 
1764   void tsubcc(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | rs2(s2) ); }
1765   void tsubcc(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1766   void tsubcctv(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
1767   void tsubcctv(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1768 
1769   // pp 237
1770 
1771   void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc);  emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1772   void trap( Condition c, CC cc, Register s1, int trapa   ) { v8_no_cc(cc);  emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1773   // simple uncond. trap
1774   void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1775 
1776   // pp 239 omit write priv register for now
1777 
1778   inline void wry(    Register d) { v9_dep();  emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1779   inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1780   inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) |
1781                                                                            rs1(s) |
1782                                                                            op3(wrreg_op3) |
1783                                                                            u_field(2, 29, 25) |
1784                                                                            u_field(1, 13, 13) |
1785                                                                            simm(simm13a, 13)); }
1786   inline void wrasi(  Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1787   inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1788 
1789 
1790   // VIS3 instructions
1791 
1792   void movstosw( FloatRegister s, Register d ) { vis3_only();  emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1793   void movstouw( FloatRegister s, Register d ) { vis3_only();  emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1794   void movdtox(  FloatRegister s, Register d ) { vis3_only();  emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1795 
1796   void movwtos( Register s, FloatRegister d ) { vis3_only();  emit_long( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1797   void movxtod( Register s, FloatRegister d ) { vis3_only();  emit_long( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1798 
1799 
1800 
1801 
1802   // For a given register condition, return the appropriate condition code
1803   // Condition (the one you would use to get the same effect after "tst" on
1804   // the target register.)
1805   Assembler::Condition reg_cond_to_cc_cond(RCondition in);
1806 
1807 
1808   // Creation
1809   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1810 #ifdef CHECK_DELAY
1811     delay_state = no_delay;
1812 #endif
1813   }
1814 
1815   // Testing
1816 #ifndef PRODUCT
1817   void test_v9();
1818   void test_v8_onlys();
1819 #endif
1820 };
1821 
1822 
1823 class RegistersForDebugging : public StackObj {
1824  public:
1825   intptr_t i[8], l[8], o[8], g[8];
1826   float    f[32];
1827   double   d[32];
1828 
1829   void print(outputStream* s);
1830 
1831   static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
1832   static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
1833   static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
1834   static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
1835   static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
1836   static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
1837 
1838   // gen asm code to save regs
1839   static void save_registers(MacroAssembler* a);
1840 
1841   // restore global registers in case C code disturbed them
1842   static void restore_registers(MacroAssembler* a, Register r);
1843 
1844 
1845 };
1846 
1847 
1848 // MacroAssembler extends Assembler by a few frequently used macros.
1849 //
1850 // Most of the standard SPARC synthetic ops are defined here.
1851 // Instructions for which a 'better' code sequence exists depending
1852 // on arguments should also go in here.
1853 
1854 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
1855 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
1856 #define JUMP(a, temp, off)     jump(a, temp, off, __FILE__, __LINE__)
1857 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
1858 
1859 
1860 class MacroAssembler: public Assembler {
1861  protected:
1862   // Support for VM calls
1863   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1864   // may customize this version by overriding it for its purposes (e.g., to save/restore
1865   // additional registers when doing a VM call).
1866 #ifdef CC_INTERP
1867   #define VIRTUAL
1868 #else
1869   #define VIRTUAL virtual
1870 #endif
1871 
1872   VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
1873 
1874   //
1875   // It is imperative that all calls into the VM are handled via the call_VM macros.
1876   // They make sure that the stack linkage is setup correctly. call_VM's correspond
1877   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1878   //
1879   // This is the base routine called by the different versions of call_VM. The interpreter
1880   // may customize this version by overriding it for its purposes (e.g., to save/restore
1881   // additional registers when doing a VM call).
1882   //
1883   // A non-volatile java_thread_cache register should be specified so
1884   // that the G2_thread value can be preserved across the call.
1885   // (If java_thread_cache is noreg, then a slow get_thread call
1886   // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
1887   // thread.
1888   //
1889   // If no last_java_sp is specified (noreg) than SP will be used instead.
1890 
1891   virtual void call_VM_base(
1892     Register        oop_result,             // where an oop-result ends up if any; use noreg otherwise
1893     Register        java_thread_cache,      // the thread if computed before     ; use noreg otherwise
1894     Register        last_java_sp,           // to set up last_Java_frame in stubs; use noreg otherwise
1895     address         entry_point,            // the entry point
1896     int             number_of_arguments,    // the number of arguments (w/o thread) to pop after call
1897     bool            check_exception=true    // flag which indicates if exception should be checked
1898   );
1899 
1900   // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1901   // The implementation is only non-empty for the InterpreterMacroAssembler,
1902   // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
1903   virtual void check_and_handle_popframe(Register scratch_reg);
1904   virtual void check_and_handle_earlyret(Register scratch_reg);
1905 
1906  public:
1907   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1908 
1909   // Support for NULL-checks
1910   //
1911   // Generates code that causes a NULL OS exception if the content of reg is NULL.
1912   // If the accessed location is M[reg + offset] and the offset is known, provide the
1913   // offset.  No explicit code generation is needed if the offset is within a certain
1914   // range (0 <= offset <= page_size).
1915   //
1916   // %%%%%% Currently not done for SPARC
1917 
1918   void null_check(Register reg, int offset = -1);
1919   static bool needs_explicit_null_check(intptr_t offset);
1920 
1921   // support for delayed instructions
1922   MacroAssembler* delayed() { Assembler::delayed();  return this; }
1923 
1924   // branches that use right instruction for v8 vs. v9
1925   inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1926   inline void br( Condition c, bool a, Predict p, Label& L );
1927 
1928   inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1929   inline void fb( Condition c, bool a, Predict p, Label& L );
1930 
1931   // compares register with zero (32 bit) and branches (V9 and V8 instructions)
1932   void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
1933   // Compares a pointer register with zero and branches on (not)null.
1934   // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1935   void br_null   ( Register s1, bool a, Predict p, Label& L );
1936   void br_notnull( Register s1, bool a, Predict p, Label& L );
1937 
1938   // These versions will do the most efficient thing on v8 and v9.  Perhaps
1939   // this is what the routine above was meant to do, but it didn't (and
1940   // didn't cover both target address kinds.)
1941   void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1942   void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
1943 
1944   //
1945   // Compare registers and branch with nop in delay slot or cbcond without delay slot.
1946   //
1947   // ATTENTION: use these instructions with caution because cbcond instruction
1948   //            has very short distance: 512 instructions (2Kbyte).
1949 
1950   // Compare integer (32 bit) values (icc only).
1951   void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
1952   void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
1953   // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64).
1954   void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
1955   void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
1956 
1957   // Short branch version for compares a pointer pwith zero.
1958   void br_null_short   ( Register s1, Predict p, Label& L );
1959   void br_notnull_short( Register s1, Predict p, Label& L );
1960 
1961   // unconditional short branch
1962   void ba_short(Label& L);
1963 
1964   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1965   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1966 
1967   // Branch that tests xcc in LP64 and icc in !LP64
1968   inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1969   inline void brx( Condition c, bool a, Predict p, Label& L );
1970 
1971   // unconditional branch
1972   inline void ba( Label& L );
1973 
1974   // Branch that tests fp condition codes
1975   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1976   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1977 
1978   // get PC the best way
1979   inline int get_pc( Register d );
1980 
1981   // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
1982   inline void cmp(  Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
1983   inline void cmp(  Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
1984 
1985   inline void jmp( Register s1, Register s2 );
1986   inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1987 
1988   // Check if the call target is out of wdisp30 range (relative to the code cache)
1989   static inline bool is_far_target(address d);
1990   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
1991   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
1992   inline void callr( Register s1, Register s2 );
1993   inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1994 
1995   // Emits nothing on V8
1996   inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
1997   inline void iprefetch( Label& L);
1998 
1999   inline void tst( Register s ) { orcc( G0, s, G0 ); }
2000 
2001 #ifdef PRODUCT
2002   inline void ret(  bool trace = TraceJumps )   { if (trace) {
2003                                                     mov(I7, O7); // traceable register
2004                                                     JMP(O7, 2 * BytesPerInstWord);
2005                                                   } else {
2006                                                     jmpl( I7, 2 * BytesPerInstWord, G0 );
2007                                                   }
2008                                                 }
2009 
2010   inline void retl( bool trace = TraceJumps )  { if (trace) JMP(O7, 2 * BytesPerInstWord);
2011                                                  else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
2012 #else
2013   void ret(  bool trace = TraceJumps );
2014   void retl( bool trace = TraceJumps );
2015 #endif /* PRODUCT */
2016 
2017   // Required platform-specific helpers for Label::patch_instructions.
2018   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
2019   void pd_patch_instruction(address branch, address target);
2020 #ifndef PRODUCT
2021   static void pd_print_patched_instruction(address branch);
2022 #endif
2023 
2024   // sethi Macro handles optimizations and relocations
2025 private:
2026   void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
2027 public:
2028   void sethi(const AddressLiteral& addrlit, Register d);
2029   void patchable_sethi(const AddressLiteral& addrlit, Register d);
2030 
2031   // compute the number of instructions for a sethi/set
2032   static int  insts_for_sethi( address a, bool worst_case = false );
2033   static int  worst_case_insts_for_set();
2034 
2035   // set may be either setsw or setuw (high 32 bits may be zero or sign)
2036 private:
2037   void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
2038   static int insts_for_internal_set(intptr_t value);
2039 public:
2040   void set(const AddressLiteral& addrlit, Register d);
2041   void set(intptr_t value, Register d);
2042   void set(address addr, Register d, RelocationHolder const& rspec);
2043   static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); }
2044 
2045   void patchable_set(const AddressLiteral& addrlit, Register d);
2046   void patchable_set(intptr_t value, Register d);
2047   void set64(jlong value, Register d, Register tmp);
2048   static int insts_for_set64(jlong value);
2049 
2050   // sign-extend 32 to 64
2051   inline void signx( Register s, Register d ) { sra( s, G0, d); }
2052   inline void signx( Register d )             { sra( d, G0, d); }
2053 
2054   inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
2055   inline void not1( Register d )             { xnor( d, G0, d ); }
2056 
2057   inline void neg( Register s, Register d ) { sub( G0, s, d ); }
2058   inline void neg( Register d )             { sub( G0, d, d ); }
2059 
2060   inline void cas(  Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
2061   inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
2062   // Functions for isolating 64 bit atomic swaps for LP64
2063   // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
2064   inline void cas_ptr(  Register s1, Register s2, Register d) {
2065 #ifdef _LP64
2066     casx( s1, s2, d );
2067 #else
2068     cas( s1, s2, d );
2069 #endif
2070   }
2071 
2072   // Functions for isolating 64 bit shifts for LP64
2073   inline void sll_ptr( Register s1, Register s2, Register d );
2074   inline void sll_ptr( Register s1, int imm6a,   Register d );
2075   inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
2076   inline void srl_ptr( Register s1, Register s2, Register d );
2077   inline void srl_ptr( Register s1, int imm6a,   Register d );
2078 
2079   // little-endian
2080   inline void casl(  Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
2081   inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
2082 
2083   inline void inc(   Register d,  int const13 = 1 ) { add(   d, const13, d); }
2084   inline void inccc( Register d,  int const13 = 1 ) { addcc( d, const13, d); }
2085 
2086   inline void dec(   Register d,  int const13 = 1 ) { sub(   d, const13, d); }
2087   inline void deccc( Register d,  int const13 = 1 ) { subcc( d, const13, d); }
2088 
2089   inline void btst( Register s1,  Register s2 ) { andcc( s1, s2, G0 ); }
2090   inline void btst( int simm13a,  Register s )  { andcc( s,  simm13a, G0 ); }
2091 
2092   inline void bset( Register s1,  Register s2 ) { or3( s1, s2, s2 ); }
2093   inline void bset( int simm13a,  Register s )  { or3( s,  simm13a, s ); }
2094 
2095   inline void bclr( Register s1,  Register s2 ) { andn( s1, s2, s2 ); }
2096   inline void bclr( int simm13a,  Register s )  { andn( s,  simm13a, s ); }
2097 
2098   inline void btog( Register s1,  Register s2 ) { xor3( s1, s2, s2 ); }
2099   inline void btog( int simm13a,  Register s )  { xor3( s,  simm13a, s ); }
2100 
2101   inline void clr( Register d ) { or3( G0, G0, d ); }
2102 
2103   inline void clrb( Register s1, Register s2);
2104   inline void clrh( Register s1, Register s2);
2105   inline void clr(  Register s1, Register s2);
2106   inline void clrx( Register s1, Register s2);
2107 
2108   inline void clrb( Register s1, int simm13a);
2109   inline void clrh( Register s1, int simm13a);
2110   inline void clr(  Register s1, int simm13a);
2111   inline void clrx( Register s1, int simm13a);
2112 
2113   // copy & clear upper word
2114   inline void clruw( Register s, Register d ) { srl( s, G0, d); }
2115   // clear upper word
2116   inline void clruwu( Register d ) { srl( d, G0, d); }
2117 
2118   // membar psuedo instruction.  takes into account target memory model.
2119   inline void membar( Assembler::Membar_mask_bits const7a );
2120 
2121   // returns if membar generates anything.
2122   inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
2123 
2124   // mov pseudo instructions
2125   inline void mov( Register s,  Register d) {
2126     if ( s != d )    or3( G0, s, d);
2127     else             assert_not_delayed();  // Put something useful in the delay slot!
2128   }
2129 
2130   inline void mov_or_nop( Register s,  Register d) {
2131     if ( s != d )    or3( G0, s, d);
2132     else             nop();
2133   }
2134 
2135   inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
2136 
2137   // address pseudos: make these names unlike instruction names to avoid confusion
2138   inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
2139   inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
2140   inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
2141   inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
2142   inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
2143   inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
2144   inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0);
2145   inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
2146 
2147   // ring buffer traceable jumps
2148 
2149   void jmp2( Register r1, Register r2, const char* file, int line );
2150   void jmp ( Register r1, int offset,  const char* file, int line );
2151 
2152   void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
2153   void jump (const AddressLiteral& addrlit, Register temp,             int offset, const char* file, int line);
2154 
2155 
2156   // argument pseudos:
2157 
2158   inline void load_argument( Argument& a, Register  d );
2159   inline void store_argument( Register s, Argument& a );
2160   inline void store_ptr_argument( Register s, Argument& a );
2161   inline void store_float_argument( FloatRegister s, Argument& a );
2162   inline void store_double_argument( FloatRegister s, Argument& a );
2163   inline void store_long_argument( Register s, Argument& a );
2164 
2165   // handy macros:
2166 
2167   inline void round_to( Register r, int modulus ) {
2168     assert_not_delayed();
2169     inc( r, modulus - 1 );
2170     and3( r, -modulus, r );
2171   }
2172 
2173   // --------------------------------------------------
2174 
2175   // Functions for isolating 64 bit loads for LP64
2176   // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
2177   // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
2178   inline void ld_ptr(Register s1, Register s2, Register d);
2179   inline void ld_ptr(Register s1, int simm13a, Register d);
2180   inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
2181   inline void ld_ptr(const Address& a, Register d, int offset = 0);
2182   inline void st_ptr(Register d, Register s1, Register s2);
2183   inline void st_ptr(Register d, Register s1, int simm13a);
2184   inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
2185   inline void st_ptr(Register d, const Address& a, int offset = 0);
2186 
2187 #ifdef ASSERT
2188   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
2189   inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
2190   inline void st_ptr(Register d, Register s1, ByteSize simm13a);
2191 #endif
2192 
2193   // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
2194   // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
2195   inline void ld_long(Register s1, Register s2, Register d);
2196   inline void ld_long(Register s1, int simm13a, Register d);
2197   inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
2198   inline void ld_long(const Address& a, Register d, int offset = 0);
2199   inline void st_long(Register d, Register s1, Register s2);
2200   inline void st_long(Register d, Register s1, int simm13a);
2201   inline void st_long(Register d, Register s1, RegisterOrConstant s2);
2202   inline void st_long(Register d, const Address& a, int offset = 0);
2203 
2204   // Helpers for address formation.
2205   // - They emit only a move if s2 is a constant zero.
2206   // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
2207   // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
2208   RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2209   RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2210   RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2211 
2212   RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
2213     if (is_simm13(src.constant_or_zero()))
2214       return src;               // register or short constant
2215     guarantee(temp != noreg, "constant offset overflow");
2216     set(src.as_constant(), temp);
2217     return temp;
2218   }
2219 
2220   // --------------------------------------------------
2221 
2222  public:
2223   // traps as per trap.h (SPARC ABI?)
2224 
2225   void breakpoint_trap();
2226   void breakpoint_trap(Condition c, CC cc = icc);
2227   void flush_windows_trap();
2228   void clean_windows_trap();
2229   void get_psr_trap();
2230   void set_psr_trap();
2231 
2232   // V8/V9 flush_windows
2233   void flush_windows();
2234 
2235   // Support for serializing memory accesses between threads
2236   void serialize_memory(Register thread, Register tmp1, Register tmp2);
2237 
2238   // Stack frame creation/removal
2239   void enter();
2240   void leave();
2241 
2242   // V8/V9 integer multiply
2243   void mult(Register s1, Register s2, Register d);
2244   void mult(Register s1, int simm13a, Register d);
2245 
2246   // V8/V9 read and write of condition codes.
2247   void read_ccr(Register d);
2248   void write_ccr(Register s);
2249 
2250   // Manipulation of C++ bools
2251   // These are idioms to flag the need for care with accessing bools but on
2252   // this platform we assume byte size
2253 
2254   inline void stbool(Register d, const Address& a) { stb(d, a); }
2255   inline void ldbool(const Address& a, Register d) { ldsb(a, d); }
2256   inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
2257 
2258   // klass oop manipulations if compressed
2259   void load_klass(Register src_oop, Register klass);
2260   void store_klass(Register klass, Register dst_oop);
2261   void store_klass_gap(Register s, Register dst_oop);
2262 
2263    // oop manipulations
2264   void load_heap_oop(const Address& s, Register d);
2265   void load_heap_oop(Register s1, Register s2, Register d);
2266   void load_heap_oop(Register s1, int simm13a, Register d);
2267   void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
2268   void store_heap_oop(Register d, Register s1, Register s2);
2269   void store_heap_oop(Register d, Register s1, int simm13a);
2270   void store_heap_oop(Register d, const Address& a, int offset = 0);
2271 
2272   void encode_heap_oop(Register src, Register dst);
2273   void encode_heap_oop(Register r) {
2274     encode_heap_oop(r, r);
2275   }
2276   void decode_heap_oop(Register src, Register dst);
2277   void decode_heap_oop(Register r) {
2278     decode_heap_oop(r, r);
2279   }
2280   void encode_heap_oop_not_null(Register r);
2281   void decode_heap_oop_not_null(Register r);
2282   void encode_heap_oop_not_null(Register src, Register dst);
2283   void decode_heap_oop_not_null(Register src, Register dst);
2284 
2285   // Support for managing the JavaThread pointer (i.e.; the reference to
2286   // thread-local information).
2287   void get_thread();                                // load G2_thread
2288   void verify_thread();                             // verify G2_thread contents
2289   void save_thread   (const Register threache); // save to cache
2290   void restore_thread(const Register thread_cache); // restore from cache
2291 
2292   // Support for last Java frame (but use call_VM instead where possible)
2293   void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
2294   void reset_last_Java_frame(void);
2295 
2296   // Call into the VM.
2297   // Passes the thread pointer (in O0) as a prepended argument.
2298   // Makes sure oop return values are visible to the GC.
2299   void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2300   void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
2301   void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2302   void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2303 
2304   // these overloadings are not presently used on SPARC:
2305   void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2306   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
2307   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2308   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2309 
2310   void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
2311   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
2312   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
2313   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
2314 
2315   void get_vm_result  (Register oop_result);
2316   void get_vm_result_2(Register oop_result);
2317 
2318   // vm result is currently getting hijacked to for oop preservation
2319   void set_vm_result(Register oop_result);
2320 
2321   // if call_VM_base was called with check_exceptions=false, then call
2322   // check_and_forward_exception to handle exceptions when it is safe
2323   void check_and_forward_exception(Register scratch_reg);
2324 
2325  private:
2326   // For V8
2327   void read_ccr_trap(Register ccr_save);
2328   void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
2329 
2330 #ifdef ASSERT
2331   // For V8 debugging.  Uses V8 instruction sequence and checks
2332   // result with V9 insturctions rdccr and wrccr.
2333   // Uses Gscatch and Gscatch2
2334   void read_ccr_v8_assert(Register ccr_save);
2335   void write_ccr_v8_assert(Register ccr_save);
2336 #endif // ASSERT
2337 
2338  public:
2339 
2340   // Write to card table for - register is destroyed afterwards.
2341   void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
2342 
2343   void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2344 
2345 #ifndef SERIALGC
2346   // General G1 pre-barrier generator.
2347   void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs);
2348 
2349   // General G1 post-barrier generator
2350   void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2351 #endif // SERIALGC
2352 
2353   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2354   void push_fTOS();
2355 
2356   // pops double TOS element from CPU stack and pushes on FPU stack
2357   void pop_fTOS();
2358 
2359   void empty_FPU_stack();
2360 
2361   void push_IU_state();
2362   void pop_IU_state();
2363 
2364   void push_FPU_state();
2365   void pop_FPU_state();
2366 
2367   void push_CPU_state();
2368   void pop_CPU_state();
2369 
2370   // if heap base register is used - reinit it with the correct value
2371   void reinit_heapbase();
2372 
2373   // Debugging
2374   void _verify_oop(Register reg, const char * msg, const char * file, int line);
2375   void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
2376 
2377 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
2378 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
2379 
2380         // only if +VerifyOops
2381   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2382         // only if +VerifyFPU
2383   void stop(const char* msg);                          // prints msg, dumps registers and stops execution
2384   void warn(const char* msg);                          // prints msg, but don't stop
2385   void untested(const char* what = "");
2386   void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
2387   void should_not_reach_here()                   { stop("should not reach here"); }
2388   void print_CPU_state();
2389 
2390   // oops in code
2391   AddressLiteral allocate_oop_address(jobject obj);                          // allocate_index
2392   AddressLiteral constant_oop_address(jobject obj);                          // find_index
2393   inline void    set_oop             (jobject obj, Register d);              // uses allocate_oop_address
2394   inline void    set_oop_constant    (jobject obj, Register d);              // uses constant_oop_address
2395   inline void    set_oop             (const AddressLiteral& obj_addr, Register d); // same as load_address
2396 
2397   void set_narrow_oop( jobject obj, Register d );
2398 
2399   // nop padding
2400   void align(int modulus);
2401 
2402   // declare a safepoint
2403   void safepoint();
2404 
2405   // factor out part of stop into subroutine to save space
2406   void stop_subroutine();
2407   // factor out part of verify_oop into subroutine to save space
2408   void verify_oop_subroutine();
2409 
2410   // side-door communication with signalHandler in os_solaris.cpp
2411   static address _verify_oop_implicit_branch[3];
2412 
2413 #ifndef PRODUCT
2414   static void test();
2415 #endif
2416 
2417   // convert an incoming arglist to varargs format; put the pointer in d
2418   void set_varargs( Argument a, Register d );
2419 
2420   int total_frame_size_in_bytes(int extraWords);
2421 
2422   // used when extraWords known statically
2423   void save_frame(int extraWords = 0);
2424   void save_frame_c1(int size_in_bytes);
2425   // make a frame, and simultaneously pass up one or two register value
2426   // into the new register window
2427   void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
2428 
2429   // give no. (outgoing) params, calc # of words will need on frame
2430   void calc_mem_param_words(Register Rparam_words, Register Rresult);
2431 
2432   // used to calculate frame size dynamically
2433   // result is in bytes and must be negated for save inst
2434   void calc_frame_size(Register extraWords, Register resultReg);
2435 
2436   // calc and also save
2437   void calc_frame_size_and_save(Register extraWords, Register resultReg);
2438 
2439   static void debug(char* msg, RegistersForDebugging* outWindow);
2440 
2441   // implementations of bytecodes used by both interpreter and compiler
2442 
2443   void lcmp( Register Ra_hi, Register Ra_low,
2444              Register Rb_hi, Register Rb_low,
2445              Register Rresult);
2446 
2447   void lneg( Register Rhi, Register Rlow );
2448 
2449   void lshl(  Register Rin_high,  Register Rin_low,  Register Rcount,
2450               Register Rout_high, Register Rout_low, Register Rtemp );
2451 
2452   void lshr(  Register Rin_high,  Register Rin_low,  Register Rcount,
2453               Register Rout_high, Register Rout_low, Register Rtemp );
2454 
2455   void lushr( Register Rin_high,  Register Rin_low,  Register Rcount,
2456               Register Rout_high, Register Rout_low, Register Rtemp );
2457 
2458 #ifdef _LP64
2459   void lcmp( Register Ra, Register Rb, Register Rresult);
2460 #endif
2461 
2462   // Load and store values by size and signed-ness
2463   void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
2464   void store_sized_value(Register src, Address dst, size_t size_in_bytes);
2465 
2466   void float_cmp( bool is_float, int unordered_result,
2467                   FloatRegister Fa, FloatRegister Fb,
2468                   Register Rresult);
2469 
2470   void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2471   void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
2472   void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2473   void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2474 
2475   void save_all_globals_into_locals();
2476   void restore_globals_from_locals();
2477 
2478   void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2479     address lock_addr=0, bool use_call_vm=false);
2480   void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2481     address lock_addr=0, bool use_call_vm=false);
2482   void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
2483 
2484   // These set the icc condition code to equal if the lock succeeded
2485   // and notEqual if it failed and requires a slow case
2486   void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
2487                             Register Rscratch,
2488                             BiasedLockingCounters* counters = NULL,
2489                             bool try_bias = UseBiasedLocking);
2490   void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
2491                               Register Rscratch,
2492                               bool try_bias = UseBiasedLocking);
2493 
2494   // Biased locking support
2495   // Upon entry, lock_reg must point to the lock record on the stack,
2496   // obj_reg must contain the target object, and mark_reg must contain
2497   // the target object's header.
2498   // Destroys mark_reg if an attempt is made to bias an anonymously
2499   // biased lock. In this case a failure will go either to the slow
2500   // case or fall through with the notEqual condition code set with
2501   // the expectation that the slow case in the runtime will be called.
2502   // In the fall-through case where the CAS-based lock is done,
2503   // mark_reg is not destroyed.
2504   void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
2505                             Label& done, Label* slow_case = NULL,
2506                             BiasedLockingCounters* counters = NULL);
2507   // Upon entry, the base register of mark_addr must contain the oop.
2508   // Destroys temp_reg.
2509 
2510   // If allow_delay_slot_filling is set to true, the next instruction
2511   // emitted after this one will go in an annulled delay slot if the
2512   // biased locking exit case failed.
2513   void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
2514 
2515   // allocation
2516   void eden_allocate(
2517     Register obj,                      // result: pointer to object after successful allocation
2518     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
2519     int      con_size_in_bytes,        // object size in bytes if   known at compile time
2520     Register t1,                       // temp register
2521     Register t2,                       // temp register
2522     Label&   slow_case                 // continuation point if fast allocation fails
2523   );
2524   void tlab_allocate(
2525     Register obj,                      // result: pointer to object after successful allocation
2526     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
2527     int      con_size_in_bytes,        // object size in bytes if   known at compile time
2528     Register t1,                       // temp register
2529     Label&   slow_case                 // continuation point if fast allocation fails
2530   );
2531   void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
2532   void incr_allocated_bytes(RegisterOrConstant size_in_bytes,
2533                             Register t1, Register t2);
2534 
2535   // interface method calling
2536   void lookup_interface_method(Register recv_klass,
2537                                Register intf_klass,
2538                                RegisterOrConstant itable_index,
2539                                Register method_result,
2540                                Register temp_reg, Register temp2_reg,
2541                                Label& no_such_interface);
2542 
2543   // Test sub_klass against super_klass, with fast and slow paths.
2544 
2545   // The fast path produces a tri-state answer: yes / no / maybe-slow.
2546   // One of the three labels can be NULL, meaning take the fall-through.
2547   // If super_check_offset is -1, the value is loaded up from super_klass.
2548   // No registers are killed, except temp_reg and temp2_reg.
2549   // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
2550   void check_klass_subtype_fast_path(Register sub_klass,
2551                                      Register super_klass,
2552                                      Register temp_reg,
2553                                      Register temp2_reg,
2554                                      Label* L_success,
2555                                      Label* L_failure,
2556                                      Label* L_slow_path,
2557                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
2558 
2559   // The rest of the type check; must be wired to a corresponding fast path.
2560   // It does not repeat the fast path logic, so don't use it standalone.
2561   // The temp_reg can be noreg, if no temps are available.
2562   // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
2563   // Updates the sub's secondary super cache as necessary.
2564   void check_klass_subtype_slow_path(Register sub_klass,
2565                                      Register super_klass,
2566                                      Register temp_reg,
2567                                      Register temp2_reg,
2568                                      Register temp3_reg,
2569                                      Register temp4_reg,
2570                                      Label* L_success,
2571                                      Label* L_failure);
2572 
2573   // Simplified, combined version, good for typical uses.
2574   // Falls through on failure.
2575   void check_klass_subtype(Register sub_klass,
2576                            Register super_klass,
2577                            Register temp_reg,
2578                            Register temp2_reg,
2579                            Label& L_success);
2580 
2581   // method handles (JSR 292)
2582   void check_method_handle_type(Register mtype_reg, Register mh_reg,
2583                                 Register temp_reg,
2584                                 Label& wrong_method_type);
2585   void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
2586                                   Register temp_reg);
2587   void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true);
2588   // offset relative to Gargs of argument at tos[arg_slot].
2589   // (arg_slot == 0 means the last argument, not the first).
2590   RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
2591                                      Register temp_reg,
2592                                      int extra_slot_offset = 0);
2593   // Address of Gargs and argument_offset.
2594   Address            argument_address(RegisterOrConstant arg_slot,
2595                                       Register temp_reg,
2596                                       int extra_slot_offset = 0);
2597 
2598   // Stack overflow checking
2599 
2600   // Note: this clobbers G3_scratch
2601   void bang_stack_with_offset(int offset) {
2602     // stack grows down, caller passes positive offset
2603     assert(offset > 0, "must bang with negative offset");
2604     set((-offset)+STACK_BIAS, G3_scratch);
2605     st(G0, SP, G3_scratch);
2606   }
2607 
2608   // Writes to stack successive pages until offset reached to check for
2609   // stack overflow + shadow pages.  Clobbers tsp and scratch registers.
2610   void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
2611 
2612   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
2613 
2614   void verify_tlab();
2615 
2616   Condition negate_condition(Condition cond);
2617 
2618   // Helper functions for statistics gathering.
2619   // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
2620   void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
2621   // Unconditional increment.
2622   void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
2623   void inc_counter(int*    counter_addr, Register Rtmp1, Register Rtmp2);
2624 
2625   // Compare char[] arrays aligned to 4 bytes.
2626   void char_arrays_equals(Register ary1, Register ary2,
2627                           Register limit, Register result,
2628                           Register chr1, Register chr2, Label& Ldone);
2629 
2630 #undef VIRTUAL
2631 
2632 };
2633 
2634 /**
2635  * class SkipIfEqual:
2636  *
2637  * Instantiating this class will result in assembly code being output that will
2638  * jump around any code emitted between the creation of the instance and it's
2639  * automatic destruction at the end of a scope block, depending on the value of
2640  * the flag passed to the constructor, which will be checked at run-time.
2641  */
2642 class SkipIfEqual : public StackObj {
2643  private:
2644   MacroAssembler* _masm;
2645   Label _label;
2646 
2647  public:
2648    // 'temp' is a temp register that this object can use (and trash)
2649    SkipIfEqual(MacroAssembler*, Register temp,
2650                const bool* flag_addr, Assembler::Condition condition);
2651    ~SkipIfEqual();
2652 };
2653 
2654 #ifdef ASSERT
2655 // On RISC, there's no benefit to verifying instruction boundaries.
2656 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
2657 #endif
2658 
2659 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP