src/cpu/sparc/vm/assembler_sparc.hpp
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src/cpu/sparc/vm/assembler_sparc.hpp

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 744     fcmpd_opf   = 0x52,
 745 
 746     fstox_opf   = 0x81,
 747     fdtox_opf   = 0x82,
 748     fxtos_opf   = 0x84,
 749     fxtod_opf   = 0x88,
 750     fitos_opf   = 0xc4,
 751     fdtos_opf   = 0xc6,
 752     fitod_opf   = 0xc8,
 753     fstod_opf   = 0xc9,
 754     fstoi_opf   = 0xd1,
 755     fdtoi_opf   = 0xd2,
 756 
 757     mdtox_opf   = 0x110,
 758     mstouw_opf  = 0x111,
 759     mstosw_opf  = 0x113,
 760     mxtod_opf   = 0x118,
 761     mwtos_opf   = 0x119
 762   };
 763 
 764   enum RCondition {  rc_z = 1,  rc_lez = 2,  rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7  };
 765 
 766   enum Condition {
 767      // for FBfcc & FBPfcc instruction
 768     f_never                     = 0,
 769     f_notEqual                  = 1,
 770     f_notZero                   = 1,
 771     f_lessOrGreater             = 2,
 772     f_unorderedOrLess           = 3,
 773     f_less                      = 4,
 774     f_unorderedOrGreater        = 5,
 775     f_greater                   = 6,
 776     f_unordered                 = 7,
 777     f_always                    = 8,
 778     f_equal                     = 9,
 779     f_zero                      = 9,
 780     f_unorderedOrEqual          = 10,
 781     f_greaterOrEqual            = 11,
 782     f_unorderedOrGreaterOrEqual = 12,
 783     f_lessOrEqual               = 13,
 784     f_unorderedOrLessOrEqual    = 14,


 849     LoadStore  = 1 << 2,
 850     StoreLoad  = 1 << 1,
 851     LoadLoad   = 1 << 0,
 852 
 853     Sync       = 1 << 6,
 854     MemIssue   = 1 << 5,
 855     Lookaside  = 1 << 4
 856   };
 857 
 858   // test if x is within signed immediate range for nbits
 859   static bool is_simm(intptr_t x, int nbits) { return -( intptr_t(1) << nbits-1 )  <= x   &&   x  <  ( intptr_t(1) << nbits-1 ); }
 860 
 861   // test if -4096 <= x <= 4095
 862   static bool is_simm13(intptr_t x) { return is_simm(x, 13); }
 863 
 864   static bool is_in_wdisp_range(address a, address b, int nbits) {
 865     intptr_t d = intptr_t(b) - intptr_t(a);
 866     return is_simm(d, nbits + 2);
 867   }
 868 









 869   // test if label is in simm16 range in words (wdisp16).
 870   bool is_in_wdisp16_range(Label& L) {
 871     return is_in_wdisp_range(target(L), pc(), 16);
 872   }
 873   // test if the distance between two addresses fits in simm30 range in words
 874   static bool is_in_wdisp30_range(address a, address b) {
 875     return is_in_wdisp_range(a, b, 30);
 876   }
 877 
 878   enum ASIs { // page 72, v9
 879     ASI_PRIMARY        = 0x80,
 880     ASI_PRIMARY_LITTLE = 0x88
 881     // add more from book as needed
 882   };
 883 
 884  protected:
 885   // helpers
 886 
 887   // x is supposed to fit in a field "nbits" wide
 888   // and be sign-extended. Check the range.
 889 
 890   static void assert_signed_range(intptr_t x, int nbits) {
 891     assert(nbits == 32 || (-(1 << nbits-1) <= x  &&  x < ( 1 << nbits-1)),


 958   static int fcn(      int         x)  { return  u_field(x,             29, 25); }
 959   static int op3(      int         x)  { return  u_field(x,             24, 19); }
 960   static int rs1(      Register    r)  { return  u_field(r->encoding(), 18, 14); }
 961   static int rs2(      Register    r)  { return  u_field(r->encoding(),  4,  0); }
 962   static int annul(    bool        a)  { return  u_field(a ? 1 : 0,     29, 29); }
 963   static int cond(     int         x)  { return  u_field(x,             28, 25); }
 964   static int cond_mov( int         x)  { return  u_field(x,             17, 14); }
 965   static int rcond(    RCondition  x)  { return  u_field(x,             12, 10); }
 966   static int op2(      int         x)  { return  u_field(x,             24, 22); }
 967   static int predict(  bool        p)  { return  u_field(p ? 1 : 0,     19, 19); }
 968   static int branchcc( CC       fcca)  { return  u_field(fcca,          21, 20); }
 969   static int cmpcc(    CC       fcca)  { return  u_field(fcca,          26, 25); }
 970   static int imm_asi(  int         x)  { return  u_field(x,             12,  5); }
 971   static int immed(    bool        i)  { return  u_field(i ? 1 : 0,     13, 13); }
 972   static int opf_low6( int         w)  { return  u_field(w,             10,  5); }
 973   static int opf_low5( int         w)  { return  u_field(w,              9,  5); }
 974   static int trapcc(   CC         cc)  { return  u_field(cc,            12, 11); }
 975   static int sx(       int         i)  { return  u_field(i,             12, 12); } // shift x=1 means 64-bit
 976   static int opf(      int         x)  { return  u_field(x,             13,  5); }
 977 














 978   static int opf_cc(   CC          c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
 979   static int mov_cc(   CC          c, bool useFloat ) { return u_field(useFloat ? 0 : 1,  18, 18) | u_field(c, 12, 11); }
 980 
 981   static int fd( FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
 982   static int fs1(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
 983   static int fs2(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa),  4,  0); };
 984 
 985   // some float instructions use this encoding on the op3 field
 986   static int alt_op3(int op, FloatRegisterImpl::Width w) {
 987     int r;
 988     switch(w) {
 989      case FloatRegisterImpl::S: r = op + 0;  break;
 990      case FloatRegisterImpl::D: r = op + 3;  break;
 991      case FloatRegisterImpl::Q: r = op + 2;  break;
 992      default: ShouldNotReachHere(); break;
 993     }
 994     return op3(r);
 995   }
 996 
 997 


1009   }
1010 
1011   // compute inverse of wdisp16
1012   static intptr_t inv_wdisp16(int x, intptr_t pos) {
1013     int lo = x & (( 1 << 14 ) - 1);
1014     int hi = (x >> 20) & 3;
1015     if (hi >= 2) hi |= ~1;
1016     return (((hi << 14) | lo) << 2) + pos;
1017   }
1018 
1019   // word offset, 14 bits at LSend, 2 bits at B21, B20
1020   static int wdisp16(intptr_t x, intptr_t off) {
1021     intptr_t xx = x - off;
1022     assert_signed_word_disp_range(xx, 16);
1023     int r =  (xx >> 2) & ((1 << 14) - 1)
1024            |  (  ( (xx>>(2+14)) & 3 )  <<  20 );
1025     assert( inv_wdisp16(r, off) == x,  "inverse is not inverse");
1026     return r;
1027   }
1028 








1029 












1030   // word displacement in low-order nbits bits
1031 
1032   static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
1033     int pre_sign_extend = x & (( 1 << nbits ) - 1);
1034     int r =  pre_sign_extend >= ( 1 << (nbits-1) )
1035        ?   pre_sign_extend | ~(( 1 << nbits ) - 1)
1036        :   pre_sign_extend;
1037     return (r << 2) + pos;
1038   }
1039 
1040   static int wdisp( intptr_t x, intptr_t off, int nbits ) {
1041     intptr_t xx = x - off;
1042     assert_signed_word_disp_range(xx, nbits);
1043     int r =  (xx >> 2) & (( 1 << nbits ) - 1);
1044     assert( inv_wdisp( r, off, nbits )  ==  x, "inverse not inverse");
1045     return r;
1046   }
1047 
1048 
1049   // Extract the top 32 bits in a 64 bit word


1121 
1122  protected:
1123   // Delay slot helpers
1124   // cti is called when emitting control-transfer instruction,
1125   // BEFORE doing the emitting.
1126   // Only effective when assertion-checking is enabled.
1127   void cti() {
1128 #ifdef CHECK_DELAY
1129     assert_not_delayed("cti should not be in delay slot");
1130 #endif
1131   }
1132 
1133   // called when emitting cti with a delay slot, AFTER emitting
1134   void has_delay_slot() {
1135 #ifdef CHECK_DELAY
1136     assert_not_delayed("just checking");
1137     delay_state = at_delay_slot;
1138 #endif
1139   }
1140 


















1141 public:
1142   // Tells assembler you know that next instruction is delayed
1143   Assembler* delayed() {
1144 #ifdef CHECK_DELAY
1145     assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
1146     delay_state = filling_delay_slot;
1147 #endif
1148     return this;
1149   }
1150 
1151   void flush() {
1152 #ifdef CHECK_DELAY
1153     assert ( delay_state == no_delay, "ending code with a delay slot");
1154 #endif
1155     AbstractAssembler::flush();
1156   }
1157 
1158   inline void emit_long(int);  // shadows AbstractAssembler::emit_long
1159   inline void emit_data(int x) { emit_long(x); }
1160   inline void emit_data(int, RelocationHolder const&);


1164 
1165 
1166  public:
1167   // instructions, refer to page numbers in the SPARC Architecture Manual, V9
1168 
1169   // pp 135 (addc was addx in v8)
1170 
1171   inline void add(Register s1, Register s2, Register d );
1172   inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1173   inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1174   inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1175   inline void add(const Address& a, Register d, int offset = 0);
1176 
1177   void addcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1178   void addcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1179   void addc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | rs2(s2) ); }
1180   void addc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1181   void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1182   void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1183 

1184   // pp 136
1185 
1186   inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1187   inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
1188 
1189  protected: // use MacroAssembler::br instead
1190 
1191   // pp 138
1192 
1193   inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1194   inline void fb( Condition c, bool a, Label& L );
1195 
1196   // pp 141
1197 
1198   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1199   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1200 
1201  public:
1202 
1203   // pp 144
1204 
1205   inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1206   inline void br( Condition c, bool a, Label& L );
1207 
1208   // pp 146
1209 
1210   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1211   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1212 
1213   // pp 121 (V8)
1214 
1215   inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1216   inline void cb( Condition c, bool a, Label& L );
1217 




1218   // pp 149
1219 
1220   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
1221   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
1222 


1223   // pp 150
1224 
1225   // These instructions compare the contents of s2 with the contents of
1226   // memory at address in s1. If the values are equal, the contents of memory
1227   // at address s1 is swapped with the data in d. If the values are not equal,
1228   // the the contents of memory at s1 is loaded into d, without the swap.
1229 
1230   void casa(  Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1231   void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1232 
1233   // pp 152
1234 
1235   void udiv(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | rs2(s2)); }
1236   void udiv(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1237   void sdiv(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | rs2(s2)); }
1238   void sdiv(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1239   void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1240   void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1241   void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1242   void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }


1845   // Generates code that causes a NULL OS exception if the content of reg is NULL.
1846   // If the accessed location is M[reg + offset] and the offset is known, provide the
1847   // offset.  No explicit code generation is needed if the offset is within a certain
1848   // range (0 <= offset <= page_size).
1849   //
1850   // %%%%%% Currently not done for SPARC
1851 
1852   void null_check(Register reg, int offset = -1);
1853   static bool needs_explicit_null_check(intptr_t offset);
1854 
1855   // support for delayed instructions
1856   MacroAssembler* delayed() { Assembler::delayed();  return this; }
1857 
1858   // branches that use right instruction for v8 vs. v9
1859   inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1860   inline void br( Condition c, bool a, Predict p, Label& L );
1861 
1862   inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1863   inline void fb( Condition c, bool a, Predict p, Label& L );
1864 
1865   // compares register with zero and branches (V9 and V8 instructions)
1866   void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
1867   // Compares a pointer register with zero and branches on (not)null.
1868   // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1869   void br_null   ( Register s1, bool a, Predict p, Label& L );
1870   void br_notnull( Register s1, bool a, Predict p, Label& L );
1871 
1872   // These versions will do the most efficient thing on v8 and v9.  Perhaps
1873   // this is what the routine above was meant to do, but it didn't (and
1874   // didn't cover both target address kinds.)
1875   void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1876   void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
1877 




















1878   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1879   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1880 
1881   // Branch that tests xcc in LP64 and icc in !LP64
1882   inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1883   inline void brx( Condition c, bool a, Predict p, Label& L );
1884 
1885   // unconditional short branch
1886   inline void ba( bool a, Label& L );
1887 
1888   // Branch that tests fp condition codes
1889   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1890   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1891 
1892   // get PC the best way
1893   inline int get_pc( Register d );
1894 
1895   // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
1896   inline void cmp(  Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
1897   inline void cmp(  Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
1898 
1899   inline void jmp( Register s1, Register s2 );
1900   inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1901 
1902   // Check if the call target is out of wdisp30 range (relative to the code cache)
1903   static inline bool is_far_target(address d);
1904   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
1905   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
1906   inline void callr( Register s1, Register s2 );


2150   void serialize_memory(Register thread, Register tmp1, Register tmp2);
2151 
2152   // Stack frame creation/removal
2153   void enter();
2154   void leave();
2155 
2156   // V8/V9 integer multiply
2157   void mult(Register s1, Register s2, Register d);
2158   void mult(Register s1, int simm13a, Register d);
2159 
2160   // V8/V9 read and write of condition codes.
2161   void read_ccr(Register d);
2162   void write_ccr(Register s);
2163 
2164   // Manipulation of C++ bools
2165   // These are idioms to flag the need for care with accessing bools but on
2166   // this platform we assume byte size
2167 
2168   inline void stbool(Register d, const Address& a) { stb(d, a); }
2169   inline void ldbool(const Address& a, Register d) { ldsb(a, d); }
2170   inline void tstbool( Register s ) { tst(s); }
2171   inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
2172 
2173   // klass oop manipulations if compressed
2174   void load_klass(Register src_oop, Register klass);
2175   void store_klass(Register klass, Register dst_oop);
2176   void store_klass_gap(Register s, Register dst_oop);
2177 
2178    // oop manipulations
2179   void load_heap_oop(const Address& s, Register d);
2180   void load_heap_oop(Register s1, Register s2, Register d);
2181   void load_heap_oop(Register s1, int simm13a, Register d);
2182   void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
2183   void store_heap_oop(Register d, Register s1, Register s2);
2184   void store_heap_oop(Register d, Register s1, int simm13a);
2185   void store_heap_oop(Register d, const Address& a, int offset = 0);
2186 
2187   void encode_heap_oop(Register src, Register dst);
2188   void encode_heap_oop(Register r) {
2189     encode_heap_oop(r, r);
2190   }


2452                                Register intf_klass,
2453                                RegisterOrConstant itable_index,
2454                                Register method_result,
2455                                Register temp_reg, Register temp2_reg,
2456                                Label& no_such_interface);
2457 
2458   // Test sub_klass against super_klass, with fast and slow paths.
2459 
2460   // The fast path produces a tri-state answer: yes / no / maybe-slow.
2461   // One of the three labels can be NULL, meaning take the fall-through.
2462   // If super_check_offset is -1, the value is loaded up from super_klass.
2463   // No registers are killed, except temp_reg and temp2_reg.
2464   // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
2465   void check_klass_subtype_fast_path(Register sub_klass,
2466                                      Register super_klass,
2467                                      Register temp_reg,
2468                                      Register temp2_reg,
2469                                      Label* L_success,
2470                                      Label* L_failure,
2471                                      Label* L_slow_path,
2472                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1),
2473                 Register instanceof_hack = noreg);
2474 
2475   // The rest of the type check; must be wired to a corresponding fast path.
2476   // It does not repeat the fast path logic, so don't use it standalone.
2477   // The temp_reg can be noreg, if no temps are available.
2478   // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
2479   // Updates the sub's secondary super cache as necessary.
2480   void check_klass_subtype_slow_path(Register sub_klass,
2481                                      Register super_klass,
2482                                      Register temp_reg,
2483                                      Register temp2_reg,
2484                                      Register temp3_reg,
2485                                      Register temp4_reg,
2486                                      Label* L_success,
2487                                      Label* L_failure);
2488 
2489   // Simplified, combined version, good for typical uses.
2490   // Falls through on failure.
2491   void check_klass_subtype(Register sub_klass,
2492                            Register super_klass,
2493                            Register temp_reg,




 744     fcmpd_opf   = 0x52,
 745 
 746     fstox_opf   = 0x81,
 747     fdtox_opf   = 0x82,
 748     fxtos_opf   = 0x84,
 749     fxtod_opf   = 0x88,
 750     fitos_opf   = 0xc4,
 751     fdtos_opf   = 0xc6,
 752     fitod_opf   = 0xc8,
 753     fstod_opf   = 0xc9,
 754     fstoi_opf   = 0xd1,
 755     fdtoi_opf   = 0xd2,
 756 
 757     mdtox_opf   = 0x110,
 758     mstouw_opf  = 0x111,
 759     mstosw_opf  = 0x113,
 760     mxtod_opf   = 0x118,
 761     mwtos_opf   = 0x119
 762   };
 763 
 764   enum RCondition {  rc_z = 1,  rc_lez = 2,  rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez  };
 765 
 766   enum Condition {
 767      // for FBfcc & FBPfcc instruction
 768     f_never                     = 0,
 769     f_notEqual                  = 1,
 770     f_notZero                   = 1,
 771     f_lessOrGreater             = 2,
 772     f_unorderedOrLess           = 3,
 773     f_less                      = 4,
 774     f_unorderedOrGreater        = 5,
 775     f_greater                   = 6,
 776     f_unordered                 = 7,
 777     f_always                    = 8,
 778     f_equal                     = 9,
 779     f_zero                      = 9,
 780     f_unorderedOrEqual          = 10,
 781     f_greaterOrEqual            = 11,
 782     f_unorderedOrGreaterOrEqual = 12,
 783     f_lessOrEqual               = 13,
 784     f_unorderedOrLessOrEqual    = 14,


 849     LoadStore  = 1 << 2,
 850     StoreLoad  = 1 << 1,
 851     LoadLoad   = 1 << 0,
 852 
 853     Sync       = 1 << 6,
 854     MemIssue   = 1 << 5,
 855     Lookaside  = 1 << 4
 856   };
 857 
 858   // test if x is within signed immediate range for nbits
 859   static bool is_simm(intptr_t x, int nbits) { return -( intptr_t(1) << nbits-1 )  <= x   &&   x  <  ( intptr_t(1) << nbits-1 ); }
 860 
 861   // test if -4096 <= x <= 4095
 862   static bool is_simm13(intptr_t x) { return is_simm(x, 13); }
 863 
 864   static bool is_in_wdisp_range(address a, address b, int nbits) {
 865     intptr_t d = intptr_t(b) - intptr_t(a);
 866     return is_simm(d, nbits + 2);
 867   }
 868 
 869   address target_distance(Label& L) {
 870     // Assembler::target(L) should be called only when
 871     // a branch instruction is emitted since non-bound
 872     // labels record current pc() as a branch address.
 873     if (L.is_bound()) return target(L);
 874     // Return current address for non-bound labels.
 875     return pc();
 876   }
 877 
 878   // test if label is in simm16 range in words (wdisp16).
 879   bool is_in_wdisp16_range(Label& L) {
 880     return is_in_wdisp_range(target_distance(L), pc(), 16);
 881   }
 882   // test if the distance between two addresses fits in simm30 range in words
 883   static bool is_in_wdisp30_range(address a, address b) {
 884     return is_in_wdisp_range(a, b, 30);
 885   }
 886 
 887   enum ASIs { // page 72, v9
 888     ASI_PRIMARY        = 0x80,
 889     ASI_PRIMARY_LITTLE = 0x88
 890     // add more from book as needed
 891   };
 892 
 893  protected:
 894   // helpers
 895 
 896   // x is supposed to fit in a field "nbits" wide
 897   // and be sign-extended. Check the range.
 898 
 899   static void assert_signed_range(intptr_t x, int nbits) {
 900     assert(nbits == 32 || (-(1 << nbits-1) <= x  &&  x < ( 1 << nbits-1)),


 967   static int fcn(      int         x)  { return  u_field(x,             29, 25); }
 968   static int op3(      int         x)  { return  u_field(x,             24, 19); }
 969   static int rs1(      Register    r)  { return  u_field(r->encoding(), 18, 14); }
 970   static int rs2(      Register    r)  { return  u_field(r->encoding(),  4,  0); }
 971   static int annul(    bool        a)  { return  u_field(a ? 1 : 0,     29, 29); }
 972   static int cond(     int         x)  { return  u_field(x,             28, 25); }
 973   static int cond_mov( int         x)  { return  u_field(x,             17, 14); }
 974   static int rcond(    RCondition  x)  { return  u_field(x,             12, 10); }
 975   static int op2(      int         x)  { return  u_field(x,             24, 22); }
 976   static int predict(  bool        p)  { return  u_field(p ? 1 : 0,     19, 19); }
 977   static int branchcc( CC       fcca)  { return  u_field(fcca,          21, 20); }
 978   static int cmpcc(    CC       fcca)  { return  u_field(fcca,          26, 25); }
 979   static int imm_asi(  int         x)  { return  u_field(x,             12,  5); }
 980   static int immed(    bool        i)  { return  u_field(i ? 1 : 0,     13, 13); }
 981   static int opf_low6( int         w)  { return  u_field(w,             10,  5); }
 982   static int opf_low5( int         w)  { return  u_field(w,              9,  5); }
 983   static int trapcc(   CC         cc)  { return  u_field(cc,            12, 11); }
 984   static int sx(       int         i)  { return  u_field(i,             12, 12); } // shift x=1 means 64-bit
 985   static int opf(      int         x)  { return  u_field(x,             13,  5); }
 986 
 987   static bool is_cbcond( int x ) {
 988     return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
 989             inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
 990   }
 991   static bool is_cxb( int x ) {
 992     assert(is_cbcond(x), "wrong instruction");
 993     return (x & (1<<21)) != 0;
 994   }
 995   static int cond_cbcond( int         x)  { return  u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
 996   static int inv_cond_cbcond(int      x)  {
 997     assert(is_cbcond(x), "wrong instruction");
 998     return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
 999   }
1000 
1001   static int opf_cc(   CC          c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
1002   static int mov_cc(   CC          c, bool useFloat ) { return u_field(useFloat ? 0 : 1,  18, 18) | u_field(c, 12, 11); }
1003 
1004   static int fd( FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
1005   static int fs1(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
1006   static int fs2(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa),  4,  0); };
1007 
1008   // some float instructions use this encoding on the op3 field
1009   static int alt_op3(int op, FloatRegisterImpl::Width w) {
1010     int r;
1011     switch(w) {
1012      case FloatRegisterImpl::S: r = op + 0;  break;
1013      case FloatRegisterImpl::D: r = op + 3;  break;
1014      case FloatRegisterImpl::Q: r = op + 2;  break;
1015      default: ShouldNotReachHere(); break;
1016     }
1017     return op3(r);
1018   }
1019 
1020 


1032   }
1033 
1034   // compute inverse of wdisp16
1035   static intptr_t inv_wdisp16(int x, intptr_t pos) {
1036     int lo = x & (( 1 << 14 ) - 1);
1037     int hi = (x >> 20) & 3;
1038     if (hi >= 2) hi |= ~1;
1039     return (((hi << 14) | lo) << 2) + pos;
1040   }
1041 
1042   // word offset, 14 bits at LSend, 2 bits at B21, B20
1043   static int wdisp16(intptr_t x, intptr_t off) {
1044     intptr_t xx = x - off;
1045     assert_signed_word_disp_range(xx, 16);
1046     int r =  (xx >> 2) & ((1 << 14) - 1)
1047            |  (  ( (xx>>(2+14)) & 3 )  <<  20 );
1048     assert( inv_wdisp16(r, off) == x,  "inverse is not inverse");
1049     return r;
1050   }
1051 
1052   // compute inverse of wdisp10
1053   static intptr_t inv_wdisp10(int x, intptr_t pos) {
1054     assert(is_cbcond(x), "wrong instruction");
1055     int lo = inv_u_field(x, 12, 5);
1056     int hi = (x >> 19) & 3;
1057     if (hi >= 2) hi |= ~1;
1058     return (((hi << 8) | lo) << 2) + pos;
1059   }
1060 
1061   // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
1062   static int wdisp10(intptr_t x, intptr_t off) {
1063     assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
1064     intptr_t xx = x - off;
1065     assert_signed_word_disp_range(xx, 10);
1066     int r =  ( ( (xx >>  2   ) & ((1 << 8) - 1) ) <<  5 )
1067            | ( ( (xx >> (2+8)) & 3              ) << 19 );
1068     // Have to fake cbcond instruction to pass assert in inv_wdisp10()
1069     assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x,  "inverse is not inverse");
1070     return r;
1071   }
1072 
1073   // word displacement in low-order nbits bits
1074 
1075   static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
1076     int pre_sign_extend = x & (( 1 << nbits ) - 1);
1077     int r =  pre_sign_extend >= ( 1 << (nbits-1) )
1078        ?   pre_sign_extend | ~(( 1 << nbits ) - 1)
1079        :   pre_sign_extend;
1080     return (r << 2) + pos;
1081   }
1082 
1083   static int wdisp( intptr_t x, intptr_t off, int nbits ) {
1084     intptr_t xx = x - off;
1085     assert_signed_word_disp_range(xx, nbits);
1086     int r =  (xx >> 2) & (( 1 << nbits ) - 1);
1087     assert( inv_wdisp( r, off, nbits )  ==  x, "inverse not inverse");
1088     return r;
1089   }
1090 
1091 
1092   // Extract the top 32 bits in a 64 bit word


1164 
1165  protected:
1166   // Delay slot helpers
1167   // cti is called when emitting control-transfer instruction,
1168   // BEFORE doing the emitting.
1169   // Only effective when assertion-checking is enabled.
1170   void cti() {
1171 #ifdef CHECK_DELAY
1172     assert_not_delayed("cti should not be in delay slot");
1173 #endif
1174   }
1175 
1176   // called when emitting cti with a delay slot, AFTER emitting
1177   void has_delay_slot() {
1178 #ifdef CHECK_DELAY
1179     assert_not_delayed("just checking");
1180     delay_state = at_delay_slot;
1181 #endif
1182   }
1183 
1184   // cbcond instruction should not be generated one after an other
1185   bool cbcond_before() {
1186     if (offset() == 0) return false; // it is first instruction
1187     int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
1188     return is_cbcond(x);
1189   }
1190 
1191   void no_cbcond_before() {
1192     assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
1193   }
1194 
1195   bool use_cbcond(Label& L) {
1196     if (!UseCBCond || cbcond_before()) return false;
1197     intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
1198     assert( (x & 3) == 0, "not word aligned");
1199     return is_simm(x, 12);
1200   }
1201 
1202 public:
1203   // Tells assembler you know that next instruction is delayed
1204   Assembler* delayed() {
1205 #ifdef CHECK_DELAY
1206     assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
1207     delay_state = filling_delay_slot;
1208 #endif
1209     return this;
1210   }
1211 
1212   void flush() {
1213 #ifdef CHECK_DELAY
1214     assert ( delay_state == no_delay, "ending code with a delay slot");
1215 #endif
1216     AbstractAssembler::flush();
1217   }
1218 
1219   inline void emit_long(int);  // shadows AbstractAssembler::emit_long
1220   inline void emit_data(int x) { emit_long(x); }
1221   inline void emit_data(int, RelocationHolder const&);


1225 
1226 
1227  public:
1228   // instructions, refer to page numbers in the SPARC Architecture Manual, V9
1229 
1230   // pp 135 (addc was addx in v8)
1231 
1232   inline void add(Register s1, Register s2, Register d );
1233   inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1234   inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1235   inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1236   inline void add(const Address& a, Register d, int offset = 0);
1237 
1238   void addcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1239   void addcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1240   void addc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | rs2(s2) ); }
1241   void addc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1242   void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1243   void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1244 
1245 
1246   // pp 136
1247 
1248   inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
1249   inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
1250 
1251  protected: // use MacroAssembler::br instead
1252 
1253   // pp 138
1254 
1255   inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1256   inline void fb( Condition c, bool a, Label& L );
1257 
1258   // pp 141
1259 
1260   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1261   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1262 


1263   // pp 144
1264 
1265   inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1266   inline void br( Condition c, bool a, Label& L );
1267 
1268   // pp 146
1269 
1270   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1271   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1272 
1273   // pp 121 (V8)
1274 
1275   inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1276   inline void cb( Condition c, bool a, Label& L );
1277 
1278   // compare and branch
1279   inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
1280   inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
1281 
1282   // pp 149
1283 
1284   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
1285   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
1286 
1287  public:
1288 
1289   // pp 150
1290 
1291   // These instructions compare the contents of s2 with the contents of
1292   // memory at address in s1. If the values are equal, the contents of memory
1293   // at address s1 is swapped with the data in d. If the values are not equal,
1294   // the the contents of memory at s1 is loaded into d, without the swap.
1295 
1296   void casa(  Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1297   void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1298 
1299   // pp 152
1300 
1301   void udiv(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | rs2(s2)); }
1302   void udiv(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1303   void sdiv(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | rs2(s2)); }
1304   void sdiv(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1305   void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1306   void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1307   void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1308   void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }


1911   // Generates code that causes a NULL OS exception if the content of reg is NULL.
1912   // If the accessed location is M[reg + offset] and the offset is known, provide the
1913   // offset.  No explicit code generation is needed if the offset is within a certain
1914   // range (0 <= offset <= page_size).
1915   //
1916   // %%%%%% Currently not done for SPARC
1917 
1918   void null_check(Register reg, int offset = -1);
1919   static bool needs_explicit_null_check(intptr_t offset);
1920 
1921   // support for delayed instructions
1922   MacroAssembler* delayed() { Assembler::delayed();  return this; }
1923 
1924   // branches that use right instruction for v8 vs. v9
1925   inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1926   inline void br( Condition c, bool a, Predict p, Label& L );
1927 
1928   inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1929   inline void fb( Condition c, bool a, Predict p, Label& L );
1930 
1931   // compares register with zero (32 bit) and branches (V9 and V8 instructions)
1932   void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
1933   // Compares a pointer register with zero and branches on (not)null.
1934   // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1935   void br_null   ( Register s1, bool a, Predict p, Label& L );
1936   void br_notnull( Register s1, bool a, Predict p, Label& L );
1937 
1938   // These versions will do the most efficient thing on v8 and v9.  Perhaps
1939   // this is what the routine above was meant to do, but it didn't (and
1940   // didn't cover both target address kinds.)
1941   void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1942   void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
1943 
1944   //
1945   // Compare registers and branch with nop in delay slot or cbcond without delay slot.
1946   //
1947   // ATTENTION: use these instructions with caution because cbcond instruction
1948   //            has very short distance: 512 instructions (2Kbyte).
1949 
1950   // Compare integer (32 bit) values (icc only).
1951   void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
1952   void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
1953   // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64).
1954   void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
1955   void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
1956 
1957   // Short branch version for compares a pointer pwith zero.
1958   void br_null_short   ( Register s1, Predict p, Label& L );
1959   void br_notnull_short( Register s1, Predict p, Label& L );
1960 
1961   // unconditional short branch
1962   void ba_short(Label& L);
1963 
1964   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1965   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1966 
1967   // Branch that tests xcc in LP64 and icc in !LP64
1968   inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1969   inline void brx( Condition c, bool a, Predict p, Label& L );
1970 
1971   // unconditional branch
1972   inline void ba( Label& L );
1973 
1974   // Branch that tests fp condition codes
1975   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1976   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1977 
1978   // get PC the best way
1979   inline int get_pc( Register d );
1980 
1981   // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
1982   inline void cmp(  Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
1983   inline void cmp(  Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
1984 
1985   inline void jmp( Register s1, Register s2 );
1986   inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1987 
1988   // Check if the call target is out of wdisp30 range (relative to the code cache)
1989   static inline bool is_far_target(address d);
1990   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
1991   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
1992   inline void callr( Register s1, Register s2 );


2236   void serialize_memory(Register thread, Register tmp1, Register tmp2);
2237 
2238   // Stack frame creation/removal
2239   void enter();
2240   void leave();
2241 
2242   // V8/V9 integer multiply
2243   void mult(Register s1, Register s2, Register d);
2244   void mult(Register s1, int simm13a, Register d);
2245 
2246   // V8/V9 read and write of condition codes.
2247   void read_ccr(Register d);
2248   void write_ccr(Register s);
2249 
2250   // Manipulation of C++ bools
2251   // These are idioms to flag the need for care with accessing bools but on
2252   // this platform we assume byte size
2253 
2254   inline void stbool(Register d, const Address& a) { stb(d, a); }
2255   inline void ldbool(const Address& a, Register d) { ldsb(a, d); }

2256   inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
2257 
2258   // klass oop manipulations if compressed
2259   void load_klass(Register src_oop, Register klass);
2260   void store_klass(Register klass, Register dst_oop);
2261   void store_klass_gap(Register s, Register dst_oop);
2262 
2263    // oop manipulations
2264   void load_heap_oop(const Address& s, Register d);
2265   void load_heap_oop(Register s1, Register s2, Register d);
2266   void load_heap_oop(Register s1, int simm13a, Register d);
2267   void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
2268   void store_heap_oop(Register d, Register s1, Register s2);
2269   void store_heap_oop(Register d, Register s1, int simm13a);
2270   void store_heap_oop(Register d, const Address& a, int offset = 0);
2271 
2272   void encode_heap_oop(Register src, Register dst);
2273   void encode_heap_oop(Register r) {
2274     encode_heap_oop(r, r);
2275   }


2537                                Register intf_klass,
2538                                RegisterOrConstant itable_index,
2539                                Register method_result,
2540                                Register temp_reg, Register temp2_reg,
2541                                Label& no_such_interface);
2542 
2543   // Test sub_klass against super_klass, with fast and slow paths.
2544 
2545   // The fast path produces a tri-state answer: yes / no / maybe-slow.
2546   // One of the three labels can be NULL, meaning take the fall-through.
2547   // If super_check_offset is -1, the value is loaded up from super_klass.
2548   // No registers are killed, except temp_reg and temp2_reg.
2549   // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
2550   void check_klass_subtype_fast_path(Register sub_klass,
2551                                      Register super_klass,
2552                                      Register temp_reg,
2553                                      Register temp2_reg,
2554                                      Label* L_success,
2555                                      Label* L_failure,
2556                                      Label* L_slow_path,
2557                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));

2558 
2559   // The rest of the type check; must be wired to a corresponding fast path.
2560   // It does not repeat the fast path logic, so don't use it standalone.
2561   // The temp_reg can be noreg, if no temps are available.
2562   // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
2563   // Updates the sub's secondary super cache as necessary.
2564   void check_klass_subtype_slow_path(Register sub_klass,
2565                                      Register super_klass,
2566                                      Register temp_reg,
2567                                      Register temp2_reg,
2568                                      Register temp3_reg,
2569                                      Register temp4_reg,
2570                                      Label* L_success,
2571                                      Label* L_failure);
2572 
2573   // Simplified, combined version, good for typical uses.
2574   // Falls through on failure.
2575   void check_klass_subtype(Register sub_klass,
2576                            Register super_klass,
2577                            Register temp_reg,


src/cpu/sparc/vm/assembler_sparc.hpp
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