1 /*
   2  * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
  26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
  27 
  28 #include "asm/assembler.inline.hpp"
  29 #include "asm/codeBuffer.hpp"
  30 #include "code/codeCache.hpp"
  31 #include "runtime/handles.inline.hpp"
  32 
  33 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
  34   jint& stub_inst = *(jint*) branch;
  35   stub_inst = patched_branch(target - branch, stub_inst, 0);
  36 }
  37 
  38 #ifndef PRODUCT
  39 inline void MacroAssembler::pd_print_patched_instruction(address branch) {
  40   jint stub_inst = *(jint*) branch;
  41   print_instruction(stub_inst);
  42   ::tty->print("%s", " (unresolved)");
  43 }
  44 #endif // PRODUCT
  45 
  46 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
  47 
  48 
  49 inline int AddressLiteral::low10() const {
  50   return Assembler::low10(value());
  51 }
  52 
  53 
  54 // inlines for SPARC assembler -- dmu 5/97
  55 
  56 inline void Assembler::check_delay() {
  57 # ifdef CHECK_DELAY
  58   guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");
  59   delay_state = no_delay;
  60 # endif
  61 }
  62 
  63 inline void Assembler::emit_long(int x) {
  64   check_delay();
  65   AbstractAssembler::emit_long(x);
  66 }
  67 
  68 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
  69   relocate(rtype);
  70   emit_long(x);
  71 }
  72 
  73 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
  74   relocate(rspec);
  75   emit_long(x);
  76 }
  77 
  78 
  79 inline void Assembler::add(Register s1, Register s2, Register d )                             { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }
  80 inline void Assembler::add(Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }
  81 inline void Assembler::add(Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }
  82 
  83 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt);  has_delay_slot(); }
  84 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }
  85 
  86 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
  87 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }
  88 
  89 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }
  90 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }
  91 
  92 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
  93 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }
  94 
  95 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();   emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }
  96 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }
  97 
  98 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }
  99 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }
 100 
 101 inline void Assembler::call( address d,  relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt);  has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
 102 inline void Assembler::call( Label& L,   relocInfo::relocType rt ) { call( target(L), rt); }
 103 
 104 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
 105 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 106 
 107 inline void Assembler::jmpl( Register s1, Register s2, Register d                          ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2));  has_delay_slot(); }
 108 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec);  has_delay_slot(); }
 109 
 110 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d) {
 111   if (s2.is_register()) ldf(w, s1, s2.as_register(), d);
 112   else                  ldf(w, s1, s2.as_constant(), d);
 113 }
 114 
 115 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
 116 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); }
 117 
 118 inline void Assembler::ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }
 119 
 120 inline void Assembler::ldfsr(  Register s1, Register s2) { v9_dep();   emit_long( op(ldst_op) |             op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
 121 inline void Assembler::ldfsr(  Register s1, int simm13a) { v9_dep();   emit_data( op(ldst_op) |             op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 122 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(G1)    | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
 123 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(G1)    | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 124 
 125 inline void Assembler::ldc(   Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3  ) | rs1(s1) | rs2(s2) ); }
 126 inline void Assembler::ldc(   Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 127 inline void Assembler::lddc(  Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); }
 128 inline void Assembler::lddc(  Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 129 inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); }
 130 inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 131 
 132 inline void Assembler::ldsb(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }
 133 inline void Assembler::ldsb(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 134 
 135 inline void Assembler::ldsh(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }
 136 inline void Assembler::ldsh(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 137 inline void Assembler::ldsw(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }
 138 inline void Assembler::ldsw(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 139 inline void Assembler::ldub(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }
 140 inline void Assembler::ldub(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 141 inline void Assembler::lduh(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }
 142 inline void Assembler::lduh(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 143 inline void Assembler::lduw(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }
 144 inline void Assembler::lduw(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 145 
 146 inline void Assembler::ldx(   Register s1, Register s2, Register d) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }
 147 inline void Assembler::ldx(   Register s1, int simm13a, Register d) { v9_only();  emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 148 inline void Assembler::ldd(   Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }
 149 inline void Assembler::ldd(   Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 150 
 151 #ifdef _LP64
 152 // Make all 32 bit loads signed so 64 bit registers maintain proper sign
 153 inline void Assembler::ld(  Register s1, Register s2, Register d)      { ldsw( s1, s2, d); }
 154 inline void Assembler::ld(  Register s1, int simm13a, Register d)      { ldsw( s1, simm13a, d); }
 155 #else
 156 inline void Assembler::ld(  Register s1, Register s2, Register d)      { lduw( s1, s2, d); }
 157 inline void Assembler::ld(  Register s1, int simm13a, Register d)      { lduw( s1, simm13a, d); }
 158 #endif
 159 
 160 #ifdef ASSERT
 161   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 162 # ifdef _LP64
 163 inline void Assembler::ld(  Register s1, ByteSize simm13a, Register d) { ldsw( s1, in_bytes(simm13a), d); }
 164 # else
 165 inline void Assembler::ld(  Register s1, ByteSize simm13a, Register d) { lduw( s1, in_bytes(simm13a), d); }
 166 # endif
 167 #endif
 168 
 169 inline void Assembler::ld(  const Address& a, Register d, int offset) {
 170   if (a.has_index()) { assert(offset == 0, ""); ld(  a.base(), a.index(),         d); }
 171   else               {                          ld(  a.base(), a.disp() + offset, d); }
 172 }
 173 inline void Assembler::ldsb(const Address& a, Register d, int offset) {
 174   if (a.has_index()) { assert(offset == 0, ""); ldsb(a.base(), a.index(),         d); }
 175   else               {                          ldsb(a.base(), a.disp() + offset, d); }
 176 }
 177 inline void Assembler::ldsh(const Address& a, Register d, int offset) {
 178   if (a.has_index()) { assert(offset == 0, ""); ldsh(a.base(), a.index(),         d); }
 179   else               {                          ldsh(a.base(), a.disp() + offset, d); }
 180 }
 181 inline void Assembler::ldsw(const Address& a, Register d, int offset) {
 182   if (a.has_index()) { assert(offset == 0, ""); ldsw(a.base(), a.index(),         d); }
 183   else               {                          ldsw(a.base(), a.disp() + offset, d); }
 184 }
 185 inline void Assembler::ldub(const Address& a, Register d, int offset) {
 186   if (a.has_index()) { assert(offset == 0, ""); ldub(a.base(), a.index(),         d); }
 187   else               {                          ldub(a.base(), a.disp() + offset, d); }
 188 }
 189 inline void Assembler::lduh(const Address& a, Register d, int offset) {
 190   if (a.has_index()) { assert(offset == 0, ""); lduh(a.base(), a.index(),         d); }
 191   else               {                          lduh(a.base(), a.disp() + offset, d); }
 192 }
 193 inline void Assembler::lduw(const Address& a, Register d, int offset) {
 194   if (a.has_index()) { assert(offset == 0, ""); lduw(a.base(), a.index(),         d); }
 195   else               {                          lduw(a.base(), a.disp() + offset, d); }
 196 }
 197 inline void Assembler::ldd( const Address& a, Register d, int offset) {
 198   if (a.has_index()) { assert(offset == 0, ""); ldd( a.base(), a.index(),         d); }
 199   else               {                          ldd( a.base(), a.disp() + offset, d); }
 200 }
 201 inline void Assembler::ldx( const Address& a, Register d, int offset) {
 202   if (a.has_index()) { assert(offset == 0, ""); ldx( a.base(), a.index(),         d); }
 203   else               {                          ldx( a.base(), a.disp() + offset, d); }
 204 }
 205 
 206 inline void Assembler::ldub(Register s1, RegisterOrConstant s2, Register d) { ldub(Address(s1, s2), d); }
 207 inline void Assembler::ldsb(Register s1, RegisterOrConstant s2, Register d) { ldsb(Address(s1, s2), d); }
 208 inline void Assembler::lduh(Register s1, RegisterOrConstant s2, Register d) { lduh(Address(s1, s2), d); }
 209 inline void Assembler::ldsh(Register s1, RegisterOrConstant s2, Register d) { ldsh(Address(s1, s2), d); }
 210 inline void Assembler::lduw(Register s1, RegisterOrConstant s2, Register d) { lduw(Address(s1, s2), d); }
 211 inline void Assembler::ldsw(Register s1, RegisterOrConstant s2, Register d) { ldsw(Address(s1, s2), d); }
 212 inline void Assembler::ldx( Register s1, RegisterOrConstant s2, Register d) { ldx( Address(s1, s2), d); }
 213 inline void Assembler::ld(  Register s1, RegisterOrConstant s2, Register d) { ld(  Address(s1, s2), d); }
 214 inline void Assembler::ldd( Register s1, RegisterOrConstant s2, Register d) { ldd( Address(s1, s2), d); }
 215 
 216 // form effective addresses this way:
 217 inline void Assembler::add(const Address& a, Register d, int offset) {
 218   if (a.has_index())   add(a.base(), a.index(),         d);
 219   else               { add(a.base(), a.disp() + offset, d, a.rspec(offset)); offset = 0; }
 220   if (offset != 0)     add(d,        offset,            d);
 221 }
 222 inline void Assembler::add(Register s1, RegisterOrConstant s2, Register d, int offset) {
 223   if (s2.is_register())  add(s1, s2.as_register(),          d);
 224   else                 { add(s1, s2.as_constant() + offset, d); offset = 0; }
 225   if (offset != 0)       add(d,  offset,                    d);
 226 }
 227 
 228 inline void Assembler::andn(Register s1, RegisterOrConstant s2, Register d) {
 229   if (s2.is_register())  andn(s1, s2.as_register(), d);
 230   else                   andn(s1, s2.as_constant(), d);
 231 }
 232 
 233 inline void Assembler::ldstub(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); }
 234 inline void Assembler::ldstub(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 235 
 236 
 237 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only();  emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
 238 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only();  emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 239 
 240 inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); }
 241 
 242 
 243 inline void Assembler::rett( Register s1, Register s2                         ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2));  has_delay_slot(); }
 244 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt);  has_delay_slot(); }
 245 
 246 inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }
 247 
 248   // pp 222
 249 
 250 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2) {
 251   if (s2.is_register()) stf(w, d, s1, s2.as_register());
 252   else                  stf(w, d, s1, s2.as_constant());
 253 }
 254 
 255 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }
 256 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 257 
 258 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) {
 259   relocate(a.rspec(offset));
 260   if (a.has_index()) { assert(offset == 0, ""); stf(w, d, a.base(), a.index()        ); }
 261   else               {                          stf(w, d, a.base(), a.disp() + offset); }
 262 }
 263 
 264 inline void Assembler::stfsr(  Register s1, Register s2) { v9_dep();   emit_long( op(ldst_op) |             op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
 265 inline void Assembler::stfsr(  Register s1, int simm13a) { v9_dep();   emit_data( op(ldst_op) |             op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 266 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(G1)    | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
 267 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(G1)    | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 268 
 269   // p 226
 270 
 271 inline void Assembler::stb(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }
 272 inline void Assembler::stb(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 273 inline void Assembler::sth(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }
 274 inline void Assembler::sth(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 275 inline void Assembler::stw(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }
 276 inline void Assembler::stw(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 277 
 278 
 279 inline void Assembler::stx(  Register d, Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }
 280 inline void Assembler::stx(  Register d, Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 281 inline void Assembler::std(  Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }
 282 inline void Assembler::std(  Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 283 
 284 inline void Assembler::st( Register d, Register s1, Register s2)      { stw(d, s1, s2); }
 285 inline void Assembler::st( Register d, Register s1, int simm13a)      { stw(d, s1, simm13a); }
 286 
 287 #ifdef ASSERT
 288 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 289 inline void Assembler::st( Register d, Register s1, ByteSize simm13a) { stw(d, s1, in_bytes(simm13a)); }
 290 #endif
 291 
 292 inline void Assembler::stb(Register d, const Address& a, int offset) {
 293   if (a.has_index()) { assert(offset == 0, ""); stb(d, a.base(), a.index()        ); }
 294   else               {                          stb(d, a.base(), a.disp() + offset); }
 295 }
 296 inline void Assembler::sth(Register d, const Address& a, int offset) {
 297   if (a.has_index()) { assert(offset == 0, ""); sth(d, a.base(), a.index()        ); }
 298   else               {                          sth(d, a.base(), a.disp() + offset); }
 299 }
 300 inline void Assembler::stw(Register d, const Address& a, int offset) {
 301   if (a.has_index()) { assert(offset == 0, ""); stw(d, a.base(), a.index()        ); }
 302   else               {                          stw(d, a.base(), a.disp() + offset); }
 303 }
 304 inline void Assembler::st( Register d, const Address& a, int offset) {
 305   if (a.has_index()) { assert(offset == 0, ""); st( d, a.base(), a.index()        ); }
 306   else               {                          st( d, a.base(), a.disp() + offset); }
 307 }
 308 inline void Assembler::std(Register d, const Address& a, int offset) {
 309   if (a.has_index()) { assert(offset == 0, ""); std(d, a.base(), a.index()        ); }
 310   else               {                          std(d, a.base(), a.disp() + offset); }
 311 }
 312 inline void Assembler::stx(Register d, const Address& a, int offset) {
 313   if (a.has_index()) { assert(offset == 0, ""); stx(d, a.base(), a.index()        ); }
 314   else               {                          stx(d, a.base(), a.disp() + offset); }
 315 }
 316 
 317 inline void Assembler::stb(Register d, Register s1, RegisterOrConstant s2) { stb(d, Address(s1, s2)); }
 318 inline void Assembler::sth(Register d, Register s1, RegisterOrConstant s2) { sth(d, Address(s1, s2)); }
 319 inline void Assembler::stw(Register d, Register s1, RegisterOrConstant s2) { stw(d, Address(s1, s2)); }
 320 inline void Assembler::stx(Register d, Register s1, RegisterOrConstant s2) { stx(d, Address(s1, s2)); }
 321 inline void Assembler::std(Register d, Register s1, RegisterOrConstant s2) { std(d, Address(s1, s2)); }
 322 inline void Assembler::st( Register d, Register s1, RegisterOrConstant s2) { st( d, Address(s1, s2)); }
 323 
 324 // v8 p 99
 325 
 326 inline void Assembler::stc(    int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); }
 327 inline void Assembler::stc(    int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 328 inline void Assembler::stdc(   int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); }
 329 inline void Assembler::stdc(   int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 330 inline void Assembler::stcsr(  int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); }
 331 inline void Assembler::stcsr(  int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 332 inline void Assembler::stdcq(  int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); }
 333 inline void Assembler::stdcq(  int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 334 
 335 inline void Assembler::sub(Register s1, RegisterOrConstant s2, Register d, int offset) {
 336   if (s2.is_register())  sub(s1, s2.as_register(),          d);
 337   else                 { sub(s1, s2.as_constant() + offset, d); offset = 0; }
 338   if (offset != 0)       sub(d,  offset,                    d);
 339 }
 340 
 341 // pp 231
 342 
 343 inline void Assembler::swap(    Register s1, Register s2, Register d) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }
 344 inline void Assembler::swap(    Register s1, int simm13a, Register d) { v9_dep();  emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 345 
 346 inline void Assembler::swap(    Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap(  a.base(), a.disp() + offset, d ); }
 347 
 348 
 349 // Use the right loads/stores for the platform
 350 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {
 351 #ifdef _LP64
 352   Assembler::ldx(s1, s2, d);
 353 #else
 354   Assembler::ld( s1, s2, d);
 355 #endif
 356 }
 357 
 358 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {
 359 #ifdef _LP64
 360   Assembler::ldx(s1, simm13a, d);
 361 #else
 362   Assembler::ld( s1, simm13a, d);
 363 #endif
 364 }
 365 
 366 #ifdef ASSERT
 367 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 368 inline void MacroAssembler::ld_ptr( Register s1, ByteSize simm13a, Register d ) {
 369   ld_ptr(s1, in_bytes(simm13a), d);
 370 }
 371 #endif
 372 
 373 inline void MacroAssembler::ld_ptr( Register s1, RegisterOrConstant s2, Register d ) {
 374 #ifdef _LP64
 375   Assembler::ldx(s1, s2, d);
 376 #else
 377   Assembler::ld( s1, s2, d);
 378 #endif
 379 }
 380 
 381 inline void MacroAssembler::ld_ptr(const Address& a, Register d, int offset) {
 382 #ifdef _LP64
 383   Assembler::ldx(a, d, offset);
 384 #else
 385   Assembler::ld( a, d, offset);
 386 #endif
 387 }
 388 
 389 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {
 390 #ifdef _LP64
 391   Assembler::stx(d, s1, s2);
 392 #else
 393   Assembler::st( d, s1, s2);
 394 #endif
 395 }
 396 
 397 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {
 398 #ifdef _LP64
 399   Assembler::stx(d, s1, simm13a);
 400 #else
 401   Assembler::st( d, s1, simm13a);
 402 #endif
 403 }
 404 
 405 #ifdef ASSERT
 406 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 407 inline void MacroAssembler::st_ptr( Register d, Register s1, ByteSize simm13a ) {
 408   st_ptr(d, s1, in_bytes(simm13a));
 409 }
 410 #endif
 411 
 412 inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterOrConstant s2 ) {
 413 #ifdef _LP64
 414   Assembler::stx(d, s1, s2);
 415 #else
 416   Assembler::st( d, s1, s2);
 417 #endif
 418 }
 419 
 420 inline void MacroAssembler::st_ptr(Register d, const Address& a, int offset) {
 421 #ifdef _LP64
 422   Assembler::stx(d, a, offset);
 423 #else
 424   Assembler::st( d, a, offset);
 425 #endif
 426 }
 427 
 428 // Use the right loads/stores for the platform
 429 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {
 430 #ifdef _LP64
 431   Assembler::ldx(s1, s2, d);
 432 #else
 433   Assembler::ldd(s1, s2, d);
 434 #endif
 435 }
 436 
 437 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {
 438 #ifdef _LP64
 439   Assembler::ldx(s1, simm13a, d);
 440 #else
 441   Assembler::ldd(s1, simm13a, d);
 442 #endif
 443 }
 444 
 445 inline void MacroAssembler::ld_long( Register s1, RegisterOrConstant s2, Register d ) {
 446 #ifdef _LP64
 447   Assembler::ldx(s1, s2, d);
 448 #else
 449   Assembler::ldd(s1, s2, d);
 450 #endif
 451 }
 452 
 453 inline void MacroAssembler::ld_long(const Address& a, Register d, int offset) {
 454 #ifdef _LP64
 455   Assembler::ldx(a, d, offset);
 456 #else
 457   Assembler::ldd(a, d, offset);
 458 #endif
 459 }
 460 
 461 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {
 462 #ifdef _LP64
 463   Assembler::stx(d, s1, s2);
 464 #else
 465   Assembler::std(d, s1, s2);
 466 #endif
 467 }
 468 
 469 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {
 470 #ifdef _LP64
 471   Assembler::stx(d, s1, simm13a);
 472 #else
 473   Assembler::std(d, s1, simm13a);
 474 #endif
 475 }
 476 
 477 inline void MacroAssembler::st_long( Register d, Register s1, RegisterOrConstant s2 ) {
 478 #ifdef _LP64
 479   Assembler::stx(d, s1, s2);
 480 #else
 481   Assembler::std(d, s1, s2);
 482 #endif
 483 }
 484 
 485 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {
 486 #ifdef _LP64
 487   Assembler::stx(d, a, offset);
 488 #else
 489   Assembler::std(d, a, offset);
 490 #endif
 491 }
 492 
 493 // Functions for isolating 64 bit shifts for LP64
 494 
 495 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {
 496 #ifdef _LP64
 497   Assembler::sllx(s1, s2, d);
 498 #else
 499   Assembler::sll( s1, s2, d);
 500 #endif
 501 }
 502 
 503 inline void MacroAssembler::sll_ptr( Register s1, int imm6a,   Register d ) {
 504 #ifdef _LP64
 505   Assembler::sllx(s1, imm6a, d);
 506 #else
 507   Assembler::sll( s1, imm6a, d);
 508 #endif
 509 }
 510 
 511 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {
 512 #ifdef _LP64
 513   Assembler::srlx(s1, s2, d);
 514 #else
 515   Assembler::srl( s1, s2, d);
 516 #endif
 517 }
 518 
 519 inline void MacroAssembler::srl_ptr( Register s1, int imm6a,   Register d ) {
 520 #ifdef _LP64
 521   Assembler::srlx(s1, imm6a, d);
 522 #else
 523   Assembler::srl( s1, imm6a, d);
 524 #endif
 525 }
 526 
 527 inline void MacroAssembler::sll_ptr( Register s1, RegisterOrConstant s2, Register d ) {
 528   if (s2.is_register())  sll_ptr(s1, s2.as_register(), d);
 529   else                   sll_ptr(s1, s2.as_constant(), d);
 530 }
 531 
 532 // Use the right branch for the platform
 533 
 534 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 535   if (VM_Version::v9_instructions_work())
 536     Assembler::bp(c, a, icc, p, d, rt);
 537   else
 538     Assembler::br(c, a, d, rt);
 539 }
 540 
 541 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
 542   br(c, a, p, target(L));
 543 }
 544 
 545 
 546 // Branch that tests either xcc or icc depending on the
 547 // architecture compiled (LP64 or not)
 548 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 549 #ifdef _LP64
 550     Assembler::bp(c, a, xcc, p, d, rt);
 551 #else
 552     MacroAssembler::br(c, a, p, d, rt);
 553 #endif
 554 }
 555 
 556 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
 557   brx(c, a, p, target(L));
 558 }
 559 
 560 inline void MacroAssembler::ba( bool a, Label& L ) {
 561   br(always, a, pt, L);
 562 }
 563 
 564 // Warning: V9 only functions
 565 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
 566   Assembler::bp(c, a, cc, p, d, rt);
 567 }
 568 
 569 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
 570   Assembler::bp(c, a, cc, p, L);
 571 }
 572 
 573 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 574   if (VM_Version::v9_instructions_work())
 575     fbp(c, a, fcc0, p, d, rt);
 576   else
 577     Assembler::fb(c, a, d, rt);
 578 }
 579 
 580 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
 581   fb(c, a, p, target(L));
 582 }
 583 
 584 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
 585   Assembler::fbp(c, a, cc, p, d, rt);
 586 }
 587 
 588 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
 589   Assembler::fbp(c, a, cc, p, L);
 590 }
 591 
 592 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
 593 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
 594 
 595 inline bool MacroAssembler::is_far_target(address d) {
 596   return !is_in_wdisp30_range(d, CodeCache::low_bound()) || !is_in_wdisp30_range(d, CodeCache::high_bound());
 597 }
 598 
 599 // Call with a check to see if we need to deal with the added
 600 // expense of relocation and if we overflow the displacement
 601 // of the quick call instruction.
 602 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {
 603 #ifdef _LP64
 604   intptr_t disp;
 605   // NULL is ok because it will be relocated later.
 606   // Must change NULL to a reachable address in order to
 607   // pass asserts here and in wdisp.
 608   if ( d == NULL )
 609     d = pc();
 610 
 611   // Is this address within range of the call instruction?
 612   // If not, use the expensive instruction sequence
 613   if (is_far_target(d)) {
 614     relocate(rt);
 615     AddressLiteral dest(d);
 616     jumpl_to(dest, O7, O7);
 617   } else {
 618     Assembler::call(d, rt);
 619   }
 620 #else
 621   Assembler::call( d, rt );
 622 #endif
 623 }
 624 
 625 inline void MacroAssembler::call( Label& L,   relocInfo::relocType rt ) {
 626   MacroAssembler::call( target(L), rt);
 627 }
 628 
 629 
 630 
 631 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
 632 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
 633 
 634 // prefetch instruction
 635 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
 636   if (VM_Version::v9_instructions_work())
 637     Assembler::bp( never, true, xcc, pt, d, rt );
 638 }
 639 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
 640 
 641 
 642 // clobbers o7 on V8!!
 643 // returns delta from gotten pc to addr after
 644 inline int MacroAssembler::get_pc( Register d ) {
 645   int x = offset();
 646   if (VM_Version::v9_instructions_work())
 647     rdpc(d);
 648   else {
 649     Label lbl;
 650     Assembler::call(lbl, relocInfo::none);  // No relocation as this is call to pc+0x8
 651     if (d == O7)  delayed()->nop();
 652     else          delayed()->mov(O7, d);
 653     bind(lbl);
 654   }
 655   return offset() - x;
 656 }
 657 
 658 
 659 // Note:  All MacroAssembler::set_foo functions are defined out-of-line.
 660 
 661 
 662 // Loads the current PC of the following instruction as an immediate value in
 663 // 2 instructions.  All PCs in the CodeCache are within 2 Gig of each other.
 664 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
 665   intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
 666 #ifdef _LP64
 667   Unimplemented();
 668 #else
 669   Assembler::sethi(  thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));
 670   Assembler::add(reg,thepc &  0x3ff, reg, internal_word_Relocation::spec((address)thepc));
 671 #endif
 672   return thepc;
 673 }
 674 
 675 
 676 inline void MacroAssembler::load_contents(const AddressLiteral& addrlit, Register d, int offset) {
 677   assert_not_delayed();
 678   sethi(addrlit, d);
 679   ld(d, addrlit.low10() + offset, d);
 680 }
 681 
 682 
 683 inline void MacroAssembler::load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset) {
 684   assert_not_delayed();
 685   sethi(addrlit, d);
 686   ld_ptr(d, addrlit.low10() + offset, d);
 687 }
 688 
 689 
 690 inline void MacroAssembler::store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) {
 691   assert_not_delayed();
 692   sethi(addrlit, temp);
 693   st(s, temp, addrlit.low10() + offset);
 694 }
 695 
 696 
 697 inline void MacroAssembler::store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) {
 698   assert_not_delayed();
 699   sethi(addrlit, temp);
 700   st_ptr(s, temp, addrlit.low10() + offset);
 701 }
 702 
 703 
 704 // This code sequence is relocatable to any address, even on LP64.
 705 inline void MacroAssembler::jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset) {
 706   assert_not_delayed();
 707   // Force fixed length sethi because NativeJump and NativeFarCall don't handle
 708   // variable length instruction streams.
 709   patchable_sethi(addrlit, temp);
 710   jmpl(temp, addrlit.low10() + offset, d);
 711 }
 712 
 713 
 714 inline void MacroAssembler::jump_to(const AddressLiteral& addrlit, Register temp, int offset) {
 715   jumpl_to(addrlit, temp, G0, offset);
 716 }
 717 
 718 
 719 inline void MacroAssembler::jump_indirect_to(Address& a, Register temp,
 720                                              int ld_offset, int jmp_offset) {
 721   assert_not_delayed();
 722   //sethi(al);                   // sethi is caller responsibility for this one
 723   ld_ptr(a, temp, ld_offset);
 724   jmp(temp, jmp_offset);
 725 }
 726 
 727 
 728 inline void MacroAssembler::set_oop(jobject obj, Register d) {
 729   set_oop(allocate_oop_address(obj), d);
 730 }
 731 
 732 
 733 inline void MacroAssembler::set_oop_constant(jobject obj, Register d) {
 734   set_oop(constant_oop_address(obj), d);
 735 }
 736 
 737 
 738 inline void MacroAssembler::set_oop(const AddressLiteral& obj_addr, Register d) {
 739   assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
 740   set(obj_addr, d);
 741 }
 742 
 743 
 744 inline void MacroAssembler::load_argument( Argument& a, Register  d ) {
 745   if (a.is_register())
 746     mov(a.as_register(), d);
 747   else
 748     ld (a.as_address(),  d);
 749 }
 750 
 751 inline void MacroAssembler::store_argument( Register s, Argument& a ) {
 752   if (a.is_register())
 753     mov(s, a.as_register());
 754   else
 755     st_ptr (s, a.as_address());         // ABI says everything is right justified.
 756 }
 757 
 758 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {
 759   if (a.is_register())
 760     mov(s, a.as_register());
 761   else
 762     st_ptr (s, a.as_address());
 763 }
 764 
 765 
 766 #ifdef _LP64
 767 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {
 768   if (a.is_float_register())
 769 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2
 770     fmov(FloatRegisterImpl::S, s, a.as_float_register() );
 771   else
 772     // Floats are stored in the high half of the stack entry
 773     // The low half is undefined per the ABI.
 774     stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));
 775 }
 776 
 777 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {
 778   if (a.is_float_register())
 779 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2
 780     fmov(FloatRegisterImpl::D, s, a.as_double_register() );
 781   else
 782     stf(FloatRegisterImpl::D, s, a.as_address());
 783 }
 784 
 785 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {
 786   if (a.is_register())
 787     mov(s, a.as_register());
 788   else
 789     stx(s, a.as_address());
 790 }
 791 #endif
 792 
 793 inline void MacroAssembler::clrb( Register s1, Register s2) {  stb( G0, s1, s2 ); }
 794 inline void MacroAssembler::clrh( Register s1, Register s2) {  sth( G0, s1, s2 ); }
 795 inline void MacroAssembler::clr(  Register s1, Register s2) {  stw( G0, s1, s2 ); }
 796 inline void MacroAssembler::clrx( Register s1, Register s2) {  stx( G0, s1, s2 ); }
 797 
 798 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }
 799 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }
 800 inline void MacroAssembler::clr(  Register s1, int simm13a) { stw( G0, s1, simm13a); }
 801 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }
 802 
 803 // returns if membar generates anything, obviously this code should mirror
 804 // membar below.
 805 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {
 806   if( !os::is_MP() ) return false;  // Not needed on single CPU
 807   if( VM_Version::v9_instructions_work() ) {
 808     const Membar_mask_bits effective_mask =
 809         Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
 810     return (effective_mask != 0);
 811   } else {
 812     return true;
 813   }
 814 }
 815 
 816 inline void MacroAssembler::membar( Membar_mask_bits const7a ) {
 817   // Uniprocessors do not need memory barriers
 818   if (!os::is_MP()) return;
 819   // Weakened for current Sparcs and TSO.  See the v9 manual, sections 8.4.3,
 820   // 8.4.4.3, a.31 and a.50.
 821   if( VM_Version::v9_instructions_work() ) {
 822     // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value
 823     // of the mmask subfield of const7a that does anything that isn't done
 824     // implicitly is StoreLoad.
 825     const Membar_mask_bits effective_mask =
 826         Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
 827     if ( effective_mask != 0 ) {
 828       Assembler::membar( effective_mask );
 829     }
 830   } else {
 831     // stbar is the closest there is on v8.  Equivalent to membar(StoreStore).  We
 832     // do not issue the stbar because to my knowledge all v8 machines implement TSO,
 833     // which guarantees that all stores behave as if an stbar were issued just after
 834     // each one of them.  On these machines, stbar ought to be a nop.  There doesn't
 835     // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
 836     // it can't be specified by stbar, nor have I come up with a way to simulate it.
 837     //
 838     // Addendum.  Dave says that ldstub guarantees a write buffer flush to coherent
 839     // space.  Put one here to be on the safe side.
 840     Assembler::ldstub(SP, 0, G0);
 841   }
 842 }
 843 
 844 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP