1 //
   2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved.
   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
   6 // under the terms of the GNU General Public License version 2 only, as
   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
  17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // SPARC Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 register %{
  32 //----------Architecture Description Register Definitions----------------------
  33 // General Registers
  34 // "reg_def"  name ( register save type, C convention save type,
  35 //                   ideal register type, encoding, vm name );
  36 // Register Save Types:
  37 //
  38 // NS  = No-Save:       The register allocator assumes that these registers
  39 //                      can be used without saving upon entry to the method, &
  40 //                      that they do not need to be saved at call sites.
  41 //
  42 // SOC = Save-On-Call:  The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method,
  44 //                      but that they must be saved at call sites.
  45 //
  46 // SOE = Save-On-Entry: The register allocator assumes that these registers
  47 //                      must be saved before using them upon entry to the
  48 //                      method, but they do not need to be saved at call
  49 //                      sites.
  50 //
  51 // AS  = Always-Save:   The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, & that they must be saved at call sites.
  54 //
  55 // Ideal Register Type is used to determine how to save & restore a
  56 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  57 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  58 //
  59 // The encoding number is the actual bit-pattern placed into the opcodes.
  60 
  61 
  62 // ----------------------------
  63 // Integer/Long Registers
  64 // ----------------------------
  65 
  66 // Need to expose the hi/lo aspect of 64-bit registers
  67 // This register set is used for both the 64-bit build and
  68 // the 32-bit build with 1-register longs.
  69 
  70 // Global Registers 0-7
  71 reg_def R_G0H( NS,  NS, Op_RegI,128, G0->as_VMReg()->next());
  72 reg_def R_G0 ( NS,  NS, Op_RegI,  0, G0->as_VMReg());
  73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
  74 reg_def R_G1 (SOC, SOC, Op_RegI,  1, G1->as_VMReg());
  75 reg_def R_G2H( NS,  NS, Op_RegI,130, G2->as_VMReg()->next());
  76 reg_def R_G2 ( NS,  NS, Op_RegI,  2, G2->as_VMReg());
  77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
  78 reg_def R_G3 (SOC, SOC, Op_RegI,  3, G3->as_VMReg());
  79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
  80 reg_def R_G4 (SOC, SOC, Op_RegI,  4, G4->as_VMReg());
  81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
  82 reg_def R_G5 (SOC, SOC, Op_RegI,  5, G5->as_VMReg());
  83 reg_def R_G6H( NS,  NS, Op_RegI,134, G6->as_VMReg()->next());
  84 reg_def R_G6 ( NS,  NS, Op_RegI,  6, G6->as_VMReg());
  85 reg_def R_G7H( NS,  NS, Op_RegI,135, G7->as_VMReg()->next());
  86 reg_def R_G7 ( NS,  NS, Op_RegI,  7, G7->as_VMReg());
  87 
  88 // Output Registers 0-7
  89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
  90 reg_def R_O0 (SOC, SOC, Op_RegI,  8, O0->as_VMReg());
  91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
  92 reg_def R_O1 (SOC, SOC, Op_RegI,  9, O1->as_VMReg());
  93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
  94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
  95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
  96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
  97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
  98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
  99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
 101 reg_def R_SPH( NS,  NS, Op_RegI,142, SP->as_VMReg()->next());
 102 reg_def R_SP ( NS,  NS, Op_RegI, 14, SP->as_VMReg());
 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
 105 
 106 // Local Registers 0-7
 107 reg_def R_L0H( NS,  NS, Op_RegI,144, L0->as_VMReg()->next());
 108 reg_def R_L0 ( NS,  NS, Op_RegI, 16, L0->as_VMReg());
 109 reg_def R_L1H( NS,  NS, Op_RegI,145, L1->as_VMReg()->next());
 110 reg_def R_L1 ( NS,  NS, Op_RegI, 17, L1->as_VMReg());
 111 reg_def R_L2H( NS,  NS, Op_RegI,146, L2->as_VMReg()->next());
 112 reg_def R_L2 ( NS,  NS, Op_RegI, 18, L2->as_VMReg());
 113 reg_def R_L3H( NS,  NS, Op_RegI,147, L3->as_VMReg()->next());
 114 reg_def R_L3 ( NS,  NS, Op_RegI, 19, L3->as_VMReg());
 115 reg_def R_L4H( NS,  NS, Op_RegI,148, L4->as_VMReg()->next());
 116 reg_def R_L4 ( NS,  NS, Op_RegI, 20, L4->as_VMReg());
 117 reg_def R_L5H( NS,  NS, Op_RegI,149, L5->as_VMReg()->next());
 118 reg_def R_L5 ( NS,  NS, Op_RegI, 21, L5->as_VMReg());
 119 reg_def R_L6H( NS,  NS, Op_RegI,150, L6->as_VMReg()->next());
 120 reg_def R_L6 ( NS,  NS, Op_RegI, 22, L6->as_VMReg());
 121 reg_def R_L7H( NS,  NS, Op_RegI,151, L7->as_VMReg()->next());
 122 reg_def R_L7 ( NS,  NS, Op_RegI, 23, L7->as_VMReg());
 123 
 124 // Input Registers 0-7
 125 reg_def R_I0H( NS,  NS, Op_RegI,152, I0->as_VMReg()->next());
 126 reg_def R_I0 ( NS,  NS, Op_RegI, 24, I0->as_VMReg());
 127 reg_def R_I1H( NS,  NS, Op_RegI,153, I1->as_VMReg()->next());
 128 reg_def R_I1 ( NS,  NS, Op_RegI, 25, I1->as_VMReg());
 129 reg_def R_I2H( NS,  NS, Op_RegI,154, I2->as_VMReg()->next());
 130 reg_def R_I2 ( NS,  NS, Op_RegI, 26, I2->as_VMReg());
 131 reg_def R_I3H( NS,  NS, Op_RegI,155, I3->as_VMReg()->next());
 132 reg_def R_I3 ( NS,  NS, Op_RegI, 27, I3->as_VMReg());
 133 reg_def R_I4H( NS,  NS, Op_RegI,156, I4->as_VMReg()->next());
 134 reg_def R_I4 ( NS,  NS, Op_RegI, 28, I4->as_VMReg());
 135 reg_def R_I5H( NS,  NS, Op_RegI,157, I5->as_VMReg()->next());
 136 reg_def R_I5 ( NS,  NS, Op_RegI, 29, I5->as_VMReg());
 137 reg_def R_FPH( NS,  NS, Op_RegI,158, FP->as_VMReg()->next());
 138 reg_def R_FP ( NS,  NS, Op_RegI, 30, FP->as_VMReg());
 139 reg_def R_I7H( NS,  NS, Op_RegI,159, I7->as_VMReg()->next());
 140 reg_def R_I7 ( NS,  NS, Op_RegI, 31, I7->as_VMReg());
 141 
 142 // ----------------------------
 143 // Float/Double Registers
 144 // ----------------------------
 145 
 146 // Float Registers
 147 reg_def R_F0 ( SOC, SOC, Op_RegF,  0, F0->as_VMReg());
 148 reg_def R_F1 ( SOC, SOC, Op_RegF,  1, F1->as_VMReg());
 149 reg_def R_F2 ( SOC, SOC, Op_RegF,  2, F2->as_VMReg());
 150 reg_def R_F3 ( SOC, SOC, Op_RegF,  3, F3->as_VMReg());
 151 reg_def R_F4 ( SOC, SOC, Op_RegF,  4, F4->as_VMReg());
 152 reg_def R_F5 ( SOC, SOC, Op_RegF,  5, F5->as_VMReg());
 153 reg_def R_F6 ( SOC, SOC, Op_RegF,  6, F6->as_VMReg());
 154 reg_def R_F7 ( SOC, SOC, Op_RegF,  7, F7->as_VMReg());
 155 reg_def R_F8 ( SOC, SOC, Op_RegF,  8, F8->as_VMReg());
 156 reg_def R_F9 ( SOC, SOC, Op_RegF,  9, F9->as_VMReg());
 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
 179 
 180 // Double Registers
 181 // The rules of ADL require that double registers be defined in pairs.
 182 // Each pair must be two 32-bit values, but not necessarily a pair of
 183 // single float registers.  In each pair, ADLC-assigned register numbers
 184 // must be adjacent, with the lower number even.  Finally, when the
 185 // CPU stores such a register pair to memory, the word associated with
 186 // the lower ADLC-assigned number must be stored to the lower address.
 187 
 188 // These definitions specify the actual bit encodings of the sparc
 189 // double fp register numbers.  FloatRegisterImpl in register_sparc.hpp
 190 // wants 0-63, so we have to convert every time we want to use fp regs
 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
 192 // 255 is a flag meaning "don't go here".
 193 // I believe we can't handle callee-save doubles D32 and up until
 194 // the place in the sparc stack crawler that asserts on the 255 is
 195 // fixed up.
 196 reg_def R_D32 (SOC, SOC, Op_RegD,  1, F32->as_VMReg());
 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
 198 reg_def R_D34 (SOC, SOC, Op_RegD,  3, F34->as_VMReg());
 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
 200 reg_def R_D36 (SOC, SOC, Op_RegD,  5, F36->as_VMReg());
 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
 202 reg_def R_D38 (SOC, SOC, Op_RegD,  7, F38->as_VMReg());
 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
 204 reg_def R_D40 (SOC, SOC, Op_RegD,  9, F40->as_VMReg());
 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
 228 
 229 
 230 // ----------------------------
 231 // Special Registers
 232 // Condition Codes Flag Registers
 233 // I tried to break out ICC and XCC but it's not very pretty.
 234 // Every Sparc instruction which defs/kills one also kills the other.
 235 // Hence every compare instruction which defs one kind of flags ends
 236 // up needing a kill of the other.
 237 reg_def CCR (SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
 238 
 239 reg_def FCC0(SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
 240 reg_def FCC1(SOC, SOC,  Op_RegFlags, 1, VMRegImpl::Bad());
 241 reg_def FCC2(SOC, SOC,  Op_RegFlags, 2, VMRegImpl::Bad());
 242 reg_def FCC3(SOC, SOC,  Op_RegFlags, 3, VMRegImpl::Bad());
 243 
 244 // ----------------------------
 245 // Specify the enum values for the registers.  These enums are only used by the
 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
 247 // for visibility to the rest of the vm. The order of this enum influences the
 248 // register allocator so having the freedom to set this order and not be stuck
 249 // with the order that is natural for the rest of the vm is worth it.
 250 alloc_class chunk0(
 251   R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
 252   R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
 253   R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
 254   R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
 255 
 256 // Note that a register is not allocatable unless it is also mentioned
 257 // in a widely-used reg_class below.  Thus, R_G7 and R_G0 are outside i_reg.
 258 
 259 alloc_class chunk1(
 260   // The first registers listed here are those most likely to be used
 261   // as temporaries.  We move F0..F7 away from the front of the list,
 262   // to reduce the likelihood of interferences with parameters and
 263   // return values.  Likewise, we avoid using F0/F1 for parameters,
 264   // since they are used for return values.
 265   // This FPU fine-tuning is worth about 1% on the SPEC geomean.
 266   R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 267   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
 268   R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
 269   R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
 270   R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
 271   R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
 272   R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
 273   R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
 274 
 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
 276 
 277 //----------Architecture Description Register Classes--------------------------
 278 // Several register classes are automatically defined based upon information in
 279 // this architecture description.
 280 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 283 //
 284 
 285 // G0 is not included in integer class since it has special meaning.
 286 reg_class g0_reg(R_G0);
 287 
 288 // ----------------------------
 289 // Integer Register Classes
 290 // ----------------------------
 291 // Exclusions from i_reg:
 292 // R_G0: hardwired zero
 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
 294 // R_G6: reserved by Solaris ABI to tools
 295 // R_G7: reserved by Solaris ABI to libthread
 296 // R_O7: Used as a temp in many encodings
 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 298 
 299 // Class for all integer registers, except the G registers.  This is used for
 300 // encodings which use G registers as temps.  The regular inputs to such
 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
 302 // will not put an input into a temp register.
 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 304 
 305 reg_class g1_regI(R_G1);
 306 reg_class g3_regI(R_G3);
 307 reg_class g4_regI(R_G4);
 308 reg_class o0_regI(R_O0);
 309 reg_class o7_regI(R_O7);
 310 
 311 // ----------------------------
 312 // Pointer Register Classes
 313 // ----------------------------
 314 #ifdef _LP64
 315 // 64-bit build means 64-bit pointers means hi/lo pairs
 316 reg_class ptr_reg(            R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
 317                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
 318                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 319                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
 320 // Lock encodings use G3 and G4 internally
 321 reg_class lock_ptr_reg(       R_G1H,R_G1,                                     R_G5H,R_G5,
 322                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
 323                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 324                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
 325 // Special class for storeP instructions, which can store SP or RPC to TLS.
 326 // It is also used for memory addressing, allowing direct TLS addressing.
 327 reg_class sp_ptr_reg(         R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
 328                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
 329                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 330                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
 332 // We use it to save R_G2 across calls out of Java.
 333 reg_class l7_regP(R_L7H,R_L7);
 334 
 335 // Other special pointer regs
 336 reg_class g1_regP(R_G1H,R_G1);
 337 reg_class g2_regP(R_G2H,R_G2);
 338 reg_class g3_regP(R_G3H,R_G3);
 339 reg_class g4_regP(R_G4H,R_G4);
 340 reg_class g5_regP(R_G5H,R_G5);
 341 reg_class i0_regP(R_I0H,R_I0);
 342 reg_class o0_regP(R_O0H,R_O0);
 343 reg_class o1_regP(R_O1H,R_O1);
 344 reg_class o2_regP(R_O2H,R_O2);
 345 reg_class o7_regP(R_O7H,R_O7);
 346 
 347 #else // _LP64
 348 // 32-bit build means 32-bit pointers means 1 register.
 349 reg_class ptr_reg(     R_G1,     R_G3,R_G4,R_G5,
 350                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
 351                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 352                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 353 // Lock encodings use G3 and G4 internally
 354 reg_class lock_ptr_reg(R_G1,               R_G5,
 355                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
 356                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 357                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 358 // Special class for storeP instructions, which can store SP or RPC to TLS.
 359 // It is also used for memory addressing, allowing direct TLS addressing.
 360 reg_class sp_ptr_reg(  R_G1,R_G2,R_G3,R_G4,R_G5,
 361                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
 362                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 363                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
 365 // We use it to save R_G2 across calls out of Java.
 366 reg_class l7_regP(R_L7);
 367 
 368 // Other special pointer regs
 369 reg_class g1_regP(R_G1);
 370 reg_class g2_regP(R_G2);
 371 reg_class g3_regP(R_G3);
 372 reg_class g4_regP(R_G4);
 373 reg_class g5_regP(R_G5);
 374 reg_class i0_regP(R_I0);
 375 reg_class o0_regP(R_O0);
 376 reg_class o1_regP(R_O1);
 377 reg_class o2_regP(R_O2);
 378 reg_class o7_regP(R_O7);
 379 #endif // _LP64
 380 
 381 
 382 // ----------------------------
 383 // Long Register Classes
 384 // ----------------------------
 385 // Longs in 1 register.  Aligned adjacent hi/lo pairs.
 386 // Note:  O7 is never in this class; it is sometimes used as an encoding temp.
 387 reg_class long_reg(             R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
 388                    ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
 389 #ifdef _LP64
 390 // 64-bit, longs in 1 register: use all 64-bit integer registers
 391 // 32-bit, longs in 1 register: cannot use I's and L's.  Restrict to O's and G's.
 392                    ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
 393                    ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
 394 #endif // _LP64
 395                   );
 396 
 397 reg_class g1_regL(R_G1H,R_G1);
 398 reg_class g3_regL(R_G3H,R_G3);
 399 reg_class o2_regL(R_O2H,R_O2);
 400 reg_class o7_regL(R_O7H,R_O7);
 401 
 402 // ----------------------------
 403 // Special Class for Condition Code Flags Register
 404 reg_class int_flags(CCR);
 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
 406 reg_class float_flag0(FCC0);
 407 
 408 
 409 // ----------------------------
 410 // Float Point Register Classes
 411 // ----------------------------
 412 // Skip F30/F31, they are reserved for mem-mem copies
 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 414 
 415 // Paired floating point registers--they show up in the same order as the floats,
 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 418                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
 419                    /* Use extra V9 double registers; this AD file does not support V8 */
 420                    R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
 421                    R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
 422                    );
 423 
 424 // Paired floating point registers--they show up in the same order as the floats,
 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 426 // This class is usable for mis-aligned loads as happen in I2C adapters.
 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 428                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 429 %}
 430 
 431 //----------DEFINITION BLOCK---------------------------------------------------
 432 // Define name --> value mappings to inform the ADLC of an integer valued name
 433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 434 // Format:
 435 //        int_def  <name>         ( <int_value>, <expression>);
 436 // Generated Code in ad_<arch>.hpp
 437 //        #define  <name>   (<expression>)
 438 //        // value == <int_value>
 439 // Generated code in ad_<arch>.cpp adlc_verification()
 440 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 441 //
 442 definitions %{
 443 // The default cost (of an ALU instruction).
 444   int_def DEFAULT_COST      (    100,     100);
 445   int_def HUGE_COST         (1000000, 1000000);
 446 
 447 // Memory refs are twice as expensive as run-of-the-mill.
 448   int_def MEMORY_REF_COST   (    200, DEFAULT_COST * 2);
 449 
 450 // Branches are even more expensive.
 451   int_def BRANCH_COST       (    300, DEFAULT_COST * 3);
 452   int_def CALL_COST         (    300, DEFAULT_COST * 3);
 453 %}
 454 
 455 
 456 //----------SOURCE BLOCK-------------------------------------------------------
 457 // This is a block of C++ code which provides values, functions, and
 458 // definitions necessary in the rest of the architecture description
 459 source_hpp %{
 460 // Must be visible to the DFA in dfa_sparc.cpp
 461 extern bool can_branch_register( Node *bol, Node *cmp );
 462 
 463 // Macros to extract hi & lo halves from a long pair.
 464 // G0 is not part of any long pair, so assert on that.
 465 // Prevents accidentally using G1 instead of G0.
 466 #define LONG_HI_REG(x) (x)
 467 #define LONG_LO_REG(x) (x)
 468 
 469 %}
 470 
 471 source %{
 472 #define __ _masm.
 473 
 474 // Block initializing store
 475 #define ASI_BLK_INIT_QUAD_LDD_P    0xE2
 476 
 477 // tertiary op of a LoadP or StoreP encoding
 478 #define REGP_OP true
 479 
 480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
 481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
 482 static Register reg_to_register_object(int register_encoding);
 483 
 484 // Used by the DFA in dfa_sparc.cpp.
 485 // Check for being able to use a V9 branch-on-register.  Requires a
 486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
 487 // extended.  Doesn't work following an integer ADD, for example, because of
 488 // overflow (-1 incremented yields 0 plus a carry in the high-order word).  On
 489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
 490 // replace them with zero, which could become sign-extension in a different OS
 491 // release.  There's no obvious reason why an interrupt will ever fill these
 492 // bits with non-zero junk (the registers are reloaded with standard LD
 493 // instructions which either zero-fill or sign-fill).
 494 bool can_branch_register( Node *bol, Node *cmp ) {
 495   if( !BranchOnRegister ) return false;
 496 #ifdef _LP64
 497   if( cmp->Opcode() == Op_CmpP )
 498     return true;  // No problems with pointer compares
 499 #endif
 500   if( cmp->Opcode() == Op_CmpL )
 501     return true;  // No problems with long compares
 502 
 503   if( !SparcV9RegsHiBitsZero ) return false;
 504   if( bol->as_Bool()->_test._test != BoolTest::ne &&
 505       bol->as_Bool()->_test._test != BoolTest::eq )
 506      return false;
 507 
 508   // Check for comparing against a 'safe' value.  Any operation which
 509   // clears out the high word is safe.  Thus, loads and certain shifts
 510   // are safe, as are non-negative constants.  Any operation which
 511   // preserves zero bits in the high word is safe as long as each of its
 512   // inputs are safe.  Thus, phis and bitwise booleans are safe if their
 513   // inputs are safe.  At present, the only important case to recognize
 514   // seems to be loads.  Constants should fold away, and shifts &
 515   // logicals can use the 'cc' forms.
 516   Node *x = cmp->in(1);
 517   if( x->is_Load() ) return true;
 518   if( x->is_Phi() ) {
 519     for( uint i = 1; i < x->req(); i++ )
 520       if( !x->in(i)->is_Load() )
 521         return false;
 522     return true;
 523   }
 524   return false;
 525 }
 526 
 527 // ****************************************************************************
 528 
 529 // REQUIRED FUNCTIONALITY
 530 
 531 // !!!!! Special hack to get all type of calls to specify the byte offset
 532 //       from the start of the call to the point where the return address
 533 //       will point.
 534 //       The "return address" is the address of the call instruction, plus 8.
 535 
 536 int MachCallStaticJavaNode::ret_addr_offset() {
 537   int offset = NativeCall::instruction_size;  // call; delay slot
 538   if (_method_handle_invoke)
 539     offset += 4;  // restore SP
 540   return offset;
 541 }
 542 
 543 int MachCallDynamicJavaNode::ret_addr_offset() {
 544   int vtable_index = this->_vtable_index;
 545   if (vtable_index < 0) {
 546     // must be invalid_vtable_index, not nonvirtual_vtable_index
 547     assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
 548     return (NativeMovConstReg::instruction_size +
 549            NativeCall::instruction_size);  // sethi; setlo; call; delay slot
 550   } else {
 551     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 552     int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
 553     int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
 554     int klass_load_size;
 555     if (UseCompressedOops) {
 556       assert(Universe::heap() != NULL, "java heap should be initialized");
 557       if (Universe::narrow_oop_base() == NULL)
 558         klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
 559       else
 560         klass_load_size = 3*BytesPerInstWord;
 561     } else {
 562       klass_load_size = 1*BytesPerInstWord;
 563     }
 564     if( Assembler::is_simm13(v_off) ) {
 565       return klass_load_size +
 566              (2*BytesPerInstWord +           // ld_ptr, ld_ptr
 567              NativeCall::instruction_size);  // call; delay slot
 568     } else {
 569       return klass_load_size +
 570              (4*BytesPerInstWord +           // set_hi, set, ld_ptr, ld_ptr
 571              NativeCall::instruction_size);  // call; delay slot
 572     }
 573   }
 574 }
 575 
 576 int MachCallRuntimeNode::ret_addr_offset() {
 577 #ifdef _LP64
 578   if (MacroAssembler::is_far_target(entry_point())) {
 579     return NativeFarCall::instruction_size;
 580   } else {
 581     return NativeCall::instruction_size;
 582   }
 583 #else
 584   return NativeCall::instruction_size;  // call; delay slot
 585 #endif
 586 }
 587 
 588 // Indicate if the safepoint node needs the polling page as an input.
 589 // Since Sparc does not have absolute addressing, it does.
 590 bool SafePointNode::needs_polling_address_input() {
 591   return true;
 592 }
 593 
 594 // emit an interrupt that is caught by the debugger (for debugging compiler)
 595 void emit_break(CodeBuffer &cbuf) {
 596   MacroAssembler _masm(&cbuf);
 597   __ breakpoint_trap();
 598 }
 599 
 600 #ifndef PRODUCT
 601 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
 602   st->print("TA");
 603 }
 604 #endif
 605 
 606 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 607   emit_break(cbuf);
 608 }
 609 
 610 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 611   return MachNode::size(ra_);
 612 }
 613 
 614 // Traceable jump
 615 void  emit_jmpl(CodeBuffer &cbuf, int jump_target) {
 616   MacroAssembler _masm(&cbuf);
 617   Register rdest = reg_to_register_object(jump_target);
 618   __ JMP(rdest, 0);
 619   __ delayed()->nop();
 620 }
 621 
 622 // Traceable jump and set exception pc
 623 void  emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
 624   MacroAssembler _masm(&cbuf);
 625   Register rdest = reg_to_register_object(jump_target);
 626   __ JMP(rdest, 0);
 627   __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
 628 }
 629 
 630 void emit_nop(CodeBuffer &cbuf) {
 631   MacroAssembler _masm(&cbuf);
 632   __ nop();
 633 }
 634 
 635 void emit_illtrap(CodeBuffer &cbuf) {
 636   MacroAssembler _masm(&cbuf);
 637   __ illtrap(0);
 638 }
 639 
 640 
 641 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
 642   assert(n->rule() != loadUB_rule, "");
 643 
 644   intptr_t offset = 0;
 645   const TypePtr *adr_type = TYPE_PTR_SENTINAL;  // Check for base==RegI, disp==immP
 646   const Node* addr = n->get_base_and_disp(offset, adr_type);
 647   assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
 648   assert(addr != NULL && addr != (Node*)-1, "invalid addr");
 649   assert(addr->bottom_type()->isa_oopptr() == atype, "");
 650   atype = atype->add_offset(offset);
 651   assert(disp32 == offset, "wrong disp32");
 652   return atype->_offset;
 653 }
 654 
 655 
 656 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
 657   assert(n->rule() != loadUB_rule, "");
 658 
 659   intptr_t offset = 0;
 660   Node* addr = n->in(2);
 661   assert(addr->bottom_type()->isa_oopptr() == atype, "");
 662   if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
 663     Node* a = addr->in(2/*AddPNode::Address*/);
 664     Node* o = addr->in(3/*AddPNode::Offset*/);
 665     offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
 666     atype = a->bottom_type()->is_ptr()->add_offset(offset);
 667     assert(atype->isa_oop_ptr(), "still an oop");
 668   }
 669   offset = atype->is_ptr()->_offset;
 670   if (offset != Type::OffsetBot)  offset += disp32;
 671   return offset;
 672 }
 673 
 674 static inline jdouble replicate_immI(int con, int count, int width) {
 675   // Load a constant replicated "count" times with width "width"
 676   int bit_width = width * 8;
 677   jlong elt_val = con;
 678   elt_val &= (((jlong) 1) << bit_width) - 1;  // mask off sign bits
 679   jlong val = elt_val;
 680   for (int i = 0; i < count - 1; i++) {
 681     val <<= bit_width;
 682     val |= elt_val;
 683   }
 684   jdouble dval = *((jdouble*) &val);  // coerce to double type
 685   return dval;
 686 }
 687 
 688 // Standard Sparc opcode form2 field breakdown
 689 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
 690   f0 &= (1<<19)-1;     // Mask displacement to 19 bits
 691   int op = (f30 << 30) |
 692            (f29 << 29) |
 693            (f25 << 25) |
 694            (f22 << 22) |
 695            (f20 << 20) |
 696            (f19 << 19) |
 697            (f0  <<  0);
 698   cbuf.insts()->emit_int32(op);
 699 }
 700 
 701 // Standard Sparc opcode form2 field breakdown
 702 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
 703   f0 >>= 10;           // Drop 10 bits
 704   f0 &= (1<<22)-1;     // Mask displacement to 22 bits
 705   int op = (f30 << 30) |
 706            (f25 << 25) |
 707            (f22 << 22) |
 708            (f0  <<  0);
 709   cbuf.insts()->emit_int32(op);
 710 }
 711 
 712 // Standard Sparc opcode form3 field breakdown
 713 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
 714   int op = (f30 << 30) |
 715            (f25 << 25) |
 716            (f19 << 19) |
 717            (f14 << 14) |
 718            (f5  <<  5) |
 719            (f0  <<  0);
 720   cbuf.insts()->emit_int32(op);
 721 }
 722 
 723 // Standard Sparc opcode form3 field breakdown
 724 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
 725   simm13 &= (1<<13)-1; // Mask to 13 bits
 726   int op = (f30 << 30) |
 727            (f25 << 25) |
 728            (f19 << 19) |
 729            (f14 << 14) |
 730            (1   << 13) | // bit to indicate immediate-mode
 731            (simm13<<0);
 732   cbuf.insts()->emit_int32(op);
 733 }
 734 
 735 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
 736   simm10 &= (1<<10)-1; // Mask to 10 bits
 737   emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
 738 }
 739 
 740 #ifdef ASSERT
 741 // Helper function for VerifyOops in emit_form3_mem_reg
 742 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
 743   warning("VerifyOops encountered unexpected instruction:");
 744   n->dump(2);
 745   warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
 746 }
 747 #endif
 748 
 749 
 750 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
 751                         int src1_enc, int disp32, int src2_enc, int dst_enc) {
 752 
 753 #ifdef ASSERT
 754   // The following code implements the +VerifyOops feature.
 755   // It verifies oop values which are loaded into or stored out of
 756   // the current method activation.  +VerifyOops complements techniques
 757   // like ScavengeALot, because it eagerly inspects oops in transit,
 758   // as they enter or leave the stack, as opposed to ScavengeALot,
 759   // which inspects oops "at rest", in the stack or heap, at safepoints.
 760   // For this reason, +VerifyOops can sometimes detect bugs very close
 761   // to their point of creation.  It can also serve as a cross-check
 762   // on the validity of oop maps, when used toegether with ScavengeALot.
 763 
 764   // It would be good to verify oops at other points, especially
 765   // when an oop is used as a base pointer for a load or store.
 766   // This is presently difficult, because it is hard to know when
 767   // a base address is biased or not.  (If we had such information,
 768   // it would be easy and useful to make a two-argument version of
 769   // verify_oop which unbiases the base, and performs verification.)
 770 
 771   assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
 772   bool is_verified_oop_base  = false;
 773   bool is_verified_oop_load  = false;
 774   bool is_verified_oop_store = false;
 775   int tmp_enc = -1;
 776   if (VerifyOops && src1_enc != R_SP_enc) {
 777     // classify the op, mainly for an assert check
 778     int st_op = 0, ld_op = 0;
 779     switch (primary) {
 780     case Assembler::stb_op3:  st_op = Op_StoreB; break;
 781     case Assembler::sth_op3:  st_op = Op_StoreC; break;
 782     case Assembler::stx_op3:  // may become StoreP or stay StoreI or StoreD0
 783     case Assembler::stw_op3:  st_op = Op_StoreI; break;
 784     case Assembler::std_op3:  st_op = Op_StoreL; break;
 785     case Assembler::stf_op3:  st_op = Op_StoreF; break;
 786     case Assembler::stdf_op3: st_op = Op_StoreD; break;
 787 
 788     case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
 789     case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
 790     case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
 791     case Assembler::ldx_op3:  // may become LoadP or stay LoadI
 792     case Assembler::ldsw_op3: // may become LoadP or stay LoadI
 793     case Assembler::lduw_op3: ld_op = Op_LoadI; break;
 794     case Assembler::ldd_op3:  ld_op = Op_LoadL; break;
 795     case Assembler::ldf_op3:  ld_op = Op_LoadF; break;
 796     case Assembler::lddf_op3: ld_op = Op_LoadD; break;
 797     case Assembler::ldub_op3: ld_op = Op_LoadB; break;
 798     case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
 799 
 800     default: ShouldNotReachHere();
 801     }
 802     if (tertiary == REGP_OP) {
 803       if      (st_op == Op_StoreI)  st_op = Op_StoreP;
 804       else if (ld_op == Op_LoadI)   ld_op = Op_LoadP;
 805       else                          ShouldNotReachHere();
 806       if (st_op) {
 807         // a store
 808         // inputs are (0:control, 1:memory, 2:address, 3:value)
 809         Node* n2 = n->in(3);
 810         if (n2 != NULL) {
 811           const Type* t = n2->bottom_type();
 812           is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
 813         }
 814       } else {
 815         // a load
 816         const Type* t = n->bottom_type();
 817         is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
 818       }
 819     }
 820 
 821     if (ld_op) {
 822       // a Load
 823       // inputs are (0:control, 1:memory, 2:address)
 824       if (!(n->ideal_Opcode()==ld_op)       && // Following are special cases
 825           !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
 826           !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
 827           !(n->ideal_Opcode()==Op_LoadI     && ld_op==Op_LoadF) &&
 828           !(n->ideal_Opcode()==Op_LoadF     && ld_op==Op_LoadI) &&
 829           !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
 830           !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
 831           !(n->ideal_Opcode()==Op_LoadL     && ld_op==Op_LoadI) &&
 832           !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
 833           !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
 834           !(n->ideal_Opcode()==Op_ConvI2F   && ld_op==Op_LoadF) &&
 835           !(n->ideal_Opcode()==Op_ConvI2D   && ld_op==Op_LoadF) &&
 836           !(n->ideal_Opcode()==Op_PrefetchRead  && ld_op==Op_LoadI) &&
 837           !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
 838           !(n->ideal_Opcode()==Op_Load2I    && ld_op==Op_LoadD) &&
 839           !(n->ideal_Opcode()==Op_Load4C    && ld_op==Op_LoadD) &&
 840           !(n->ideal_Opcode()==Op_Load4S    && ld_op==Op_LoadD) &&
 841           !(n->ideal_Opcode()==Op_Load8B    && ld_op==Op_LoadD) &&
 842           !(n->rule() == loadUB_rule)) {
 843         verify_oops_warning(n, n->ideal_Opcode(), ld_op);
 844       }
 845     } else if (st_op) {
 846       // a Store
 847       // inputs are (0:control, 1:memory, 2:address, 3:value)
 848       if (!(n->ideal_Opcode()==st_op)    && // Following are special cases
 849           !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
 850           !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
 851           !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
 852           !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
 853           !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
 854           !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
 855           !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
 856           !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
 857         verify_oops_warning(n, n->ideal_Opcode(), st_op);
 858       }
 859     }
 860 
 861     if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
 862       Node* addr = n->in(2);
 863       if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
 864         const TypeOopPtr* atype = addr->bottom_type()->isa_instptr();  // %%% oopptr?
 865         if (atype != NULL) {
 866           intptr_t offset = get_offset_from_base(n, atype, disp32);
 867           intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
 868           if (offset != offset_2) {
 869             get_offset_from_base(n, atype, disp32);
 870             get_offset_from_base_2(n, atype, disp32);
 871           }
 872           assert(offset == offset_2, "different offsets");
 873           if (offset == disp32) {
 874             // we now know that src1 is a true oop pointer
 875             is_verified_oop_base = true;
 876             if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
 877               if( primary == Assembler::ldd_op3 ) {
 878                 is_verified_oop_base = false; // Cannot 'ldd' into O7
 879               } else {
 880                 tmp_enc = dst_enc;
 881                 dst_enc = R_O7_enc; // Load into O7; preserve source oop
 882                 assert(src1_enc != dst_enc, "");
 883               }
 884             }
 885           }
 886           if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
 887                        || offset == oopDesc::mark_offset_in_bytes())) {
 888                       // loading the mark should not be allowed either, but
 889                       // we don't check this since it conflicts with InlineObjectHash
 890                       // usage of LoadINode to get the mark. We could keep the
 891                       // check if we create a new LoadMarkNode
 892             // but do not verify the object before its header is initialized
 893             ShouldNotReachHere();
 894           }
 895         }
 896       }
 897     }
 898   }
 899 #endif
 900 
 901   uint instr;
 902   instr = (Assembler::ldst_op << 30)
 903         | (dst_enc        << 25)
 904         | (primary        << 19)
 905         | (src1_enc       << 14);
 906 
 907   uint index = src2_enc;
 908   int disp = disp32;
 909 
 910   if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
 911     disp += STACK_BIAS;
 912 
 913   // We should have a compiler bailout here rather than a guarantee.
 914   // Better yet would be some mechanism to handle variable-size matches correctly.
 915   guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
 916 
 917   if( disp == 0 ) {
 918     // use reg-reg form
 919     // bit 13 is already zero
 920     instr |= index;
 921   } else {
 922     // use reg-imm form
 923     instr |= 0x00002000;          // set bit 13 to one
 924     instr |= disp & 0x1FFF;
 925   }
 926 
 927   cbuf.insts()->emit_int32(instr);
 928 
 929 #ifdef ASSERT
 930   {
 931     MacroAssembler _masm(&cbuf);
 932     if (is_verified_oop_base) {
 933       __ verify_oop(reg_to_register_object(src1_enc));
 934     }
 935     if (is_verified_oop_store) {
 936       __ verify_oop(reg_to_register_object(dst_enc));
 937     }
 938     if (tmp_enc != -1) {
 939       __ mov(O7, reg_to_register_object(tmp_enc));
 940     }
 941     if (is_verified_oop_load) {
 942       __ verify_oop(reg_to_register_object(dst_enc));
 943     }
 944   }
 945 #endif
 946 }
 947 
 948 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
 949   // The method which records debug information at every safepoint
 950   // expects the call to be the first instruction in the snippet as
 951   // it creates a PcDesc structure which tracks the offset of a call
 952   // from the start of the codeBlob. This offset is computed as
 953   // code_end() - code_begin() of the code which has been emitted
 954   // so far.
 955   // In this particular case we have skirted around the problem by
 956   // putting the "mov" instruction in the delay slot but the problem
 957   // may bite us again at some other point and a cleaner/generic
 958   // solution using relocations would be needed.
 959   MacroAssembler _masm(&cbuf);
 960   __ set_inst_mark();
 961 
 962   // We flush the current window just so that there is a valid stack copy
 963   // the fact that the current window becomes active again instantly is
 964   // not a problem there is nothing live in it.
 965 
 966 #ifdef ASSERT
 967   int startpos = __ offset();
 968 #endif /* ASSERT */
 969 
 970   __ call((address)entry_point, rtype);
 971 
 972   if (preserve_g2)   __ delayed()->mov(G2, L7);
 973   else __ delayed()->nop();
 974 
 975   if (preserve_g2)   __ mov(L7, G2);
 976 
 977 #ifdef ASSERT
 978   if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
 979 #ifdef _LP64
 980     // Trash argument dump slots.
 981     __ set(0xb0b8ac0db0b8ac0d, G1);
 982     __ mov(G1, G5);
 983     __ stx(G1, SP, STACK_BIAS + 0x80);
 984     __ stx(G1, SP, STACK_BIAS + 0x88);
 985     __ stx(G1, SP, STACK_BIAS + 0x90);
 986     __ stx(G1, SP, STACK_BIAS + 0x98);
 987     __ stx(G1, SP, STACK_BIAS + 0xA0);
 988     __ stx(G1, SP, STACK_BIAS + 0xA8);
 989 #else // _LP64
 990     // this is also a native call, so smash the first 7 stack locations,
 991     // and the various registers
 992 
 993     // Note:  [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
 994     // while [SP+0x44..0x58] are the argument dump slots.
 995     __ set((intptr_t)0xbaadf00d, G1);
 996     __ mov(G1, G5);
 997     __ sllx(G1, 32, G1);
 998     __ or3(G1, G5, G1);
 999     __ mov(G1, G5);
1000     __ stx(G1, SP, 0x40);
1001     __ stx(G1, SP, 0x48);
1002     __ stx(G1, SP, 0x50);
1003     __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1004 #endif // _LP64
1005   }
1006 #endif /*ASSERT*/
1007 }
1008 
1009 //=============================================================================
1010 // REQUIRED FUNCTIONALITY for encoding
1011 void emit_lo(CodeBuffer &cbuf, int val) {  }
1012 void emit_hi(CodeBuffer &cbuf, int val) {  }
1013 
1014 
1015 //=============================================================================
1016 const bool Matcher::constant_table_absolute_addressing = false;
1017 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
1018 
1019 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1020   Compile* C = ra_->C;
1021   Compile::ConstantTable& constant_table = C->constant_table();
1022   MacroAssembler _masm(&cbuf);
1023 
1024   Register r = as_Register(ra_->get_encode(this));
1025   CodeSection* cs = __ code()->consts();
1026   int consts_size = cs->align_at_start(cs->size());
1027 
1028   if (UseRDPCForConstantTableBase) {
1029     // For the following RDPC logic to work correctly the consts
1030     // section must be allocated right before the insts section.  This
1031     // assert checks for that.  The layout and the SECT_* constants
1032     // are defined in src/share/vm/asm/codeBuffer.hpp.
1033     assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1034     int offset = __ offset();
1035     int disp;
1036 
1037     // If the displacement from the current PC to the constant table
1038     // base fits into simm13 we set the constant table base to the
1039     // current PC.
1040     if (__ is_simm13(-(consts_size + offset))) {
1041       constant_table.set_table_base_offset(-(consts_size + offset));
1042       disp = 0;
1043     } else {
1044       // If the offset of the top constant (last entry in the table)
1045       // fits into simm13 we set the constant table base to the actual
1046       // table base.
1047       if (__ is_simm13(constant_table.top_offset())) {
1048         constant_table.set_table_base_offset(0);
1049         disp = consts_size + offset;
1050       } else {
1051         // Otherwise we set the constant table base in the middle of the
1052         // constant table.
1053         int half_consts_size = consts_size / 2;
1054         assert(half_consts_size * 2 == consts_size, "sanity");
1055         constant_table.set_table_base_offset(-half_consts_size);  // table base offset gets added to the load displacement.
1056         disp = half_consts_size + offset;
1057       }
1058     }
1059 
1060     __ rdpc(r);
1061 
1062     if (disp != 0) {
1063       assert(r != O7, "need temporary");
1064       __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1065     }
1066   }
1067   else {
1068     // Materialize the constant table base.
1069     assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1070     address baseaddr = cs->start() + -(constant_table.table_base_offset());
1071     RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1072     AddressLiteral base(baseaddr, rspec);
1073     __ set(base, r);
1074   }
1075 }
1076 
1077 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1078   if (UseRDPCForConstantTableBase) {
1079     // This is really the worst case but generally it's only 1 instruction.
1080     return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1081   } else {
1082     return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1083   }
1084 }
1085 
1086 #ifndef PRODUCT
1087 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1088   char reg[128];
1089   ra_->dump_register(this, reg);
1090   if (UseRDPCForConstantTableBase) {
1091     st->print("RDPC   %s\t! constant table base", reg);
1092   } else {
1093     st->print("SET    &constanttable,%s\t! constant table base", reg);
1094   }
1095 }
1096 #endif
1097 
1098 
1099 //=============================================================================
1100 
1101 #ifndef PRODUCT
1102 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1103   Compile* C = ra_->C;
1104 
1105   for (int i = 0; i < OptoPrologueNops; i++) {
1106     st->print_cr("NOP"); st->print("\t");
1107   }
1108 
1109   if( VerifyThread ) {
1110     st->print_cr("Verify_Thread"); st->print("\t");
1111   }
1112 
1113   size_t framesize = C->frame_slots() << LogBytesPerInt;
1114 
1115   // Calls to C2R adapters often do not accept exceptional returns.
1116   // We require that their callers must bang for them.  But be careful, because
1117   // some VM calls (such as call site linkage) can use several kilobytes of
1118   // stack.  But the stack safety zone should account for that.
1119   // See bugs 4446381, 4468289, 4497237.
1120   if (C->need_stack_bang(framesize)) {
1121     st->print_cr("! stack bang"); st->print("\t");
1122   }
1123 
1124   if (Assembler::is_simm13(-framesize)) {
1125     st->print   ("SAVE   R_SP,-%d,R_SP",framesize);
1126   } else {
1127     st->print_cr("SETHI  R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1128     st->print_cr("ADD    R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1129     st->print   ("SAVE   R_SP,R_G3,R_SP");
1130   }
1131 
1132 }
1133 #endif
1134 
1135 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1136   Compile* C = ra_->C;
1137   MacroAssembler _masm(&cbuf);
1138 
1139   for (int i = 0; i < OptoPrologueNops; i++) {
1140     __ nop();
1141   }
1142 
1143   __ verify_thread();
1144 
1145   size_t framesize = C->frame_slots() << LogBytesPerInt;
1146   assert(framesize >= 16*wordSize, "must have room for reg. save area");
1147   assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1148 
1149   // Calls to C2R adapters often do not accept exceptional returns.
1150   // We require that their callers must bang for them.  But be careful, because
1151   // some VM calls (such as call site linkage) can use several kilobytes of
1152   // stack.  But the stack safety zone should account for that.
1153   // See bugs 4446381, 4468289, 4497237.
1154   if (C->need_stack_bang(framesize)) {
1155     __ generate_stack_overflow_check(framesize);
1156   }
1157 
1158   if (Assembler::is_simm13(-framesize)) {
1159     __ save(SP, -framesize, SP);
1160   } else {
1161     __ sethi(-framesize & ~0x3ff, G3);
1162     __ add(G3, -framesize & 0x3ff, G3);
1163     __ save(SP, G3, SP);
1164   }
1165   C->set_frame_complete( __ offset() );
1166 }
1167 
1168 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1169   return MachNode::size(ra_);
1170 }
1171 
1172 int MachPrologNode::reloc() const {
1173   return 10; // a large enough number
1174 }
1175 
1176 //=============================================================================
1177 #ifndef PRODUCT
1178 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1179   Compile* C = ra_->C;
1180 
1181   if( do_polling() && ra_->C->is_method_compilation() ) {
1182     st->print("SETHI  #PollAddr,L0\t! Load Polling address\n\t");
1183 #ifdef _LP64
1184     st->print("LDX    [L0],G0\t!Poll for Safepointing\n\t");
1185 #else
1186     st->print("LDUW   [L0],G0\t!Poll for Safepointing\n\t");
1187 #endif
1188   }
1189 
1190   if( do_polling() )
1191     st->print("RET\n\t");
1192 
1193   st->print("RESTORE");
1194 }
1195 #endif
1196 
1197 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1198   MacroAssembler _masm(&cbuf);
1199   Compile* C = ra_->C;
1200 
1201   __ verify_thread();
1202 
1203   // If this does safepoint polling, then do it here
1204   if( do_polling() && ra_->C->is_method_compilation() ) {
1205     AddressLiteral polling_page(os::get_polling_page());
1206     __ sethi(polling_page, L0);
1207     __ relocate(relocInfo::poll_return_type);
1208     __ ld_ptr( L0, 0, G0 );
1209   }
1210 
1211   // If this is a return, then stuff the restore in the delay slot
1212   if( do_polling() ) {
1213     __ ret();
1214     __ delayed()->restore();
1215   } else {
1216     __ restore();
1217   }
1218 }
1219 
1220 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1221   return MachNode::size(ra_);
1222 }
1223 
1224 int MachEpilogNode::reloc() const {
1225   return 16; // a large enough number
1226 }
1227 
1228 const Pipeline * MachEpilogNode::pipeline() const {
1229   return MachNode::pipeline_class();
1230 }
1231 
1232 int MachEpilogNode::safepoint_offset() const {
1233   assert( do_polling(), "no return for this epilog node");
1234   return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1235 }
1236 
1237 //=============================================================================
1238 
1239 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1240 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1241 static enum RC rc_class( OptoReg::Name reg ) {
1242   if( !OptoReg::is_valid(reg)  ) return rc_bad;
1243   if (OptoReg::is_stack(reg)) return rc_stack;
1244   VMReg r = OptoReg::as_VMReg(reg);
1245   if (r->is_Register()) return rc_int;
1246   assert(r->is_FloatRegister(), "must be");
1247   return rc_float;
1248 }
1249 
1250 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1251   if( cbuf ) {
1252     // Better yet would be some mechanism to handle variable-size matches correctly
1253     if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1254       ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1255     } else {
1256       emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1257     }
1258   }
1259 #ifndef PRODUCT
1260   else if( !do_size ) {
1261     if( size != 0 ) st->print("\n\t");
1262     if( is_load ) st->print("%s   [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1263     else          st->print("%s   R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1264   }
1265 #endif
1266   return size+4;
1267 }
1268 
1269 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1270   if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1271 #ifndef PRODUCT
1272   else if( !do_size ) {
1273     if( size != 0 ) st->print("\n\t");
1274     st->print("%s  R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1275   }
1276 #endif
1277   return size+4;
1278 }
1279 
1280 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1281                                         PhaseRegAlloc *ra_,
1282                                         bool do_size,
1283                                         outputStream* st ) const {
1284   // Get registers to move
1285   OptoReg::Name src_second = ra_->get_reg_second(in(1));
1286   OptoReg::Name src_first = ra_->get_reg_first(in(1));
1287   OptoReg::Name dst_second = ra_->get_reg_second(this );
1288   OptoReg::Name dst_first = ra_->get_reg_first(this );
1289 
1290   enum RC src_second_rc = rc_class(src_second);
1291   enum RC src_first_rc = rc_class(src_first);
1292   enum RC dst_second_rc = rc_class(dst_second);
1293   enum RC dst_first_rc = rc_class(dst_first);
1294 
1295   assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1296 
1297   // Generate spill code!
1298   int size = 0;
1299 
1300   if( src_first == dst_first && src_second == dst_second )
1301     return size;            // Self copy, no move
1302 
1303   // --------------------------------------
1304   // Check for mem-mem move.  Load into unused float registers and fall into
1305   // the float-store case.
1306   if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1307     int offset = ra_->reg2offset(src_first);
1308     // Further check for aligned-adjacent pair, so we can use a double load
1309     if( (src_first&1)==0 && src_first+1 == src_second ) {
1310       src_second    = OptoReg::Name(R_F31_num);
1311       src_second_rc = rc_float;
1312       size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1313     } else {
1314       size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1315     }
1316     src_first    = OptoReg::Name(R_F30_num);
1317     src_first_rc = rc_float;
1318   }
1319 
1320   if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1321     int offset = ra_->reg2offset(src_second);
1322     size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1323     src_second    = OptoReg::Name(R_F31_num);
1324     src_second_rc = rc_float;
1325   }
1326 
1327   // --------------------------------------
1328   // Check for float->int copy; requires a trip through memory
1329   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1330     int offset = frame::register_save_words*wordSize;
1331     if (cbuf) {
1332       emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1333       impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1334       impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1335       emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1336     }
1337 #ifndef PRODUCT
1338     else if (!do_size) {
1339       if (size != 0) st->print("\n\t");
1340       st->print(  "SUB    R_SP,16,R_SP\n");
1341       impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1342       impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1343       st->print("\tADD    R_SP,16,R_SP\n");
1344     }
1345 #endif
1346     size += 16;
1347   }
1348 
1349   // Check for float->int copy on T4
1350   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1351     // Further check for aligned-adjacent pair, so we can use a double move
1352     if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1353       return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1354     size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1355   }
1356   // Check for int->float copy on T4
1357   if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1358     // Further check for aligned-adjacent pair, so we can use a double move
1359     if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1360       return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1361     size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1362   }
1363 
1364   // --------------------------------------
1365   // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1366   // In such cases, I have to do the big-endian swap.  For aligned targets, the
1367   // hardware does the flop for me.  Doubles are always aligned, so no problem
1368   // there.  Misaligned sources only come from native-long-returns (handled
1369   // special below).
1370 #ifndef _LP64
1371   if( src_first_rc == rc_int &&     // source is already big-endian
1372       src_second_rc != rc_bad &&    // 64-bit move
1373       ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1374     assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1375     // Do the big-endian flop.
1376     OptoReg::Name tmp    = dst_first   ; dst_first    = dst_second   ; dst_second    = tmp   ;
1377     enum RC       tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1378   }
1379 #endif
1380 
1381   // --------------------------------------
1382   // Check for integer reg-reg copy
1383   if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1384 #ifndef _LP64
1385     if( src_first == R_O0_num && src_second == R_O1_num ) {  // Check for the evil O0/O1 native long-return case
1386       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1387       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
1388       //       operand contains the least significant word of the 64-bit value and vice versa.
1389       OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1390       assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1391       // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1392       if( cbuf ) {
1393         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1394         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1395         emit3       ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1396 #ifndef PRODUCT
1397       } else if( !do_size ) {
1398         if( size != 0 ) st->print("\n\t");
1399         st->print("SLLX   R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1400         st->print("SRL    R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1401         st->print("OR     R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1402 #endif
1403       }
1404       return size+12;
1405     }
1406     else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1407       // returning a long value in I0/I1
1408       // a SpillCopy must be able to target a return instruction's reg_class
1409       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1410       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
1411       //       operand contains the least significant word of the 64-bit value and vice versa.
1412       OptoReg::Name tdest = dst_first;
1413 
1414       if (src_first == dst_first) {
1415         tdest = OptoReg::Name(R_O7_num);
1416         size += 4;
1417       }
1418 
1419       if( cbuf ) {
1420         assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1421         // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1422         // ShrL_reg_imm6
1423         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1424         // ShrR_reg_imm6  src, 0, dst
1425         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1426         if (tdest != dst_first) {
1427           emit3     ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1428         }
1429       }
1430 #ifndef PRODUCT
1431       else if( !do_size ) {
1432         if( size != 0 ) st->print("\n\t");  // %%%%% !!!!!
1433         st->print("SRLX   R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1434         st->print("SRL    R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1435         if (tdest != dst_first) {
1436           st->print("MOV    R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1437         }
1438       }
1439 #endif // PRODUCT
1440       return size+8;
1441     }
1442 #endif // !_LP64
1443     // Else normal reg-reg copy
1444     assert( src_second != dst_first, "smashed second before evacuating it" );
1445     size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV  ",size, st);
1446     assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1447     // This moves an aligned adjacent pair.
1448     // See if we are done.
1449     if( src_first+1 == src_second && dst_first+1 == dst_second )
1450       return size;
1451   }
1452 
1453   // Check for integer store
1454   if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1455     int offset = ra_->reg2offset(dst_first);
1456     // Further check for aligned-adjacent pair, so we can use a double store
1457     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1458       return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1459     size  =  impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1460   }
1461 
1462   // Check for integer load
1463   if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1464     int offset = ra_->reg2offset(src_first);
1465     // Further check for aligned-adjacent pair, so we can use a double load
1466     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1467       return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1468     size  =  impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1469   }
1470 
1471   // Check for float reg-reg copy
1472   if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1473     // Further check for aligned-adjacent pair, so we can use a double move
1474     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1475       return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1476     size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1477   }
1478 
1479   // Check for float store
1480   if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1481     int offset = ra_->reg2offset(dst_first);
1482     // Further check for aligned-adjacent pair, so we can use a double store
1483     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1484       return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1485     size  =  impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1486   }
1487 
1488   // Check for float load
1489   if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1490     int offset = ra_->reg2offset(src_first);
1491     // Further check for aligned-adjacent pair, so we can use a double load
1492     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1493       return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1494     size  =  impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1495   }
1496 
1497   // --------------------------------------------------------------------
1498   // Check for hi bits still needing moving.  Only happens for misaligned
1499   // arguments to native calls.
1500   if( src_second == dst_second )
1501     return size;               // Self copy; no move
1502   assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1503 
1504 #ifndef _LP64
1505   // In the LP64 build, all registers can be moved as aligned/adjacent
1506   // pairs, so there's never any need to move the high bits separately.
1507   // The 32-bit builds have to deal with the 32-bit ABI which can force
1508   // all sorts of silly alignment problems.
1509 
1510   // Check for integer reg-reg copy.  Hi bits are stuck up in the top
1511   // 32-bits of a 64-bit register, but are needed in low bits of another
1512   // register (else it's a hi-bits-to-hi-bits copy which should have
1513   // happened already as part of a 64-bit move)
1514   if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1515     assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1516     assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1517     // Shift src_second down to dst_second's low bits.
1518     if( cbuf ) {
1519       emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1520 #ifndef PRODUCT
1521     } else if( !do_size ) {
1522       if( size != 0 ) st->print("\n\t");
1523       st->print("SRLX   R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1524 #endif
1525     }
1526     return size+4;
1527   }
1528 
1529   // Check for high word integer store.  Must down-shift the hi bits
1530   // into a temp register, then fall into the case of storing int bits.
1531   if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1532     // Shift src_second down to dst_second's low bits.
1533     if( cbuf ) {
1534       emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1535 #ifndef PRODUCT
1536     } else if( !do_size ) {
1537       if( size != 0 ) st->print("\n\t");
1538       st->print("SRLX   R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1539 #endif
1540     }
1541     size+=4;
1542     src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1543   }
1544 
1545   // Check for high word integer load
1546   if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1547     return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1548 
1549   // Check for high word integer store
1550   if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1551     return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1552 
1553   // Check for high word float store
1554   if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1555     return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1556 
1557 #endif // !_LP64
1558 
1559   Unimplemented();
1560 }
1561 
1562 #ifndef PRODUCT
1563 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1564   implementation( NULL, ra_, false, st );
1565 }
1566 #endif
1567 
1568 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1569   implementation( &cbuf, ra_, false, NULL );
1570 }
1571 
1572 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1573   return implementation( NULL, ra_, true, NULL );
1574 }
1575 
1576 //=============================================================================
1577 #ifndef PRODUCT
1578 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1579   st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1580 }
1581 #endif
1582 
1583 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1584   MacroAssembler _masm(&cbuf);
1585   for(int i = 0; i < _count; i += 1) {
1586     __ nop();
1587   }
1588 }
1589 
1590 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1591   return 4 * _count;
1592 }
1593 
1594 
1595 //=============================================================================
1596 #ifndef PRODUCT
1597 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1598   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1599   int reg = ra_->get_reg_first(this);
1600   st->print("LEA    [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1601 }
1602 #endif
1603 
1604 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1605   MacroAssembler _masm(&cbuf);
1606   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1607   int reg = ra_->get_encode(this);
1608 
1609   if (Assembler::is_simm13(offset)) {
1610      __ add(SP, offset, reg_to_register_object(reg));
1611   } else {
1612      __ set(offset, O7);
1613      __ add(SP, O7, reg_to_register_object(reg));
1614   }
1615 }
1616 
1617 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1618   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1619   assert(ra_ == ra_->C->regalloc(), "sanity");
1620   return ra_->C->scratch_emit_size(this);
1621 }
1622 
1623 //=============================================================================
1624 
1625 // emit call stub, compiled java to interpretor
1626 void emit_java_to_interp(CodeBuffer &cbuf ) {
1627 
1628   // Stub is fixed up when the corresponding call is converted from calling
1629   // compiled code to calling interpreted code.
1630   // set (empty), G5
1631   // jmp -1
1632 
1633   address mark = cbuf.insts_mark();  // get mark within main instrs section
1634 
1635   MacroAssembler _masm(&cbuf);
1636 
1637   address base =
1638   __ start_a_stub(Compile::MAX_stubs_size);
1639   if (base == NULL)  return;  // CodeBuffer::expand failed
1640 
1641   // static stub relocation stores the instruction address of the call
1642   __ relocate(static_stub_Relocation::spec(mark));
1643 
1644   __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1645 
1646   __ set_inst_mark();
1647   AddressLiteral addrlit(-1);
1648   __ JUMP(addrlit, G3, 0);
1649 
1650   __ delayed()->nop();
1651 
1652   // Update current stubs pointer and restore code_end.
1653   __ end_a_stub();
1654 }
1655 
1656 // size of call stub, compiled java to interpretor
1657 uint size_java_to_interp() {
1658   // This doesn't need to be accurate but it must be larger or equal to
1659   // the real size of the stub.
1660   return (NativeMovConstReg::instruction_size +  // sethi/setlo;
1661           NativeJump::instruction_size + // sethi; jmp; nop
1662           (TraceJumps ? 20 * BytesPerInstWord : 0) );
1663 }
1664 // relocation entries for call stub, compiled java to interpretor
1665 uint reloc_java_to_interp() {
1666   return 10;  // 4 in emit_java_to_interp + 1 in Java_Static_Call
1667 }
1668 
1669 
1670 //=============================================================================
1671 #ifndef PRODUCT
1672 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1673   st->print_cr("\nUEP:");
1674 #ifdef    _LP64
1675   if (UseCompressedOops) {
1676     assert(Universe::heap() != NULL, "java heap should be initialized");
1677     st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1678     st->print_cr("\tSLL    R_G5,3,R_G5");
1679     if (Universe::narrow_oop_base() != NULL)
1680       st->print_cr("\tADD    R_G5,R_G6_heap_base,R_G5");
1681   } else {
1682     st->print_cr("\tLDX    [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1683   }
1684   st->print_cr("\tCMP    R_G5,R_G3" );
1685   st->print   ("\tTne    xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1686 #else  // _LP64
1687   st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1688   st->print_cr("\tCMP    R_G5,R_G3" );
1689   st->print   ("\tTne    icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1690 #endif // _LP64
1691 }
1692 #endif
1693 
1694 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1695   MacroAssembler _masm(&cbuf);
1696   Register G5_ic_reg  = reg_to_register_object(Matcher::inline_cache_reg_encode());
1697   Register temp_reg   = G3;
1698   assert( G5_ic_reg != temp_reg, "conflicting registers" );
1699 
1700   // Load klass from receiver
1701   __ load_klass(O0, temp_reg);
1702   // Compare against expected klass
1703   __ cmp(temp_reg, G5_ic_reg);
1704   // Branch to miss code, checks xcc or icc depending
1705   __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1706 }
1707 
1708 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1709   return MachNode::size(ra_);
1710 }
1711 
1712 
1713 //=============================================================================
1714 
1715 uint size_exception_handler() {
1716   if (TraceJumps) {
1717     return (400); // just a guess
1718   }
1719   return ( NativeJump::instruction_size ); // sethi;jmp;nop
1720 }
1721 
1722 uint size_deopt_handler() {
1723   if (TraceJumps) {
1724     return (400); // just a guess
1725   }
1726   return ( 4+  NativeJump::instruction_size ); // save;sethi;jmp;restore
1727 }
1728 
1729 // Emit exception handler code.
1730 int emit_exception_handler(CodeBuffer& cbuf) {
1731   Register temp_reg = G3;
1732   AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1733   MacroAssembler _masm(&cbuf);
1734 
1735   address base =
1736   __ start_a_stub(size_exception_handler());
1737   if (base == NULL)  return 0;  // CodeBuffer::expand failed
1738 
1739   int offset = __ offset();
1740 
1741   __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1742   __ delayed()->nop();
1743 
1744   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1745 
1746   __ end_a_stub();
1747 
1748   return offset;
1749 }
1750 
1751 int emit_deopt_handler(CodeBuffer& cbuf) {
1752   // Can't use any of the current frame's registers as we may have deopted
1753   // at a poll and everything (including G3) can be live.
1754   Register temp_reg = L0;
1755   AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1756   MacroAssembler _masm(&cbuf);
1757 
1758   address base =
1759   __ start_a_stub(size_deopt_handler());
1760   if (base == NULL)  return 0;  // CodeBuffer::expand failed
1761 
1762   int offset = __ offset();
1763   __ save_frame(0);
1764   __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1765   __ delayed()->restore();
1766 
1767   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1768 
1769   __ end_a_stub();
1770   return offset;
1771 
1772 }
1773 
1774 // Given a register encoding, produce a Integer Register object
1775 static Register reg_to_register_object(int register_encoding) {
1776   assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1777   return as_Register(register_encoding);
1778 }
1779 
1780 // Given a register encoding, produce a single-precision Float Register object
1781 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1782   assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1783   return as_SingleFloatRegister(register_encoding);
1784 }
1785 
1786 // Given a register encoding, produce a double-precision Float Register object
1787 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1788   assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1789   assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1790   return as_DoubleFloatRegister(register_encoding);
1791 }
1792 
1793 const bool Matcher::match_rule_supported(int opcode) {
1794   if (!has_match_rule(opcode))
1795     return false;
1796 
1797   switch (opcode) {
1798   case Op_CountLeadingZerosI:
1799   case Op_CountLeadingZerosL:
1800   case Op_CountTrailingZerosI:
1801   case Op_CountTrailingZerosL:
1802     if (!UsePopCountInstruction)
1803       return false;
1804     break;
1805   }
1806 
1807   return true;  // Per default match rules are supported.
1808 }
1809 
1810 int Matcher::regnum_to_fpu_offset(int regnum) {
1811   return regnum - 32; // The FP registers are in the second chunk
1812 }
1813 
1814 #ifdef ASSERT
1815 address last_rethrow = NULL;  // debugging aid for Rethrow encoding
1816 #endif
1817 
1818 // Vector width in bytes
1819 const uint Matcher::vector_width_in_bytes(void) {
1820   return 8;
1821 }
1822 
1823 // Vector ideal reg
1824 const uint Matcher::vector_ideal_reg(void) {
1825   return Op_RegD;
1826 }
1827 
1828 // USII supports fxtof through the whole range of number, USIII doesn't
1829 const bool Matcher::convL2FSupported(void) {
1830   return VM_Version::has_fast_fxtof();
1831 }
1832 
1833 // Is this branch offset short enough that a short branch can be used?
1834 //
1835 // NOTE: If the platform does not provide any short branch variants, then
1836 //       this method should return false for offset 0.
1837 bool Matcher::is_short_branch_offset(int rule, int offset) {
1838   return false;
1839 }
1840 
1841 const bool Matcher::isSimpleConstant64(jlong value) {
1842   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1843   // Depends on optimizations in MacroAssembler::setx.
1844   int hi = (int)(value >> 32);
1845   int lo = (int)(value & ~0);
1846   return (hi == 0) || (hi == -1) || (lo == 0);
1847 }
1848 
1849 // No scaling for the parameter the ClearArray node.
1850 const bool Matcher::init_array_count_is_in_bytes = true;
1851 
1852 // Threshold size for cleararray.
1853 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1854 
1855 // Should the Matcher clone shifts on addressing modes, expecting them to
1856 // be subsumed into complex addressing expressions or compute them into
1857 // registers?  True for Intel but false for most RISCs
1858 const bool Matcher::clone_shift_expressions = false;
1859 
1860 // Do we need to mask the count passed to shift instructions or does
1861 // the cpu only look at the lower 5/6 bits anyway?
1862 const bool Matcher::need_masked_shift_count = false;
1863 
1864 bool Matcher::narrow_oop_use_complex_address() {
1865   NOT_LP64(ShouldNotCallThis());
1866   assert(UseCompressedOops, "only for compressed oops code");
1867   return false;
1868 }
1869 
1870 // Is it better to copy float constants, or load them directly from memory?
1871 // Intel can load a float constant from a direct address, requiring no
1872 // extra registers.  Most RISCs will have to materialize an address into a
1873 // register first, so they would do better to copy the constant from stack.
1874 const bool Matcher::rematerialize_float_constants = false;
1875 
1876 // If CPU can load and store mis-aligned doubles directly then no fixup is
1877 // needed.  Else we split the double into 2 integer pieces and move it
1878 // piece-by-piece.  Only happens when passing doubles into C code as the
1879 // Java calling convention forces doubles to be aligned.
1880 #ifdef _LP64
1881 const bool Matcher::misaligned_doubles_ok = true;
1882 #else
1883 const bool Matcher::misaligned_doubles_ok = false;
1884 #endif
1885 
1886 // No-op on SPARC.
1887 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1888 }
1889 
1890 // Advertise here if the CPU requires explicit rounding operations
1891 // to implement the UseStrictFP mode.
1892 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1893 
1894 // Are floats conerted to double when stored to stack during deoptimization?
1895 // Sparc does not handle callee-save floats.
1896 bool Matcher::float_in_double() { return false; }
1897 
1898 // Do ints take an entire long register or just half?
1899 // Note that we if-def off of _LP64.
1900 // The relevant question is how the int is callee-saved.  In _LP64
1901 // the whole long is written but de-opt'ing will have to extract
1902 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1903 #ifdef _LP64
1904 const bool Matcher::int_in_long = true;
1905 #else
1906 const bool Matcher::int_in_long = false;
1907 #endif
1908 
1909 // Return whether or not this register is ever used as an argument.  This
1910 // function is used on startup to build the trampoline stubs in generateOptoStub.
1911 // Registers not mentioned will be killed by the VM call in the trampoline, and
1912 // arguments in those registers not be available to the callee.
1913 bool Matcher::can_be_java_arg( int reg ) {
1914   // Standard sparc 6 args in registers
1915   if( reg == R_I0_num ||
1916       reg == R_I1_num ||
1917       reg == R_I2_num ||
1918       reg == R_I3_num ||
1919       reg == R_I4_num ||
1920       reg == R_I5_num ) return true;
1921 #ifdef _LP64
1922   // 64-bit builds can pass 64-bit pointers and longs in
1923   // the high I registers
1924   if( reg == R_I0H_num ||
1925       reg == R_I1H_num ||
1926       reg == R_I2H_num ||
1927       reg == R_I3H_num ||
1928       reg == R_I4H_num ||
1929       reg == R_I5H_num ) return true;
1930 
1931   if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1932     return true;
1933   }
1934 
1935 #else
1936   // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1937   // Longs cannot be passed in O regs, because O regs become I regs
1938   // after a 'save' and I regs get their high bits chopped off on
1939   // interrupt.
1940   if( reg == R_G1H_num || reg == R_G1_num ) return true;
1941   if( reg == R_G4H_num || reg == R_G4_num ) return true;
1942 #endif
1943   // A few float args in registers
1944   if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1945 
1946   return false;
1947 }
1948 
1949 bool Matcher::is_spillable_arg( int reg ) {
1950   return can_be_java_arg(reg);
1951 }
1952 
1953 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1954   // Use hardware SDIVX instruction when it is
1955   // faster than a code which use multiply.
1956   return VM_Version::has_fast_idiv();
1957 }
1958 
1959 // Register for DIVI projection of divmodI
1960 RegMask Matcher::divI_proj_mask() {
1961   ShouldNotReachHere();
1962   return RegMask();
1963 }
1964 
1965 // Register for MODI projection of divmodI
1966 RegMask Matcher::modI_proj_mask() {
1967   ShouldNotReachHere();
1968   return RegMask();
1969 }
1970 
1971 // Register for DIVL projection of divmodL
1972 RegMask Matcher::divL_proj_mask() {
1973   ShouldNotReachHere();
1974   return RegMask();
1975 }
1976 
1977 // Register for MODL projection of divmodL
1978 RegMask Matcher::modL_proj_mask() {
1979   ShouldNotReachHere();
1980   return RegMask();
1981 }
1982 
1983 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1984   return L7_REGP_mask;
1985 }
1986 
1987 %}
1988 
1989 
1990 // The intptr_t operand types, defined by textual substitution.
1991 // (Cf. opto/type.hpp.  This lets us avoid many, many other ifdefs.)
1992 #ifdef _LP64
1993 #define immX      immL
1994 #define immX13    immL13
1995 #define immX13m7  immL13m7
1996 #define iRegX     iRegL
1997 #define g1RegX    g1RegL
1998 #else
1999 #define immX      immI
2000 #define immX13    immI13
2001 #define immX13m7  immI13m7
2002 #define iRegX     iRegI
2003 #define g1RegX    g1RegI
2004 #endif
2005 
2006 //----------ENCODING BLOCK-----------------------------------------------------
2007 // This block specifies the encoding classes used by the compiler to output
2008 // byte streams.  Encoding classes are parameterized macros used by
2009 // Machine Instruction Nodes in order to generate the bit encoding of the
2010 // instruction.  Operands specify their base encoding interface with the
2011 // interface keyword.  There are currently supported four interfaces,
2012 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
2013 // operand to generate a function which returns its register number when
2014 // queried.   CONST_INTER causes an operand to generate a function which
2015 // returns the value of the constant when queried.  MEMORY_INTER causes an
2016 // operand to generate four functions which return the Base Register, the
2017 // Index Register, the Scale Value, and the Offset Value of the operand when
2018 // queried.  COND_INTER causes an operand to generate six functions which
2019 // return the encoding code (ie - encoding bits for the instruction)
2020 // associated with each basic boolean condition for a conditional instruction.
2021 //
2022 // Instructions specify two basic values for encoding.  Again, a function
2023 // is available to check if the constant displacement is an oop. They use the
2024 // ins_encode keyword to specify their encoding classes (which must be
2025 // a sequence of enc_class names, and their parameters, specified in
2026 // the encoding block), and they use the
2027 // opcode keyword to specify, in order, their primary, secondary, and
2028 // tertiary opcode.  Only the opcode sections which a particular instruction
2029 // needs for encoding need to be specified.
2030 encode %{
2031   enc_class enc_untested %{
2032 #ifdef ASSERT
2033     MacroAssembler _masm(&cbuf);
2034     __ untested("encoding");
2035 #endif
2036   %}
2037 
2038   enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2039     emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2040                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2041   %}
2042 
2043   enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2044     emit_form3_mem_reg(cbuf, this, $primary, -1,
2045                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2046   %}
2047 
2048   enc_class form3_mem_prefetch_read( memory mem ) %{
2049     emit_form3_mem_reg(cbuf, this, $primary, -1,
2050                        $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2051   %}
2052 
2053   enc_class form3_mem_prefetch_write( memory mem ) %{
2054     emit_form3_mem_reg(cbuf, this, $primary, -1,
2055                        $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2056   %}
2057 
2058   enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2059     assert( Assembler::is_simm13($mem$$disp  ), "need disp and disp+4" );
2060     assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2061     guarantee($mem$$index == R_G0_enc, "double index?");
2062     emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2063     emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg );
2064     emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2065     emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2066   %}
2067 
2068   enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2069     assert( Assembler::is_simm13($mem$$disp  ), "need disp and disp+4" );
2070     assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2071     guarantee($mem$$index == R_G0_enc, "double index?");
2072     // Load long with 2 instructions
2073     emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg+0 );
2074     emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2075   %}
2076 
2077   //%%% form3_mem_plus_4_reg is a hack--get rid of it
2078   enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2079     guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2080     emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2081   %}
2082 
2083   enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2084     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2085     if( $rs2$$reg != $rd$$reg )
2086       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2087   %}
2088 
2089   // Target lo half of long
2090   enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2091     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2092     if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2093       emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2094   %}
2095 
2096   // Source lo half of long
2097   enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2098     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2099     if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2100       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2101   %}
2102 
2103   // Target hi half of long
2104   enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2105     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2106   %}
2107 
2108   // Source lo half of long, and leave it sign extended.
2109   enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2110     // Sign extend low half
2111     emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2112   %}
2113 
2114   // Source hi half of long, and leave it sign extended.
2115   enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2116     // Shift high half to low half
2117     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2118   %}
2119 
2120   // Source hi half of long
2121   enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2122     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2123     if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2124       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2125   %}
2126 
2127   enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2128     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2129   %}
2130 
2131   enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2132     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, 0, 0, $src$$reg );
2133     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2134   %}
2135 
2136   enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2137     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2138     // clear if nothing else is happening
2139     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  0 );
2140     // blt,a,pn done
2141     emit2_19    ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2142     // mov dst,-1 in delay slot
2143     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2144   %}
2145 
2146   enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2147     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2148   %}
2149 
2150   enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2151     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2152   %}
2153 
2154   enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2155     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2156   %}
2157 
2158   enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2159     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2160   %}
2161 
2162   enc_class move_return_pc_to_o1() %{
2163     emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2164   %}
2165 
2166 #ifdef _LP64
2167   /* %%% merge with enc_to_bool */
2168   enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2169     MacroAssembler _masm(&cbuf);
2170 
2171     Register   src_reg = reg_to_register_object($src$$reg);
2172     Register   dst_reg = reg_to_register_object($dst$$reg);
2173     __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2174   %}
2175 #endif
2176 
2177   enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2178     // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2179     MacroAssembler _masm(&cbuf);
2180 
2181     Register   p_reg = reg_to_register_object($p$$reg);
2182     Register   q_reg = reg_to_register_object($q$$reg);
2183     Register   y_reg = reg_to_register_object($y$$reg);
2184     Register tmp_reg = reg_to_register_object($tmp$$reg);
2185 
2186     __ subcc( p_reg, q_reg,   p_reg );
2187     __ add  ( p_reg, y_reg, tmp_reg );
2188     __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2189   %}
2190 
2191   enc_class form_d2i_helper(regD src, regF dst) %{
2192     // fcmp %fcc0,$src,$src
2193     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2194     // branch %fcc0 not-nan, predict taken
2195     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2196     // fdtoi $src,$dst
2197     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtoi_opf, $src$$reg );
2198     // fitos $dst,$dst (if nan)
2199     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
2200     // clear $dst (if nan)
2201     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2202     // carry on here...
2203   %}
2204 
2205   enc_class form_d2l_helper(regD src, regD dst) %{
2206     // fcmp %fcc0,$src,$src  check for NAN
2207     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2208     // branch %fcc0 not-nan, predict taken
2209     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2210     // fdtox $src,$dst   convert in delay slot
2211     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtox_opf, $src$$reg );
2212     // fxtod $dst,$dst  (if nan)
2213     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
2214     // clear $dst (if nan)
2215     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2216     // carry on here...
2217   %}
2218 
2219   enc_class form_f2i_helper(regF src, regF dst) %{
2220     // fcmps %fcc0,$src,$src
2221     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2222     // branch %fcc0 not-nan, predict taken
2223     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2224     // fstoi $src,$dst
2225     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstoi_opf, $src$$reg );
2226     // fitos $dst,$dst (if nan)
2227     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
2228     // clear $dst (if nan)
2229     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2230     // carry on here...
2231   %}
2232 
2233   enc_class form_f2l_helper(regF src, regD dst) %{
2234     // fcmps %fcc0,$src,$src
2235     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2236     // branch %fcc0 not-nan, predict taken
2237     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2238     // fstox $src,$dst
2239     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstox_opf, $src$$reg );
2240     // fxtod $dst,$dst (if nan)
2241     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
2242     // clear $dst (if nan)
2243     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2244     // carry on here...
2245   %}
2246 
2247   enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2248   enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2249   enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2250   enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2251 
2252   enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2253 
2254   enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2255   enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2256 
2257   enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2258     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2259   %}
2260 
2261   enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2262     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2263   %}
2264 
2265   enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2266     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2267   %}
2268 
2269   enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2270     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2271   %}
2272 
2273   enc_class form3_convI2F(regF rs2, regF rd) %{
2274     emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2275   %}
2276 
2277   // Encloding class for traceable jumps
2278   enc_class form_jmpl(g3RegP dest) %{
2279     emit_jmpl(cbuf, $dest$$reg);
2280   %}
2281 
2282   enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2283     emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2284   %}
2285 
2286   enc_class form2_nop() %{
2287     emit_nop(cbuf);
2288   %}
2289 
2290   enc_class form2_illtrap() %{
2291     emit_illtrap(cbuf);
2292   %}
2293 
2294 
2295   // Compare longs and convert into -1, 0, 1.
2296   enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2297     // CMP $src1,$src2
2298     emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2299     // blt,a,pn done
2300     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less   , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2301     // mov dst,-1 in delay slot
2302     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2303     // bgt,a,pn done
2304     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2305     // mov dst,1 in delay slot
2306     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  1 );
2307     // CLR    $dst
2308     emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2309   %}
2310 
2311   enc_class enc_PartialSubtypeCheck() %{
2312     MacroAssembler _masm(&cbuf);
2313     __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2314     __ delayed()->nop();
2315   %}
2316 
2317   enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2318     MacroAssembler _masm(&cbuf);
2319     Label* L = $labl$$label;
2320     Assembler::Predict predict_taken =
2321       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2322 
2323     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2324     __ delayed()->nop();
2325   %}
2326 
2327   enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2328     MacroAssembler _masm(&cbuf);
2329     Label* L = $labl$$label;
2330     Assembler::Predict predict_taken =
2331       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2332 
2333     __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2334     __ delayed()->nop();
2335   %}
2336 
2337   enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2338     int op = (Assembler::arith_op << 30) |
2339              ($dst$$reg << 25) |
2340              (Assembler::movcc_op3 << 19) |
2341              (1 << 18) |                    // cc2 bit for 'icc'
2342              ($cmp$$cmpcode << 14) |
2343              (0 << 13) |                    // select register move
2344              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc' or 'xcc'
2345              ($src$$reg << 0);
2346     cbuf.insts()->emit_int32(op);
2347   %}
2348 
2349   enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2350     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2351     int op = (Assembler::arith_op << 30) |
2352              ($dst$$reg << 25) |
2353              (Assembler::movcc_op3 << 19) |
2354              (1 << 18) |                    // cc2 bit for 'icc'
2355              ($cmp$$cmpcode << 14) |
2356              (1 << 13) |                    // select immediate move
2357              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc'
2358              (simm11 << 0);
2359     cbuf.insts()->emit_int32(op);
2360   %}
2361 
2362   enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2363     int op = (Assembler::arith_op << 30) |
2364              ($dst$$reg << 25) |
2365              (Assembler::movcc_op3 << 19) |
2366              (0 << 18) |                    // cc2 bit for 'fccX'
2367              ($cmp$$cmpcode << 14) |
2368              (0 << 13) |                    // select register move
2369              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
2370              ($src$$reg << 0);
2371     cbuf.insts()->emit_int32(op);
2372   %}
2373 
2374   enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2375     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2376     int op = (Assembler::arith_op << 30) |
2377              ($dst$$reg << 25) |
2378              (Assembler::movcc_op3 << 19) |
2379              (0 << 18) |                    // cc2 bit for 'fccX'
2380              ($cmp$$cmpcode << 14) |
2381              (1 << 13) |                    // select immediate move
2382              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
2383              (simm11 << 0);
2384     cbuf.insts()->emit_int32(op);
2385   %}
2386 
2387   enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2388     int op = (Assembler::arith_op << 30) |
2389              ($dst$$reg << 25) |
2390              (Assembler::fpop2_op3 << 19) |
2391              (0 << 18) |
2392              ($cmp$$cmpcode << 14) |
2393              (1 << 13) |                    // select register move
2394              ($pcc$$constant << 11) |       // cc1-cc0 bits for 'icc' or 'xcc'
2395              ($primary << 5) |              // select single, double or quad
2396              ($src$$reg << 0);
2397     cbuf.insts()->emit_int32(op);
2398   %}
2399 
2400   enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2401     int op = (Assembler::arith_op << 30) |
2402              ($dst$$reg << 25) |
2403              (Assembler::fpop2_op3 << 19) |
2404              (0 << 18) |
2405              ($cmp$$cmpcode << 14) |
2406              ($fcc$$reg << 11) |            // cc2-cc0 bits for 'fccX'
2407              ($primary << 5) |              // select single, double or quad
2408              ($src$$reg << 0);
2409     cbuf.insts()->emit_int32(op);
2410   %}
2411 
2412   // Used by the MIN/MAX encodings.  Same as a CMOV, but
2413   // the condition comes from opcode-field instead of an argument.
2414   enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2415     int op = (Assembler::arith_op << 30) |
2416              ($dst$$reg << 25) |
2417              (Assembler::movcc_op3 << 19) |
2418              (1 << 18) |                    // cc2 bit for 'icc'
2419              ($primary << 14) |
2420              (0 << 13) |                    // select register move
2421              (0 << 11) |                    // cc1, cc0 bits for 'icc'
2422              ($src$$reg << 0);
2423     cbuf.insts()->emit_int32(op);
2424   %}
2425 
2426   enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2427     int op = (Assembler::arith_op << 30) |
2428              ($dst$$reg << 25) |
2429              (Assembler::movcc_op3 << 19) |
2430              (6 << 16) |                    // cc2 bit for 'xcc'
2431              ($primary << 14) |
2432              (0 << 13) |                    // select register move
2433              (0 << 11) |                    // cc1, cc0 bits for 'icc'
2434              ($src$$reg << 0);
2435     cbuf.insts()->emit_int32(op);
2436   %}
2437 
2438   enc_class Set13( immI13 src, iRegI rd ) %{
2439     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2440   %}
2441 
2442   enc_class SetHi22( immI src, iRegI rd ) %{
2443     emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2444   %}
2445 
2446   enc_class Set32( immI src, iRegI rd ) %{
2447     MacroAssembler _masm(&cbuf);
2448     __ set($src$$constant, reg_to_register_object($rd$$reg));
2449   %}
2450 
2451   enc_class call_epilog %{
2452     if( VerifyStackAtCalls ) {
2453       MacroAssembler _masm(&cbuf);
2454       int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2455       Register temp_reg = G3;
2456       __ add(SP, framesize, temp_reg);
2457       __ cmp(temp_reg, FP);
2458       __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2459     }
2460   %}
2461 
2462   // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2463   // to G1 so the register allocator will not have to deal with the misaligned register
2464   // pair.
2465   enc_class adjust_long_from_native_call %{
2466 #ifndef _LP64
2467     if (returns_long()) {
2468       //    sllx  O0,32,O0
2469       emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2470       //    srl   O1,0,O1
2471       emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2472       //    or    O0,O1,G1
2473       emit3       ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2474     }
2475 #endif
2476   %}
2477 
2478   enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime
2479     // CALL directly to the runtime
2480     // The user of this is responsible for ensuring that R_L7 is empty (killed).
2481     emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2482                     /*preserve_g2=*/true);
2483   %}
2484 
2485   enc_class preserve_SP %{
2486     MacroAssembler _masm(&cbuf);
2487     __ mov(SP, L7_mh_SP_save);
2488   %}
2489 
2490   enc_class restore_SP %{
2491     MacroAssembler _masm(&cbuf);
2492     __ mov(L7_mh_SP_save, SP);
2493   %}
2494 
2495   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
2496     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
2497     // who we intended to call.
2498     if ( !_method ) {
2499       emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2500     } else if (_optimized_virtual) {
2501       emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2502     } else {
2503       emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2504     }
2505     if( _method ) {  // Emit stub for static call
2506       emit_java_to_interp(cbuf);
2507     }
2508   %}
2509 
2510   enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL
2511     MacroAssembler _masm(&cbuf);
2512     __ set_inst_mark();
2513     int vtable_index = this->_vtable_index;
2514     // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2515     if (vtable_index < 0) {
2516       // must be invalid_vtable_index, not nonvirtual_vtable_index
2517       assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2518       Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2519       assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2520       assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2521       // !!!!!
2522       // Generate  "set 0x01, R_G5", placeholder instruction to load oop-info
2523       // emit_call_dynamic_prologue( cbuf );
2524       __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2525 
2526       address  virtual_call_oop_addr = __ inst_mark();
2527       // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
2528       // who we intended to call.
2529       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2530       emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2531     } else {
2532       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2533       // Just go thru the vtable
2534       // get receiver klass (receiver already checked for non-null)
2535       // If we end up going thru a c2i adapter interpreter expects method in G5
2536       int off = __ offset();
2537       __ load_klass(O0, G3_scratch);
2538       int klass_load_size;
2539       if (UseCompressedOops) {
2540         assert(Universe::heap() != NULL, "java heap should be initialized");
2541         if (Universe::narrow_oop_base() == NULL)
2542           klass_load_size = 2*BytesPerInstWord;
2543         else
2544           klass_load_size = 3*BytesPerInstWord;
2545       } else {
2546         klass_load_size = 1*BytesPerInstWord;
2547       }
2548       int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2549       int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2550       if( __ is_simm13(v_off) ) {
2551         __ ld_ptr(G3, v_off, G5_method);
2552       } else {
2553         // Generate 2 instructions
2554         __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2555         __ or3(G5_method, v_off & 0x3ff, G5_method);
2556         // ld_ptr, set_hi, set
2557         assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2558                "Unexpected instruction size(s)");
2559         __ ld_ptr(G3, G5_method, G5_method);
2560       }
2561       // NOTE: for vtable dispatches, the vtable entry will never be null.
2562       // However it may very well end up in handle_wrong_method if the
2563       // method is abstract for the particular class.
2564       __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2565       // jump to target (either compiled code or c2iadapter)
2566       __ jmpl(G3_scratch, G0, O7);
2567       __ delayed()->nop();
2568     }
2569   %}
2570 
2571   enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL
2572     MacroAssembler _masm(&cbuf);
2573 
2574     Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2575     Register temp_reg = G3;   // caller must kill G3!  We cannot reuse G5_ic_reg here because
2576                               // we might be calling a C2I adapter which needs it.
2577 
2578     assert(temp_reg != G5_ic_reg, "conflicting registers");
2579     // Load nmethod
2580     __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2581 
2582     // CALL to compiled java, indirect the contents of G3
2583     __ set_inst_mark();
2584     __ callr(temp_reg, G0);
2585     __ delayed()->nop();
2586   %}
2587 
2588 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2589     MacroAssembler _masm(&cbuf);
2590     Register Rdividend = reg_to_register_object($src1$$reg);
2591     Register Rdivisor = reg_to_register_object($src2$$reg);
2592     Register Rresult = reg_to_register_object($dst$$reg);
2593 
2594     __ sra(Rdivisor, 0, Rdivisor);
2595     __ sra(Rdividend, 0, Rdividend);
2596     __ sdivx(Rdividend, Rdivisor, Rresult);
2597 %}
2598 
2599 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2600     MacroAssembler _masm(&cbuf);
2601 
2602     Register Rdividend = reg_to_register_object($src1$$reg);
2603     int divisor = $imm$$constant;
2604     Register Rresult = reg_to_register_object($dst$$reg);
2605 
2606     __ sra(Rdividend, 0, Rdividend);
2607     __ sdivx(Rdividend, divisor, Rresult);
2608 %}
2609 
2610 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2611     MacroAssembler _masm(&cbuf);
2612     Register Rsrc1 = reg_to_register_object($src1$$reg);
2613     Register Rsrc2 = reg_to_register_object($src2$$reg);
2614     Register Rdst  = reg_to_register_object($dst$$reg);
2615 
2616     __ sra( Rsrc1, 0, Rsrc1 );
2617     __ sra( Rsrc2, 0, Rsrc2 );
2618     __ mulx( Rsrc1, Rsrc2, Rdst );
2619     __ srlx( Rdst, 32, Rdst );
2620 %}
2621 
2622 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2623     MacroAssembler _masm(&cbuf);
2624     Register Rdividend = reg_to_register_object($src1$$reg);
2625     Register Rdivisor = reg_to_register_object($src2$$reg);
2626     Register Rresult = reg_to_register_object($dst$$reg);
2627     Register Rscratch = reg_to_register_object($scratch$$reg);
2628 
2629     assert(Rdividend != Rscratch, "");
2630     assert(Rdivisor  != Rscratch, "");
2631 
2632     __ sra(Rdividend, 0, Rdividend);
2633     __ sra(Rdivisor, 0, Rdivisor);
2634     __ sdivx(Rdividend, Rdivisor, Rscratch);
2635     __ mulx(Rscratch, Rdivisor, Rscratch);
2636     __ sub(Rdividend, Rscratch, Rresult);
2637 %}
2638 
2639 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2640     MacroAssembler _masm(&cbuf);
2641 
2642     Register Rdividend = reg_to_register_object($src1$$reg);
2643     int divisor = $imm$$constant;
2644     Register Rresult = reg_to_register_object($dst$$reg);
2645     Register Rscratch = reg_to_register_object($scratch$$reg);
2646 
2647     assert(Rdividend != Rscratch, "");
2648 
2649     __ sra(Rdividend, 0, Rdividend);
2650     __ sdivx(Rdividend, divisor, Rscratch);
2651     __ mulx(Rscratch, divisor, Rscratch);
2652     __ sub(Rdividend, Rscratch, Rresult);
2653 %}
2654 
2655 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2656     MacroAssembler _masm(&cbuf);
2657 
2658     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2659     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2660 
2661     __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2662 %}
2663 
2664 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2665     MacroAssembler _masm(&cbuf);
2666 
2667     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2668     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2669 
2670     __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2671 %}
2672 
2673 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2674     MacroAssembler _masm(&cbuf);
2675 
2676     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2677     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2678 
2679     __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2680 %}
2681 
2682 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2683     MacroAssembler _masm(&cbuf);
2684 
2685     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2686     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2687 
2688     __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2689 %}
2690 
2691 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2692     MacroAssembler _masm(&cbuf);
2693 
2694     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2695     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2696 
2697     __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2698 %}
2699 
2700 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2701     MacroAssembler _masm(&cbuf);
2702 
2703     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2704     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2705 
2706     __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2707 %}
2708 
2709 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2710     MacroAssembler _masm(&cbuf);
2711 
2712     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2713     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2714 
2715     __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2716 %}
2717 
2718 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2719     MacroAssembler _masm(&cbuf);
2720 
2721     Register Roop  = reg_to_register_object($oop$$reg);
2722     Register Rbox  = reg_to_register_object($box$$reg);
2723     Register Rscratch = reg_to_register_object($scratch$$reg);
2724     Register Rmark =    reg_to_register_object($scratch2$$reg);
2725 
2726     assert(Roop  != Rscratch, "");
2727     assert(Roop  != Rmark, "");
2728     assert(Rbox  != Rscratch, "");
2729     assert(Rbox  != Rmark, "");
2730 
2731     __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2732 %}
2733 
2734 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2735     MacroAssembler _masm(&cbuf);
2736 
2737     Register Roop  = reg_to_register_object($oop$$reg);
2738     Register Rbox  = reg_to_register_object($box$$reg);
2739     Register Rscratch = reg_to_register_object($scratch$$reg);
2740     Register Rmark =    reg_to_register_object($scratch2$$reg);
2741 
2742     assert(Roop  != Rscratch, "");
2743     assert(Roop  != Rmark, "");
2744     assert(Rbox  != Rscratch, "");
2745     assert(Rbox  != Rmark, "");
2746 
2747     __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2748   %}
2749 
2750   enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2751     MacroAssembler _masm(&cbuf);
2752     Register Rmem = reg_to_register_object($mem$$reg);
2753     Register Rold = reg_to_register_object($old$$reg);
2754     Register Rnew = reg_to_register_object($new$$reg);
2755 
2756     // casx_under_lock picks 1 of 3 encodings:
2757     // For 32-bit pointers you get a 32-bit CAS
2758     // For 64-bit pointers you get a 64-bit CASX
2759     __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2760     __ cmp( Rold, Rnew );
2761   %}
2762 
2763   enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2764     Register Rmem = reg_to_register_object($mem$$reg);
2765     Register Rold = reg_to_register_object($old$$reg);
2766     Register Rnew = reg_to_register_object($new$$reg);
2767 
2768     MacroAssembler _masm(&cbuf);
2769     __ mov(Rnew, O7);
2770     __ casx(Rmem, Rold, O7);
2771     __ cmp( Rold, O7 );
2772   %}
2773 
2774   // raw int cas, used for compareAndSwap
2775   enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2776     Register Rmem = reg_to_register_object($mem$$reg);
2777     Register Rold = reg_to_register_object($old$$reg);
2778     Register Rnew = reg_to_register_object($new$$reg);
2779 
2780     MacroAssembler _masm(&cbuf);
2781     __ mov(Rnew, O7);
2782     __ cas(Rmem, Rold, O7);
2783     __ cmp( Rold, O7 );
2784   %}
2785 
2786   enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2787     Register Rres = reg_to_register_object($res$$reg);
2788 
2789     MacroAssembler _masm(&cbuf);
2790     __ mov(1, Rres);
2791     __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2792   %}
2793 
2794   enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2795     Register Rres = reg_to_register_object($res$$reg);
2796 
2797     MacroAssembler _masm(&cbuf);
2798     __ mov(1, Rres);
2799     __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2800   %}
2801 
2802   enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2803     MacroAssembler _masm(&cbuf);
2804     Register Rdst = reg_to_register_object($dst$$reg);
2805     FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2806                                      : reg_to_DoubleFloatRegister_object($src1$$reg);
2807     FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2808                                      : reg_to_DoubleFloatRegister_object($src2$$reg);
2809 
2810     // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2811     __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2812   %}
2813 
2814   // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2815   enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2816     MacroAssembler _masm(&cbuf);
2817     Register    nof_bytes_arg   = reg_to_register_object($cnt$$reg);
2818     Register    nof_bytes_tmp    = reg_to_register_object($temp$$reg);
2819     Register    base_pointer_arg = reg_to_register_object($base$$reg);
2820 
2821     Label loop;
2822     __ mov(nof_bytes_arg, nof_bytes_tmp);
2823 
2824     // Loop and clear, walking backwards through the array.
2825     // nof_bytes_tmp (if >0) is always the number of bytes to zero
2826     __ bind(loop);
2827     __ deccc(nof_bytes_tmp, 8);
2828     __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2829     __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2830     // %%%% this mini-loop must not cross a cache boundary!
2831   %}
2832 
2833 
2834   enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2835     Label Ldone, Lloop;
2836     MacroAssembler _masm(&cbuf);
2837 
2838     Register   str1_reg = reg_to_register_object($str1$$reg);
2839     Register   str2_reg = reg_to_register_object($str2$$reg);
2840     Register   cnt1_reg = reg_to_register_object($cnt1$$reg);
2841     Register   cnt2_reg = reg_to_register_object($cnt2$$reg);
2842     Register result_reg = reg_to_register_object($result$$reg);
2843 
2844     assert(result_reg != str1_reg &&
2845            result_reg != str2_reg &&
2846            result_reg != cnt1_reg &&
2847            result_reg != cnt2_reg ,
2848            "need different registers");
2849 
2850     // Compute the minimum of the string lengths(str1_reg) and the
2851     // difference of the string lengths (stack)
2852 
2853     // See if the lengths are different, and calculate min in str1_reg.
2854     // Stash diff in O7 in case we need it for a tie-breaker.
2855     Label Lskip;
2856     __ subcc(cnt1_reg, cnt2_reg, O7);
2857     __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2858     __ br(Assembler::greater, true, Assembler::pt, Lskip);
2859     // cnt2 is shorter, so use its count:
2860     __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2861     __ bind(Lskip);
2862 
2863     // reallocate cnt1_reg, cnt2_reg, result_reg
2864     // Note:  limit_reg holds the string length pre-scaled by 2
2865     Register limit_reg =   cnt1_reg;
2866     Register  chr2_reg =   cnt2_reg;
2867     Register  chr1_reg = result_reg;
2868     // str{12} are the base pointers
2869 
2870     // Is the minimum length zero?
2871     __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2872     __ br(Assembler::equal, true, Assembler::pn, Ldone);
2873     __ delayed()->mov(O7, result_reg);  // result is difference in lengths
2874 
2875     // Load first characters
2876     __ lduh(str1_reg, 0, chr1_reg);
2877     __ lduh(str2_reg, 0, chr2_reg);
2878 
2879     // Compare first characters
2880     __ subcc(chr1_reg, chr2_reg, chr1_reg);
2881     __ br(Assembler::notZero, false, Assembler::pt,  Ldone);
2882     assert(chr1_reg == result_reg, "result must be pre-placed");
2883     __ delayed()->nop();
2884 
2885     {
2886       // Check after comparing first character to see if strings are equivalent
2887       Label LSkip2;
2888       // Check if the strings start at same location
2889       __ cmp(str1_reg, str2_reg);
2890       __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2891       __ delayed()->nop();
2892 
2893       // Check if the length difference is zero (in O7)
2894       __ cmp(G0, O7);
2895       __ br(Assembler::equal, true, Assembler::pn, Ldone);
2896       __ delayed()->mov(G0, result_reg);  // result is zero
2897 
2898       // Strings might not be equal
2899       __ bind(LSkip2);
2900     }
2901 
2902     __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2903     __ br(Assembler::equal, true, Assembler::pn, Ldone);
2904     __ delayed()->mov(O7, result_reg);  // result is difference in lengths
2905 
2906     // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2907     __ add(str1_reg, limit_reg, str1_reg);
2908     __ add(str2_reg, limit_reg, str2_reg);
2909     __ neg(chr1_reg, limit_reg);  // limit = -(limit-2)
2910 
2911     // Compare the rest of the characters
2912     __ lduh(str1_reg, limit_reg, chr1_reg);
2913     __ bind(Lloop);
2914     // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2915     __ lduh(str2_reg, limit_reg, chr2_reg);
2916     __ subcc(chr1_reg, chr2_reg, chr1_reg);
2917     __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2918     assert(chr1_reg == result_reg, "result must be pre-placed");
2919     __ delayed()->inccc(limit_reg, sizeof(jchar));
2920     // annul LDUH if branch is not taken to prevent access past end of string
2921     __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2922     __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2923 
2924     // If strings are equal up to min length, return the length difference.
2925     __ mov(O7, result_reg);
2926 
2927     // Otherwise, return the difference between the first mismatched chars.
2928     __ bind(Ldone);
2929   %}
2930 
2931 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2932     Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2933     MacroAssembler _masm(&cbuf);
2934 
2935     Register   str1_reg = reg_to_register_object($str1$$reg);
2936     Register   str2_reg = reg_to_register_object($str2$$reg);
2937     Register    cnt_reg = reg_to_register_object($cnt$$reg);
2938     Register   tmp1_reg = O7;
2939     Register result_reg = reg_to_register_object($result$$reg);
2940 
2941     assert(result_reg != str1_reg &&
2942            result_reg != str2_reg &&
2943            result_reg !=  cnt_reg &&
2944            result_reg != tmp1_reg ,
2945            "need different registers");
2946 
2947     __ cmp(str1_reg, str2_reg); //same char[] ?
2948     __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2949     __ delayed()->add(G0, 1, result_reg);
2950 
2951     __ bpr(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone);
2952     __ delayed()->add(G0, 1, result_reg); // count == 0
2953 
2954     //rename registers
2955     Register limit_reg =    cnt_reg;
2956     Register  chr1_reg = result_reg;
2957     Register  chr2_reg =   tmp1_reg;
2958 
2959     //check for alignment and position the pointers to the ends
2960     __ or3(str1_reg, str2_reg, chr1_reg);
2961     __ andcc(chr1_reg, 0x3, chr1_reg);
2962     // notZero means at least one not 4-byte aligned.
2963     // We could optimize the case when both arrays are not aligned
2964     // but it is not frequent case and it requires additional checks.
2965     __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2966     __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2967 
2968     // Compare char[] arrays aligned to 4 bytes.
2969     __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2970                           chr1_reg, chr2_reg, Ldone);
2971     __ ba(Ldone);
2972     __ delayed()->add(G0, 1, result_reg);
2973 
2974     // char by char compare
2975     __ bind(Lchar);
2976     __ add(str1_reg, limit_reg, str1_reg);
2977     __ add(str2_reg, limit_reg, str2_reg);
2978     __ neg(limit_reg); //negate count
2979 
2980     __ lduh(str1_reg, limit_reg, chr1_reg);
2981     // Lchar_loop
2982     __ bind(Lchar_loop);
2983     __ lduh(str2_reg, limit_reg, chr2_reg);
2984     __ cmp(chr1_reg, chr2_reg);
2985     __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2986     __ delayed()->mov(G0, result_reg); //not equal
2987     __ inccc(limit_reg, sizeof(jchar));
2988     // annul LDUH if branch is not taken to prevent access past end of string
2989     __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
2990     __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2991 
2992     __ add(G0, 1, result_reg);  //equal
2993 
2994     __ bind(Ldone);
2995   %}
2996 
2997 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
2998     Label Lvector, Ldone, Lloop;
2999     MacroAssembler _masm(&cbuf);
3000 
3001     Register   ary1_reg = reg_to_register_object($ary1$$reg);
3002     Register   ary2_reg = reg_to_register_object($ary2$$reg);
3003     Register   tmp1_reg = reg_to_register_object($tmp1$$reg);
3004     Register   tmp2_reg = O7;
3005     Register result_reg = reg_to_register_object($result$$reg);
3006 
3007     int length_offset  = arrayOopDesc::length_offset_in_bytes();
3008     int base_offset    = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3009 
3010     // return true if the same array
3011     __ cmp(ary1_reg, ary2_reg);
3012     __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3013     __ delayed()->add(G0, 1, result_reg); // equal
3014 
3015     __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3016     __ delayed()->mov(G0, result_reg);    // not equal
3017 
3018     __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3019     __ delayed()->mov(G0, result_reg);    // not equal
3020 
3021     //load the lengths of arrays
3022     __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3023     __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3024 
3025     // return false if the two arrays are not equal length
3026     __ cmp(tmp1_reg, tmp2_reg);
3027     __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3028     __ delayed()->mov(G0, result_reg);     // not equal
3029 
3030     __ bpr(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone);
3031     __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3032 
3033     // load array addresses
3034     __ add(ary1_reg, base_offset, ary1_reg);
3035     __ add(ary2_reg, base_offset, ary2_reg);
3036 
3037     // renaming registers
3038     Register chr1_reg  =  result_reg; // for characters in ary1
3039     Register chr2_reg  =  tmp2_reg;   // for characters in ary2
3040     Register limit_reg =  tmp1_reg;   // length
3041 
3042     // set byte count
3043     __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3044 
3045     // Compare char[] arrays aligned to 4 bytes.
3046     __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3047                           chr1_reg, chr2_reg, Ldone);
3048     __ add(G0, 1, result_reg); // equals
3049 
3050     __ bind(Ldone);
3051   %}
3052 
3053   enc_class enc_rethrow() %{
3054     cbuf.set_insts_mark();
3055     Register temp_reg = G3;
3056     AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3057     assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3058     MacroAssembler _masm(&cbuf);
3059 #ifdef ASSERT
3060     __ save_frame(0);
3061     AddressLiteral last_rethrow_addrlit(&last_rethrow);
3062     __ sethi(last_rethrow_addrlit, L1);
3063     Address addr(L1, last_rethrow_addrlit.low10());
3064     __ get_pc(L2);
3065     __ inc(L2, 3 * BytesPerInstWord);  // skip this & 2 more insns to point at jump_to
3066     __ st_ptr(L2, addr);
3067     __ restore();
3068 #endif
3069     __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3070     __ delayed()->nop();
3071   %}
3072 
3073   enc_class emit_mem_nop() %{
3074     // Generates the instruction LDUXA [o6,g0],#0x82,g0
3075     cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3076   %}
3077 
3078   enc_class emit_fadd_nop() %{
3079     // Generates the instruction FMOVS f31,f31
3080     cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3081   %}
3082 
3083   enc_class emit_br_nop() %{
3084     // Generates the instruction BPN,PN .
3085     cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3086   %}
3087 
3088   enc_class enc_membar_acquire %{
3089     MacroAssembler _masm(&cbuf);
3090     __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3091   %}
3092 
3093   enc_class enc_membar_release %{
3094     MacroAssembler _masm(&cbuf);
3095     __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3096   %}
3097 
3098   enc_class enc_membar_volatile %{
3099     MacroAssembler _masm(&cbuf);
3100     __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3101   %}
3102 
3103   enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3104     MacroAssembler _masm(&cbuf);
3105     Register src_reg = reg_to_register_object($src$$reg);
3106     Register dst_reg = reg_to_register_object($dst$$reg);
3107     __ sllx(src_reg, 56, dst_reg);
3108     __ srlx(dst_reg,  8, O7);
3109     __ or3 (dst_reg, O7, dst_reg);
3110     __ srlx(dst_reg, 16, O7);
3111     __ or3 (dst_reg, O7, dst_reg);
3112     __ srlx(dst_reg, 32, O7);
3113     __ or3 (dst_reg, O7, dst_reg);
3114   %}
3115 
3116   enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3117     MacroAssembler _masm(&cbuf);
3118     Register src_reg = reg_to_register_object($src$$reg);
3119     Register dst_reg = reg_to_register_object($dst$$reg);
3120     __ sll(src_reg, 24, dst_reg);
3121     __ srl(dst_reg,  8, O7);
3122     __ or3(dst_reg, O7, dst_reg);
3123     __ srl(dst_reg, 16, O7);
3124     __ or3(dst_reg, O7, dst_reg);
3125   %}
3126 
3127   enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3128     MacroAssembler _masm(&cbuf);
3129     Register src_reg = reg_to_register_object($src$$reg);
3130     Register dst_reg = reg_to_register_object($dst$$reg);
3131     __ sllx(src_reg, 48, dst_reg);
3132     __ srlx(dst_reg, 16, O7);
3133     __ or3 (dst_reg, O7, dst_reg);
3134     __ srlx(dst_reg, 32, O7);
3135     __ or3 (dst_reg, O7, dst_reg);
3136   %}
3137 
3138   enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3139     MacroAssembler _masm(&cbuf);
3140     Register src_reg = reg_to_register_object($src$$reg);
3141     Register dst_reg = reg_to_register_object($dst$$reg);
3142     __ sllx(src_reg, 32, dst_reg);
3143     __ srlx(dst_reg, 32, O7);
3144     __ or3 (dst_reg, O7, dst_reg);
3145   %}
3146 
3147 %}
3148 
3149 //----------FRAME--------------------------------------------------------------
3150 // Definition of frame structure and management information.
3151 //
3152 //  S T A C K   L A Y O U T    Allocators stack-slot number
3153 //                             |   (to get allocators register number
3154 //  G  Owned by    |        |  v    add VMRegImpl::stack0)
3155 //  r   CALLER     |        |
3156 //  o     |        +--------+      pad to even-align allocators stack-slot
3157 //  w     V        |  pad0  |        numbers; owned by CALLER
3158 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
3159 //  h     ^        |   in   |  5
3160 //        |        |  args  |  4   Holes in incoming args owned by SELF
3161 //  |     |        |        |  3
3162 //  |     |        +--------+
3163 //  V     |        | old out|      Empty on Intel, window on Sparc
3164 //        |    old |preserve|      Must be even aligned.
3165 //        |     SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3166 //        |        |   in   |  3   area for Intel ret address
3167 //     Owned by    |preserve|      Empty on Sparc.
3168 //       SELF      +--------+
3169 //        |        |  pad2  |  2   pad to align old SP
3170 //        |        +--------+  1
3171 //        |        | locks  |  0
3172 //        |        +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3173 //        |        |  pad1  | 11   pad to align new SP
3174 //        |        +--------+
3175 //        |        |        | 10
3176 //        |        | spills |  9   spills
3177 //        V        |        |  8   (pad0 slot for callee)
3178 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
3179 //        ^        |  out   |  7
3180 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
3181 //     Owned by    +--------+
3182 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
3183 //        |    new |preserve|      Must be even-aligned.
3184 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
3185 //        |        |        |
3186 //
3187 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
3188 //         known from SELF's arguments and the Java calling convention.
3189 //         Region 6-7 is determined per call site.
3190 // Note 2: If the calling convention leaves holes in the incoming argument
3191 //         area, those holes are owned by SELF.  Holes in the outgoing area
3192 //         are owned by the CALLEE.  Holes should not be nessecary in the
3193 //         incoming area, as the Java calling convention is completely under
3194 //         the control of the AD file.  Doubles can be sorted and packed to
3195 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
3196 //         varargs C calling conventions.
3197 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
3198 //         even aligned with pad0 as needed.
3199 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
3200 //         region 6-11 is even aligned; it may be padded out more so that
3201 //         the region from SP to FP meets the minimum stack alignment.
3202 
3203 frame %{
3204   // What direction does stack grow in (assumed to be same for native & Java)
3205   stack_direction(TOWARDS_LOW);
3206 
3207   // These two registers define part of the calling convention
3208   // between compiled code and the interpreter.
3209   inline_cache_reg(R_G5);                // Inline Cache Register or methodOop for I2C
3210   interpreter_method_oop_reg(R_G5);      // Method Oop Register when calling interpreter
3211 
3212   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3213   cisc_spilling_operand_name(indOffset);
3214 
3215   // Number of stack slots consumed by a Monitor enter
3216 #ifdef _LP64
3217   sync_stack_slots(2);
3218 #else
3219   sync_stack_slots(1);
3220 #endif
3221 
3222   // Compiled code's Frame Pointer
3223   frame_pointer(R_SP);
3224 
3225   // Stack alignment requirement
3226   stack_alignment(StackAlignmentInBytes);
3227   //  LP64: Alignment size in bytes (128-bit -> 16 bytes)
3228   // !LP64: Alignment size in bytes (64-bit  ->  8 bytes)
3229 
3230   // Number of stack slots between incoming argument block and the start of
3231   // a new frame.  The PROLOG must add this many slots to the stack.  The
3232   // EPILOG must remove this many slots.
3233   in_preserve_stack_slots(0);
3234 
3235   // Number of outgoing stack slots killed above the out_preserve_stack_slots
3236   // for calls to C.  Supports the var-args backing area for register parms.
3237   // ADLC doesn't support parsing expressions, so I folded the math by hand.
3238 #ifdef _LP64
3239   // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3240   varargs_C_out_slots_killed(12);
3241 #else
3242   // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3243   varargs_C_out_slots_killed( 7);
3244 #endif
3245 
3246   // The after-PROLOG location of the return address.  Location of
3247   // return address specifies a type (REG or STACK) and a number
3248   // representing the register number (i.e. - use a register name) or
3249   // stack slot.
3250   return_addr(REG R_I7);          // Ret Addr is in register I7
3251 
3252   // Body of function which returns an OptoRegs array locating
3253   // arguments either in registers or in stack slots for calling
3254   // java
3255   calling_convention %{
3256     (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3257 
3258   %}
3259 
3260   // Body of function which returns an OptoRegs array locating
3261   // arguments either in registers or in stack slots for callin
3262   // C.
3263   c_calling_convention %{
3264     // This is obviously always outgoing
3265     (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3266   %}
3267 
3268   // Location of native (C/C++) and interpreter return values.  This is specified to
3269   // be the  same as Java.  In the 32-bit VM, long values are actually returned from
3270   // native calls in O0:O1 and returned to the interpreter in I0:I1.  The copying
3271   // to and from the register pairs is done by the appropriate call and epilog
3272   // opcodes.  This simplifies the register allocator.
3273   c_return_value %{
3274     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3275 #ifdef     _LP64
3276     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
3277     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
3278     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
3279     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
3280 #else  // !_LP64
3281     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
3282     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3283     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
3284     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3285 #endif
3286     return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3287                         (is_outgoing?lo_out:lo_in)[ideal_reg] );
3288   %}
3289 
3290   // Location of compiled Java return values.  Same as C
3291   return_value %{
3292     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3293 #ifdef     _LP64
3294     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
3295     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
3296     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
3297     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
3298 #else  // !_LP64
3299     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
3300     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3301     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
3302     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3303 #endif
3304     return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3305                         (is_outgoing?lo_out:lo_in)[ideal_reg] );
3306   %}
3307 
3308 %}
3309 
3310 
3311 //----------ATTRIBUTES---------------------------------------------------------
3312 //----------Operand Attributes-------------------------------------------------
3313 op_attrib op_cost(1);          // Required cost attribute
3314 
3315 //----------Instruction Attributes---------------------------------------------
3316 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3317 ins_attrib ins_size(32);       // Required size attribute (in bits)
3318 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3319 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3320                                 // non-matching short branch variant of some
3321                                                             // long branch?
3322 
3323 //----------OPERANDS-----------------------------------------------------------
3324 // Operand definitions must precede instruction definitions for correct parsing
3325 // in the ADLC because operands constitute user defined types which are used in
3326 // instruction definitions.
3327 
3328 //----------Simple Operands----------------------------------------------------
3329 // Immediate Operands
3330 // Integer Immediate: 32-bit
3331 operand immI() %{
3332   match(ConI);
3333 
3334   op_cost(0);
3335   // formats are generated automatically for constants and base registers
3336   format %{ %}
3337   interface(CONST_INTER);
3338 %}
3339 
3340 // Integer Immediate: 8-bit
3341 operand immI8() %{
3342   predicate(Assembler::is_simm(n->get_int(), 8));
3343   match(ConI);
3344   op_cost(0);
3345   format %{ %}
3346   interface(CONST_INTER);
3347 %}
3348 
3349 // Integer Immediate: 13-bit
3350 operand immI13() %{
3351   predicate(Assembler::is_simm13(n->get_int()));
3352   match(ConI);
3353   op_cost(0);
3354 
3355   format %{ %}
3356   interface(CONST_INTER);
3357 %}
3358 
3359 // Integer Immediate: 13-bit minus 7
3360 operand immI13m7() %{
3361   predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3362   match(ConI);
3363   op_cost(0);
3364 
3365   format %{ %}
3366   interface(CONST_INTER);
3367 %}
3368 
3369 // Integer Immediate: 16-bit
3370 operand immI16() %{
3371   predicate(Assembler::is_simm(n->get_int(), 16));
3372   match(ConI);
3373   op_cost(0);
3374   format %{ %}
3375   interface(CONST_INTER);
3376 %}
3377 
3378 // Unsigned (positive) Integer Immediate: 13-bit
3379 operand immU13() %{
3380   predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3381   match(ConI);
3382   op_cost(0);
3383 
3384   format %{ %}
3385   interface(CONST_INTER);
3386 %}
3387 
3388 // Integer Immediate: 6-bit
3389 operand immU6() %{
3390   predicate(n->get_int() >= 0 && n->get_int() <= 63);
3391   match(ConI);
3392   op_cost(0);
3393   format %{ %}
3394   interface(CONST_INTER);
3395 %}
3396 
3397 // Integer Immediate: 11-bit
3398 operand immI11() %{
3399   predicate(Assembler::is_simm(n->get_int(),11));
3400   match(ConI);
3401   op_cost(0);
3402   format %{ %}
3403   interface(CONST_INTER);
3404 %}
3405 
3406 // Integer Immediate: 0-bit
3407 operand immI0() %{
3408   predicate(n->get_int() == 0);
3409   match(ConI);
3410   op_cost(0);
3411 
3412   format %{ %}
3413   interface(CONST_INTER);
3414 %}
3415 
3416 // Integer Immediate: the value 10
3417 operand immI10() %{
3418   predicate(n->get_int() == 10);
3419   match(ConI);
3420   op_cost(0);
3421 
3422   format %{ %}
3423   interface(CONST_INTER);
3424 %}
3425 
3426 // Integer Immediate: the values 0-31
3427 operand immU5() %{
3428   predicate(n->get_int() >= 0 && n->get_int() <= 31);
3429   match(ConI);
3430   op_cost(0);
3431 
3432   format %{ %}
3433   interface(CONST_INTER);
3434 %}
3435 
3436 // Integer Immediate: the values 1-31
3437 operand immI_1_31() %{
3438   predicate(n->get_int() >= 1 && n->get_int() <= 31);
3439   match(ConI);
3440   op_cost(0);
3441 
3442   format %{ %}
3443   interface(CONST_INTER);
3444 %}
3445 
3446 // Integer Immediate: the values 32-63
3447 operand immI_32_63() %{
3448   predicate(n->get_int() >= 32 && n->get_int() <= 63);
3449   match(ConI);
3450   op_cost(0);
3451 
3452   format %{ %}
3453   interface(CONST_INTER);
3454 %}
3455 
3456 // Immediates for special shifts (sign extend)
3457 
3458 // Integer Immediate: the value 16
3459 operand immI_16() %{
3460   predicate(n->get_int() == 16);
3461   match(ConI);
3462   op_cost(0);
3463 
3464   format %{ %}
3465   interface(CONST_INTER);
3466 %}
3467 
3468 // Integer Immediate: the value 24
3469 operand immI_24() %{
3470   predicate(n->get_int() == 24);
3471   match(ConI);
3472   op_cost(0);
3473 
3474   format %{ %}
3475   interface(CONST_INTER);
3476 %}
3477 
3478 // Integer Immediate: the value 255
3479 operand immI_255() %{
3480   predicate( n->get_int() == 255 );
3481   match(ConI);
3482   op_cost(0);
3483 
3484   format %{ %}
3485   interface(CONST_INTER);
3486 %}
3487 
3488 // Integer Immediate: the value 65535
3489 operand immI_65535() %{
3490   predicate(n->get_int() == 65535);
3491   match(ConI);
3492   op_cost(0);
3493 
3494   format %{ %}
3495   interface(CONST_INTER);
3496 %}
3497 
3498 // Long Immediate: the value FF
3499 operand immL_FF() %{
3500   predicate( n->get_long() == 0xFFL );
3501   match(ConL);
3502   op_cost(0);
3503 
3504   format %{ %}
3505   interface(CONST_INTER);
3506 %}
3507 
3508 // Long Immediate: the value FFFF
3509 operand immL_FFFF() %{
3510   predicate( n->get_long() == 0xFFFFL );
3511   match(ConL);
3512   op_cost(0);
3513 
3514   format %{ %}
3515   interface(CONST_INTER);
3516 %}
3517 
3518 // Pointer Immediate: 32 or 64-bit
3519 operand immP() %{
3520   match(ConP);
3521 
3522   op_cost(5);
3523   // formats are generated automatically for constants and base registers
3524   format %{ %}
3525   interface(CONST_INTER);
3526 %}
3527 
3528 #ifdef _LP64
3529 // Pointer Immediate: 64-bit
3530 operand immP_set() %{
3531   predicate(!VM_Version::is_niagara_plus());
3532   match(ConP);
3533 
3534   op_cost(5);
3535   // formats are generated automatically for constants and base registers
3536   format %{ %}
3537   interface(CONST_INTER);
3538 %}
3539 
3540 // Pointer Immediate: 64-bit
3541 // From Niagara2 processors on a load should be better than materializing.
3542 operand immP_load() %{
3543   predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3544   match(ConP);
3545 
3546   op_cost(5);
3547   // formats are generated automatically for constants and base registers
3548   format %{ %}
3549   interface(CONST_INTER);
3550 %}
3551 
3552 // Pointer Immediate: 64-bit
3553 operand immP_no_oop_cheap() %{
3554   predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3555   match(ConP);
3556 
3557   op_cost(5);
3558   // formats are generated automatically for constants and base registers
3559   format %{ %}
3560   interface(CONST_INTER);
3561 %}
3562 #endif
3563 
3564 operand immP13() %{
3565   predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3566   match(ConP);
3567   op_cost(0);
3568 
3569   format %{ %}
3570   interface(CONST_INTER);
3571 %}
3572 
3573 operand immP0() %{
3574   predicate(n->get_ptr() == 0);
3575   match(ConP);
3576   op_cost(0);
3577 
3578   format %{ %}
3579   interface(CONST_INTER);
3580 %}
3581 
3582 operand immP_poll() %{
3583   predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3584   match(ConP);
3585 
3586   // formats are generated automatically for constants and base registers
3587   format %{ %}
3588   interface(CONST_INTER);
3589 %}
3590 
3591 // Pointer Immediate
3592 operand immN()
3593 %{
3594   match(ConN);
3595 
3596   op_cost(10);
3597   format %{ %}
3598   interface(CONST_INTER);
3599 %}
3600 
3601 // NULL Pointer Immediate
3602 operand immN0()
3603 %{
3604   predicate(n->get_narrowcon() == 0);
3605   match(ConN);
3606 
3607   op_cost(0);
3608   format %{ %}
3609   interface(CONST_INTER);
3610 %}
3611 
3612 operand immL() %{
3613   match(ConL);
3614   op_cost(40);
3615   // formats are generated automatically for constants and base registers
3616   format %{ %}
3617   interface(CONST_INTER);
3618 %}
3619 
3620 operand immL0() %{
3621   predicate(n->get_long() == 0L);
3622   match(ConL);
3623   op_cost(0);
3624   // formats are generated automatically for constants and base registers
3625   format %{ %}
3626   interface(CONST_INTER);
3627 %}
3628 
3629 // Long Immediate: 13-bit
3630 operand immL13() %{
3631   predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3632   match(ConL);
3633   op_cost(0);
3634 
3635   format %{ %}
3636   interface(CONST_INTER);
3637 %}
3638 
3639 // Long Immediate: 13-bit minus 7
3640 operand immL13m7() %{
3641   predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3642   match(ConL);
3643   op_cost(0);
3644 
3645   format %{ %}
3646   interface(CONST_INTER);
3647 %}
3648 
3649 // Long Immediate: low 32-bit mask
3650 operand immL_32bits() %{
3651   predicate(n->get_long() == 0xFFFFFFFFL);
3652   match(ConL);
3653   op_cost(0);
3654 
3655   format %{ %}
3656   interface(CONST_INTER);
3657 %}
3658 
3659 // Long Immediate: cheap (materialize in <= 3 instructions)
3660 operand immL_cheap() %{
3661   predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3662   match(ConL);
3663   op_cost(0);
3664 
3665   format %{ %}
3666   interface(CONST_INTER);
3667 %}
3668 
3669 // Long Immediate: expensive (materialize in > 3 instructions)
3670 operand immL_expensive() %{
3671   predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3672   match(ConL);
3673   op_cost(0);
3674 
3675   format %{ %}
3676   interface(CONST_INTER);
3677 %}
3678 
3679 // Double Immediate
3680 operand immD() %{
3681   match(ConD);
3682 
3683   op_cost(40);
3684   format %{ %}
3685   interface(CONST_INTER);
3686 %}
3687 
3688 operand immD0() %{
3689 #ifdef _LP64
3690   // on 64-bit architectures this comparision is faster
3691   predicate(jlong_cast(n->getd()) == 0);
3692 #else
3693   predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3694 #endif
3695   match(ConD);
3696 
3697   op_cost(0);
3698   format %{ %}
3699   interface(CONST_INTER);
3700 %}
3701 
3702 // Float Immediate
3703 operand immF() %{
3704   match(ConF);
3705 
3706   op_cost(20);
3707   format %{ %}
3708   interface(CONST_INTER);
3709 %}
3710 
3711 // Float Immediate: 0
3712 operand immF0() %{
3713   predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3714   match(ConF);
3715 
3716   op_cost(0);
3717   format %{ %}
3718   interface(CONST_INTER);
3719 %}
3720 
3721 // Integer Register Operands
3722 // Integer Register
3723 operand iRegI() %{
3724   constraint(ALLOC_IN_RC(int_reg));
3725   match(RegI);
3726 
3727   match(notemp_iRegI);
3728   match(g1RegI);
3729   match(o0RegI);
3730   match(iRegIsafe);
3731 
3732   format %{ %}
3733   interface(REG_INTER);
3734 %}
3735 
3736 operand notemp_iRegI() %{
3737   constraint(ALLOC_IN_RC(notemp_int_reg));
3738   match(RegI);
3739 
3740   match(o0RegI);
3741 
3742   format %{ %}
3743   interface(REG_INTER);
3744 %}
3745 
3746 operand o0RegI() %{
3747   constraint(ALLOC_IN_RC(o0_regI));
3748   match(iRegI);
3749 
3750   format %{ %}
3751   interface(REG_INTER);
3752 %}
3753 
3754 // Pointer Register
3755 operand iRegP() %{
3756   constraint(ALLOC_IN_RC(ptr_reg));
3757   match(RegP);
3758 
3759   match(lock_ptr_RegP);
3760   match(g1RegP);
3761   match(g2RegP);
3762   match(g3RegP);
3763   match(g4RegP);
3764   match(i0RegP);
3765   match(o0RegP);
3766   match(o1RegP);
3767   match(l7RegP);
3768 
3769   format %{ %}
3770   interface(REG_INTER);
3771 %}
3772 
3773 operand sp_ptr_RegP() %{
3774   constraint(ALLOC_IN_RC(sp_ptr_reg));
3775   match(RegP);
3776   match(iRegP);
3777 
3778   format %{ %}
3779   interface(REG_INTER);
3780 %}
3781 
3782 operand lock_ptr_RegP() %{
3783   constraint(ALLOC_IN_RC(lock_ptr_reg));
3784   match(RegP);
3785   match(i0RegP);
3786   match(o0RegP);
3787   match(o1RegP);
3788   match(l7RegP);
3789 
3790   format %{ %}
3791   interface(REG_INTER);
3792 %}
3793 
3794 operand g1RegP() %{
3795   constraint(ALLOC_IN_RC(g1_regP));
3796   match(iRegP);
3797 
3798   format %{ %}
3799   interface(REG_INTER);
3800 %}
3801 
3802 operand g2RegP() %{
3803   constraint(ALLOC_IN_RC(g2_regP));
3804   match(iRegP);
3805 
3806   format %{ %}
3807   interface(REG_INTER);
3808 %}
3809 
3810 operand g3RegP() %{
3811   constraint(ALLOC_IN_RC(g3_regP));
3812   match(iRegP);
3813 
3814   format %{ %}
3815   interface(REG_INTER);
3816 %}
3817 
3818 operand g1RegI() %{
3819   constraint(ALLOC_IN_RC(g1_regI));
3820   match(iRegI);
3821 
3822   format %{ %}
3823   interface(REG_INTER);
3824 %}
3825 
3826 operand g3RegI() %{
3827   constraint(ALLOC_IN_RC(g3_regI));
3828   match(iRegI);
3829 
3830   format %{ %}
3831   interface(REG_INTER);
3832 %}
3833 
3834 operand g4RegI() %{
3835   constraint(ALLOC_IN_RC(g4_regI));
3836   match(iRegI);
3837 
3838   format %{ %}
3839   interface(REG_INTER);
3840 %}
3841 
3842 operand g4RegP() %{
3843   constraint(ALLOC_IN_RC(g4_regP));
3844   match(iRegP);
3845 
3846   format %{ %}
3847   interface(REG_INTER);
3848 %}
3849 
3850 operand i0RegP() %{
3851   constraint(ALLOC_IN_RC(i0_regP));
3852   match(iRegP);
3853 
3854   format %{ %}
3855   interface(REG_INTER);
3856 %}
3857 
3858 operand o0RegP() %{
3859   constraint(ALLOC_IN_RC(o0_regP));
3860   match(iRegP);
3861 
3862   format %{ %}
3863   interface(REG_INTER);
3864 %}
3865 
3866 operand o1RegP() %{
3867   constraint(ALLOC_IN_RC(o1_regP));
3868   match(iRegP);
3869 
3870   format %{ %}
3871   interface(REG_INTER);
3872 %}
3873 
3874 operand o2RegP() %{
3875   constraint(ALLOC_IN_RC(o2_regP));
3876   match(iRegP);
3877 
3878   format %{ %}
3879   interface(REG_INTER);
3880 %}
3881 
3882 operand o7RegP() %{
3883   constraint(ALLOC_IN_RC(o7_regP));
3884   match(iRegP);
3885 
3886   format %{ %}
3887   interface(REG_INTER);
3888 %}
3889 
3890 operand l7RegP() %{
3891   constraint(ALLOC_IN_RC(l7_regP));
3892   match(iRegP);
3893 
3894   format %{ %}
3895   interface(REG_INTER);
3896 %}
3897 
3898 operand o7RegI() %{
3899   constraint(ALLOC_IN_RC(o7_regI));
3900   match(iRegI);
3901 
3902   format %{ %}
3903   interface(REG_INTER);
3904 %}
3905 
3906 operand iRegN() %{
3907   constraint(ALLOC_IN_RC(int_reg));
3908   match(RegN);
3909 
3910   format %{ %}
3911   interface(REG_INTER);
3912 %}
3913 
3914 // Long Register
3915 operand iRegL() %{
3916   constraint(ALLOC_IN_RC(long_reg));
3917   match(RegL);
3918 
3919   format %{ %}
3920   interface(REG_INTER);
3921 %}
3922 
3923 operand o2RegL() %{
3924   constraint(ALLOC_IN_RC(o2_regL));
3925   match(iRegL);
3926 
3927   format %{ %}
3928   interface(REG_INTER);
3929 %}
3930 
3931 operand o7RegL() %{
3932   constraint(ALLOC_IN_RC(o7_regL));
3933   match(iRegL);
3934 
3935   format %{ %}
3936   interface(REG_INTER);
3937 %}
3938 
3939 operand g1RegL() %{
3940   constraint(ALLOC_IN_RC(g1_regL));
3941   match(iRegL);
3942 
3943   format %{ %}
3944   interface(REG_INTER);
3945 %}
3946 
3947 operand g3RegL() %{
3948   constraint(ALLOC_IN_RC(g3_regL));
3949   match(iRegL);
3950 
3951   format %{ %}
3952   interface(REG_INTER);
3953 %}
3954 
3955 // Int Register safe
3956 // This is 64bit safe
3957 operand iRegIsafe() %{
3958   constraint(ALLOC_IN_RC(long_reg));
3959 
3960   match(iRegI);
3961 
3962   format %{ %}
3963   interface(REG_INTER);
3964 %}
3965 
3966 // Condition Code Flag Register
3967 operand flagsReg() %{
3968   constraint(ALLOC_IN_RC(int_flags));
3969   match(RegFlags);
3970 
3971   format %{ "ccr" %} // both ICC and XCC
3972   interface(REG_INTER);
3973 %}
3974 
3975 // Condition Code Register, unsigned comparisons.
3976 operand flagsRegU() %{
3977   constraint(ALLOC_IN_RC(int_flags));
3978   match(RegFlags);
3979 
3980   format %{ "icc_U" %}
3981   interface(REG_INTER);
3982 %}
3983 
3984 // Condition Code Register, pointer comparisons.
3985 operand flagsRegP() %{
3986   constraint(ALLOC_IN_RC(int_flags));
3987   match(RegFlags);
3988 
3989 #ifdef _LP64
3990   format %{ "xcc_P" %}
3991 #else
3992   format %{ "icc_P" %}
3993 #endif
3994   interface(REG_INTER);
3995 %}
3996 
3997 // Condition Code Register, long comparisons.
3998 operand flagsRegL() %{
3999   constraint(ALLOC_IN_RC(int_flags));
4000   match(RegFlags);
4001 
4002   format %{ "xcc_L" %}
4003   interface(REG_INTER);
4004 %}
4005 
4006 // Condition Code Register, floating comparisons, unordered same as "less".
4007 operand flagsRegF() %{
4008   constraint(ALLOC_IN_RC(float_flags));
4009   match(RegFlags);
4010   match(flagsRegF0);
4011 
4012   format %{ %}
4013   interface(REG_INTER);
4014 %}
4015 
4016 operand flagsRegF0() %{
4017   constraint(ALLOC_IN_RC(float_flag0));
4018   match(RegFlags);
4019 
4020   format %{ %}
4021   interface(REG_INTER);
4022 %}
4023 
4024 
4025 // Condition Code Flag Register used by long compare
4026 operand flagsReg_long_LTGE() %{
4027   constraint(ALLOC_IN_RC(int_flags));
4028   match(RegFlags);
4029   format %{ "icc_LTGE" %}
4030   interface(REG_INTER);
4031 %}
4032 operand flagsReg_long_EQNE() %{
4033   constraint(ALLOC_IN_RC(int_flags));
4034   match(RegFlags);
4035   format %{ "icc_EQNE" %}
4036   interface(REG_INTER);
4037 %}
4038 operand flagsReg_long_LEGT() %{
4039   constraint(ALLOC_IN_RC(int_flags));
4040   match(RegFlags);
4041   format %{ "icc_LEGT" %}
4042   interface(REG_INTER);
4043 %}
4044 
4045 
4046 operand regD() %{
4047   constraint(ALLOC_IN_RC(dflt_reg));
4048   match(RegD);
4049 
4050   match(regD_low);
4051 
4052   format %{ %}
4053   interface(REG_INTER);
4054 %}
4055 
4056 operand regF() %{
4057   constraint(ALLOC_IN_RC(sflt_reg));
4058   match(RegF);
4059 
4060   format %{ %}
4061   interface(REG_INTER);
4062 %}
4063 
4064 operand regD_low() %{
4065   constraint(ALLOC_IN_RC(dflt_low_reg));
4066   match(regD);
4067 
4068   format %{ %}
4069   interface(REG_INTER);
4070 %}
4071 
4072 // Special Registers
4073 
4074 // Method Register
4075 operand inline_cache_regP(iRegP reg) %{
4076   constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4077   match(reg);
4078   format %{ %}
4079   interface(REG_INTER);
4080 %}
4081 
4082 operand interpreter_method_oop_regP(iRegP reg) %{
4083   constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4084   match(reg);
4085   format %{ %}
4086   interface(REG_INTER);
4087 %}
4088 
4089 
4090 //----------Complex Operands---------------------------------------------------
4091 // Indirect Memory Reference
4092 operand indirect(sp_ptr_RegP reg) %{
4093   constraint(ALLOC_IN_RC(sp_ptr_reg));
4094   match(reg);
4095 
4096   op_cost(100);
4097   format %{ "[$reg]" %}
4098   interface(MEMORY_INTER) %{
4099     base($reg);
4100     index(0x0);
4101     scale(0x0);
4102     disp(0x0);
4103   %}
4104 %}
4105 
4106 // Indirect with simm13 Offset
4107 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4108   constraint(ALLOC_IN_RC(sp_ptr_reg));
4109   match(AddP reg offset);
4110 
4111   op_cost(100);
4112   format %{ "[$reg + $offset]" %}
4113   interface(MEMORY_INTER) %{
4114     base($reg);
4115     index(0x0);
4116     scale(0x0);
4117     disp($offset);
4118   %}
4119 %}
4120 
4121 // Indirect with simm13 Offset minus 7
4122 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4123   constraint(ALLOC_IN_RC(sp_ptr_reg));
4124   match(AddP reg offset);
4125 
4126   op_cost(100);
4127   format %{ "[$reg + $offset]" %}
4128   interface(MEMORY_INTER) %{
4129     base($reg);
4130     index(0x0);
4131     scale(0x0);
4132     disp($offset);
4133   %}
4134 %}
4135 
4136 // Note:  Intel has a swapped version also, like this:
4137 //operand indOffsetX(iRegI reg, immP offset) %{
4138 //  constraint(ALLOC_IN_RC(int_reg));
4139 //  match(AddP offset reg);
4140 //
4141 //  op_cost(100);
4142 //  format %{ "[$reg + $offset]" %}
4143 //  interface(MEMORY_INTER) %{
4144 //    base($reg);
4145 //    index(0x0);
4146 //    scale(0x0);
4147 //    disp($offset);
4148 //  %}
4149 //%}
4150 //// However, it doesn't make sense for SPARC, since
4151 // we have no particularly good way to embed oops in
4152 // single instructions.
4153 
4154 // Indirect with Register Index
4155 operand indIndex(iRegP addr, iRegX index) %{
4156   constraint(ALLOC_IN_RC(ptr_reg));
4157   match(AddP addr index);
4158 
4159   op_cost(100);
4160   format %{ "[$addr + $index]" %}
4161   interface(MEMORY_INTER) %{
4162     base($addr);
4163     index($index);
4164     scale(0x0);
4165     disp(0x0);
4166   %}
4167 %}
4168 
4169 //----------Special Memory Operands--------------------------------------------
4170 // Stack Slot Operand - This operand is used for loading and storing temporary
4171 //                      values on the stack where a match requires a value to
4172 //                      flow through memory.
4173 operand stackSlotI(sRegI reg) %{
4174   constraint(ALLOC_IN_RC(stack_slots));
4175   op_cost(100);
4176   //match(RegI);
4177   format %{ "[$reg]" %}
4178   interface(MEMORY_INTER) %{
4179     base(0xE);   // R_SP
4180     index(0x0);
4181     scale(0x0);
4182     disp($reg);  // Stack Offset
4183   %}
4184 %}
4185 
4186 operand stackSlotP(sRegP reg) %{
4187   constraint(ALLOC_IN_RC(stack_slots));
4188   op_cost(100);
4189   //match(RegP);
4190   format %{ "[$reg]" %}
4191   interface(MEMORY_INTER) %{
4192     base(0xE);   // R_SP
4193     index(0x0);
4194     scale(0x0);
4195     disp($reg);  // Stack Offset
4196   %}
4197 %}
4198 
4199 operand stackSlotF(sRegF reg) %{
4200   constraint(ALLOC_IN_RC(stack_slots));
4201   op_cost(100);
4202   //match(RegF);
4203   format %{ "[$reg]" %}
4204   interface(MEMORY_INTER) %{
4205     base(0xE);   // R_SP
4206     index(0x0);
4207     scale(0x0);
4208     disp($reg);  // Stack Offset
4209   %}
4210 %}
4211 operand stackSlotD(sRegD reg) %{
4212   constraint(ALLOC_IN_RC(stack_slots));
4213   op_cost(100);
4214   //match(RegD);
4215   format %{ "[$reg]" %}
4216   interface(MEMORY_INTER) %{
4217     base(0xE);   // R_SP
4218     index(0x0);
4219     scale(0x0);
4220     disp($reg);  // Stack Offset
4221   %}
4222 %}
4223 operand stackSlotL(sRegL reg) %{
4224   constraint(ALLOC_IN_RC(stack_slots));
4225   op_cost(100);
4226   //match(RegL);
4227   format %{ "[$reg]" %}
4228   interface(MEMORY_INTER) %{
4229     base(0xE);   // R_SP
4230     index(0x0);
4231     scale(0x0);
4232     disp($reg);  // Stack Offset
4233   %}
4234 %}
4235 
4236 // Operands for expressing Control Flow
4237 // NOTE:  Label is a predefined operand which should not be redefined in
4238 //        the AD file.  It is generically handled within the ADLC.
4239 
4240 //----------Conditional Branch Operands----------------------------------------
4241 // Comparison Op  - This is the operation of the comparison, and is limited to
4242 //                  the following set of codes:
4243 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4244 //
4245 // Other attributes of the comparison, such as unsignedness, are specified
4246 // by the comparison instruction that sets a condition code flags register.
4247 // That result is represented by a flags operand whose subtype is appropriate
4248 // to the unsignedness (etc.) of the comparison.
4249 //
4250 // Later, the instruction which matches both the Comparison Op (a Bool) and
4251 // the flags (produced by the Cmp) specifies the coding of the comparison op
4252 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4253 
4254 operand cmpOp() %{
4255   match(Bool);
4256 
4257   format %{ "" %}
4258   interface(COND_INTER) %{
4259     equal(0x1);
4260     not_equal(0x9);
4261     less(0x3);
4262     greater_equal(0xB);
4263     less_equal(0x2);
4264     greater(0xA);
4265   %}
4266 %}
4267 
4268 // Comparison Op, unsigned
4269 operand cmpOpU() %{
4270   match(Bool);
4271 
4272   format %{ "u" %}
4273   interface(COND_INTER) %{
4274     equal(0x1);
4275     not_equal(0x9);
4276     less(0x5);
4277     greater_equal(0xD);
4278     less_equal(0x4);
4279     greater(0xC);
4280   %}
4281 %}
4282 
4283 // Comparison Op, pointer (same as unsigned)
4284 operand cmpOpP() %{
4285   match(Bool);
4286 
4287   format %{ "p" %}
4288   interface(COND_INTER) %{
4289     equal(0x1);
4290     not_equal(0x9);
4291     less(0x5);
4292     greater_equal(0xD);
4293     less_equal(0x4);
4294     greater(0xC);
4295   %}
4296 %}
4297 
4298 // Comparison Op, branch-register encoding
4299 operand cmpOp_reg() %{
4300   match(Bool);
4301 
4302   format %{ "" %}
4303   interface(COND_INTER) %{
4304     equal        (0x1);
4305     not_equal    (0x5);
4306     less         (0x3);
4307     greater_equal(0x7);
4308     less_equal   (0x2);
4309     greater      (0x6);
4310   %}
4311 %}
4312 
4313 // Comparison Code, floating, unordered same as less
4314 operand cmpOpF() %{
4315   match(Bool);
4316 
4317   format %{ "fl" %}
4318   interface(COND_INTER) %{
4319     equal(0x9);
4320     not_equal(0x1);
4321     less(0x3);
4322     greater_equal(0xB);
4323     less_equal(0xE);
4324     greater(0x6);
4325   %}
4326 %}
4327 
4328 // Used by long compare
4329 operand cmpOp_commute() %{
4330   match(Bool);
4331 
4332   format %{ "" %}
4333   interface(COND_INTER) %{
4334     equal(0x1);
4335     not_equal(0x9);
4336     less(0xA);
4337     greater_equal(0x2);
4338     less_equal(0xB);
4339     greater(0x3);
4340   %}
4341 %}
4342 
4343 //----------OPERAND CLASSES----------------------------------------------------
4344 // Operand Classes are groups of operands that are used to simplify
4345 // instruction definitions by not requiring the AD writer to specify separate
4346 // instructions for every form of operand when the instruction accepts
4347 // multiple operand types with the same basic encoding and format.  The classic
4348 // case of this is memory operands.
4349 opclass memory( indirect, indOffset13, indIndex );
4350 opclass indIndexMemory( indIndex );
4351 
4352 //----------PIPELINE-----------------------------------------------------------
4353 pipeline %{
4354 
4355 //----------ATTRIBUTES---------------------------------------------------------
4356 attributes %{
4357   fixed_size_instructions;           // Fixed size instructions
4358   branch_has_delay_slot;             // Branch has delay slot following
4359   max_instructions_per_bundle = 4;   // Up to 4 instructions per bundle
4360   instruction_unit_size = 4;         // An instruction is 4 bytes long
4361   instruction_fetch_unit_size = 16;  // The processor fetches one line
4362   instruction_fetch_units = 1;       // of 16 bytes
4363 
4364   // List of nop instructions
4365   nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4366 %}
4367 
4368 //----------RESOURCES----------------------------------------------------------
4369 // Resources are the functional units available to the machine
4370 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4371 
4372 //----------PIPELINE DESCRIPTION-----------------------------------------------
4373 // Pipeline Description specifies the stages in the machine's pipeline
4374 
4375 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4376 
4377 //----------PIPELINE CLASSES---------------------------------------------------
4378 // Pipeline Classes describe the stages in which input and output are
4379 // referenced by the hardware pipeline.
4380 
4381 // Integer ALU reg-reg operation
4382 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4383     single_instruction;
4384     dst   : E(write);
4385     src1  : R(read);
4386     src2  : R(read);
4387     IALU  : R;
4388 %}
4389 
4390 // Integer ALU reg-reg long operation
4391 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4392     instruction_count(2);
4393     dst   : E(write);
4394     src1  : R(read);
4395     src2  : R(read);
4396     IALU  : R;
4397     IALU  : R;
4398 %}
4399 
4400 // Integer ALU reg-reg long dependent operation
4401 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4402     instruction_count(1); multiple_bundles;
4403     dst   : E(write);
4404     src1  : R(read);
4405     src2  : R(read);
4406     cr    : E(write);
4407     IALU  : R(2);
4408 %}
4409 
4410 // Integer ALU reg-imm operaion
4411 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4412     single_instruction;
4413     dst   : E(write);
4414     src1  : R(read);
4415     IALU  : R;
4416 %}
4417 
4418 // Integer ALU reg-reg operation with condition code
4419 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4420     single_instruction;
4421     dst   : E(write);
4422     cr    : E(write);
4423     src1  : R(read);
4424     src2  : R(read);
4425     IALU  : R;
4426 %}
4427 
4428 // Integer ALU reg-imm operation with condition code
4429 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4430     single_instruction;
4431     dst   : E(write);
4432     cr    : E(write);
4433     src1  : R(read);
4434     IALU  : R;
4435 %}
4436 
4437 // Integer ALU zero-reg operation
4438 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4439     single_instruction;
4440     dst   : E(write);
4441     src2  : R(read);
4442     IALU  : R;
4443 %}
4444 
4445 // Integer ALU zero-reg operation with condition code only
4446 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4447     single_instruction;
4448     cr    : E(write);
4449     src   : R(read);
4450     IALU  : R;
4451 %}
4452 
4453 // Integer ALU reg-reg operation with condition code only
4454 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4455     single_instruction;
4456     cr    : E(write);
4457     src1  : R(read);
4458     src2  : R(read);
4459     IALU  : R;
4460 %}
4461 
4462 // Integer ALU reg-imm operation with condition code only
4463 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4464     single_instruction;
4465     cr    : E(write);
4466     src1  : R(read);
4467     IALU  : R;
4468 %}
4469 
4470 // Integer ALU reg-reg-zero operation with condition code only
4471 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4472     single_instruction;
4473     cr    : E(write);
4474     src1  : R(read);
4475     src2  : R(read);
4476     IALU  : R;
4477 %}
4478 
4479 // Integer ALU reg-imm-zero operation with condition code only
4480 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4481     single_instruction;
4482     cr    : E(write);
4483     src1  : R(read);
4484     IALU  : R;
4485 %}
4486 
4487 // Integer ALU reg-reg operation with condition code, src1 modified
4488 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4489     single_instruction;
4490     cr    : E(write);
4491     src1  : E(write);
4492     src1  : R(read);
4493     src2  : R(read);
4494     IALU  : R;
4495 %}
4496 
4497 // Integer ALU reg-imm operation with condition code, src1 modified
4498 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4499     single_instruction;
4500     cr    : E(write);
4501     src1  : E(write);
4502     src1  : R(read);
4503     IALU  : R;
4504 %}
4505 
4506 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4507     multiple_bundles;
4508     dst   : E(write)+4;
4509     cr    : E(write);
4510     src1  : R(read);
4511     src2  : R(read);
4512     IALU  : R(3);
4513     BR    : R(2);
4514 %}
4515 
4516 // Integer ALU operation
4517 pipe_class ialu_none(iRegI dst) %{
4518     single_instruction;
4519     dst   : E(write);
4520     IALU  : R;
4521 %}
4522 
4523 // Integer ALU reg operation
4524 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4525     single_instruction; may_have_no_code;
4526     dst   : E(write);
4527     src   : R(read);
4528     IALU  : R;
4529 %}
4530 
4531 // Integer ALU reg conditional operation
4532 // This instruction has a 1 cycle stall, and cannot execute
4533 // in the same cycle as the instruction setting the condition
4534 // code. We kludge this by pretending to read the condition code
4535 // 1 cycle earlier, and by marking the functional units as busy
4536 // for 2 cycles with the result available 1 cycle later than
4537 // is really the case.
4538 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4539     single_instruction;
4540     op2_out : C(write);
4541     op1     : R(read);
4542     cr      : R(read);       // This is really E, with a 1 cycle stall
4543     BR      : R(2);
4544     MS      : R(2);
4545 %}
4546 
4547 #ifdef _LP64
4548 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4549     instruction_count(1); multiple_bundles;
4550     dst     : C(write)+1;
4551     src     : R(read)+1;
4552     IALU    : R(1);
4553     BR      : E(2);
4554     MS      : E(2);
4555 %}
4556 #endif
4557 
4558 // Integer ALU reg operation
4559 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4560     single_instruction; may_have_no_code;
4561     dst   : E(write);
4562     src   : R(read);
4563     IALU  : R;
4564 %}
4565 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4566     single_instruction; may_have_no_code;
4567     dst   : E(write);
4568     src   : R(read);
4569     IALU  : R;
4570 %}
4571 
4572 // Two integer ALU reg operations
4573 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4574     instruction_count(2);
4575     dst   : E(write);
4576     src   : R(read);
4577     A0    : R;
4578     A1    : R;
4579 %}
4580 
4581 // Two integer ALU reg operations
4582 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4583     instruction_count(2); may_have_no_code;
4584     dst   : E(write);
4585     src   : R(read);
4586     A0    : R;
4587     A1    : R;
4588 %}
4589 
4590 // Integer ALU imm operation
4591 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4592     single_instruction;
4593     dst   : E(write);
4594     IALU  : R;
4595 %}
4596 
4597 // Integer ALU reg-reg with carry operation
4598 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4599     single_instruction;
4600     dst   : E(write);
4601     src1  : R(read);
4602     src2  : R(read);
4603     IALU  : R;
4604 %}
4605 
4606 // Integer ALU cc operation
4607 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4608     single_instruction;
4609     dst   : E(write);
4610     cc    : R(read);
4611     IALU  : R;
4612 %}
4613 
4614 // Integer ALU cc / second IALU operation
4615 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4616     instruction_count(1); multiple_bundles;
4617     dst   : E(write)+1;
4618     src   : R(read);
4619     IALU  : R;
4620 %}
4621 
4622 // Integer ALU cc / second IALU operation
4623 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4624     instruction_count(1); multiple_bundles;
4625     dst   : E(write)+1;
4626     p     : R(read);
4627     q     : R(read);
4628     IALU  : R;
4629 %}
4630 
4631 // Integer ALU hi-lo-reg operation
4632 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4633     instruction_count(1); multiple_bundles;
4634     dst   : E(write)+1;
4635     IALU  : R(2);
4636 %}
4637 
4638 // Float ALU hi-lo-reg operation (with temp)
4639 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4640     instruction_count(1); multiple_bundles;
4641     dst   : E(write)+1;
4642     IALU  : R(2);
4643 %}
4644 
4645 // Long Constant
4646 pipe_class loadConL( iRegL dst, immL src ) %{
4647     instruction_count(2); multiple_bundles;
4648     dst   : E(write)+1;
4649     IALU  : R(2);
4650     IALU  : R(2);
4651 %}
4652 
4653 // Pointer Constant
4654 pipe_class loadConP( iRegP dst, immP src ) %{
4655     instruction_count(0); multiple_bundles;
4656     fixed_latency(6);
4657 %}
4658 
4659 // Polling Address
4660 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4661 #ifdef _LP64
4662     instruction_count(0); multiple_bundles;
4663     fixed_latency(6);
4664 #else
4665     dst   : E(write);
4666     IALU  : R;
4667 #endif
4668 %}
4669 
4670 // Long Constant small
4671 pipe_class loadConLlo( iRegL dst, immL src ) %{
4672     instruction_count(2);
4673     dst   : E(write);
4674     IALU  : R;
4675     IALU  : R;
4676 %}
4677 
4678 // [PHH] This is wrong for 64-bit.  See LdImmF/D.
4679 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4680     instruction_count(1); multiple_bundles;
4681     src   : R(read);
4682     dst   : M(write)+1;
4683     IALU  : R;
4684     MS    : E;
4685 %}
4686 
4687 // Integer ALU nop operation
4688 pipe_class ialu_nop() %{
4689     single_instruction;
4690     IALU  : R;
4691 %}
4692 
4693 // Integer ALU nop operation
4694 pipe_class ialu_nop_A0() %{
4695     single_instruction;
4696     A0    : R;
4697 %}
4698 
4699 // Integer ALU nop operation
4700 pipe_class ialu_nop_A1() %{
4701     single_instruction;
4702     A1    : R;
4703 %}
4704 
4705 // Integer Multiply reg-reg operation
4706 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4707     single_instruction;
4708     dst   : E(write);
4709     src1  : R(read);
4710     src2  : R(read);
4711     MS    : R(5);
4712 %}
4713 
4714 // Integer Multiply reg-imm operation
4715 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4716     single_instruction;
4717     dst   : E(write);
4718     src1  : R(read);
4719     MS    : R(5);
4720 %}
4721 
4722 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4723     single_instruction;
4724     dst   : E(write)+4;
4725     src1  : R(read);
4726     src2  : R(read);
4727     MS    : R(6);
4728 %}
4729 
4730 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4731     single_instruction;
4732     dst   : E(write)+4;
4733     src1  : R(read);
4734     MS    : R(6);
4735 %}
4736 
4737 // Integer Divide reg-reg
4738 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4739     instruction_count(1); multiple_bundles;
4740     dst   : E(write);
4741     temp  : E(write);
4742     src1  : R(read);
4743     src2  : R(read);
4744     temp  : R(read);
4745     MS    : R(38);
4746 %}
4747 
4748 // Integer Divide reg-imm
4749 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4750     instruction_count(1); multiple_bundles;
4751     dst   : E(write);
4752     temp  : E(write);
4753     src1  : R(read);
4754     temp  : R(read);
4755     MS    : R(38);
4756 %}
4757 
4758 // Long Divide
4759 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4760     dst  : E(write)+71;
4761     src1 : R(read);
4762     src2 : R(read)+1;
4763     MS   : R(70);
4764 %}
4765 
4766 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4767     dst  : E(write)+71;
4768     src1 : R(read);
4769     MS   : R(70);
4770 %}
4771 
4772 // Floating Point Add Float
4773 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4774     single_instruction;
4775     dst   : X(write);
4776     src1  : E(read);
4777     src2  : E(read);
4778     FA    : R;
4779 %}
4780 
4781 // Floating Point Add Double
4782 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4783     single_instruction;
4784     dst   : X(write);
4785     src1  : E(read);
4786     src2  : E(read);
4787     FA    : R;
4788 %}
4789 
4790 // Floating Point Conditional Move based on integer flags
4791 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4792     single_instruction;
4793     dst   : X(write);
4794     src   : E(read);
4795     cr    : R(read);
4796     FA    : R(2);
4797     BR    : R(2);
4798 %}
4799 
4800 // Floating Point Conditional Move based on integer flags
4801 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4802     single_instruction;
4803     dst   : X(write);
4804     src   : E(read);
4805     cr    : R(read);
4806     FA    : R(2);
4807     BR    : R(2);
4808 %}
4809 
4810 // Floating Point Multiply Float
4811 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4812     single_instruction;
4813     dst   : X(write);
4814     src1  : E(read);
4815     src2  : E(read);
4816     FM    : R;
4817 %}
4818 
4819 // Floating Point Multiply Double
4820 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4821     single_instruction;
4822     dst   : X(write);
4823     src1  : E(read);
4824     src2  : E(read);
4825     FM    : R;
4826 %}
4827 
4828 // Floating Point Divide Float
4829 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4830     single_instruction;
4831     dst   : X(write);
4832     src1  : E(read);
4833     src2  : E(read);
4834     FM    : R;
4835     FDIV  : C(14);
4836 %}
4837 
4838 // Floating Point Divide Double
4839 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4840     single_instruction;
4841     dst   : X(write);
4842     src1  : E(read);
4843     src2  : E(read);
4844     FM    : R;
4845     FDIV  : C(17);
4846 %}
4847 
4848 // Floating Point Move/Negate/Abs Float
4849 pipe_class faddF_reg(regF dst, regF src) %{
4850     single_instruction;
4851     dst   : W(write);
4852     src   : E(read);
4853     FA    : R(1);
4854 %}
4855 
4856 // Floating Point Move/Negate/Abs Double
4857 pipe_class faddD_reg(regD dst, regD src) %{
4858     single_instruction;
4859     dst   : W(write);
4860     src   : E(read);
4861     FA    : R;
4862 %}
4863 
4864 // Floating Point Convert F->D
4865 pipe_class fcvtF2D(regD dst, regF src) %{
4866     single_instruction;
4867     dst   : X(write);
4868     src   : E(read);
4869     FA    : R;
4870 %}
4871 
4872 // Floating Point Convert I->D
4873 pipe_class fcvtI2D(regD dst, regF src) %{
4874     single_instruction;
4875     dst   : X(write);
4876     src   : E(read);
4877     FA    : R;
4878 %}
4879 
4880 // Floating Point Convert LHi->D
4881 pipe_class fcvtLHi2D(regD dst, regD src) %{
4882     single_instruction;
4883     dst   : X(write);
4884     src   : E(read);
4885     FA    : R;
4886 %}
4887 
4888 // Floating Point Convert L->D
4889 pipe_class fcvtL2D(regD dst, regF src) %{
4890     single_instruction;
4891     dst   : X(write);
4892     src   : E(read);
4893     FA    : R;
4894 %}
4895 
4896 // Floating Point Convert L->F
4897 pipe_class fcvtL2F(regD dst, regF src) %{
4898     single_instruction;
4899     dst   : X(write);
4900     src   : E(read);
4901     FA    : R;
4902 %}
4903 
4904 // Floating Point Convert D->F
4905 pipe_class fcvtD2F(regD dst, regF src) %{
4906     single_instruction;
4907     dst   : X(write);
4908     src   : E(read);
4909     FA    : R;
4910 %}
4911 
4912 // Floating Point Convert I->L
4913 pipe_class fcvtI2L(regD dst, regF src) %{
4914     single_instruction;
4915     dst   : X(write);
4916     src   : E(read);
4917     FA    : R;
4918 %}
4919 
4920 // Floating Point Convert D->F
4921 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4922     instruction_count(1); multiple_bundles;
4923     dst   : X(write)+6;
4924     src   : E(read);
4925     FA    : R;
4926 %}
4927 
4928 // Floating Point Convert D->L
4929 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4930     instruction_count(1); multiple_bundles;
4931     dst   : X(write)+6;
4932     src   : E(read);
4933     FA    : R;
4934 %}
4935 
4936 // Floating Point Convert F->I
4937 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4938     instruction_count(1); multiple_bundles;
4939     dst   : X(write)+6;
4940     src   : E(read);
4941     FA    : R;
4942 %}
4943 
4944 // Floating Point Convert F->L
4945 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4946     instruction_count(1); multiple_bundles;
4947     dst   : X(write)+6;
4948     src   : E(read);
4949     FA    : R;
4950 %}
4951 
4952 // Floating Point Convert I->F
4953 pipe_class fcvtI2F(regF dst, regF src) %{
4954     single_instruction;
4955     dst   : X(write);
4956     src   : E(read);
4957     FA    : R;
4958 %}
4959 
4960 // Floating Point Compare
4961 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4962     single_instruction;
4963     cr    : X(write);
4964     src1  : E(read);
4965     src2  : E(read);
4966     FA    : R;
4967 %}
4968 
4969 // Floating Point Compare
4970 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4971     single_instruction;
4972     cr    : X(write);
4973     src1  : E(read);
4974     src2  : E(read);
4975     FA    : R;
4976 %}
4977 
4978 // Floating Add Nop
4979 pipe_class fadd_nop() %{
4980     single_instruction;
4981     FA  : R;
4982 %}
4983 
4984 // Integer Store to Memory
4985 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4986     single_instruction;
4987     mem   : R(read);
4988     src   : C(read);
4989     MS    : R;
4990 %}
4991 
4992 // Integer Store to Memory
4993 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4994     single_instruction;
4995     mem   : R(read);
4996     src   : C(read);
4997     MS    : R;
4998 %}
4999 
5000 // Integer Store Zero to Memory
5001 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5002     single_instruction;
5003     mem   : R(read);
5004     MS    : R;
5005 %}
5006 
5007 // Special Stack Slot Store
5008 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5009     single_instruction;
5010     stkSlot : R(read);
5011     src     : C(read);
5012     MS      : R;
5013 %}
5014 
5015 // Special Stack Slot Store
5016 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5017     instruction_count(2); multiple_bundles;
5018     stkSlot : R(read);
5019     src     : C(read);
5020     MS      : R(2);
5021 %}
5022 
5023 // Float Store
5024 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5025     single_instruction;
5026     mem : R(read);
5027     src : C(read);
5028     MS  : R;
5029 %}
5030 
5031 // Float Store
5032 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5033     single_instruction;
5034     mem : R(read);
5035     MS  : R;
5036 %}
5037 
5038 // Double Store
5039 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5040     instruction_count(1);
5041     mem : R(read);
5042     src : C(read);
5043     MS  : R;
5044 %}
5045 
5046 // Double Store
5047 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5048     single_instruction;
5049     mem : R(read);
5050     MS  : R;
5051 %}
5052 
5053 // Special Stack Slot Float Store
5054 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5055     single_instruction;
5056     stkSlot : R(read);
5057     src     : C(read);
5058     MS      : R;
5059 %}
5060 
5061 // Special Stack Slot Double Store
5062 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5063     single_instruction;
5064     stkSlot : R(read);
5065     src     : C(read);
5066     MS      : R;
5067 %}
5068 
5069 // Integer Load (when sign bit propagation not needed)
5070 pipe_class iload_mem(iRegI dst, memory mem) %{
5071     single_instruction;
5072     mem : R(read);
5073     dst : C(write);
5074     MS  : R;
5075 %}
5076 
5077 // Integer Load from stack operand
5078 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5079     single_instruction;
5080     mem : R(read);
5081     dst : C(write);
5082     MS  : R;
5083 %}
5084 
5085 // Integer Load (when sign bit propagation or masking is needed)
5086 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5087     single_instruction;
5088     mem : R(read);
5089     dst : M(write);
5090     MS  : R;
5091 %}
5092 
5093 // Float Load
5094 pipe_class floadF_mem(regF dst, memory mem) %{
5095     single_instruction;
5096     mem : R(read);
5097     dst : M(write);
5098     MS  : R;
5099 %}
5100 
5101 // Float Load
5102 pipe_class floadD_mem(regD dst, memory mem) %{
5103     instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5104     mem : R(read);
5105     dst : M(write);
5106     MS  : R;
5107 %}
5108 
5109 // Float Load
5110 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5111     single_instruction;
5112     stkSlot : R(read);
5113     dst : M(write);
5114     MS  : R;
5115 %}
5116 
5117 // Float Load
5118 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5119     single_instruction;
5120     stkSlot : R(read);
5121     dst : M(write);
5122     MS  : R;
5123 %}
5124 
5125 // Memory Nop
5126 pipe_class mem_nop() %{
5127     single_instruction;
5128     MS  : R;
5129 %}
5130 
5131 pipe_class sethi(iRegP dst, immI src) %{
5132     single_instruction;
5133     dst  : E(write);
5134     IALU : R;
5135 %}
5136 
5137 pipe_class loadPollP(iRegP poll) %{
5138     single_instruction;
5139     poll : R(read);
5140     MS   : R;
5141 %}
5142 
5143 pipe_class br(Universe br, label labl) %{
5144     single_instruction_with_delay_slot;
5145     BR  : R;
5146 %}
5147 
5148 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5149     single_instruction_with_delay_slot;
5150     cr    : E(read);
5151     BR    : R;
5152 %}
5153 
5154 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5155     single_instruction_with_delay_slot;
5156     op1 : E(read);
5157     BR  : R;
5158     MS  : R;
5159 %}
5160 
5161 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5162     single_instruction_with_delay_slot;
5163     cr    : E(read);
5164     BR    : R;
5165 %}
5166 
5167 pipe_class br_nop() %{
5168     single_instruction;
5169     BR  : R;
5170 %}
5171 
5172 pipe_class simple_call(method meth) %{
5173     instruction_count(2); multiple_bundles; force_serialization;
5174     fixed_latency(100);
5175     BR  : R(1);
5176     MS  : R(1);
5177     A0  : R(1);
5178 %}
5179 
5180 pipe_class compiled_call(method meth) %{
5181     instruction_count(1); multiple_bundles; force_serialization;
5182     fixed_latency(100);
5183     MS  : R(1);
5184 %}
5185 
5186 pipe_class call(method meth) %{
5187     instruction_count(0); multiple_bundles; force_serialization;
5188     fixed_latency(100);
5189 %}
5190 
5191 pipe_class tail_call(Universe ignore, label labl) %{
5192     single_instruction; has_delay_slot;
5193     fixed_latency(100);
5194     BR  : R(1);
5195     MS  : R(1);
5196 %}
5197 
5198 pipe_class ret(Universe ignore) %{
5199     single_instruction; has_delay_slot;
5200     BR  : R(1);
5201     MS  : R(1);
5202 %}
5203 
5204 pipe_class ret_poll(g3RegP poll) %{
5205     instruction_count(3); has_delay_slot;
5206     poll : E(read);
5207     MS   : R;
5208 %}
5209 
5210 // The real do-nothing guy
5211 pipe_class empty( ) %{
5212     instruction_count(0);
5213 %}
5214 
5215 pipe_class long_memory_op() %{
5216     instruction_count(0); multiple_bundles; force_serialization;
5217     fixed_latency(25);
5218     MS  : R(1);
5219 %}
5220 
5221 // Check-cast
5222 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5223     array : R(read);
5224     match  : R(read);
5225     IALU   : R(2);
5226     BR     : R(2);
5227     MS     : R;
5228 %}
5229 
5230 // Convert FPU flags into +1,0,-1
5231 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5232     src1  : E(read);
5233     src2  : E(read);
5234     dst   : E(write);
5235     FA    : R;
5236     MS    : R(2);
5237     BR    : R(2);
5238 %}
5239 
5240 // Compare for p < q, and conditionally add y
5241 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5242     p     : E(read);
5243     q     : E(read);
5244     y     : E(read);
5245     IALU  : R(3)
5246 %}
5247 
5248 // Perform a compare, then move conditionally in a branch delay slot.
5249 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5250     src2   : E(read);
5251     srcdst : E(read);
5252     IALU   : R;
5253     BR     : R;
5254 %}
5255 
5256 // Define the class for the Nop node
5257 define %{
5258    MachNop = ialu_nop;
5259 %}
5260 
5261 %}
5262 
5263 //----------INSTRUCTIONS-------------------------------------------------------
5264 
5265 //------------Special Stack Slot instructions - no match rules-----------------
5266 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5267   // No match rule to avoid chain rule match.
5268   effect(DEF dst, USE src);
5269   ins_cost(MEMORY_REF_COST);
5270   size(4);
5271   format %{ "LDF    $src,$dst\t! stkI to regF" %}
5272   opcode(Assembler::ldf_op3);
5273   ins_encode(simple_form3_mem_reg(src, dst));
5274   ins_pipe(floadF_stk);
5275 %}
5276 
5277 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5278   // No match rule to avoid chain rule match.
5279   effect(DEF dst, USE src);
5280   ins_cost(MEMORY_REF_COST);
5281   size(4);
5282   format %{ "LDDF   $src,$dst\t! stkL to regD" %}
5283   opcode(Assembler::lddf_op3);
5284   ins_encode(simple_form3_mem_reg(src, dst));
5285   ins_pipe(floadD_stk);
5286 %}
5287 
5288 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5289   // No match rule to avoid chain rule match.
5290   effect(DEF dst, USE src);
5291   ins_cost(MEMORY_REF_COST);
5292   size(4);
5293   format %{ "STF    $src,$dst\t! regF to stkI" %}
5294   opcode(Assembler::stf_op3);
5295   ins_encode(simple_form3_mem_reg(dst, src));
5296   ins_pipe(fstoreF_stk_reg);
5297 %}
5298 
5299 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5300   // No match rule to avoid chain rule match.
5301   effect(DEF dst, USE src);
5302   ins_cost(MEMORY_REF_COST);
5303   size(4);
5304   format %{ "STDF   $src,$dst\t! regD to stkL" %}
5305   opcode(Assembler::stdf_op3);
5306   ins_encode(simple_form3_mem_reg(dst, src));
5307   ins_pipe(fstoreD_stk_reg);
5308 %}
5309 
5310 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5311   effect(DEF dst, USE src);
5312   ins_cost(MEMORY_REF_COST*2);
5313   size(8);
5314   format %{ "STW    $src,$dst.hi\t! long\n\t"
5315             "STW    R_G0,$dst.lo" %}
5316   opcode(Assembler::stw_op3);
5317   ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5318   ins_pipe(lstoreI_stk_reg);
5319 %}
5320 
5321 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5322   // No match rule to avoid chain rule match.
5323   effect(DEF dst, USE src);
5324   ins_cost(MEMORY_REF_COST);
5325   size(4);
5326   format %{ "STX    $src,$dst\t! regL to stkD" %}
5327   opcode(Assembler::stx_op3);
5328   ins_encode(simple_form3_mem_reg( dst, src ) );
5329   ins_pipe(istore_stk_reg);
5330 %}
5331 
5332 //---------- Chain stack slots between similar types --------
5333 
5334 // Load integer from stack slot
5335 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5336   match(Set dst src);
5337   ins_cost(MEMORY_REF_COST);
5338 
5339   size(4);
5340   format %{ "LDUW   $src,$dst\t!stk" %}
5341   opcode(Assembler::lduw_op3);
5342   ins_encode(simple_form3_mem_reg( src, dst ) );
5343   ins_pipe(iload_mem);
5344 %}
5345 
5346 // Store integer to stack slot
5347 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5348   match(Set dst src);
5349   ins_cost(MEMORY_REF_COST);
5350 
5351   size(4);
5352   format %{ "STW    $src,$dst\t!stk" %}
5353   opcode(Assembler::stw_op3);
5354   ins_encode(simple_form3_mem_reg( dst, src ) );
5355   ins_pipe(istore_mem_reg);
5356 %}
5357 
5358 // Load long from stack slot
5359 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5360   match(Set dst src);
5361 
5362   ins_cost(MEMORY_REF_COST);
5363   size(4);
5364   format %{ "LDX    $src,$dst\t! long" %}
5365   opcode(Assembler::ldx_op3);
5366   ins_encode(simple_form3_mem_reg( src, dst ) );
5367   ins_pipe(iload_mem);
5368 %}
5369 
5370 // Store long to stack slot
5371 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5372   match(Set dst src);
5373 
5374   ins_cost(MEMORY_REF_COST);
5375   size(4);
5376   format %{ "STX    $src,$dst\t! long" %}
5377   opcode(Assembler::stx_op3);
5378   ins_encode(simple_form3_mem_reg( dst, src ) );
5379   ins_pipe(istore_mem_reg);
5380 %}
5381 
5382 #ifdef _LP64
5383 // Load pointer from stack slot, 64-bit encoding
5384 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5385   match(Set dst src);
5386   ins_cost(MEMORY_REF_COST);
5387   size(4);
5388   format %{ "LDX    $src,$dst\t!ptr" %}
5389   opcode(Assembler::ldx_op3);
5390   ins_encode(simple_form3_mem_reg( src, dst ) );
5391   ins_pipe(iload_mem);
5392 %}
5393 
5394 // Store pointer to stack slot
5395 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5396   match(Set dst src);
5397   ins_cost(MEMORY_REF_COST);
5398   size(4);
5399   format %{ "STX    $src,$dst\t!ptr" %}
5400   opcode(Assembler::stx_op3);
5401   ins_encode(simple_form3_mem_reg( dst, src ) );
5402   ins_pipe(istore_mem_reg);
5403 %}
5404 #else // _LP64
5405 // Load pointer from stack slot, 32-bit encoding
5406 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5407   match(Set dst src);
5408   ins_cost(MEMORY_REF_COST);
5409   format %{ "LDUW   $src,$dst\t!ptr" %}
5410   opcode(Assembler::lduw_op3, Assembler::ldst_op);
5411   ins_encode(simple_form3_mem_reg( src, dst ) );
5412   ins_pipe(iload_mem);
5413 %}
5414 
5415 // Store pointer to stack slot
5416 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5417   match(Set dst src);
5418   ins_cost(MEMORY_REF_COST);
5419   format %{ "STW    $src,$dst\t!ptr" %}
5420   opcode(Assembler::stw_op3, Assembler::ldst_op);
5421   ins_encode(simple_form3_mem_reg( dst, src ) );
5422   ins_pipe(istore_mem_reg);
5423 %}
5424 #endif // _LP64
5425 
5426 //------------Special Nop instructions for bundling - no match rules-----------
5427 // Nop using the A0 functional unit
5428 instruct Nop_A0() %{
5429   ins_cost(0);
5430 
5431   format %{ "NOP    ! Alu Pipeline" %}
5432   opcode(Assembler::or_op3, Assembler::arith_op);
5433   ins_encode( form2_nop() );
5434   ins_pipe(ialu_nop_A0);
5435 %}
5436 
5437 // Nop using the A1 functional unit
5438 instruct Nop_A1( ) %{
5439   ins_cost(0);
5440 
5441   format %{ "NOP    ! Alu Pipeline" %}
5442   opcode(Assembler::or_op3, Assembler::arith_op);
5443   ins_encode( form2_nop() );
5444   ins_pipe(ialu_nop_A1);
5445 %}
5446 
5447 // Nop using the memory functional unit
5448 instruct Nop_MS( ) %{
5449   ins_cost(0);
5450 
5451   format %{ "NOP    ! Memory Pipeline" %}
5452   ins_encode( emit_mem_nop );
5453   ins_pipe(mem_nop);
5454 %}
5455 
5456 // Nop using the floating add functional unit
5457 instruct Nop_FA( ) %{
5458   ins_cost(0);
5459 
5460   format %{ "NOP    ! Floating Add Pipeline" %}
5461   ins_encode( emit_fadd_nop );
5462   ins_pipe(fadd_nop);
5463 %}
5464 
5465 // Nop using the branch functional unit
5466 instruct Nop_BR( ) %{
5467   ins_cost(0);
5468 
5469   format %{ "NOP    ! Branch Pipeline" %}
5470   ins_encode( emit_br_nop );
5471   ins_pipe(br_nop);
5472 %}
5473 
5474 //----------Load/Store/Move Instructions---------------------------------------
5475 //----------Load Instructions--------------------------------------------------
5476 // Load Byte (8bit signed)
5477 instruct loadB(iRegI dst, memory mem) %{
5478   match(Set dst (LoadB mem));
5479   ins_cost(MEMORY_REF_COST);
5480 
5481   size(4);
5482   format %{ "LDSB   $mem,$dst\t! byte" %}
5483   ins_encode %{
5484     __ ldsb($mem$$Address, $dst$$Register);
5485   %}
5486   ins_pipe(iload_mask_mem);
5487 %}
5488 
5489 // Load Byte (8bit signed) into a Long Register
5490 instruct loadB2L(iRegL dst, memory mem) %{
5491   match(Set dst (ConvI2L (LoadB mem)));
5492   ins_cost(MEMORY_REF_COST);
5493 
5494   size(4);
5495   format %{ "LDSB   $mem,$dst\t! byte -> long" %}
5496   ins_encode %{
5497     __ ldsb($mem$$Address, $dst$$Register);
5498   %}
5499   ins_pipe(iload_mask_mem);
5500 %}
5501 
5502 // Load Unsigned Byte (8bit UNsigned) into an int reg
5503 instruct loadUB(iRegI dst, memory mem) %{
5504   match(Set dst (LoadUB mem));
5505   ins_cost(MEMORY_REF_COST);
5506 
5507   size(4);
5508   format %{ "LDUB   $mem,$dst\t! ubyte" %}
5509   ins_encode %{
5510     __ ldub($mem$$Address, $dst$$Register);
5511   %}
5512   ins_pipe(iload_mem);
5513 %}
5514 
5515 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5516 instruct loadUB2L(iRegL dst, memory mem) %{
5517   match(Set dst (ConvI2L (LoadUB mem)));
5518   ins_cost(MEMORY_REF_COST);
5519 
5520   size(4);
5521   format %{ "LDUB   $mem,$dst\t! ubyte -> long" %}
5522   ins_encode %{
5523     __ ldub($mem$$Address, $dst$$Register);
5524   %}
5525   ins_pipe(iload_mem);
5526 %}
5527 
5528 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5529 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5530   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5531   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5532 
5533   size(2*4);
5534   format %{ "LDUB   $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5535             "AND    $dst,$mask,$dst" %}
5536   ins_encode %{
5537     __ ldub($mem$$Address, $dst$$Register);
5538     __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5539   %}
5540   ins_pipe(iload_mem);
5541 %}
5542 
5543 // Load Short (16bit signed)
5544 instruct loadS(iRegI dst, memory mem) %{
5545   match(Set dst (LoadS mem));
5546   ins_cost(MEMORY_REF_COST);
5547 
5548   size(4);
5549   format %{ "LDSH   $mem,$dst\t! short" %}
5550   ins_encode %{
5551     __ ldsh($mem$$Address, $dst$$Register);
5552   %}
5553   ins_pipe(iload_mask_mem);
5554 %}
5555 
5556 // Load Short (16 bit signed) to Byte (8 bit signed)
5557 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5558   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5559   ins_cost(MEMORY_REF_COST);
5560 
5561   size(4);
5562 
5563   format %{ "LDSB   $mem+1,$dst\t! short -> byte" %}
5564   ins_encode %{
5565     __ ldsb($mem$$Address, $dst$$Register, 1);
5566   %}
5567   ins_pipe(iload_mask_mem);
5568 %}
5569 
5570 // Load Short (16bit signed) into a Long Register
5571 instruct loadS2L(iRegL dst, memory mem) %{
5572   match(Set dst (ConvI2L (LoadS mem)));
5573   ins_cost(MEMORY_REF_COST);
5574 
5575   size(4);
5576   format %{ "LDSH   $mem,$dst\t! short -> long" %}
5577   ins_encode %{
5578     __ ldsh($mem$$Address, $dst$$Register);
5579   %}
5580   ins_pipe(iload_mask_mem);
5581 %}
5582 
5583 // Load Unsigned Short/Char (16bit UNsigned)
5584 instruct loadUS(iRegI dst, memory mem) %{
5585   match(Set dst (LoadUS mem));
5586   ins_cost(MEMORY_REF_COST);
5587 
5588   size(4);
5589   format %{ "LDUH   $mem,$dst\t! ushort/char" %}
5590   ins_encode %{
5591     __ lduh($mem$$Address, $dst$$Register);
5592   %}
5593   ins_pipe(iload_mem);
5594 %}
5595 
5596 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5597 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5598   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5599   ins_cost(MEMORY_REF_COST);
5600 
5601   size(4);
5602   format %{ "LDSB   $mem+1,$dst\t! ushort -> byte" %}
5603   ins_encode %{
5604     __ ldsb($mem$$Address, $dst$$Register, 1);
5605   %}
5606   ins_pipe(iload_mask_mem);
5607 %}
5608 
5609 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5610 instruct loadUS2L(iRegL dst, memory mem) %{
5611   match(Set dst (ConvI2L (LoadUS mem)));
5612   ins_cost(MEMORY_REF_COST);
5613 
5614   size(4);
5615   format %{ "LDUH   $mem,$dst\t! ushort/char -> long" %}
5616   ins_encode %{
5617     __ lduh($mem$$Address, $dst$$Register);
5618   %}
5619   ins_pipe(iload_mem);
5620 %}
5621 
5622 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5623 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5624   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5625   ins_cost(MEMORY_REF_COST);
5626 
5627   size(4);
5628   format %{ "LDUB   $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5629   ins_encode %{
5630     __ ldub($mem$$Address, $dst$$Register, 1);  // LSB is index+1 on BE
5631   %}
5632   ins_pipe(iload_mem);
5633 %}
5634 
5635 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5636 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5637   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5638   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5639 
5640   size(2*4);
5641   format %{ "LDUH   $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5642             "AND    $dst,$mask,$dst" %}
5643   ins_encode %{
5644     Register Rdst = $dst$$Register;
5645     __ lduh($mem$$Address, Rdst);
5646     __ and3(Rdst, $mask$$constant, Rdst);
5647   %}
5648   ins_pipe(iload_mem);
5649 %}
5650 
5651 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5652 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5653   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5654   effect(TEMP dst, TEMP tmp);
5655   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5656 
5657   size((3+1)*4);  // set may use two instructions.
5658   format %{ "LDUH   $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5659             "SET    $mask,$tmp\n\t"
5660             "AND    $dst,$tmp,$dst" %}
5661   ins_encode %{
5662     Register Rdst = $dst$$Register;
5663     Register Rtmp = $tmp$$Register;
5664     __ lduh($mem$$Address, Rdst);
5665     __ set($mask$$constant, Rtmp);
5666     __ and3(Rdst, Rtmp, Rdst);
5667   %}
5668   ins_pipe(iload_mem);
5669 %}
5670 
5671 // Load Integer
5672 instruct loadI(iRegI dst, memory mem) %{
5673   match(Set dst (LoadI mem));
5674   ins_cost(MEMORY_REF_COST);
5675 
5676   size(4);
5677   format %{ "LDUW   $mem,$dst\t! int" %}
5678   ins_encode %{
5679     __ lduw($mem$$Address, $dst$$Register);
5680   %}
5681   ins_pipe(iload_mem);
5682 %}
5683 
5684 // Load Integer to Byte (8 bit signed)
5685 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5686   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5687   ins_cost(MEMORY_REF_COST);
5688 
5689   size(4);
5690 
5691   format %{ "LDSB   $mem+3,$dst\t! int -> byte" %}
5692   ins_encode %{
5693     __ ldsb($mem$$Address, $dst$$Register, 3);
5694   %}
5695   ins_pipe(iload_mask_mem);
5696 %}
5697 
5698 // Load Integer to Unsigned Byte (8 bit UNsigned)
5699 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5700   match(Set dst (AndI (LoadI mem) mask));
5701   ins_cost(MEMORY_REF_COST);
5702 
5703   size(4);
5704 
5705   format %{ "LDUB   $mem+3,$dst\t! int -> ubyte" %}
5706   ins_encode %{
5707     __ ldub($mem$$Address, $dst$$Register, 3);
5708   %}
5709   ins_pipe(iload_mask_mem);
5710 %}
5711 
5712 // Load Integer to Short (16 bit signed)
5713 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5714   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5715   ins_cost(MEMORY_REF_COST);
5716 
5717   size(4);
5718 
5719   format %{ "LDSH   $mem+2,$dst\t! int -> short" %}
5720   ins_encode %{
5721     __ ldsh($mem$$Address, $dst$$Register, 2);
5722   %}
5723   ins_pipe(iload_mask_mem);
5724 %}
5725 
5726 // Load Integer to Unsigned Short (16 bit UNsigned)
5727 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5728   match(Set dst (AndI (LoadI mem) mask));
5729   ins_cost(MEMORY_REF_COST);
5730 
5731   size(4);
5732 
5733   format %{ "LDUH   $mem+2,$dst\t! int -> ushort/char" %}
5734   ins_encode %{
5735     __ lduh($mem$$Address, $dst$$Register, 2);
5736   %}
5737   ins_pipe(iload_mask_mem);
5738 %}
5739 
5740 // Load Integer into a Long Register
5741 instruct loadI2L(iRegL dst, memory mem) %{
5742   match(Set dst (ConvI2L (LoadI mem)));
5743   ins_cost(MEMORY_REF_COST);
5744 
5745   size(4);
5746   format %{ "LDSW   $mem,$dst\t! int -> long" %}
5747   ins_encode %{
5748     __ ldsw($mem$$Address, $dst$$Register);
5749   %}
5750   ins_pipe(iload_mask_mem);
5751 %}
5752 
5753 // Load Integer with mask 0xFF into a Long Register
5754 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5755   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5756   ins_cost(MEMORY_REF_COST);
5757 
5758   size(4);
5759   format %{ "LDUB   $mem+3,$dst\t! int & 0xFF -> long" %}
5760   ins_encode %{
5761     __ ldub($mem$$Address, $dst$$Register, 3);  // LSB is index+3 on BE
5762   %}
5763   ins_pipe(iload_mem);
5764 %}
5765 
5766 // Load Integer with mask 0xFFFF into a Long Register
5767 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5768   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5769   ins_cost(MEMORY_REF_COST);
5770 
5771   size(4);
5772   format %{ "LDUH   $mem+2,$dst\t! int & 0xFFFF -> long" %}
5773   ins_encode %{
5774     __ lduh($mem$$Address, $dst$$Register, 2);  // LSW is index+2 on BE
5775   %}
5776   ins_pipe(iload_mem);
5777 %}
5778 
5779 // Load Integer with a 13-bit mask into a Long Register
5780 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5781   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5782   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5783 
5784   size(2*4);
5785   format %{ "LDUW   $mem,$dst\t! int & 13-bit mask -> long\n\t"
5786             "AND    $dst,$mask,$dst" %}
5787   ins_encode %{
5788     Register Rdst = $dst$$Register;
5789     __ lduw($mem$$Address, Rdst);
5790     __ and3(Rdst, $mask$$constant, Rdst);
5791   %}
5792   ins_pipe(iload_mem);
5793 %}
5794 
5795 // Load Integer with a 32-bit mask into a Long Register
5796 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5797   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5798   effect(TEMP dst, TEMP tmp);
5799   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5800 
5801   size((3+1)*4);  // set may use two instructions.
5802   format %{ "LDUW   $mem,$dst\t! int & 32-bit mask -> long\n\t"
5803             "SET    $mask,$tmp\n\t"
5804             "AND    $dst,$tmp,$dst" %}
5805   ins_encode %{
5806     Register Rdst = $dst$$Register;
5807     Register Rtmp = $tmp$$Register;
5808     __ lduw($mem$$Address, Rdst);
5809     __ set($mask$$constant, Rtmp);
5810     __ and3(Rdst, Rtmp, Rdst);
5811   %}
5812   ins_pipe(iload_mem);
5813 %}
5814 
5815 // Load Unsigned Integer into a Long Register
5816 instruct loadUI2L(iRegL dst, memory mem) %{
5817   match(Set dst (LoadUI2L mem));
5818   ins_cost(MEMORY_REF_COST);
5819 
5820   size(4);
5821   format %{ "LDUW   $mem,$dst\t! uint -> long" %}
5822   ins_encode %{
5823     __ lduw($mem$$Address, $dst$$Register);
5824   %}
5825   ins_pipe(iload_mem);
5826 %}
5827 
5828 // Load Long - aligned
5829 instruct loadL(iRegL dst, memory mem ) %{
5830   match(Set dst (LoadL mem));
5831   ins_cost(MEMORY_REF_COST);
5832 
5833   size(4);
5834   format %{ "LDX    $mem,$dst\t! long" %}
5835   ins_encode %{
5836     __ ldx($mem$$Address, $dst$$Register);
5837   %}
5838   ins_pipe(iload_mem);
5839 %}
5840 
5841 // Load Long - UNaligned
5842 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5843   match(Set dst (LoadL_unaligned mem));
5844   effect(KILL tmp);
5845   ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5846   size(16);
5847   format %{ "LDUW   $mem+4,R_O7\t! misaligned long\n"
5848           "\tLDUW   $mem  ,$dst\n"
5849           "\tSLLX   #32, $dst, $dst\n"
5850           "\tOR     $dst, R_O7, $dst" %}
5851   opcode(Assembler::lduw_op3);
5852   ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5853   ins_pipe(iload_mem);
5854 %}
5855 
5856 // Load Aligned Packed Byte into a Double Register
5857 instruct loadA8B(regD dst, memory mem) %{
5858   match(Set dst (Load8B mem));
5859   ins_cost(MEMORY_REF_COST);
5860   size(4);
5861   format %{ "LDDF   $mem,$dst\t! packed8B" %}
5862   opcode(Assembler::lddf_op3);
5863   ins_encode(simple_form3_mem_reg( mem, dst ) );
5864   ins_pipe(floadD_mem);
5865 %}
5866 
5867 // Load Aligned Packed Char into a Double Register
5868 instruct loadA4C(regD dst, memory mem) %{
5869   match(Set dst (Load4C mem));
5870   ins_cost(MEMORY_REF_COST);
5871   size(4);
5872   format %{ "LDDF   $mem,$dst\t! packed4C" %}
5873   opcode(Assembler::lddf_op3);
5874   ins_encode(simple_form3_mem_reg( mem, dst ) );
5875   ins_pipe(floadD_mem);
5876 %}
5877 
5878 // Load Aligned Packed Short into a Double Register
5879 instruct loadA4S(regD dst, memory mem) %{
5880   match(Set dst (Load4S mem));
5881   ins_cost(MEMORY_REF_COST);
5882   size(4);
5883   format %{ "LDDF   $mem,$dst\t! packed4S" %}
5884   opcode(Assembler::lddf_op3);
5885   ins_encode(simple_form3_mem_reg( mem, dst ) );
5886   ins_pipe(floadD_mem);
5887 %}
5888 
5889 // Load Aligned Packed Int into a Double Register
5890 instruct loadA2I(regD dst, memory mem) %{
5891   match(Set dst (Load2I mem));
5892   ins_cost(MEMORY_REF_COST);
5893   size(4);
5894   format %{ "LDDF   $mem,$dst\t! packed2I" %}
5895   opcode(Assembler::lddf_op3);
5896   ins_encode(simple_form3_mem_reg( mem, dst ) );
5897   ins_pipe(floadD_mem);
5898 %}
5899 
5900 // Load Range
5901 instruct loadRange(iRegI dst, memory mem) %{
5902   match(Set dst (LoadRange mem));
5903   ins_cost(MEMORY_REF_COST);
5904 
5905   size(4);
5906   format %{ "LDUW   $mem,$dst\t! range" %}
5907   opcode(Assembler::lduw_op3);
5908   ins_encode(simple_form3_mem_reg( mem, dst ) );
5909   ins_pipe(iload_mem);
5910 %}
5911 
5912 // Load Integer into %f register (for fitos/fitod)
5913 instruct loadI_freg(regF dst, memory mem) %{
5914   match(Set dst (LoadI mem));
5915   ins_cost(MEMORY_REF_COST);
5916   size(4);
5917 
5918   format %{ "LDF    $mem,$dst\t! for fitos/fitod" %}
5919   opcode(Assembler::ldf_op3);
5920   ins_encode(simple_form3_mem_reg( mem, dst ) );
5921   ins_pipe(floadF_mem);
5922 %}
5923 
5924 // Load Pointer
5925 instruct loadP(iRegP dst, memory mem) %{
5926   match(Set dst (LoadP mem));
5927   ins_cost(MEMORY_REF_COST);
5928   size(4);
5929 
5930 #ifndef _LP64
5931   format %{ "LDUW   $mem,$dst\t! ptr" %}
5932   ins_encode %{
5933     __ lduw($mem$$Address, $dst$$Register);
5934   %}
5935 #else
5936   format %{ "LDX    $mem,$dst\t! ptr" %}
5937   ins_encode %{
5938     __ ldx($mem$$Address, $dst$$Register);
5939   %}
5940 #endif
5941   ins_pipe(iload_mem);
5942 %}
5943 
5944 // Load Compressed Pointer
5945 instruct loadN(iRegN dst, memory mem) %{
5946   match(Set dst (LoadN mem));
5947   ins_cost(MEMORY_REF_COST);
5948   size(4);
5949 
5950   format %{ "LDUW   $mem,$dst\t! compressed ptr" %}
5951   ins_encode %{
5952     __ lduw($mem$$Address, $dst$$Register);
5953   %}
5954   ins_pipe(iload_mem);
5955 %}
5956 
5957 // Load Klass Pointer
5958 instruct loadKlass(iRegP dst, memory mem) %{
5959   match(Set dst (LoadKlass mem));
5960   ins_cost(MEMORY_REF_COST);
5961   size(4);
5962 
5963 #ifndef _LP64
5964   format %{ "LDUW   $mem,$dst\t! klass ptr" %}
5965   ins_encode %{
5966     __ lduw($mem$$Address, $dst$$Register);
5967   %}
5968 #else
5969   format %{ "LDX    $mem,$dst\t! klass ptr" %}
5970   ins_encode %{
5971     __ ldx($mem$$Address, $dst$$Register);
5972   %}
5973 #endif
5974   ins_pipe(iload_mem);
5975 %}
5976 
5977 // Load narrow Klass Pointer
5978 instruct loadNKlass(iRegN dst, memory mem) %{
5979   match(Set dst (LoadNKlass mem));
5980   ins_cost(MEMORY_REF_COST);
5981   size(4);
5982 
5983   format %{ "LDUW   $mem,$dst\t! compressed klass ptr" %}
5984   ins_encode %{
5985     __ lduw($mem$$Address, $dst$$Register);
5986   %}
5987   ins_pipe(iload_mem);
5988 %}
5989 
5990 // Load Double
5991 instruct loadD(regD dst, memory mem) %{
5992   match(Set dst (LoadD mem));
5993   ins_cost(MEMORY_REF_COST);
5994 
5995   size(4);
5996   format %{ "LDDF   $mem,$dst" %}
5997   opcode(Assembler::lddf_op3);
5998   ins_encode(simple_form3_mem_reg( mem, dst ) );
5999   ins_pipe(floadD_mem);
6000 %}
6001 
6002 // Load Double - UNaligned
6003 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6004   match(Set dst (LoadD_unaligned mem));
6005   ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6006   size(8);
6007   format %{ "LDF    $mem  ,$dst.hi\t! misaligned double\n"
6008           "\tLDF    $mem+4,$dst.lo\t!" %}
6009   opcode(Assembler::ldf_op3);
6010   ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6011   ins_pipe(iload_mem);
6012 %}
6013 
6014 // Load Float
6015 instruct loadF(regF dst, memory mem) %{
6016   match(Set dst (LoadF mem));
6017   ins_cost(MEMORY_REF_COST);
6018 
6019   size(4);
6020   format %{ "LDF    $mem,$dst" %}
6021   opcode(Assembler::ldf_op3);
6022   ins_encode(simple_form3_mem_reg( mem, dst ) );
6023   ins_pipe(floadF_mem);
6024 %}
6025 
6026 // Load Constant
6027 instruct loadConI( iRegI dst, immI src ) %{
6028   match(Set dst src);
6029   ins_cost(DEFAULT_COST * 3/2);
6030   format %{ "SET    $src,$dst" %}
6031   ins_encode( Set32(src, dst) );
6032   ins_pipe(ialu_hi_lo_reg);
6033 %}
6034 
6035 instruct loadConI13( iRegI dst, immI13 src ) %{
6036   match(Set dst src);
6037 
6038   size(4);
6039   format %{ "MOV    $src,$dst" %}
6040   ins_encode( Set13( src, dst ) );
6041   ins_pipe(ialu_imm);
6042 %}
6043 
6044 #ifndef _LP64
6045 instruct loadConP(iRegP dst, immP con) %{
6046   match(Set dst con);
6047   ins_cost(DEFAULT_COST * 3/2);
6048   format %{ "SET    $con,$dst\t!ptr" %}
6049   ins_encode %{
6050     // [RGV] This next line should be generated from ADLC
6051     if (_opnds[1]->constant_is_oop()) {
6052       intptr_t val = $con$$constant;
6053       __ set_oop_constant((jobject) val, $dst$$Register);
6054     } else {          // non-oop pointers, e.g. card mark base, heap top
6055       __ set($con$$constant, $dst$$Register);
6056     }
6057   %}
6058   ins_pipe(loadConP);
6059 %}
6060 #else
6061 instruct loadConP_set(iRegP dst, immP_set con) %{
6062   match(Set dst con);
6063   ins_cost(DEFAULT_COST * 3/2);
6064   format %{ "SET    $con,$dst\t! ptr" %}
6065   ins_encode %{
6066     // [RGV] This next line should be generated from ADLC
6067     if (_opnds[1]->constant_is_oop()) {
6068       intptr_t val = $con$$constant;
6069       __ set_oop_constant((jobject) val, $dst$$Register);
6070     } else {          // non-oop pointers, e.g. card mark base, heap top
6071       __ set($con$$constant, $dst$$Register);
6072     }
6073   %}
6074   ins_pipe(loadConP);
6075 %}
6076 
6077 instruct loadConP_load(iRegP dst, immP_load con) %{
6078   match(Set dst con);
6079   ins_cost(MEMORY_REF_COST);
6080   format %{ "LD     [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6081   ins_encode %{
6082     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6083     __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6084   %}
6085   ins_pipe(loadConP);
6086 %}
6087 
6088 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6089   match(Set dst con);
6090   ins_cost(DEFAULT_COST * 3/2);
6091   format %{ "SET    $con,$dst\t! non-oop ptr" %}
6092   ins_encode %{
6093     __ set($con$$constant, $dst$$Register);
6094   %}
6095   ins_pipe(loadConP);
6096 %}
6097 #endif // _LP64
6098 
6099 instruct loadConP0(iRegP dst, immP0 src) %{
6100   match(Set dst src);
6101 
6102   size(4);
6103   format %{ "CLR    $dst\t!ptr" %}
6104   ins_encode %{
6105     __ clr($dst$$Register);
6106   %}
6107   ins_pipe(ialu_imm);
6108 %}
6109 
6110 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6111   match(Set dst src);
6112   ins_cost(DEFAULT_COST);
6113   format %{ "SET    $src,$dst\t!ptr" %}
6114   ins_encode %{
6115     AddressLiteral polling_page(os::get_polling_page());
6116     __ sethi(polling_page, reg_to_register_object($dst$$reg));
6117   %}
6118   ins_pipe(loadConP_poll);
6119 %}
6120 
6121 instruct loadConN0(iRegN dst, immN0 src) %{
6122   match(Set dst src);
6123 
6124   size(4);
6125   format %{ "CLR    $dst\t! compressed NULL ptr" %}
6126   ins_encode %{
6127     __ clr($dst$$Register);
6128   %}
6129   ins_pipe(ialu_imm);
6130 %}
6131 
6132 instruct loadConN(iRegN dst, immN src) %{
6133   match(Set dst src);
6134   ins_cost(DEFAULT_COST * 3/2);
6135   format %{ "SET    $src,$dst\t! compressed ptr" %}
6136   ins_encode %{
6137     Register dst = $dst$$Register;
6138     __ set_narrow_oop((jobject)$src$$constant, dst);
6139   %}
6140   ins_pipe(ialu_hi_lo_reg);
6141 %}
6142 
6143 // Materialize long value (predicated by immL_cheap).
6144 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6145   match(Set dst con);
6146   effect(KILL tmp);
6147   ins_cost(DEFAULT_COST * 3);
6148   format %{ "SET64   $con,$dst KILL $tmp\t! cheap long" %}
6149   ins_encode %{
6150     __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6151   %}
6152   ins_pipe(loadConL);
6153 %}
6154 
6155 // Load long value from constant table (predicated by immL_expensive).
6156 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6157   match(Set dst con);
6158   ins_cost(MEMORY_REF_COST);
6159   format %{ "LDX     [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6160   ins_encode %{
6161       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6162     __ ldx($constanttablebase, con_offset, $dst$$Register);
6163   %}
6164   ins_pipe(loadConL);
6165 %}
6166 
6167 instruct loadConL0( iRegL dst, immL0 src ) %{
6168   match(Set dst src);
6169   ins_cost(DEFAULT_COST);
6170   size(4);
6171   format %{ "CLR    $dst\t! long" %}
6172   ins_encode( Set13( src, dst ) );
6173   ins_pipe(ialu_imm);
6174 %}
6175 
6176 instruct loadConL13( iRegL dst, immL13 src ) %{
6177   match(Set dst src);
6178   ins_cost(DEFAULT_COST * 2);
6179 
6180   size(4);
6181   format %{ "MOV    $src,$dst\t! long" %}
6182   ins_encode( Set13( src, dst ) );
6183   ins_pipe(ialu_imm);
6184 %}
6185 
6186 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6187   match(Set dst con);
6188   effect(KILL tmp);
6189   format %{ "LDF    [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6190   ins_encode %{
6191       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6192     __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6193   %}
6194   ins_pipe(loadConFD);
6195 %}
6196 
6197 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6198   match(Set dst con);
6199   effect(KILL tmp);
6200   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6201   ins_encode %{
6202     // XXX This is a quick fix for 6833573.
6203     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6204     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6205     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6206   %}
6207   ins_pipe(loadConFD);
6208 %}
6209 
6210 // Prefetch instructions.
6211 // Must be safe to execute with invalid address (cannot fault).
6212 
6213 instruct prefetchr( memory mem ) %{
6214   match( PrefetchRead mem );
6215   ins_cost(MEMORY_REF_COST);
6216 
6217   format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6218   opcode(Assembler::prefetch_op3);
6219   ins_encode( form3_mem_prefetch_read( mem ) );
6220   ins_pipe(iload_mem);
6221 %}
6222 
6223 instruct prefetchw( memory mem ) %{
6224   predicate(AllocatePrefetchStyle != 3 );
6225   match( PrefetchWrite mem );
6226   ins_cost(MEMORY_REF_COST);
6227 
6228   format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6229   opcode(Assembler::prefetch_op3);
6230   ins_encode( form3_mem_prefetch_write( mem ) );
6231   ins_pipe(iload_mem);
6232 %}
6233 
6234 // Use BIS instruction to prefetch.
6235 instruct prefetchw_bis( memory mem ) %{
6236   predicate(AllocatePrefetchStyle == 3);
6237   match( PrefetchWrite mem );
6238   ins_cost(MEMORY_REF_COST);
6239 
6240   format %{ "STXA   G0,$mem\t! // Block initializing store" %}
6241   ins_encode %{
6242      Register base = as_Register($mem$$base);
6243      int disp = $mem$$disp;
6244      if (disp != 0) {
6245        __ add(base, AllocatePrefetchStepSize, base);
6246      }
6247      __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
6248   %}
6249   ins_pipe(istore_mem_reg);
6250 %}
6251 
6252 //----------Store Instructions-------------------------------------------------
6253 // Store Byte
6254 instruct storeB(memory mem, iRegI src) %{
6255   match(Set mem (StoreB mem src));
6256   ins_cost(MEMORY_REF_COST);
6257 
6258   size(4);
6259   format %{ "STB    $src,$mem\t! byte" %}
6260   opcode(Assembler::stb_op3);
6261   ins_encode(simple_form3_mem_reg( mem, src ) );
6262   ins_pipe(istore_mem_reg);
6263 %}
6264 
6265 instruct storeB0(memory mem, immI0 src) %{
6266   match(Set mem (StoreB mem src));
6267   ins_cost(MEMORY_REF_COST);
6268 
6269   size(4);
6270   format %{ "STB    $src,$mem\t! byte" %}
6271   opcode(Assembler::stb_op3);
6272   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6273   ins_pipe(istore_mem_zero);
6274 %}
6275 
6276 instruct storeCM0(memory mem, immI0 src) %{
6277   match(Set mem (StoreCM mem src));
6278   ins_cost(MEMORY_REF_COST);
6279 
6280   size(4);
6281   format %{ "STB    $src,$mem\t! CMS card-mark byte 0" %}
6282   opcode(Assembler::stb_op3);
6283   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6284   ins_pipe(istore_mem_zero);
6285 %}
6286 
6287 // Store Char/Short
6288 instruct storeC(memory mem, iRegI src) %{
6289   match(Set mem (StoreC mem src));
6290   ins_cost(MEMORY_REF_COST);
6291 
6292   size(4);
6293   format %{ "STH    $src,$mem\t! short" %}
6294   opcode(Assembler::sth_op3);
6295   ins_encode(simple_form3_mem_reg( mem, src ) );
6296   ins_pipe(istore_mem_reg);
6297 %}
6298 
6299 instruct storeC0(memory mem, immI0 src) %{
6300   match(Set mem (StoreC mem src));
6301   ins_cost(MEMORY_REF_COST);
6302 
6303   size(4);
6304   format %{ "STH    $src,$mem\t! short" %}
6305   opcode(Assembler::sth_op3);
6306   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6307   ins_pipe(istore_mem_zero);
6308 %}
6309 
6310 // Store Integer
6311 instruct storeI(memory mem, iRegI src) %{
6312   match(Set mem (StoreI mem src));
6313   ins_cost(MEMORY_REF_COST);
6314 
6315   size(4);
6316   format %{ "STW    $src,$mem" %}
6317   opcode(Assembler::stw_op3);
6318   ins_encode(simple_form3_mem_reg( mem, src ) );
6319   ins_pipe(istore_mem_reg);
6320 %}
6321 
6322 // Store Long
6323 instruct storeL(memory mem, iRegL src) %{
6324   match(Set mem (StoreL mem src));
6325   ins_cost(MEMORY_REF_COST);
6326   size(4);
6327   format %{ "STX    $src,$mem\t! long" %}
6328   opcode(Assembler::stx_op3);
6329   ins_encode(simple_form3_mem_reg( mem, src ) );
6330   ins_pipe(istore_mem_reg);
6331 %}
6332 
6333 instruct storeI0(memory mem, immI0 src) %{
6334   match(Set mem (StoreI mem src));
6335   ins_cost(MEMORY_REF_COST);
6336 
6337   size(4);
6338   format %{ "STW    $src,$mem" %}
6339   opcode(Assembler::stw_op3);
6340   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6341   ins_pipe(istore_mem_zero);
6342 %}
6343 
6344 instruct storeL0(memory mem, immL0 src) %{
6345   match(Set mem (StoreL mem src));
6346   ins_cost(MEMORY_REF_COST);
6347 
6348   size(4);
6349   format %{ "STX    $src,$mem" %}
6350   opcode(Assembler::stx_op3);
6351   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6352   ins_pipe(istore_mem_zero);
6353 %}
6354 
6355 // Store Integer from float register (used after fstoi)
6356 instruct storeI_Freg(memory mem, regF src) %{
6357   match(Set mem (StoreI mem src));
6358   ins_cost(MEMORY_REF_COST);
6359 
6360   size(4);
6361   format %{ "STF    $src,$mem\t! after fstoi/fdtoi" %}
6362   opcode(Assembler::stf_op3);
6363   ins_encode(simple_form3_mem_reg( mem, src ) );
6364   ins_pipe(fstoreF_mem_reg);
6365 %}
6366 
6367 // Store Pointer
6368 instruct storeP(memory dst, sp_ptr_RegP src) %{
6369   match(Set dst (StoreP dst src));
6370   ins_cost(MEMORY_REF_COST);
6371   size(4);
6372 
6373 #ifndef _LP64
6374   format %{ "STW    $src,$dst\t! ptr" %}
6375   opcode(Assembler::stw_op3, 0, REGP_OP);
6376 #else
6377   format %{ "STX    $src,$dst\t! ptr" %}
6378   opcode(Assembler::stx_op3, 0, REGP_OP);
6379 #endif
6380   ins_encode( form3_mem_reg( dst, src ) );
6381   ins_pipe(istore_mem_spORreg);
6382 %}
6383 
6384 instruct storeP0(memory dst, immP0 src) %{
6385   match(Set dst (StoreP dst src));
6386   ins_cost(MEMORY_REF_COST);
6387   size(4);
6388 
6389 #ifndef _LP64
6390   format %{ "STW    $src,$dst\t! ptr" %}
6391   opcode(Assembler::stw_op3, 0, REGP_OP);
6392 #else
6393   format %{ "STX    $src,$dst\t! ptr" %}
6394   opcode(Assembler::stx_op3, 0, REGP_OP);
6395 #endif
6396   ins_encode( form3_mem_reg( dst, R_G0 ) );
6397   ins_pipe(istore_mem_zero);
6398 %}
6399 
6400 // Store Compressed Pointer
6401 instruct storeN(memory dst, iRegN src) %{
6402    match(Set dst (StoreN dst src));
6403    ins_cost(MEMORY_REF_COST);
6404    size(4);
6405 
6406    format %{ "STW    $src,$dst\t! compressed ptr" %}
6407    ins_encode %{
6408      Register base = as_Register($dst$$base);
6409      Register index = as_Register($dst$$index);
6410      Register src = $src$$Register;
6411      if (index != G0) {
6412        __ stw(src, base, index);
6413      } else {
6414        __ stw(src, base, $dst$$disp);
6415      }
6416    %}
6417    ins_pipe(istore_mem_spORreg);
6418 %}
6419 
6420 instruct storeN0(memory dst, immN0 src) %{
6421    match(Set dst (StoreN dst src));
6422    ins_cost(MEMORY_REF_COST);
6423    size(4);
6424 
6425    format %{ "STW    $src,$dst\t! compressed ptr" %}
6426    ins_encode %{
6427      Register base = as_Register($dst$$base);
6428      Register index = as_Register($dst$$index);
6429      if (index != G0) {
6430        __ stw(0, base, index);
6431      } else {
6432        __ stw(0, base, $dst$$disp);
6433      }
6434    %}
6435    ins_pipe(istore_mem_zero);
6436 %}
6437 
6438 // Store Double
6439 instruct storeD( memory mem, regD src) %{
6440   match(Set mem (StoreD mem src));
6441   ins_cost(MEMORY_REF_COST);
6442 
6443   size(4);
6444   format %{ "STDF   $src,$mem" %}
6445   opcode(Assembler::stdf_op3);
6446   ins_encode(simple_form3_mem_reg( mem, src ) );
6447   ins_pipe(fstoreD_mem_reg);
6448 %}
6449 
6450 instruct storeD0( memory mem, immD0 src) %{
6451   match(Set mem (StoreD mem src));
6452   ins_cost(MEMORY_REF_COST);
6453 
6454   size(4);
6455   format %{ "STX    $src,$mem" %}
6456   opcode(Assembler::stx_op3);
6457   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6458   ins_pipe(fstoreD_mem_zero);
6459 %}
6460 
6461 // Store Float
6462 instruct storeF( memory mem, regF src) %{
6463   match(Set mem (StoreF mem src));
6464   ins_cost(MEMORY_REF_COST);
6465 
6466   size(4);
6467   format %{ "STF    $src,$mem" %}
6468   opcode(Assembler::stf_op3);
6469   ins_encode(simple_form3_mem_reg( mem, src ) );
6470   ins_pipe(fstoreF_mem_reg);
6471 %}
6472 
6473 instruct storeF0( memory mem, immF0 src) %{
6474   match(Set mem (StoreF mem src));
6475   ins_cost(MEMORY_REF_COST);
6476 
6477   size(4);
6478   format %{ "STW    $src,$mem\t! storeF0" %}
6479   opcode(Assembler::stw_op3);
6480   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6481   ins_pipe(fstoreF_mem_zero);
6482 %}
6483 
6484 // Store Aligned Packed Bytes in Double register to memory
6485 instruct storeA8B(memory mem, regD src) %{
6486   match(Set mem (Store8B mem src));
6487   ins_cost(MEMORY_REF_COST);
6488   size(4);
6489   format %{ "STDF   $src,$mem\t! packed8B" %}
6490   opcode(Assembler::stdf_op3);
6491   ins_encode(simple_form3_mem_reg( mem, src ) );
6492   ins_pipe(fstoreD_mem_reg);
6493 %}
6494 
6495 // Convert oop pointer into compressed form
6496 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6497   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6498   match(Set dst (EncodeP src));
6499   format %{ "encode_heap_oop $src, $dst" %}
6500   ins_encode %{
6501     __ encode_heap_oop($src$$Register, $dst$$Register);
6502   %}
6503   ins_pipe(ialu_reg);
6504 %}
6505 
6506 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6507   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6508   match(Set dst (EncodeP src));
6509   format %{ "encode_heap_oop_not_null $src, $dst" %}
6510   ins_encode %{
6511     __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6512   %}
6513   ins_pipe(ialu_reg);
6514 %}
6515 
6516 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6517   predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6518             n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6519   match(Set dst (DecodeN src));
6520   format %{ "decode_heap_oop $src, $dst" %}
6521   ins_encode %{
6522     __ decode_heap_oop($src$$Register, $dst$$Register);
6523   %}
6524   ins_pipe(ialu_reg);
6525 %}
6526 
6527 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6528   predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6529             n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6530   match(Set dst (DecodeN src));
6531   format %{ "decode_heap_oop_not_null $src, $dst" %}
6532   ins_encode %{
6533     __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6534   %}
6535   ins_pipe(ialu_reg);
6536 %}
6537 
6538 
6539 // Store Zero into Aligned Packed Bytes
6540 instruct storeA8B0(memory mem, immI0 zero) %{
6541   match(Set mem (Store8B mem zero));
6542   ins_cost(MEMORY_REF_COST);
6543   size(4);
6544   format %{ "STX    $zero,$mem\t! packed8B" %}
6545   opcode(Assembler::stx_op3);
6546   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6547   ins_pipe(fstoreD_mem_zero);
6548 %}
6549 
6550 // Store Aligned Packed Chars/Shorts in Double register to memory
6551 instruct storeA4C(memory mem, regD src) %{
6552   match(Set mem (Store4C mem src));
6553   ins_cost(MEMORY_REF_COST);
6554   size(4);
6555   format %{ "STDF   $src,$mem\t! packed4C" %}
6556   opcode(Assembler::stdf_op3);
6557   ins_encode(simple_form3_mem_reg( mem, src ) );
6558   ins_pipe(fstoreD_mem_reg);
6559 %}
6560 
6561 // Store Zero into Aligned Packed Chars/Shorts
6562 instruct storeA4C0(memory mem, immI0 zero) %{
6563   match(Set mem (Store4C mem (Replicate4C zero)));
6564   ins_cost(MEMORY_REF_COST);
6565   size(4);
6566   format %{ "STX    $zero,$mem\t! packed4C" %}
6567   opcode(Assembler::stx_op3);
6568   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6569   ins_pipe(fstoreD_mem_zero);
6570 %}
6571 
6572 // Store Aligned Packed Ints in Double register to memory
6573 instruct storeA2I(memory mem, regD src) %{
6574   match(Set mem (Store2I mem src));
6575   ins_cost(MEMORY_REF_COST);
6576   size(4);
6577   format %{ "STDF   $src,$mem\t! packed2I" %}
6578   opcode(Assembler::stdf_op3);
6579   ins_encode(simple_form3_mem_reg( mem, src ) );
6580   ins_pipe(fstoreD_mem_reg);
6581 %}
6582 
6583 // Store Zero into Aligned Packed Ints
6584 instruct storeA2I0(memory mem, immI0 zero) %{
6585   match(Set mem (Store2I mem zero));
6586   ins_cost(MEMORY_REF_COST);
6587   size(4);
6588   format %{ "STX    $zero,$mem\t! packed2I" %}
6589   opcode(Assembler::stx_op3);
6590   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6591   ins_pipe(fstoreD_mem_zero);
6592 %}
6593 
6594 
6595 //----------MemBar Instructions-----------------------------------------------
6596 // Memory barrier flavors
6597 
6598 instruct membar_acquire() %{
6599   match(MemBarAcquire);
6600   ins_cost(4*MEMORY_REF_COST);
6601 
6602   size(0);
6603   format %{ "MEMBAR-acquire" %}
6604   ins_encode( enc_membar_acquire );
6605   ins_pipe(long_memory_op);
6606 %}
6607 
6608 instruct membar_acquire_lock() %{
6609   match(MemBarAcquire);
6610   predicate(Matcher::prior_fast_lock(n));
6611   ins_cost(0);
6612 
6613   size(0);
6614   format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6615   ins_encode( );
6616   ins_pipe(empty);
6617 %}
6618 
6619 instruct membar_release() %{
6620   match(MemBarRelease);
6621   ins_cost(4*MEMORY_REF_COST);
6622 
6623   size(0);
6624   format %{ "MEMBAR-release" %}
6625   ins_encode( enc_membar_release );
6626   ins_pipe(long_memory_op);
6627 %}
6628 
6629 instruct membar_release_lock() %{
6630   match(MemBarRelease);
6631   predicate(Matcher::post_fast_unlock(n));
6632   ins_cost(0);
6633 
6634   size(0);
6635   format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6636   ins_encode( );
6637   ins_pipe(empty);
6638 %}
6639 
6640 instruct membar_volatile() %{
6641   match(MemBarVolatile);
6642   ins_cost(4*MEMORY_REF_COST);
6643 
6644   size(4);
6645   format %{ "MEMBAR-volatile" %}
6646   ins_encode( enc_membar_volatile );
6647   ins_pipe(long_memory_op);
6648 %}
6649 
6650 instruct unnecessary_membar_volatile() %{
6651   match(MemBarVolatile);
6652   predicate(Matcher::post_store_load_barrier(n));
6653   ins_cost(0);
6654 
6655   size(0);
6656   format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6657   ins_encode( );
6658   ins_pipe(empty);
6659 %}
6660 
6661 //----------Register Move Instructions-----------------------------------------
6662 instruct roundDouble_nop(regD dst) %{
6663   match(Set dst (RoundDouble dst));
6664   ins_cost(0);
6665   // SPARC results are already "rounded" (i.e., normal-format IEEE)
6666   ins_encode( );
6667   ins_pipe(empty);
6668 %}
6669 
6670 
6671 instruct roundFloat_nop(regF dst) %{
6672   match(Set dst (RoundFloat dst));
6673   ins_cost(0);
6674   // SPARC results are already "rounded" (i.e., normal-format IEEE)
6675   ins_encode( );
6676   ins_pipe(empty);
6677 %}
6678 
6679 
6680 // Cast Index to Pointer for unsafe natives
6681 instruct castX2P(iRegX src, iRegP dst) %{
6682   match(Set dst (CastX2P src));
6683 
6684   format %{ "MOV    $src,$dst\t! IntX->Ptr" %}
6685   ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6686   ins_pipe(ialu_reg);
6687 %}
6688 
6689 // Cast Pointer to Index for unsafe natives
6690 instruct castP2X(iRegP src, iRegX dst) %{
6691   match(Set dst (CastP2X src));
6692 
6693   format %{ "MOV    $src,$dst\t! Ptr->IntX" %}
6694   ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6695   ins_pipe(ialu_reg);
6696 %}
6697 
6698 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6699   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6700   match(Set stkSlot src);   // chain rule
6701   ins_cost(MEMORY_REF_COST);
6702   format %{ "STDF   $src,$stkSlot\t!stk" %}
6703   opcode(Assembler::stdf_op3);
6704   ins_encode(simple_form3_mem_reg(stkSlot, src));
6705   ins_pipe(fstoreD_stk_reg);
6706 %}
6707 
6708 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6709   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6710   match(Set dst stkSlot);   // chain rule
6711   ins_cost(MEMORY_REF_COST);
6712   format %{ "LDDF   $stkSlot,$dst\t!stk" %}
6713   opcode(Assembler::lddf_op3);
6714   ins_encode(simple_form3_mem_reg(stkSlot, dst));
6715   ins_pipe(floadD_stk);
6716 %}
6717 
6718 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6719   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6720   match(Set stkSlot src);   // chain rule
6721   ins_cost(MEMORY_REF_COST);
6722   format %{ "STF   $src,$stkSlot\t!stk" %}
6723   opcode(Assembler::stf_op3);
6724   ins_encode(simple_form3_mem_reg(stkSlot, src));
6725   ins_pipe(fstoreF_stk_reg);
6726 %}
6727 
6728 //----------Conditional Move---------------------------------------------------
6729 // Conditional move
6730 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6731   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6732   ins_cost(150);
6733   format %{ "MOV$cmp $pcc,$src,$dst" %}
6734   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6735   ins_pipe(ialu_reg);
6736 %}
6737 
6738 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6739   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6740   ins_cost(140);
6741   format %{ "MOV$cmp $pcc,$src,$dst" %}
6742   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6743   ins_pipe(ialu_imm);
6744 %}
6745 
6746 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6747   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6748   ins_cost(150);
6749   size(4);
6750   format %{ "MOV$cmp  $icc,$src,$dst" %}
6751   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6752   ins_pipe(ialu_reg);
6753 %}
6754 
6755 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6756   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6757   ins_cost(140);
6758   size(4);
6759   format %{ "MOV$cmp  $icc,$src,$dst" %}
6760   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6761   ins_pipe(ialu_imm);
6762 %}
6763 
6764 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6765   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6766   ins_cost(150);
6767   size(4);
6768   format %{ "MOV$cmp  $icc,$src,$dst" %}
6769   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6770   ins_pipe(ialu_reg);
6771 %}
6772 
6773 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6774   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6775   ins_cost(140);
6776   size(4);
6777   format %{ "MOV$cmp  $icc,$src,$dst" %}
6778   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6779   ins_pipe(ialu_imm);
6780 %}
6781 
6782 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6783   match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6784   ins_cost(150);
6785   size(4);
6786   format %{ "MOV$cmp $fcc,$src,$dst" %}
6787   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6788   ins_pipe(ialu_reg);
6789 %}
6790 
6791 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6792   match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6793   ins_cost(140);
6794   size(4);
6795   format %{ "MOV$cmp $fcc,$src,$dst" %}
6796   ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6797   ins_pipe(ialu_imm);
6798 %}
6799 
6800 // Conditional move for RegN. Only cmov(reg,reg).
6801 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6802   match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6803   ins_cost(150);
6804   format %{ "MOV$cmp $pcc,$src,$dst" %}
6805   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6806   ins_pipe(ialu_reg);
6807 %}
6808 
6809 // This instruction also works with CmpN so we don't need cmovNN_reg.
6810 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6811   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6812   ins_cost(150);
6813   size(4);
6814   format %{ "MOV$cmp  $icc,$src,$dst" %}
6815   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6816   ins_pipe(ialu_reg);
6817 %}
6818 
6819 // This instruction also works with CmpN so we don't need cmovNN_reg.
6820 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6821   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6822   ins_cost(150);
6823   size(4);
6824   format %{ "MOV$cmp  $icc,$src,$dst" %}
6825   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6826   ins_pipe(ialu_reg);
6827 %}
6828 
6829 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6830   match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6831   ins_cost(150);
6832   size(4);
6833   format %{ "MOV$cmp $fcc,$src,$dst" %}
6834   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6835   ins_pipe(ialu_reg);
6836 %}
6837 
6838 // Conditional move
6839 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6840   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6841   ins_cost(150);
6842   format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6843   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6844   ins_pipe(ialu_reg);
6845 %}
6846 
6847 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6848   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6849   ins_cost(140);
6850   format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6851   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6852   ins_pipe(ialu_imm);
6853 %}
6854 
6855 // This instruction also works with CmpN so we don't need cmovPN_reg.
6856 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6857   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6858   ins_cost(150);
6859 
6860   size(4);
6861   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6862   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6863   ins_pipe(ialu_reg);
6864 %}
6865 
6866 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6867   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6868   ins_cost(150);
6869 
6870   size(4);
6871   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6872   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6873   ins_pipe(ialu_reg);
6874 %}
6875 
6876 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6877   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6878   ins_cost(140);
6879 
6880   size(4);
6881   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6882   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6883   ins_pipe(ialu_imm);
6884 %}
6885 
6886 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6887   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6888   ins_cost(140);
6889 
6890   size(4);
6891   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6892   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6893   ins_pipe(ialu_imm);
6894 %}
6895 
6896 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6897   match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6898   ins_cost(150);
6899   size(4);
6900   format %{ "MOV$cmp $fcc,$src,$dst" %}
6901   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6902   ins_pipe(ialu_imm);
6903 %}
6904 
6905 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6906   match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6907   ins_cost(140);
6908   size(4);
6909   format %{ "MOV$cmp $fcc,$src,$dst" %}
6910   ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6911   ins_pipe(ialu_imm);
6912 %}
6913 
6914 // Conditional move
6915 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6916   match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6917   ins_cost(150);
6918   opcode(0x101);
6919   format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6920   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6921   ins_pipe(int_conditional_float_move);
6922 %}
6923 
6924 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6925   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6926   ins_cost(150);
6927 
6928   size(4);
6929   format %{ "FMOVS$cmp $icc,$src,$dst" %}
6930   opcode(0x101);
6931   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6932   ins_pipe(int_conditional_float_move);
6933 %}
6934 
6935 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6936   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6937   ins_cost(150);
6938 
6939   size(4);
6940   format %{ "FMOVS$cmp $icc,$src,$dst" %}
6941   opcode(0x101);
6942   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6943   ins_pipe(int_conditional_float_move);
6944 %}
6945 
6946 // Conditional move,
6947 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6948   match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6949   ins_cost(150);
6950   size(4);
6951   format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6952   opcode(0x1);
6953   ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6954   ins_pipe(int_conditional_double_move);
6955 %}
6956 
6957 // Conditional move
6958 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6959   match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6960   ins_cost(150);
6961   size(4);
6962   opcode(0x102);
6963   format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6964   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6965   ins_pipe(int_conditional_double_move);
6966 %}
6967 
6968 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6969   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6970   ins_cost(150);
6971 
6972   size(4);
6973   format %{ "FMOVD$cmp $icc,$src,$dst" %}
6974   opcode(0x102);
6975   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6976   ins_pipe(int_conditional_double_move);
6977 %}
6978 
6979 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6980   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6981   ins_cost(150);
6982 
6983   size(4);
6984   format %{ "FMOVD$cmp $icc,$src,$dst" %}
6985   opcode(0x102);
6986   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6987   ins_pipe(int_conditional_double_move);
6988 %}
6989 
6990 // Conditional move,
6991 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6992   match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6993   ins_cost(150);
6994   size(4);
6995   format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6996   opcode(0x2);
6997   ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6998   ins_pipe(int_conditional_double_move);
6999 %}
7000 
7001 // Conditional move
7002 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7003   match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7004   ins_cost(150);
7005   format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7006   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7007   ins_pipe(ialu_reg);
7008 %}
7009 
7010 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7011   match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7012   ins_cost(140);
7013   format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7014   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7015   ins_pipe(ialu_imm);
7016 %}
7017 
7018 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7019   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7020   ins_cost(150);
7021 
7022   size(4);
7023   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
7024   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7025   ins_pipe(ialu_reg);
7026 %}
7027 
7028 
7029 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7030   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7031   ins_cost(150);
7032 
7033   size(4);
7034   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
7035   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7036   ins_pipe(ialu_reg);
7037 %}
7038 
7039 
7040 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7041   match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7042   ins_cost(150);
7043 
7044   size(4);
7045   format %{ "MOV$cmp  $fcc,$src,$dst\t! long" %}
7046   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7047   ins_pipe(ialu_reg);
7048 %}
7049 
7050 
7051 
7052 //----------OS and Locking Instructions----------------------------------------
7053 
7054 // This name is KNOWN by the ADLC and cannot be changed.
7055 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7056 // for this guy.
7057 instruct tlsLoadP(g2RegP dst) %{
7058   match(Set dst (ThreadLocal));
7059 
7060   size(0);
7061   ins_cost(0);
7062   format %{ "# TLS is in G2" %}
7063   ins_encode( /*empty encoding*/ );
7064   ins_pipe(ialu_none);
7065 %}
7066 
7067 instruct checkCastPP( iRegP dst ) %{
7068   match(Set dst (CheckCastPP dst));
7069 
7070   size(0);
7071   format %{ "# checkcastPP of $dst" %}
7072   ins_encode( /*empty encoding*/ );
7073   ins_pipe(empty);
7074 %}
7075 
7076 
7077 instruct castPP( iRegP dst ) %{
7078   match(Set dst (CastPP dst));
7079   format %{ "# castPP of $dst" %}
7080   ins_encode( /*empty encoding*/ );
7081   ins_pipe(empty);
7082 %}
7083 
7084 instruct castII( iRegI dst ) %{
7085   match(Set dst (CastII dst));
7086   format %{ "# castII of $dst" %}
7087   ins_encode( /*empty encoding*/ );
7088   ins_cost(0);
7089   ins_pipe(empty);
7090 %}
7091 
7092 //----------Arithmetic Instructions--------------------------------------------
7093 // Addition Instructions
7094 // Register Addition
7095 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7096   match(Set dst (AddI src1 src2));
7097 
7098   size(4);
7099   format %{ "ADD    $src1,$src2,$dst" %}
7100   ins_encode %{
7101     __ add($src1$$Register, $src2$$Register, $dst$$Register);
7102   %}
7103   ins_pipe(ialu_reg_reg);
7104 %}
7105 
7106 // Immediate Addition
7107 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7108   match(Set dst (AddI src1 src2));
7109 
7110   size(4);
7111   format %{ "ADD    $src1,$src2,$dst" %}
7112   opcode(Assembler::add_op3, Assembler::arith_op);
7113   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7114   ins_pipe(ialu_reg_imm);
7115 %}
7116 
7117 // Pointer Register Addition
7118 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7119   match(Set dst (AddP src1 src2));
7120 
7121   size(4);
7122   format %{ "ADD    $src1,$src2,$dst" %}
7123   opcode(Assembler::add_op3, Assembler::arith_op);
7124   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7125   ins_pipe(ialu_reg_reg);
7126 %}
7127 
7128 // Pointer Immediate Addition
7129 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7130   match(Set dst (AddP src1 src2));
7131 
7132   size(4);
7133   format %{ "ADD    $src1,$src2,$dst" %}
7134   opcode(Assembler::add_op3, Assembler::arith_op);
7135   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7136   ins_pipe(ialu_reg_imm);
7137 %}
7138 
7139 // Long Addition
7140 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7141   match(Set dst (AddL src1 src2));
7142 
7143   size(4);
7144   format %{ "ADD    $src1,$src2,$dst\t! long" %}
7145   opcode(Assembler::add_op3, Assembler::arith_op);
7146   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7147   ins_pipe(ialu_reg_reg);
7148 %}
7149 
7150 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7151   match(Set dst (AddL src1 con));
7152 
7153   size(4);
7154   format %{ "ADD    $src1,$con,$dst" %}
7155   opcode(Assembler::add_op3, Assembler::arith_op);
7156   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7157   ins_pipe(ialu_reg_imm);
7158 %}
7159 
7160 //----------Conditional_store--------------------------------------------------
7161 // Conditional-store of the updated heap-top.
7162 // Used during allocation of the shared heap.
7163 // Sets flags (EQ) on success.  Implemented with a CASA on Sparc.
7164 
7165 // LoadP-locked.  Same as a regular pointer load when used with a compare-swap
7166 instruct loadPLocked(iRegP dst, memory mem) %{
7167   match(Set dst (LoadPLocked mem));
7168   ins_cost(MEMORY_REF_COST);
7169 
7170 #ifndef _LP64
7171   size(4);
7172   format %{ "LDUW   $mem,$dst\t! ptr" %}
7173   opcode(Assembler::lduw_op3, 0, REGP_OP);
7174 #else
7175   format %{ "LDX    $mem,$dst\t! ptr" %}
7176   opcode(Assembler::ldx_op3, 0, REGP_OP);
7177 #endif
7178   ins_encode( form3_mem_reg( mem, dst ) );
7179   ins_pipe(iload_mem);
7180 %}
7181 
7182 // LoadL-locked.  Same as a regular long load when used with a compare-swap
7183 instruct loadLLocked(iRegL dst, memory mem) %{
7184   match(Set dst (LoadLLocked mem));
7185   ins_cost(MEMORY_REF_COST);
7186   size(4);
7187   format %{ "LDX    $mem,$dst\t! long" %}
7188   opcode(Assembler::ldx_op3);
7189   ins_encode(simple_form3_mem_reg( mem, dst ) );
7190   ins_pipe(iload_mem);
7191 %}
7192 
7193 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7194   match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7195   effect( KILL newval );
7196   format %{ "CASA   [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7197             "CMP    R_G3,$oldval\t\t! See if we made progress"  %}
7198   ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7199   ins_pipe( long_memory_op );
7200 %}
7201 
7202 // Conditional-store of an int value.
7203 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7204   match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7205   effect( KILL newval );
7206   format %{ "CASA   [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7207             "CMP    $oldval,$newval\t\t! See if we made progress"  %}
7208   ins_encode( enc_cas(mem_ptr,oldval,newval) );
7209   ins_pipe( long_memory_op );
7210 %}
7211 
7212 // Conditional-store of a long value.
7213 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7214   match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7215   effect( KILL newval );
7216   format %{ "CASXA  [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7217             "CMP    $oldval,$newval\t\t! See if we made progress"  %}
7218   ins_encode( enc_cas(mem_ptr,oldval,newval) );
7219   ins_pipe( long_memory_op );
7220 %}
7221 
7222 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7223 
7224 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7225   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7226   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7227   format %{
7228             "MOV    $newval,O7\n\t"
7229             "CASXA  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7230             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7231             "MOV    1,$res\n\t"
7232             "MOVne  xcc,R_G0,$res"
7233   %}
7234   ins_encode( enc_casx(mem_ptr, oldval, newval),
7235               enc_lflags_ne_to_boolean(res) );
7236   ins_pipe( long_memory_op );
7237 %}
7238 
7239 
7240 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7241   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7242   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7243   format %{
7244             "MOV    $newval,O7\n\t"
7245             "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7246             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7247             "MOV    1,$res\n\t"
7248             "MOVne  icc,R_G0,$res"
7249   %}
7250   ins_encode( enc_casi(mem_ptr, oldval, newval),
7251               enc_iflags_ne_to_boolean(res) );
7252   ins_pipe( long_memory_op );
7253 %}
7254 
7255 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7256   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7257   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7258   format %{
7259             "MOV    $newval,O7\n\t"
7260             "CASA_PTR  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7261             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7262             "MOV    1,$res\n\t"
7263             "MOVne  xcc,R_G0,$res"
7264   %}
7265 #ifdef _LP64
7266   ins_encode( enc_casx(mem_ptr, oldval, newval),
7267               enc_lflags_ne_to_boolean(res) );
7268 #else
7269   ins_encode( enc_casi(mem_ptr, oldval, newval),
7270               enc_iflags_ne_to_boolean(res) );
7271 #endif
7272   ins_pipe( long_memory_op );
7273 %}
7274 
7275 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7276   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7277   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7278   format %{
7279             "MOV    $newval,O7\n\t"
7280             "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7281             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7282             "MOV    1,$res\n\t"
7283             "MOVne  icc,R_G0,$res"
7284   %}
7285   ins_encode( enc_casi(mem_ptr, oldval, newval),
7286               enc_iflags_ne_to_boolean(res) );
7287   ins_pipe( long_memory_op );
7288 %}
7289 
7290 //---------------------
7291 // Subtraction Instructions
7292 // Register Subtraction
7293 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7294   match(Set dst (SubI src1 src2));
7295 
7296   size(4);
7297   format %{ "SUB    $src1,$src2,$dst" %}
7298   opcode(Assembler::sub_op3, Assembler::arith_op);
7299   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7300   ins_pipe(ialu_reg_reg);
7301 %}
7302 
7303 // Immediate Subtraction
7304 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7305   match(Set dst (SubI src1 src2));
7306 
7307   size(4);
7308   format %{ "SUB    $src1,$src2,$dst" %}
7309   opcode(Assembler::sub_op3, Assembler::arith_op);
7310   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7311   ins_pipe(ialu_reg_imm);
7312 %}
7313 
7314 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7315   match(Set dst (SubI zero src2));
7316 
7317   size(4);
7318   format %{ "NEG    $src2,$dst" %}
7319   opcode(Assembler::sub_op3, Assembler::arith_op);
7320   ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7321   ins_pipe(ialu_zero_reg);
7322 %}
7323 
7324 // Long subtraction
7325 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7326   match(Set dst (SubL src1 src2));
7327 
7328   size(4);
7329   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7330   opcode(Assembler::sub_op3, Assembler::arith_op);
7331   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7332   ins_pipe(ialu_reg_reg);
7333 %}
7334 
7335 // Immediate Subtraction
7336 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7337   match(Set dst (SubL src1 con));
7338 
7339   size(4);
7340   format %{ "SUB    $src1,$con,$dst\t! long" %}
7341   opcode(Assembler::sub_op3, Assembler::arith_op);
7342   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7343   ins_pipe(ialu_reg_imm);
7344 %}
7345 
7346 // Long negation
7347 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7348   match(Set dst (SubL zero src2));
7349 
7350   size(4);
7351   format %{ "NEG    $src2,$dst\t! long" %}
7352   opcode(Assembler::sub_op3, Assembler::arith_op);
7353   ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7354   ins_pipe(ialu_zero_reg);
7355 %}
7356 
7357 // Multiplication Instructions
7358 // Integer Multiplication
7359 // Register Multiplication
7360 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7361   match(Set dst (MulI src1 src2));
7362 
7363   size(4);
7364   format %{ "MULX   $src1,$src2,$dst" %}
7365   opcode(Assembler::mulx_op3, Assembler::arith_op);
7366   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7367   ins_pipe(imul_reg_reg);
7368 %}
7369 
7370 // Immediate Multiplication
7371 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7372   match(Set dst (MulI src1 src2));
7373 
7374   size(4);
7375   format %{ "MULX   $src1,$src2,$dst" %}
7376   opcode(Assembler::mulx_op3, Assembler::arith_op);
7377   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7378   ins_pipe(imul_reg_imm);
7379 %}
7380 
7381 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7382   match(Set dst (MulL src1 src2));
7383   ins_cost(DEFAULT_COST * 5);
7384   size(4);
7385   format %{ "MULX   $src1,$src2,$dst\t! long" %}
7386   opcode(Assembler::mulx_op3, Assembler::arith_op);
7387   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7388   ins_pipe(mulL_reg_reg);
7389 %}
7390 
7391 // Immediate Multiplication
7392 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7393   match(Set dst (MulL src1 src2));
7394   ins_cost(DEFAULT_COST * 5);
7395   size(4);
7396   format %{ "MULX   $src1,$src2,$dst" %}
7397   opcode(Assembler::mulx_op3, Assembler::arith_op);
7398   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7399   ins_pipe(mulL_reg_imm);
7400 %}
7401 
7402 // Integer Division
7403 // Register Division
7404 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7405   match(Set dst (DivI src1 src2));
7406   ins_cost((2+71)*DEFAULT_COST);
7407 
7408   format %{ "SRA     $src2,0,$src2\n\t"
7409             "SRA     $src1,0,$src1\n\t"
7410             "SDIVX   $src1,$src2,$dst" %}
7411   ins_encode( idiv_reg( src1, src2, dst ) );
7412   ins_pipe(sdiv_reg_reg);
7413 %}
7414 
7415 // Immediate Division
7416 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7417   match(Set dst (DivI src1 src2));
7418   ins_cost((2+71)*DEFAULT_COST);
7419 
7420   format %{ "SRA     $src1,0,$src1\n\t"
7421             "SDIVX   $src1,$src2,$dst" %}
7422   ins_encode( idiv_imm( src1, src2, dst ) );
7423   ins_pipe(sdiv_reg_imm);
7424 %}
7425 
7426 //----------Div-By-10-Expansion------------------------------------------------
7427 // Extract hi bits of a 32x32->64 bit multiply.
7428 // Expand rule only, not matched
7429 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7430   effect( DEF dst, USE src1, USE src2 );
7431   format %{ "MULX   $src1,$src2,$dst\t! Used in div-by-10\n\t"
7432             "SRLX   $dst,#32,$dst\t\t! Extract only hi word of result" %}
7433   ins_encode( enc_mul_hi(dst,src1,src2));
7434   ins_pipe(sdiv_reg_reg);
7435 %}
7436 
7437 // Magic constant, reciprocal of 10
7438 instruct loadConI_x66666667(iRegIsafe dst) %{
7439   effect( DEF dst );
7440 
7441   size(8);
7442   format %{ "SET    0x66666667,$dst\t! Used in div-by-10" %}
7443   ins_encode( Set32(0x66666667, dst) );
7444   ins_pipe(ialu_hi_lo_reg);
7445 %}
7446 
7447 // Register Shift Right Arithmetic Long by 32-63
7448 instruct sra_31( iRegI dst, iRegI src ) %{
7449   effect( DEF dst, USE src );
7450   format %{ "SRA    $src,31,$dst\t! Used in div-by-10" %}
7451   ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7452   ins_pipe(ialu_reg_reg);
7453 %}
7454 
7455 // Arithmetic Shift Right by 8-bit immediate
7456 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7457   effect( DEF dst, USE src );
7458   format %{ "SRA    $src,2,$dst\t! Used in div-by-10" %}
7459   opcode(Assembler::sra_op3, Assembler::arith_op);
7460   ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7461   ins_pipe(ialu_reg_imm);
7462 %}
7463 
7464 // Integer DIV with 10
7465 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7466   match(Set dst (DivI src div));
7467   ins_cost((6+6)*DEFAULT_COST);
7468   expand %{
7469     iRegIsafe tmp1;               // Killed temps;
7470     iRegIsafe tmp2;               // Killed temps;
7471     iRegI tmp3;                   // Killed temps;
7472     iRegI tmp4;                   // Killed temps;
7473     loadConI_x66666667( tmp1 );   // SET  0x66666667 -> tmp1
7474     mul_hi( tmp2, src, tmp1 );    // MUL  hibits(src * tmp1) -> tmp2
7475     sra_31( tmp3, src );          // SRA  src,31 -> tmp3
7476     sra_reg_2( tmp4, tmp2 );      // SRA  tmp2,2 -> tmp4
7477     subI_reg_reg( dst,tmp4,tmp3); // SUB  tmp4 - tmp3 -> dst
7478   %}
7479 %}
7480 
7481 // Register Long Division
7482 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7483   match(Set dst (DivL src1 src2));
7484   ins_cost(DEFAULT_COST*71);
7485   size(4);
7486   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7487   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7488   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7489   ins_pipe(divL_reg_reg);
7490 %}
7491 
7492 // Register Long Division
7493 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7494   match(Set dst (DivL src1 src2));
7495   ins_cost(DEFAULT_COST*71);
7496   size(4);
7497   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7498   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7499   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7500   ins_pipe(divL_reg_imm);
7501 %}
7502 
7503 // Integer Remainder
7504 // Register Remainder
7505 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7506   match(Set dst (ModI src1 src2));
7507   effect( KILL ccr, KILL temp);
7508 
7509   format %{ "SREM   $src1,$src2,$dst" %}
7510   ins_encode( irem_reg(src1, src2, dst, temp) );
7511   ins_pipe(sdiv_reg_reg);
7512 %}
7513 
7514 // Immediate Remainder
7515 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7516   match(Set dst (ModI src1 src2));
7517   effect( KILL ccr, KILL temp);
7518 
7519   format %{ "SREM   $src1,$src2,$dst" %}
7520   ins_encode( irem_imm(src1, src2, dst, temp) );
7521   ins_pipe(sdiv_reg_imm);
7522 %}
7523 
7524 // Register Long Remainder
7525 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7526   effect(DEF dst, USE src1, USE src2);
7527   size(4);
7528   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7529   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7530   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7531   ins_pipe(divL_reg_reg);
7532 %}
7533 
7534 // Register Long Division
7535 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7536   effect(DEF dst, USE src1, USE src2);
7537   size(4);
7538   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7539   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7540   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7541   ins_pipe(divL_reg_imm);
7542 %}
7543 
7544 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7545   effect(DEF dst, USE src1, USE src2);
7546   size(4);
7547   format %{ "MULX   $src1,$src2,$dst\t! long" %}
7548   opcode(Assembler::mulx_op3, Assembler::arith_op);
7549   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7550   ins_pipe(mulL_reg_reg);
7551 %}
7552 
7553 // Immediate Multiplication
7554 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7555   effect(DEF dst, USE src1, USE src2);
7556   size(4);
7557   format %{ "MULX   $src1,$src2,$dst" %}
7558   opcode(Assembler::mulx_op3, Assembler::arith_op);
7559   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7560   ins_pipe(mulL_reg_imm);
7561 %}
7562 
7563 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7564   effect(DEF dst, USE src1, USE src2);
7565   size(4);
7566   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7567   opcode(Assembler::sub_op3, Assembler::arith_op);
7568   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7569   ins_pipe(ialu_reg_reg);
7570 %}
7571 
7572 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7573   effect(DEF dst, USE src1, USE src2);
7574   size(4);
7575   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7576   opcode(Assembler::sub_op3, Assembler::arith_op);
7577   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7578   ins_pipe(ialu_reg_reg);
7579 %}
7580 
7581 // Register Long Remainder
7582 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7583   match(Set dst (ModL src1 src2));
7584   ins_cost(DEFAULT_COST*(71 + 6 + 1));
7585   expand %{
7586     iRegL tmp1;
7587     iRegL tmp2;
7588     divL_reg_reg_1(tmp1, src1, src2);
7589     mulL_reg_reg_1(tmp2, tmp1, src2);
7590     subL_reg_reg_1(dst,  src1, tmp2);
7591   %}
7592 %}
7593 
7594 // Register Long Remainder
7595 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7596   match(Set dst (ModL src1 src2));
7597   ins_cost(DEFAULT_COST*(71 + 6 + 1));
7598   expand %{
7599     iRegL tmp1;
7600     iRegL tmp2;
7601     divL_reg_imm13_1(tmp1, src1, src2);
7602     mulL_reg_imm13_1(tmp2, tmp1, src2);
7603     subL_reg_reg_2  (dst,  src1, tmp2);
7604   %}
7605 %}
7606 
7607 // Integer Shift Instructions
7608 // Register Shift Left
7609 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7610   match(Set dst (LShiftI src1 src2));
7611 
7612   size(4);
7613   format %{ "SLL    $src1,$src2,$dst" %}
7614   opcode(Assembler::sll_op3, Assembler::arith_op);
7615   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7616   ins_pipe(ialu_reg_reg);
7617 %}
7618 
7619 // Register Shift Left Immediate
7620 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7621   match(Set dst (LShiftI src1 src2));
7622 
7623   size(4);
7624   format %{ "SLL    $src1,$src2,$dst" %}
7625   opcode(Assembler::sll_op3, Assembler::arith_op);
7626   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7627   ins_pipe(ialu_reg_imm);
7628 %}
7629 
7630 // Register Shift Left
7631 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7632   match(Set dst (LShiftL src1 src2));
7633 
7634   size(4);
7635   format %{ "SLLX   $src1,$src2,$dst" %}
7636   opcode(Assembler::sllx_op3, Assembler::arith_op);
7637   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7638   ins_pipe(ialu_reg_reg);
7639 %}
7640 
7641 // Register Shift Left Immediate
7642 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7643   match(Set dst (LShiftL src1 src2));
7644 
7645   size(4);
7646   format %{ "SLLX   $src1,$src2,$dst" %}
7647   opcode(Assembler::sllx_op3, Assembler::arith_op);
7648   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7649   ins_pipe(ialu_reg_imm);
7650 %}
7651 
7652 // Register Arithmetic Shift Right
7653 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7654   match(Set dst (RShiftI src1 src2));
7655   size(4);
7656   format %{ "SRA    $src1,$src2,$dst" %}
7657   opcode(Assembler::sra_op3, Assembler::arith_op);
7658   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7659   ins_pipe(ialu_reg_reg);
7660 %}
7661 
7662 // Register Arithmetic Shift Right Immediate
7663 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7664   match(Set dst (RShiftI src1 src2));
7665 
7666   size(4);
7667   format %{ "SRA    $src1,$src2,$dst" %}
7668   opcode(Assembler::sra_op3, Assembler::arith_op);
7669   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7670   ins_pipe(ialu_reg_imm);
7671 %}
7672 
7673 // Register Shift Right Arithmatic Long
7674 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7675   match(Set dst (RShiftL src1 src2));
7676 
7677   size(4);
7678   format %{ "SRAX   $src1,$src2,$dst" %}
7679   opcode(Assembler::srax_op3, Assembler::arith_op);
7680   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7681   ins_pipe(ialu_reg_reg);
7682 %}
7683 
7684 // Register Shift Left Immediate
7685 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7686   match(Set dst (RShiftL src1 src2));
7687 
7688   size(4);
7689   format %{ "SRAX   $src1,$src2,$dst" %}
7690   opcode(Assembler::srax_op3, Assembler::arith_op);
7691   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7692   ins_pipe(ialu_reg_imm);
7693 %}
7694 
7695 // Register Shift Right
7696 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7697   match(Set dst (URShiftI src1 src2));
7698 
7699   size(4);
7700   format %{ "SRL    $src1,$src2,$dst" %}
7701   opcode(Assembler::srl_op3, Assembler::arith_op);
7702   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7703   ins_pipe(ialu_reg_reg);
7704 %}
7705 
7706 // Register Shift Right Immediate
7707 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7708   match(Set dst (URShiftI src1 src2));
7709 
7710   size(4);
7711   format %{ "SRL    $src1,$src2,$dst" %}
7712   opcode(Assembler::srl_op3, Assembler::arith_op);
7713   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7714   ins_pipe(ialu_reg_imm);
7715 %}
7716 
7717 // Register Shift Right
7718 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7719   match(Set dst (URShiftL src1 src2));
7720 
7721   size(4);
7722   format %{ "SRLX   $src1,$src2,$dst" %}
7723   opcode(Assembler::srlx_op3, Assembler::arith_op);
7724   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7725   ins_pipe(ialu_reg_reg);
7726 %}
7727 
7728 // Register Shift Right Immediate
7729 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7730   match(Set dst (URShiftL src1 src2));
7731 
7732   size(4);
7733   format %{ "SRLX   $src1,$src2,$dst" %}
7734   opcode(Assembler::srlx_op3, Assembler::arith_op);
7735   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7736   ins_pipe(ialu_reg_imm);
7737 %}
7738 
7739 // Register Shift Right Immediate with a CastP2X
7740 #ifdef _LP64
7741 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7742   match(Set dst (URShiftL (CastP2X src1) src2));
7743   size(4);
7744   format %{ "SRLX   $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7745   opcode(Assembler::srlx_op3, Assembler::arith_op);
7746   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7747   ins_pipe(ialu_reg_imm);
7748 %}
7749 #else
7750 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7751   match(Set dst (URShiftI (CastP2X src1) src2));
7752   size(4);
7753   format %{ "SRL    $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7754   opcode(Assembler::srl_op3, Assembler::arith_op);
7755   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7756   ins_pipe(ialu_reg_imm);
7757 %}
7758 #endif
7759 
7760 
7761 //----------Floating Point Arithmetic Instructions-----------------------------
7762 
7763 //  Add float single precision
7764 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7765   match(Set dst (AddF src1 src2));
7766 
7767   size(4);
7768   format %{ "FADDS  $src1,$src2,$dst" %}
7769   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7770   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7771   ins_pipe(faddF_reg_reg);
7772 %}
7773 
7774 //  Add float double precision
7775 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7776   match(Set dst (AddD src1 src2));
7777 
7778   size(4);
7779   format %{ "FADDD  $src1,$src2,$dst" %}
7780   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7781   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7782   ins_pipe(faddD_reg_reg);
7783 %}
7784 
7785 //  Sub float single precision
7786 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7787   match(Set dst (SubF src1 src2));
7788 
7789   size(4);
7790   format %{ "FSUBS  $src1,$src2,$dst" %}
7791   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7792   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7793   ins_pipe(faddF_reg_reg);
7794 %}
7795 
7796 //  Sub float double precision
7797 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7798   match(Set dst (SubD src1 src2));
7799 
7800   size(4);
7801   format %{ "FSUBD  $src1,$src2,$dst" %}
7802   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7803   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7804   ins_pipe(faddD_reg_reg);
7805 %}
7806 
7807 //  Mul float single precision
7808 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7809   match(Set dst (MulF src1 src2));
7810 
7811   size(4);
7812   format %{ "FMULS  $src1,$src2,$dst" %}
7813   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7814   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7815   ins_pipe(fmulF_reg_reg);
7816 %}
7817 
7818 //  Mul float double precision
7819 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7820   match(Set dst (MulD src1 src2));
7821 
7822   size(4);
7823   format %{ "FMULD  $src1,$src2,$dst" %}
7824   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7825   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7826   ins_pipe(fmulD_reg_reg);
7827 %}
7828 
7829 //  Div float single precision
7830 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7831   match(Set dst (DivF src1 src2));
7832 
7833   size(4);
7834   format %{ "FDIVS  $src1,$src2,$dst" %}
7835   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7836   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7837   ins_pipe(fdivF_reg_reg);
7838 %}
7839 
7840 //  Div float double precision
7841 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7842   match(Set dst (DivD src1 src2));
7843 
7844   size(4);
7845   format %{ "FDIVD  $src1,$src2,$dst" %}
7846   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7847   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7848   ins_pipe(fdivD_reg_reg);
7849 %}
7850 
7851 //  Absolute float double precision
7852 instruct absD_reg(regD dst, regD src) %{
7853   match(Set dst (AbsD src));
7854 
7855   format %{ "FABSd  $src,$dst" %}
7856   ins_encode(fabsd(dst, src));
7857   ins_pipe(faddD_reg);
7858 %}
7859 
7860 //  Absolute float single precision
7861 instruct absF_reg(regF dst, regF src) %{
7862   match(Set dst (AbsF src));
7863 
7864   format %{ "FABSs  $src,$dst" %}
7865   ins_encode(fabss(dst, src));
7866   ins_pipe(faddF_reg);
7867 %}
7868 
7869 instruct negF_reg(regF dst, regF src) %{
7870   match(Set dst (NegF src));
7871 
7872   size(4);
7873   format %{ "FNEGs  $src,$dst" %}
7874   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7875   ins_encode(form3_opf_rs2F_rdF(src, dst));
7876   ins_pipe(faddF_reg);
7877 %}
7878 
7879 instruct negD_reg(regD dst, regD src) %{
7880   match(Set dst (NegD src));
7881 
7882   format %{ "FNEGd  $src,$dst" %}
7883   ins_encode(fnegd(dst, src));
7884   ins_pipe(faddD_reg);
7885 %}
7886 
7887 //  Sqrt float double precision
7888 instruct sqrtF_reg_reg(regF dst, regF src) %{
7889   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7890 
7891   size(4);
7892   format %{ "FSQRTS $src,$dst" %}
7893   ins_encode(fsqrts(dst, src));
7894   ins_pipe(fdivF_reg_reg);
7895 %}
7896 
7897 //  Sqrt float double precision
7898 instruct sqrtD_reg_reg(regD dst, regD src) %{
7899   match(Set dst (SqrtD src));
7900 
7901   size(4);
7902   format %{ "FSQRTD $src,$dst" %}
7903   ins_encode(fsqrtd(dst, src));
7904   ins_pipe(fdivD_reg_reg);
7905 %}
7906 
7907 //----------Logical Instructions-----------------------------------------------
7908 // And Instructions
7909 // Register And
7910 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7911   match(Set dst (AndI src1 src2));
7912 
7913   size(4);
7914   format %{ "AND    $src1,$src2,$dst" %}
7915   opcode(Assembler::and_op3, Assembler::arith_op);
7916   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7917   ins_pipe(ialu_reg_reg);
7918 %}
7919 
7920 // Immediate And
7921 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7922   match(Set dst (AndI src1 src2));
7923 
7924   size(4);
7925   format %{ "AND    $src1,$src2,$dst" %}
7926   opcode(Assembler::and_op3, Assembler::arith_op);
7927   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7928   ins_pipe(ialu_reg_imm);
7929 %}
7930 
7931 // Register And Long
7932 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7933   match(Set dst (AndL src1 src2));
7934 
7935   ins_cost(DEFAULT_COST);
7936   size(4);
7937   format %{ "AND    $src1,$src2,$dst\t! long" %}
7938   opcode(Assembler::and_op3, Assembler::arith_op);
7939   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7940   ins_pipe(ialu_reg_reg);
7941 %}
7942 
7943 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7944   match(Set dst (AndL src1 con));
7945 
7946   ins_cost(DEFAULT_COST);
7947   size(4);
7948   format %{ "AND    $src1,$con,$dst\t! long" %}
7949   opcode(Assembler::and_op3, Assembler::arith_op);
7950   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7951   ins_pipe(ialu_reg_imm);
7952 %}
7953 
7954 // Or Instructions
7955 // Register Or
7956 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7957   match(Set dst (OrI src1 src2));
7958 
7959   size(4);
7960   format %{ "OR     $src1,$src2,$dst" %}
7961   opcode(Assembler::or_op3, Assembler::arith_op);
7962   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7963   ins_pipe(ialu_reg_reg);
7964 %}
7965 
7966 // Immediate Or
7967 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7968   match(Set dst (OrI src1 src2));
7969 
7970   size(4);
7971   format %{ "OR     $src1,$src2,$dst" %}
7972   opcode(Assembler::or_op3, Assembler::arith_op);
7973   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7974   ins_pipe(ialu_reg_imm);
7975 %}
7976 
7977 // Register Or Long
7978 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7979   match(Set dst (OrL src1 src2));
7980 
7981   ins_cost(DEFAULT_COST);
7982   size(4);
7983   format %{ "OR     $src1,$src2,$dst\t! long" %}
7984   opcode(Assembler::or_op3, Assembler::arith_op);
7985   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7986   ins_pipe(ialu_reg_reg);
7987 %}
7988 
7989 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7990   match(Set dst (OrL src1 con));
7991   ins_cost(DEFAULT_COST*2);
7992 
7993   ins_cost(DEFAULT_COST);
7994   size(4);
7995   format %{ "OR     $src1,$con,$dst\t! long" %}
7996   opcode(Assembler::or_op3, Assembler::arith_op);
7997   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7998   ins_pipe(ialu_reg_imm);
7999 %}
8000 
8001 #ifndef _LP64
8002 
8003 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8004 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8005   match(Set dst (OrI src1 (CastP2X src2)));
8006 
8007   size(4);
8008   format %{ "OR     $src1,$src2,$dst" %}
8009   opcode(Assembler::or_op3, Assembler::arith_op);
8010   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8011   ins_pipe(ialu_reg_reg);
8012 %}
8013 
8014 #else
8015 
8016 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8017   match(Set dst (OrL src1 (CastP2X src2)));
8018 
8019   ins_cost(DEFAULT_COST);
8020   size(4);
8021   format %{ "OR     $src1,$src2,$dst\t! long" %}
8022   opcode(Assembler::or_op3, Assembler::arith_op);
8023   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8024   ins_pipe(ialu_reg_reg);
8025 %}
8026 
8027 #endif
8028 
8029 // Xor Instructions
8030 // Register Xor
8031 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8032   match(Set dst (XorI src1 src2));
8033 
8034   size(4);
8035   format %{ "XOR    $src1,$src2,$dst" %}
8036   opcode(Assembler::xor_op3, Assembler::arith_op);
8037   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8038   ins_pipe(ialu_reg_reg);
8039 %}
8040 
8041 // Immediate Xor
8042 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8043   match(Set dst (XorI src1 src2));
8044 
8045   size(4);
8046   format %{ "XOR    $src1,$src2,$dst" %}
8047   opcode(Assembler::xor_op3, Assembler::arith_op);
8048   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8049   ins_pipe(ialu_reg_imm);
8050 %}
8051 
8052 // Register Xor Long
8053 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8054   match(Set dst (XorL src1 src2));
8055 
8056   ins_cost(DEFAULT_COST);
8057   size(4);
8058   format %{ "XOR    $src1,$src2,$dst\t! long" %}
8059   opcode(Assembler::xor_op3, Assembler::arith_op);
8060   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8061   ins_pipe(ialu_reg_reg);
8062 %}
8063 
8064 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8065   match(Set dst (XorL src1 con));
8066 
8067   ins_cost(DEFAULT_COST);
8068   size(4);
8069   format %{ "XOR    $src1,$con,$dst\t! long" %}
8070   opcode(Assembler::xor_op3, Assembler::arith_op);
8071   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8072   ins_pipe(ialu_reg_imm);
8073 %}
8074 
8075 //----------Convert to Boolean-------------------------------------------------
8076 // Nice hack for 32-bit tests but doesn't work for
8077 // 64-bit pointers.
8078 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8079   match(Set dst (Conv2B src));
8080   effect( KILL ccr );
8081   ins_cost(DEFAULT_COST*2);
8082   format %{ "CMP    R_G0,$src\n\t"
8083             "ADDX   R_G0,0,$dst" %}
8084   ins_encode( enc_to_bool( src, dst ) );
8085   ins_pipe(ialu_reg_ialu);
8086 %}
8087 
8088 #ifndef _LP64
8089 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8090   match(Set dst (Conv2B src));
8091   effect( KILL ccr );
8092   ins_cost(DEFAULT_COST*2);
8093   format %{ "CMP    R_G0,$src\n\t"
8094             "ADDX   R_G0,0,$dst" %}
8095   ins_encode( enc_to_bool( src, dst ) );
8096   ins_pipe(ialu_reg_ialu);
8097 %}
8098 #else
8099 instruct convP2B( iRegI dst, iRegP src ) %{
8100   match(Set dst (Conv2B src));
8101   ins_cost(DEFAULT_COST*2);
8102   format %{ "MOV    $src,$dst\n\t"
8103             "MOVRNZ $src,1,$dst" %}
8104   ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8105   ins_pipe(ialu_clr_and_mover);
8106 %}
8107 #endif
8108 
8109 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8110   match(Set dst (CmpLTMask src zero));
8111   effect(KILL ccr);
8112   size(4);
8113   format %{ "SRA    $src,#31,$dst\t# cmpLTMask0" %}
8114   ins_encode %{
8115     __ sra($src$$Register, 31, $dst$$Register);
8116   %}
8117   ins_pipe(ialu_reg_imm);
8118 %}
8119 
8120 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8121   match(Set dst (CmpLTMask p q));
8122   effect( KILL ccr );
8123   ins_cost(DEFAULT_COST*4);
8124   format %{ "CMP    $p,$q\n\t"
8125             "MOV    #0,$dst\n\t"
8126             "BLT,a  .+8\n\t"
8127             "MOV    #-1,$dst" %}
8128   ins_encode( enc_ltmask(p,q,dst) );
8129   ins_pipe(ialu_reg_reg_ialu);
8130 %}
8131 
8132 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8133   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8134   effect(KILL ccr, TEMP tmp);
8135   ins_cost(DEFAULT_COST*3);
8136 
8137   format %{ "SUBcc  $p,$q,$p\t! p' = p-q\n\t"
8138             "ADD    $p,$y,$tmp\t! g3=p-q+y\n\t"
8139             "MOVlt  $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8140   ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8141   ins_pipe( cadd_cmpltmask );
8142 %}
8143 
8144 
8145 //-----------------------------------------------------------------
8146 // Direct raw moves between float and general registers using VIS3.
8147 
8148 //  ins_pipe(faddF_reg);
8149 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8150   predicate(UseVIS >= 3);
8151   match(Set dst (MoveF2I src));
8152 
8153   format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8154   ins_encode %{
8155     __ movstouw($src$$FloatRegister, $dst$$Register);
8156   %}
8157   ins_pipe(ialu_reg_reg);
8158 %}
8159 
8160 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8161   predicate(UseVIS >= 3);
8162   match(Set dst (MoveI2F src));
8163 
8164   format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8165   ins_encode %{
8166     __ movwtos($src$$Register, $dst$$FloatRegister);
8167   %}
8168   ins_pipe(ialu_reg_reg);
8169 %}
8170 
8171 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8172   predicate(UseVIS >= 3);
8173   match(Set dst (MoveD2L src));
8174 
8175   format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8176   ins_encode %{
8177     __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8178   %}
8179   ins_pipe(ialu_reg_reg);
8180 %}
8181 
8182 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8183   predicate(UseVIS >= 3);
8184   match(Set dst (MoveL2D src));
8185 
8186   format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8187   ins_encode %{
8188     __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8189   %}
8190   ins_pipe(ialu_reg_reg);
8191 %}
8192 
8193 
8194 // Raw moves between float and general registers using stack.
8195 
8196 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8197   match(Set dst (MoveF2I src));
8198   effect(DEF dst, USE src);
8199   ins_cost(MEMORY_REF_COST);
8200 
8201   size(4);
8202   format %{ "LDUW   $src,$dst\t! MoveF2I" %}
8203   opcode(Assembler::lduw_op3);
8204   ins_encode(simple_form3_mem_reg( src, dst ) );
8205   ins_pipe(iload_mem);
8206 %}
8207 
8208 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8209   match(Set dst (MoveI2F src));
8210   effect(DEF dst, USE src);
8211   ins_cost(MEMORY_REF_COST);
8212 
8213   size(4);
8214   format %{ "LDF    $src,$dst\t! MoveI2F" %}
8215   opcode(Assembler::ldf_op3);
8216   ins_encode(simple_form3_mem_reg(src, dst));
8217   ins_pipe(floadF_stk);
8218 %}
8219 
8220 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8221   match(Set dst (MoveD2L src));
8222   effect(DEF dst, USE src);
8223   ins_cost(MEMORY_REF_COST);
8224 
8225   size(4);
8226   format %{ "LDX    $src,$dst\t! MoveD2L" %}
8227   opcode(Assembler::ldx_op3);
8228   ins_encode(simple_form3_mem_reg( src, dst ) );
8229   ins_pipe(iload_mem);
8230 %}
8231 
8232 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8233   match(Set dst (MoveL2D src));
8234   effect(DEF dst, USE src);
8235   ins_cost(MEMORY_REF_COST);
8236 
8237   size(4);
8238   format %{ "LDDF   $src,$dst\t! MoveL2D" %}
8239   opcode(Assembler::lddf_op3);
8240   ins_encode(simple_form3_mem_reg(src, dst));
8241   ins_pipe(floadD_stk);
8242 %}
8243 
8244 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8245   match(Set dst (MoveF2I src));
8246   effect(DEF dst, USE src);
8247   ins_cost(MEMORY_REF_COST);
8248 
8249   size(4);
8250   format %{ "STF   $src,$dst\t! MoveF2I" %}
8251   opcode(Assembler::stf_op3);
8252   ins_encode(simple_form3_mem_reg(dst, src));
8253   ins_pipe(fstoreF_stk_reg);
8254 %}
8255 
8256 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8257   match(Set dst (MoveI2F src));
8258   effect(DEF dst, USE src);
8259   ins_cost(MEMORY_REF_COST);
8260 
8261   size(4);
8262   format %{ "STW    $src,$dst\t! MoveI2F" %}
8263   opcode(Assembler::stw_op3);
8264   ins_encode(simple_form3_mem_reg( dst, src ) );
8265   ins_pipe(istore_mem_reg);
8266 %}
8267 
8268 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8269   match(Set dst (MoveD2L src));
8270   effect(DEF dst, USE src);
8271   ins_cost(MEMORY_REF_COST);
8272 
8273   size(4);
8274   format %{ "STDF   $src,$dst\t! MoveD2L" %}
8275   opcode(Assembler::stdf_op3);
8276   ins_encode(simple_form3_mem_reg(dst, src));
8277   ins_pipe(fstoreD_stk_reg);
8278 %}
8279 
8280 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8281   match(Set dst (MoveL2D src));
8282   effect(DEF dst, USE src);
8283   ins_cost(MEMORY_REF_COST);
8284 
8285   size(4);
8286   format %{ "STX    $src,$dst\t! MoveL2D" %}
8287   opcode(Assembler::stx_op3);
8288   ins_encode(simple_form3_mem_reg( dst, src ) );
8289   ins_pipe(istore_mem_reg);
8290 %}
8291 
8292 
8293 //----------Arithmetic Conversion Instructions---------------------------------
8294 // The conversions operations are all Alpha sorted.  Please keep it that way!
8295 
8296 instruct convD2F_reg(regF dst, regD src) %{
8297   match(Set dst (ConvD2F src));
8298   size(4);
8299   format %{ "FDTOS  $src,$dst" %}
8300   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8301   ins_encode(form3_opf_rs2D_rdF(src, dst));
8302   ins_pipe(fcvtD2F);
8303 %}
8304 
8305 
8306 // Convert a double to an int in a float register.
8307 // If the double is a NAN, stuff a zero in instead.
8308 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8309   effect(DEF dst, USE src, KILL fcc0);
8310   format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
8311             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8312             "FDTOI  $src,$dst\t! convert in delay slot\n\t"
8313             "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
8314             "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
8315       "skip:" %}
8316   ins_encode(form_d2i_helper(src,dst));
8317   ins_pipe(fcvtD2I);
8318 %}
8319 
8320 instruct convD2I_stk(stackSlotI dst, regD src) %{
8321   match(Set dst (ConvD2I src));
8322   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8323   expand %{
8324     regF tmp;
8325     convD2I_helper(tmp, src);
8326     regF_to_stkI(dst, tmp);
8327   %}
8328 %}
8329 
8330 instruct convD2I_reg(iRegI dst, regD src) %{
8331   predicate(UseVIS >= 3);
8332   match(Set dst (ConvD2I src));
8333   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8334   expand %{
8335     regF tmp;
8336     convD2I_helper(tmp, src);
8337     MoveF2I_reg_reg(dst, tmp);
8338   %}
8339 %}
8340 
8341 
8342 // Convert a double to a long in a double register.
8343 // If the double is a NAN, stuff a zero in instead.
8344 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8345   effect(DEF dst, USE src, KILL fcc0);
8346   format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
8347             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8348             "FDTOX  $src,$dst\t! convert in delay slot\n\t"
8349             "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
8350             "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
8351       "skip:" %}
8352   ins_encode(form_d2l_helper(src,dst));
8353   ins_pipe(fcvtD2L);
8354 %}
8355 
8356 instruct convD2L_stk(stackSlotL dst, regD src) %{
8357   match(Set dst (ConvD2L src));
8358   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8359   expand %{
8360     regD tmp;
8361     convD2L_helper(tmp, src);
8362     regD_to_stkL(dst, tmp);
8363   %}
8364 %}
8365 
8366 instruct convD2L_reg(iRegL dst, regD src) %{
8367   predicate(UseVIS >= 3);
8368   match(Set dst (ConvD2L src));
8369   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8370   expand %{
8371     regD tmp;
8372     convD2L_helper(tmp, src);
8373     MoveD2L_reg_reg(dst, tmp);
8374   %}
8375 %}
8376 
8377 
8378 instruct convF2D_reg(regD dst, regF src) %{
8379   match(Set dst (ConvF2D src));
8380   format %{ "FSTOD  $src,$dst" %}
8381   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8382   ins_encode(form3_opf_rs2F_rdD(src, dst));
8383   ins_pipe(fcvtF2D);
8384 %}
8385 
8386 
8387 // Convert a float to an int in a float register.
8388 // If the float is a NAN, stuff a zero in instead.
8389 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8390   effect(DEF dst, USE src, KILL fcc0);
8391   format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
8392             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8393             "FSTOI  $src,$dst\t! convert in delay slot\n\t"
8394             "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
8395             "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
8396       "skip:" %}
8397   ins_encode(form_f2i_helper(src,dst));
8398   ins_pipe(fcvtF2I);
8399 %}
8400 
8401 instruct convF2I_stk(stackSlotI dst, regF src) %{
8402   match(Set dst (ConvF2I src));
8403   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8404   expand %{
8405     regF tmp;
8406     convF2I_helper(tmp, src);
8407     regF_to_stkI(dst, tmp);
8408   %}
8409 %}
8410 
8411 instruct convF2I_reg(iRegI dst, regF src) %{
8412   predicate(UseVIS >= 3);
8413   match(Set dst (ConvF2I src));
8414   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8415   expand %{
8416     regF tmp;
8417     convF2I_helper(tmp, src);
8418     MoveF2I_reg_reg(dst, tmp);
8419   %}
8420 %}
8421 
8422 
8423 // Convert a float to a long in a float register.
8424 // If the float is a NAN, stuff a zero in instead.
8425 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8426   effect(DEF dst, USE src, KILL fcc0);
8427   format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
8428             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8429             "FSTOX  $src,$dst\t! convert in delay slot\n\t"
8430             "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
8431             "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
8432       "skip:" %}
8433   ins_encode(form_f2l_helper(src,dst));
8434   ins_pipe(fcvtF2L);
8435 %}
8436 
8437 instruct convF2L_stk(stackSlotL dst, regF src) %{
8438   match(Set dst (ConvF2L src));
8439   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8440   expand %{
8441     regD tmp;
8442     convF2L_helper(tmp, src);
8443     regD_to_stkL(dst, tmp);
8444   %}
8445 %}
8446 
8447 instruct convF2L_reg(iRegL dst, regF src) %{
8448   predicate(UseVIS >= 3);
8449   match(Set dst (ConvF2L src));
8450   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8451   expand %{
8452     regD tmp;
8453     convF2L_helper(tmp, src);
8454     MoveD2L_reg_reg(dst, tmp);
8455   %}
8456 %}
8457 
8458 
8459 instruct convI2D_helper(regD dst, regF tmp) %{
8460   effect(USE tmp, DEF dst);
8461   format %{ "FITOD  $tmp,$dst" %}
8462   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8463   ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8464   ins_pipe(fcvtI2D);
8465 %}
8466 
8467 instruct convI2D_stk(stackSlotI src, regD dst) %{
8468   match(Set dst (ConvI2D src));
8469   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8470   expand %{
8471     regF tmp;
8472     stkI_to_regF(tmp, src);
8473     convI2D_helper(dst, tmp);
8474   %}
8475 %}
8476 
8477 instruct convI2D_reg(regD_low dst, iRegI src) %{
8478   predicate(UseVIS >= 3);
8479   match(Set dst (ConvI2D src));
8480   expand %{
8481     regF tmp;
8482     MoveI2F_reg_reg(tmp, src);
8483     convI2D_helper(dst, tmp);
8484   %}
8485 %}
8486 
8487 instruct convI2D_mem(regD_low dst, memory mem) %{
8488   match(Set dst (ConvI2D (LoadI mem)));
8489   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8490   size(8);
8491   format %{ "LDF    $mem,$dst\n\t"
8492             "FITOD  $dst,$dst" %}
8493   opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8494   ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8495   ins_pipe(floadF_mem);
8496 %}
8497 
8498 
8499 instruct convI2F_helper(regF dst, regF tmp) %{
8500   effect(DEF dst, USE tmp);
8501   format %{ "FITOS  $tmp,$dst" %}
8502   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8503   ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8504   ins_pipe(fcvtI2F);
8505 %}
8506 
8507 instruct convI2F_stk(regF dst, stackSlotI src) %{
8508   match(Set dst (ConvI2F src));
8509   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8510   expand %{
8511     regF tmp;
8512     stkI_to_regF(tmp,src);
8513     convI2F_helper(dst, tmp);
8514   %}
8515 %}
8516 
8517 instruct convI2F_reg(regF dst, iRegI src) %{
8518   predicate(UseVIS >= 3);
8519   match(Set dst (ConvI2F src));
8520   ins_cost(DEFAULT_COST);
8521   expand %{
8522     regF tmp;
8523     MoveI2F_reg_reg(tmp, src);
8524     convI2F_helper(dst, tmp);
8525   %}
8526 %}
8527 
8528 instruct convI2F_mem( regF dst, memory mem ) %{
8529   match(Set dst (ConvI2F (LoadI mem)));
8530   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8531   size(8);
8532   format %{ "LDF    $mem,$dst\n\t"
8533             "FITOS  $dst,$dst" %}
8534   opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8535   ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8536   ins_pipe(floadF_mem);
8537 %}
8538 
8539 
8540 instruct convI2L_reg(iRegL dst, iRegI src) %{
8541   match(Set dst (ConvI2L src));
8542   size(4);
8543   format %{ "SRA    $src,0,$dst\t! int->long" %}
8544   opcode(Assembler::sra_op3, Assembler::arith_op);
8545   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8546   ins_pipe(ialu_reg_reg);
8547 %}
8548 
8549 // Zero-extend convert int to long
8550 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8551   match(Set dst (AndL (ConvI2L src) mask) );
8552   size(4);
8553   format %{ "SRL    $src,0,$dst\t! zero-extend int to long" %}
8554   opcode(Assembler::srl_op3, Assembler::arith_op);
8555   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8556   ins_pipe(ialu_reg_reg);
8557 %}
8558 
8559 // Zero-extend long
8560 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8561   match(Set dst (AndL src mask) );
8562   size(4);
8563   format %{ "SRL    $src,0,$dst\t! zero-extend long" %}
8564   opcode(Assembler::srl_op3, Assembler::arith_op);
8565   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8566   ins_pipe(ialu_reg_reg);
8567 %}
8568 
8569 
8570 //-----------
8571 // Long to Double conversion using V8 opcodes.
8572 // Still useful because cheetah traps and becomes
8573 // amazingly slow for some common numbers.
8574 
8575 // Magic constant, 0x43300000
8576 instruct loadConI_x43300000(iRegI dst) %{
8577   effect(DEF dst);
8578   size(4);
8579   format %{ "SETHI  HI(0x43300000),$dst\t! 2^52" %}
8580   ins_encode(SetHi22(0x43300000, dst));
8581   ins_pipe(ialu_none);
8582 %}
8583 
8584 // Magic constant, 0x41f00000
8585 instruct loadConI_x41f00000(iRegI dst) %{
8586   effect(DEF dst);
8587   size(4);
8588   format %{ "SETHI  HI(0x41f00000),$dst\t! 2^32" %}
8589   ins_encode(SetHi22(0x41f00000, dst));
8590   ins_pipe(ialu_none);
8591 %}
8592 
8593 // Construct a double from two float halves
8594 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8595   effect(DEF dst, USE src1, USE src2);
8596   size(8);
8597   format %{ "FMOVS  $src1.hi,$dst.hi\n\t"
8598             "FMOVS  $src2.lo,$dst.lo" %}
8599   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8600   ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8601   ins_pipe(faddD_reg_reg);
8602 %}
8603 
8604 // Convert integer in high half of a double register (in the lower half of
8605 // the double register file) to double
8606 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8607   effect(DEF dst, USE src);
8608   size(4);
8609   format %{ "FITOD  $src,$dst" %}
8610   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8611   ins_encode(form3_opf_rs2D_rdD(src, dst));
8612   ins_pipe(fcvtLHi2D);
8613 %}
8614 
8615 // Add float double precision
8616 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8617   effect(DEF dst, USE src1, USE src2);
8618   size(4);
8619   format %{ "FADDD  $src1,$src2,$dst" %}
8620   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8621   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8622   ins_pipe(faddD_reg_reg);
8623 %}
8624 
8625 // Sub float double precision
8626 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8627   effect(DEF dst, USE src1, USE src2);
8628   size(4);
8629   format %{ "FSUBD  $src1,$src2,$dst" %}
8630   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8631   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8632   ins_pipe(faddD_reg_reg);
8633 %}
8634 
8635 // Mul float double precision
8636 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8637   effect(DEF dst, USE src1, USE src2);
8638   size(4);
8639   format %{ "FMULD  $src1,$src2,$dst" %}
8640   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8641   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8642   ins_pipe(fmulD_reg_reg);
8643 %}
8644 
8645 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8646   match(Set dst (ConvL2D src));
8647   ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8648 
8649   expand %{
8650     regD_low   tmpsrc;
8651     iRegI      ix43300000;
8652     iRegI      ix41f00000;
8653     stackSlotL lx43300000;
8654     stackSlotL lx41f00000;
8655     regD_low   dx43300000;
8656     regD       dx41f00000;
8657     regD       tmp1;
8658     regD_low   tmp2;
8659     regD       tmp3;
8660     regD       tmp4;
8661 
8662     stkL_to_regD(tmpsrc, src);
8663 
8664     loadConI_x43300000(ix43300000);
8665     loadConI_x41f00000(ix41f00000);
8666     regI_to_stkLHi(lx43300000, ix43300000);
8667     regI_to_stkLHi(lx41f00000, ix41f00000);
8668     stkL_to_regD(dx43300000, lx43300000);
8669     stkL_to_regD(dx41f00000, lx41f00000);
8670 
8671     convI2D_regDHi_regD(tmp1, tmpsrc);
8672     regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8673     subD_regD_regD(tmp3, tmp2, dx43300000);
8674     mulD_regD_regD(tmp4, tmp1, dx41f00000);
8675     addD_regD_regD(dst, tmp3, tmp4);
8676   %}
8677 %}
8678 
8679 // Long to Double conversion using fast fxtof
8680 instruct convL2D_helper(regD dst, regD tmp) %{
8681   effect(DEF dst, USE tmp);
8682   size(4);
8683   format %{ "FXTOD  $tmp,$dst" %}
8684   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8685   ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8686   ins_pipe(fcvtL2D);
8687 %}
8688 
8689 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8690   predicate(VM_Version::has_fast_fxtof());
8691   match(Set dst (ConvL2D src));
8692   ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8693   expand %{
8694     regD tmp;
8695     stkL_to_regD(tmp, src);
8696     convL2D_helper(dst, tmp);
8697   %}
8698 %}
8699 
8700 instruct convL2D_reg(regD dst, iRegL src) %{
8701   predicate(UseVIS >= 3);
8702   match(Set dst (ConvL2D src));
8703   expand %{
8704     regD tmp;
8705     MoveL2D_reg_reg(tmp, src);
8706     convL2D_helper(dst, tmp);
8707   %}
8708 %}
8709 
8710 // Long to Float conversion using fast fxtof
8711 instruct convL2F_helper(regF dst, regD tmp) %{
8712   effect(DEF dst, USE tmp);
8713   size(4);
8714   format %{ "FXTOS  $tmp,$dst" %}
8715   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8716   ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8717   ins_pipe(fcvtL2F);
8718 %}
8719 
8720 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8721   match(Set dst (ConvL2F src));
8722   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8723   expand %{
8724     regD tmp;
8725     stkL_to_regD(tmp, src);
8726     convL2F_helper(dst, tmp);
8727   %}
8728 %}
8729 
8730 instruct convL2F_reg(regF dst, iRegL src) %{
8731   predicate(UseVIS >= 3);
8732   match(Set dst (ConvL2F src));
8733   ins_cost(DEFAULT_COST);
8734   expand %{
8735     regD tmp;
8736     MoveL2D_reg_reg(tmp, src);
8737     convL2F_helper(dst, tmp);
8738   %}
8739 %}
8740 
8741 //-----------
8742 
8743 instruct convL2I_reg(iRegI dst, iRegL src) %{
8744   match(Set dst (ConvL2I src));
8745 #ifndef _LP64
8746   format %{ "MOV    $src.lo,$dst\t! long->int" %}
8747   ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8748   ins_pipe(ialu_move_reg_I_to_L);
8749 #else
8750   size(4);
8751   format %{ "SRA    $src,R_G0,$dst\t! long->int" %}
8752   ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8753   ins_pipe(ialu_reg);
8754 #endif
8755 %}
8756 
8757 // Register Shift Right Immediate
8758 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8759   match(Set dst (ConvL2I (RShiftL src cnt)));
8760 
8761   size(4);
8762   format %{ "SRAX   $src,$cnt,$dst" %}
8763   opcode(Assembler::srax_op3, Assembler::arith_op);
8764   ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8765   ins_pipe(ialu_reg_imm);
8766 %}
8767 
8768 // Replicate scalar to packed byte values in Double register
8769 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8770   effect(DEF dst, USE src);
8771   format %{ "SLLX  $src,56,$dst\n\t"
8772             "SRLX  $dst, 8,O7\n\t"
8773             "OR    $dst,O7,$dst\n\t"
8774             "SRLX  $dst,16,O7\n\t"
8775             "OR    $dst,O7,$dst\n\t"
8776             "SRLX  $dst,32,O7\n\t"
8777             "OR    $dst,O7,$dst\t! replicate8B" %}
8778   ins_encode( enc_repl8b(src, dst));
8779   ins_pipe(ialu_reg);
8780 %}
8781 
8782 // Replicate scalar to packed byte values in Double register
8783 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8784   match(Set dst (Replicate8B src));
8785   expand %{
8786     iRegL tmp;
8787     Repl8B_reg_helper(tmp, src);
8788     regL_to_stkD(dst, tmp);
8789   %}
8790 %}
8791 
8792 // Replicate scalar constant to packed byte values in Double register
8793 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
8794   match(Set dst (Replicate8B con));
8795   effect(KILL tmp);
8796   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8797   ins_encode %{
8798     // XXX This is a quick fix for 6833573.
8799     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8800     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
8801     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8802   %}
8803   ins_pipe(loadConFD);
8804 %}
8805 
8806 // Replicate scalar to packed char values into stack slot
8807 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8808   effect(DEF dst, USE src);
8809   format %{ "SLLX  $src,48,$dst\n\t"
8810             "SRLX  $dst,16,O7\n\t"
8811             "OR    $dst,O7,$dst\n\t"
8812             "SRLX  $dst,32,O7\n\t"
8813             "OR    $dst,O7,$dst\t! replicate4C" %}
8814   ins_encode( enc_repl4s(src, dst) );
8815   ins_pipe(ialu_reg);
8816 %}
8817 
8818 // Replicate scalar to packed char values into stack slot
8819 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8820   match(Set dst (Replicate4C src));
8821   expand %{
8822     iRegL tmp;
8823     Repl4C_reg_helper(tmp, src);
8824     regL_to_stkD(dst, tmp);
8825   %}
8826 %}
8827 
8828 // Replicate scalar constant to packed char values in Double register
8829 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
8830   match(Set dst (Replicate4C con));
8831   effect(KILL tmp);
8832   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8833   ins_encode %{
8834     // XXX This is a quick fix for 6833573.
8835     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8836     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8837     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8838   %}
8839   ins_pipe(loadConFD);
8840 %}
8841 
8842 // Replicate scalar to packed short values into stack slot
8843 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8844   effect(DEF dst, USE src);
8845   format %{ "SLLX  $src,48,$dst\n\t"
8846             "SRLX  $dst,16,O7\n\t"
8847             "OR    $dst,O7,$dst\n\t"
8848             "SRLX  $dst,32,O7\n\t"
8849             "OR    $dst,O7,$dst\t! replicate4S" %}
8850   ins_encode( enc_repl4s(src, dst) );
8851   ins_pipe(ialu_reg);
8852 %}
8853 
8854 // Replicate scalar to packed short values into stack slot
8855 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8856   match(Set dst (Replicate4S src));
8857   expand %{
8858     iRegL tmp;
8859     Repl4S_reg_helper(tmp, src);
8860     regL_to_stkD(dst, tmp);
8861   %}
8862 %}
8863 
8864 // Replicate scalar constant to packed short values in Double register
8865 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
8866   match(Set dst (Replicate4S con));
8867   effect(KILL tmp);
8868   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8869   ins_encode %{
8870     // XXX This is a quick fix for 6833573.
8871     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8872     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8873     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8874   %}
8875   ins_pipe(loadConFD);
8876 %}
8877 
8878 // Replicate scalar to packed int values in Double register
8879 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8880   effect(DEF dst, USE src);
8881   format %{ "SLLX  $src,32,$dst\n\t"
8882             "SRLX  $dst,32,O7\n\t"
8883             "OR    $dst,O7,$dst\t! replicate2I" %}
8884   ins_encode( enc_repl2i(src, dst));
8885   ins_pipe(ialu_reg);
8886 %}
8887 
8888 // Replicate scalar to packed int values in Double register
8889 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8890   match(Set dst (Replicate2I src));
8891   expand %{
8892     iRegL tmp;
8893     Repl2I_reg_helper(tmp, src);
8894     regL_to_stkD(dst, tmp);
8895   %}
8896 %}
8897 
8898 // Replicate scalar zero constant to packed int values in Double register
8899 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
8900   match(Set dst (Replicate2I con));
8901   effect(KILL tmp);
8902   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
8903   ins_encode %{
8904     // XXX This is a quick fix for 6833573.
8905     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
8906     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
8907     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8908   %}
8909   ins_pipe(loadConFD);
8910 %}
8911 
8912 //----------Control Flow Instructions------------------------------------------
8913 // Compare Instructions
8914 // Compare Integers
8915 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8916   match(Set icc (CmpI op1 op2));
8917   effect( DEF icc, USE op1, USE op2 );
8918 
8919   size(4);
8920   format %{ "CMP    $op1,$op2" %}
8921   opcode(Assembler::subcc_op3, Assembler::arith_op);
8922   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8923   ins_pipe(ialu_cconly_reg_reg);
8924 %}
8925 
8926 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8927   match(Set icc (CmpU op1 op2));
8928 
8929   size(4);
8930   format %{ "CMP    $op1,$op2\t! unsigned" %}
8931   opcode(Assembler::subcc_op3, Assembler::arith_op);
8932   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8933   ins_pipe(ialu_cconly_reg_reg);
8934 %}
8935 
8936 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8937   match(Set icc (CmpI op1 op2));
8938   effect( DEF icc, USE op1 );
8939 
8940   size(4);
8941   format %{ "CMP    $op1,$op2" %}
8942   opcode(Assembler::subcc_op3, Assembler::arith_op);
8943   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8944   ins_pipe(ialu_cconly_reg_imm);
8945 %}
8946 
8947 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8948   match(Set icc (CmpI (AndI op1 op2) zero));
8949 
8950   size(4);
8951   format %{ "BTST   $op2,$op1" %}
8952   opcode(Assembler::andcc_op3, Assembler::arith_op);
8953   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8954   ins_pipe(ialu_cconly_reg_reg_zero);
8955 %}
8956 
8957 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8958   match(Set icc (CmpI (AndI op1 op2) zero));
8959 
8960   size(4);
8961   format %{ "BTST   $op2,$op1" %}
8962   opcode(Assembler::andcc_op3, Assembler::arith_op);
8963   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8964   ins_pipe(ialu_cconly_reg_imm_zero);
8965 %}
8966 
8967 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8968   match(Set xcc (CmpL op1 op2));
8969   effect( DEF xcc, USE op1, USE op2 );
8970 
8971   size(4);
8972   format %{ "CMP    $op1,$op2\t\t! long" %}
8973   opcode(Assembler::subcc_op3, Assembler::arith_op);
8974   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8975   ins_pipe(ialu_cconly_reg_reg);
8976 %}
8977 
8978 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8979   match(Set xcc (CmpL op1 con));
8980   effect( DEF xcc, USE op1, USE con );
8981 
8982   size(4);
8983   format %{ "CMP    $op1,$con\t\t! long" %}
8984   opcode(Assembler::subcc_op3, Assembler::arith_op);
8985   ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8986   ins_pipe(ialu_cconly_reg_reg);
8987 %}
8988 
8989 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8990   match(Set xcc (CmpL (AndL op1 op2) zero));
8991   effect( DEF xcc, USE op1, USE op2 );
8992 
8993   size(4);
8994   format %{ "BTST   $op1,$op2\t\t! long" %}
8995   opcode(Assembler::andcc_op3, Assembler::arith_op);
8996   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8997   ins_pipe(ialu_cconly_reg_reg);
8998 %}
8999 
9000 // useful for checking the alignment of a pointer:
9001 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
9002   match(Set xcc (CmpL (AndL op1 con) zero));
9003   effect( DEF xcc, USE op1, USE con );
9004 
9005   size(4);
9006   format %{ "BTST   $op1,$con\t\t! long" %}
9007   opcode(Assembler::andcc_op3, Assembler::arith_op);
9008   ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9009   ins_pipe(ialu_cconly_reg_reg);
9010 %}
9011 
9012 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
9013   match(Set icc (CmpU op1 op2));
9014 
9015   size(4);
9016   format %{ "CMP    $op1,$op2\t! unsigned" %}
9017   opcode(Assembler::subcc_op3, Assembler::arith_op);
9018   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9019   ins_pipe(ialu_cconly_reg_imm);
9020 %}
9021 
9022 // Compare Pointers
9023 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9024   match(Set pcc (CmpP op1 op2));
9025 
9026   size(4);
9027   format %{ "CMP    $op1,$op2\t! ptr" %}
9028   opcode(Assembler::subcc_op3, Assembler::arith_op);
9029   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9030   ins_pipe(ialu_cconly_reg_reg);
9031 %}
9032 
9033 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9034   match(Set pcc (CmpP op1 op2));
9035 
9036   size(4);
9037   format %{ "CMP    $op1,$op2\t! ptr" %}
9038   opcode(Assembler::subcc_op3, Assembler::arith_op);
9039   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9040   ins_pipe(ialu_cconly_reg_imm);
9041 %}
9042 
9043 // Compare Narrow oops
9044 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9045   match(Set icc (CmpN op1 op2));
9046 
9047   size(4);
9048   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
9049   opcode(Assembler::subcc_op3, Assembler::arith_op);
9050   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9051   ins_pipe(ialu_cconly_reg_reg);
9052 %}
9053 
9054 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9055   match(Set icc (CmpN op1 op2));
9056 
9057   size(4);
9058   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
9059   opcode(Assembler::subcc_op3, Assembler::arith_op);
9060   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9061   ins_pipe(ialu_cconly_reg_imm);
9062 %}
9063 
9064 //----------Max and Min--------------------------------------------------------
9065 // Min Instructions
9066 // Conditional move for min
9067 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9068   effect( USE_DEF op2, USE op1, USE icc );
9069 
9070   size(4);
9071   format %{ "MOVlt  icc,$op1,$op2\t! min" %}
9072   opcode(Assembler::less);
9073   ins_encode( enc_cmov_reg_minmax(op2,op1) );
9074   ins_pipe(ialu_reg_flags);
9075 %}
9076 
9077 // Min Register with Register.
9078 instruct minI_eReg(iRegI op1, iRegI op2) %{
9079   match(Set op2 (MinI op1 op2));
9080   ins_cost(DEFAULT_COST*2);
9081   expand %{
9082     flagsReg icc;
9083     compI_iReg(icc,op1,op2);
9084     cmovI_reg_lt(op2,op1,icc);
9085   %}
9086 %}
9087 
9088 // Max Instructions
9089 // Conditional move for max
9090 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9091   effect( USE_DEF op2, USE op1, USE icc );
9092   format %{ "MOVgt  icc,$op1,$op2\t! max" %}
9093   opcode(Assembler::greater);
9094   ins_encode( enc_cmov_reg_minmax(op2,op1) );
9095   ins_pipe(ialu_reg_flags);
9096 %}
9097 
9098 // Max Register with Register
9099 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9100   match(Set op2 (MaxI op1 op2));
9101   ins_cost(DEFAULT_COST*2);
9102   expand %{
9103     flagsReg icc;
9104     compI_iReg(icc,op1,op2);
9105     cmovI_reg_gt(op2,op1,icc);
9106   %}
9107 %}
9108 
9109 
9110 //----------Float Compares----------------------------------------------------
9111 // Compare floating, generate condition code
9112 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9113   match(Set fcc (CmpF src1 src2));
9114 
9115   size(4);
9116   format %{ "FCMPs  $fcc,$src1,$src2" %}
9117   opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9118   ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9119   ins_pipe(faddF_fcc_reg_reg_zero);
9120 %}
9121 
9122 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9123   match(Set fcc (CmpD src1 src2));
9124 
9125   size(4);
9126   format %{ "FCMPd  $fcc,$src1,$src2" %}
9127   opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9128   ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9129   ins_pipe(faddD_fcc_reg_reg_zero);
9130 %}
9131 
9132 
9133 // Compare floating, generate -1,0,1
9134 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9135   match(Set dst (CmpF3 src1 src2));
9136   effect(KILL fcc0);
9137   ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9138   format %{ "fcmpl  $dst,$src1,$src2" %}
9139   // Primary = float
9140   opcode( true );
9141   ins_encode( floating_cmp( dst, src1, src2 ) );
9142   ins_pipe( floating_cmp );
9143 %}
9144 
9145 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9146   match(Set dst (CmpD3 src1 src2));
9147   effect(KILL fcc0);
9148   ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9149   format %{ "dcmpl  $dst,$src1,$src2" %}
9150   // Primary = double (not float)
9151   opcode( false );
9152   ins_encode( floating_cmp( dst, src1, src2 ) );
9153   ins_pipe( floating_cmp );
9154 %}
9155 
9156 //----------Branches---------------------------------------------------------
9157 // Jump
9158 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9159 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9160   match(Jump switch_val);
9161 
9162   ins_cost(350);
9163 
9164   format %{  "ADD    $constanttablebase, $constantoffset, O7\n\t"
9165              "LD     [O7 + $switch_val], O7\n\t"
9166              "JUMP   O7"
9167          %}
9168   ins_encode %{
9169     // Calculate table address into a register.
9170     Register table_reg;
9171     Register label_reg = O7;
9172     if (constant_offset() == 0) {
9173       table_reg = $constanttablebase;
9174     } else {
9175       table_reg = O7;
9176       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9177       __ add($constanttablebase, con_offset, table_reg);
9178     }
9179 
9180     // Jump to base address + switch value
9181     __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9182     __ jmp(label_reg, G0);
9183     __ delayed()->nop();
9184   %}
9185   ins_pc_relative(1);
9186   ins_pipe(ialu_reg_reg);
9187 %}
9188 
9189 // Direct Branch.  Use V8 version with longer range.
9190 instruct branch(label labl) %{
9191   match(Goto);
9192   effect(USE labl);
9193 
9194   size(8);
9195   ins_cost(BRANCH_COST);
9196   format %{ "BA     $labl" %}
9197   ins_encode %{
9198     Label* L = $labl$$label;
9199     __ ba(*L);
9200     __ delayed()->nop();
9201   %}
9202   ins_pc_relative(1);
9203   ins_pipe(br);
9204 %}
9205 
9206 // Conditional Direct Branch
9207 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9208   match(If cmp icc);
9209   effect(USE labl);
9210 
9211   size(8);
9212   ins_cost(BRANCH_COST);
9213   format %{ "BP$cmp   $icc,$labl" %}
9214   // Prim = bits 24-22, Secnd = bits 31-30
9215   ins_encode( enc_bp( labl, cmp, icc ) );
9216   ins_pc_relative(1);
9217   ins_pipe(br_cc);
9218 %}
9219 
9220 // Branch-on-register tests all 64 bits.  We assume that values
9221 // in 64-bit registers always remains zero or sign extended
9222 // unless our code munges the high bits.  Interrupts can chop
9223 // the high order bits to zero or sign at any time.
9224 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9225   match(If cmp (CmpI op1 zero));
9226   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9227   effect(USE labl);
9228 
9229   size(8);
9230   ins_cost(BRANCH_COST);
9231   format %{ "BR$cmp   $op1,$labl" %}
9232   ins_encode( enc_bpr( labl, cmp, op1 ) );
9233   ins_pc_relative(1);
9234   ins_pipe(br_reg);
9235 %}
9236 
9237 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9238   match(If cmp (CmpP op1 null));
9239   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9240   effect(USE labl);
9241 
9242   size(8);
9243   ins_cost(BRANCH_COST);
9244   format %{ "BR$cmp   $op1,$labl" %}
9245   ins_encode( enc_bpr( labl, cmp, op1 ) );
9246   ins_pc_relative(1);
9247   ins_pipe(br_reg);
9248 %}
9249 
9250 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9251   match(If cmp (CmpL op1 zero));
9252   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9253   effect(USE labl);
9254 
9255   size(8);
9256   ins_cost(BRANCH_COST);
9257   format %{ "BR$cmp   $op1,$labl" %}
9258   ins_encode( enc_bpr( labl, cmp, op1 ) );
9259   ins_pc_relative(1);
9260   ins_pipe(br_reg);
9261 %}
9262 
9263 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9264   match(If cmp icc);
9265   effect(USE labl);
9266 
9267   format %{ "BP$cmp  $icc,$labl" %}
9268   // Prim = bits 24-22, Secnd = bits 31-30
9269   ins_encode( enc_bp( labl, cmp, icc ) );
9270   ins_pc_relative(1);
9271   ins_pipe(br_cc);
9272 %}
9273 
9274 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9275   match(If cmp pcc);
9276   effect(USE labl);
9277 
9278   size(8);
9279   ins_cost(BRANCH_COST);
9280   format %{ "BP$cmp  $pcc,$labl" %}
9281   ins_encode %{
9282     Label* L = $labl$$label;
9283     Assembler::Predict predict_taken =
9284       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9285 
9286     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9287     __ delayed()->nop();
9288   %}
9289   ins_pc_relative(1);
9290   ins_pipe(br_cc);
9291 %}
9292 
9293 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9294   match(If cmp fcc);
9295   effect(USE labl);
9296 
9297   size(8);
9298   ins_cost(BRANCH_COST);
9299   format %{ "FBP$cmp $fcc,$labl" %}
9300   ins_encode %{
9301     Label* L = $labl$$label;
9302     Assembler::Predict predict_taken =
9303       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9304 
9305     __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9306     __ delayed()->nop();
9307   %}
9308   ins_pc_relative(1);
9309   ins_pipe(br_fcc);
9310 %}
9311 
9312 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9313   match(CountedLoopEnd cmp icc);
9314   effect(USE labl);
9315 
9316   size(8);
9317   ins_cost(BRANCH_COST);
9318   format %{ "BP$cmp   $icc,$labl\t! Loop end" %}
9319   // Prim = bits 24-22, Secnd = bits 31-30
9320   ins_encode( enc_bp( labl, cmp, icc ) );
9321   ins_pc_relative(1);
9322   ins_pipe(br_cc);
9323 %}
9324 
9325 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9326   match(CountedLoopEnd cmp icc);
9327   effect(USE labl);
9328 
9329   size(8);
9330   ins_cost(BRANCH_COST);
9331   format %{ "BP$cmp  $icc,$labl\t! Loop end" %}
9332   // Prim = bits 24-22, Secnd = bits 31-30
9333   ins_encode( enc_bp( labl, cmp, icc ) );
9334   ins_pc_relative(1);
9335   ins_pipe(br_cc);
9336 %}
9337 
9338 // ============================================================================
9339 // Long Compare
9340 //
9341 // Currently we hold longs in 2 registers.  Comparing such values efficiently
9342 // is tricky.  The flavor of compare used depends on whether we are testing
9343 // for LT, LE, or EQ.  For a simple LT test we can check just the sign bit.
9344 // The GE test is the negated LT test.  The LE test can be had by commuting
9345 // the operands (yielding a GE test) and then negating; negate again for the
9346 // GT test.  The EQ test is done by ORcc'ing the high and low halves, and the
9347 // NE test is negated from that.
9348 
9349 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9350 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)).  Note the
9351 // difference between 'Y' and '0L'.  The tree-matches for the CmpI sections
9352 // are collapsed internally in the ADLC's dfa-gen code.  The match for
9353 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9354 // foo match ends up with the wrong leaf.  One fix is to not match both
9355 // reg-reg and reg-zero forms of long-compare.  This is unfortunate because
9356 // both forms beat the trinary form of long-compare and both are very useful
9357 // on Intel which has so few registers.
9358 
9359 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9360   match(If cmp xcc);
9361   effect(USE labl);
9362 
9363   size(8);
9364   ins_cost(BRANCH_COST);
9365   format %{ "BP$cmp   $xcc,$labl" %}
9366   ins_encode %{
9367     Label* L = $labl$$label;
9368     Assembler::Predict predict_taken =
9369       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9370 
9371     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9372     __ delayed()->nop();
9373   %}
9374   ins_pc_relative(1);
9375   ins_pipe(br_cc);
9376 %}
9377 
9378 // Manifest a CmpL3 result in an integer register.  Very painful.
9379 // This is the test to avoid.
9380 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9381   match(Set dst (CmpL3 src1 src2) );
9382   effect( KILL ccr );
9383   ins_cost(6*DEFAULT_COST);
9384   size(24);
9385   format %{ "CMP    $src1,$src2\t\t! long\n"
9386           "\tBLT,a,pn done\n"
9387           "\tMOV    -1,$dst\t! delay slot\n"
9388           "\tBGT,a,pn done\n"
9389           "\tMOV    1,$dst\t! delay slot\n"
9390           "\tCLR    $dst\n"
9391     "done:"     %}
9392   ins_encode( cmpl_flag(src1,src2,dst) );
9393   ins_pipe(cmpL_reg);
9394 %}
9395 
9396 // Conditional move
9397 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9398   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9399   ins_cost(150);
9400   format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
9401   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9402   ins_pipe(ialu_reg);
9403 %}
9404 
9405 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9406   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9407   ins_cost(140);
9408   format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
9409   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9410   ins_pipe(ialu_imm);
9411 %}
9412 
9413 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9414   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9415   ins_cost(150);
9416   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9417   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9418   ins_pipe(ialu_reg);
9419 %}
9420 
9421 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9422   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9423   ins_cost(140);
9424   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9425   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9426   ins_pipe(ialu_imm);
9427 %}
9428 
9429 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9430   match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9431   ins_cost(150);
9432   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9433   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9434   ins_pipe(ialu_reg);
9435 %}
9436 
9437 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9438   match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9439   ins_cost(150);
9440   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9441   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9442   ins_pipe(ialu_reg);
9443 %}
9444 
9445 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9446   match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9447   ins_cost(140);
9448   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9449   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9450   ins_pipe(ialu_imm);
9451 %}
9452 
9453 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9454   match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9455   ins_cost(150);
9456   opcode(0x101);
9457   format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9458   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9459   ins_pipe(int_conditional_float_move);
9460 %}
9461 
9462 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9463   match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9464   ins_cost(150);
9465   opcode(0x102);
9466   format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9467   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9468   ins_pipe(int_conditional_float_move);
9469 %}
9470 
9471 // ============================================================================
9472 // Safepoint Instruction
9473 instruct safePoint_poll(iRegP poll) %{
9474   match(SafePoint poll);
9475   effect(USE poll);
9476 
9477   size(4);
9478 #ifdef _LP64
9479   format %{ "LDX    [$poll],R_G0\t! Safepoint: poll for GC" %}
9480 #else
9481   format %{ "LDUW   [$poll],R_G0\t! Safepoint: poll for GC" %}
9482 #endif
9483   ins_encode %{
9484     __ relocate(relocInfo::poll_type);
9485     __ ld_ptr($poll$$Register, 0, G0);
9486   %}
9487   ins_pipe(loadPollP);
9488 %}
9489 
9490 // ============================================================================
9491 // Call Instructions
9492 // Call Java Static Instruction
9493 instruct CallStaticJavaDirect( method meth ) %{
9494   match(CallStaticJava);
9495   predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9496   effect(USE meth);
9497 
9498   size(8);
9499   ins_cost(CALL_COST);
9500   format %{ "CALL,static  ; NOP ==> " %}
9501   ins_encode( Java_Static_Call( meth ), call_epilog );
9502   ins_pc_relative(1);
9503   ins_pipe(simple_call);
9504 %}
9505 
9506 // Call Java Static Instruction (method handle version)
9507 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9508   match(CallStaticJava);
9509   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9510   effect(USE meth, KILL l7_mh_SP_save);
9511 
9512   size(8);
9513   ins_cost(CALL_COST);
9514   format %{ "CALL,static/MethodHandle" %}
9515   ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9516   ins_pc_relative(1);
9517   ins_pipe(simple_call);
9518 %}
9519 
9520 // Call Java Dynamic Instruction
9521 instruct CallDynamicJavaDirect( method meth ) %{
9522   match(CallDynamicJava);
9523   effect(USE meth);
9524 
9525   ins_cost(CALL_COST);
9526   format %{ "SET    (empty),R_G5\n\t"
9527             "CALL,dynamic  ; NOP ==> " %}
9528   ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9529   ins_pc_relative(1);
9530   ins_pipe(call);
9531 %}
9532 
9533 // Call Runtime Instruction
9534 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9535   match(CallRuntime);
9536   effect(USE meth, KILL l7);
9537   ins_cost(CALL_COST);
9538   format %{ "CALL,runtime" %}
9539   ins_encode( Java_To_Runtime( meth ),
9540               call_epilog, adjust_long_from_native_call );
9541   ins_pc_relative(1);
9542   ins_pipe(simple_call);
9543 %}
9544 
9545 // Call runtime without safepoint - same as CallRuntime
9546 instruct CallLeafDirect(method meth, l7RegP l7) %{
9547   match(CallLeaf);
9548   effect(USE meth, KILL l7);
9549   ins_cost(CALL_COST);
9550   format %{ "CALL,runtime leaf" %}
9551   ins_encode( Java_To_Runtime( meth ),
9552               call_epilog,
9553               adjust_long_from_native_call );
9554   ins_pc_relative(1);
9555   ins_pipe(simple_call);
9556 %}
9557 
9558 // Call runtime without safepoint - same as CallLeaf
9559 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9560   match(CallLeafNoFP);
9561   effect(USE meth, KILL l7);
9562   ins_cost(CALL_COST);
9563   format %{ "CALL,runtime leaf nofp" %}
9564   ins_encode( Java_To_Runtime( meth ),
9565               call_epilog,
9566               adjust_long_from_native_call );
9567   ins_pc_relative(1);
9568   ins_pipe(simple_call);
9569 %}
9570 
9571 // Tail Call; Jump from runtime stub to Java code.
9572 // Also known as an 'interprocedural jump'.
9573 // Target of jump will eventually return to caller.
9574 // TailJump below removes the return address.
9575 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9576   match(TailCall jump_target method_oop );
9577 
9578   ins_cost(CALL_COST);
9579   format %{ "Jmp     $jump_target  ; NOP \t! $method_oop holds method oop" %}
9580   ins_encode(form_jmpl(jump_target));
9581   ins_pipe(tail_call);
9582 %}
9583 
9584 
9585 // Return Instruction
9586 instruct Ret() %{
9587   match(Return);
9588 
9589   // The epilogue node did the ret already.
9590   size(0);
9591   format %{ "! return" %}
9592   ins_encode();
9593   ins_pipe(empty);
9594 %}
9595 
9596 
9597 // Tail Jump; remove the return address; jump to target.
9598 // TailCall above leaves the return address around.
9599 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9600 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9601 // "restore" before this instruction (in Epilogue), we need to materialize it
9602 // in %i0.
9603 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9604   match( TailJump jump_target ex_oop );
9605   ins_cost(CALL_COST);
9606   format %{ "! discard R_O7\n\t"
9607             "Jmp     $jump_target  ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9608   ins_encode(form_jmpl_set_exception_pc(jump_target));
9609   // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9610   // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9611   // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9612   ins_pipe(tail_call);
9613 %}
9614 
9615 // Create exception oop: created by stack-crawling runtime code.
9616 // Created exception is now available to this handler, and is setup
9617 // just prior to jumping to this handler.  No code emitted.
9618 instruct CreateException( o0RegP ex_oop )
9619 %{
9620   match(Set ex_oop (CreateEx));
9621   ins_cost(0);
9622 
9623   size(0);
9624   // use the following format syntax
9625   format %{ "! exception oop is in R_O0; no code emitted" %}
9626   ins_encode();
9627   ins_pipe(empty);
9628 %}
9629 
9630 
9631 // Rethrow exception:
9632 // The exception oop will come in the first argument position.
9633 // Then JUMP (not call) to the rethrow stub code.
9634 instruct RethrowException()
9635 %{
9636   match(Rethrow);
9637   ins_cost(CALL_COST);
9638 
9639   // use the following format syntax
9640   format %{ "Jmp    rethrow_stub" %}
9641   ins_encode(enc_rethrow);
9642   ins_pipe(tail_call);
9643 %}
9644 
9645 
9646 // Die now
9647 instruct ShouldNotReachHere( )
9648 %{
9649   match(Halt);
9650   ins_cost(CALL_COST);
9651 
9652   size(4);
9653   // Use the following format syntax
9654   format %{ "ILLTRAP   ; ShouldNotReachHere" %}
9655   ins_encode( form2_illtrap() );
9656   ins_pipe(tail_call);
9657 %}
9658 
9659 // ============================================================================
9660 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary superklass
9661 // array for an instance of the superklass.  Set a hidden internal cache on a
9662 // hit (cache is checked with exposed code in gen_subtype_check()).  Return
9663 // not zero for a miss or zero for a hit.  The encoding ALSO sets flags.
9664 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9665   match(Set index (PartialSubtypeCheck sub super));
9666   effect( KILL pcc, KILL o7 );
9667   ins_cost(DEFAULT_COST*10);
9668   format %{ "CALL   PartialSubtypeCheck\n\tNOP" %}
9669   ins_encode( enc_PartialSubtypeCheck() );
9670   ins_pipe(partial_subtype_check_pipe);
9671 %}
9672 
9673 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9674   match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9675   effect( KILL idx, KILL o7 );
9676   ins_cost(DEFAULT_COST*10);
9677   format %{ "CALL   PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9678   ins_encode( enc_PartialSubtypeCheck() );
9679   ins_pipe(partial_subtype_check_pipe);
9680 %}
9681 
9682 
9683 // ============================================================================
9684 // inlined locking and unlocking
9685 
9686 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9687   match(Set pcc (FastLock object box));
9688 
9689   effect(KILL scratch, TEMP scratch2);
9690   ins_cost(100);
9691 
9692   format %{ "FASTLOCK  $object, $box; KILL $scratch, $scratch2, $box" %}
9693   ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9694   ins_pipe(long_memory_op);
9695 %}
9696 
9697 
9698 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9699   match(Set pcc (FastUnlock object box));
9700   effect(KILL scratch, TEMP scratch2);
9701   ins_cost(100);
9702 
9703   format %{ "FASTUNLOCK  $object, $box; KILL $scratch, $scratch2, $box" %}
9704   ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9705   ins_pipe(long_memory_op);
9706 %}
9707 
9708 // Count and Base registers are fixed because the allocator cannot
9709 // kill unknown registers.  The encodings are generic.
9710 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9711   match(Set dummy (ClearArray cnt base));
9712   effect(TEMP temp, KILL ccr);
9713   ins_cost(300);
9714   format %{ "MOV    $cnt,$temp\n"
9715     "loop:   SUBcc  $temp,8,$temp\t! Count down a dword of bytes\n"
9716     "        BRge   loop\t\t! Clearing loop\n"
9717     "        STX    G0,[$base+$temp]\t! delay slot" %}
9718   ins_encode( enc_Clear_Array(cnt, base, temp) );
9719   ins_pipe(long_memory_op);
9720 %}
9721 
9722 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9723                         o7RegI tmp, flagsReg ccr) %{
9724   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9725   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9726   ins_cost(300);
9727   format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp" %}
9728   ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
9729   ins_pipe(long_memory_op);
9730 %}
9731 
9732 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9733                        o7RegI tmp, flagsReg ccr) %{
9734   match(Set result (StrEquals (Binary str1 str2) cnt));
9735   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9736   ins_cost(300);
9737   format %{ "String Equals $str1,$str2,$cnt -> $result   // KILL $tmp" %}
9738   ins_encode( enc_String_Equals(str1, str2, cnt, result) );
9739   ins_pipe(long_memory_op);
9740 %}
9741 
9742 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9743                       o7RegI tmp2, flagsReg ccr) %{
9744   match(Set result (AryEq ary1 ary2));
9745   effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9746   ins_cost(300);
9747   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
9748   ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9749   ins_pipe(long_memory_op);
9750 %}
9751 
9752 
9753 //---------- Zeros Count Instructions ------------------------------------------
9754 
9755 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9756   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
9757   match(Set dst (CountLeadingZerosI src));
9758   effect(TEMP dst, TEMP tmp, KILL cr);
9759 
9760   // x |= (x >> 1);
9761   // x |= (x >> 2);
9762   // x |= (x >> 4);
9763   // x |= (x >> 8);
9764   // x |= (x >> 16);
9765   // return (WORDBITS - popc(x));
9766   format %{ "SRL     $src,1,$tmp\t! count leading zeros (int)\n\t"
9767             "SRL     $src,0,$dst\t! 32-bit zero extend\n\t"
9768             "OR      $dst,$tmp,$dst\n\t"
9769             "SRL     $dst,2,$tmp\n\t"
9770             "OR      $dst,$tmp,$dst\n\t"
9771             "SRL     $dst,4,$tmp\n\t"
9772             "OR      $dst,$tmp,$dst\n\t"
9773             "SRL     $dst,8,$tmp\n\t"
9774             "OR      $dst,$tmp,$dst\n\t"
9775             "SRL     $dst,16,$tmp\n\t"
9776             "OR      $dst,$tmp,$dst\n\t"
9777             "POPC    $dst,$dst\n\t"
9778             "MOV     32,$tmp\n\t"
9779             "SUB     $tmp,$dst,$dst" %}
9780   ins_encode %{
9781     Register Rdst = $dst$$Register;
9782     Register Rsrc = $src$$Register;
9783     Register Rtmp = $tmp$$Register;
9784     __ srl(Rsrc, 1,    Rtmp);
9785     __ srl(Rsrc, 0,    Rdst);
9786     __ or3(Rdst, Rtmp, Rdst);
9787     __ srl(Rdst, 2,    Rtmp);
9788     __ or3(Rdst, Rtmp, Rdst);
9789     __ srl(Rdst, 4,    Rtmp);
9790     __ or3(Rdst, Rtmp, Rdst);
9791     __ srl(Rdst, 8,    Rtmp);
9792     __ or3(Rdst, Rtmp, Rdst);
9793     __ srl(Rdst, 16,   Rtmp);
9794     __ or3(Rdst, Rtmp, Rdst);
9795     __ popc(Rdst, Rdst);
9796     __ mov(BitsPerInt, Rtmp);
9797     __ sub(Rtmp, Rdst, Rdst);
9798   %}
9799   ins_pipe(ialu_reg);
9800 %}
9801 
9802 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
9803   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
9804   match(Set dst (CountLeadingZerosL src));
9805   effect(TEMP dst, TEMP tmp, KILL cr);
9806 
9807   // x |= (x >> 1);
9808   // x |= (x >> 2);
9809   // x |= (x >> 4);
9810   // x |= (x >> 8);
9811   // x |= (x >> 16);
9812   // x |= (x >> 32);
9813   // return (WORDBITS - popc(x));
9814   format %{ "SRLX    $src,1,$tmp\t! count leading zeros (long)\n\t"
9815             "OR      $src,$tmp,$dst\n\t"
9816             "SRLX    $dst,2,$tmp\n\t"
9817             "OR      $dst,$tmp,$dst\n\t"
9818             "SRLX    $dst,4,$tmp\n\t"
9819             "OR      $dst,$tmp,$dst\n\t"
9820             "SRLX    $dst,8,$tmp\n\t"
9821             "OR      $dst,$tmp,$dst\n\t"
9822             "SRLX    $dst,16,$tmp\n\t"
9823             "OR      $dst,$tmp,$dst\n\t"
9824             "SRLX    $dst,32,$tmp\n\t"
9825             "OR      $dst,$tmp,$dst\n\t"
9826             "POPC    $dst,$dst\n\t"
9827             "MOV     64,$tmp\n\t"
9828             "SUB     $tmp,$dst,$dst" %}
9829   ins_encode %{
9830     Register Rdst = $dst$$Register;
9831     Register Rsrc = $src$$Register;
9832     Register Rtmp = $tmp$$Register;
9833     __ srlx(Rsrc, 1,    Rtmp);
9834     __ or3( Rsrc, Rtmp, Rdst);
9835     __ srlx(Rdst, 2,    Rtmp);
9836     __ or3( Rdst, Rtmp, Rdst);
9837     __ srlx(Rdst, 4,    Rtmp);
9838     __ or3( Rdst, Rtmp, Rdst);
9839     __ srlx(Rdst, 8,    Rtmp);
9840     __ or3( Rdst, Rtmp, Rdst);
9841     __ srlx(Rdst, 16,   Rtmp);
9842     __ or3( Rdst, Rtmp, Rdst);
9843     __ srlx(Rdst, 32,   Rtmp);
9844     __ or3( Rdst, Rtmp, Rdst);
9845     __ popc(Rdst, Rdst);
9846     __ mov(BitsPerLong, Rtmp);
9847     __ sub(Rtmp, Rdst, Rdst);
9848   %}
9849   ins_pipe(ialu_reg);
9850 %}
9851 
9852 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9853   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
9854   match(Set dst (CountTrailingZerosI src));
9855   effect(TEMP dst, KILL cr);
9856 
9857   // return popc(~x & (x - 1));
9858   format %{ "SUB     $src,1,$dst\t! count trailing zeros (int)\n\t"
9859             "ANDN    $dst,$src,$dst\n\t"
9860             "SRL     $dst,R_G0,$dst\n\t"
9861             "POPC    $dst,$dst" %}
9862   ins_encode %{
9863     Register Rdst = $dst$$Register;
9864     Register Rsrc = $src$$Register;
9865     __ sub(Rsrc, 1, Rdst);
9866     __ andn(Rdst, Rsrc, Rdst);
9867     __ srl(Rdst, G0, Rdst);
9868     __ popc(Rdst, Rdst);
9869   %}
9870   ins_pipe(ialu_reg);
9871 %}
9872 
9873 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9874   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
9875   match(Set dst (CountTrailingZerosL src));
9876   effect(TEMP dst, KILL cr);
9877 
9878   // return popc(~x & (x - 1));
9879   format %{ "SUB     $src,1,$dst\t! count trailing zeros (long)\n\t"
9880             "ANDN    $dst,$src,$dst\n\t"
9881             "POPC    $dst,$dst" %}
9882   ins_encode %{
9883     Register Rdst = $dst$$Register;
9884     Register Rsrc = $src$$Register;
9885     __ sub(Rsrc, 1, Rdst);
9886     __ andn(Rdst, Rsrc, Rdst);
9887     __ popc(Rdst, Rdst);
9888   %}
9889   ins_pipe(ialu_reg);
9890 %}
9891 
9892 
9893 //---------- Population Count Instructions -------------------------------------
9894 
9895 instruct popCountI(iRegI dst, iRegI src) %{
9896   predicate(UsePopCountInstruction);
9897   match(Set dst (PopCountI src));
9898 
9899   format %{ "POPC   $src, $dst" %}
9900   ins_encode %{
9901     __ popc($src$$Register, $dst$$Register);
9902   %}
9903   ins_pipe(ialu_reg);
9904 %}
9905 
9906 // Note: Long.bitCount(long) returns an int.
9907 instruct popCountL(iRegI dst, iRegL src) %{
9908   predicate(UsePopCountInstruction);
9909   match(Set dst (PopCountL src));
9910 
9911   format %{ "POPC   $src, $dst" %}
9912   ins_encode %{
9913     __ popc($src$$Register, $dst$$Register);
9914   %}
9915   ins_pipe(ialu_reg);
9916 %}
9917 
9918 
9919 // ============================================================================
9920 //------------Bytes reverse--------------------------------------------------
9921 
9922 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9923   match(Set dst (ReverseBytesI src));
9924 
9925   // Op cost is artificially doubled to make sure that load or store
9926   // instructions are preferred over this one which requires a spill
9927   // onto a stack slot.
9928   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9929   format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
9930 
9931   ins_encode %{
9932     __ set($src$$disp + STACK_BIAS, O7);
9933     __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9934   %}
9935   ins_pipe( iload_mem );
9936 %}
9937 
9938 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9939   match(Set dst (ReverseBytesL src));
9940 
9941   // Op cost is artificially doubled to make sure that load or store
9942   // instructions are preferred over this one which requires a spill
9943   // onto a stack slot.
9944   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9945   format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
9946 
9947   ins_encode %{
9948     __ set($src$$disp + STACK_BIAS, O7);
9949     __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9950   %}
9951   ins_pipe( iload_mem );
9952 %}
9953 
9954 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
9955   match(Set dst (ReverseBytesUS src));
9956 
9957   // Op cost is artificially doubled to make sure that load or store
9958   // instructions are preferred over this one which requires a spill
9959   // onto a stack slot.
9960   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9961   format %{ "LDUHA  $src, $dst\t!asi=primary_little\n\t" %}
9962 
9963   ins_encode %{
9964     // the value was spilled as an int so bias the load
9965     __ set($src$$disp + STACK_BIAS + 2, O7);
9966     __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9967   %}
9968   ins_pipe( iload_mem );
9969 %}
9970 
9971 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
9972   match(Set dst (ReverseBytesS src));
9973 
9974   // Op cost is artificially doubled to make sure that load or store
9975   // instructions are preferred over this one which requires a spill
9976   // onto a stack slot.
9977   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9978   format %{ "LDSHA  $src, $dst\t!asi=primary_little\n\t" %}
9979 
9980   ins_encode %{
9981     // the value was spilled as an int so bias the load
9982     __ set($src$$disp + STACK_BIAS + 2, O7);
9983     __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9984   %}
9985   ins_pipe( iload_mem );
9986 %}
9987 
9988 // Load Integer reversed byte order
9989 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
9990   match(Set dst (ReverseBytesI (LoadI src)));
9991 
9992   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9993   size(4);
9994   format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
9995 
9996   ins_encode %{
9997     __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9998   %}
9999   ins_pipe(iload_mem);
10000 %}
10001 
10002 // Load Long - aligned and reversed
10003 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10004   match(Set dst (ReverseBytesL (LoadL src)));
10005 
10006   ins_cost(MEMORY_REF_COST);
10007   size(4);
10008   format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
10009 
10010   ins_encode %{
10011     __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10012   %}
10013   ins_pipe(iload_mem);
10014 %}
10015 
10016 // Load unsigned short / char reversed byte order
10017 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10018   match(Set dst (ReverseBytesUS (LoadUS src)));
10019 
10020   ins_cost(MEMORY_REF_COST);
10021   size(4);
10022   format %{ "LDUHA  $src, $dst\t!asi=primary_little" %}
10023 
10024   ins_encode %{
10025     __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10026   %}
10027   ins_pipe(iload_mem);
10028 %}
10029 
10030 // Load short reversed byte order
10031 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10032   match(Set dst (ReverseBytesS (LoadS src)));
10033 
10034   ins_cost(MEMORY_REF_COST);
10035   size(4);
10036   format %{ "LDSHA  $src, $dst\t!asi=primary_little" %}
10037 
10038   ins_encode %{
10039     __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10040   %}
10041   ins_pipe(iload_mem);
10042 %}
10043 
10044 // Store Integer reversed byte order
10045 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10046   match(Set dst (StoreI dst (ReverseBytesI src)));
10047 
10048   ins_cost(MEMORY_REF_COST);
10049   size(4);
10050   format %{ "STWA   $src, $dst\t!asi=primary_little" %}
10051 
10052   ins_encode %{
10053     __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10054   %}
10055   ins_pipe(istore_mem_reg);
10056 %}
10057 
10058 // Store Long reversed byte order
10059 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10060   match(Set dst (StoreL dst (ReverseBytesL src)));
10061 
10062   ins_cost(MEMORY_REF_COST);
10063   size(4);
10064   format %{ "STXA   $src, $dst\t!asi=primary_little" %}
10065 
10066   ins_encode %{
10067     __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10068   %}
10069   ins_pipe(istore_mem_reg);
10070 %}
10071 
10072 // Store unsighed short/char reversed byte order
10073 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10074   match(Set dst (StoreC dst (ReverseBytesUS src)));
10075 
10076   ins_cost(MEMORY_REF_COST);
10077   size(4);
10078   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
10079 
10080   ins_encode %{
10081     __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10082   %}
10083   ins_pipe(istore_mem_reg);
10084 %}
10085 
10086 // Store short reversed byte order
10087 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10088   match(Set dst (StoreC dst (ReverseBytesS src)));
10089 
10090   ins_cost(MEMORY_REF_COST);
10091   size(4);
10092   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
10093 
10094   ins_encode %{
10095     __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10096   %}
10097   ins_pipe(istore_mem_reg);
10098 %}
10099 
10100 //----------PEEPHOLE RULES-----------------------------------------------------
10101 // These must follow all instruction definitions as they use the names
10102 // defined in the instructions definitions.
10103 //
10104 // peepmatch ( root_instr_name [preceding_instruction]* );
10105 //
10106 // peepconstraint %{
10107 // (instruction_number.operand_name relational_op instruction_number.operand_name
10108 //  [, ...] );
10109 // // instruction numbers are zero-based using left to right order in peepmatch
10110 //
10111 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
10112 // // provide an instruction_number.operand_name for each operand that appears
10113 // // in the replacement instruction's match rule
10114 //
10115 // ---------VM FLAGS---------------------------------------------------------
10116 //
10117 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10118 //
10119 // Each peephole rule is given an identifying number starting with zero and
10120 // increasing by one in the order seen by the parser.  An individual peephole
10121 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10122 // on the command-line.
10123 //
10124 // ---------CURRENT LIMITATIONS----------------------------------------------
10125 //
10126 // Only match adjacent instructions in same basic block
10127 // Only equality constraints
10128 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10129 // Only one replacement instruction
10130 //
10131 // ---------EXAMPLE----------------------------------------------------------
10132 //
10133 // // pertinent parts of existing instructions in architecture description
10134 // instruct movI(eRegI dst, eRegI src) %{
10135 //   match(Set dst (CopyI src));
10136 // %}
10137 //
10138 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10139 //   match(Set dst (AddI dst src));
10140 //   effect(KILL cr);
10141 // %}
10142 //
10143 // // Change (inc mov) to lea
10144 // peephole %{
10145 //   // increment preceeded by register-register move
10146 //   peepmatch ( incI_eReg movI );
10147 //   // require that the destination register of the increment
10148 //   // match the destination register of the move
10149 //   peepconstraint ( 0.dst == 1.dst );
10150 //   // construct a replacement instruction that sets
10151 //   // the destination to ( move's source register + one )
10152 //   peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10153 // %}
10154 //
10155 
10156 // // Change load of spilled value to only a spill
10157 // instruct storeI(memory mem, eRegI src) %{
10158 //   match(Set mem (StoreI mem src));
10159 // %}
10160 //
10161 // instruct loadI(eRegI dst, memory mem) %{
10162 //   match(Set dst (LoadI mem));
10163 // %}
10164 //
10165 // peephole %{
10166 //   peepmatch ( loadI storeI );
10167 //   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10168 //   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10169 // %}
10170 
10171 //----------SMARTSPILL RULES---------------------------------------------------
10172 // These must follow all instruction definitions as they use the names
10173 // defined in the instructions definitions.
10174 //
10175 // SPARC will probably not have any of these rules due to RISC instruction set.
10176 
10177 //----------PIPELINE-----------------------------------------------------------
10178 // Rules which define the behavior of the target architectures pipeline.