src/cpu/sparc/vm/sparc.ad
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*** old/src/cpu/sparc/vm/sparc.ad	Fri Jul 15 18:49:42 2011
--- new/src/cpu/sparc/vm/sparc.ad	Fri Jul 15 18:49:42 2011

*** 1691,1701 **** --- 1691,1700 ---- } #endif void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { MacroAssembler _masm(&cbuf); Label L; Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); Register temp_reg = G3; assert( G5_ic_reg != temp_reg, "conflicting registers" ); // Load klass from receiver
*** 2313,2379 **** --- 2312,2341 ---- MacroAssembler _masm(&cbuf); __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); __ delayed()->nop(); %} ! enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ ! enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ MacroAssembler _masm(&cbuf); ! Label &L = *($labl$$label); ! Label* L = $labl$$label; Assembler::Predict predict_taken = ! cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; ! __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); __ delayed()->nop(); %} ! enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ ! enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ MacroAssembler _masm(&cbuf); ! Label &L = *($labl$$label); ! Label* L = $labl$$label; Assembler::Predict predict_taken = ! cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; ! __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); ! __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); __ delayed()->nop(); %} enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ MacroAssembler _masm(&cbuf); Label &L = *($labl$$label); Assembler::Predict predict_taken = cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); __ delayed()->nop(); %} enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ MacroAssembler _masm(&cbuf); Label &L = *($labl$$label); Assembler::Predict predict_taken = cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); __ delayed()->nop(); %} enc_class enc_ba( Label labl ) %{ MacroAssembler _masm(&cbuf); Label &L = *($labl$$label); __ ba(false, L); __ delayed()->nop(); %} enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ MacroAssembler _masm(&cbuf); Label &L = *$labl$$label; Assembler::Predict predict_taken = cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); __ delayed()->nop(); %} enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ int op = (Assembler::arith_op << 30) | ($dst$$reg << 25) | (Assembler::movcc_op3 << 19) | (1 << 18) | // cc2 bit for 'icc'
*** 2984,2994 **** --- 2946,2956 ---- __ cmp(str1_reg, str2_reg); //same char[] ? __ brx(Assembler::equal, true, Assembler::pn, Ldone); __ delayed()->add(G0, 1, result_reg); ! __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); ! __ bpr(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); __ delayed()->add(G0, 1, result_reg); // count == 0 //rename registers Register limit_reg = cnt_reg; Register chr1_reg = result_reg;
*** 3004,3014 **** --- 2966,2976 ---- __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count // Compare char[] arrays aligned to 4 bytes. __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, chr1_reg, chr2_reg, Ldone); - __ ba(false,Ldone); __ delayed()->add(G0, 1, result_reg); // char by char compare __ bind(Lchar); __ add(str1_reg, limit_reg, str1_reg);
*** 3063,3073 **** --- 3025,3035 ---- // return false if the two arrays are not equal length __ cmp(tmp1_reg, tmp2_reg); __ br(Assembler::notEqual, true, Assembler::pn, Ldone); __ delayed()->mov(G0, result_reg); // not equal ! __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); ! __ bpr(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal // load array addresses __ add(ary1_reg, base_offset, ary1_reg); __ add(ary2_reg, base_offset, ary2_reg);
*** 9230,9242 **** --- 9192,9206 ---- effect(USE labl); size(8); ins_cost(BRANCH_COST); format %{ "BA $labl" %} // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond ! opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); ! ins_encode( enc_ba( labl ) ); + ins_encode %{ ! Label* L = $labl$$label; ! __ ba(*L); + __ delayed()->nop(); + %} ins_pc_relative(1); ins_pipe(br); %} // Conditional Direct Branch
*** 9312,9323 **** --- 9276,9293 ---- effect(USE labl); size(8); ins_cost(BRANCH_COST); format %{ "BP$cmp $pcc,$labl" %} // Prim = bits 24-22, Secnd = bits 31-30 ! ins_encode( enc_bpx( labl, cmp, pcc ) ); + ins_encode %{ ! Label* L = $labl$$label; + Assembler::Predict predict_taken = + cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; + + __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); + __ delayed()->nop(); + %} ins_pc_relative(1); ins_pipe(br_cc); %} instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
*** 9325,9336 **** --- 9295,9312 ---- effect(USE labl); size(8); ins_cost(BRANCH_COST); format %{ "FBP$cmp $fcc,$labl" %} // Prim = bits 24-22, Secnd = bits 31-30 ! ins_encode( enc_fbp( labl, cmp, fcc ) ); + ins_encode %{ ! Label* L = $labl$$label; + Assembler::Predict predict_taken = + cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; + + __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); + __ delayed()->nop(); + %} ins_pc_relative(1); ins_pipe(br_fcc); %} instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
*** 9385,9396 **** --- 9361,9378 ---- effect(USE labl); size(8); ins_cost(BRANCH_COST); format %{ "BP$cmp $xcc,$labl" %} // Prim = bits 24-22, Secnd = bits 31-30 ! ins_encode( enc_bpl( labl, cmp, xcc ) ); + ins_encode %{ ! Label* L = $labl$$label; + Assembler::Predict predict_taken = + cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; + + __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); + __ delayed()->nop(); + %} ins_pc_relative(1); ins_pipe(br_cc); %} // Manifest a CmpL3 result in an integer register. Very painful.
*** 9705,9715 **** --- 9687,9696 ---- match(Set pcc (FastLock object box)); effect(KILL scratch, TEMP scratch2); ins_cost(100); size(4*112); // conservative overestimation ... format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} ins_encode( Fast_Lock(object, box, scratch, scratch2) ); ins_pipe(long_memory_op); %}
*** 9717,9727 **** --- 9698,9707 ---- instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ match(Set pcc (FastUnlock object box)); effect(KILL scratch, TEMP scratch2); ins_cost(100); size(4*120); // conservative overestimation ... format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); ins_pipe(long_memory_op); %}

src/cpu/sparc/vm/sparc.ad
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