1 /* 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP 26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP 27 28 #include "runtime/globals_extension.hpp" 29 #include "runtime/vm_version.hpp" 30 31 class VM_Version: public Abstract_VM_Version { 32 protected: 33 enum Feature_Flag { 34 v8_instructions = 0, 35 hardware_mul32 = 1, 36 hardware_div32 = 2, 37 hardware_fsmuld = 3, 38 hardware_popc = 4, 39 v9_instructions = 5, 40 vis1_instructions = 6, 41 vis2_instructions = 7, 42 sun4v_instructions = 8, 43 blk_init_instructions = 9, 44 fmaf_instructions = 10, 45 fmau_instructions = 11, 46 vis3_instructions = 12, 47 sparc64_family = 13, 48 T_family = 14, 49 T1_model = 15, 50 cbcond_instructions = 16 51 }; 52 53 enum Feature_Flag_Set { 54 unknown_m = 0, 55 all_features_m = -1, 56 57 v8_instructions_m = 1 << v8_instructions, 58 hardware_mul32_m = 1 << hardware_mul32, 59 hardware_div32_m = 1 << hardware_div32, 60 hardware_fsmuld_m = 1 << hardware_fsmuld, 61 hardware_popc_m = 1 << hardware_popc, 62 v9_instructions_m = 1 << v9_instructions, 63 vis1_instructions_m = 1 << vis1_instructions, 64 vis2_instructions_m = 1 << vis2_instructions, 65 sun4v_m = 1 << sun4v_instructions, 66 blk_init_instructions_m = 1 << blk_init_instructions, 67 fmaf_instructions_m = 1 << fmaf_instructions, 68 fmau_instructions_m = 1 << fmau_instructions, 69 vis3_instructions_m = 1 << vis3_instructions, 70 sparc64_family_m = 1 << sparc64_family, 71 T_family_m = 1 << T_family, 72 T1_model_m = 1 << T1_model, 73 cbcond_instructions_m = 1 << cbcond_instructions, 74 75 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, 76 generic_v9_m = generic_v8_m | v9_instructions_m, 77 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, 78 79 // Temporary until we have something more accurate 80 niagara1_unique_m = sun4v_m, 81 niagara1_m = generic_v9_m | niagara1_unique_m 82 }; 83 84 static int _features; 85 static const char* _features_str; 86 87 static void print_features(); 88 static int determine_features(); 89 static int platform_features(int features); 90 91 // Returns true if the platform is in the niagara line (T series) 92 static bool is_T_family(int features) { return (features & T_family_m) != 0; } 93 static bool is_niagara() { return is_T_family(_features); } 94 DEBUG_ONLY( static bool is_niagara(int features) { return (features & sun4v_m) != 0; } ) 95 96 // Returns true if it is niagara1 (T1). 97 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); } 98 99 static int maximum_niagara1_processor_count() { return 32; } 100 101 public: 102 // Initialization 103 static void initialize(); 104 105 // Instruction support 106 static bool has_v8() { return (_features & v8_instructions_m) != 0; } 107 static bool has_v9() { return (_features & v9_instructions_m) != 0; } 108 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; } 109 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; } 110 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; } 111 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } 112 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } 113 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } 114 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } 115 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } 116 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; } 117 118 static bool supports_compare_and_exchange() 119 { return has_v9(); } 120 121 // Returns true if the platform is in the niagara line (T series) 122 // and newer than the niagara1. 123 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); } 124 125 // Fujitsu SPARC64 126 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } 127 128 static bool is_sun4v() { return (_features & sun4v_m) != 0; } 129 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); } 130 131 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } 132 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } 133 // T4 and newer Sparc have fast RDPC instruction. 134 static bool has_fast_rdpc() { return is_niagara_plus() && has_cbcond(); } 135 136 static const char* cpu_features() { return _features_str; } 137 138 static intx L1_data_cache_line_size() { 139 return 64; // default prefetch block size on sparc 140 } 141 142 // Prefetch 143 static intx prefetch_copy_interval_in_bytes() { 144 intx interval = PrefetchCopyIntervalInBytes; 145 return interval >= 0 ? interval : (has_v9() ? 512 : 0); 146 } 147 static intx prefetch_scan_interval_in_bytes() { 148 intx interval = PrefetchScanIntervalInBytes; 149 return interval >= 0 ? interval : (has_v9() ? 512 : 0); 150 } 151 static intx prefetch_fields_ahead() { 152 intx count = PrefetchFieldsAhead; 153 return count >= 0 ? count : (is_ultra3() ? 1 : 0); 154 } 155 156 static intx allocate_prefetch_distance() { 157 // This method should be called before allocate_prefetch_style(). 158 intx count = AllocatePrefetchDistance; 159 if (count < 0) { // default is not defined ? 160 count = 512; 161 } 162 return count; 163 } 164 static intx allocate_prefetch_style() { 165 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 166 // Return 0 if AllocatePrefetchDistance was not defined. 167 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; 168 } 169 170 // Legacy 171 static bool v8_instructions_work() { return has_v8() && !has_v9(); } 172 static bool v9_instructions_work() { return has_v9(); } 173 174 // Assembler testing 175 static void allow_all(); 176 static void revert(); 177 178 // Override the Abstract_VM_Version implementation. 179 static uint page_size_count() { return is_sun4v() ? 4 : 2; } 180 181 // Calculates the number of parallel threads 182 static unsigned int calc_parallel_worker_threads(); 183 }; 184 185 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP