src/cpu/sparc/vm/vm_version_sparc.hpp
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*** old/src/cpu/sparc/vm/vm_version_sparc.hpp	Fri Jul 15 18:49:46 2011
--- new/src/cpu/sparc/vm/vm_version_sparc.hpp	Fri Jul 15 18:49:46 2011

*** 44,54 **** --- 44,55 ---- fmaf_instructions = 10, fmau_instructions = 11, vis3_instructions = 12, sparc64_family = 13, T_family = 14, ! T1_model = 15, + cbcond_instructions = 16 }; enum Feature_Flag_Set { unknown_m = 0, all_features_m = -1,
*** 67,76 **** --- 68,78 ---- fmau_instructions_m = 1 << fmau_instructions, vis3_instructions_m = 1 << vis3_instructions, sparc64_family_m = 1 << sparc64_family, T_family_m = 1 << T_family, T1_model_m = 1 << T1_model, + cbcond_instructions_m = 1 << cbcond_instructions, generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, generic_v9_m = generic_v8_m | v9_instructions_m, ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
*** 109,132 **** --- 111,139 ---- static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } + static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; } static bool supports_compare_and_exchange() { return has_v9(); } static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m; } static bool is_sun4v() { return (_features & sun4v_m) != 0; } // Returns true if the platform is in the niagara line (T series) // and newer than the niagara1. static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); } + // Fujitsu SPARC64 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } + static bool is_sun4v() { return (_features & sun4v_m) != 0; } + static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); } + static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } + // T4 and newer Sparc have fast RDPC instruction. + static bool has_fast_rdpc() { return is_niagara_plus() && has_cbcond(); } static const char* cpu_features() { return _features_str; } static intx L1_data_cache_line_size() { return 64; // default prefetch block size on sparc

src/cpu/sparc/vm/vm_version_sparc.hpp
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