1 //
2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // Block initializing store
475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2
476
477 // tertiary op of a LoadP or StoreP encoding
478 #define REGP_OP true
479
480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
482 static Register reg_to_register_object(int register_encoding);
483
484 // Used by the DFA in dfa_sparc.cpp.
485 // Check for being able to use a V9 branch-on-register. Requires a
486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
487 // extended. Doesn't work following an integer ADD, for example, because of
488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
490 // replace them with zero, which could become sign-extension in a different OS
491 // release. There's no obvious reason why an interrupt will ever fill these
492 // bits with non-zero junk (the registers are reloaded with standard LD
493 // instructions which either zero-fill or sign-fill).
494 bool can_branch_register( Node *bol, Node *cmp ) {
495 if( !BranchOnRegister ) return false;
496 #ifdef _LP64
497 if( cmp->Opcode() == Op_CmpP )
498 return true; // No problems with pointer compares
499 #endif
500 if( cmp->Opcode() == Op_CmpL )
501 return true; // No problems with long compares
502
503 if( !SparcV9RegsHiBitsZero ) return false;
504 if( bol->as_Bool()->_test._test != BoolTest::ne &&
505 bol->as_Bool()->_test._test != BoolTest::eq )
506 return false;
507
508 // Check for comparing against a 'safe' value. Any operation which
509 // clears out the high word is safe. Thus, loads and certain shifts
510 // are safe, as are non-negative constants. Any operation which
511 // preserves zero bits in the high word is safe as long as each of its
512 // inputs are safe. Thus, phis and bitwise booleans are safe if their
513 // inputs are safe. At present, the only important case to recognize
514 // seems to be loads. Constants should fold away, and shifts &
515 // logicals can use the 'cc' forms.
516 Node *x = cmp->in(1);
517 if( x->is_Load() ) return true;
518 if( x->is_Phi() ) {
519 for( uint i = 1; i < x->req(); i++ )
520 if( !x->in(i)->is_Load() )
521 return false;
522 return true;
523 }
524 return false;
525 }
526
527 // ****************************************************************************
528
529 // REQUIRED FUNCTIONALITY
530
531 // !!!!! Special hack to get all type of calls to specify the byte offset
532 // from the start of the call to the point where the return address
533 // will point.
534 // The "return address" is the address of the call instruction, plus 8.
535
536 int MachCallStaticJavaNode::ret_addr_offset() {
537 int offset = NativeCall::instruction_size; // call; delay slot
538 if (_method_handle_invoke)
539 offset += 4; // restore SP
540 return offset;
541 }
542
543 int MachCallDynamicJavaNode::ret_addr_offset() {
544 int vtable_index = this->_vtable_index;
545 if (vtable_index < 0) {
546 // must be invalid_vtable_index, not nonvirtual_vtable_index
547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
548 return (NativeMovConstReg::instruction_size +
549 NativeCall::instruction_size); // sethi; setlo; call; delay slot
550 } else {
551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
554 int klass_load_size;
555 if (UseCompressedOops) {
556 assert(Universe::heap() != NULL, "java heap should be initialized");
557 if (Universe::narrow_oop_base() == NULL)
558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
559 else
560 klass_load_size = 3*BytesPerInstWord;
561 } else {
562 klass_load_size = 1*BytesPerInstWord;
563 }
564 if( Assembler::is_simm13(v_off) ) {
565 return klass_load_size +
566 (2*BytesPerInstWord + // ld_ptr, ld_ptr
567 NativeCall::instruction_size); // call; delay slot
568 } else {
569 return klass_load_size +
570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
571 NativeCall::instruction_size); // call; delay slot
572 }
573 }
574 }
575
576 int MachCallRuntimeNode::ret_addr_offset() {
577 #ifdef _LP64
578 if (MacroAssembler::is_far_target(entry_point())) {
579 return NativeFarCall::instruction_size;
580 } else {
581 return NativeCall::instruction_size;
582 }
583 #else
584 return NativeCall::instruction_size; // call; delay slot
585 #endif
586 }
587
588 // Indicate if the safepoint node needs the polling page as an input.
589 // Since Sparc does not have absolute addressing, it does.
590 bool SafePointNode::needs_polling_address_input() {
591 return true;
592 }
593
594 // emit an interrupt that is caught by the debugger (for debugging compiler)
595 void emit_break(CodeBuffer &cbuf) {
596 MacroAssembler _masm(&cbuf);
597 __ breakpoint_trap();
598 }
599
600 #ifndef PRODUCT
601 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
602 st->print("TA");
603 }
604 #endif
605
606 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
607 emit_break(cbuf);
608 }
609
610 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
611 return MachNode::size(ra_);
612 }
613
614 // Traceable jump
615 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
616 MacroAssembler _masm(&cbuf);
617 Register rdest = reg_to_register_object(jump_target);
618 __ JMP(rdest, 0);
619 __ delayed()->nop();
620 }
621
622 // Traceable jump and set exception pc
623 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
624 MacroAssembler _masm(&cbuf);
625 Register rdest = reg_to_register_object(jump_target);
626 __ JMP(rdest, 0);
627 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
628 }
629
630 void emit_nop(CodeBuffer &cbuf) {
631 MacroAssembler _masm(&cbuf);
632 __ nop();
633 }
634
635 void emit_illtrap(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ illtrap(0);
638 }
639
640
641 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
642 assert(n->rule() != loadUB_rule, "");
643
644 intptr_t offset = 0;
645 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
646 const Node* addr = n->get_base_and_disp(offset, adr_type);
647 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
648 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
649 assert(addr->bottom_type()->isa_oopptr() == atype, "");
650 atype = atype->add_offset(offset);
651 assert(disp32 == offset, "wrong disp32");
652 return atype->_offset;
653 }
654
655
656 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
657 assert(n->rule() != loadUB_rule, "");
658
659 intptr_t offset = 0;
660 Node* addr = n->in(2);
661 assert(addr->bottom_type()->isa_oopptr() == atype, "");
662 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
663 Node* a = addr->in(2/*AddPNode::Address*/);
664 Node* o = addr->in(3/*AddPNode::Offset*/);
665 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
666 atype = a->bottom_type()->is_ptr()->add_offset(offset);
667 assert(atype->isa_oop_ptr(), "still an oop");
668 }
669 offset = atype->is_ptr()->_offset;
670 if (offset != Type::OffsetBot) offset += disp32;
671 return offset;
672 }
673
674 static inline jdouble replicate_immI(int con, int count, int width) {
675 // Load a constant replicated "count" times with width "width"
676 int bit_width = width * 8;
677 jlong elt_val = con;
678 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
679 jlong val = elt_val;
680 for (int i = 0; i < count - 1; i++) {
681 val <<= bit_width;
682 val |= elt_val;
683 }
684 jdouble dval = *((jdouble*) &val); // coerce to double type
685 return dval;
686 }
687
688 // Standard Sparc opcode form2 field breakdown
689 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
690 f0 &= (1<<19)-1; // Mask displacement to 19 bits
691 int op = (f30 << 30) |
692 (f29 << 29) |
693 (f25 << 25) |
694 (f22 << 22) |
695 (f20 << 20) |
696 (f19 << 19) |
697 (f0 << 0);
698 cbuf.insts()->emit_int32(op);
699 }
700
701 // Standard Sparc opcode form2 field breakdown
702 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
703 f0 >>= 10; // Drop 10 bits
704 f0 &= (1<<22)-1; // Mask displacement to 22 bits
705 int op = (f30 << 30) |
706 (f25 << 25) |
707 (f22 << 22) |
708 (f0 << 0);
709 cbuf.insts()->emit_int32(op);
710 }
711
712 // Standard Sparc opcode form3 field breakdown
713 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
714 int op = (f30 << 30) |
715 (f25 << 25) |
716 (f19 << 19) |
717 (f14 << 14) |
718 (f5 << 5) |
719 (f0 << 0);
720 cbuf.insts()->emit_int32(op);
721 }
722
723 // Standard Sparc opcode form3 field breakdown
724 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
725 simm13 &= (1<<13)-1; // Mask to 13 bits
726 int op = (f30 << 30) |
727 (f25 << 25) |
728 (f19 << 19) |
729 (f14 << 14) |
730 (1 << 13) | // bit to indicate immediate-mode
731 (simm13<<0);
732 cbuf.insts()->emit_int32(op);
733 }
734
735 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
736 simm10 &= (1<<10)-1; // Mask to 10 bits
737 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
738 }
739
740 #ifdef ASSERT
741 // Helper function for VerifyOops in emit_form3_mem_reg
742 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
743 warning("VerifyOops encountered unexpected instruction:");
744 n->dump(2);
745 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
746 }
747 #endif
748
749
750 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
751 int src1_enc, int disp32, int src2_enc, int dst_enc) {
752
753 #ifdef ASSERT
754 // The following code implements the +VerifyOops feature.
755 // It verifies oop values which are loaded into or stored out of
756 // the current method activation. +VerifyOops complements techniques
757 // like ScavengeALot, because it eagerly inspects oops in transit,
758 // as they enter or leave the stack, as opposed to ScavengeALot,
759 // which inspects oops "at rest", in the stack or heap, at safepoints.
760 // For this reason, +VerifyOops can sometimes detect bugs very close
761 // to their point of creation. It can also serve as a cross-check
762 // on the validity of oop maps, when used toegether with ScavengeALot.
763
764 // It would be good to verify oops at other points, especially
765 // when an oop is used as a base pointer for a load or store.
766 // This is presently difficult, because it is hard to know when
767 // a base address is biased or not. (If we had such information,
768 // it would be easy and useful to make a two-argument version of
769 // verify_oop which unbiases the base, and performs verification.)
770
771 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
772 bool is_verified_oop_base = false;
773 bool is_verified_oop_load = false;
774 bool is_verified_oop_store = false;
775 int tmp_enc = -1;
776 if (VerifyOops && src1_enc != R_SP_enc) {
777 // classify the op, mainly for an assert check
778 int st_op = 0, ld_op = 0;
779 switch (primary) {
780 case Assembler::stb_op3: st_op = Op_StoreB; break;
781 case Assembler::sth_op3: st_op = Op_StoreC; break;
782 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
783 case Assembler::stw_op3: st_op = Op_StoreI; break;
784 case Assembler::std_op3: st_op = Op_StoreL; break;
785 case Assembler::stf_op3: st_op = Op_StoreF; break;
786 case Assembler::stdf_op3: st_op = Op_StoreD; break;
787
788 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
789 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
790 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
791 case Assembler::ldx_op3: // may become LoadP or stay LoadI
792 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
793 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
794 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
795 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
796 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
797 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
798 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
799
800 default: ShouldNotReachHere();
801 }
802 if (tertiary == REGP_OP) {
803 if (st_op == Op_StoreI) st_op = Op_StoreP;
804 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
805 else ShouldNotReachHere();
806 if (st_op) {
807 // a store
808 // inputs are (0:control, 1:memory, 2:address, 3:value)
809 Node* n2 = n->in(3);
810 if (n2 != NULL) {
811 const Type* t = n2->bottom_type();
812 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
813 }
814 } else {
815 // a load
816 const Type* t = n->bottom_type();
817 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
818 }
819 }
820
821 if (ld_op) {
822 // a Load
823 // inputs are (0:control, 1:memory, 2:address)
824 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
825 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
826 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
827 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
828 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
829 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
830 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
831 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
832 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
833 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
834 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
835 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
836 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
839 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
840 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
841 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
842 !(n->rule() == loadUB_rule)) {
843 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
844 }
845 } else if (st_op) {
846 // a Store
847 // inputs are (0:control, 1:memory, 2:address, 3:value)
848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
853 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
854 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
855 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
856 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
857 verify_oops_warning(n, n->ideal_Opcode(), st_op);
858 }
859 }
860
861 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
862 Node* addr = n->in(2);
863 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
864 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
865 if (atype != NULL) {
866 intptr_t offset = get_offset_from_base(n, atype, disp32);
867 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
868 if (offset != offset_2) {
869 get_offset_from_base(n, atype, disp32);
870 get_offset_from_base_2(n, atype, disp32);
871 }
872 assert(offset == offset_2, "different offsets");
873 if (offset == disp32) {
874 // we now know that src1 is a true oop pointer
875 is_verified_oop_base = true;
876 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
877 if( primary == Assembler::ldd_op3 ) {
878 is_verified_oop_base = false; // Cannot 'ldd' into O7
879 } else {
880 tmp_enc = dst_enc;
881 dst_enc = R_O7_enc; // Load into O7; preserve source oop
882 assert(src1_enc != dst_enc, "");
883 }
884 }
885 }
886 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
887 || offset == oopDesc::mark_offset_in_bytes())) {
888 // loading the mark should not be allowed either, but
889 // we don't check this since it conflicts with InlineObjectHash
890 // usage of LoadINode to get the mark. We could keep the
891 // check if we create a new LoadMarkNode
892 // but do not verify the object before its header is initialized
893 ShouldNotReachHere();
894 }
895 }
896 }
897 }
898 }
899 #endif
900
901 uint instr;
902 instr = (Assembler::ldst_op << 30)
903 | (dst_enc << 25)
904 | (primary << 19)
905 | (src1_enc << 14);
906
907 uint index = src2_enc;
908 int disp = disp32;
909
910 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
911 disp += STACK_BIAS;
912
913 // We should have a compiler bailout here rather than a guarantee.
914 // Better yet would be some mechanism to handle variable-size matches correctly.
915 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
916
917 if( disp == 0 ) {
918 // use reg-reg form
919 // bit 13 is already zero
920 instr |= index;
921 } else {
922 // use reg-imm form
923 instr |= 0x00002000; // set bit 13 to one
924 instr |= disp & 0x1FFF;
925 }
926
927 cbuf.insts()->emit_int32(instr);
928
929 #ifdef ASSERT
930 {
931 MacroAssembler _masm(&cbuf);
932 if (is_verified_oop_base) {
933 __ verify_oop(reg_to_register_object(src1_enc));
934 }
935 if (is_verified_oop_store) {
936 __ verify_oop(reg_to_register_object(dst_enc));
937 }
938 if (tmp_enc != -1) {
939 __ mov(O7, reg_to_register_object(tmp_enc));
940 }
941 if (is_verified_oop_load) {
942 __ verify_oop(reg_to_register_object(dst_enc));
943 }
944 }
945 #endif
946 }
947
948 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
949 // The method which records debug information at every safepoint
950 // expects the call to be the first instruction in the snippet as
951 // it creates a PcDesc structure which tracks the offset of a call
952 // from the start of the codeBlob. This offset is computed as
953 // code_end() - code_begin() of the code which has been emitted
954 // so far.
955 // In this particular case we have skirted around the problem by
956 // putting the "mov" instruction in the delay slot but the problem
957 // may bite us again at some other point and a cleaner/generic
958 // solution using relocations would be needed.
959 MacroAssembler _masm(&cbuf);
960 __ set_inst_mark();
961
962 // We flush the current window just so that there is a valid stack copy
963 // the fact that the current window becomes active again instantly is
964 // not a problem there is nothing live in it.
965
966 #ifdef ASSERT
967 int startpos = __ offset();
968 #endif /* ASSERT */
969
970 __ call((address)entry_point, rtype);
971
972 if (preserve_g2) __ delayed()->mov(G2, L7);
973 else __ delayed()->nop();
974
975 if (preserve_g2) __ mov(L7, G2);
976
977 #ifdef ASSERT
978 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
979 #ifdef _LP64
980 // Trash argument dump slots.
981 __ set(0xb0b8ac0db0b8ac0d, G1);
982 __ mov(G1, G5);
983 __ stx(G1, SP, STACK_BIAS + 0x80);
984 __ stx(G1, SP, STACK_BIAS + 0x88);
985 __ stx(G1, SP, STACK_BIAS + 0x90);
986 __ stx(G1, SP, STACK_BIAS + 0x98);
987 __ stx(G1, SP, STACK_BIAS + 0xA0);
988 __ stx(G1, SP, STACK_BIAS + 0xA8);
989 #else // _LP64
990 // this is also a native call, so smash the first 7 stack locations,
991 // and the various registers
992
993 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
994 // while [SP+0x44..0x58] are the argument dump slots.
995 __ set((intptr_t)0xbaadf00d, G1);
996 __ mov(G1, G5);
997 __ sllx(G1, 32, G1);
998 __ or3(G1, G5, G1);
999 __ mov(G1, G5);
1000 __ stx(G1, SP, 0x40);
1001 __ stx(G1, SP, 0x48);
1002 __ stx(G1, SP, 0x50);
1003 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1004 #endif // _LP64
1005 }
1006 #endif /*ASSERT*/
1007 }
1008
1009 //=============================================================================
1010 // REQUIRED FUNCTIONALITY for encoding
1011 void emit_lo(CodeBuffer &cbuf, int val) { }
1012 void emit_hi(CodeBuffer &cbuf, int val) { }
1013
1014
1015 //=============================================================================
1016 const bool Matcher::constant_table_absolute_addressing = false;
1017 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
1018
1019 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1020 Compile* C = ra_->C;
1021 Compile::ConstantTable& constant_table = C->constant_table();
1022 MacroAssembler _masm(&cbuf);
1023
1024 Register r = as_Register(ra_->get_encode(this));
1025 CodeSection* cs = __ code()->consts();
1026 int consts_size = cs->align_at_start(cs->size());
1027
1028 if (UseRDPCForConstantTableBase) {
1029 // For the following RDPC logic to work correctly the consts
1030 // section must be allocated right before the insts section. This
1031 // assert checks for that. The layout and the SECT_* constants
1032 // are defined in src/share/vm/asm/codeBuffer.hpp.
1033 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1034 int offset = __ offset();
1035 int disp;
1036
1037 // If the displacement from the current PC to the constant table
1038 // base fits into simm13 we set the constant table base to the
1039 // current PC.
1040 if (__ is_simm13(-(consts_size + offset))) {
1041 constant_table.set_table_base_offset(-(consts_size + offset));
1042 disp = 0;
1043 } else {
1044 // If the offset of the top constant (last entry in the table)
1045 // fits into simm13 we set the constant table base to the actual
1046 // table base.
1047 if (__ is_simm13(constant_table.top_offset())) {
1048 constant_table.set_table_base_offset(0);
1049 disp = consts_size + offset;
1050 } else {
1051 // Otherwise we set the constant table base in the middle of the
1052 // constant table.
1053 int half_consts_size = consts_size / 2;
1054 assert(half_consts_size * 2 == consts_size, "sanity");
1055 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement.
1056 disp = half_consts_size + offset;
1057 }
1058 }
1059
1060 __ rdpc(r);
1061
1062 if (disp != 0) {
1063 assert(r != O7, "need temporary");
1064 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1065 }
1066 }
1067 else {
1068 // Materialize the constant table base.
1069 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1070 address baseaddr = cs->start() + -(constant_table.table_base_offset());
1071 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1072 AddressLiteral base(baseaddr, rspec);
1073 __ set(base, r);
1074 }
1075 }
1076
1077 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1078 if (UseRDPCForConstantTableBase) {
1079 // This is really the worst case but generally it's only 1 instruction.
1080 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1081 } else {
1082 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1083 }
1084 }
1085
1086 #ifndef PRODUCT
1087 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1088 char reg[128];
1089 ra_->dump_register(this, reg);
1090 if (UseRDPCForConstantTableBase) {
1091 st->print("RDPC %s\t! constant table base", reg);
1092 } else {
1093 st->print("SET &constanttable,%s\t! constant table base", reg);
1094 }
1095 }
1096 #endif
1097
1098
1099 //=============================================================================
1100
1101 #ifndef PRODUCT
1102 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1103 Compile* C = ra_->C;
1104
1105 for (int i = 0; i < OptoPrologueNops; i++) {
1106 st->print_cr("NOP"); st->print("\t");
1107 }
1108
1109 if( VerifyThread ) {
1110 st->print_cr("Verify_Thread"); st->print("\t");
1111 }
1112
1113 size_t framesize = C->frame_slots() << LogBytesPerInt;
1114
1115 // Calls to C2R adapters often do not accept exceptional returns.
1116 // We require that their callers must bang for them. But be careful, because
1117 // some VM calls (such as call site linkage) can use several kilobytes of
1118 // stack. But the stack safety zone should account for that.
1119 // See bugs 4446381, 4468289, 4497237.
1120 if (C->need_stack_bang(framesize)) {
1121 st->print_cr("! stack bang"); st->print("\t");
1122 }
1123
1124 if (Assembler::is_simm13(-framesize)) {
1125 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1126 } else {
1127 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1128 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1129 st->print ("SAVE R_SP,R_G3,R_SP");
1130 }
1131
1132 }
1133 #endif
1134
1135 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1136 Compile* C = ra_->C;
1137 MacroAssembler _masm(&cbuf);
1138
1139 for (int i = 0; i < OptoPrologueNops; i++) {
1140 __ nop();
1141 }
1142
1143 __ verify_thread();
1144
1145 size_t framesize = C->frame_slots() << LogBytesPerInt;
1146 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1147 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1148
1149 // Calls to C2R adapters often do not accept exceptional returns.
1150 // We require that their callers must bang for them. But be careful, because
1151 // some VM calls (such as call site linkage) can use several kilobytes of
1152 // stack. But the stack safety zone should account for that.
1153 // See bugs 4446381, 4468289, 4497237.
1154 if (C->need_stack_bang(framesize)) {
1155 __ generate_stack_overflow_check(framesize);
1156 }
1157
1158 if (Assembler::is_simm13(-framesize)) {
1159 __ save(SP, -framesize, SP);
1160 } else {
1161 __ sethi(-framesize & ~0x3ff, G3);
1162 __ add(G3, -framesize & 0x3ff, G3);
1163 __ save(SP, G3, SP);
1164 }
1165 C->set_frame_complete( __ offset() );
1166 }
1167
1168 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1169 return MachNode::size(ra_);
1170 }
1171
1172 int MachPrologNode::reloc() const {
1173 return 10; // a large enough number
1174 }
1175
1176 //=============================================================================
1177 #ifndef PRODUCT
1178 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1179 Compile* C = ra_->C;
1180
1181 if( do_polling() && ra_->C->is_method_compilation() ) {
1182 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1183 #ifdef _LP64
1184 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1185 #else
1186 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1187 #endif
1188 }
1189
1190 if( do_polling() )
1191 st->print("RET\n\t");
1192
1193 st->print("RESTORE");
1194 }
1195 #endif
1196
1197 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1198 MacroAssembler _masm(&cbuf);
1199 Compile* C = ra_->C;
1200
1201 __ verify_thread();
1202
1203 // If this does safepoint polling, then do it here
1204 if( do_polling() && ra_->C->is_method_compilation() ) {
1205 AddressLiteral polling_page(os::get_polling_page());
1206 __ sethi(polling_page, L0);
1207 __ relocate(relocInfo::poll_return_type);
1208 __ ld_ptr( L0, 0, G0 );
1209 }
1210
1211 // If this is a return, then stuff the restore in the delay slot
1212 if( do_polling() ) {
1213 __ ret();
1214 __ delayed()->restore();
1215 } else {
1216 __ restore();
1217 }
1218 }
1219
1220 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1221 return MachNode::size(ra_);
1222 }
1223
1224 int MachEpilogNode::reloc() const {
1225 return 16; // a large enough number
1226 }
1227
1228 const Pipeline * MachEpilogNode::pipeline() const {
1229 return MachNode::pipeline_class();
1230 }
1231
1232 int MachEpilogNode::safepoint_offset() const {
1233 assert( do_polling(), "no return for this epilog node");
1234 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1235 }
1236
1237 //=============================================================================
1238
1239 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1240 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1241 static enum RC rc_class( OptoReg::Name reg ) {
1242 if( !OptoReg::is_valid(reg) ) return rc_bad;
1243 if (OptoReg::is_stack(reg)) return rc_stack;
1244 VMReg r = OptoReg::as_VMReg(reg);
1245 if (r->is_Register()) return rc_int;
1246 assert(r->is_FloatRegister(), "must be");
1247 return rc_float;
1248 }
1249
1250 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1251 if( cbuf ) {
1252 // Better yet would be some mechanism to handle variable-size matches correctly
1253 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1254 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1255 } else {
1256 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1257 }
1258 }
1259 #ifndef PRODUCT
1260 else if( !do_size ) {
1261 if( size != 0 ) st->print("\n\t");
1262 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1263 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1264 }
1265 #endif
1266 return size+4;
1267 }
1268
1269 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1270 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1271 #ifndef PRODUCT
1272 else if( !do_size ) {
1273 if( size != 0 ) st->print("\n\t");
1274 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1275 }
1276 #endif
1277 return size+4;
1278 }
1279
1280 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1281 PhaseRegAlloc *ra_,
1282 bool do_size,
1283 outputStream* st ) const {
1284 // Get registers to move
1285 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1286 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1287 OptoReg::Name dst_second = ra_->get_reg_second(this );
1288 OptoReg::Name dst_first = ra_->get_reg_first(this );
1289
1290 enum RC src_second_rc = rc_class(src_second);
1291 enum RC src_first_rc = rc_class(src_first);
1292 enum RC dst_second_rc = rc_class(dst_second);
1293 enum RC dst_first_rc = rc_class(dst_first);
1294
1295 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1296
1297 // Generate spill code!
1298 int size = 0;
1299
1300 if( src_first == dst_first && src_second == dst_second )
1301 return size; // Self copy, no move
1302
1303 // --------------------------------------
1304 // Check for mem-mem move. Load into unused float registers and fall into
1305 // the float-store case.
1306 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1307 int offset = ra_->reg2offset(src_first);
1308 // Further check for aligned-adjacent pair, so we can use a double load
1309 if( (src_first&1)==0 && src_first+1 == src_second ) {
1310 src_second = OptoReg::Name(R_F31_num);
1311 src_second_rc = rc_float;
1312 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1313 } else {
1314 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1315 }
1316 src_first = OptoReg::Name(R_F30_num);
1317 src_first_rc = rc_float;
1318 }
1319
1320 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1321 int offset = ra_->reg2offset(src_second);
1322 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1323 src_second = OptoReg::Name(R_F31_num);
1324 src_second_rc = rc_float;
1325 }
1326
1327 // --------------------------------------
1328 // Check for float->int copy; requires a trip through memory
1329 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1330 int offset = frame::register_save_words*wordSize;
1331 if (cbuf) {
1332 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1333 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1334 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1335 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1336 }
1337 #ifndef PRODUCT
1338 else if (!do_size) {
1339 if (size != 0) st->print("\n\t");
1340 st->print( "SUB R_SP,16,R_SP\n");
1341 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1342 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1343 st->print("\tADD R_SP,16,R_SP\n");
1344 }
1345 #endif
1346 size += 16;
1347 }
1348
1349 // Check for float->int copy on T4
1350 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1351 // Further check for aligned-adjacent pair, so we can use a double move
1352 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1353 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1354 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1355 }
1356 // Check for int->float copy on T4
1357 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1358 // Further check for aligned-adjacent pair, so we can use a double move
1359 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1360 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1361 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1362 }
1363
1364 // --------------------------------------
1365 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1366 // In such cases, I have to do the big-endian swap. For aligned targets, the
1367 // hardware does the flop for me. Doubles are always aligned, so no problem
1368 // there. Misaligned sources only come from native-long-returns (handled
1369 // special below).
1370 #ifndef _LP64
1371 if( src_first_rc == rc_int && // source is already big-endian
1372 src_second_rc != rc_bad && // 64-bit move
1373 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1374 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1375 // Do the big-endian flop.
1376 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1377 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1378 }
1379 #endif
1380
1381 // --------------------------------------
1382 // Check for integer reg-reg copy
1383 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1384 #ifndef _LP64
1385 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1386 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1387 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1388 // operand contains the least significant word of the 64-bit value and vice versa.
1389 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1390 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1391 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1392 if( cbuf ) {
1393 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1394 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1395 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1396 #ifndef PRODUCT
1397 } else if( !do_size ) {
1398 if( size != 0 ) st->print("\n\t");
1399 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1400 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1401 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1402 #endif
1403 }
1404 return size+12;
1405 }
1406 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1407 // returning a long value in I0/I1
1408 // a SpillCopy must be able to target a return instruction's reg_class
1409 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1410 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1411 // operand contains the least significant word of the 64-bit value and vice versa.
1412 OptoReg::Name tdest = dst_first;
1413
1414 if (src_first == dst_first) {
1415 tdest = OptoReg::Name(R_O7_num);
1416 size += 4;
1417 }
1418
1419 if( cbuf ) {
1420 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1421 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1422 // ShrL_reg_imm6
1423 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1424 // ShrR_reg_imm6 src, 0, dst
1425 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1426 if (tdest != dst_first) {
1427 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1428 }
1429 }
1430 #ifndef PRODUCT
1431 else if( !do_size ) {
1432 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1433 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1434 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1435 if (tdest != dst_first) {
1436 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1437 }
1438 }
1439 #endif // PRODUCT
1440 return size+8;
1441 }
1442 #endif // !_LP64
1443 // Else normal reg-reg copy
1444 assert( src_second != dst_first, "smashed second before evacuating it" );
1445 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1446 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1447 // This moves an aligned adjacent pair.
1448 // See if we are done.
1449 if( src_first+1 == src_second && dst_first+1 == dst_second )
1450 return size;
1451 }
1452
1453 // Check for integer store
1454 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1455 int offset = ra_->reg2offset(dst_first);
1456 // Further check for aligned-adjacent pair, so we can use a double store
1457 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1458 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1459 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1460 }
1461
1462 // Check for integer load
1463 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1464 int offset = ra_->reg2offset(src_first);
1465 // Further check for aligned-adjacent pair, so we can use a double load
1466 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1467 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1468 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1469 }
1470
1471 // Check for float reg-reg copy
1472 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1473 // Further check for aligned-adjacent pair, so we can use a double move
1474 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1475 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1476 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1477 }
1478
1479 // Check for float store
1480 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1481 int offset = ra_->reg2offset(dst_first);
1482 // Further check for aligned-adjacent pair, so we can use a double store
1483 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1484 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1485 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1486 }
1487
1488 // Check for float load
1489 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1490 int offset = ra_->reg2offset(src_first);
1491 // Further check for aligned-adjacent pair, so we can use a double load
1492 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1493 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1494 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1495 }
1496
1497 // --------------------------------------------------------------------
1498 // Check for hi bits still needing moving. Only happens for misaligned
1499 // arguments to native calls.
1500 if( src_second == dst_second )
1501 return size; // Self copy; no move
1502 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1503
1504 #ifndef _LP64
1505 // In the LP64 build, all registers can be moved as aligned/adjacent
1506 // pairs, so there's never any need to move the high bits separately.
1507 // The 32-bit builds have to deal with the 32-bit ABI which can force
1508 // all sorts of silly alignment problems.
1509
1510 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1511 // 32-bits of a 64-bit register, but are needed in low bits of another
1512 // register (else it's a hi-bits-to-hi-bits copy which should have
1513 // happened already as part of a 64-bit move)
1514 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1515 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1516 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1517 // Shift src_second down to dst_second's low bits.
1518 if( cbuf ) {
1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1520 #ifndef PRODUCT
1521 } else if( !do_size ) {
1522 if( size != 0 ) st->print("\n\t");
1523 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1524 #endif
1525 }
1526 return size+4;
1527 }
1528
1529 // Check for high word integer store. Must down-shift the hi bits
1530 // into a temp register, then fall into the case of storing int bits.
1531 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1532 // Shift src_second down to dst_second's low bits.
1533 if( cbuf ) {
1534 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1535 #ifndef PRODUCT
1536 } else if( !do_size ) {
1537 if( size != 0 ) st->print("\n\t");
1538 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1539 #endif
1540 }
1541 size+=4;
1542 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1543 }
1544
1545 // Check for high word integer load
1546 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1547 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1548
1549 // Check for high word integer store
1550 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1551 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1552
1553 // Check for high word float store
1554 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1555 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1556
1557 #endif // !_LP64
1558
1559 Unimplemented();
1560 }
1561
1562 #ifndef PRODUCT
1563 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1564 implementation( NULL, ra_, false, st );
1565 }
1566 #endif
1567
1568 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1569 implementation( &cbuf, ra_, false, NULL );
1570 }
1571
1572 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1573 return implementation( NULL, ra_, true, NULL );
1574 }
1575
1576 //=============================================================================
1577 #ifndef PRODUCT
1578 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1579 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1580 }
1581 #endif
1582
1583 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1584 MacroAssembler _masm(&cbuf);
1585 for(int i = 0; i < _count; i += 1) {
1586 __ nop();
1587 }
1588 }
1589
1590 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1591 return 4 * _count;
1592 }
1593
1594
1595 //=============================================================================
1596 #ifndef PRODUCT
1597 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1598 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1599 int reg = ra_->get_reg_first(this);
1600 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1601 }
1602 #endif
1603
1604 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1605 MacroAssembler _masm(&cbuf);
1606 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1607 int reg = ra_->get_encode(this);
1608
1609 if (Assembler::is_simm13(offset)) {
1610 __ add(SP, offset, reg_to_register_object(reg));
1611 } else {
1612 __ set(offset, O7);
1613 __ add(SP, O7, reg_to_register_object(reg));
1614 }
1615 }
1616
1617 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1618 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1619 assert(ra_ == ra_->C->regalloc(), "sanity");
1620 return ra_->C->scratch_emit_size(this);
1621 }
1622
1623 //=============================================================================
1624
1625 // emit call stub, compiled java to interpretor
1626 void emit_java_to_interp(CodeBuffer &cbuf ) {
1627
1628 // Stub is fixed up when the corresponding call is converted from calling
1629 // compiled code to calling interpreted code.
1630 // set (empty), G5
1631 // jmp -1
1632
1633 address mark = cbuf.insts_mark(); // get mark within main instrs section
1634
1635 MacroAssembler _masm(&cbuf);
1636
1637 address base =
1638 __ start_a_stub(Compile::MAX_stubs_size);
1639 if (base == NULL) return; // CodeBuffer::expand failed
1640
1641 // static stub relocation stores the instruction address of the call
1642 __ relocate(static_stub_Relocation::spec(mark));
1643
1644 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1645
1646 __ set_inst_mark();
1647 AddressLiteral addrlit(-1);
1648 __ JUMP(addrlit, G3, 0);
1649
1650 __ delayed()->nop();
1651
1652 // Update current stubs pointer and restore code_end.
1653 __ end_a_stub();
1654 }
1655
1656 // size of call stub, compiled java to interpretor
1657 uint size_java_to_interp() {
1658 // This doesn't need to be accurate but it must be larger or equal to
1659 // the real size of the stub.
1660 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1661 NativeJump::instruction_size + // sethi; jmp; nop
1662 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1663 }
1664 // relocation entries for call stub, compiled java to interpretor
1665 uint reloc_java_to_interp() {
1666 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1667 }
1668
1669
1670 //=============================================================================
1671 #ifndef PRODUCT
1672 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1673 st->print_cr("\nUEP:");
1674 #ifdef _LP64
1675 if (UseCompressedOops) {
1676 assert(Universe::heap() != NULL, "java heap should be initialized");
1677 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1678 st->print_cr("\tSLL R_G5,3,R_G5");
1679 if (Universe::narrow_oop_base() != NULL)
1680 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1681 } else {
1682 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1683 }
1684 st->print_cr("\tCMP R_G5,R_G3" );
1685 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1686 #else // _LP64
1687 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1688 st->print_cr("\tCMP R_G5,R_G3" );
1689 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1690 #endif // _LP64
1691 }
1692 #endif
1693
1694 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1695 MacroAssembler _masm(&cbuf);
1696 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1697 Register temp_reg = G3;
1698 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1699
1700 // Load klass from receiver
1701 __ load_klass(O0, temp_reg);
1702 // Compare against expected klass
1703 __ cmp(temp_reg, G5_ic_reg);
1704 // Branch to miss code, checks xcc or icc depending
1705 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1706 }
1707
1708 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1709 return MachNode::size(ra_);
1710 }
1711
1712
1713 //=============================================================================
1714
1715 uint size_exception_handler() {
1716 if (TraceJumps) {
1717 return (400); // just a guess
1718 }
1719 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1720 }
1721
1722 uint size_deopt_handler() {
1723 if (TraceJumps) {
1724 return (400); // just a guess
1725 }
1726 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1727 }
1728
1729 // Emit exception handler code.
1730 int emit_exception_handler(CodeBuffer& cbuf) {
1731 Register temp_reg = G3;
1732 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1733 MacroAssembler _masm(&cbuf);
1734
1735 address base =
1736 __ start_a_stub(size_exception_handler());
1737 if (base == NULL) return 0; // CodeBuffer::expand failed
1738
1739 int offset = __ offset();
1740
1741 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1742 __ delayed()->nop();
1743
1744 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1745
1746 __ end_a_stub();
1747
1748 return offset;
1749 }
1750
1751 int emit_deopt_handler(CodeBuffer& cbuf) {
1752 // Can't use any of the current frame's registers as we may have deopted
1753 // at a poll and everything (including G3) can be live.
1754 Register temp_reg = L0;
1755 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1756 MacroAssembler _masm(&cbuf);
1757
1758 address base =
1759 __ start_a_stub(size_deopt_handler());
1760 if (base == NULL) return 0; // CodeBuffer::expand failed
1761
1762 int offset = __ offset();
1763 __ save_frame(0);
1764 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1765 __ delayed()->restore();
1766
1767 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1768
1769 __ end_a_stub();
1770 return offset;
1771
1772 }
1773
1774 // Given a register encoding, produce a Integer Register object
1775 static Register reg_to_register_object(int register_encoding) {
1776 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1777 return as_Register(register_encoding);
1778 }
1779
1780 // Given a register encoding, produce a single-precision Float Register object
1781 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1782 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1783 return as_SingleFloatRegister(register_encoding);
1784 }
1785
1786 // Given a register encoding, produce a double-precision Float Register object
1787 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1788 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1789 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1790 return as_DoubleFloatRegister(register_encoding);
1791 }
1792
1793 const bool Matcher::match_rule_supported(int opcode) {
1794 if (!has_match_rule(opcode))
1795 return false;
1796
1797 switch (opcode) {
1798 case Op_CountLeadingZerosI:
1799 case Op_CountLeadingZerosL:
1800 case Op_CountTrailingZerosI:
1801 case Op_CountTrailingZerosL:
1802 if (!UsePopCountInstruction)
1803 return false;
1804 break;
1805 }
1806
1807 return true; // Per default match rules are supported.
1808 }
1809
1810 int Matcher::regnum_to_fpu_offset(int regnum) {
1811 return regnum - 32; // The FP registers are in the second chunk
1812 }
1813
1814 #ifdef ASSERT
1815 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1816 #endif
1817
1818 // Vector width in bytes
1819 const uint Matcher::vector_width_in_bytes(void) {
1820 return 8;
1821 }
1822
1823 // Vector ideal reg
1824 const uint Matcher::vector_ideal_reg(void) {
1825 return Op_RegD;
1826 }
1827
1828 // USII supports fxtof through the whole range of number, USIII doesn't
1829 const bool Matcher::convL2FSupported(void) {
1830 return VM_Version::has_fast_fxtof();
1831 }
1832
1833 // Is this branch offset short enough that a short branch can be used?
1834 //
1835 // NOTE: If the platform does not provide any short branch variants, then
1836 // this method should return false for offset 0.
1837 bool Matcher::is_short_branch_offset(int rule, int offset) {
1838 return false;
1839 }
1840
1841 const bool Matcher::isSimpleConstant64(jlong value) {
1842 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1843 // Depends on optimizations in MacroAssembler::setx.
1844 int hi = (int)(value >> 32);
1845 int lo = (int)(value & ~0);
1846 return (hi == 0) || (hi == -1) || (lo == 0);
1847 }
1848
1849 // No scaling for the parameter the ClearArray node.
1850 const bool Matcher::init_array_count_is_in_bytes = true;
1851
1852 // Threshold size for cleararray.
1853 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1854
1855 // Should the Matcher clone shifts on addressing modes, expecting them to
1856 // be subsumed into complex addressing expressions or compute them into
1857 // registers? True for Intel but false for most RISCs
1858 const bool Matcher::clone_shift_expressions = false;
1859
1860 // Do we need to mask the count passed to shift instructions or does
1861 // the cpu only look at the lower 5/6 bits anyway?
1862 const bool Matcher::need_masked_shift_count = false;
1863
1864 bool Matcher::narrow_oop_use_complex_address() {
1865 NOT_LP64(ShouldNotCallThis());
1866 assert(UseCompressedOops, "only for compressed oops code");
1867 return false;
1868 }
1869
1870 // Is it better to copy float constants, or load them directly from memory?
1871 // Intel can load a float constant from a direct address, requiring no
1872 // extra registers. Most RISCs will have to materialize an address into a
1873 // register first, so they would do better to copy the constant from stack.
1874 const bool Matcher::rematerialize_float_constants = false;
1875
1876 // If CPU can load and store mis-aligned doubles directly then no fixup is
1877 // needed. Else we split the double into 2 integer pieces and move it
1878 // piece-by-piece. Only happens when passing doubles into C code as the
1879 // Java calling convention forces doubles to be aligned.
1880 #ifdef _LP64
1881 const bool Matcher::misaligned_doubles_ok = true;
1882 #else
1883 const bool Matcher::misaligned_doubles_ok = false;
1884 #endif
1885
1886 // No-op on SPARC.
1887 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1888 }
1889
1890 // Advertise here if the CPU requires explicit rounding operations
1891 // to implement the UseStrictFP mode.
1892 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1893
1894 // Are floats conerted to double when stored to stack during deoptimization?
1895 // Sparc does not handle callee-save floats.
1896 bool Matcher::float_in_double() { return false; }
1897
1898 // Do ints take an entire long register or just half?
1899 // Note that we if-def off of _LP64.
1900 // The relevant question is how the int is callee-saved. In _LP64
1901 // the whole long is written but de-opt'ing will have to extract
1902 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1903 #ifdef _LP64
1904 const bool Matcher::int_in_long = true;
1905 #else
1906 const bool Matcher::int_in_long = false;
1907 #endif
1908
1909 // Return whether or not this register is ever used as an argument. This
1910 // function is used on startup to build the trampoline stubs in generateOptoStub.
1911 // Registers not mentioned will be killed by the VM call in the trampoline, and
1912 // arguments in those registers not be available to the callee.
1913 bool Matcher::can_be_java_arg( int reg ) {
1914 // Standard sparc 6 args in registers
1915 if( reg == R_I0_num ||
1916 reg == R_I1_num ||
1917 reg == R_I2_num ||
1918 reg == R_I3_num ||
1919 reg == R_I4_num ||
1920 reg == R_I5_num ) return true;
1921 #ifdef _LP64
1922 // 64-bit builds can pass 64-bit pointers and longs in
1923 // the high I registers
1924 if( reg == R_I0H_num ||
1925 reg == R_I1H_num ||
1926 reg == R_I2H_num ||
1927 reg == R_I3H_num ||
1928 reg == R_I4H_num ||
1929 reg == R_I5H_num ) return true;
1930
1931 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1932 return true;
1933 }
1934
1935 #else
1936 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1937 // Longs cannot be passed in O regs, because O regs become I regs
1938 // after a 'save' and I regs get their high bits chopped off on
1939 // interrupt.
1940 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1941 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1942 #endif
1943 // A few float args in registers
1944 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1945
1946 return false;
1947 }
1948
1949 bool Matcher::is_spillable_arg( int reg ) {
1950 return can_be_java_arg(reg);
1951 }
1952
1953 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1954 // Use hardware SDIVX instruction when it is
1955 // faster than a code which use multiply.
1956 return VM_Version::has_fast_idiv();
1957 }
1958
1959 // Register for DIVI projection of divmodI
1960 RegMask Matcher::divI_proj_mask() {
1961 ShouldNotReachHere();
1962 return RegMask();
1963 }
1964
1965 // Register for MODI projection of divmodI
1966 RegMask Matcher::modI_proj_mask() {
1967 ShouldNotReachHere();
1968 return RegMask();
1969 }
1970
1971 // Register for DIVL projection of divmodL
1972 RegMask Matcher::divL_proj_mask() {
1973 ShouldNotReachHere();
1974 return RegMask();
1975 }
1976
1977 // Register for MODL projection of divmodL
1978 RegMask Matcher::modL_proj_mask() {
1979 ShouldNotReachHere();
1980 return RegMask();
1981 }
1982
1983 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1984 return L7_REGP_mask;
1985 }
1986
1987 %}
1988
1989
1990 // The intptr_t operand types, defined by textual substitution.
1991 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1992 #ifdef _LP64
1993 #define immX immL
1994 #define immX13 immL13
1995 #define immX13m7 immL13m7
1996 #define iRegX iRegL
1997 #define g1RegX g1RegL
1998 #else
1999 #define immX immI
2000 #define immX13 immI13
2001 #define immX13m7 immI13m7
2002 #define iRegX iRegI
2003 #define g1RegX g1RegI
2004 #endif
2005
2006 //----------ENCODING BLOCK-----------------------------------------------------
2007 // This block specifies the encoding classes used by the compiler to output
2008 // byte streams. Encoding classes are parameterized macros used by
2009 // Machine Instruction Nodes in order to generate the bit encoding of the
2010 // instruction. Operands specify their base encoding interface with the
2011 // interface keyword. There are currently supported four interfaces,
2012 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2013 // operand to generate a function which returns its register number when
2014 // queried. CONST_INTER causes an operand to generate a function which
2015 // returns the value of the constant when queried. MEMORY_INTER causes an
2016 // operand to generate four functions which return the Base Register, the
2017 // Index Register, the Scale Value, and the Offset Value of the operand when
2018 // queried. COND_INTER causes an operand to generate six functions which
2019 // return the encoding code (ie - encoding bits for the instruction)
2020 // associated with each basic boolean condition for a conditional instruction.
2021 //
2022 // Instructions specify two basic values for encoding. Again, a function
2023 // is available to check if the constant displacement is an oop. They use the
2024 // ins_encode keyword to specify their encoding classes (which must be
2025 // a sequence of enc_class names, and their parameters, specified in
2026 // the encoding block), and they use the
2027 // opcode keyword to specify, in order, their primary, secondary, and
2028 // tertiary opcode. Only the opcode sections which a particular instruction
2029 // needs for encoding need to be specified.
2030 encode %{
2031 enc_class enc_untested %{
2032 #ifdef ASSERT
2033 MacroAssembler _masm(&cbuf);
2034 __ untested("encoding");
2035 #endif
2036 %}
2037
2038 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2039 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2040 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2041 %}
2042
2043 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2044 emit_form3_mem_reg(cbuf, this, $primary, -1,
2045 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2046 %}
2047
2048 enc_class form3_mem_prefetch_read( memory mem ) %{
2049 emit_form3_mem_reg(cbuf, this, $primary, -1,
2050 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2051 %}
2052
2053 enc_class form3_mem_prefetch_write( memory mem ) %{
2054 emit_form3_mem_reg(cbuf, this, $primary, -1,
2055 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2056 %}
2057
2058 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2059 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2060 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2061 guarantee($mem$$index == R_G0_enc, "double index?");
2062 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2063 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2064 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2065 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2066 %}
2067
2068 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2069 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2070 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2071 guarantee($mem$$index == R_G0_enc, "double index?");
2072 // Load long with 2 instructions
2073 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2074 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2075 %}
2076
2077 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2078 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2079 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2080 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2081 %}
2082
2083 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2084 // Encode a reg-reg copy. If it is useless, then empty encoding.
2085 if( $rs2$$reg != $rd$$reg )
2086 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2087 %}
2088
2089 // Target lo half of long
2090 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2091 // Encode a reg-reg copy. If it is useless, then empty encoding.
2092 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2093 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2094 %}
2095
2096 // Source lo half of long
2097 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2098 // Encode a reg-reg copy. If it is useless, then empty encoding.
2099 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2100 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2101 %}
2102
2103 // Target hi half of long
2104 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2105 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2106 %}
2107
2108 // Source lo half of long, and leave it sign extended.
2109 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2110 // Sign extend low half
2111 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2112 %}
2113
2114 // Source hi half of long, and leave it sign extended.
2115 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2116 // Shift high half to low half
2117 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2118 %}
2119
2120 // Source hi half of long
2121 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2122 // Encode a reg-reg copy. If it is useless, then empty encoding.
2123 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2124 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2125 %}
2126
2127 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2128 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2129 %}
2130
2131 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2132 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2133 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2134 %}
2135
2136 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2137 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2138 // clear if nothing else is happening
2139 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2140 // blt,a,pn done
2141 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2142 // mov dst,-1 in delay slot
2143 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2144 %}
2145
2146 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2147 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2148 %}
2149
2150 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2151 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2152 %}
2153
2154 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2155 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2156 %}
2157
2158 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2159 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2160 %}
2161
2162 enc_class move_return_pc_to_o1() %{
2163 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2164 %}
2165
2166 #ifdef _LP64
2167 /* %%% merge with enc_to_bool */
2168 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2169 MacroAssembler _masm(&cbuf);
2170
2171 Register src_reg = reg_to_register_object($src$$reg);
2172 Register dst_reg = reg_to_register_object($dst$$reg);
2173 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2174 %}
2175 #endif
2176
2177 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2178 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2179 MacroAssembler _masm(&cbuf);
2180
2181 Register p_reg = reg_to_register_object($p$$reg);
2182 Register q_reg = reg_to_register_object($q$$reg);
2183 Register y_reg = reg_to_register_object($y$$reg);
2184 Register tmp_reg = reg_to_register_object($tmp$$reg);
2185
2186 __ subcc( p_reg, q_reg, p_reg );
2187 __ add ( p_reg, y_reg, tmp_reg );
2188 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2189 %}
2190
2191 enc_class form_d2i_helper(regD src, regF dst) %{
2192 // fcmp %fcc0,$src,$src
2193 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2194 // branch %fcc0 not-nan, predict taken
2195 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2196 // fdtoi $src,$dst
2197 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2198 // fitos $dst,$dst (if nan)
2199 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2200 // clear $dst (if nan)
2201 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2202 // carry on here...
2203 %}
2204
2205 enc_class form_d2l_helper(regD src, regD dst) %{
2206 // fcmp %fcc0,$src,$src check for NAN
2207 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2208 // branch %fcc0 not-nan, predict taken
2209 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2210 // fdtox $src,$dst convert in delay slot
2211 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2212 // fxtod $dst,$dst (if nan)
2213 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2214 // clear $dst (if nan)
2215 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2216 // carry on here...
2217 %}
2218
2219 enc_class form_f2i_helper(regF src, regF dst) %{
2220 // fcmps %fcc0,$src,$src
2221 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2222 // branch %fcc0 not-nan, predict taken
2223 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2224 // fstoi $src,$dst
2225 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2226 // fitos $dst,$dst (if nan)
2227 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2228 // clear $dst (if nan)
2229 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2230 // carry on here...
2231 %}
2232
2233 enc_class form_f2l_helper(regF src, regD dst) %{
2234 // fcmps %fcc0,$src,$src
2235 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2236 // branch %fcc0 not-nan, predict taken
2237 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2238 // fstox $src,$dst
2239 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2240 // fxtod $dst,$dst (if nan)
2241 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2242 // clear $dst (if nan)
2243 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2244 // carry on here...
2245 %}
2246
2247 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2248 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2249 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2250 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2251
2252 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2253
2254 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2255 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2256
2257 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2258 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2259 %}
2260
2261 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2262 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2263 %}
2264
2265 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2266 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2267 %}
2268
2269 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2270 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2271 %}
2272
2273 enc_class form3_convI2F(regF rs2, regF rd) %{
2274 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2275 %}
2276
2277 // Encloding class for traceable jumps
2278 enc_class form_jmpl(g3RegP dest) %{
2279 emit_jmpl(cbuf, $dest$$reg);
2280 %}
2281
2282 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2283 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2284 %}
2285
2286 enc_class form2_nop() %{
2287 emit_nop(cbuf);
2288 %}
2289
2290 enc_class form2_illtrap() %{
2291 emit_illtrap(cbuf);
2292 %}
2293
2294
2295 // Compare longs and convert into -1, 0, 1.
2296 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2297 // CMP $src1,$src2
2298 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2299 // blt,a,pn done
2300 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2301 // mov dst,-1 in delay slot
2302 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2303 // bgt,a,pn done
2304 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2305 // mov dst,1 in delay slot
2306 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2307 // CLR $dst
2308 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2309 %}
2310
2311 enc_class enc_PartialSubtypeCheck() %{
2312 MacroAssembler _masm(&cbuf);
2313 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2314 __ delayed()->nop();
2315 %}
2316
2317 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2318 MacroAssembler _masm(&cbuf);
2319 Label* L = $labl$$label;
2320 Assembler::Predict predict_taken =
2321 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2322
2323 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2324 __ delayed()->nop();
2325 %}
2326
2327 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2328 MacroAssembler _masm(&cbuf);
2329 Label* L = $labl$$label;
2330 Assembler::Predict predict_taken =
2331 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2332
2333 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2334 __ delayed()->nop();
2335 %}
2336
2337 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2338 int op = (Assembler::arith_op << 30) |
2339 ($dst$$reg << 25) |
2340 (Assembler::movcc_op3 << 19) |
2341 (1 << 18) | // cc2 bit for 'icc'
2342 ($cmp$$cmpcode << 14) |
2343 (0 << 13) | // select register move
2344 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2345 ($src$$reg << 0);
2346 cbuf.insts()->emit_int32(op);
2347 %}
2348
2349 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2350 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2351 int op = (Assembler::arith_op << 30) |
2352 ($dst$$reg << 25) |
2353 (Assembler::movcc_op3 << 19) |
2354 (1 << 18) | // cc2 bit for 'icc'
2355 ($cmp$$cmpcode << 14) |
2356 (1 << 13) | // select immediate move
2357 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2358 (simm11 << 0);
2359 cbuf.insts()->emit_int32(op);
2360 %}
2361
2362 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2363 int op = (Assembler::arith_op << 30) |
2364 ($dst$$reg << 25) |
2365 (Assembler::movcc_op3 << 19) |
2366 (0 << 18) | // cc2 bit for 'fccX'
2367 ($cmp$$cmpcode << 14) |
2368 (0 << 13) | // select register move
2369 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2370 ($src$$reg << 0);
2371 cbuf.insts()->emit_int32(op);
2372 %}
2373
2374 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2375 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2376 int op = (Assembler::arith_op << 30) |
2377 ($dst$$reg << 25) |
2378 (Assembler::movcc_op3 << 19) |
2379 (0 << 18) | // cc2 bit for 'fccX'
2380 ($cmp$$cmpcode << 14) |
2381 (1 << 13) | // select immediate move
2382 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2383 (simm11 << 0);
2384 cbuf.insts()->emit_int32(op);
2385 %}
2386
2387 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2388 int op = (Assembler::arith_op << 30) |
2389 ($dst$$reg << 25) |
2390 (Assembler::fpop2_op3 << 19) |
2391 (0 << 18) |
2392 ($cmp$$cmpcode << 14) |
2393 (1 << 13) | // select register move
2394 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2395 ($primary << 5) | // select single, double or quad
2396 ($src$$reg << 0);
2397 cbuf.insts()->emit_int32(op);
2398 %}
2399
2400 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2401 int op = (Assembler::arith_op << 30) |
2402 ($dst$$reg << 25) |
2403 (Assembler::fpop2_op3 << 19) |
2404 (0 << 18) |
2405 ($cmp$$cmpcode << 14) |
2406 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2407 ($primary << 5) | // select single, double or quad
2408 ($src$$reg << 0);
2409 cbuf.insts()->emit_int32(op);
2410 %}
2411
2412 // Used by the MIN/MAX encodings. Same as a CMOV, but
2413 // the condition comes from opcode-field instead of an argument.
2414 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2415 int op = (Assembler::arith_op << 30) |
2416 ($dst$$reg << 25) |
2417 (Assembler::movcc_op3 << 19) |
2418 (1 << 18) | // cc2 bit for 'icc'
2419 ($primary << 14) |
2420 (0 << 13) | // select register move
2421 (0 << 11) | // cc1, cc0 bits for 'icc'
2422 ($src$$reg << 0);
2423 cbuf.insts()->emit_int32(op);
2424 %}
2425
2426 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2427 int op = (Assembler::arith_op << 30) |
2428 ($dst$$reg << 25) |
2429 (Assembler::movcc_op3 << 19) |
2430 (6 << 16) | // cc2 bit for 'xcc'
2431 ($primary << 14) |
2432 (0 << 13) | // select register move
2433 (0 << 11) | // cc1, cc0 bits for 'icc'
2434 ($src$$reg << 0);
2435 cbuf.insts()->emit_int32(op);
2436 %}
2437
2438 enc_class Set13( immI13 src, iRegI rd ) %{
2439 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2440 %}
2441
2442 enc_class SetHi22( immI src, iRegI rd ) %{
2443 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2444 %}
2445
2446 enc_class Set32( immI src, iRegI rd ) %{
2447 MacroAssembler _masm(&cbuf);
2448 __ set($src$$constant, reg_to_register_object($rd$$reg));
2449 %}
2450
2451 enc_class call_epilog %{
2452 if( VerifyStackAtCalls ) {
2453 MacroAssembler _masm(&cbuf);
2454 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2455 Register temp_reg = G3;
2456 __ add(SP, framesize, temp_reg);
2457 __ cmp(temp_reg, FP);
2458 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2459 }
2460 %}
2461
2462 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2463 // to G1 so the register allocator will not have to deal with the misaligned register
2464 // pair.
2465 enc_class adjust_long_from_native_call %{
2466 #ifndef _LP64
2467 if (returns_long()) {
2468 // sllx O0,32,O0
2469 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2470 // srl O1,0,O1
2471 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2472 // or O0,O1,G1
2473 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2474 }
2475 #endif
2476 %}
2477
2478 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2479 // CALL directly to the runtime
2480 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2481 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2482 /*preserve_g2=*/true);
2483 %}
2484
2485 enc_class preserve_SP %{
2486 MacroAssembler _masm(&cbuf);
2487 __ mov(SP, L7_mh_SP_save);
2488 %}
2489
2490 enc_class restore_SP %{
2491 MacroAssembler _masm(&cbuf);
2492 __ mov(L7_mh_SP_save, SP);
2493 %}
2494
2495 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2496 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2497 // who we intended to call.
2498 if ( !_method ) {
2499 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2500 } else if (_optimized_virtual) {
2501 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2502 } else {
2503 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2504 }
2505 if( _method ) { // Emit stub for static call
2506 emit_java_to_interp(cbuf);
2507 }
2508 %}
2509
2510 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2511 MacroAssembler _masm(&cbuf);
2512 __ set_inst_mark();
2513 int vtable_index = this->_vtable_index;
2514 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2515 if (vtable_index < 0) {
2516 // must be invalid_vtable_index, not nonvirtual_vtable_index
2517 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2518 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2519 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2520 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2521 // !!!!!
2522 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2523 // emit_call_dynamic_prologue( cbuf );
2524 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2525
2526 address virtual_call_oop_addr = __ inst_mark();
2527 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2528 // who we intended to call.
2529 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2530 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2531 } else {
2532 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2533 // Just go thru the vtable
2534 // get receiver klass (receiver already checked for non-null)
2535 // If we end up going thru a c2i adapter interpreter expects method in G5
2536 int off = __ offset();
2537 __ load_klass(O0, G3_scratch);
2538 int klass_load_size;
2539 if (UseCompressedOops) {
2540 assert(Universe::heap() != NULL, "java heap should be initialized");
2541 if (Universe::narrow_oop_base() == NULL)
2542 klass_load_size = 2*BytesPerInstWord;
2543 else
2544 klass_load_size = 3*BytesPerInstWord;
2545 } else {
2546 klass_load_size = 1*BytesPerInstWord;
2547 }
2548 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2549 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2550 if( __ is_simm13(v_off) ) {
2551 __ ld_ptr(G3, v_off, G5_method);
2552 } else {
2553 // Generate 2 instructions
2554 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2555 __ or3(G5_method, v_off & 0x3ff, G5_method);
2556 // ld_ptr, set_hi, set
2557 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2558 "Unexpected instruction size(s)");
2559 __ ld_ptr(G3, G5_method, G5_method);
2560 }
2561 // NOTE: for vtable dispatches, the vtable entry will never be null.
2562 // However it may very well end up in handle_wrong_method if the
2563 // method is abstract for the particular class.
2564 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2565 // jump to target (either compiled code or c2iadapter)
2566 __ jmpl(G3_scratch, G0, O7);
2567 __ delayed()->nop();
2568 }
2569 %}
2570
2571 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2572 MacroAssembler _masm(&cbuf);
2573
2574 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2575 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2576 // we might be calling a C2I adapter which needs it.
2577
2578 assert(temp_reg != G5_ic_reg, "conflicting registers");
2579 // Load nmethod
2580 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2581
2582 // CALL to compiled java, indirect the contents of G3
2583 __ set_inst_mark();
2584 __ callr(temp_reg, G0);
2585 __ delayed()->nop();
2586 %}
2587
2588 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2589 MacroAssembler _masm(&cbuf);
2590 Register Rdividend = reg_to_register_object($src1$$reg);
2591 Register Rdivisor = reg_to_register_object($src2$$reg);
2592 Register Rresult = reg_to_register_object($dst$$reg);
2593
2594 __ sra(Rdivisor, 0, Rdivisor);
2595 __ sra(Rdividend, 0, Rdividend);
2596 __ sdivx(Rdividend, Rdivisor, Rresult);
2597 %}
2598
2599 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2600 MacroAssembler _masm(&cbuf);
2601
2602 Register Rdividend = reg_to_register_object($src1$$reg);
2603 int divisor = $imm$$constant;
2604 Register Rresult = reg_to_register_object($dst$$reg);
2605
2606 __ sra(Rdividend, 0, Rdividend);
2607 __ sdivx(Rdividend, divisor, Rresult);
2608 %}
2609
2610 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2611 MacroAssembler _masm(&cbuf);
2612 Register Rsrc1 = reg_to_register_object($src1$$reg);
2613 Register Rsrc2 = reg_to_register_object($src2$$reg);
2614 Register Rdst = reg_to_register_object($dst$$reg);
2615
2616 __ sra( Rsrc1, 0, Rsrc1 );
2617 __ sra( Rsrc2, 0, Rsrc2 );
2618 __ mulx( Rsrc1, Rsrc2, Rdst );
2619 __ srlx( Rdst, 32, Rdst );
2620 %}
2621
2622 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2623 MacroAssembler _masm(&cbuf);
2624 Register Rdividend = reg_to_register_object($src1$$reg);
2625 Register Rdivisor = reg_to_register_object($src2$$reg);
2626 Register Rresult = reg_to_register_object($dst$$reg);
2627 Register Rscratch = reg_to_register_object($scratch$$reg);
2628
2629 assert(Rdividend != Rscratch, "");
2630 assert(Rdivisor != Rscratch, "");
2631
2632 __ sra(Rdividend, 0, Rdividend);
2633 __ sra(Rdivisor, 0, Rdivisor);
2634 __ sdivx(Rdividend, Rdivisor, Rscratch);
2635 __ mulx(Rscratch, Rdivisor, Rscratch);
2636 __ sub(Rdividend, Rscratch, Rresult);
2637 %}
2638
2639 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2640 MacroAssembler _masm(&cbuf);
2641
2642 Register Rdividend = reg_to_register_object($src1$$reg);
2643 int divisor = $imm$$constant;
2644 Register Rresult = reg_to_register_object($dst$$reg);
2645 Register Rscratch = reg_to_register_object($scratch$$reg);
2646
2647 assert(Rdividend != Rscratch, "");
2648
2649 __ sra(Rdividend, 0, Rdividend);
2650 __ sdivx(Rdividend, divisor, Rscratch);
2651 __ mulx(Rscratch, divisor, Rscratch);
2652 __ sub(Rdividend, Rscratch, Rresult);
2653 %}
2654
2655 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2656 MacroAssembler _masm(&cbuf);
2657
2658 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2659 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2660
2661 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2662 %}
2663
2664 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2665 MacroAssembler _masm(&cbuf);
2666
2667 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2668 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2669
2670 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2671 %}
2672
2673 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2674 MacroAssembler _masm(&cbuf);
2675
2676 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2677 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2678
2679 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2680 %}
2681
2682 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2683 MacroAssembler _masm(&cbuf);
2684
2685 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2686 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2687
2688 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2689 %}
2690
2691 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2692 MacroAssembler _masm(&cbuf);
2693
2694 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2695 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2696
2697 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2698 %}
2699
2700 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2701 MacroAssembler _masm(&cbuf);
2702
2703 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2704 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2705
2706 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2707 %}
2708
2709 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2710 MacroAssembler _masm(&cbuf);
2711
2712 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2713 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2714
2715 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2716 %}
2717
2718 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2719 MacroAssembler _masm(&cbuf);
2720
2721 Register Roop = reg_to_register_object($oop$$reg);
2722 Register Rbox = reg_to_register_object($box$$reg);
2723 Register Rscratch = reg_to_register_object($scratch$$reg);
2724 Register Rmark = reg_to_register_object($scratch2$$reg);
2725
2726 assert(Roop != Rscratch, "");
2727 assert(Roop != Rmark, "");
2728 assert(Rbox != Rscratch, "");
2729 assert(Rbox != Rmark, "");
2730
2731 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2732 %}
2733
2734 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2735 MacroAssembler _masm(&cbuf);
2736
2737 Register Roop = reg_to_register_object($oop$$reg);
2738 Register Rbox = reg_to_register_object($box$$reg);
2739 Register Rscratch = reg_to_register_object($scratch$$reg);
2740 Register Rmark = reg_to_register_object($scratch2$$reg);
2741
2742 assert(Roop != Rscratch, "");
2743 assert(Roop != Rmark, "");
2744 assert(Rbox != Rscratch, "");
2745 assert(Rbox != Rmark, "");
2746
2747 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2748 %}
2749
2750 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2751 MacroAssembler _masm(&cbuf);
2752 Register Rmem = reg_to_register_object($mem$$reg);
2753 Register Rold = reg_to_register_object($old$$reg);
2754 Register Rnew = reg_to_register_object($new$$reg);
2755
2756 // casx_under_lock picks 1 of 3 encodings:
2757 // For 32-bit pointers you get a 32-bit CAS
2758 // For 64-bit pointers you get a 64-bit CASX
2759 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2760 __ cmp( Rold, Rnew );
2761 %}
2762
2763 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2764 Register Rmem = reg_to_register_object($mem$$reg);
2765 Register Rold = reg_to_register_object($old$$reg);
2766 Register Rnew = reg_to_register_object($new$$reg);
2767
2768 MacroAssembler _masm(&cbuf);
2769 __ mov(Rnew, O7);
2770 __ casx(Rmem, Rold, O7);
2771 __ cmp( Rold, O7 );
2772 %}
2773
2774 // raw int cas, used for compareAndSwap
2775 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2776 Register Rmem = reg_to_register_object($mem$$reg);
2777 Register Rold = reg_to_register_object($old$$reg);
2778 Register Rnew = reg_to_register_object($new$$reg);
2779
2780 MacroAssembler _masm(&cbuf);
2781 __ mov(Rnew, O7);
2782 __ cas(Rmem, Rold, O7);
2783 __ cmp( Rold, O7 );
2784 %}
2785
2786 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2787 Register Rres = reg_to_register_object($res$$reg);
2788
2789 MacroAssembler _masm(&cbuf);
2790 __ mov(1, Rres);
2791 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2792 %}
2793
2794 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2795 Register Rres = reg_to_register_object($res$$reg);
2796
2797 MacroAssembler _masm(&cbuf);
2798 __ mov(1, Rres);
2799 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2800 %}
2801
2802 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2803 MacroAssembler _masm(&cbuf);
2804 Register Rdst = reg_to_register_object($dst$$reg);
2805 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2806 : reg_to_DoubleFloatRegister_object($src1$$reg);
2807 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2808 : reg_to_DoubleFloatRegister_object($src2$$reg);
2809
2810 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2811 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2812 %}
2813
2814 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2815 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2816 MacroAssembler _masm(&cbuf);
2817 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2818 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2819 Register base_pointer_arg = reg_to_register_object($base$$reg);
2820
2821 Label loop;
2822 __ mov(nof_bytes_arg, nof_bytes_tmp);
2823
2824 // Loop and clear, walking backwards through the array.
2825 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2826 __ bind(loop);
2827 __ deccc(nof_bytes_tmp, 8);
2828 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2829 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2830 // %%%% this mini-loop must not cross a cache boundary!
2831 %}
2832
2833
2834 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2835 Label Ldone, Lloop;
2836 MacroAssembler _masm(&cbuf);
2837
2838 Register str1_reg = reg_to_register_object($str1$$reg);
2839 Register str2_reg = reg_to_register_object($str2$$reg);
2840 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2841 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2842 Register result_reg = reg_to_register_object($result$$reg);
2843
2844 assert(result_reg != str1_reg &&
2845 result_reg != str2_reg &&
2846 result_reg != cnt1_reg &&
2847 result_reg != cnt2_reg ,
2848 "need different registers");
2849
2850 // Compute the minimum of the string lengths(str1_reg) and the
2851 // difference of the string lengths (stack)
2852
2853 // See if the lengths are different, and calculate min in str1_reg.
2854 // Stash diff in O7 in case we need it for a tie-breaker.
2855 Label Lskip;
2856 __ subcc(cnt1_reg, cnt2_reg, O7);
2857 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2858 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2859 // cnt2 is shorter, so use its count:
2860 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2861 __ bind(Lskip);
2862
2863 // reallocate cnt1_reg, cnt2_reg, result_reg
2864 // Note: limit_reg holds the string length pre-scaled by 2
2865 Register limit_reg = cnt1_reg;
2866 Register chr2_reg = cnt2_reg;
2867 Register chr1_reg = result_reg;
2868 // str{12} are the base pointers
2869
2870 // Is the minimum length zero?
2871 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2872 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2873 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2874
2875 // Load first characters
2876 __ lduh(str1_reg, 0, chr1_reg);
2877 __ lduh(str2_reg, 0, chr2_reg);
2878
2879 // Compare first characters
2880 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2881 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2882 assert(chr1_reg == result_reg, "result must be pre-placed");
2883 __ delayed()->nop();
2884
2885 {
2886 // Check after comparing first character to see if strings are equivalent
2887 Label LSkip2;
2888 // Check if the strings start at same location
2889 __ cmp(str1_reg, str2_reg);
2890 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2891 __ delayed()->nop();
2892
2893 // Check if the length difference is zero (in O7)
2894 __ cmp(G0, O7);
2895 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2896 __ delayed()->mov(G0, result_reg); // result is zero
2897
2898 // Strings might not be equal
2899 __ bind(LSkip2);
2900 }
2901
2902 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2903 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2904 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2905
2906 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2907 __ add(str1_reg, limit_reg, str1_reg);
2908 __ add(str2_reg, limit_reg, str2_reg);
2909 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2910
2911 // Compare the rest of the characters
2912 __ lduh(str1_reg, limit_reg, chr1_reg);
2913 __ bind(Lloop);
2914 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2915 __ lduh(str2_reg, limit_reg, chr2_reg);
2916 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2917 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2918 assert(chr1_reg == result_reg, "result must be pre-placed");
2919 __ delayed()->inccc(limit_reg, sizeof(jchar));
2920 // annul LDUH if branch is not taken to prevent access past end of string
2921 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2922 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2923
2924 // If strings are equal up to min length, return the length difference.
2925 __ mov(O7, result_reg);
2926
2927 // Otherwise, return the difference between the first mismatched chars.
2928 __ bind(Ldone);
2929 %}
2930
2931 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2932 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2933 MacroAssembler _masm(&cbuf);
2934
2935 Register str1_reg = reg_to_register_object($str1$$reg);
2936 Register str2_reg = reg_to_register_object($str2$$reg);
2937 Register cnt_reg = reg_to_register_object($cnt$$reg);
2938 Register tmp1_reg = O7;
2939 Register result_reg = reg_to_register_object($result$$reg);
2940
2941 assert(result_reg != str1_reg &&
2942 result_reg != str2_reg &&
2943 result_reg != cnt_reg &&
2944 result_reg != tmp1_reg ,
2945 "need different registers");
2946
2947 __ cmp(str1_reg, str2_reg); //same char[] ?
2948 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2949 __ delayed()->add(G0, 1, result_reg);
2950
2951 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2952 __ delayed()->add(G0, 1, result_reg); // count == 0
2953
2954 //rename registers
2955 Register limit_reg = cnt_reg;
2956 Register chr1_reg = result_reg;
2957 Register chr2_reg = tmp1_reg;
2958
2959 //check for alignment and position the pointers to the ends
2960 __ or3(str1_reg, str2_reg, chr1_reg);
2961 __ andcc(chr1_reg, 0x3, chr1_reg);
2962 // notZero means at least one not 4-byte aligned.
2963 // We could optimize the case when both arrays are not aligned
2964 // but it is not frequent case and it requires additional checks.
2965 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2966 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2967
2968 // Compare char[] arrays aligned to 4 bytes.
2969 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2970 chr1_reg, chr2_reg, Ldone);
2971 __ ba(Ldone);
2972 __ delayed()->add(G0, 1, result_reg);
2973
2974 // char by char compare
2975 __ bind(Lchar);
2976 __ add(str1_reg, limit_reg, str1_reg);
2977 __ add(str2_reg, limit_reg, str2_reg);
2978 __ neg(limit_reg); //negate count
2979
2980 __ lduh(str1_reg, limit_reg, chr1_reg);
2981 // Lchar_loop
2982 __ bind(Lchar_loop);
2983 __ lduh(str2_reg, limit_reg, chr2_reg);
2984 __ cmp(chr1_reg, chr2_reg);
2985 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2986 __ delayed()->mov(G0, result_reg); //not equal
2987 __ inccc(limit_reg, sizeof(jchar));
2988 // annul LDUH if branch is not taken to prevent access past end of string
2989 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
2990 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2991
2992 __ add(G0, 1, result_reg); //equal
2993
2994 __ bind(Ldone);
2995 %}
2996
2997 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
2998 Label Lvector, Ldone, Lloop;
2999 MacroAssembler _masm(&cbuf);
3000
3001 Register ary1_reg = reg_to_register_object($ary1$$reg);
3002 Register ary2_reg = reg_to_register_object($ary2$$reg);
3003 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3004 Register tmp2_reg = O7;
3005 Register result_reg = reg_to_register_object($result$$reg);
3006
3007 int length_offset = arrayOopDesc::length_offset_in_bytes();
3008 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3009
3010 // return true if the same array
3011 __ cmp(ary1_reg, ary2_reg);
3012 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3013 __ delayed()->add(G0, 1, result_reg); // equal
3014
3015 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3016 __ delayed()->mov(G0, result_reg); // not equal
3017
3018 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3019 __ delayed()->mov(G0, result_reg); // not equal
3020
3021 //load the lengths of arrays
3022 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3023 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3024
3025 // return false if the two arrays are not equal length
3026 __ cmp(tmp1_reg, tmp2_reg);
3027 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3028 __ delayed()->mov(G0, result_reg); // not equal
3029
3030 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3031 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3032
3033 // load array addresses
3034 __ add(ary1_reg, base_offset, ary1_reg);
3035 __ add(ary2_reg, base_offset, ary2_reg);
3036
3037 // renaming registers
3038 Register chr1_reg = result_reg; // for characters in ary1
3039 Register chr2_reg = tmp2_reg; // for characters in ary2
3040 Register limit_reg = tmp1_reg; // length
3041
3042 // set byte count
3043 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3044
3045 // Compare char[] arrays aligned to 4 bytes.
3046 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3047 chr1_reg, chr2_reg, Ldone);
3048 __ add(G0, 1, result_reg); // equals
3049
3050 __ bind(Ldone);
3051 %}
3052
3053 enc_class enc_rethrow() %{
3054 cbuf.set_insts_mark();
3055 Register temp_reg = G3;
3056 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3057 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3058 MacroAssembler _masm(&cbuf);
3059 #ifdef ASSERT
3060 __ save_frame(0);
3061 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3062 __ sethi(last_rethrow_addrlit, L1);
3063 Address addr(L1, last_rethrow_addrlit.low10());
3064 __ get_pc(L2);
3065 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3066 __ st_ptr(L2, addr);
3067 __ restore();
3068 #endif
3069 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3070 __ delayed()->nop();
3071 %}
3072
3073 enc_class emit_mem_nop() %{
3074 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3075 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3076 %}
3077
3078 enc_class emit_fadd_nop() %{
3079 // Generates the instruction FMOVS f31,f31
3080 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3081 %}
3082
3083 enc_class emit_br_nop() %{
3084 // Generates the instruction BPN,PN .
3085 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3086 %}
3087
3088 enc_class enc_membar_acquire %{
3089 MacroAssembler _masm(&cbuf);
3090 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3091 %}
3092
3093 enc_class enc_membar_release %{
3094 MacroAssembler _masm(&cbuf);
3095 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3096 %}
3097
3098 enc_class enc_membar_volatile %{
3099 MacroAssembler _masm(&cbuf);
3100 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3101 %}
3102
3103 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3104 MacroAssembler _masm(&cbuf);
3105 Register src_reg = reg_to_register_object($src$$reg);
3106 Register dst_reg = reg_to_register_object($dst$$reg);
3107 __ sllx(src_reg, 56, dst_reg);
3108 __ srlx(dst_reg, 8, O7);
3109 __ or3 (dst_reg, O7, dst_reg);
3110 __ srlx(dst_reg, 16, O7);
3111 __ or3 (dst_reg, O7, dst_reg);
3112 __ srlx(dst_reg, 32, O7);
3113 __ or3 (dst_reg, O7, dst_reg);
3114 %}
3115
3116 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3117 MacroAssembler _masm(&cbuf);
3118 Register src_reg = reg_to_register_object($src$$reg);
3119 Register dst_reg = reg_to_register_object($dst$$reg);
3120 __ sll(src_reg, 24, dst_reg);
3121 __ srl(dst_reg, 8, O7);
3122 __ or3(dst_reg, O7, dst_reg);
3123 __ srl(dst_reg, 16, O7);
3124 __ or3(dst_reg, O7, dst_reg);
3125 %}
3126
3127 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3128 MacroAssembler _masm(&cbuf);
3129 Register src_reg = reg_to_register_object($src$$reg);
3130 Register dst_reg = reg_to_register_object($dst$$reg);
3131 __ sllx(src_reg, 48, dst_reg);
3132 __ srlx(dst_reg, 16, O7);
3133 __ or3 (dst_reg, O7, dst_reg);
3134 __ srlx(dst_reg, 32, O7);
3135 __ or3 (dst_reg, O7, dst_reg);
3136 %}
3137
3138 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3139 MacroAssembler _masm(&cbuf);
3140 Register src_reg = reg_to_register_object($src$$reg);
3141 Register dst_reg = reg_to_register_object($dst$$reg);
3142 __ sllx(src_reg, 32, dst_reg);
3143 __ srlx(dst_reg, 32, O7);
3144 __ or3 (dst_reg, O7, dst_reg);
3145 %}
3146
3147 %}
3148
3149 //----------FRAME--------------------------------------------------------------
3150 // Definition of frame structure and management information.
3151 //
3152 // S T A C K L A Y O U T Allocators stack-slot number
3153 // | (to get allocators register number
3154 // G Owned by | | v add VMRegImpl::stack0)
3155 // r CALLER | |
3156 // o | +--------+ pad to even-align allocators stack-slot
3157 // w V | pad0 | numbers; owned by CALLER
3158 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3159 // h ^ | in | 5
3160 // | | args | 4 Holes in incoming args owned by SELF
3161 // | | | | 3
3162 // | | +--------+
3163 // V | | old out| Empty on Intel, window on Sparc
3164 // | old |preserve| Must be even aligned.
3165 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3166 // | | in | 3 area for Intel ret address
3167 // Owned by |preserve| Empty on Sparc.
3168 // SELF +--------+
3169 // | | pad2 | 2 pad to align old SP
3170 // | +--------+ 1
3171 // | | locks | 0
3172 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3173 // | | pad1 | 11 pad to align new SP
3174 // | +--------+
3175 // | | | 10
3176 // | | spills | 9 spills
3177 // V | | 8 (pad0 slot for callee)
3178 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3179 // ^ | out | 7
3180 // | | args | 6 Holes in outgoing args owned by CALLEE
3181 // Owned by +--------+
3182 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3183 // | new |preserve| Must be even-aligned.
3184 // | SP-+--------+----> Matcher::_new_SP, even aligned
3185 // | | |
3186 //
3187 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3188 // known from SELF's arguments and the Java calling convention.
3189 // Region 6-7 is determined per call site.
3190 // Note 2: If the calling convention leaves holes in the incoming argument
3191 // area, those holes are owned by SELF. Holes in the outgoing area
3192 // are owned by the CALLEE. Holes should not be nessecary in the
3193 // incoming area, as the Java calling convention is completely under
3194 // the control of the AD file. Doubles can be sorted and packed to
3195 // avoid holes. Holes in the outgoing arguments may be nessecary for
3196 // varargs C calling conventions.
3197 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3198 // even aligned with pad0 as needed.
3199 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3200 // region 6-11 is even aligned; it may be padded out more so that
3201 // the region from SP to FP meets the minimum stack alignment.
3202
3203 frame %{
3204 // What direction does stack grow in (assumed to be same for native & Java)
3205 stack_direction(TOWARDS_LOW);
3206
3207 // These two registers define part of the calling convention
3208 // between compiled code and the interpreter.
3209 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3210 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3211
3212 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3213 cisc_spilling_operand_name(indOffset);
3214
3215 // Number of stack slots consumed by a Monitor enter
3216 #ifdef _LP64
3217 sync_stack_slots(2);
3218 #else
3219 sync_stack_slots(1);
3220 #endif
3221
3222 // Compiled code's Frame Pointer
3223 frame_pointer(R_SP);
3224
3225 // Stack alignment requirement
3226 stack_alignment(StackAlignmentInBytes);
3227 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3228 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3229
3230 // Number of stack slots between incoming argument block and the start of
3231 // a new frame. The PROLOG must add this many slots to the stack. The
3232 // EPILOG must remove this many slots.
3233 in_preserve_stack_slots(0);
3234
3235 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3236 // for calls to C. Supports the var-args backing area for register parms.
3237 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3238 #ifdef _LP64
3239 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3240 varargs_C_out_slots_killed(12);
3241 #else
3242 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3243 varargs_C_out_slots_killed( 7);
3244 #endif
3245
3246 // The after-PROLOG location of the return address. Location of
3247 // return address specifies a type (REG or STACK) and a number
3248 // representing the register number (i.e. - use a register name) or
3249 // stack slot.
3250 return_addr(REG R_I7); // Ret Addr is in register I7
3251
3252 // Body of function which returns an OptoRegs array locating
3253 // arguments either in registers or in stack slots for calling
3254 // java
3255 calling_convention %{
3256 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3257
3258 %}
3259
3260 // Body of function which returns an OptoRegs array locating
3261 // arguments either in registers or in stack slots for callin
3262 // C.
3263 c_calling_convention %{
3264 // This is obviously always outgoing
3265 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3266 %}
3267
3268 // Location of native (C/C++) and interpreter return values. This is specified to
3269 // be the same as Java. In the 32-bit VM, long values are actually returned from
3270 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3271 // to and from the register pairs is done by the appropriate call and epilog
3272 // opcodes. This simplifies the register allocator.
3273 c_return_value %{
3274 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3275 #ifdef _LP64
3276 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3277 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3278 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3279 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3280 #else // !_LP64
3281 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3282 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3283 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3284 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3285 #endif
3286 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3287 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3288 %}
3289
3290 // Location of compiled Java return values. Same as C
3291 return_value %{
3292 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3293 #ifdef _LP64
3294 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3295 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3296 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3297 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3298 #else // !_LP64
3299 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3300 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3301 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3302 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3303 #endif
3304 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3305 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3306 %}
3307
3308 %}
3309
3310
3311 //----------ATTRIBUTES---------------------------------------------------------
3312 //----------Operand Attributes-------------------------------------------------
3313 op_attrib op_cost(1); // Required cost attribute
3314
3315 //----------Instruction Attributes---------------------------------------------
3316 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3317 ins_attrib ins_size(32); // Required size attribute (in bits)
3318 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3319 // non-matching short branch variant of some
3320 // long branch?
3321
3322 //----------OPERANDS-----------------------------------------------------------
3323 // Operand definitions must precede instruction definitions for correct parsing
3324 // in the ADLC because operands constitute user defined types which are used in
3325 // instruction definitions.
3326
3327 //----------Simple Operands----------------------------------------------------
3328 // Immediate Operands
3329 // Integer Immediate: 32-bit
3330 operand immI() %{
3331 match(ConI);
3332
3333 op_cost(0);
3334 // formats are generated automatically for constants and base registers
3335 format %{ %}
3336 interface(CONST_INTER);
3337 %}
3338
3339 // Integer Immediate: 8-bit
3340 operand immI8() %{
3341 predicate(Assembler::is_simm(n->get_int(), 8));
3342 match(ConI);
3343 op_cost(0);
3344 format %{ %}
3345 interface(CONST_INTER);
3346 %}
3347
3348 // Integer Immediate: 13-bit
3349 operand immI13() %{
3350 predicate(Assembler::is_simm13(n->get_int()));
3351 match(ConI);
3352 op_cost(0);
3353
3354 format %{ %}
3355 interface(CONST_INTER);
3356 %}
3357
3358 // Integer Immediate: 13-bit minus 7
3359 operand immI13m7() %{
3360 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3361 match(ConI);
3362 op_cost(0);
3363
3364 format %{ %}
3365 interface(CONST_INTER);
3366 %}
3367
3368 // Integer Immediate: 16-bit
3369 operand immI16() %{
3370 predicate(Assembler::is_simm(n->get_int(), 16));
3371 match(ConI);
3372 op_cost(0);
3373 format %{ %}
3374 interface(CONST_INTER);
3375 %}
3376
3377 // Unsigned (positive) Integer Immediate: 13-bit
3378 operand immU13() %{
3379 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3380 match(ConI);
3381 op_cost(0);
3382
3383 format %{ %}
3384 interface(CONST_INTER);
3385 %}
3386
3387 // Integer Immediate: 6-bit
3388 operand immU6() %{
3389 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3390 match(ConI);
3391 op_cost(0);
3392 format %{ %}
3393 interface(CONST_INTER);
3394 %}
3395
3396 // Integer Immediate: 11-bit
3397 operand immI11() %{
3398 predicate(Assembler::is_simm(n->get_int(),11));
3399 match(ConI);
3400 op_cost(0);
3401 format %{ %}
3402 interface(CONST_INTER);
3403 %}
3404
3405 // Integer Immediate: 0-bit
3406 operand immI0() %{
3407 predicate(n->get_int() == 0);
3408 match(ConI);
3409 op_cost(0);
3410
3411 format %{ %}
3412 interface(CONST_INTER);
3413 %}
3414
3415 // Integer Immediate: the value 10
3416 operand immI10() %{
3417 predicate(n->get_int() == 10);
3418 match(ConI);
3419 op_cost(0);
3420
3421 format %{ %}
3422 interface(CONST_INTER);
3423 %}
3424
3425 // Integer Immediate: the values 0-31
3426 operand immU5() %{
3427 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3428 match(ConI);
3429 op_cost(0);
3430
3431 format %{ %}
3432 interface(CONST_INTER);
3433 %}
3434
3435 // Integer Immediate: the values 1-31
3436 operand immI_1_31() %{
3437 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3438 match(ConI);
3439 op_cost(0);
3440
3441 format %{ %}
3442 interface(CONST_INTER);
3443 %}
3444
3445 // Integer Immediate: the values 32-63
3446 operand immI_32_63() %{
3447 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3448 match(ConI);
3449 op_cost(0);
3450
3451 format %{ %}
3452 interface(CONST_INTER);
3453 %}
3454
3455 // Immediates for special shifts (sign extend)
3456
3457 // Integer Immediate: the value 16
3458 operand immI_16() %{
3459 predicate(n->get_int() == 16);
3460 match(ConI);
3461 op_cost(0);
3462
3463 format %{ %}
3464 interface(CONST_INTER);
3465 %}
3466
3467 // Integer Immediate: the value 24
3468 operand immI_24() %{
3469 predicate(n->get_int() == 24);
3470 match(ConI);
3471 op_cost(0);
3472
3473 format %{ %}
3474 interface(CONST_INTER);
3475 %}
3476
3477 // Integer Immediate: the value 255
3478 operand immI_255() %{
3479 predicate( n->get_int() == 255 );
3480 match(ConI);
3481 op_cost(0);
3482
3483 format %{ %}
3484 interface(CONST_INTER);
3485 %}
3486
3487 // Integer Immediate: the value 65535
3488 operand immI_65535() %{
3489 predicate(n->get_int() == 65535);
3490 match(ConI);
3491 op_cost(0);
3492
3493 format %{ %}
3494 interface(CONST_INTER);
3495 %}
3496
3497 // Long Immediate: the value FF
3498 operand immL_FF() %{
3499 predicate( n->get_long() == 0xFFL );
3500 match(ConL);
3501 op_cost(0);
3502
3503 format %{ %}
3504 interface(CONST_INTER);
3505 %}
3506
3507 // Long Immediate: the value FFFF
3508 operand immL_FFFF() %{
3509 predicate( n->get_long() == 0xFFFFL );
3510 match(ConL);
3511 op_cost(0);
3512
3513 format %{ %}
3514 interface(CONST_INTER);
3515 %}
3516
3517 // Pointer Immediate: 32 or 64-bit
3518 operand immP() %{
3519 match(ConP);
3520
3521 op_cost(5);
3522 // formats are generated automatically for constants and base registers
3523 format %{ %}
3524 interface(CONST_INTER);
3525 %}
3526
3527 #ifdef _LP64
3528 // Pointer Immediate: 64-bit
3529 operand immP_set() %{
3530 predicate(!VM_Version::is_niagara_plus());
3531 match(ConP);
3532
3533 op_cost(5);
3534 // formats are generated automatically for constants and base registers
3535 format %{ %}
3536 interface(CONST_INTER);
3537 %}
3538
3539 // Pointer Immediate: 64-bit
3540 // From Niagara2 processors on a load should be better than materializing.
3541 operand immP_load() %{
3542 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3543 match(ConP);
3544
3545 op_cost(5);
3546 // formats are generated automatically for constants and base registers
3547 format %{ %}
3548 interface(CONST_INTER);
3549 %}
3550
3551 // Pointer Immediate: 64-bit
3552 operand immP_no_oop_cheap() %{
3553 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3554 match(ConP);
3555
3556 op_cost(5);
3557 // formats are generated automatically for constants and base registers
3558 format %{ %}
3559 interface(CONST_INTER);
3560 %}
3561 #endif
3562
3563 operand immP13() %{
3564 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3565 match(ConP);
3566 op_cost(0);
3567
3568 format %{ %}
3569 interface(CONST_INTER);
3570 %}
3571
3572 operand immP0() %{
3573 predicate(n->get_ptr() == 0);
3574 match(ConP);
3575 op_cost(0);
3576
3577 format %{ %}
3578 interface(CONST_INTER);
3579 %}
3580
3581 operand immP_poll() %{
3582 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3583 match(ConP);
3584
3585 // formats are generated automatically for constants and base registers
3586 format %{ %}
3587 interface(CONST_INTER);
3588 %}
3589
3590 // Pointer Immediate
3591 operand immN()
3592 %{
3593 match(ConN);
3594
3595 op_cost(10);
3596 format %{ %}
3597 interface(CONST_INTER);
3598 %}
3599
3600 // NULL Pointer Immediate
3601 operand immN0()
3602 %{
3603 predicate(n->get_narrowcon() == 0);
3604 match(ConN);
3605
3606 op_cost(0);
3607 format %{ %}
3608 interface(CONST_INTER);
3609 %}
3610
3611 operand immL() %{
3612 match(ConL);
3613 op_cost(40);
3614 // formats are generated automatically for constants and base registers
3615 format %{ %}
3616 interface(CONST_INTER);
3617 %}
3618
3619 operand immL0() %{
3620 predicate(n->get_long() == 0L);
3621 match(ConL);
3622 op_cost(0);
3623 // formats are generated automatically for constants and base registers
3624 format %{ %}
3625 interface(CONST_INTER);
3626 %}
3627
3628 // Long Immediate: 13-bit
3629 operand immL13() %{
3630 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3631 match(ConL);
3632 op_cost(0);
3633
3634 format %{ %}
3635 interface(CONST_INTER);
3636 %}
3637
3638 // Long Immediate: 13-bit minus 7
3639 operand immL13m7() %{
3640 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3641 match(ConL);
3642 op_cost(0);
3643
3644 format %{ %}
3645 interface(CONST_INTER);
3646 %}
3647
3648 // Long Immediate: low 32-bit mask
3649 operand immL_32bits() %{
3650 predicate(n->get_long() == 0xFFFFFFFFL);
3651 match(ConL);
3652 op_cost(0);
3653
3654 format %{ %}
3655 interface(CONST_INTER);
3656 %}
3657
3658 // Long Immediate: cheap (materialize in <= 3 instructions)
3659 operand immL_cheap() %{
3660 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3661 match(ConL);
3662 op_cost(0);
3663
3664 format %{ %}
3665 interface(CONST_INTER);
3666 %}
3667
3668 // Long Immediate: expensive (materialize in > 3 instructions)
3669 operand immL_expensive() %{
3670 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3671 match(ConL);
3672 op_cost(0);
3673
3674 format %{ %}
3675 interface(CONST_INTER);
3676 %}
3677
3678 // Double Immediate
3679 operand immD() %{
3680 match(ConD);
3681
3682 op_cost(40);
3683 format %{ %}
3684 interface(CONST_INTER);
3685 %}
3686
3687 operand immD0() %{
3688 #ifdef _LP64
3689 // on 64-bit architectures this comparision is faster
3690 predicate(jlong_cast(n->getd()) == 0);
3691 #else
3692 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3693 #endif
3694 match(ConD);
3695
3696 op_cost(0);
3697 format %{ %}
3698 interface(CONST_INTER);
3699 %}
3700
3701 // Float Immediate
3702 operand immF() %{
3703 match(ConF);
3704
3705 op_cost(20);
3706 format %{ %}
3707 interface(CONST_INTER);
3708 %}
3709
3710 // Float Immediate: 0
3711 operand immF0() %{
3712 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3713 match(ConF);
3714
3715 op_cost(0);
3716 format %{ %}
3717 interface(CONST_INTER);
3718 %}
3719
3720 // Integer Register Operands
3721 // Integer Register
3722 operand iRegI() %{
3723 constraint(ALLOC_IN_RC(int_reg));
3724 match(RegI);
3725
3726 match(notemp_iRegI);
3727 match(g1RegI);
3728 match(o0RegI);
3729 match(iRegIsafe);
3730
3731 format %{ %}
3732 interface(REG_INTER);
3733 %}
3734
3735 operand notemp_iRegI() %{
3736 constraint(ALLOC_IN_RC(notemp_int_reg));
3737 match(RegI);
3738
3739 match(o0RegI);
3740
3741 format %{ %}
3742 interface(REG_INTER);
3743 %}
3744
3745 operand o0RegI() %{
3746 constraint(ALLOC_IN_RC(o0_regI));
3747 match(iRegI);
3748
3749 format %{ %}
3750 interface(REG_INTER);
3751 %}
3752
3753 // Pointer Register
3754 operand iRegP() %{
3755 constraint(ALLOC_IN_RC(ptr_reg));
3756 match(RegP);
3757
3758 match(lock_ptr_RegP);
3759 match(g1RegP);
3760 match(g2RegP);
3761 match(g3RegP);
3762 match(g4RegP);
3763 match(i0RegP);
3764 match(o0RegP);
3765 match(o1RegP);
3766 match(l7RegP);
3767
3768 format %{ %}
3769 interface(REG_INTER);
3770 %}
3771
3772 operand sp_ptr_RegP() %{
3773 constraint(ALLOC_IN_RC(sp_ptr_reg));
3774 match(RegP);
3775 match(iRegP);
3776
3777 format %{ %}
3778 interface(REG_INTER);
3779 %}
3780
3781 operand lock_ptr_RegP() %{
3782 constraint(ALLOC_IN_RC(lock_ptr_reg));
3783 match(RegP);
3784 match(i0RegP);
3785 match(o0RegP);
3786 match(o1RegP);
3787 match(l7RegP);
3788
3789 format %{ %}
3790 interface(REG_INTER);
3791 %}
3792
3793 operand g1RegP() %{
3794 constraint(ALLOC_IN_RC(g1_regP));
3795 match(iRegP);
3796
3797 format %{ %}
3798 interface(REG_INTER);
3799 %}
3800
3801 operand g2RegP() %{
3802 constraint(ALLOC_IN_RC(g2_regP));
3803 match(iRegP);
3804
3805 format %{ %}
3806 interface(REG_INTER);
3807 %}
3808
3809 operand g3RegP() %{
3810 constraint(ALLOC_IN_RC(g3_regP));
3811 match(iRegP);
3812
3813 format %{ %}
3814 interface(REG_INTER);
3815 %}
3816
3817 operand g1RegI() %{
3818 constraint(ALLOC_IN_RC(g1_regI));
3819 match(iRegI);
3820
3821 format %{ %}
3822 interface(REG_INTER);
3823 %}
3824
3825 operand g3RegI() %{
3826 constraint(ALLOC_IN_RC(g3_regI));
3827 match(iRegI);
3828
3829 format %{ %}
3830 interface(REG_INTER);
3831 %}
3832
3833 operand g4RegI() %{
3834 constraint(ALLOC_IN_RC(g4_regI));
3835 match(iRegI);
3836
3837 format %{ %}
3838 interface(REG_INTER);
3839 %}
3840
3841 operand g4RegP() %{
3842 constraint(ALLOC_IN_RC(g4_regP));
3843 match(iRegP);
3844
3845 format %{ %}
3846 interface(REG_INTER);
3847 %}
3848
3849 operand i0RegP() %{
3850 constraint(ALLOC_IN_RC(i0_regP));
3851 match(iRegP);
3852
3853 format %{ %}
3854 interface(REG_INTER);
3855 %}
3856
3857 operand o0RegP() %{
3858 constraint(ALLOC_IN_RC(o0_regP));
3859 match(iRegP);
3860
3861 format %{ %}
3862 interface(REG_INTER);
3863 %}
3864
3865 operand o1RegP() %{
3866 constraint(ALLOC_IN_RC(o1_regP));
3867 match(iRegP);
3868
3869 format %{ %}
3870 interface(REG_INTER);
3871 %}
3872
3873 operand o2RegP() %{
3874 constraint(ALLOC_IN_RC(o2_regP));
3875 match(iRegP);
3876
3877 format %{ %}
3878 interface(REG_INTER);
3879 %}
3880
3881 operand o7RegP() %{
3882 constraint(ALLOC_IN_RC(o7_regP));
3883 match(iRegP);
3884
3885 format %{ %}
3886 interface(REG_INTER);
3887 %}
3888
3889 operand l7RegP() %{
3890 constraint(ALLOC_IN_RC(l7_regP));
3891 match(iRegP);
3892
3893 format %{ %}
3894 interface(REG_INTER);
3895 %}
3896
3897 operand o7RegI() %{
3898 constraint(ALLOC_IN_RC(o7_regI));
3899 match(iRegI);
3900
3901 format %{ %}
3902 interface(REG_INTER);
3903 %}
3904
3905 operand iRegN() %{
3906 constraint(ALLOC_IN_RC(int_reg));
3907 match(RegN);
3908
3909 format %{ %}
3910 interface(REG_INTER);
3911 %}
3912
3913 // Long Register
3914 operand iRegL() %{
3915 constraint(ALLOC_IN_RC(long_reg));
3916 match(RegL);
3917
3918 format %{ %}
3919 interface(REG_INTER);
3920 %}
3921
3922 operand o2RegL() %{
3923 constraint(ALLOC_IN_RC(o2_regL));
3924 match(iRegL);
3925
3926 format %{ %}
3927 interface(REG_INTER);
3928 %}
3929
3930 operand o7RegL() %{
3931 constraint(ALLOC_IN_RC(o7_regL));
3932 match(iRegL);
3933
3934 format %{ %}
3935 interface(REG_INTER);
3936 %}
3937
3938 operand g1RegL() %{
3939 constraint(ALLOC_IN_RC(g1_regL));
3940 match(iRegL);
3941
3942 format %{ %}
3943 interface(REG_INTER);
3944 %}
3945
3946 operand g3RegL() %{
3947 constraint(ALLOC_IN_RC(g3_regL));
3948 match(iRegL);
3949
3950 format %{ %}
3951 interface(REG_INTER);
3952 %}
3953
3954 // Int Register safe
3955 // This is 64bit safe
3956 operand iRegIsafe() %{
3957 constraint(ALLOC_IN_RC(long_reg));
3958
3959 match(iRegI);
3960
3961 format %{ %}
3962 interface(REG_INTER);
3963 %}
3964
3965 // Condition Code Flag Register
3966 operand flagsReg() %{
3967 constraint(ALLOC_IN_RC(int_flags));
3968 match(RegFlags);
3969
3970 format %{ "ccr" %} // both ICC and XCC
3971 interface(REG_INTER);
3972 %}
3973
3974 // Condition Code Register, unsigned comparisons.
3975 operand flagsRegU() %{
3976 constraint(ALLOC_IN_RC(int_flags));
3977 match(RegFlags);
3978
3979 format %{ "icc_U" %}
3980 interface(REG_INTER);
3981 %}
3982
3983 // Condition Code Register, pointer comparisons.
3984 operand flagsRegP() %{
3985 constraint(ALLOC_IN_RC(int_flags));
3986 match(RegFlags);
3987
3988 #ifdef _LP64
3989 format %{ "xcc_P" %}
3990 #else
3991 format %{ "icc_P" %}
3992 #endif
3993 interface(REG_INTER);
3994 %}
3995
3996 // Condition Code Register, long comparisons.
3997 operand flagsRegL() %{
3998 constraint(ALLOC_IN_RC(int_flags));
3999 match(RegFlags);
4000
4001 format %{ "xcc_L" %}
4002 interface(REG_INTER);
4003 %}
4004
4005 // Condition Code Register, floating comparisons, unordered same as "less".
4006 operand flagsRegF() %{
4007 constraint(ALLOC_IN_RC(float_flags));
4008 match(RegFlags);
4009 match(flagsRegF0);
4010
4011 format %{ %}
4012 interface(REG_INTER);
4013 %}
4014
4015 operand flagsRegF0() %{
4016 constraint(ALLOC_IN_RC(float_flag0));
4017 match(RegFlags);
4018
4019 format %{ %}
4020 interface(REG_INTER);
4021 %}
4022
4023
4024 // Condition Code Flag Register used by long compare
4025 operand flagsReg_long_LTGE() %{
4026 constraint(ALLOC_IN_RC(int_flags));
4027 match(RegFlags);
4028 format %{ "icc_LTGE" %}
4029 interface(REG_INTER);
4030 %}
4031 operand flagsReg_long_EQNE() %{
4032 constraint(ALLOC_IN_RC(int_flags));
4033 match(RegFlags);
4034 format %{ "icc_EQNE" %}
4035 interface(REG_INTER);
4036 %}
4037 operand flagsReg_long_LEGT() %{
4038 constraint(ALLOC_IN_RC(int_flags));
4039 match(RegFlags);
4040 format %{ "icc_LEGT" %}
4041 interface(REG_INTER);
4042 %}
4043
4044
4045 operand regD() %{
4046 constraint(ALLOC_IN_RC(dflt_reg));
4047 match(RegD);
4048
4049 match(regD_low);
4050
4051 format %{ %}
4052 interface(REG_INTER);
4053 %}
4054
4055 operand regF() %{
4056 constraint(ALLOC_IN_RC(sflt_reg));
4057 match(RegF);
4058
4059 format %{ %}
4060 interface(REG_INTER);
4061 %}
4062
4063 operand regD_low() %{
4064 constraint(ALLOC_IN_RC(dflt_low_reg));
4065 match(regD);
4066
4067 format %{ %}
4068 interface(REG_INTER);
4069 %}
4070
4071 // Special Registers
4072
4073 // Method Register
4074 operand inline_cache_regP(iRegP reg) %{
4075 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4076 match(reg);
4077 format %{ %}
4078 interface(REG_INTER);
4079 %}
4080
4081 operand interpreter_method_oop_regP(iRegP reg) %{
4082 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4083 match(reg);
4084 format %{ %}
4085 interface(REG_INTER);
4086 %}
4087
4088
4089 //----------Complex Operands---------------------------------------------------
4090 // Indirect Memory Reference
4091 operand indirect(sp_ptr_RegP reg) %{
4092 constraint(ALLOC_IN_RC(sp_ptr_reg));
4093 match(reg);
4094
4095 op_cost(100);
4096 format %{ "[$reg]" %}
4097 interface(MEMORY_INTER) %{
4098 base($reg);
4099 index(0x0);
4100 scale(0x0);
4101 disp(0x0);
4102 %}
4103 %}
4104
4105 // Indirect with simm13 Offset
4106 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4107 constraint(ALLOC_IN_RC(sp_ptr_reg));
4108 match(AddP reg offset);
4109
4110 op_cost(100);
4111 format %{ "[$reg + $offset]" %}
4112 interface(MEMORY_INTER) %{
4113 base($reg);
4114 index(0x0);
4115 scale(0x0);
4116 disp($offset);
4117 %}
4118 %}
4119
4120 // Indirect with simm13 Offset minus 7
4121 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4122 constraint(ALLOC_IN_RC(sp_ptr_reg));
4123 match(AddP reg offset);
4124
4125 op_cost(100);
4126 format %{ "[$reg + $offset]" %}
4127 interface(MEMORY_INTER) %{
4128 base($reg);
4129 index(0x0);
4130 scale(0x0);
4131 disp($offset);
4132 %}
4133 %}
4134
4135 // Note: Intel has a swapped version also, like this:
4136 //operand indOffsetX(iRegI reg, immP offset) %{
4137 // constraint(ALLOC_IN_RC(int_reg));
4138 // match(AddP offset reg);
4139 //
4140 // op_cost(100);
4141 // format %{ "[$reg + $offset]" %}
4142 // interface(MEMORY_INTER) %{
4143 // base($reg);
4144 // index(0x0);
4145 // scale(0x0);
4146 // disp($offset);
4147 // %}
4148 //%}
4149 //// However, it doesn't make sense for SPARC, since
4150 // we have no particularly good way to embed oops in
4151 // single instructions.
4152
4153 // Indirect with Register Index
4154 operand indIndex(iRegP addr, iRegX index) %{
4155 constraint(ALLOC_IN_RC(ptr_reg));
4156 match(AddP addr index);
4157
4158 op_cost(100);
4159 format %{ "[$addr + $index]" %}
4160 interface(MEMORY_INTER) %{
4161 base($addr);
4162 index($index);
4163 scale(0x0);
4164 disp(0x0);
4165 %}
4166 %}
4167
4168 //----------Special Memory Operands--------------------------------------------
4169 // Stack Slot Operand - This operand is used for loading and storing temporary
4170 // values on the stack where a match requires a value to
4171 // flow through memory.
4172 operand stackSlotI(sRegI reg) %{
4173 constraint(ALLOC_IN_RC(stack_slots));
4174 op_cost(100);
4175 //match(RegI);
4176 format %{ "[$reg]" %}
4177 interface(MEMORY_INTER) %{
4178 base(0xE); // R_SP
4179 index(0x0);
4180 scale(0x0);
4181 disp($reg); // Stack Offset
4182 %}
4183 %}
4184
4185 operand stackSlotP(sRegP reg) %{
4186 constraint(ALLOC_IN_RC(stack_slots));
4187 op_cost(100);
4188 //match(RegP);
4189 format %{ "[$reg]" %}
4190 interface(MEMORY_INTER) %{
4191 base(0xE); // R_SP
4192 index(0x0);
4193 scale(0x0);
4194 disp($reg); // Stack Offset
4195 %}
4196 %}
4197
4198 operand stackSlotF(sRegF reg) %{
4199 constraint(ALLOC_IN_RC(stack_slots));
4200 op_cost(100);
4201 //match(RegF);
4202 format %{ "[$reg]" %}
4203 interface(MEMORY_INTER) %{
4204 base(0xE); // R_SP
4205 index(0x0);
4206 scale(0x0);
4207 disp($reg); // Stack Offset
4208 %}
4209 %}
4210 operand stackSlotD(sRegD reg) %{
4211 constraint(ALLOC_IN_RC(stack_slots));
4212 op_cost(100);
4213 //match(RegD);
4214 format %{ "[$reg]" %}
4215 interface(MEMORY_INTER) %{
4216 base(0xE); // R_SP
4217 index(0x0);
4218 scale(0x0);
4219 disp($reg); // Stack Offset
4220 %}
4221 %}
4222 operand stackSlotL(sRegL reg) %{
4223 constraint(ALLOC_IN_RC(stack_slots));
4224 op_cost(100);
4225 //match(RegL);
4226 format %{ "[$reg]" %}
4227 interface(MEMORY_INTER) %{
4228 base(0xE); // R_SP
4229 index(0x0);
4230 scale(0x0);
4231 disp($reg); // Stack Offset
4232 %}
4233 %}
4234
4235 // Operands for expressing Control Flow
4236 // NOTE: Label is a predefined operand which should not be redefined in
4237 // the AD file. It is generically handled within the ADLC.
4238
4239 //----------Conditional Branch Operands----------------------------------------
4240 // Comparison Op - This is the operation of the comparison, and is limited to
4241 // the following set of codes:
4242 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4243 //
4244 // Other attributes of the comparison, such as unsignedness, are specified
4245 // by the comparison instruction that sets a condition code flags register.
4246 // That result is represented by a flags operand whose subtype is appropriate
4247 // to the unsignedness (etc.) of the comparison.
4248 //
4249 // Later, the instruction which matches both the Comparison Op (a Bool) and
4250 // the flags (produced by the Cmp) specifies the coding of the comparison op
4251 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4252
4253 operand cmpOp() %{
4254 match(Bool);
4255
4256 format %{ "" %}
4257 interface(COND_INTER) %{
4258 equal(0x1);
4259 not_equal(0x9);
4260 less(0x3);
4261 greater_equal(0xB);
4262 less_equal(0x2);
4263 greater(0xA);
4264 %}
4265 %}
4266
4267 // Comparison Op, unsigned
4268 operand cmpOpU() %{
4269 match(Bool);
4270
4271 format %{ "u" %}
4272 interface(COND_INTER) %{
4273 equal(0x1);
4274 not_equal(0x9);
4275 less(0x5);
4276 greater_equal(0xD);
4277 less_equal(0x4);
4278 greater(0xC);
4279 %}
4280 %}
4281
4282 // Comparison Op, pointer (same as unsigned)
4283 operand cmpOpP() %{
4284 match(Bool);
4285
4286 format %{ "p" %}
4287 interface(COND_INTER) %{
4288 equal(0x1);
4289 not_equal(0x9);
4290 less(0x5);
4291 greater_equal(0xD);
4292 less_equal(0x4);
4293 greater(0xC);
4294 %}
4295 %}
4296
4297 // Comparison Op, branch-register encoding
4298 operand cmpOp_reg() %{
4299 match(Bool);
4300
4301 format %{ "" %}
4302 interface(COND_INTER) %{
4303 equal (0x1);
4304 not_equal (0x5);
4305 less (0x3);
4306 greater_equal(0x7);
4307 less_equal (0x2);
4308 greater (0x6);
4309 %}
4310 %}
4311
4312 // Comparison Code, floating, unordered same as less
4313 operand cmpOpF() %{
4314 match(Bool);
4315
4316 format %{ "fl" %}
4317 interface(COND_INTER) %{
4318 equal(0x9);
4319 not_equal(0x1);
4320 less(0x3);
4321 greater_equal(0xB);
4322 less_equal(0xE);
4323 greater(0x6);
4324 %}
4325 %}
4326
4327 // Used by long compare
4328 operand cmpOp_commute() %{
4329 match(Bool);
4330
4331 format %{ "" %}
4332 interface(COND_INTER) %{
4333 equal(0x1);
4334 not_equal(0x9);
4335 less(0xA);
4336 greater_equal(0x2);
4337 less_equal(0xB);
4338 greater(0x3);
4339 %}
4340 %}
4341
4342 //----------OPERAND CLASSES----------------------------------------------------
4343 // Operand Classes are groups of operands that are used to simplify
4344 // instruction definitions by not requiring the AD writer to specify separate
4345 // instructions for every form of operand when the instruction accepts
4346 // multiple operand types with the same basic encoding and format. The classic
4347 // case of this is memory operands.
4348 opclass memory( indirect, indOffset13, indIndex );
4349 opclass indIndexMemory( indIndex );
4350
4351 //----------PIPELINE-----------------------------------------------------------
4352 pipeline %{
4353
4354 //----------ATTRIBUTES---------------------------------------------------------
4355 attributes %{
4356 fixed_size_instructions; // Fixed size instructions
4357 branch_has_delay_slot; // Branch has delay slot following
4358 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4359 instruction_unit_size = 4; // An instruction is 4 bytes long
4360 instruction_fetch_unit_size = 16; // The processor fetches one line
4361 instruction_fetch_units = 1; // of 16 bytes
4362
4363 // List of nop instructions
4364 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4365 %}
4366
4367 //----------RESOURCES----------------------------------------------------------
4368 // Resources are the functional units available to the machine
4369 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4370
4371 //----------PIPELINE DESCRIPTION-----------------------------------------------
4372 // Pipeline Description specifies the stages in the machine's pipeline
4373
4374 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4375
4376 //----------PIPELINE CLASSES---------------------------------------------------
4377 // Pipeline Classes describe the stages in which input and output are
4378 // referenced by the hardware pipeline.
4379
4380 // Integer ALU reg-reg operation
4381 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4382 single_instruction;
4383 dst : E(write);
4384 src1 : R(read);
4385 src2 : R(read);
4386 IALU : R;
4387 %}
4388
4389 // Integer ALU reg-reg long operation
4390 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4391 instruction_count(2);
4392 dst : E(write);
4393 src1 : R(read);
4394 src2 : R(read);
4395 IALU : R;
4396 IALU : R;
4397 %}
4398
4399 // Integer ALU reg-reg long dependent operation
4400 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4401 instruction_count(1); multiple_bundles;
4402 dst : E(write);
4403 src1 : R(read);
4404 src2 : R(read);
4405 cr : E(write);
4406 IALU : R(2);
4407 %}
4408
4409 // Integer ALU reg-imm operaion
4410 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4411 single_instruction;
4412 dst : E(write);
4413 src1 : R(read);
4414 IALU : R;
4415 %}
4416
4417 // Integer ALU reg-reg operation with condition code
4418 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4419 single_instruction;
4420 dst : E(write);
4421 cr : E(write);
4422 src1 : R(read);
4423 src2 : R(read);
4424 IALU : R;
4425 %}
4426
4427 // Integer ALU reg-imm operation with condition code
4428 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4429 single_instruction;
4430 dst : E(write);
4431 cr : E(write);
4432 src1 : R(read);
4433 IALU : R;
4434 %}
4435
4436 // Integer ALU zero-reg operation
4437 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4438 single_instruction;
4439 dst : E(write);
4440 src2 : R(read);
4441 IALU : R;
4442 %}
4443
4444 // Integer ALU zero-reg operation with condition code only
4445 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4446 single_instruction;
4447 cr : E(write);
4448 src : R(read);
4449 IALU : R;
4450 %}
4451
4452 // Integer ALU reg-reg operation with condition code only
4453 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4454 single_instruction;
4455 cr : E(write);
4456 src1 : R(read);
4457 src2 : R(read);
4458 IALU : R;
4459 %}
4460
4461 // Integer ALU reg-imm operation with condition code only
4462 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4463 single_instruction;
4464 cr : E(write);
4465 src1 : R(read);
4466 IALU : R;
4467 %}
4468
4469 // Integer ALU reg-reg-zero operation with condition code only
4470 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4471 single_instruction;
4472 cr : E(write);
4473 src1 : R(read);
4474 src2 : R(read);
4475 IALU : R;
4476 %}
4477
4478 // Integer ALU reg-imm-zero operation with condition code only
4479 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4480 single_instruction;
4481 cr : E(write);
4482 src1 : R(read);
4483 IALU : R;
4484 %}
4485
4486 // Integer ALU reg-reg operation with condition code, src1 modified
4487 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4488 single_instruction;
4489 cr : E(write);
4490 src1 : E(write);
4491 src1 : R(read);
4492 src2 : R(read);
4493 IALU : R;
4494 %}
4495
4496 // Integer ALU reg-imm operation with condition code, src1 modified
4497 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4498 single_instruction;
4499 cr : E(write);
4500 src1 : E(write);
4501 src1 : R(read);
4502 IALU : R;
4503 %}
4504
4505 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4506 multiple_bundles;
4507 dst : E(write)+4;
4508 cr : E(write);
4509 src1 : R(read);
4510 src2 : R(read);
4511 IALU : R(3);
4512 BR : R(2);
4513 %}
4514
4515 // Integer ALU operation
4516 pipe_class ialu_none(iRegI dst) %{
4517 single_instruction;
4518 dst : E(write);
4519 IALU : R;
4520 %}
4521
4522 // Integer ALU reg operation
4523 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4524 single_instruction; may_have_no_code;
4525 dst : E(write);
4526 src : R(read);
4527 IALU : R;
4528 %}
4529
4530 // Integer ALU reg conditional operation
4531 // This instruction has a 1 cycle stall, and cannot execute
4532 // in the same cycle as the instruction setting the condition
4533 // code. We kludge this by pretending to read the condition code
4534 // 1 cycle earlier, and by marking the functional units as busy
4535 // for 2 cycles with the result available 1 cycle later than
4536 // is really the case.
4537 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4538 single_instruction;
4539 op2_out : C(write);
4540 op1 : R(read);
4541 cr : R(read); // This is really E, with a 1 cycle stall
4542 BR : R(2);
4543 MS : R(2);
4544 %}
4545
4546 #ifdef _LP64
4547 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4548 instruction_count(1); multiple_bundles;
4549 dst : C(write)+1;
4550 src : R(read)+1;
4551 IALU : R(1);
4552 BR : E(2);
4553 MS : E(2);
4554 %}
4555 #endif
4556
4557 // Integer ALU reg operation
4558 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4559 single_instruction; may_have_no_code;
4560 dst : E(write);
4561 src : R(read);
4562 IALU : R;
4563 %}
4564 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4565 single_instruction; may_have_no_code;
4566 dst : E(write);
4567 src : R(read);
4568 IALU : R;
4569 %}
4570
4571 // Two integer ALU reg operations
4572 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4573 instruction_count(2);
4574 dst : E(write);
4575 src : R(read);
4576 A0 : R;
4577 A1 : R;
4578 %}
4579
4580 // Two integer ALU reg operations
4581 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4582 instruction_count(2); may_have_no_code;
4583 dst : E(write);
4584 src : R(read);
4585 A0 : R;
4586 A1 : R;
4587 %}
4588
4589 // Integer ALU imm operation
4590 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4591 single_instruction;
4592 dst : E(write);
4593 IALU : R;
4594 %}
4595
4596 // Integer ALU reg-reg with carry operation
4597 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4598 single_instruction;
4599 dst : E(write);
4600 src1 : R(read);
4601 src2 : R(read);
4602 IALU : R;
4603 %}
4604
4605 // Integer ALU cc operation
4606 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4607 single_instruction;
4608 dst : E(write);
4609 cc : R(read);
4610 IALU : R;
4611 %}
4612
4613 // Integer ALU cc / second IALU operation
4614 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4615 instruction_count(1); multiple_bundles;
4616 dst : E(write)+1;
4617 src : R(read);
4618 IALU : R;
4619 %}
4620
4621 // Integer ALU cc / second IALU operation
4622 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4623 instruction_count(1); multiple_bundles;
4624 dst : E(write)+1;
4625 p : R(read);
4626 q : R(read);
4627 IALU : R;
4628 %}
4629
4630 // Integer ALU hi-lo-reg operation
4631 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4632 instruction_count(1); multiple_bundles;
4633 dst : E(write)+1;
4634 IALU : R(2);
4635 %}
4636
4637 // Float ALU hi-lo-reg operation (with temp)
4638 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4639 instruction_count(1); multiple_bundles;
4640 dst : E(write)+1;
4641 IALU : R(2);
4642 %}
4643
4644 // Long Constant
4645 pipe_class loadConL( iRegL dst, immL src ) %{
4646 instruction_count(2); multiple_bundles;
4647 dst : E(write)+1;
4648 IALU : R(2);
4649 IALU : R(2);
4650 %}
4651
4652 // Pointer Constant
4653 pipe_class loadConP( iRegP dst, immP src ) %{
4654 instruction_count(0); multiple_bundles;
4655 fixed_latency(6);
4656 %}
4657
4658 // Polling Address
4659 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4660 #ifdef _LP64
4661 instruction_count(0); multiple_bundles;
4662 fixed_latency(6);
4663 #else
4664 dst : E(write);
4665 IALU : R;
4666 #endif
4667 %}
4668
4669 // Long Constant small
4670 pipe_class loadConLlo( iRegL dst, immL src ) %{
4671 instruction_count(2);
4672 dst : E(write);
4673 IALU : R;
4674 IALU : R;
4675 %}
4676
4677 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4678 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4679 instruction_count(1); multiple_bundles;
4680 src : R(read);
4681 dst : M(write)+1;
4682 IALU : R;
4683 MS : E;
4684 %}
4685
4686 // Integer ALU nop operation
4687 pipe_class ialu_nop() %{
4688 single_instruction;
4689 IALU : R;
4690 %}
4691
4692 // Integer ALU nop operation
4693 pipe_class ialu_nop_A0() %{
4694 single_instruction;
4695 A0 : R;
4696 %}
4697
4698 // Integer ALU nop operation
4699 pipe_class ialu_nop_A1() %{
4700 single_instruction;
4701 A1 : R;
4702 %}
4703
4704 // Integer Multiply reg-reg operation
4705 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4706 single_instruction;
4707 dst : E(write);
4708 src1 : R(read);
4709 src2 : R(read);
4710 MS : R(5);
4711 %}
4712
4713 // Integer Multiply reg-imm operation
4714 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4715 single_instruction;
4716 dst : E(write);
4717 src1 : R(read);
4718 MS : R(5);
4719 %}
4720
4721 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4722 single_instruction;
4723 dst : E(write)+4;
4724 src1 : R(read);
4725 src2 : R(read);
4726 MS : R(6);
4727 %}
4728
4729 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4730 single_instruction;
4731 dst : E(write)+4;
4732 src1 : R(read);
4733 MS : R(6);
4734 %}
4735
4736 // Integer Divide reg-reg
4737 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4738 instruction_count(1); multiple_bundles;
4739 dst : E(write);
4740 temp : E(write);
4741 src1 : R(read);
4742 src2 : R(read);
4743 temp : R(read);
4744 MS : R(38);
4745 %}
4746
4747 // Integer Divide reg-imm
4748 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4749 instruction_count(1); multiple_bundles;
4750 dst : E(write);
4751 temp : E(write);
4752 src1 : R(read);
4753 temp : R(read);
4754 MS : R(38);
4755 %}
4756
4757 // Long Divide
4758 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4759 dst : E(write)+71;
4760 src1 : R(read);
4761 src2 : R(read)+1;
4762 MS : R(70);
4763 %}
4764
4765 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4766 dst : E(write)+71;
4767 src1 : R(read);
4768 MS : R(70);
4769 %}
4770
4771 // Floating Point Add Float
4772 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4773 single_instruction;
4774 dst : X(write);
4775 src1 : E(read);
4776 src2 : E(read);
4777 FA : R;
4778 %}
4779
4780 // Floating Point Add Double
4781 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4782 single_instruction;
4783 dst : X(write);
4784 src1 : E(read);
4785 src2 : E(read);
4786 FA : R;
4787 %}
4788
4789 // Floating Point Conditional Move based on integer flags
4790 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4791 single_instruction;
4792 dst : X(write);
4793 src : E(read);
4794 cr : R(read);
4795 FA : R(2);
4796 BR : R(2);
4797 %}
4798
4799 // Floating Point Conditional Move based on integer flags
4800 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4801 single_instruction;
4802 dst : X(write);
4803 src : E(read);
4804 cr : R(read);
4805 FA : R(2);
4806 BR : R(2);
4807 %}
4808
4809 // Floating Point Multiply Float
4810 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4811 single_instruction;
4812 dst : X(write);
4813 src1 : E(read);
4814 src2 : E(read);
4815 FM : R;
4816 %}
4817
4818 // Floating Point Multiply Double
4819 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4820 single_instruction;
4821 dst : X(write);
4822 src1 : E(read);
4823 src2 : E(read);
4824 FM : R;
4825 %}
4826
4827 // Floating Point Divide Float
4828 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4829 single_instruction;
4830 dst : X(write);
4831 src1 : E(read);
4832 src2 : E(read);
4833 FM : R;
4834 FDIV : C(14);
4835 %}
4836
4837 // Floating Point Divide Double
4838 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4839 single_instruction;
4840 dst : X(write);
4841 src1 : E(read);
4842 src2 : E(read);
4843 FM : R;
4844 FDIV : C(17);
4845 %}
4846
4847 // Floating Point Move/Negate/Abs Float
4848 pipe_class faddF_reg(regF dst, regF src) %{
4849 single_instruction;
4850 dst : W(write);
4851 src : E(read);
4852 FA : R(1);
4853 %}
4854
4855 // Floating Point Move/Negate/Abs Double
4856 pipe_class faddD_reg(regD dst, regD src) %{
4857 single_instruction;
4858 dst : W(write);
4859 src : E(read);
4860 FA : R;
4861 %}
4862
4863 // Floating Point Convert F->D
4864 pipe_class fcvtF2D(regD dst, regF src) %{
4865 single_instruction;
4866 dst : X(write);
4867 src : E(read);
4868 FA : R;
4869 %}
4870
4871 // Floating Point Convert I->D
4872 pipe_class fcvtI2D(regD dst, regF src) %{
4873 single_instruction;
4874 dst : X(write);
4875 src : E(read);
4876 FA : R;
4877 %}
4878
4879 // Floating Point Convert LHi->D
4880 pipe_class fcvtLHi2D(regD dst, regD src) %{
4881 single_instruction;
4882 dst : X(write);
4883 src : E(read);
4884 FA : R;
4885 %}
4886
4887 // Floating Point Convert L->D
4888 pipe_class fcvtL2D(regD dst, regF src) %{
4889 single_instruction;
4890 dst : X(write);
4891 src : E(read);
4892 FA : R;
4893 %}
4894
4895 // Floating Point Convert L->F
4896 pipe_class fcvtL2F(regD dst, regF src) %{
4897 single_instruction;
4898 dst : X(write);
4899 src : E(read);
4900 FA : R;
4901 %}
4902
4903 // Floating Point Convert D->F
4904 pipe_class fcvtD2F(regD dst, regF src) %{
4905 single_instruction;
4906 dst : X(write);
4907 src : E(read);
4908 FA : R;
4909 %}
4910
4911 // Floating Point Convert I->L
4912 pipe_class fcvtI2L(regD dst, regF src) %{
4913 single_instruction;
4914 dst : X(write);
4915 src : E(read);
4916 FA : R;
4917 %}
4918
4919 // Floating Point Convert D->F
4920 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4921 instruction_count(1); multiple_bundles;
4922 dst : X(write)+6;
4923 src : E(read);
4924 FA : R;
4925 %}
4926
4927 // Floating Point Convert D->L
4928 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4929 instruction_count(1); multiple_bundles;
4930 dst : X(write)+6;
4931 src : E(read);
4932 FA : R;
4933 %}
4934
4935 // Floating Point Convert F->I
4936 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4937 instruction_count(1); multiple_bundles;
4938 dst : X(write)+6;
4939 src : E(read);
4940 FA : R;
4941 %}
4942
4943 // Floating Point Convert F->L
4944 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4945 instruction_count(1); multiple_bundles;
4946 dst : X(write)+6;
4947 src : E(read);
4948 FA : R;
4949 %}
4950
4951 // Floating Point Convert I->F
4952 pipe_class fcvtI2F(regF dst, regF src) %{
4953 single_instruction;
4954 dst : X(write);
4955 src : E(read);
4956 FA : R;
4957 %}
4958
4959 // Floating Point Compare
4960 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4961 single_instruction;
4962 cr : X(write);
4963 src1 : E(read);
4964 src2 : E(read);
4965 FA : R;
4966 %}
4967
4968 // Floating Point Compare
4969 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4970 single_instruction;
4971 cr : X(write);
4972 src1 : E(read);
4973 src2 : E(read);
4974 FA : R;
4975 %}
4976
4977 // Floating Add Nop
4978 pipe_class fadd_nop() %{
4979 single_instruction;
4980 FA : R;
4981 %}
4982
4983 // Integer Store to Memory
4984 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4985 single_instruction;
4986 mem : R(read);
4987 src : C(read);
4988 MS : R;
4989 %}
4990
4991 // Integer Store to Memory
4992 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4993 single_instruction;
4994 mem : R(read);
4995 src : C(read);
4996 MS : R;
4997 %}
4998
4999 // Integer Store Zero to Memory
5000 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5001 single_instruction;
5002 mem : R(read);
5003 MS : R;
5004 %}
5005
5006 // Special Stack Slot Store
5007 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5008 single_instruction;
5009 stkSlot : R(read);
5010 src : C(read);
5011 MS : R;
5012 %}
5013
5014 // Special Stack Slot Store
5015 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5016 instruction_count(2); multiple_bundles;
5017 stkSlot : R(read);
5018 src : C(read);
5019 MS : R(2);
5020 %}
5021
5022 // Float Store
5023 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5024 single_instruction;
5025 mem : R(read);
5026 src : C(read);
5027 MS : R;
5028 %}
5029
5030 // Float Store
5031 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5032 single_instruction;
5033 mem : R(read);
5034 MS : R;
5035 %}
5036
5037 // Double Store
5038 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5039 instruction_count(1);
5040 mem : R(read);
5041 src : C(read);
5042 MS : R;
5043 %}
5044
5045 // Double Store
5046 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5047 single_instruction;
5048 mem : R(read);
5049 MS : R;
5050 %}
5051
5052 // Special Stack Slot Float Store
5053 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5054 single_instruction;
5055 stkSlot : R(read);
5056 src : C(read);
5057 MS : R;
5058 %}
5059
5060 // Special Stack Slot Double Store
5061 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5062 single_instruction;
5063 stkSlot : R(read);
5064 src : C(read);
5065 MS : R;
5066 %}
5067
5068 // Integer Load (when sign bit propagation not needed)
5069 pipe_class iload_mem(iRegI dst, memory mem) %{
5070 single_instruction;
5071 mem : R(read);
5072 dst : C(write);
5073 MS : R;
5074 %}
5075
5076 // Integer Load from stack operand
5077 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5078 single_instruction;
5079 mem : R(read);
5080 dst : C(write);
5081 MS : R;
5082 %}
5083
5084 // Integer Load (when sign bit propagation or masking is needed)
5085 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5086 single_instruction;
5087 mem : R(read);
5088 dst : M(write);
5089 MS : R;
5090 %}
5091
5092 // Float Load
5093 pipe_class floadF_mem(regF dst, memory mem) %{
5094 single_instruction;
5095 mem : R(read);
5096 dst : M(write);
5097 MS : R;
5098 %}
5099
5100 // Float Load
5101 pipe_class floadD_mem(regD dst, memory mem) %{
5102 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5103 mem : R(read);
5104 dst : M(write);
5105 MS : R;
5106 %}
5107
5108 // Float Load
5109 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5110 single_instruction;
5111 stkSlot : R(read);
5112 dst : M(write);
5113 MS : R;
5114 %}
5115
5116 // Float Load
5117 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5118 single_instruction;
5119 stkSlot : R(read);
5120 dst : M(write);
5121 MS : R;
5122 %}
5123
5124 // Memory Nop
5125 pipe_class mem_nop() %{
5126 single_instruction;
5127 MS : R;
5128 %}
5129
5130 pipe_class sethi(iRegP dst, immI src) %{
5131 single_instruction;
5132 dst : E(write);
5133 IALU : R;
5134 %}
5135
5136 pipe_class loadPollP(iRegP poll) %{
5137 single_instruction;
5138 poll : R(read);
5139 MS : R;
5140 %}
5141
5142 pipe_class br(Universe br, label labl) %{
5143 single_instruction_with_delay_slot;
5144 BR : R;
5145 %}
5146
5147 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5148 single_instruction_with_delay_slot;
5149 cr : E(read);
5150 BR : R;
5151 %}
5152
5153 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5154 single_instruction_with_delay_slot;
5155 op1 : E(read);
5156 BR : R;
5157 MS : R;
5158 %}
5159
5160 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5161 single_instruction_with_delay_slot;
5162 cr : E(read);
5163 BR : R;
5164 %}
5165
5166 pipe_class br_nop() %{
5167 single_instruction;
5168 BR : R;
5169 %}
5170
5171 pipe_class simple_call(method meth) %{
5172 instruction_count(2); multiple_bundles; force_serialization;
5173 fixed_latency(100);
5174 BR : R(1);
5175 MS : R(1);
5176 A0 : R(1);
5177 %}
5178
5179 pipe_class compiled_call(method meth) %{
5180 instruction_count(1); multiple_bundles; force_serialization;
5181 fixed_latency(100);
5182 MS : R(1);
5183 %}
5184
5185 pipe_class call(method meth) %{
5186 instruction_count(0); multiple_bundles; force_serialization;
5187 fixed_latency(100);
5188 %}
5189
5190 pipe_class tail_call(Universe ignore, label labl) %{
5191 single_instruction; has_delay_slot;
5192 fixed_latency(100);
5193 BR : R(1);
5194 MS : R(1);
5195 %}
5196
5197 pipe_class ret(Universe ignore) %{
5198 single_instruction; has_delay_slot;
5199 BR : R(1);
5200 MS : R(1);
5201 %}
5202
5203 pipe_class ret_poll(g3RegP poll) %{
5204 instruction_count(3); has_delay_slot;
5205 poll : E(read);
5206 MS : R;
5207 %}
5208
5209 // The real do-nothing guy
5210 pipe_class empty( ) %{
5211 instruction_count(0);
5212 %}
5213
5214 pipe_class long_memory_op() %{
5215 instruction_count(0); multiple_bundles; force_serialization;
5216 fixed_latency(25);
5217 MS : R(1);
5218 %}
5219
5220 // Check-cast
5221 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5222 array : R(read);
5223 match : R(read);
5224 IALU : R(2);
5225 BR : R(2);
5226 MS : R;
5227 %}
5228
5229 // Convert FPU flags into +1,0,-1
5230 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5231 src1 : E(read);
5232 src2 : E(read);
5233 dst : E(write);
5234 FA : R;
5235 MS : R(2);
5236 BR : R(2);
5237 %}
5238
5239 // Compare for p < q, and conditionally add y
5240 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5241 p : E(read);
5242 q : E(read);
5243 y : E(read);
5244 IALU : R(3)
5245 %}
5246
5247 // Perform a compare, then move conditionally in a branch delay slot.
5248 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5249 src2 : E(read);
5250 srcdst : E(read);
5251 IALU : R;
5252 BR : R;
5253 %}
5254
5255 // Define the class for the Nop node
5256 define %{
5257 MachNop = ialu_nop;
5258 %}
5259
5260 %}
5261
5262 //----------INSTRUCTIONS-------------------------------------------------------
5263
5264 //------------Special Stack Slot instructions - no match rules-----------------
5265 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5266 // No match rule to avoid chain rule match.
5267 effect(DEF dst, USE src);
5268 ins_cost(MEMORY_REF_COST);
5269 size(4);
5270 format %{ "LDF $src,$dst\t! stkI to regF" %}
5271 opcode(Assembler::ldf_op3);
5272 ins_encode(simple_form3_mem_reg(src, dst));
5273 ins_pipe(floadF_stk);
5274 %}
5275
5276 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5277 // No match rule to avoid chain rule match.
5278 effect(DEF dst, USE src);
5279 ins_cost(MEMORY_REF_COST);
5280 size(4);
5281 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5282 opcode(Assembler::lddf_op3);
5283 ins_encode(simple_form3_mem_reg(src, dst));
5284 ins_pipe(floadD_stk);
5285 %}
5286
5287 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5288 // No match rule to avoid chain rule match.
5289 effect(DEF dst, USE src);
5290 ins_cost(MEMORY_REF_COST);
5291 size(4);
5292 format %{ "STF $src,$dst\t! regF to stkI" %}
5293 opcode(Assembler::stf_op3);
5294 ins_encode(simple_form3_mem_reg(dst, src));
5295 ins_pipe(fstoreF_stk_reg);
5296 %}
5297
5298 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5299 // No match rule to avoid chain rule match.
5300 effect(DEF dst, USE src);
5301 ins_cost(MEMORY_REF_COST);
5302 size(4);
5303 format %{ "STDF $src,$dst\t! regD to stkL" %}
5304 opcode(Assembler::stdf_op3);
5305 ins_encode(simple_form3_mem_reg(dst, src));
5306 ins_pipe(fstoreD_stk_reg);
5307 %}
5308
5309 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5310 effect(DEF dst, USE src);
5311 ins_cost(MEMORY_REF_COST*2);
5312 size(8);
5313 format %{ "STW $src,$dst.hi\t! long\n\t"
5314 "STW R_G0,$dst.lo" %}
5315 opcode(Assembler::stw_op3);
5316 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5317 ins_pipe(lstoreI_stk_reg);
5318 %}
5319
5320 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5321 // No match rule to avoid chain rule match.
5322 effect(DEF dst, USE src);
5323 ins_cost(MEMORY_REF_COST);
5324 size(4);
5325 format %{ "STX $src,$dst\t! regL to stkD" %}
5326 opcode(Assembler::stx_op3);
5327 ins_encode(simple_form3_mem_reg( dst, src ) );
5328 ins_pipe(istore_stk_reg);
5329 %}
5330
5331 //---------- Chain stack slots between similar types --------
5332
5333 // Load integer from stack slot
5334 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5335 match(Set dst src);
5336 ins_cost(MEMORY_REF_COST);
5337
5338 size(4);
5339 format %{ "LDUW $src,$dst\t!stk" %}
5340 opcode(Assembler::lduw_op3);
5341 ins_encode(simple_form3_mem_reg( src, dst ) );
5342 ins_pipe(iload_mem);
5343 %}
5344
5345 // Store integer to stack slot
5346 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5347 match(Set dst src);
5348 ins_cost(MEMORY_REF_COST);
5349
5350 size(4);
5351 format %{ "STW $src,$dst\t!stk" %}
5352 opcode(Assembler::stw_op3);
5353 ins_encode(simple_form3_mem_reg( dst, src ) );
5354 ins_pipe(istore_mem_reg);
5355 %}
5356
5357 // Load long from stack slot
5358 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5359 match(Set dst src);
5360
5361 ins_cost(MEMORY_REF_COST);
5362 size(4);
5363 format %{ "LDX $src,$dst\t! long" %}
5364 opcode(Assembler::ldx_op3);
5365 ins_encode(simple_form3_mem_reg( src, dst ) );
5366 ins_pipe(iload_mem);
5367 %}
5368
5369 // Store long to stack slot
5370 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5371 match(Set dst src);
5372
5373 ins_cost(MEMORY_REF_COST);
5374 size(4);
5375 format %{ "STX $src,$dst\t! long" %}
5376 opcode(Assembler::stx_op3);
5377 ins_encode(simple_form3_mem_reg( dst, src ) );
5378 ins_pipe(istore_mem_reg);
5379 %}
5380
5381 #ifdef _LP64
5382 // Load pointer from stack slot, 64-bit encoding
5383 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5384 match(Set dst src);
5385 ins_cost(MEMORY_REF_COST);
5386 size(4);
5387 format %{ "LDX $src,$dst\t!ptr" %}
5388 opcode(Assembler::ldx_op3);
5389 ins_encode(simple_form3_mem_reg( src, dst ) );
5390 ins_pipe(iload_mem);
5391 %}
5392
5393 // Store pointer to stack slot
5394 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5395 match(Set dst src);
5396 ins_cost(MEMORY_REF_COST);
5397 size(4);
5398 format %{ "STX $src,$dst\t!ptr" %}
5399 opcode(Assembler::stx_op3);
5400 ins_encode(simple_form3_mem_reg( dst, src ) );
5401 ins_pipe(istore_mem_reg);
5402 %}
5403 #else // _LP64
5404 // Load pointer from stack slot, 32-bit encoding
5405 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5406 match(Set dst src);
5407 ins_cost(MEMORY_REF_COST);
5408 format %{ "LDUW $src,$dst\t!ptr" %}
5409 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5410 ins_encode(simple_form3_mem_reg( src, dst ) );
5411 ins_pipe(iload_mem);
5412 %}
5413
5414 // Store pointer to stack slot
5415 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5416 match(Set dst src);
5417 ins_cost(MEMORY_REF_COST);
5418 format %{ "STW $src,$dst\t!ptr" %}
5419 opcode(Assembler::stw_op3, Assembler::ldst_op);
5420 ins_encode(simple_form3_mem_reg( dst, src ) );
5421 ins_pipe(istore_mem_reg);
5422 %}
5423 #endif // _LP64
5424
5425 //------------Special Nop instructions for bundling - no match rules-----------
5426 // Nop using the A0 functional unit
5427 instruct Nop_A0() %{
5428 ins_cost(0);
5429
5430 format %{ "NOP ! Alu Pipeline" %}
5431 opcode(Assembler::or_op3, Assembler::arith_op);
5432 ins_encode( form2_nop() );
5433 ins_pipe(ialu_nop_A0);
5434 %}
5435
5436 // Nop using the A1 functional unit
5437 instruct Nop_A1( ) %{
5438 ins_cost(0);
5439
5440 format %{ "NOP ! Alu Pipeline" %}
5441 opcode(Assembler::or_op3, Assembler::arith_op);
5442 ins_encode( form2_nop() );
5443 ins_pipe(ialu_nop_A1);
5444 %}
5445
5446 // Nop using the memory functional unit
5447 instruct Nop_MS( ) %{
5448 ins_cost(0);
5449
5450 format %{ "NOP ! Memory Pipeline" %}
5451 ins_encode( emit_mem_nop );
5452 ins_pipe(mem_nop);
5453 %}
5454
5455 // Nop using the floating add functional unit
5456 instruct Nop_FA( ) %{
5457 ins_cost(0);
5458
5459 format %{ "NOP ! Floating Add Pipeline" %}
5460 ins_encode( emit_fadd_nop );
5461 ins_pipe(fadd_nop);
5462 %}
5463
5464 // Nop using the branch functional unit
5465 instruct Nop_BR( ) %{
5466 ins_cost(0);
5467
5468 format %{ "NOP ! Branch Pipeline" %}
5469 ins_encode( emit_br_nop );
5470 ins_pipe(br_nop);
5471 %}
5472
5473 //----------Load/Store/Move Instructions---------------------------------------
5474 //----------Load Instructions--------------------------------------------------
5475 // Load Byte (8bit signed)
5476 instruct loadB(iRegI dst, memory mem) %{
5477 match(Set dst (LoadB mem));
5478 ins_cost(MEMORY_REF_COST);
5479
5480 size(4);
5481 format %{ "LDSB $mem,$dst\t! byte" %}
5482 ins_encode %{
5483 __ ldsb($mem$$Address, $dst$$Register);
5484 %}
5485 ins_pipe(iload_mask_mem);
5486 %}
5487
5488 // Load Byte (8bit signed) into a Long Register
5489 instruct loadB2L(iRegL dst, memory mem) %{
5490 match(Set dst (ConvI2L (LoadB mem)));
5491 ins_cost(MEMORY_REF_COST);
5492
5493 size(4);
5494 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5495 ins_encode %{
5496 __ ldsb($mem$$Address, $dst$$Register);
5497 %}
5498 ins_pipe(iload_mask_mem);
5499 %}
5500
5501 // Load Unsigned Byte (8bit UNsigned) into an int reg
5502 instruct loadUB(iRegI dst, memory mem) %{
5503 match(Set dst (LoadUB mem));
5504 ins_cost(MEMORY_REF_COST);
5505
5506 size(4);
5507 format %{ "LDUB $mem,$dst\t! ubyte" %}
5508 ins_encode %{
5509 __ ldub($mem$$Address, $dst$$Register);
5510 %}
5511 ins_pipe(iload_mem);
5512 %}
5513
5514 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5515 instruct loadUB2L(iRegL dst, memory mem) %{
5516 match(Set dst (ConvI2L (LoadUB mem)));
5517 ins_cost(MEMORY_REF_COST);
5518
5519 size(4);
5520 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5521 ins_encode %{
5522 __ ldub($mem$$Address, $dst$$Register);
5523 %}
5524 ins_pipe(iload_mem);
5525 %}
5526
5527 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5528 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5529 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5530 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5531
5532 size(2*4);
5533 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5534 "AND $dst,$mask,$dst" %}
5535 ins_encode %{
5536 __ ldub($mem$$Address, $dst$$Register);
5537 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5538 %}
5539 ins_pipe(iload_mem);
5540 %}
5541
5542 // Load Short (16bit signed)
5543 instruct loadS(iRegI dst, memory mem) %{
5544 match(Set dst (LoadS mem));
5545 ins_cost(MEMORY_REF_COST);
5546
5547 size(4);
5548 format %{ "LDSH $mem,$dst\t! short" %}
5549 ins_encode %{
5550 __ ldsh($mem$$Address, $dst$$Register);
5551 %}
5552 ins_pipe(iload_mask_mem);
5553 %}
5554
5555 // Load Short (16 bit signed) to Byte (8 bit signed)
5556 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5557 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5558 ins_cost(MEMORY_REF_COST);
5559
5560 size(4);
5561
5562 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5563 ins_encode %{
5564 __ ldsb($mem$$Address, $dst$$Register, 1);
5565 %}
5566 ins_pipe(iload_mask_mem);
5567 %}
5568
5569 // Load Short (16bit signed) into a Long Register
5570 instruct loadS2L(iRegL dst, memory mem) %{
5571 match(Set dst (ConvI2L (LoadS mem)));
5572 ins_cost(MEMORY_REF_COST);
5573
5574 size(4);
5575 format %{ "LDSH $mem,$dst\t! short -> long" %}
5576 ins_encode %{
5577 __ ldsh($mem$$Address, $dst$$Register);
5578 %}
5579 ins_pipe(iload_mask_mem);
5580 %}
5581
5582 // Load Unsigned Short/Char (16bit UNsigned)
5583 instruct loadUS(iRegI dst, memory mem) %{
5584 match(Set dst (LoadUS mem));
5585 ins_cost(MEMORY_REF_COST);
5586
5587 size(4);
5588 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5589 ins_encode %{
5590 __ lduh($mem$$Address, $dst$$Register);
5591 %}
5592 ins_pipe(iload_mem);
5593 %}
5594
5595 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5596 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5597 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5598 ins_cost(MEMORY_REF_COST);
5599
5600 size(4);
5601 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5602 ins_encode %{
5603 __ ldsb($mem$$Address, $dst$$Register, 1);
5604 %}
5605 ins_pipe(iload_mask_mem);
5606 %}
5607
5608 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5609 instruct loadUS2L(iRegL dst, memory mem) %{
5610 match(Set dst (ConvI2L (LoadUS mem)));
5611 ins_cost(MEMORY_REF_COST);
5612
5613 size(4);
5614 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5615 ins_encode %{
5616 __ lduh($mem$$Address, $dst$$Register);
5617 %}
5618 ins_pipe(iload_mem);
5619 %}
5620
5621 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5622 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5623 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5624 ins_cost(MEMORY_REF_COST);
5625
5626 size(4);
5627 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5628 ins_encode %{
5629 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5630 %}
5631 ins_pipe(iload_mem);
5632 %}
5633
5634 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5635 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5636 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5637 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5638
5639 size(2*4);
5640 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5641 "AND $dst,$mask,$dst" %}
5642 ins_encode %{
5643 Register Rdst = $dst$$Register;
5644 __ lduh($mem$$Address, Rdst);
5645 __ and3(Rdst, $mask$$constant, Rdst);
5646 %}
5647 ins_pipe(iload_mem);
5648 %}
5649
5650 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5651 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5652 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5653 effect(TEMP dst, TEMP tmp);
5654 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5655
5656 size((3+1)*4); // set may use two instructions.
5657 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5658 "SET $mask,$tmp\n\t"
5659 "AND $dst,$tmp,$dst" %}
5660 ins_encode %{
5661 Register Rdst = $dst$$Register;
5662 Register Rtmp = $tmp$$Register;
5663 __ lduh($mem$$Address, Rdst);
5664 __ set($mask$$constant, Rtmp);
5665 __ and3(Rdst, Rtmp, Rdst);
5666 %}
5667 ins_pipe(iload_mem);
5668 %}
5669
5670 // Load Integer
5671 instruct loadI(iRegI dst, memory mem) %{
5672 match(Set dst (LoadI mem));
5673 ins_cost(MEMORY_REF_COST);
5674
5675 size(4);
5676 format %{ "LDUW $mem,$dst\t! int" %}
5677 ins_encode %{
5678 __ lduw($mem$$Address, $dst$$Register);
5679 %}
5680 ins_pipe(iload_mem);
5681 %}
5682
5683 // Load Integer to Byte (8 bit signed)
5684 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5685 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5686 ins_cost(MEMORY_REF_COST);
5687
5688 size(4);
5689
5690 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5691 ins_encode %{
5692 __ ldsb($mem$$Address, $dst$$Register, 3);
5693 %}
5694 ins_pipe(iload_mask_mem);
5695 %}
5696
5697 // Load Integer to Unsigned Byte (8 bit UNsigned)
5698 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5699 match(Set dst (AndI (LoadI mem) mask));
5700 ins_cost(MEMORY_REF_COST);
5701
5702 size(4);
5703
5704 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5705 ins_encode %{
5706 __ ldub($mem$$Address, $dst$$Register, 3);
5707 %}
5708 ins_pipe(iload_mask_mem);
5709 %}
5710
5711 // Load Integer to Short (16 bit signed)
5712 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5713 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5714 ins_cost(MEMORY_REF_COST);
5715
5716 size(4);
5717
5718 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5719 ins_encode %{
5720 __ ldsh($mem$$Address, $dst$$Register, 2);
5721 %}
5722 ins_pipe(iload_mask_mem);
5723 %}
5724
5725 // Load Integer to Unsigned Short (16 bit UNsigned)
5726 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5727 match(Set dst (AndI (LoadI mem) mask));
5728 ins_cost(MEMORY_REF_COST);
5729
5730 size(4);
5731
5732 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5733 ins_encode %{
5734 __ lduh($mem$$Address, $dst$$Register, 2);
5735 %}
5736 ins_pipe(iload_mask_mem);
5737 %}
5738
5739 // Load Integer into a Long Register
5740 instruct loadI2L(iRegL dst, memory mem) %{
5741 match(Set dst (ConvI2L (LoadI mem)));
5742 ins_cost(MEMORY_REF_COST);
5743
5744 size(4);
5745 format %{ "LDSW $mem,$dst\t! int -> long" %}
5746 ins_encode %{
5747 __ ldsw($mem$$Address, $dst$$Register);
5748 %}
5749 ins_pipe(iload_mask_mem);
5750 %}
5751
5752 // Load Integer with mask 0xFF into a Long Register
5753 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5754 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5755 ins_cost(MEMORY_REF_COST);
5756
5757 size(4);
5758 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5759 ins_encode %{
5760 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5761 %}
5762 ins_pipe(iload_mem);
5763 %}
5764
5765 // Load Integer with mask 0xFFFF into a Long Register
5766 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5767 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5768 ins_cost(MEMORY_REF_COST);
5769
5770 size(4);
5771 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5772 ins_encode %{
5773 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5774 %}
5775 ins_pipe(iload_mem);
5776 %}
5777
5778 // Load Integer with a 13-bit mask into a Long Register
5779 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5780 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5781 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5782
5783 size(2*4);
5784 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5785 "AND $dst,$mask,$dst" %}
5786 ins_encode %{
5787 Register Rdst = $dst$$Register;
5788 __ lduw($mem$$Address, Rdst);
5789 __ and3(Rdst, $mask$$constant, Rdst);
5790 %}
5791 ins_pipe(iload_mem);
5792 %}
5793
5794 // Load Integer with a 32-bit mask into a Long Register
5795 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5796 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5797 effect(TEMP dst, TEMP tmp);
5798 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5799
5800 size((3+1)*4); // set may use two instructions.
5801 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5802 "SET $mask,$tmp\n\t"
5803 "AND $dst,$tmp,$dst" %}
5804 ins_encode %{
5805 Register Rdst = $dst$$Register;
5806 Register Rtmp = $tmp$$Register;
5807 __ lduw($mem$$Address, Rdst);
5808 __ set($mask$$constant, Rtmp);
5809 __ and3(Rdst, Rtmp, Rdst);
5810 %}
5811 ins_pipe(iload_mem);
5812 %}
5813
5814 // Load Unsigned Integer into a Long Register
5815 instruct loadUI2L(iRegL dst, memory mem) %{
5816 match(Set dst (LoadUI2L mem));
5817 ins_cost(MEMORY_REF_COST);
5818
5819 size(4);
5820 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5821 ins_encode %{
5822 __ lduw($mem$$Address, $dst$$Register);
5823 %}
5824 ins_pipe(iload_mem);
5825 %}
5826
5827 // Load Long - aligned
5828 instruct loadL(iRegL dst, memory mem ) %{
5829 match(Set dst (LoadL mem));
5830 ins_cost(MEMORY_REF_COST);
5831
5832 size(4);
5833 format %{ "LDX $mem,$dst\t! long" %}
5834 ins_encode %{
5835 __ ldx($mem$$Address, $dst$$Register);
5836 %}
5837 ins_pipe(iload_mem);
5838 %}
5839
5840 // Load Long - UNaligned
5841 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5842 match(Set dst (LoadL_unaligned mem));
5843 effect(KILL tmp);
5844 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5845 size(16);
5846 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5847 "\tLDUW $mem ,$dst\n"
5848 "\tSLLX #32, $dst, $dst\n"
5849 "\tOR $dst, R_O7, $dst" %}
5850 opcode(Assembler::lduw_op3);
5851 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5852 ins_pipe(iload_mem);
5853 %}
5854
5855 // Load Aligned Packed Byte into a Double Register
5856 instruct loadA8B(regD dst, memory mem) %{
5857 match(Set dst (Load8B mem));
5858 ins_cost(MEMORY_REF_COST);
5859 size(4);
5860 format %{ "LDDF $mem,$dst\t! packed8B" %}
5861 opcode(Assembler::lddf_op3);
5862 ins_encode(simple_form3_mem_reg( mem, dst ) );
5863 ins_pipe(floadD_mem);
5864 %}
5865
5866 // Load Aligned Packed Char into a Double Register
5867 instruct loadA4C(regD dst, memory mem) %{
5868 match(Set dst (Load4C mem));
5869 ins_cost(MEMORY_REF_COST);
5870 size(4);
5871 format %{ "LDDF $mem,$dst\t! packed4C" %}
5872 opcode(Assembler::lddf_op3);
5873 ins_encode(simple_form3_mem_reg( mem, dst ) );
5874 ins_pipe(floadD_mem);
5875 %}
5876
5877 // Load Aligned Packed Short into a Double Register
5878 instruct loadA4S(regD dst, memory mem) %{
5879 match(Set dst (Load4S mem));
5880 ins_cost(MEMORY_REF_COST);
5881 size(4);
5882 format %{ "LDDF $mem,$dst\t! packed4S" %}
5883 opcode(Assembler::lddf_op3);
5884 ins_encode(simple_form3_mem_reg( mem, dst ) );
5885 ins_pipe(floadD_mem);
5886 %}
5887
5888 // Load Aligned Packed Int into a Double Register
5889 instruct loadA2I(regD dst, memory mem) %{
5890 match(Set dst (Load2I mem));
5891 ins_cost(MEMORY_REF_COST);
5892 size(4);
5893 format %{ "LDDF $mem,$dst\t! packed2I" %}
5894 opcode(Assembler::lddf_op3);
5895 ins_encode(simple_form3_mem_reg( mem, dst ) );
5896 ins_pipe(floadD_mem);
5897 %}
5898
5899 // Load Range
5900 instruct loadRange(iRegI dst, memory mem) %{
5901 match(Set dst (LoadRange mem));
5902 ins_cost(MEMORY_REF_COST);
5903
5904 size(4);
5905 format %{ "LDUW $mem,$dst\t! range" %}
5906 opcode(Assembler::lduw_op3);
5907 ins_encode(simple_form3_mem_reg( mem, dst ) );
5908 ins_pipe(iload_mem);
5909 %}
5910
5911 // Load Integer into %f register (for fitos/fitod)
5912 instruct loadI_freg(regF dst, memory mem) %{
5913 match(Set dst (LoadI mem));
5914 ins_cost(MEMORY_REF_COST);
5915 size(4);
5916
5917 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5918 opcode(Assembler::ldf_op3);
5919 ins_encode(simple_form3_mem_reg( mem, dst ) );
5920 ins_pipe(floadF_mem);
5921 %}
5922
5923 // Load Pointer
5924 instruct loadP(iRegP dst, memory mem) %{
5925 match(Set dst (LoadP mem));
5926 ins_cost(MEMORY_REF_COST);
5927 size(4);
5928
5929 #ifndef _LP64
5930 format %{ "LDUW $mem,$dst\t! ptr" %}
5931 ins_encode %{
5932 __ lduw($mem$$Address, $dst$$Register);
5933 %}
5934 #else
5935 format %{ "LDX $mem,$dst\t! ptr" %}
5936 ins_encode %{
5937 __ ldx($mem$$Address, $dst$$Register);
5938 %}
5939 #endif
5940 ins_pipe(iload_mem);
5941 %}
5942
5943 // Load Compressed Pointer
5944 instruct loadN(iRegN dst, memory mem) %{
5945 match(Set dst (LoadN mem));
5946 ins_cost(MEMORY_REF_COST);
5947 size(4);
5948
5949 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5950 ins_encode %{
5951 __ lduw($mem$$Address, $dst$$Register);
5952 %}
5953 ins_pipe(iload_mem);
5954 %}
5955
5956 // Load Klass Pointer
5957 instruct loadKlass(iRegP dst, memory mem) %{
5958 match(Set dst (LoadKlass mem));
5959 ins_cost(MEMORY_REF_COST);
5960 size(4);
5961
5962 #ifndef _LP64
5963 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5964 ins_encode %{
5965 __ lduw($mem$$Address, $dst$$Register);
5966 %}
5967 #else
5968 format %{ "LDX $mem,$dst\t! klass ptr" %}
5969 ins_encode %{
5970 __ ldx($mem$$Address, $dst$$Register);
5971 %}
5972 #endif
5973 ins_pipe(iload_mem);
5974 %}
5975
5976 // Load narrow Klass Pointer
5977 instruct loadNKlass(iRegN dst, memory mem) %{
5978 match(Set dst (LoadNKlass mem));
5979 ins_cost(MEMORY_REF_COST);
5980 size(4);
5981
5982 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5983 ins_encode %{
5984 __ lduw($mem$$Address, $dst$$Register);
5985 %}
5986 ins_pipe(iload_mem);
5987 %}
5988
5989 // Load Double
5990 instruct loadD(regD dst, memory mem) %{
5991 match(Set dst (LoadD mem));
5992 ins_cost(MEMORY_REF_COST);
5993
5994 size(4);
5995 format %{ "LDDF $mem,$dst" %}
5996 opcode(Assembler::lddf_op3);
5997 ins_encode(simple_form3_mem_reg( mem, dst ) );
5998 ins_pipe(floadD_mem);
5999 %}
6000
6001 // Load Double - UNaligned
6002 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6003 match(Set dst (LoadD_unaligned mem));
6004 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6005 size(8);
6006 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6007 "\tLDF $mem+4,$dst.lo\t!" %}
6008 opcode(Assembler::ldf_op3);
6009 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6010 ins_pipe(iload_mem);
6011 %}
6012
6013 // Load Float
6014 instruct loadF(regF dst, memory mem) %{
6015 match(Set dst (LoadF mem));
6016 ins_cost(MEMORY_REF_COST);
6017
6018 size(4);
6019 format %{ "LDF $mem,$dst" %}
6020 opcode(Assembler::ldf_op3);
6021 ins_encode(simple_form3_mem_reg( mem, dst ) );
6022 ins_pipe(floadF_mem);
6023 %}
6024
6025 // Load Constant
6026 instruct loadConI( iRegI dst, immI src ) %{
6027 match(Set dst src);
6028 ins_cost(DEFAULT_COST * 3/2);
6029 format %{ "SET $src,$dst" %}
6030 ins_encode( Set32(src, dst) );
6031 ins_pipe(ialu_hi_lo_reg);
6032 %}
6033
6034 instruct loadConI13( iRegI dst, immI13 src ) %{
6035 match(Set dst src);
6036
6037 size(4);
6038 format %{ "MOV $src,$dst" %}
6039 ins_encode( Set13( src, dst ) );
6040 ins_pipe(ialu_imm);
6041 %}
6042
6043 #ifndef _LP64
6044 instruct loadConP(iRegP dst, immP con) %{
6045 match(Set dst con);
6046 ins_cost(DEFAULT_COST * 3/2);
6047 format %{ "SET $con,$dst\t!ptr" %}
6048 ins_encode %{
6049 // [RGV] This next line should be generated from ADLC
6050 if (_opnds[1]->constant_is_oop()) {
6051 intptr_t val = $con$$constant;
6052 __ set_oop_constant((jobject) val, $dst$$Register);
6053 } else { // non-oop pointers, e.g. card mark base, heap top
6054 __ set($con$$constant, $dst$$Register);
6055 }
6056 %}
6057 ins_pipe(loadConP);
6058 %}
6059 #else
6060 instruct loadConP_set(iRegP dst, immP_set con) %{
6061 match(Set dst con);
6062 ins_cost(DEFAULT_COST * 3/2);
6063 format %{ "SET $con,$dst\t! ptr" %}
6064 ins_encode %{
6065 // [RGV] This next line should be generated from ADLC
6066 if (_opnds[1]->constant_is_oop()) {
6067 intptr_t val = $con$$constant;
6068 __ set_oop_constant((jobject) val, $dst$$Register);
6069 } else { // non-oop pointers, e.g. card mark base, heap top
6070 __ set($con$$constant, $dst$$Register);
6071 }
6072 %}
6073 ins_pipe(loadConP);
6074 %}
6075
6076 instruct loadConP_load(iRegP dst, immP_load con) %{
6077 match(Set dst con);
6078 ins_cost(MEMORY_REF_COST);
6079 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6080 ins_encode %{
6081 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6082 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6083 %}
6084 ins_pipe(loadConP);
6085 %}
6086
6087 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6088 match(Set dst con);
6089 ins_cost(DEFAULT_COST * 3/2);
6090 format %{ "SET $con,$dst\t! non-oop ptr" %}
6091 ins_encode %{
6092 __ set($con$$constant, $dst$$Register);
6093 %}
6094 ins_pipe(loadConP);
6095 %}
6096 #endif // _LP64
6097
6098 instruct loadConP0(iRegP dst, immP0 src) %{
6099 match(Set dst src);
6100
6101 size(4);
6102 format %{ "CLR $dst\t!ptr" %}
6103 ins_encode %{
6104 __ clr($dst$$Register);
6105 %}
6106 ins_pipe(ialu_imm);
6107 %}
6108
6109 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6110 match(Set dst src);
6111 ins_cost(DEFAULT_COST);
6112 format %{ "SET $src,$dst\t!ptr" %}
6113 ins_encode %{
6114 AddressLiteral polling_page(os::get_polling_page());
6115 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6116 %}
6117 ins_pipe(loadConP_poll);
6118 %}
6119
6120 instruct loadConN0(iRegN dst, immN0 src) %{
6121 match(Set dst src);
6122
6123 size(4);
6124 format %{ "CLR $dst\t! compressed NULL ptr" %}
6125 ins_encode %{
6126 __ clr($dst$$Register);
6127 %}
6128 ins_pipe(ialu_imm);
6129 %}
6130
6131 instruct loadConN(iRegN dst, immN src) %{
6132 match(Set dst src);
6133 ins_cost(DEFAULT_COST * 3/2);
6134 format %{ "SET $src,$dst\t! compressed ptr" %}
6135 ins_encode %{
6136 Register dst = $dst$$Register;
6137 __ set_narrow_oop((jobject)$src$$constant, dst);
6138 %}
6139 ins_pipe(ialu_hi_lo_reg);
6140 %}
6141
6142 // Materialize long value (predicated by immL_cheap).
6143 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6144 match(Set dst con);
6145 effect(KILL tmp);
6146 ins_cost(DEFAULT_COST * 3);
6147 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6148 ins_encode %{
6149 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6150 %}
6151 ins_pipe(loadConL);
6152 %}
6153
6154 // Load long value from constant table (predicated by immL_expensive).
6155 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6156 match(Set dst con);
6157 ins_cost(MEMORY_REF_COST);
6158 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6159 ins_encode %{
6160 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6161 __ ldx($constanttablebase, con_offset, $dst$$Register);
6162 %}
6163 ins_pipe(loadConL);
6164 %}
6165
6166 instruct loadConL0( iRegL dst, immL0 src ) %{
6167 match(Set dst src);
6168 ins_cost(DEFAULT_COST);
6169 size(4);
6170 format %{ "CLR $dst\t! long" %}
6171 ins_encode( Set13( src, dst ) );
6172 ins_pipe(ialu_imm);
6173 %}
6174
6175 instruct loadConL13( iRegL dst, immL13 src ) %{
6176 match(Set dst src);
6177 ins_cost(DEFAULT_COST * 2);
6178
6179 size(4);
6180 format %{ "MOV $src,$dst\t! long" %}
6181 ins_encode( Set13( src, dst ) );
6182 ins_pipe(ialu_imm);
6183 %}
6184
6185 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6186 match(Set dst con);
6187 effect(KILL tmp);
6188 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6189 ins_encode %{
6190 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6191 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6192 %}
6193 ins_pipe(loadConFD);
6194 %}
6195
6196 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6197 match(Set dst con);
6198 effect(KILL tmp);
6199 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6200 ins_encode %{
6201 // XXX This is a quick fix for 6833573.
6202 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6203 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6204 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6205 %}
6206 ins_pipe(loadConFD);
6207 %}
6208
6209 // Prefetch instructions.
6210 // Must be safe to execute with invalid address (cannot fault).
6211
6212 instruct prefetchr( memory mem ) %{
6213 match( PrefetchRead mem );
6214 ins_cost(MEMORY_REF_COST);
6215
6216 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6217 opcode(Assembler::prefetch_op3);
6218 ins_encode( form3_mem_prefetch_read( mem ) );
6219 ins_pipe(iload_mem);
6220 %}
6221
6222 instruct prefetchw( memory mem ) %{
6223 predicate(AllocatePrefetchStyle != 3 );
6224 match( PrefetchWrite mem );
6225 ins_cost(MEMORY_REF_COST);
6226
6227 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6228 opcode(Assembler::prefetch_op3);
6229 ins_encode( form3_mem_prefetch_write( mem ) );
6230 ins_pipe(iload_mem);
6231 %}
6232
6233 // Use BIS instruction to prefetch.
6234 instruct prefetchw_bis( memory mem ) %{
6235 predicate(AllocatePrefetchStyle == 3);
6236 match( PrefetchWrite mem );
6237 ins_cost(MEMORY_REF_COST);
6238
6239 format %{ "STXA G0,$mem\t! // Block initializing store" %}
6240 ins_encode %{
6241 Register base = as_Register($mem$$base);
6242 int disp = $mem$$disp;
6243 if (disp != 0) {
6244 __ add(base, AllocatePrefetchStepSize, base);
6245 }
6246 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
6247 %}
6248 ins_pipe(istore_mem_reg);
6249 %}
6250
6251 //----------Store Instructions-------------------------------------------------
6252 // Store Byte
6253 instruct storeB(memory mem, iRegI src) %{
6254 match(Set mem (StoreB mem src));
6255 ins_cost(MEMORY_REF_COST);
6256
6257 size(4);
6258 format %{ "STB $src,$mem\t! byte" %}
6259 opcode(Assembler::stb_op3);
6260 ins_encode(simple_form3_mem_reg( mem, src ) );
6261 ins_pipe(istore_mem_reg);
6262 %}
6263
6264 instruct storeB0(memory mem, immI0 src) %{
6265 match(Set mem (StoreB mem src));
6266 ins_cost(MEMORY_REF_COST);
6267
6268 size(4);
6269 format %{ "STB $src,$mem\t! byte" %}
6270 opcode(Assembler::stb_op3);
6271 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6272 ins_pipe(istore_mem_zero);
6273 %}
6274
6275 instruct storeCM0(memory mem, immI0 src) %{
6276 match(Set mem (StoreCM mem src));
6277 ins_cost(MEMORY_REF_COST);
6278
6279 size(4);
6280 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6281 opcode(Assembler::stb_op3);
6282 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6283 ins_pipe(istore_mem_zero);
6284 %}
6285
6286 // Store Char/Short
6287 instruct storeC(memory mem, iRegI src) %{
6288 match(Set mem (StoreC mem src));
6289 ins_cost(MEMORY_REF_COST);
6290
6291 size(4);
6292 format %{ "STH $src,$mem\t! short" %}
6293 opcode(Assembler::sth_op3);
6294 ins_encode(simple_form3_mem_reg( mem, src ) );
6295 ins_pipe(istore_mem_reg);
6296 %}
6297
6298 instruct storeC0(memory mem, immI0 src) %{
6299 match(Set mem (StoreC mem src));
6300 ins_cost(MEMORY_REF_COST);
6301
6302 size(4);
6303 format %{ "STH $src,$mem\t! short" %}
6304 opcode(Assembler::sth_op3);
6305 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6306 ins_pipe(istore_mem_zero);
6307 %}
6308
6309 // Store Integer
6310 instruct storeI(memory mem, iRegI src) %{
6311 match(Set mem (StoreI mem src));
6312 ins_cost(MEMORY_REF_COST);
6313
6314 size(4);
6315 format %{ "STW $src,$mem" %}
6316 opcode(Assembler::stw_op3);
6317 ins_encode(simple_form3_mem_reg( mem, src ) );
6318 ins_pipe(istore_mem_reg);
6319 %}
6320
6321 // Store Long
6322 instruct storeL(memory mem, iRegL src) %{
6323 match(Set mem (StoreL mem src));
6324 ins_cost(MEMORY_REF_COST);
6325 size(4);
6326 format %{ "STX $src,$mem\t! long" %}
6327 opcode(Assembler::stx_op3);
6328 ins_encode(simple_form3_mem_reg( mem, src ) );
6329 ins_pipe(istore_mem_reg);
6330 %}
6331
6332 instruct storeI0(memory mem, immI0 src) %{
6333 match(Set mem (StoreI mem src));
6334 ins_cost(MEMORY_REF_COST);
6335
6336 size(4);
6337 format %{ "STW $src,$mem" %}
6338 opcode(Assembler::stw_op3);
6339 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6340 ins_pipe(istore_mem_zero);
6341 %}
6342
6343 instruct storeL0(memory mem, immL0 src) %{
6344 match(Set mem (StoreL mem src));
6345 ins_cost(MEMORY_REF_COST);
6346
6347 size(4);
6348 format %{ "STX $src,$mem" %}
6349 opcode(Assembler::stx_op3);
6350 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6351 ins_pipe(istore_mem_zero);
6352 %}
6353
6354 // Store Integer from float register (used after fstoi)
6355 instruct storeI_Freg(memory mem, regF src) %{
6356 match(Set mem (StoreI mem src));
6357 ins_cost(MEMORY_REF_COST);
6358
6359 size(4);
6360 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6361 opcode(Assembler::stf_op3);
6362 ins_encode(simple_form3_mem_reg( mem, src ) );
6363 ins_pipe(fstoreF_mem_reg);
6364 %}
6365
6366 // Store Pointer
6367 instruct storeP(memory dst, sp_ptr_RegP src) %{
6368 match(Set dst (StoreP dst src));
6369 ins_cost(MEMORY_REF_COST);
6370 size(4);
6371
6372 #ifndef _LP64
6373 format %{ "STW $src,$dst\t! ptr" %}
6374 opcode(Assembler::stw_op3, 0, REGP_OP);
6375 #else
6376 format %{ "STX $src,$dst\t! ptr" %}
6377 opcode(Assembler::stx_op3, 0, REGP_OP);
6378 #endif
6379 ins_encode( form3_mem_reg( dst, src ) );
6380 ins_pipe(istore_mem_spORreg);
6381 %}
6382
6383 instruct storeP0(memory dst, immP0 src) %{
6384 match(Set dst (StoreP dst src));
6385 ins_cost(MEMORY_REF_COST);
6386 size(4);
6387
6388 #ifndef _LP64
6389 format %{ "STW $src,$dst\t! ptr" %}
6390 opcode(Assembler::stw_op3, 0, REGP_OP);
6391 #else
6392 format %{ "STX $src,$dst\t! ptr" %}
6393 opcode(Assembler::stx_op3, 0, REGP_OP);
6394 #endif
6395 ins_encode( form3_mem_reg( dst, R_G0 ) );
6396 ins_pipe(istore_mem_zero);
6397 %}
6398
6399 // Store Compressed Pointer
6400 instruct storeN(memory dst, iRegN src) %{
6401 match(Set dst (StoreN dst src));
6402 ins_cost(MEMORY_REF_COST);
6403 size(4);
6404
6405 format %{ "STW $src,$dst\t! compressed ptr" %}
6406 ins_encode %{
6407 Register base = as_Register($dst$$base);
6408 Register index = as_Register($dst$$index);
6409 Register src = $src$$Register;
6410 if (index != G0) {
6411 __ stw(src, base, index);
6412 } else {
6413 __ stw(src, base, $dst$$disp);
6414 }
6415 %}
6416 ins_pipe(istore_mem_spORreg);
6417 %}
6418
6419 instruct storeN0(memory dst, immN0 src) %{
6420 match(Set dst (StoreN dst src));
6421 ins_cost(MEMORY_REF_COST);
6422 size(4);
6423
6424 format %{ "STW $src,$dst\t! compressed ptr" %}
6425 ins_encode %{
6426 Register base = as_Register($dst$$base);
6427 Register index = as_Register($dst$$index);
6428 if (index != G0) {
6429 __ stw(0, base, index);
6430 } else {
6431 __ stw(0, base, $dst$$disp);
6432 }
6433 %}
6434 ins_pipe(istore_mem_zero);
6435 %}
6436
6437 // Store Double
6438 instruct storeD( memory mem, regD src) %{
6439 match(Set mem (StoreD mem src));
6440 ins_cost(MEMORY_REF_COST);
6441
6442 size(4);
6443 format %{ "STDF $src,$mem" %}
6444 opcode(Assembler::stdf_op3);
6445 ins_encode(simple_form3_mem_reg( mem, src ) );
6446 ins_pipe(fstoreD_mem_reg);
6447 %}
6448
6449 instruct storeD0( memory mem, immD0 src) %{
6450 match(Set mem (StoreD mem src));
6451 ins_cost(MEMORY_REF_COST);
6452
6453 size(4);
6454 format %{ "STX $src,$mem" %}
6455 opcode(Assembler::stx_op3);
6456 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6457 ins_pipe(fstoreD_mem_zero);
6458 %}
6459
6460 // Store Float
6461 instruct storeF( memory mem, regF src) %{
6462 match(Set mem (StoreF mem src));
6463 ins_cost(MEMORY_REF_COST);
6464
6465 size(4);
6466 format %{ "STF $src,$mem" %}
6467 opcode(Assembler::stf_op3);
6468 ins_encode(simple_form3_mem_reg( mem, src ) );
6469 ins_pipe(fstoreF_mem_reg);
6470 %}
6471
6472 instruct storeF0( memory mem, immF0 src) %{
6473 match(Set mem (StoreF mem src));
6474 ins_cost(MEMORY_REF_COST);
6475
6476 size(4);
6477 format %{ "STW $src,$mem\t! storeF0" %}
6478 opcode(Assembler::stw_op3);
6479 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6480 ins_pipe(fstoreF_mem_zero);
6481 %}
6482
6483 // Store Aligned Packed Bytes in Double register to memory
6484 instruct storeA8B(memory mem, regD src) %{
6485 match(Set mem (Store8B mem src));
6486 ins_cost(MEMORY_REF_COST);
6487 size(4);
6488 format %{ "STDF $src,$mem\t! packed8B" %}
6489 opcode(Assembler::stdf_op3);
6490 ins_encode(simple_form3_mem_reg( mem, src ) );
6491 ins_pipe(fstoreD_mem_reg);
6492 %}
6493
6494 // Convert oop pointer into compressed form
6495 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6496 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6497 match(Set dst (EncodeP src));
6498 format %{ "encode_heap_oop $src, $dst" %}
6499 ins_encode %{
6500 __ encode_heap_oop($src$$Register, $dst$$Register);
6501 %}
6502 ins_pipe(ialu_reg);
6503 %}
6504
6505 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6506 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6507 match(Set dst (EncodeP src));
6508 format %{ "encode_heap_oop_not_null $src, $dst" %}
6509 ins_encode %{
6510 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6511 %}
6512 ins_pipe(ialu_reg);
6513 %}
6514
6515 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6516 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6517 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6518 match(Set dst (DecodeN src));
6519 format %{ "decode_heap_oop $src, $dst" %}
6520 ins_encode %{
6521 __ decode_heap_oop($src$$Register, $dst$$Register);
6522 %}
6523 ins_pipe(ialu_reg);
6524 %}
6525
6526 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6527 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6528 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6529 match(Set dst (DecodeN src));
6530 format %{ "decode_heap_oop_not_null $src, $dst" %}
6531 ins_encode %{
6532 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6533 %}
6534 ins_pipe(ialu_reg);
6535 %}
6536
6537
6538 // Store Zero into Aligned Packed Bytes
6539 instruct storeA8B0(memory mem, immI0 zero) %{
6540 match(Set mem (Store8B mem zero));
6541 ins_cost(MEMORY_REF_COST);
6542 size(4);
6543 format %{ "STX $zero,$mem\t! packed8B" %}
6544 opcode(Assembler::stx_op3);
6545 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6546 ins_pipe(fstoreD_mem_zero);
6547 %}
6548
6549 // Store Aligned Packed Chars/Shorts in Double register to memory
6550 instruct storeA4C(memory mem, regD src) %{
6551 match(Set mem (Store4C mem src));
6552 ins_cost(MEMORY_REF_COST);
6553 size(4);
6554 format %{ "STDF $src,$mem\t! packed4C" %}
6555 opcode(Assembler::stdf_op3);
6556 ins_encode(simple_form3_mem_reg( mem, src ) );
6557 ins_pipe(fstoreD_mem_reg);
6558 %}
6559
6560 // Store Zero into Aligned Packed Chars/Shorts
6561 instruct storeA4C0(memory mem, immI0 zero) %{
6562 match(Set mem (Store4C mem (Replicate4C zero)));
6563 ins_cost(MEMORY_REF_COST);
6564 size(4);
6565 format %{ "STX $zero,$mem\t! packed4C" %}
6566 opcode(Assembler::stx_op3);
6567 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6568 ins_pipe(fstoreD_mem_zero);
6569 %}
6570
6571 // Store Aligned Packed Ints in Double register to memory
6572 instruct storeA2I(memory mem, regD src) %{
6573 match(Set mem (Store2I mem src));
6574 ins_cost(MEMORY_REF_COST);
6575 size(4);
6576 format %{ "STDF $src,$mem\t! packed2I" %}
6577 opcode(Assembler::stdf_op3);
6578 ins_encode(simple_form3_mem_reg( mem, src ) );
6579 ins_pipe(fstoreD_mem_reg);
6580 %}
6581
6582 // Store Zero into Aligned Packed Ints
6583 instruct storeA2I0(memory mem, immI0 zero) %{
6584 match(Set mem (Store2I mem zero));
6585 ins_cost(MEMORY_REF_COST);
6586 size(4);
6587 format %{ "STX $zero,$mem\t! packed2I" %}
6588 opcode(Assembler::stx_op3);
6589 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6590 ins_pipe(fstoreD_mem_zero);
6591 %}
6592
6593
6594 //----------MemBar Instructions-----------------------------------------------
6595 // Memory barrier flavors
6596
6597 instruct membar_acquire() %{
6598 match(MemBarAcquire);
6599 ins_cost(4*MEMORY_REF_COST);
6600
6601 size(0);
6602 format %{ "MEMBAR-acquire" %}
6603 ins_encode( enc_membar_acquire );
6604 ins_pipe(long_memory_op);
6605 %}
6606
6607 instruct membar_acquire_lock() %{
6608 match(MemBarAcquire);
6609 predicate(Matcher::prior_fast_lock(n));
6610 ins_cost(0);
6611
6612 size(0);
6613 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6614 ins_encode( );
6615 ins_pipe(empty);
6616 %}
6617
6618 instruct membar_release() %{
6619 match(MemBarRelease);
6620 ins_cost(4*MEMORY_REF_COST);
6621
6622 size(0);
6623 format %{ "MEMBAR-release" %}
6624 ins_encode( enc_membar_release );
6625 ins_pipe(long_memory_op);
6626 %}
6627
6628 instruct membar_release_lock() %{
6629 match(MemBarRelease);
6630 predicate(Matcher::post_fast_unlock(n));
6631 ins_cost(0);
6632
6633 size(0);
6634 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6635 ins_encode( );
6636 ins_pipe(empty);
6637 %}
6638
6639 instruct membar_volatile() %{
6640 match(MemBarVolatile);
6641 ins_cost(4*MEMORY_REF_COST);
6642
6643 size(4);
6644 format %{ "MEMBAR-volatile" %}
6645 ins_encode( enc_membar_volatile );
6646 ins_pipe(long_memory_op);
6647 %}
6648
6649 instruct unnecessary_membar_volatile() %{
6650 match(MemBarVolatile);
6651 predicate(Matcher::post_store_load_barrier(n));
6652 ins_cost(0);
6653
6654 size(0);
6655 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6656 ins_encode( );
6657 ins_pipe(empty);
6658 %}
6659
6660 //----------Register Move Instructions-----------------------------------------
6661 instruct roundDouble_nop(regD dst) %{
6662 match(Set dst (RoundDouble dst));
6663 ins_cost(0);
6664 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6665 ins_encode( );
6666 ins_pipe(empty);
6667 %}
6668
6669
6670 instruct roundFloat_nop(regF dst) %{
6671 match(Set dst (RoundFloat dst));
6672 ins_cost(0);
6673 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6674 ins_encode( );
6675 ins_pipe(empty);
6676 %}
6677
6678
6679 // Cast Index to Pointer for unsafe natives
6680 instruct castX2P(iRegX src, iRegP dst) %{
6681 match(Set dst (CastX2P src));
6682
6683 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6684 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6685 ins_pipe(ialu_reg);
6686 %}
6687
6688 // Cast Pointer to Index for unsafe natives
6689 instruct castP2X(iRegP src, iRegX dst) %{
6690 match(Set dst (CastP2X src));
6691
6692 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6693 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6694 ins_pipe(ialu_reg);
6695 %}
6696
6697 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6698 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6699 match(Set stkSlot src); // chain rule
6700 ins_cost(MEMORY_REF_COST);
6701 format %{ "STDF $src,$stkSlot\t!stk" %}
6702 opcode(Assembler::stdf_op3);
6703 ins_encode(simple_form3_mem_reg(stkSlot, src));
6704 ins_pipe(fstoreD_stk_reg);
6705 %}
6706
6707 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6708 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6709 match(Set dst stkSlot); // chain rule
6710 ins_cost(MEMORY_REF_COST);
6711 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6712 opcode(Assembler::lddf_op3);
6713 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6714 ins_pipe(floadD_stk);
6715 %}
6716
6717 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6718 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6719 match(Set stkSlot src); // chain rule
6720 ins_cost(MEMORY_REF_COST);
6721 format %{ "STF $src,$stkSlot\t!stk" %}
6722 opcode(Assembler::stf_op3);
6723 ins_encode(simple_form3_mem_reg(stkSlot, src));
6724 ins_pipe(fstoreF_stk_reg);
6725 %}
6726
6727 //----------Conditional Move---------------------------------------------------
6728 // Conditional move
6729 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6730 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6731 ins_cost(150);
6732 format %{ "MOV$cmp $pcc,$src,$dst" %}
6733 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6734 ins_pipe(ialu_reg);
6735 %}
6736
6737 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6738 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6739 ins_cost(140);
6740 format %{ "MOV$cmp $pcc,$src,$dst" %}
6741 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6742 ins_pipe(ialu_imm);
6743 %}
6744
6745 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6746 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6747 ins_cost(150);
6748 size(4);
6749 format %{ "MOV$cmp $icc,$src,$dst" %}
6750 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6751 ins_pipe(ialu_reg);
6752 %}
6753
6754 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6755 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6756 ins_cost(140);
6757 size(4);
6758 format %{ "MOV$cmp $icc,$src,$dst" %}
6759 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6760 ins_pipe(ialu_imm);
6761 %}
6762
6763 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6764 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6765 ins_cost(150);
6766 size(4);
6767 format %{ "MOV$cmp $icc,$src,$dst" %}
6768 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6769 ins_pipe(ialu_reg);
6770 %}
6771
6772 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6773 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6774 ins_cost(140);
6775 size(4);
6776 format %{ "MOV$cmp $icc,$src,$dst" %}
6777 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6778 ins_pipe(ialu_imm);
6779 %}
6780
6781 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6782 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6783 ins_cost(150);
6784 size(4);
6785 format %{ "MOV$cmp $fcc,$src,$dst" %}
6786 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6787 ins_pipe(ialu_reg);
6788 %}
6789
6790 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6791 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6792 ins_cost(140);
6793 size(4);
6794 format %{ "MOV$cmp $fcc,$src,$dst" %}
6795 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6796 ins_pipe(ialu_imm);
6797 %}
6798
6799 // Conditional move for RegN. Only cmov(reg,reg).
6800 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6801 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6802 ins_cost(150);
6803 format %{ "MOV$cmp $pcc,$src,$dst" %}
6804 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6805 ins_pipe(ialu_reg);
6806 %}
6807
6808 // This instruction also works with CmpN so we don't need cmovNN_reg.
6809 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6810 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6811 ins_cost(150);
6812 size(4);
6813 format %{ "MOV$cmp $icc,$src,$dst" %}
6814 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6815 ins_pipe(ialu_reg);
6816 %}
6817
6818 // This instruction also works with CmpN so we don't need cmovNN_reg.
6819 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6820 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6821 ins_cost(150);
6822 size(4);
6823 format %{ "MOV$cmp $icc,$src,$dst" %}
6824 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6825 ins_pipe(ialu_reg);
6826 %}
6827
6828 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6829 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6830 ins_cost(150);
6831 size(4);
6832 format %{ "MOV$cmp $fcc,$src,$dst" %}
6833 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6834 ins_pipe(ialu_reg);
6835 %}
6836
6837 // Conditional move
6838 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6839 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6840 ins_cost(150);
6841 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6842 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6843 ins_pipe(ialu_reg);
6844 %}
6845
6846 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6847 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6848 ins_cost(140);
6849 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6850 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6851 ins_pipe(ialu_imm);
6852 %}
6853
6854 // This instruction also works with CmpN so we don't need cmovPN_reg.
6855 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6856 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6857 ins_cost(150);
6858
6859 size(4);
6860 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6861 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6862 ins_pipe(ialu_reg);
6863 %}
6864
6865 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6866 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6867 ins_cost(150);
6868
6869 size(4);
6870 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6871 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6872 ins_pipe(ialu_reg);
6873 %}
6874
6875 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6876 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6877 ins_cost(140);
6878
6879 size(4);
6880 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6881 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6882 ins_pipe(ialu_imm);
6883 %}
6884
6885 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6886 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6887 ins_cost(140);
6888
6889 size(4);
6890 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6891 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6892 ins_pipe(ialu_imm);
6893 %}
6894
6895 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6896 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6897 ins_cost(150);
6898 size(4);
6899 format %{ "MOV$cmp $fcc,$src,$dst" %}
6900 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6901 ins_pipe(ialu_imm);
6902 %}
6903
6904 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6905 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6906 ins_cost(140);
6907 size(4);
6908 format %{ "MOV$cmp $fcc,$src,$dst" %}
6909 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6910 ins_pipe(ialu_imm);
6911 %}
6912
6913 // Conditional move
6914 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6915 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6916 ins_cost(150);
6917 opcode(0x101);
6918 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6919 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6920 ins_pipe(int_conditional_float_move);
6921 %}
6922
6923 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6924 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6925 ins_cost(150);
6926
6927 size(4);
6928 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6929 opcode(0x101);
6930 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6931 ins_pipe(int_conditional_float_move);
6932 %}
6933
6934 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6935 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6936 ins_cost(150);
6937
6938 size(4);
6939 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6940 opcode(0x101);
6941 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6942 ins_pipe(int_conditional_float_move);
6943 %}
6944
6945 // Conditional move,
6946 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6947 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6948 ins_cost(150);
6949 size(4);
6950 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6951 opcode(0x1);
6952 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6953 ins_pipe(int_conditional_double_move);
6954 %}
6955
6956 // Conditional move
6957 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6958 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6959 ins_cost(150);
6960 size(4);
6961 opcode(0x102);
6962 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6963 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6964 ins_pipe(int_conditional_double_move);
6965 %}
6966
6967 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6968 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6969 ins_cost(150);
6970
6971 size(4);
6972 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6973 opcode(0x102);
6974 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6975 ins_pipe(int_conditional_double_move);
6976 %}
6977
6978 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6979 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6980 ins_cost(150);
6981
6982 size(4);
6983 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6984 opcode(0x102);
6985 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6986 ins_pipe(int_conditional_double_move);
6987 %}
6988
6989 // Conditional move,
6990 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6991 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6992 ins_cost(150);
6993 size(4);
6994 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6995 opcode(0x2);
6996 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6997 ins_pipe(int_conditional_double_move);
6998 %}
6999
7000 // Conditional move
7001 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7002 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7003 ins_cost(150);
7004 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7005 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7006 ins_pipe(ialu_reg);
7007 %}
7008
7009 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7010 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7011 ins_cost(140);
7012 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7013 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7014 ins_pipe(ialu_imm);
7015 %}
7016
7017 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7018 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7019 ins_cost(150);
7020
7021 size(4);
7022 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7023 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7024 ins_pipe(ialu_reg);
7025 %}
7026
7027
7028 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7029 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7030 ins_cost(150);
7031
7032 size(4);
7033 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7034 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7035 ins_pipe(ialu_reg);
7036 %}
7037
7038
7039 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7040 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7041 ins_cost(150);
7042
7043 size(4);
7044 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7045 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7046 ins_pipe(ialu_reg);
7047 %}
7048
7049
7050
7051 //----------OS and Locking Instructions----------------------------------------
7052
7053 // This name is KNOWN by the ADLC and cannot be changed.
7054 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7055 // for this guy.
7056 instruct tlsLoadP(g2RegP dst) %{
7057 match(Set dst (ThreadLocal));
7058
7059 size(0);
7060 ins_cost(0);
7061 format %{ "# TLS is in G2" %}
7062 ins_encode( /*empty encoding*/ );
7063 ins_pipe(ialu_none);
7064 %}
7065
7066 instruct checkCastPP( iRegP dst ) %{
7067 match(Set dst (CheckCastPP dst));
7068
7069 size(0);
7070 format %{ "# checkcastPP of $dst" %}
7071 ins_encode( /*empty encoding*/ );
7072 ins_pipe(empty);
7073 %}
7074
7075
7076 instruct castPP( iRegP dst ) %{
7077 match(Set dst (CastPP dst));
7078 format %{ "# castPP of $dst" %}
7079 ins_encode( /*empty encoding*/ );
7080 ins_pipe(empty);
7081 %}
7082
7083 instruct castII( iRegI dst ) %{
7084 match(Set dst (CastII dst));
7085 format %{ "# castII of $dst" %}
7086 ins_encode( /*empty encoding*/ );
7087 ins_cost(0);
7088 ins_pipe(empty);
7089 %}
7090
7091 //----------Arithmetic Instructions--------------------------------------------
7092 // Addition Instructions
7093 // Register Addition
7094 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7095 match(Set dst (AddI src1 src2));
7096
7097 size(4);
7098 format %{ "ADD $src1,$src2,$dst" %}
7099 ins_encode %{
7100 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7101 %}
7102 ins_pipe(ialu_reg_reg);
7103 %}
7104
7105 // Immediate Addition
7106 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7107 match(Set dst (AddI src1 src2));
7108
7109 size(4);
7110 format %{ "ADD $src1,$src2,$dst" %}
7111 opcode(Assembler::add_op3, Assembler::arith_op);
7112 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7113 ins_pipe(ialu_reg_imm);
7114 %}
7115
7116 // Pointer Register Addition
7117 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7118 match(Set dst (AddP src1 src2));
7119
7120 size(4);
7121 format %{ "ADD $src1,$src2,$dst" %}
7122 opcode(Assembler::add_op3, Assembler::arith_op);
7123 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7124 ins_pipe(ialu_reg_reg);
7125 %}
7126
7127 // Pointer Immediate Addition
7128 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7129 match(Set dst (AddP src1 src2));
7130
7131 size(4);
7132 format %{ "ADD $src1,$src2,$dst" %}
7133 opcode(Assembler::add_op3, Assembler::arith_op);
7134 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7135 ins_pipe(ialu_reg_imm);
7136 %}
7137
7138 // Long Addition
7139 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7140 match(Set dst (AddL src1 src2));
7141
7142 size(4);
7143 format %{ "ADD $src1,$src2,$dst\t! long" %}
7144 opcode(Assembler::add_op3, Assembler::arith_op);
7145 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7146 ins_pipe(ialu_reg_reg);
7147 %}
7148
7149 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7150 match(Set dst (AddL src1 con));
7151
7152 size(4);
7153 format %{ "ADD $src1,$con,$dst" %}
7154 opcode(Assembler::add_op3, Assembler::arith_op);
7155 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7156 ins_pipe(ialu_reg_imm);
7157 %}
7158
7159 //----------Conditional_store--------------------------------------------------
7160 // Conditional-store of the updated heap-top.
7161 // Used during allocation of the shared heap.
7162 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7163
7164 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7165 instruct loadPLocked(iRegP dst, memory mem) %{
7166 match(Set dst (LoadPLocked mem));
7167 ins_cost(MEMORY_REF_COST);
7168
7169 #ifndef _LP64
7170 size(4);
7171 format %{ "LDUW $mem,$dst\t! ptr" %}
7172 opcode(Assembler::lduw_op3, 0, REGP_OP);
7173 #else
7174 format %{ "LDX $mem,$dst\t! ptr" %}
7175 opcode(Assembler::ldx_op3, 0, REGP_OP);
7176 #endif
7177 ins_encode( form3_mem_reg( mem, dst ) );
7178 ins_pipe(iload_mem);
7179 %}
7180
7181 // LoadL-locked. Same as a regular long load when used with a compare-swap
7182 instruct loadLLocked(iRegL dst, memory mem) %{
7183 match(Set dst (LoadLLocked mem));
7184 ins_cost(MEMORY_REF_COST);
7185 size(4);
7186 format %{ "LDX $mem,$dst\t! long" %}
7187 opcode(Assembler::ldx_op3);
7188 ins_encode(simple_form3_mem_reg( mem, dst ) );
7189 ins_pipe(iload_mem);
7190 %}
7191
7192 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7193 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7194 effect( KILL newval );
7195 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7196 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7197 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7198 ins_pipe( long_memory_op );
7199 %}
7200
7201 // Conditional-store of an int value.
7202 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7203 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7204 effect( KILL newval );
7205 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7206 "CMP $oldval,$newval\t\t! See if we made progress" %}
7207 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7208 ins_pipe( long_memory_op );
7209 %}
7210
7211 // Conditional-store of a long value.
7212 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7213 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7214 effect( KILL newval );
7215 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7216 "CMP $oldval,$newval\t\t! See if we made progress" %}
7217 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7218 ins_pipe( long_memory_op );
7219 %}
7220
7221 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7222
7223 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7224 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7225 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7226 format %{
7227 "MOV $newval,O7\n\t"
7228 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7229 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7230 "MOV 1,$res\n\t"
7231 "MOVne xcc,R_G0,$res"
7232 %}
7233 ins_encode( enc_casx(mem_ptr, oldval, newval),
7234 enc_lflags_ne_to_boolean(res) );
7235 ins_pipe( long_memory_op );
7236 %}
7237
7238
7239 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7240 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7241 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7242 format %{
7243 "MOV $newval,O7\n\t"
7244 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7245 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7246 "MOV 1,$res\n\t"
7247 "MOVne icc,R_G0,$res"
7248 %}
7249 ins_encode( enc_casi(mem_ptr, oldval, newval),
7250 enc_iflags_ne_to_boolean(res) );
7251 ins_pipe( long_memory_op );
7252 %}
7253
7254 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7255 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7256 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7257 format %{
7258 "MOV $newval,O7\n\t"
7259 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7260 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7261 "MOV 1,$res\n\t"
7262 "MOVne xcc,R_G0,$res"
7263 %}
7264 #ifdef _LP64
7265 ins_encode( enc_casx(mem_ptr, oldval, newval),
7266 enc_lflags_ne_to_boolean(res) );
7267 #else
7268 ins_encode( enc_casi(mem_ptr, oldval, newval),
7269 enc_iflags_ne_to_boolean(res) );
7270 #endif
7271 ins_pipe( long_memory_op );
7272 %}
7273
7274 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7275 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7276 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7277 format %{
7278 "MOV $newval,O7\n\t"
7279 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7280 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7281 "MOV 1,$res\n\t"
7282 "MOVne icc,R_G0,$res"
7283 %}
7284 ins_encode( enc_casi(mem_ptr, oldval, newval),
7285 enc_iflags_ne_to_boolean(res) );
7286 ins_pipe( long_memory_op );
7287 %}
7288
7289 //---------------------
7290 // Subtraction Instructions
7291 // Register Subtraction
7292 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7293 match(Set dst (SubI src1 src2));
7294
7295 size(4);
7296 format %{ "SUB $src1,$src2,$dst" %}
7297 opcode(Assembler::sub_op3, Assembler::arith_op);
7298 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7299 ins_pipe(ialu_reg_reg);
7300 %}
7301
7302 // Immediate Subtraction
7303 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7304 match(Set dst (SubI src1 src2));
7305
7306 size(4);
7307 format %{ "SUB $src1,$src2,$dst" %}
7308 opcode(Assembler::sub_op3, Assembler::arith_op);
7309 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7310 ins_pipe(ialu_reg_imm);
7311 %}
7312
7313 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7314 match(Set dst (SubI zero src2));
7315
7316 size(4);
7317 format %{ "NEG $src2,$dst" %}
7318 opcode(Assembler::sub_op3, Assembler::arith_op);
7319 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7320 ins_pipe(ialu_zero_reg);
7321 %}
7322
7323 // Long subtraction
7324 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7325 match(Set dst (SubL src1 src2));
7326
7327 size(4);
7328 format %{ "SUB $src1,$src2,$dst\t! long" %}
7329 opcode(Assembler::sub_op3, Assembler::arith_op);
7330 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7331 ins_pipe(ialu_reg_reg);
7332 %}
7333
7334 // Immediate Subtraction
7335 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7336 match(Set dst (SubL src1 con));
7337
7338 size(4);
7339 format %{ "SUB $src1,$con,$dst\t! long" %}
7340 opcode(Assembler::sub_op3, Assembler::arith_op);
7341 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7342 ins_pipe(ialu_reg_imm);
7343 %}
7344
7345 // Long negation
7346 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7347 match(Set dst (SubL zero src2));
7348
7349 size(4);
7350 format %{ "NEG $src2,$dst\t! long" %}
7351 opcode(Assembler::sub_op3, Assembler::arith_op);
7352 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7353 ins_pipe(ialu_zero_reg);
7354 %}
7355
7356 // Multiplication Instructions
7357 // Integer Multiplication
7358 // Register Multiplication
7359 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7360 match(Set dst (MulI src1 src2));
7361
7362 size(4);
7363 format %{ "MULX $src1,$src2,$dst" %}
7364 opcode(Assembler::mulx_op3, Assembler::arith_op);
7365 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7366 ins_pipe(imul_reg_reg);
7367 %}
7368
7369 // Immediate Multiplication
7370 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7371 match(Set dst (MulI src1 src2));
7372
7373 size(4);
7374 format %{ "MULX $src1,$src2,$dst" %}
7375 opcode(Assembler::mulx_op3, Assembler::arith_op);
7376 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7377 ins_pipe(imul_reg_imm);
7378 %}
7379
7380 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7381 match(Set dst (MulL src1 src2));
7382 ins_cost(DEFAULT_COST * 5);
7383 size(4);
7384 format %{ "MULX $src1,$src2,$dst\t! long" %}
7385 opcode(Assembler::mulx_op3, Assembler::arith_op);
7386 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7387 ins_pipe(mulL_reg_reg);
7388 %}
7389
7390 // Immediate Multiplication
7391 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7392 match(Set dst (MulL src1 src2));
7393 ins_cost(DEFAULT_COST * 5);
7394 size(4);
7395 format %{ "MULX $src1,$src2,$dst" %}
7396 opcode(Assembler::mulx_op3, Assembler::arith_op);
7397 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7398 ins_pipe(mulL_reg_imm);
7399 %}
7400
7401 // Integer Division
7402 // Register Division
7403 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7404 match(Set dst (DivI src1 src2));
7405 ins_cost((2+71)*DEFAULT_COST);
7406
7407 format %{ "SRA $src2,0,$src2\n\t"
7408 "SRA $src1,0,$src1\n\t"
7409 "SDIVX $src1,$src2,$dst" %}
7410 ins_encode( idiv_reg( src1, src2, dst ) );
7411 ins_pipe(sdiv_reg_reg);
7412 %}
7413
7414 // Immediate Division
7415 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7416 match(Set dst (DivI src1 src2));
7417 ins_cost((2+71)*DEFAULT_COST);
7418
7419 format %{ "SRA $src1,0,$src1\n\t"
7420 "SDIVX $src1,$src2,$dst" %}
7421 ins_encode( idiv_imm( src1, src2, dst ) );
7422 ins_pipe(sdiv_reg_imm);
7423 %}
7424
7425 //----------Div-By-10-Expansion------------------------------------------------
7426 // Extract hi bits of a 32x32->64 bit multiply.
7427 // Expand rule only, not matched
7428 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7429 effect( DEF dst, USE src1, USE src2 );
7430 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7431 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7432 ins_encode( enc_mul_hi(dst,src1,src2));
7433 ins_pipe(sdiv_reg_reg);
7434 %}
7435
7436 // Magic constant, reciprocal of 10
7437 instruct loadConI_x66666667(iRegIsafe dst) %{
7438 effect( DEF dst );
7439
7440 size(8);
7441 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7442 ins_encode( Set32(0x66666667, dst) );
7443 ins_pipe(ialu_hi_lo_reg);
7444 %}
7445
7446 // Register Shift Right Arithmetic Long by 32-63
7447 instruct sra_31( iRegI dst, iRegI src ) %{
7448 effect( DEF dst, USE src );
7449 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7450 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7451 ins_pipe(ialu_reg_reg);
7452 %}
7453
7454 // Arithmetic Shift Right by 8-bit immediate
7455 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7456 effect( DEF dst, USE src );
7457 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7458 opcode(Assembler::sra_op3, Assembler::arith_op);
7459 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7460 ins_pipe(ialu_reg_imm);
7461 %}
7462
7463 // Integer DIV with 10
7464 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7465 match(Set dst (DivI src div));
7466 ins_cost((6+6)*DEFAULT_COST);
7467 expand %{
7468 iRegIsafe tmp1; // Killed temps;
7469 iRegIsafe tmp2; // Killed temps;
7470 iRegI tmp3; // Killed temps;
7471 iRegI tmp4; // Killed temps;
7472 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7473 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7474 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7475 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7476 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7477 %}
7478 %}
7479
7480 // Register Long Division
7481 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7482 match(Set dst (DivL src1 src2));
7483 ins_cost(DEFAULT_COST*71);
7484 size(4);
7485 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7486 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7487 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7488 ins_pipe(divL_reg_reg);
7489 %}
7490
7491 // Register Long Division
7492 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7493 match(Set dst (DivL src1 src2));
7494 ins_cost(DEFAULT_COST*71);
7495 size(4);
7496 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7497 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7498 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7499 ins_pipe(divL_reg_imm);
7500 %}
7501
7502 // Integer Remainder
7503 // Register Remainder
7504 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7505 match(Set dst (ModI src1 src2));
7506 effect( KILL ccr, KILL temp);
7507
7508 format %{ "SREM $src1,$src2,$dst" %}
7509 ins_encode( irem_reg(src1, src2, dst, temp) );
7510 ins_pipe(sdiv_reg_reg);
7511 %}
7512
7513 // Immediate Remainder
7514 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7515 match(Set dst (ModI src1 src2));
7516 effect( KILL ccr, KILL temp);
7517
7518 format %{ "SREM $src1,$src2,$dst" %}
7519 ins_encode( irem_imm(src1, src2, dst, temp) );
7520 ins_pipe(sdiv_reg_imm);
7521 %}
7522
7523 // Register Long Remainder
7524 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7525 effect(DEF dst, USE src1, USE src2);
7526 size(4);
7527 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7528 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7529 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7530 ins_pipe(divL_reg_reg);
7531 %}
7532
7533 // Register Long Division
7534 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7535 effect(DEF dst, USE src1, USE src2);
7536 size(4);
7537 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7538 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7539 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7540 ins_pipe(divL_reg_imm);
7541 %}
7542
7543 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7544 effect(DEF dst, USE src1, USE src2);
7545 size(4);
7546 format %{ "MULX $src1,$src2,$dst\t! long" %}
7547 opcode(Assembler::mulx_op3, Assembler::arith_op);
7548 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7549 ins_pipe(mulL_reg_reg);
7550 %}
7551
7552 // Immediate Multiplication
7553 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7554 effect(DEF dst, USE src1, USE src2);
7555 size(4);
7556 format %{ "MULX $src1,$src2,$dst" %}
7557 opcode(Assembler::mulx_op3, Assembler::arith_op);
7558 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7559 ins_pipe(mulL_reg_imm);
7560 %}
7561
7562 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7563 effect(DEF dst, USE src1, USE src2);
7564 size(4);
7565 format %{ "SUB $src1,$src2,$dst\t! long" %}
7566 opcode(Assembler::sub_op3, Assembler::arith_op);
7567 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7568 ins_pipe(ialu_reg_reg);
7569 %}
7570
7571 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7572 effect(DEF dst, USE src1, USE src2);
7573 size(4);
7574 format %{ "SUB $src1,$src2,$dst\t! long" %}
7575 opcode(Assembler::sub_op3, Assembler::arith_op);
7576 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7577 ins_pipe(ialu_reg_reg);
7578 %}
7579
7580 // Register Long Remainder
7581 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7582 match(Set dst (ModL src1 src2));
7583 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7584 expand %{
7585 iRegL tmp1;
7586 iRegL tmp2;
7587 divL_reg_reg_1(tmp1, src1, src2);
7588 mulL_reg_reg_1(tmp2, tmp1, src2);
7589 subL_reg_reg_1(dst, src1, tmp2);
7590 %}
7591 %}
7592
7593 // Register Long Remainder
7594 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7595 match(Set dst (ModL src1 src2));
7596 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7597 expand %{
7598 iRegL tmp1;
7599 iRegL tmp2;
7600 divL_reg_imm13_1(tmp1, src1, src2);
7601 mulL_reg_imm13_1(tmp2, tmp1, src2);
7602 subL_reg_reg_2 (dst, src1, tmp2);
7603 %}
7604 %}
7605
7606 // Integer Shift Instructions
7607 // Register Shift Left
7608 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7609 match(Set dst (LShiftI src1 src2));
7610
7611 size(4);
7612 format %{ "SLL $src1,$src2,$dst" %}
7613 opcode(Assembler::sll_op3, Assembler::arith_op);
7614 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7615 ins_pipe(ialu_reg_reg);
7616 %}
7617
7618 // Register Shift Left Immediate
7619 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7620 match(Set dst (LShiftI src1 src2));
7621
7622 size(4);
7623 format %{ "SLL $src1,$src2,$dst" %}
7624 opcode(Assembler::sll_op3, Assembler::arith_op);
7625 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7626 ins_pipe(ialu_reg_imm);
7627 %}
7628
7629 // Register Shift Left
7630 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7631 match(Set dst (LShiftL src1 src2));
7632
7633 size(4);
7634 format %{ "SLLX $src1,$src2,$dst" %}
7635 opcode(Assembler::sllx_op3, Assembler::arith_op);
7636 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7637 ins_pipe(ialu_reg_reg);
7638 %}
7639
7640 // Register Shift Left Immediate
7641 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7642 match(Set dst (LShiftL src1 src2));
7643
7644 size(4);
7645 format %{ "SLLX $src1,$src2,$dst" %}
7646 opcode(Assembler::sllx_op3, Assembler::arith_op);
7647 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7648 ins_pipe(ialu_reg_imm);
7649 %}
7650
7651 // Register Arithmetic Shift Right
7652 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7653 match(Set dst (RShiftI src1 src2));
7654 size(4);
7655 format %{ "SRA $src1,$src2,$dst" %}
7656 opcode(Assembler::sra_op3, Assembler::arith_op);
7657 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7658 ins_pipe(ialu_reg_reg);
7659 %}
7660
7661 // Register Arithmetic Shift Right Immediate
7662 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7663 match(Set dst (RShiftI src1 src2));
7664
7665 size(4);
7666 format %{ "SRA $src1,$src2,$dst" %}
7667 opcode(Assembler::sra_op3, Assembler::arith_op);
7668 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7669 ins_pipe(ialu_reg_imm);
7670 %}
7671
7672 // Register Shift Right Arithmatic Long
7673 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7674 match(Set dst (RShiftL src1 src2));
7675
7676 size(4);
7677 format %{ "SRAX $src1,$src2,$dst" %}
7678 opcode(Assembler::srax_op3, Assembler::arith_op);
7679 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7680 ins_pipe(ialu_reg_reg);
7681 %}
7682
7683 // Register Shift Left Immediate
7684 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7685 match(Set dst (RShiftL src1 src2));
7686
7687 size(4);
7688 format %{ "SRAX $src1,$src2,$dst" %}
7689 opcode(Assembler::srax_op3, Assembler::arith_op);
7690 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7691 ins_pipe(ialu_reg_imm);
7692 %}
7693
7694 // Register Shift Right
7695 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7696 match(Set dst (URShiftI src1 src2));
7697
7698 size(4);
7699 format %{ "SRL $src1,$src2,$dst" %}
7700 opcode(Assembler::srl_op3, Assembler::arith_op);
7701 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7702 ins_pipe(ialu_reg_reg);
7703 %}
7704
7705 // Register Shift Right Immediate
7706 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7707 match(Set dst (URShiftI src1 src2));
7708
7709 size(4);
7710 format %{ "SRL $src1,$src2,$dst" %}
7711 opcode(Assembler::srl_op3, Assembler::arith_op);
7712 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7713 ins_pipe(ialu_reg_imm);
7714 %}
7715
7716 // Register Shift Right
7717 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7718 match(Set dst (URShiftL src1 src2));
7719
7720 size(4);
7721 format %{ "SRLX $src1,$src2,$dst" %}
7722 opcode(Assembler::srlx_op3, Assembler::arith_op);
7723 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7724 ins_pipe(ialu_reg_reg);
7725 %}
7726
7727 // Register Shift Right Immediate
7728 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7729 match(Set dst (URShiftL src1 src2));
7730
7731 size(4);
7732 format %{ "SRLX $src1,$src2,$dst" %}
7733 opcode(Assembler::srlx_op3, Assembler::arith_op);
7734 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7735 ins_pipe(ialu_reg_imm);
7736 %}
7737
7738 // Register Shift Right Immediate with a CastP2X
7739 #ifdef _LP64
7740 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7741 match(Set dst (URShiftL (CastP2X src1) src2));
7742 size(4);
7743 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7744 opcode(Assembler::srlx_op3, Assembler::arith_op);
7745 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7746 ins_pipe(ialu_reg_imm);
7747 %}
7748 #else
7749 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7750 match(Set dst (URShiftI (CastP2X src1) src2));
7751 size(4);
7752 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7753 opcode(Assembler::srl_op3, Assembler::arith_op);
7754 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7755 ins_pipe(ialu_reg_imm);
7756 %}
7757 #endif
7758
7759
7760 //----------Floating Point Arithmetic Instructions-----------------------------
7761
7762 // Add float single precision
7763 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7764 match(Set dst (AddF src1 src2));
7765
7766 size(4);
7767 format %{ "FADDS $src1,$src2,$dst" %}
7768 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7769 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7770 ins_pipe(faddF_reg_reg);
7771 %}
7772
7773 // Add float double precision
7774 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7775 match(Set dst (AddD src1 src2));
7776
7777 size(4);
7778 format %{ "FADDD $src1,$src2,$dst" %}
7779 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7780 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7781 ins_pipe(faddD_reg_reg);
7782 %}
7783
7784 // Sub float single precision
7785 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7786 match(Set dst (SubF src1 src2));
7787
7788 size(4);
7789 format %{ "FSUBS $src1,$src2,$dst" %}
7790 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7791 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7792 ins_pipe(faddF_reg_reg);
7793 %}
7794
7795 // Sub float double precision
7796 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7797 match(Set dst (SubD src1 src2));
7798
7799 size(4);
7800 format %{ "FSUBD $src1,$src2,$dst" %}
7801 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7802 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7803 ins_pipe(faddD_reg_reg);
7804 %}
7805
7806 // Mul float single precision
7807 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7808 match(Set dst (MulF src1 src2));
7809
7810 size(4);
7811 format %{ "FMULS $src1,$src2,$dst" %}
7812 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7813 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7814 ins_pipe(fmulF_reg_reg);
7815 %}
7816
7817 // Mul float double precision
7818 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7819 match(Set dst (MulD src1 src2));
7820
7821 size(4);
7822 format %{ "FMULD $src1,$src2,$dst" %}
7823 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7824 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7825 ins_pipe(fmulD_reg_reg);
7826 %}
7827
7828 // Div float single precision
7829 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7830 match(Set dst (DivF src1 src2));
7831
7832 size(4);
7833 format %{ "FDIVS $src1,$src2,$dst" %}
7834 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7835 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7836 ins_pipe(fdivF_reg_reg);
7837 %}
7838
7839 // Div float double precision
7840 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7841 match(Set dst (DivD src1 src2));
7842
7843 size(4);
7844 format %{ "FDIVD $src1,$src2,$dst" %}
7845 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7846 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7847 ins_pipe(fdivD_reg_reg);
7848 %}
7849
7850 // Absolute float double precision
7851 instruct absD_reg(regD dst, regD src) %{
7852 match(Set dst (AbsD src));
7853
7854 format %{ "FABSd $src,$dst" %}
7855 ins_encode(fabsd(dst, src));
7856 ins_pipe(faddD_reg);
7857 %}
7858
7859 // Absolute float single precision
7860 instruct absF_reg(regF dst, regF src) %{
7861 match(Set dst (AbsF src));
7862
7863 format %{ "FABSs $src,$dst" %}
7864 ins_encode(fabss(dst, src));
7865 ins_pipe(faddF_reg);
7866 %}
7867
7868 instruct negF_reg(regF dst, regF src) %{
7869 match(Set dst (NegF src));
7870
7871 size(4);
7872 format %{ "FNEGs $src,$dst" %}
7873 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7874 ins_encode(form3_opf_rs2F_rdF(src, dst));
7875 ins_pipe(faddF_reg);
7876 %}
7877
7878 instruct negD_reg(regD dst, regD src) %{
7879 match(Set dst (NegD src));
7880
7881 format %{ "FNEGd $src,$dst" %}
7882 ins_encode(fnegd(dst, src));
7883 ins_pipe(faddD_reg);
7884 %}
7885
7886 // Sqrt float double precision
7887 instruct sqrtF_reg_reg(regF dst, regF src) %{
7888 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7889
7890 size(4);
7891 format %{ "FSQRTS $src,$dst" %}
7892 ins_encode(fsqrts(dst, src));
7893 ins_pipe(fdivF_reg_reg);
7894 %}
7895
7896 // Sqrt float double precision
7897 instruct sqrtD_reg_reg(regD dst, regD src) %{
7898 match(Set dst (SqrtD src));
7899
7900 size(4);
7901 format %{ "FSQRTD $src,$dst" %}
7902 ins_encode(fsqrtd(dst, src));
7903 ins_pipe(fdivD_reg_reg);
7904 %}
7905
7906 //----------Logical Instructions-----------------------------------------------
7907 // And Instructions
7908 // Register And
7909 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7910 match(Set dst (AndI src1 src2));
7911
7912 size(4);
7913 format %{ "AND $src1,$src2,$dst" %}
7914 opcode(Assembler::and_op3, Assembler::arith_op);
7915 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7916 ins_pipe(ialu_reg_reg);
7917 %}
7918
7919 // Immediate And
7920 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7921 match(Set dst (AndI src1 src2));
7922
7923 size(4);
7924 format %{ "AND $src1,$src2,$dst" %}
7925 opcode(Assembler::and_op3, Assembler::arith_op);
7926 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7927 ins_pipe(ialu_reg_imm);
7928 %}
7929
7930 // Register And Long
7931 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7932 match(Set dst (AndL src1 src2));
7933
7934 ins_cost(DEFAULT_COST);
7935 size(4);
7936 format %{ "AND $src1,$src2,$dst\t! long" %}
7937 opcode(Assembler::and_op3, Assembler::arith_op);
7938 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7939 ins_pipe(ialu_reg_reg);
7940 %}
7941
7942 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7943 match(Set dst (AndL src1 con));
7944
7945 ins_cost(DEFAULT_COST);
7946 size(4);
7947 format %{ "AND $src1,$con,$dst\t! long" %}
7948 opcode(Assembler::and_op3, Assembler::arith_op);
7949 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7950 ins_pipe(ialu_reg_imm);
7951 %}
7952
7953 // Or Instructions
7954 // Register Or
7955 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7956 match(Set dst (OrI src1 src2));
7957
7958 size(4);
7959 format %{ "OR $src1,$src2,$dst" %}
7960 opcode(Assembler::or_op3, Assembler::arith_op);
7961 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7962 ins_pipe(ialu_reg_reg);
7963 %}
7964
7965 // Immediate Or
7966 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7967 match(Set dst (OrI src1 src2));
7968
7969 size(4);
7970 format %{ "OR $src1,$src2,$dst" %}
7971 opcode(Assembler::or_op3, Assembler::arith_op);
7972 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7973 ins_pipe(ialu_reg_imm);
7974 %}
7975
7976 // Register Or Long
7977 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7978 match(Set dst (OrL src1 src2));
7979
7980 ins_cost(DEFAULT_COST);
7981 size(4);
7982 format %{ "OR $src1,$src2,$dst\t! long" %}
7983 opcode(Assembler::or_op3, Assembler::arith_op);
7984 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7985 ins_pipe(ialu_reg_reg);
7986 %}
7987
7988 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7989 match(Set dst (OrL src1 con));
7990 ins_cost(DEFAULT_COST*2);
7991
7992 ins_cost(DEFAULT_COST);
7993 size(4);
7994 format %{ "OR $src1,$con,$dst\t! long" %}
7995 opcode(Assembler::or_op3, Assembler::arith_op);
7996 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7997 ins_pipe(ialu_reg_imm);
7998 %}
7999
8000 #ifndef _LP64
8001
8002 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8003 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8004 match(Set dst (OrI src1 (CastP2X src2)));
8005
8006 size(4);
8007 format %{ "OR $src1,$src2,$dst" %}
8008 opcode(Assembler::or_op3, Assembler::arith_op);
8009 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8010 ins_pipe(ialu_reg_reg);
8011 %}
8012
8013 #else
8014
8015 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8016 match(Set dst (OrL src1 (CastP2X src2)));
8017
8018 ins_cost(DEFAULT_COST);
8019 size(4);
8020 format %{ "OR $src1,$src2,$dst\t! long" %}
8021 opcode(Assembler::or_op3, Assembler::arith_op);
8022 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8023 ins_pipe(ialu_reg_reg);
8024 %}
8025
8026 #endif
8027
8028 // Xor Instructions
8029 // Register Xor
8030 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8031 match(Set dst (XorI src1 src2));
8032
8033 size(4);
8034 format %{ "XOR $src1,$src2,$dst" %}
8035 opcode(Assembler::xor_op3, Assembler::arith_op);
8036 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8037 ins_pipe(ialu_reg_reg);
8038 %}
8039
8040 // Immediate Xor
8041 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8042 match(Set dst (XorI src1 src2));
8043
8044 size(4);
8045 format %{ "XOR $src1,$src2,$dst" %}
8046 opcode(Assembler::xor_op3, Assembler::arith_op);
8047 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8048 ins_pipe(ialu_reg_imm);
8049 %}
8050
8051 // Register Xor Long
8052 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8053 match(Set dst (XorL src1 src2));
8054
8055 ins_cost(DEFAULT_COST);
8056 size(4);
8057 format %{ "XOR $src1,$src2,$dst\t! long" %}
8058 opcode(Assembler::xor_op3, Assembler::arith_op);
8059 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8060 ins_pipe(ialu_reg_reg);
8061 %}
8062
8063 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8064 match(Set dst (XorL src1 con));
8065
8066 ins_cost(DEFAULT_COST);
8067 size(4);
8068 format %{ "XOR $src1,$con,$dst\t! long" %}
8069 opcode(Assembler::xor_op3, Assembler::arith_op);
8070 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8071 ins_pipe(ialu_reg_imm);
8072 %}
8073
8074 //----------Convert to Boolean-------------------------------------------------
8075 // Nice hack for 32-bit tests but doesn't work for
8076 // 64-bit pointers.
8077 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8078 match(Set dst (Conv2B src));
8079 effect( KILL ccr );
8080 ins_cost(DEFAULT_COST*2);
8081 format %{ "CMP R_G0,$src\n\t"
8082 "ADDX R_G0,0,$dst" %}
8083 ins_encode( enc_to_bool( src, dst ) );
8084 ins_pipe(ialu_reg_ialu);
8085 %}
8086
8087 #ifndef _LP64
8088 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8089 match(Set dst (Conv2B src));
8090 effect( KILL ccr );
8091 ins_cost(DEFAULT_COST*2);
8092 format %{ "CMP R_G0,$src\n\t"
8093 "ADDX R_G0,0,$dst" %}
8094 ins_encode( enc_to_bool( src, dst ) );
8095 ins_pipe(ialu_reg_ialu);
8096 %}
8097 #else
8098 instruct convP2B( iRegI dst, iRegP src ) %{
8099 match(Set dst (Conv2B src));
8100 ins_cost(DEFAULT_COST*2);
8101 format %{ "MOV $src,$dst\n\t"
8102 "MOVRNZ $src,1,$dst" %}
8103 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8104 ins_pipe(ialu_clr_and_mover);
8105 %}
8106 #endif
8107
8108 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8109 match(Set dst (CmpLTMask src zero));
8110 effect(KILL ccr);
8111 size(4);
8112 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8113 ins_encode %{
8114 __ sra($src$$Register, 31, $dst$$Register);
8115 %}
8116 ins_pipe(ialu_reg_imm);
8117 %}
8118
8119 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8120 match(Set dst (CmpLTMask p q));
8121 effect( KILL ccr );
8122 ins_cost(DEFAULT_COST*4);
8123 format %{ "CMP $p,$q\n\t"
8124 "MOV #0,$dst\n\t"
8125 "BLT,a .+8\n\t"
8126 "MOV #-1,$dst" %}
8127 ins_encode( enc_ltmask(p,q,dst) );
8128 ins_pipe(ialu_reg_reg_ialu);
8129 %}
8130
8131 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8132 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8133 effect(KILL ccr, TEMP tmp);
8134 ins_cost(DEFAULT_COST*3);
8135
8136 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8137 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8138 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8139 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8140 ins_pipe( cadd_cmpltmask );
8141 %}
8142
8143
8144 //-----------------------------------------------------------------
8145 // Direct raw moves between float and general registers using VIS3.
8146
8147 // ins_pipe(faddF_reg);
8148 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8149 predicate(UseVIS >= 3);
8150 match(Set dst (MoveF2I src));
8151
8152 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8153 ins_encode %{
8154 __ movstouw($src$$FloatRegister, $dst$$Register);
8155 %}
8156 ins_pipe(ialu_reg_reg);
8157 %}
8158
8159 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8160 predicate(UseVIS >= 3);
8161 match(Set dst (MoveI2F src));
8162
8163 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8164 ins_encode %{
8165 __ movwtos($src$$Register, $dst$$FloatRegister);
8166 %}
8167 ins_pipe(ialu_reg_reg);
8168 %}
8169
8170 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8171 predicate(UseVIS >= 3);
8172 match(Set dst (MoveD2L src));
8173
8174 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8175 ins_encode %{
8176 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8177 %}
8178 ins_pipe(ialu_reg_reg);
8179 %}
8180
8181 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8182 predicate(UseVIS >= 3);
8183 match(Set dst (MoveL2D src));
8184
8185 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8186 ins_encode %{
8187 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8188 %}
8189 ins_pipe(ialu_reg_reg);
8190 %}
8191
8192
8193 // Raw moves between float and general registers using stack.
8194
8195 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8196 match(Set dst (MoveF2I src));
8197 effect(DEF dst, USE src);
8198 ins_cost(MEMORY_REF_COST);
8199
8200 size(4);
8201 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8202 opcode(Assembler::lduw_op3);
8203 ins_encode(simple_form3_mem_reg( src, dst ) );
8204 ins_pipe(iload_mem);
8205 %}
8206
8207 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8208 match(Set dst (MoveI2F src));
8209 effect(DEF dst, USE src);
8210 ins_cost(MEMORY_REF_COST);
8211
8212 size(4);
8213 format %{ "LDF $src,$dst\t! MoveI2F" %}
8214 opcode(Assembler::ldf_op3);
8215 ins_encode(simple_form3_mem_reg(src, dst));
8216 ins_pipe(floadF_stk);
8217 %}
8218
8219 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8220 match(Set dst (MoveD2L src));
8221 effect(DEF dst, USE src);
8222 ins_cost(MEMORY_REF_COST);
8223
8224 size(4);
8225 format %{ "LDX $src,$dst\t! MoveD2L" %}
8226 opcode(Assembler::ldx_op3);
8227 ins_encode(simple_form3_mem_reg( src, dst ) );
8228 ins_pipe(iload_mem);
8229 %}
8230
8231 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8232 match(Set dst (MoveL2D src));
8233 effect(DEF dst, USE src);
8234 ins_cost(MEMORY_REF_COST);
8235
8236 size(4);
8237 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8238 opcode(Assembler::lddf_op3);
8239 ins_encode(simple_form3_mem_reg(src, dst));
8240 ins_pipe(floadD_stk);
8241 %}
8242
8243 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8244 match(Set dst (MoveF2I src));
8245 effect(DEF dst, USE src);
8246 ins_cost(MEMORY_REF_COST);
8247
8248 size(4);
8249 format %{ "STF $src,$dst\t! MoveF2I" %}
8250 opcode(Assembler::stf_op3);
8251 ins_encode(simple_form3_mem_reg(dst, src));
8252 ins_pipe(fstoreF_stk_reg);
8253 %}
8254
8255 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8256 match(Set dst (MoveI2F src));
8257 effect(DEF dst, USE src);
8258 ins_cost(MEMORY_REF_COST);
8259
8260 size(4);
8261 format %{ "STW $src,$dst\t! MoveI2F" %}
8262 opcode(Assembler::stw_op3);
8263 ins_encode(simple_form3_mem_reg( dst, src ) );
8264 ins_pipe(istore_mem_reg);
8265 %}
8266
8267 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8268 match(Set dst (MoveD2L src));
8269 effect(DEF dst, USE src);
8270 ins_cost(MEMORY_REF_COST);
8271
8272 size(4);
8273 format %{ "STDF $src,$dst\t! MoveD2L" %}
8274 opcode(Assembler::stdf_op3);
8275 ins_encode(simple_form3_mem_reg(dst, src));
8276 ins_pipe(fstoreD_stk_reg);
8277 %}
8278
8279 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8280 match(Set dst (MoveL2D src));
8281 effect(DEF dst, USE src);
8282 ins_cost(MEMORY_REF_COST);
8283
8284 size(4);
8285 format %{ "STX $src,$dst\t! MoveL2D" %}
8286 opcode(Assembler::stx_op3);
8287 ins_encode(simple_form3_mem_reg( dst, src ) );
8288 ins_pipe(istore_mem_reg);
8289 %}
8290
8291
8292 //----------Arithmetic Conversion Instructions---------------------------------
8293 // The conversions operations are all Alpha sorted. Please keep it that way!
8294
8295 instruct convD2F_reg(regF dst, regD src) %{
8296 match(Set dst (ConvD2F src));
8297 size(4);
8298 format %{ "FDTOS $src,$dst" %}
8299 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8300 ins_encode(form3_opf_rs2D_rdF(src, dst));
8301 ins_pipe(fcvtD2F);
8302 %}
8303
8304
8305 // Convert a double to an int in a float register.
8306 // If the double is a NAN, stuff a zero in instead.
8307 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8308 effect(DEF dst, USE src, KILL fcc0);
8309 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8310 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8311 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8312 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8313 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8314 "skip:" %}
8315 ins_encode(form_d2i_helper(src,dst));
8316 ins_pipe(fcvtD2I);
8317 %}
8318
8319 instruct convD2I_stk(stackSlotI dst, regD src) %{
8320 match(Set dst (ConvD2I src));
8321 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8322 expand %{
8323 regF tmp;
8324 convD2I_helper(tmp, src);
8325 regF_to_stkI(dst, tmp);
8326 %}
8327 %}
8328
8329 instruct convD2I_reg(iRegI dst, regD src) %{
8330 predicate(UseVIS >= 3);
8331 match(Set dst (ConvD2I src));
8332 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8333 expand %{
8334 regF tmp;
8335 convD2I_helper(tmp, src);
8336 MoveF2I_reg_reg(dst, tmp);
8337 %}
8338 %}
8339
8340
8341 // Convert a double to a long in a double register.
8342 // If the double is a NAN, stuff a zero in instead.
8343 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8344 effect(DEF dst, USE src, KILL fcc0);
8345 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8346 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8347 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8348 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8349 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8350 "skip:" %}
8351 ins_encode(form_d2l_helper(src,dst));
8352 ins_pipe(fcvtD2L);
8353 %}
8354
8355 instruct convD2L_stk(stackSlotL dst, regD src) %{
8356 match(Set dst (ConvD2L src));
8357 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8358 expand %{
8359 regD tmp;
8360 convD2L_helper(tmp, src);
8361 regD_to_stkL(dst, tmp);
8362 %}
8363 %}
8364
8365 instruct convD2L_reg(iRegL dst, regD src) %{
8366 predicate(UseVIS >= 3);
8367 match(Set dst (ConvD2L src));
8368 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8369 expand %{
8370 regD tmp;
8371 convD2L_helper(tmp, src);
8372 MoveD2L_reg_reg(dst, tmp);
8373 %}
8374 %}
8375
8376
8377 instruct convF2D_reg(regD dst, regF src) %{
8378 match(Set dst (ConvF2D src));
8379 format %{ "FSTOD $src,$dst" %}
8380 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8381 ins_encode(form3_opf_rs2F_rdD(src, dst));
8382 ins_pipe(fcvtF2D);
8383 %}
8384
8385
8386 // Convert a float to an int in a float register.
8387 // If the float is a NAN, stuff a zero in instead.
8388 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8389 effect(DEF dst, USE src, KILL fcc0);
8390 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8391 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8392 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8393 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8394 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8395 "skip:" %}
8396 ins_encode(form_f2i_helper(src,dst));
8397 ins_pipe(fcvtF2I);
8398 %}
8399
8400 instruct convF2I_stk(stackSlotI dst, regF src) %{
8401 match(Set dst (ConvF2I src));
8402 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8403 expand %{
8404 regF tmp;
8405 convF2I_helper(tmp, src);
8406 regF_to_stkI(dst, tmp);
8407 %}
8408 %}
8409
8410 instruct convF2I_reg(iRegI dst, regF src) %{
8411 predicate(UseVIS >= 3);
8412 match(Set dst (ConvF2I src));
8413 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8414 expand %{
8415 regF tmp;
8416 convF2I_helper(tmp, src);
8417 MoveF2I_reg_reg(dst, tmp);
8418 %}
8419 %}
8420
8421
8422 // Convert a float to a long in a float register.
8423 // If the float is a NAN, stuff a zero in instead.
8424 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8425 effect(DEF dst, USE src, KILL fcc0);
8426 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8427 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8428 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8429 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8430 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8431 "skip:" %}
8432 ins_encode(form_f2l_helper(src,dst));
8433 ins_pipe(fcvtF2L);
8434 %}
8435
8436 instruct convF2L_stk(stackSlotL dst, regF src) %{
8437 match(Set dst (ConvF2L src));
8438 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8439 expand %{
8440 regD tmp;
8441 convF2L_helper(tmp, src);
8442 regD_to_stkL(dst, tmp);
8443 %}
8444 %}
8445
8446 instruct convF2L_reg(iRegL dst, regF src) %{
8447 predicate(UseVIS >= 3);
8448 match(Set dst (ConvF2L src));
8449 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8450 expand %{
8451 regD tmp;
8452 convF2L_helper(tmp, src);
8453 MoveD2L_reg_reg(dst, tmp);
8454 %}
8455 %}
8456
8457
8458 instruct convI2D_helper(regD dst, regF tmp) %{
8459 effect(USE tmp, DEF dst);
8460 format %{ "FITOD $tmp,$dst" %}
8461 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8462 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8463 ins_pipe(fcvtI2D);
8464 %}
8465
8466 instruct convI2D_stk(stackSlotI src, regD dst) %{
8467 match(Set dst (ConvI2D src));
8468 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8469 expand %{
8470 regF tmp;
8471 stkI_to_regF(tmp, src);
8472 convI2D_helper(dst, tmp);
8473 %}
8474 %}
8475
8476 instruct convI2D_reg(regD_low dst, iRegI src) %{
8477 predicate(UseVIS >= 3);
8478 match(Set dst (ConvI2D src));
8479 expand %{
8480 regF tmp;
8481 MoveI2F_reg_reg(tmp, src);
8482 convI2D_helper(dst, tmp);
8483 %}
8484 %}
8485
8486 instruct convI2D_mem(regD_low dst, memory mem) %{
8487 match(Set dst (ConvI2D (LoadI mem)));
8488 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8489 size(8);
8490 format %{ "LDF $mem,$dst\n\t"
8491 "FITOD $dst,$dst" %}
8492 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8493 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8494 ins_pipe(floadF_mem);
8495 %}
8496
8497
8498 instruct convI2F_helper(regF dst, regF tmp) %{
8499 effect(DEF dst, USE tmp);
8500 format %{ "FITOS $tmp,$dst" %}
8501 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8502 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8503 ins_pipe(fcvtI2F);
8504 %}
8505
8506 instruct convI2F_stk(regF dst, stackSlotI src) %{
8507 match(Set dst (ConvI2F src));
8508 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8509 expand %{
8510 regF tmp;
8511 stkI_to_regF(tmp,src);
8512 convI2F_helper(dst, tmp);
8513 %}
8514 %}
8515
8516 instruct convI2F_reg(regF dst, iRegI src) %{
8517 predicate(UseVIS >= 3);
8518 match(Set dst (ConvI2F src));
8519 ins_cost(DEFAULT_COST);
8520 expand %{
8521 regF tmp;
8522 MoveI2F_reg_reg(tmp, src);
8523 convI2F_helper(dst, tmp);
8524 %}
8525 %}
8526
8527 instruct convI2F_mem( regF dst, memory mem ) %{
8528 match(Set dst (ConvI2F (LoadI mem)));
8529 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8530 size(8);
8531 format %{ "LDF $mem,$dst\n\t"
8532 "FITOS $dst,$dst" %}
8533 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8534 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8535 ins_pipe(floadF_mem);
8536 %}
8537
8538
8539 instruct convI2L_reg(iRegL dst, iRegI src) %{
8540 match(Set dst (ConvI2L src));
8541 size(4);
8542 format %{ "SRA $src,0,$dst\t! int->long" %}
8543 opcode(Assembler::sra_op3, Assembler::arith_op);
8544 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8545 ins_pipe(ialu_reg_reg);
8546 %}
8547
8548 // Zero-extend convert int to long
8549 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8550 match(Set dst (AndL (ConvI2L src) mask) );
8551 size(4);
8552 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8553 opcode(Assembler::srl_op3, Assembler::arith_op);
8554 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8555 ins_pipe(ialu_reg_reg);
8556 %}
8557
8558 // Zero-extend long
8559 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8560 match(Set dst (AndL src mask) );
8561 size(4);
8562 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8563 opcode(Assembler::srl_op3, Assembler::arith_op);
8564 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8565 ins_pipe(ialu_reg_reg);
8566 %}
8567
8568
8569 //-----------
8570 // Long to Double conversion using V8 opcodes.
8571 // Still useful because cheetah traps and becomes
8572 // amazingly slow for some common numbers.
8573
8574 // Magic constant, 0x43300000
8575 instruct loadConI_x43300000(iRegI dst) %{
8576 effect(DEF dst);
8577 size(4);
8578 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8579 ins_encode(SetHi22(0x43300000, dst));
8580 ins_pipe(ialu_none);
8581 %}
8582
8583 // Magic constant, 0x41f00000
8584 instruct loadConI_x41f00000(iRegI dst) %{
8585 effect(DEF dst);
8586 size(4);
8587 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8588 ins_encode(SetHi22(0x41f00000, dst));
8589 ins_pipe(ialu_none);
8590 %}
8591
8592 // Construct a double from two float halves
8593 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8594 effect(DEF dst, USE src1, USE src2);
8595 size(8);
8596 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8597 "FMOVS $src2.lo,$dst.lo" %}
8598 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8599 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8600 ins_pipe(faddD_reg_reg);
8601 %}
8602
8603 // Convert integer in high half of a double register (in the lower half of
8604 // the double register file) to double
8605 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8606 effect(DEF dst, USE src);
8607 size(4);
8608 format %{ "FITOD $src,$dst" %}
8609 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8610 ins_encode(form3_opf_rs2D_rdD(src, dst));
8611 ins_pipe(fcvtLHi2D);
8612 %}
8613
8614 // Add float double precision
8615 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8616 effect(DEF dst, USE src1, USE src2);
8617 size(4);
8618 format %{ "FADDD $src1,$src2,$dst" %}
8619 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8620 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8621 ins_pipe(faddD_reg_reg);
8622 %}
8623
8624 // Sub float double precision
8625 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8626 effect(DEF dst, USE src1, USE src2);
8627 size(4);
8628 format %{ "FSUBD $src1,$src2,$dst" %}
8629 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8630 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8631 ins_pipe(faddD_reg_reg);
8632 %}
8633
8634 // Mul float double precision
8635 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8636 effect(DEF dst, USE src1, USE src2);
8637 size(4);
8638 format %{ "FMULD $src1,$src2,$dst" %}
8639 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8640 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8641 ins_pipe(fmulD_reg_reg);
8642 %}
8643
8644 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8645 match(Set dst (ConvL2D src));
8646 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8647
8648 expand %{
8649 regD_low tmpsrc;
8650 iRegI ix43300000;
8651 iRegI ix41f00000;
8652 stackSlotL lx43300000;
8653 stackSlotL lx41f00000;
8654 regD_low dx43300000;
8655 regD dx41f00000;
8656 regD tmp1;
8657 regD_low tmp2;
8658 regD tmp3;
8659 regD tmp4;
8660
8661 stkL_to_regD(tmpsrc, src);
8662
8663 loadConI_x43300000(ix43300000);
8664 loadConI_x41f00000(ix41f00000);
8665 regI_to_stkLHi(lx43300000, ix43300000);
8666 regI_to_stkLHi(lx41f00000, ix41f00000);
8667 stkL_to_regD(dx43300000, lx43300000);
8668 stkL_to_regD(dx41f00000, lx41f00000);
8669
8670 convI2D_regDHi_regD(tmp1, tmpsrc);
8671 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8672 subD_regD_regD(tmp3, tmp2, dx43300000);
8673 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8674 addD_regD_regD(dst, tmp3, tmp4);
8675 %}
8676 %}
8677
8678 // Long to Double conversion using fast fxtof
8679 instruct convL2D_helper(regD dst, regD tmp) %{
8680 effect(DEF dst, USE tmp);
8681 size(4);
8682 format %{ "FXTOD $tmp,$dst" %}
8683 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8684 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8685 ins_pipe(fcvtL2D);
8686 %}
8687
8688 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8689 predicate(VM_Version::has_fast_fxtof());
8690 match(Set dst (ConvL2D src));
8691 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8692 expand %{
8693 regD tmp;
8694 stkL_to_regD(tmp, src);
8695 convL2D_helper(dst, tmp);
8696 %}
8697 %}
8698
8699 instruct convL2D_reg(regD dst, iRegL src) %{
8700 predicate(UseVIS >= 3);
8701 match(Set dst (ConvL2D src));
8702 expand %{
8703 regD tmp;
8704 MoveL2D_reg_reg(tmp, src);
8705 convL2D_helper(dst, tmp);
8706 %}
8707 %}
8708
8709 // Long to Float conversion using fast fxtof
8710 instruct convL2F_helper(regF dst, regD tmp) %{
8711 effect(DEF dst, USE tmp);
8712 size(4);
8713 format %{ "FXTOS $tmp,$dst" %}
8714 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8715 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8716 ins_pipe(fcvtL2F);
8717 %}
8718
8719 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8720 match(Set dst (ConvL2F src));
8721 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8722 expand %{
8723 regD tmp;
8724 stkL_to_regD(tmp, src);
8725 convL2F_helper(dst, tmp);
8726 %}
8727 %}
8728
8729 instruct convL2F_reg(regF dst, iRegL src) %{
8730 predicate(UseVIS >= 3);
8731 match(Set dst (ConvL2F src));
8732 ins_cost(DEFAULT_COST);
8733 expand %{
8734 regD tmp;
8735 MoveL2D_reg_reg(tmp, src);
8736 convL2F_helper(dst, tmp);
8737 %}
8738 %}
8739
8740 //-----------
8741
8742 instruct convL2I_reg(iRegI dst, iRegL src) %{
8743 match(Set dst (ConvL2I src));
8744 #ifndef _LP64
8745 format %{ "MOV $src.lo,$dst\t! long->int" %}
8746 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8747 ins_pipe(ialu_move_reg_I_to_L);
8748 #else
8749 size(4);
8750 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8751 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8752 ins_pipe(ialu_reg);
8753 #endif
8754 %}
8755
8756 // Register Shift Right Immediate
8757 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8758 match(Set dst (ConvL2I (RShiftL src cnt)));
8759
8760 size(4);
8761 format %{ "SRAX $src,$cnt,$dst" %}
8762 opcode(Assembler::srax_op3, Assembler::arith_op);
8763 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8764 ins_pipe(ialu_reg_imm);
8765 %}
8766
8767 // Replicate scalar to packed byte values in Double register
8768 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8769 effect(DEF dst, USE src);
8770 format %{ "SLLX $src,56,$dst\n\t"
8771 "SRLX $dst, 8,O7\n\t"
8772 "OR $dst,O7,$dst\n\t"
8773 "SRLX $dst,16,O7\n\t"
8774 "OR $dst,O7,$dst\n\t"
8775 "SRLX $dst,32,O7\n\t"
8776 "OR $dst,O7,$dst\t! replicate8B" %}
8777 ins_encode( enc_repl8b(src, dst));
8778 ins_pipe(ialu_reg);
8779 %}
8780
8781 // Replicate scalar to packed byte values in Double register
8782 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8783 match(Set dst (Replicate8B src));
8784 expand %{
8785 iRegL tmp;
8786 Repl8B_reg_helper(tmp, src);
8787 regL_to_stkD(dst, tmp);
8788 %}
8789 %}
8790
8791 // Replicate scalar constant to packed byte values in Double register
8792 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
8793 match(Set dst (Replicate8B con));
8794 effect(KILL tmp);
8795 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8796 ins_encode %{
8797 // XXX This is a quick fix for 6833573.
8798 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8799 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
8800 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8801 %}
8802 ins_pipe(loadConFD);
8803 %}
8804
8805 // Replicate scalar to packed char values into stack slot
8806 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8807 effect(DEF dst, USE src);
8808 format %{ "SLLX $src,48,$dst\n\t"
8809 "SRLX $dst,16,O7\n\t"
8810 "OR $dst,O7,$dst\n\t"
8811 "SRLX $dst,32,O7\n\t"
8812 "OR $dst,O7,$dst\t! replicate4C" %}
8813 ins_encode( enc_repl4s(src, dst) );
8814 ins_pipe(ialu_reg);
8815 %}
8816
8817 // Replicate scalar to packed char values into stack slot
8818 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8819 match(Set dst (Replicate4C src));
8820 expand %{
8821 iRegL tmp;
8822 Repl4C_reg_helper(tmp, src);
8823 regL_to_stkD(dst, tmp);
8824 %}
8825 %}
8826
8827 // Replicate scalar constant to packed char values in Double register
8828 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
8829 match(Set dst (Replicate4C con));
8830 effect(KILL tmp);
8831 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8832 ins_encode %{
8833 // XXX This is a quick fix for 6833573.
8834 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8835 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8836 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8837 %}
8838 ins_pipe(loadConFD);
8839 %}
8840
8841 // Replicate scalar to packed short values into stack slot
8842 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8843 effect(DEF dst, USE src);
8844 format %{ "SLLX $src,48,$dst\n\t"
8845 "SRLX $dst,16,O7\n\t"
8846 "OR $dst,O7,$dst\n\t"
8847 "SRLX $dst,32,O7\n\t"
8848 "OR $dst,O7,$dst\t! replicate4S" %}
8849 ins_encode( enc_repl4s(src, dst) );
8850 ins_pipe(ialu_reg);
8851 %}
8852
8853 // Replicate scalar to packed short values into stack slot
8854 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8855 match(Set dst (Replicate4S src));
8856 expand %{
8857 iRegL tmp;
8858 Repl4S_reg_helper(tmp, src);
8859 regL_to_stkD(dst, tmp);
8860 %}
8861 %}
8862
8863 // Replicate scalar constant to packed short values in Double register
8864 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
8865 match(Set dst (Replicate4S con));
8866 effect(KILL tmp);
8867 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8868 ins_encode %{
8869 // XXX This is a quick fix for 6833573.
8870 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8871 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8872 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8873 %}
8874 ins_pipe(loadConFD);
8875 %}
8876
8877 // Replicate scalar to packed int values in Double register
8878 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8879 effect(DEF dst, USE src);
8880 format %{ "SLLX $src,32,$dst\n\t"
8881 "SRLX $dst,32,O7\n\t"
8882 "OR $dst,O7,$dst\t! replicate2I" %}
8883 ins_encode( enc_repl2i(src, dst));
8884 ins_pipe(ialu_reg);
8885 %}
8886
8887 // Replicate scalar to packed int values in Double register
8888 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8889 match(Set dst (Replicate2I src));
8890 expand %{
8891 iRegL tmp;
8892 Repl2I_reg_helper(tmp, src);
8893 regL_to_stkD(dst, tmp);
8894 %}
8895 %}
8896
8897 // Replicate scalar zero constant to packed int values in Double register
8898 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
8899 match(Set dst (Replicate2I con));
8900 effect(KILL tmp);
8901 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
8902 ins_encode %{
8903 // XXX This is a quick fix for 6833573.
8904 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
8905 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
8906 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8907 %}
8908 ins_pipe(loadConFD);
8909 %}
8910
8911 //----------Control Flow Instructions------------------------------------------
8912 // Compare Instructions
8913 // Compare Integers
8914 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8915 match(Set icc (CmpI op1 op2));
8916 effect( DEF icc, USE op1, USE op2 );
8917
8918 size(4);
8919 format %{ "CMP $op1,$op2" %}
8920 opcode(Assembler::subcc_op3, Assembler::arith_op);
8921 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8922 ins_pipe(ialu_cconly_reg_reg);
8923 %}
8924
8925 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8926 match(Set icc (CmpU op1 op2));
8927
8928 size(4);
8929 format %{ "CMP $op1,$op2\t! unsigned" %}
8930 opcode(Assembler::subcc_op3, Assembler::arith_op);
8931 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8932 ins_pipe(ialu_cconly_reg_reg);
8933 %}
8934
8935 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8936 match(Set icc (CmpI op1 op2));
8937 effect( DEF icc, USE op1 );
8938
8939 size(4);
8940 format %{ "CMP $op1,$op2" %}
8941 opcode(Assembler::subcc_op3, Assembler::arith_op);
8942 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8943 ins_pipe(ialu_cconly_reg_imm);
8944 %}
8945
8946 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8947 match(Set icc (CmpI (AndI op1 op2) zero));
8948
8949 size(4);
8950 format %{ "BTST $op2,$op1" %}
8951 opcode(Assembler::andcc_op3, Assembler::arith_op);
8952 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8953 ins_pipe(ialu_cconly_reg_reg_zero);
8954 %}
8955
8956 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8957 match(Set icc (CmpI (AndI op1 op2) zero));
8958
8959 size(4);
8960 format %{ "BTST $op2,$op1" %}
8961 opcode(Assembler::andcc_op3, Assembler::arith_op);
8962 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8963 ins_pipe(ialu_cconly_reg_imm_zero);
8964 %}
8965
8966 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8967 match(Set xcc (CmpL op1 op2));
8968 effect( DEF xcc, USE op1, USE op2 );
8969
8970 size(4);
8971 format %{ "CMP $op1,$op2\t\t! long" %}
8972 opcode(Assembler::subcc_op3, Assembler::arith_op);
8973 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8974 ins_pipe(ialu_cconly_reg_reg);
8975 %}
8976
8977 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8978 match(Set xcc (CmpL op1 con));
8979 effect( DEF xcc, USE op1, USE con );
8980
8981 size(4);
8982 format %{ "CMP $op1,$con\t\t! long" %}
8983 opcode(Assembler::subcc_op3, Assembler::arith_op);
8984 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8985 ins_pipe(ialu_cconly_reg_reg);
8986 %}
8987
8988 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8989 match(Set xcc (CmpL (AndL op1 op2) zero));
8990 effect( DEF xcc, USE op1, USE op2 );
8991
8992 size(4);
8993 format %{ "BTST $op1,$op2\t\t! long" %}
8994 opcode(Assembler::andcc_op3, Assembler::arith_op);
8995 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8996 ins_pipe(ialu_cconly_reg_reg);
8997 %}
8998
8999 // useful for checking the alignment of a pointer:
9000 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
9001 match(Set xcc (CmpL (AndL op1 con) zero));
9002 effect( DEF xcc, USE op1, USE con );
9003
9004 size(4);
9005 format %{ "BTST $op1,$con\t\t! long" %}
9006 opcode(Assembler::andcc_op3, Assembler::arith_op);
9007 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9008 ins_pipe(ialu_cconly_reg_reg);
9009 %}
9010
9011 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
9012 match(Set icc (CmpU op1 op2));
9013
9014 size(4);
9015 format %{ "CMP $op1,$op2\t! unsigned" %}
9016 opcode(Assembler::subcc_op3, Assembler::arith_op);
9017 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9018 ins_pipe(ialu_cconly_reg_imm);
9019 %}
9020
9021 // Compare Pointers
9022 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9023 match(Set pcc (CmpP op1 op2));
9024
9025 size(4);
9026 format %{ "CMP $op1,$op2\t! ptr" %}
9027 opcode(Assembler::subcc_op3, Assembler::arith_op);
9028 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9029 ins_pipe(ialu_cconly_reg_reg);
9030 %}
9031
9032 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9033 match(Set pcc (CmpP op1 op2));
9034
9035 size(4);
9036 format %{ "CMP $op1,$op2\t! ptr" %}
9037 opcode(Assembler::subcc_op3, Assembler::arith_op);
9038 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9039 ins_pipe(ialu_cconly_reg_imm);
9040 %}
9041
9042 // Compare Narrow oops
9043 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9044 match(Set icc (CmpN op1 op2));
9045
9046 size(4);
9047 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9048 opcode(Assembler::subcc_op3, Assembler::arith_op);
9049 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9050 ins_pipe(ialu_cconly_reg_reg);
9051 %}
9052
9053 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9054 match(Set icc (CmpN op1 op2));
9055
9056 size(4);
9057 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9058 opcode(Assembler::subcc_op3, Assembler::arith_op);
9059 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9060 ins_pipe(ialu_cconly_reg_imm);
9061 %}
9062
9063 //----------Max and Min--------------------------------------------------------
9064 // Min Instructions
9065 // Conditional move for min
9066 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9067 effect( USE_DEF op2, USE op1, USE icc );
9068
9069 size(4);
9070 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9071 opcode(Assembler::less);
9072 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9073 ins_pipe(ialu_reg_flags);
9074 %}
9075
9076 // Min Register with Register.
9077 instruct minI_eReg(iRegI op1, iRegI op2) %{
9078 match(Set op2 (MinI op1 op2));
9079 ins_cost(DEFAULT_COST*2);
9080 expand %{
9081 flagsReg icc;
9082 compI_iReg(icc,op1,op2);
9083 cmovI_reg_lt(op2,op1,icc);
9084 %}
9085 %}
9086
9087 // Max Instructions
9088 // Conditional move for max
9089 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9090 effect( USE_DEF op2, USE op1, USE icc );
9091 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9092 opcode(Assembler::greater);
9093 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9094 ins_pipe(ialu_reg_flags);
9095 %}
9096
9097 // Max Register with Register
9098 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9099 match(Set op2 (MaxI op1 op2));
9100 ins_cost(DEFAULT_COST*2);
9101 expand %{
9102 flagsReg icc;
9103 compI_iReg(icc,op1,op2);
9104 cmovI_reg_gt(op2,op1,icc);
9105 %}
9106 %}
9107
9108
9109 //----------Float Compares----------------------------------------------------
9110 // Compare floating, generate condition code
9111 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9112 match(Set fcc (CmpF src1 src2));
9113
9114 size(4);
9115 format %{ "FCMPs $fcc,$src1,$src2" %}
9116 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9117 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9118 ins_pipe(faddF_fcc_reg_reg_zero);
9119 %}
9120
9121 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9122 match(Set fcc (CmpD src1 src2));
9123
9124 size(4);
9125 format %{ "FCMPd $fcc,$src1,$src2" %}
9126 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9127 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9128 ins_pipe(faddD_fcc_reg_reg_zero);
9129 %}
9130
9131
9132 // Compare floating, generate -1,0,1
9133 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9134 match(Set dst (CmpF3 src1 src2));
9135 effect(KILL fcc0);
9136 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9137 format %{ "fcmpl $dst,$src1,$src2" %}
9138 // Primary = float
9139 opcode( true );
9140 ins_encode( floating_cmp( dst, src1, src2 ) );
9141 ins_pipe( floating_cmp );
9142 %}
9143
9144 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9145 match(Set dst (CmpD3 src1 src2));
9146 effect(KILL fcc0);
9147 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9148 format %{ "dcmpl $dst,$src1,$src2" %}
9149 // Primary = double (not float)
9150 opcode( false );
9151 ins_encode( floating_cmp( dst, src1, src2 ) );
9152 ins_pipe( floating_cmp );
9153 %}
9154
9155 //----------Branches---------------------------------------------------------
9156 // Jump
9157 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9158 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9159 match(Jump switch_val);
9160
9161 ins_cost(350);
9162
9163 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9164 "LD [O7 + $switch_val], O7\n\t"
9165 "JUMP O7"
9166 %}
9167 ins_encode %{
9168 // Calculate table address into a register.
9169 Register table_reg;
9170 Register label_reg = O7;
9171 if (constant_offset() == 0) {
9172 table_reg = $constanttablebase;
9173 } else {
9174 table_reg = O7;
9175 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9176 __ add($constanttablebase, con_offset, table_reg);
9177 }
9178
9179 // Jump to base address + switch value
9180 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9181 __ jmp(label_reg, G0);
9182 __ delayed()->nop();
9183 %}
9184 ins_pipe(ialu_reg_reg);
9185 %}
9186
9187 // Direct Branch. Use V8 version with longer range.
9188 instruct branch(label labl) %{
9189 match(Goto);
9190 effect(USE labl);
9191
9192 size(8);
9193 ins_cost(BRANCH_COST);
9194 format %{ "BA $labl" %}
9195 ins_encode %{
9196 Label* L = $labl$$label;
9197 __ ba(*L);
9198 __ delayed()->nop();
9199 %}
9200 ins_pipe(br);
9201 %}
9202
9203 // Conditional Direct Branch
9204 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9205 match(If cmp icc);
9206 effect(USE labl);
9207
9208 size(8);
9209 ins_cost(BRANCH_COST);
9210 format %{ "BP$cmp $icc,$labl" %}
9211 // Prim = bits 24-22, Secnd = bits 31-30
9212 ins_encode( enc_bp( labl, cmp, icc ) );
9213 ins_pipe(br_cc);
9214 %}
9215
9216 // Branch-on-register tests all 64 bits. We assume that values
9217 // in 64-bit registers always remains zero or sign extended
9218 // unless our code munges the high bits. Interrupts can chop
9219 // the high order bits to zero or sign at any time.
9220 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9221 match(If cmp (CmpI op1 zero));
9222 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9223 effect(USE labl);
9224
9225 size(8);
9226 ins_cost(BRANCH_COST);
9227 format %{ "BR$cmp $op1,$labl" %}
9228 ins_encode( enc_bpr( labl, cmp, op1 ) );
9229 ins_pipe(br_reg);
9230 %}
9231
9232 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9233 match(If cmp (CmpP op1 null));
9234 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9235 effect(USE labl);
9236
9237 size(8);
9238 ins_cost(BRANCH_COST);
9239 format %{ "BR$cmp $op1,$labl" %}
9240 ins_encode( enc_bpr( labl, cmp, op1 ) );
9241 ins_pipe(br_reg);
9242 %}
9243
9244 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9245 match(If cmp (CmpL op1 zero));
9246 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9247 effect(USE labl);
9248
9249 size(8);
9250 ins_cost(BRANCH_COST);
9251 format %{ "BR$cmp $op1,$labl" %}
9252 ins_encode( enc_bpr( labl, cmp, op1 ) );
9253 ins_pipe(br_reg);
9254 %}
9255
9256 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9257 match(If cmp icc);
9258 effect(USE labl);
9259
9260 format %{ "BP$cmp $icc,$labl" %}
9261 // Prim = bits 24-22, Secnd = bits 31-30
9262 ins_encode( enc_bp( labl, cmp, icc ) );
9263 ins_pipe(br_cc);
9264 %}
9265
9266 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9267 match(If cmp pcc);
9268 effect(USE labl);
9269
9270 size(8);
9271 ins_cost(BRANCH_COST);
9272 format %{ "BP$cmp $pcc,$labl" %}
9273 ins_encode %{
9274 Label* L = $labl$$label;
9275 Assembler::Predict predict_taken =
9276 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9277
9278 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9279 __ delayed()->nop();
9280 %}
9281 ins_pipe(br_cc);
9282 %}
9283
9284 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9285 match(If cmp fcc);
9286 effect(USE labl);
9287
9288 size(8);
9289 ins_cost(BRANCH_COST);
9290 format %{ "FBP$cmp $fcc,$labl" %}
9291 ins_encode %{
9292 Label* L = $labl$$label;
9293 Assembler::Predict predict_taken =
9294 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9295
9296 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9297 __ delayed()->nop();
9298 %}
9299 ins_pipe(br_fcc);
9300 %}
9301
9302 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9303 match(CountedLoopEnd cmp icc);
9304 effect(USE labl);
9305
9306 size(8);
9307 ins_cost(BRANCH_COST);
9308 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9309 // Prim = bits 24-22, Secnd = bits 31-30
9310 ins_encode( enc_bp( labl, cmp, icc ) );
9311 ins_pipe(br_cc);
9312 %}
9313
9314 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9315 match(CountedLoopEnd cmp icc);
9316 effect(USE labl);
9317
9318 size(8);
9319 ins_cost(BRANCH_COST);
9320 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9321 // Prim = bits 24-22, Secnd = bits 31-30
9322 ins_encode( enc_bp( labl, cmp, icc ) );
9323 ins_pipe(br_cc);
9324 %}
9325
9326 // ============================================================================
9327 // Long Compare
9328 //
9329 // Currently we hold longs in 2 registers. Comparing such values efficiently
9330 // is tricky. The flavor of compare used depends on whether we are testing
9331 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9332 // The GE test is the negated LT test. The LE test can be had by commuting
9333 // the operands (yielding a GE test) and then negating; negate again for the
9334 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9335 // NE test is negated from that.
9336
9337 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9338 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9339 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9340 // are collapsed internally in the ADLC's dfa-gen code. The match for
9341 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9342 // foo match ends up with the wrong leaf. One fix is to not match both
9343 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9344 // both forms beat the trinary form of long-compare and both are very useful
9345 // on Intel which has so few registers.
9346
9347 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9348 match(If cmp xcc);
9349 effect(USE labl);
9350
9351 size(8);
9352 ins_cost(BRANCH_COST);
9353 format %{ "BP$cmp $xcc,$labl" %}
9354 ins_encode %{
9355 Label* L = $labl$$label;
9356 Assembler::Predict predict_taken =
9357 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9358
9359 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9360 __ delayed()->nop();
9361 %}
9362 ins_pipe(br_cc);
9363 %}
9364
9365 // Manifest a CmpL3 result in an integer register. Very painful.
9366 // This is the test to avoid.
9367 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9368 match(Set dst (CmpL3 src1 src2) );
9369 effect( KILL ccr );
9370 ins_cost(6*DEFAULT_COST);
9371 size(24);
9372 format %{ "CMP $src1,$src2\t\t! long\n"
9373 "\tBLT,a,pn done\n"
9374 "\tMOV -1,$dst\t! delay slot\n"
9375 "\tBGT,a,pn done\n"
9376 "\tMOV 1,$dst\t! delay slot\n"
9377 "\tCLR $dst\n"
9378 "done:" %}
9379 ins_encode( cmpl_flag(src1,src2,dst) );
9380 ins_pipe(cmpL_reg);
9381 %}
9382
9383 // Conditional move
9384 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9385 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9386 ins_cost(150);
9387 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9388 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9389 ins_pipe(ialu_reg);
9390 %}
9391
9392 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9393 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9394 ins_cost(140);
9395 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9396 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9397 ins_pipe(ialu_imm);
9398 %}
9399
9400 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9401 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9402 ins_cost(150);
9403 format %{ "MOV$cmp $xcc,$src,$dst" %}
9404 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9405 ins_pipe(ialu_reg);
9406 %}
9407
9408 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9409 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9410 ins_cost(140);
9411 format %{ "MOV$cmp $xcc,$src,$dst" %}
9412 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9413 ins_pipe(ialu_imm);
9414 %}
9415
9416 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9417 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9418 ins_cost(150);
9419 format %{ "MOV$cmp $xcc,$src,$dst" %}
9420 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9421 ins_pipe(ialu_reg);
9422 %}
9423
9424 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9425 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9426 ins_cost(150);
9427 format %{ "MOV$cmp $xcc,$src,$dst" %}
9428 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9429 ins_pipe(ialu_reg);
9430 %}
9431
9432 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9433 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9434 ins_cost(140);
9435 format %{ "MOV$cmp $xcc,$src,$dst" %}
9436 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9437 ins_pipe(ialu_imm);
9438 %}
9439
9440 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9441 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9442 ins_cost(150);
9443 opcode(0x101);
9444 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9445 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9446 ins_pipe(int_conditional_float_move);
9447 %}
9448
9449 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9450 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9451 ins_cost(150);
9452 opcode(0x102);
9453 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9454 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9455 ins_pipe(int_conditional_float_move);
9456 %}
9457
9458 // ============================================================================
9459 // Safepoint Instruction
9460 instruct safePoint_poll(iRegP poll) %{
9461 match(SafePoint poll);
9462 effect(USE poll);
9463
9464 size(4);
9465 #ifdef _LP64
9466 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9467 #else
9468 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9469 #endif
9470 ins_encode %{
9471 __ relocate(relocInfo::poll_type);
9472 __ ld_ptr($poll$$Register, 0, G0);
9473 %}
9474 ins_pipe(loadPollP);
9475 %}
9476
9477 // ============================================================================
9478 // Call Instructions
9479 // Call Java Static Instruction
9480 instruct CallStaticJavaDirect( method meth ) %{
9481 match(CallStaticJava);
9482 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9483 effect(USE meth);
9484
9485 size(8);
9486 ins_cost(CALL_COST);
9487 format %{ "CALL,static ; NOP ==> " %}
9488 ins_encode( Java_Static_Call( meth ), call_epilog );
9489 ins_pipe(simple_call);
9490 %}
9491
9492 // Call Java Static Instruction (method handle version)
9493 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9494 match(CallStaticJava);
9495 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9496 effect(USE meth, KILL l7_mh_SP_save);
9497
9498 size(8);
9499 ins_cost(CALL_COST);
9500 format %{ "CALL,static/MethodHandle" %}
9501 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9502 ins_pipe(simple_call);
9503 %}
9504
9505 // Call Java Dynamic Instruction
9506 instruct CallDynamicJavaDirect( method meth ) %{
9507 match(CallDynamicJava);
9508 effect(USE meth);
9509
9510 ins_cost(CALL_COST);
9511 format %{ "SET (empty),R_G5\n\t"
9512 "CALL,dynamic ; NOP ==> " %}
9513 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9514 ins_pipe(call);
9515 %}
9516
9517 // Call Runtime Instruction
9518 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9519 match(CallRuntime);
9520 effect(USE meth, KILL l7);
9521 ins_cost(CALL_COST);
9522 format %{ "CALL,runtime" %}
9523 ins_encode( Java_To_Runtime( meth ),
9524 call_epilog, adjust_long_from_native_call );
9525 ins_pipe(simple_call);
9526 %}
9527
9528 // Call runtime without safepoint - same as CallRuntime
9529 instruct CallLeafDirect(method meth, l7RegP l7) %{
9530 match(CallLeaf);
9531 effect(USE meth, KILL l7);
9532 ins_cost(CALL_COST);
9533 format %{ "CALL,runtime leaf" %}
9534 ins_encode( Java_To_Runtime( meth ),
9535 call_epilog,
9536 adjust_long_from_native_call );
9537 ins_pipe(simple_call);
9538 %}
9539
9540 // Call runtime without safepoint - same as CallLeaf
9541 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9542 match(CallLeafNoFP);
9543 effect(USE meth, KILL l7);
9544 ins_cost(CALL_COST);
9545 format %{ "CALL,runtime leaf nofp" %}
9546 ins_encode( Java_To_Runtime( meth ),
9547 call_epilog,
9548 adjust_long_from_native_call );
9549 ins_pipe(simple_call);
9550 %}
9551
9552 // Tail Call; Jump from runtime stub to Java code.
9553 // Also known as an 'interprocedural jump'.
9554 // Target of jump will eventually return to caller.
9555 // TailJump below removes the return address.
9556 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9557 match(TailCall jump_target method_oop );
9558
9559 ins_cost(CALL_COST);
9560 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9561 ins_encode(form_jmpl(jump_target));
9562 ins_pipe(tail_call);
9563 %}
9564
9565
9566 // Return Instruction
9567 instruct Ret() %{
9568 match(Return);
9569
9570 // The epilogue node did the ret already.
9571 size(0);
9572 format %{ "! return" %}
9573 ins_encode();
9574 ins_pipe(empty);
9575 %}
9576
9577
9578 // Tail Jump; remove the return address; jump to target.
9579 // TailCall above leaves the return address around.
9580 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9581 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9582 // "restore" before this instruction (in Epilogue), we need to materialize it
9583 // in %i0.
9584 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9585 match( TailJump jump_target ex_oop );
9586 ins_cost(CALL_COST);
9587 format %{ "! discard R_O7\n\t"
9588 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9589 ins_encode(form_jmpl_set_exception_pc(jump_target));
9590 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9591 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9592 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9593 ins_pipe(tail_call);
9594 %}
9595
9596 // Create exception oop: created by stack-crawling runtime code.
9597 // Created exception is now available to this handler, and is setup
9598 // just prior to jumping to this handler. No code emitted.
9599 instruct CreateException( o0RegP ex_oop )
9600 %{
9601 match(Set ex_oop (CreateEx));
9602 ins_cost(0);
9603
9604 size(0);
9605 // use the following format syntax
9606 format %{ "! exception oop is in R_O0; no code emitted" %}
9607 ins_encode();
9608 ins_pipe(empty);
9609 %}
9610
9611
9612 // Rethrow exception:
9613 // The exception oop will come in the first argument position.
9614 // Then JUMP (not call) to the rethrow stub code.
9615 instruct RethrowException()
9616 %{
9617 match(Rethrow);
9618 ins_cost(CALL_COST);
9619
9620 // use the following format syntax
9621 format %{ "Jmp rethrow_stub" %}
9622 ins_encode(enc_rethrow);
9623 ins_pipe(tail_call);
9624 %}
9625
9626
9627 // Die now
9628 instruct ShouldNotReachHere( )
9629 %{
9630 match(Halt);
9631 ins_cost(CALL_COST);
9632
9633 size(4);
9634 // Use the following format syntax
9635 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9636 ins_encode( form2_illtrap() );
9637 ins_pipe(tail_call);
9638 %}
9639
9640 // ============================================================================
9641 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9642 // array for an instance of the superklass. Set a hidden internal cache on a
9643 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9644 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9645 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9646 match(Set index (PartialSubtypeCheck sub super));
9647 effect( KILL pcc, KILL o7 );
9648 ins_cost(DEFAULT_COST*10);
9649 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9650 ins_encode( enc_PartialSubtypeCheck() );
9651 ins_pipe(partial_subtype_check_pipe);
9652 %}
9653
9654 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9655 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9656 effect( KILL idx, KILL o7 );
9657 ins_cost(DEFAULT_COST*10);
9658 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9659 ins_encode( enc_PartialSubtypeCheck() );
9660 ins_pipe(partial_subtype_check_pipe);
9661 %}
9662
9663
9664 // ============================================================================
9665 // inlined locking and unlocking
9666
9667 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9668 match(Set pcc (FastLock object box));
9669
9670 effect(KILL scratch, TEMP scratch2);
9671 ins_cost(100);
9672
9673 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9674 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9675 ins_pipe(long_memory_op);
9676 %}
9677
9678
9679 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9680 match(Set pcc (FastUnlock object box));
9681 effect(KILL scratch, TEMP scratch2);
9682 ins_cost(100);
9683
9684 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9685 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9686 ins_pipe(long_memory_op);
9687 %}
9688
9689 // Count and Base registers are fixed because the allocator cannot
9690 // kill unknown registers. The encodings are generic.
9691 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9692 match(Set dummy (ClearArray cnt base));
9693 effect(TEMP temp, KILL ccr);
9694 ins_cost(300);
9695 format %{ "MOV $cnt,$temp\n"
9696 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9697 " BRge loop\t\t! Clearing loop\n"
9698 " STX G0,[$base+$temp]\t! delay slot" %}
9699 ins_encode( enc_Clear_Array(cnt, base, temp) );
9700 ins_pipe(long_memory_op);
9701 %}
9702
9703 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9704 o7RegI tmp, flagsReg ccr) %{
9705 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9706 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9707 ins_cost(300);
9708 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9709 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
9710 ins_pipe(long_memory_op);
9711 %}
9712
9713 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9714 o7RegI tmp, flagsReg ccr) %{
9715 match(Set result (StrEquals (Binary str1 str2) cnt));
9716 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9717 ins_cost(300);
9718 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
9719 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
9720 ins_pipe(long_memory_op);
9721 %}
9722
9723 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9724 o7RegI tmp2, flagsReg ccr) %{
9725 match(Set result (AryEq ary1 ary2));
9726 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9727 ins_cost(300);
9728 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9729 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9730 ins_pipe(long_memory_op);
9731 %}
9732
9733
9734 //---------- Zeros Count Instructions ------------------------------------------
9735
9736 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9737 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9738 match(Set dst (CountLeadingZerosI src));
9739 effect(TEMP dst, TEMP tmp, KILL cr);
9740
9741 // x |= (x >> 1);
9742 // x |= (x >> 2);
9743 // x |= (x >> 4);
9744 // x |= (x >> 8);
9745 // x |= (x >> 16);
9746 // return (WORDBITS - popc(x));
9747 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
9748 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
9749 "OR $dst,$tmp,$dst\n\t"
9750 "SRL $dst,2,$tmp\n\t"
9751 "OR $dst,$tmp,$dst\n\t"
9752 "SRL $dst,4,$tmp\n\t"
9753 "OR $dst,$tmp,$dst\n\t"
9754 "SRL $dst,8,$tmp\n\t"
9755 "OR $dst,$tmp,$dst\n\t"
9756 "SRL $dst,16,$tmp\n\t"
9757 "OR $dst,$tmp,$dst\n\t"
9758 "POPC $dst,$dst\n\t"
9759 "MOV 32,$tmp\n\t"
9760 "SUB $tmp,$dst,$dst" %}
9761 ins_encode %{
9762 Register Rdst = $dst$$Register;
9763 Register Rsrc = $src$$Register;
9764 Register Rtmp = $tmp$$Register;
9765 __ srl(Rsrc, 1, Rtmp);
9766 __ srl(Rsrc, 0, Rdst);
9767 __ or3(Rdst, Rtmp, Rdst);
9768 __ srl(Rdst, 2, Rtmp);
9769 __ or3(Rdst, Rtmp, Rdst);
9770 __ srl(Rdst, 4, Rtmp);
9771 __ or3(Rdst, Rtmp, Rdst);
9772 __ srl(Rdst, 8, Rtmp);
9773 __ or3(Rdst, Rtmp, Rdst);
9774 __ srl(Rdst, 16, Rtmp);
9775 __ or3(Rdst, Rtmp, Rdst);
9776 __ popc(Rdst, Rdst);
9777 __ mov(BitsPerInt, Rtmp);
9778 __ sub(Rtmp, Rdst, Rdst);
9779 %}
9780 ins_pipe(ialu_reg);
9781 %}
9782
9783 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
9784 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9785 match(Set dst (CountLeadingZerosL src));
9786 effect(TEMP dst, TEMP tmp, KILL cr);
9787
9788 // x |= (x >> 1);
9789 // x |= (x >> 2);
9790 // x |= (x >> 4);
9791 // x |= (x >> 8);
9792 // x |= (x >> 16);
9793 // x |= (x >> 32);
9794 // return (WORDBITS - popc(x));
9795 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
9796 "OR $src,$tmp,$dst\n\t"
9797 "SRLX $dst,2,$tmp\n\t"
9798 "OR $dst,$tmp,$dst\n\t"
9799 "SRLX $dst,4,$tmp\n\t"
9800 "OR $dst,$tmp,$dst\n\t"
9801 "SRLX $dst,8,$tmp\n\t"
9802 "OR $dst,$tmp,$dst\n\t"
9803 "SRLX $dst,16,$tmp\n\t"
9804 "OR $dst,$tmp,$dst\n\t"
9805 "SRLX $dst,32,$tmp\n\t"
9806 "OR $dst,$tmp,$dst\n\t"
9807 "POPC $dst,$dst\n\t"
9808 "MOV 64,$tmp\n\t"
9809 "SUB $tmp,$dst,$dst" %}
9810 ins_encode %{
9811 Register Rdst = $dst$$Register;
9812 Register Rsrc = $src$$Register;
9813 Register Rtmp = $tmp$$Register;
9814 __ srlx(Rsrc, 1, Rtmp);
9815 __ or3( Rsrc, Rtmp, Rdst);
9816 __ srlx(Rdst, 2, Rtmp);
9817 __ or3( Rdst, Rtmp, Rdst);
9818 __ srlx(Rdst, 4, Rtmp);
9819 __ or3( Rdst, Rtmp, Rdst);
9820 __ srlx(Rdst, 8, Rtmp);
9821 __ or3( Rdst, Rtmp, Rdst);
9822 __ srlx(Rdst, 16, Rtmp);
9823 __ or3( Rdst, Rtmp, Rdst);
9824 __ srlx(Rdst, 32, Rtmp);
9825 __ or3( Rdst, Rtmp, Rdst);
9826 __ popc(Rdst, Rdst);
9827 __ mov(BitsPerLong, Rtmp);
9828 __ sub(Rtmp, Rdst, Rdst);
9829 %}
9830 ins_pipe(ialu_reg);
9831 %}
9832
9833 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9834 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9835 match(Set dst (CountTrailingZerosI src));
9836 effect(TEMP dst, KILL cr);
9837
9838 // return popc(~x & (x - 1));
9839 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
9840 "ANDN $dst,$src,$dst\n\t"
9841 "SRL $dst,R_G0,$dst\n\t"
9842 "POPC $dst,$dst" %}
9843 ins_encode %{
9844 Register Rdst = $dst$$Register;
9845 Register Rsrc = $src$$Register;
9846 __ sub(Rsrc, 1, Rdst);
9847 __ andn(Rdst, Rsrc, Rdst);
9848 __ srl(Rdst, G0, Rdst);
9849 __ popc(Rdst, Rdst);
9850 %}
9851 ins_pipe(ialu_reg);
9852 %}
9853
9854 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9855 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9856 match(Set dst (CountTrailingZerosL src));
9857 effect(TEMP dst, KILL cr);
9858
9859 // return popc(~x & (x - 1));
9860 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
9861 "ANDN $dst,$src,$dst\n\t"
9862 "POPC $dst,$dst" %}
9863 ins_encode %{
9864 Register Rdst = $dst$$Register;
9865 Register Rsrc = $src$$Register;
9866 __ sub(Rsrc, 1, Rdst);
9867 __ andn(Rdst, Rsrc, Rdst);
9868 __ popc(Rdst, Rdst);
9869 %}
9870 ins_pipe(ialu_reg);
9871 %}
9872
9873
9874 //---------- Population Count Instructions -------------------------------------
9875
9876 instruct popCountI(iRegI dst, iRegI src) %{
9877 predicate(UsePopCountInstruction);
9878 match(Set dst (PopCountI src));
9879
9880 format %{ "POPC $src, $dst" %}
9881 ins_encode %{
9882 __ popc($src$$Register, $dst$$Register);
9883 %}
9884 ins_pipe(ialu_reg);
9885 %}
9886
9887 // Note: Long.bitCount(long) returns an int.
9888 instruct popCountL(iRegI dst, iRegL src) %{
9889 predicate(UsePopCountInstruction);
9890 match(Set dst (PopCountL src));
9891
9892 format %{ "POPC $src, $dst" %}
9893 ins_encode %{
9894 __ popc($src$$Register, $dst$$Register);
9895 %}
9896 ins_pipe(ialu_reg);
9897 %}
9898
9899
9900 // ============================================================================
9901 //------------Bytes reverse--------------------------------------------------
9902
9903 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9904 match(Set dst (ReverseBytesI src));
9905
9906 // Op cost is artificially doubled to make sure that load or store
9907 // instructions are preferred over this one which requires a spill
9908 // onto a stack slot.
9909 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9910 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9911
9912 ins_encode %{
9913 __ set($src$$disp + STACK_BIAS, O7);
9914 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9915 %}
9916 ins_pipe( iload_mem );
9917 %}
9918
9919 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9920 match(Set dst (ReverseBytesL src));
9921
9922 // Op cost is artificially doubled to make sure that load or store
9923 // instructions are preferred over this one which requires a spill
9924 // onto a stack slot.
9925 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9926 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9927
9928 ins_encode %{
9929 __ set($src$$disp + STACK_BIAS, O7);
9930 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9931 %}
9932 ins_pipe( iload_mem );
9933 %}
9934
9935 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
9936 match(Set dst (ReverseBytesUS src));
9937
9938 // Op cost is artificially doubled to make sure that load or store
9939 // instructions are preferred over this one which requires a spill
9940 // onto a stack slot.
9941 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9942 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
9943
9944 ins_encode %{
9945 // the value was spilled as an int so bias the load
9946 __ set($src$$disp + STACK_BIAS + 2, O7);
9947 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9948 %}
9949 ins_pipe( iload_mem );
9950 %}
9951
9952 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
9953 match(Set dst (ReverseBytesS src));
9954
9955 // Op cost is artificially doubled to make sure that load or store
9956 // instructions are preferred over this one which requires a spill
9957 // onto a stack slot.
9958 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9959 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
9960
9961 ins_encode %{
9962 // the value was spilled as an int so bias the load
9963 __ set($src$$disp + STACK_BIAS + 2, O7);
9964 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9965 %}
9966 ins_pipe( iload_mem );
9967 %}
9968
9969 // Load Integer reversed byte order
9970 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
9971 match(Set dst (ReverseBytesI (LoadI src)));
9972
9973 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9974 size(4);
9975 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9976
9977 ins_encode %{
9978 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9979 %}
9980 ins_pipe(iload_mem);
9981 %}
9982
9983 // Load Long - aligned and reversed
9984 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
9985 match(Set dst (ReverseBytesL (LoadL src)));
9986
9987 ins_cost(MEMORY_REF_COST);
9988 size(4);
9989 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9990
9991 ins_encode %{
9992 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9993 %}
9994 ins_pipe(iload_mem);
9995 %}
9996
9997 // Load unsigned short / char reversed byte order
9998 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
9999 match(Set dst (ReverseBytesUS (LoadUS src)));
10000
10001 ins_cost(MEMORY_REF_COST);
10002 size(4);
10003 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10004
10005 ins_encode %{
10006 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10007 %}
10008 ins_pipe(iload_mem);
10009 %}
10010
10011 // Load short reversed byte order
10012 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10013 match(Set dst (ReverseBytesS (LoadS src)));
10014
10015 ins_cost(MEMORY_REF_COST);
10016 size(4);
10017 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10018
10019 ins_encode %{
10020 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10021 %}
10022 ins_pipe(iload_mem);
10023 %}
10024
10025 // Store Integer reversed byte order
10026 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10027 match(Set dst (StoreI dst (ReverseBytesI src)));
10028
10029 ins_cost(MEMORY_REF_COST);
10030 size(4);
10031 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10032
10033 ins_encode %{
10034 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10035 %}
10036 ins_pipe(istore_mem_reg);
10037 %}
10038
10039 // Store Long reversed byte order
10040 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10041 match(Set dst (StoreL dst (ReverseBytesL src)));
10042
10043 ins_cost(MEMORY_REF_COST);
10044 size(4);
10045 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10046
10047 ins_encode %{
10048 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10049 %}
10050 ins_pipe(istore_mem_reg);
10051 %}
10052
10053 // Store unsighed short/char reversed byte order
10054 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10055 match(Set dst (StoreC dst (ReverseBytesUS src)));
10056
10057 ins_cost(MEMORY_REF_COST);
10058 size(4);
10059 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10060
10061 ins_encode %{
10062 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10063 %}
10064 ins_pipe(istore_mem_reg);
10065 %}
10066
10067 // Store short reversed byte order
10068 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10069 match(Set dst (StoreC dst (ReverseBytesS src)));
10070
10071 ins_cost(MEMORY_REF_COST);
10072 size(4);
10073 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10074
10075 ins_encode %{
10076 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10077 %}
10078 ins_pipe(istore_mem_reg);
10079 %}
10080
10081 //----------PEEPHOLE RULES-----------------------------------------------------
10082 // These must follow all instruction definitions as they use the names
10083 // defined in the instructions definitions.
10084 //
10085 // peepmatch ( root_instr_name [preceding_instruction]* );
10086 //
10087 // peepconstraint %{
10088 // (instruction_number.operand_name relational_op instruction_number.operand_name
10089 // [, ...] );
10090 // // instruction numbers are zero-based using left to right order in peepmatch
10091 //
10092 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10093 // // provide an instruction_number.operand_name for each operand that appears
10094 // // in the replacement instruction's match rule
10095 //
10096 // ---------VM FLAGS---------------------------------------------------------
10097 //
10098 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10099 //
10100 // Each peephole rule is given an identifying number starting with zero and
10101 // increasing by one in the order seen by the parser. An individual peephole
10102 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10103 // on the command-line.
10104 //
10105 // ---------CURRENT LIMITATIONS----------------------------------------------
10106 //
10107 // Only match adjacent instructions in same basic block
10108 // Only equality constraints
10109 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10110 // Only one replacement instruction
10111 //
10112 // ---------EXAMPLE----------------------------------------------------------
10113 //
10114 // // pertinent parts of existing instructions in architecture description
10115 // instruct movI(eRegI dst, eRegI src) %{
10116 // match(Set dst (CopyI src));
10117 // %}
10118 //
10119 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10120 // match(Set dst (AddI dst src));
10121 // effect(KILL cr);
10122 // %}
10123 //
10124 // // Change (inc mov) to lea
10125 // peephole %{
10126 // // increment preceeded by register-register move
10127 // peepmatch ( incI_eReg movI );
10128 // // require that the destination register of the increment
10129 // // match the destination register of the move
10130 // peepconstraint ( 0.dst == 1.dst );
10131 // // construct a replacement instruction that sets
10132 // // the destination to ( move's source register + one )
10133 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10134 // %}
10135 //
10136
10137 // // Change load of spilled value to only a spill
10138 // instruct storeI(memory mem, eRegI src) %{
10139 // match(Set mem (StoreI mem src));
10140 // %}
10141 //
10142 // instruct loadI(eRegI dst, memory mem) %{
10143 // match(Set dst (LoadI mem));
10144 // %}
10145 //
10146 // peephole %{
10147 // peepmatch ( loadI storeI );
10148 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10149 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10150 // %}
10151
10152 //----------SMARTSPILL RULES---------------------------------------------------
10153 // These must follow all instruction definitions as they use the names
10154 // defined in the instructions definitions.
10155 //
10156 // SPARC will probably not have any of these rules due to RISC instruction set.
10157
10158 //----------PIPELINE-----------------------------------------------------------
10159 // Rules which define the behavior of the target architectures pipeline.