3298 #else // !_LP64
3299 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3300 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3301 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3302 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3303 #endif
3304 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3305 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3306 %}
3307
3308 %}
3309
3310
3311 //----------ATTRIBUTES---------------------------------------------------------
3312 //----------Operand Attributes-------------------------------------------------
3313 op_attrib op_cost(1); // Required cost attribute
3314
3315 //----------Instruction Attributes---------------------------------------------
3316 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3317 ins_attrib ins_size(32); // Required size attribute (in bits)
3318 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3319 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3320 // non-matching short branch variant of some
3321 // long branch?
3322
3323 //----------OPERANDS-----------------------------------------------------------
3324 // Operand definitions must precede instruction definitions for correct parsing
3325 // in the ADLC because operands constitute user defined types which are used in
3326 // instruction definitions.
3327
3328 //----------Simple Operands----------------------------------------------------
3329 // Immediate Operands
3330 // Integer Immediate: 32-bit
3331 operand immI() %{
3332 match(ConI);
3333
3334 op_cost(0);
3335 // formats are generated automatically for constants and base registers
3336 format %{ %}
3337 interface(CONST_INTER);
3338 %}
9165 "LD [O7 + $switch_val], O7\n\t"
9166 "JUMP O7"
9167 %}
9168 ins_encode %{
9169 // Calculate table address into a register.
9170 Register table_reg;
9171 Register label_reg = O7;
9172 if (constant_offset() == 0) {
9173 table_reg = $constanttablebase;
9174 } else {
9175 table_reg = O7;
9176 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9177 __ add($constanttablebase, con_offset, table_reg);
9178 }
9179
9180 // Jump to base address + switch value
9181 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9182 __ jmp(label_reg, G0);
9183 __ delayed()->nop();
9184 %}
9185 ins_pc_relative(1);
9186 ins_pipe(ialu_reg_reg);
9187 %}
9188
9189 // Direct Branch. Use V8 version with longer range.
9190 instruct branch(label labl) %{
9191 match(Goto);
9192 effect(USE labl);
9193
9194 size(8);
9195 ins_cost(BRANCH_COST);
9196 format %{ "BA $labl" %}
9197 ins_encode %{
9198 Label* L = $labl$$label;
9199 __ ba(*L);
9200 __ delayed()->nop();
9201 %}
9202 ins_pc_relative(1);
9203 ins_pipe(br);
9204 %}
9205
9206 // Conditional Direct Branch
9207 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9208 match(If cmp icc);
9209 effect(USE labl);
9210
9211 size(8);
9212 ins_cost(BRANCH_COST);
9213 format %{ "BP$cmp $icc,$labl" %}
9214 // Prim = bits 24-22, Secnd = bits 31-30
9215 ins_encode( enc_bp( labl, cmp, icc ) );
9216 ins_pc_relative(1);
9217 ins_pipe(br_cc);
9218 %}
9219
9220 // Branch-on-register tests all 64 bits. We assume that values
9221 // in 64-bit registers always remains zero or sign extended
9222 // unless our code munges the high bits. Interrupts can chop
9223 // the high order bits to zero or sign at any time.
9224 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9225 match(If cmp (CmpI op1 zero));
9226 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9227 effect(USE labl);
9228
9229 size(8);
9230 ins_cost(BRANCH_COST);
9231 format %{ "BR$cmp $op1,$labl" %}
9232 ins_encode( enc_bpr( labl, cmp, op1 ) );
9233 ins_pc_relative(1);
9234 ins_pipe(br_reg);
9235 %}
9236
9237 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9238 match(If cmp (CmpP op1 null));
9239 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9240 effect(USE labl);
9241
9242 size(8);
9243 ins_cost(BRANCH_COST);
9244 format %{ "BR$cmp $op1,$labl" %}
9245 ins_encode( enc_bpr( labl, cmp, op1 ) );
9246 ins_pc_relative(1);
9247 ins_pipe(br_reg);
9248 %}
9249
9250 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9251 match(If cmp (CmpL op1 zero));
9252 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9253 effect(USE labl);
9254
9255 size(8);
9256 ins_cost(BRANCH_COST);
9257 format %{ "BR$cmp $op1,$labl" %}
9258 ins_encode( enc_bpr( labl, cmp, op1 ) );
9259 ins_pc_relative(1);
9260 ins_pipe(br_reg);
9261 %}
9262
9263 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9264 match(If cmp icc);
9265 effect(USE labl);
9266
9267 format %{ "BP$cmp $icc,$labl" %}
9268 // Prim = bits 24-22, Secnd = bits 31-30
9269 ins_encode( enc_bp( labl, cmp, icc ) );
9270 ins_pc_relative(1);
9271 ins_pipe(br_cc);
9272 %}
9273
9274 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9275 match(If cmp pcc);
9276 effect(USE labl);
9277
9278 size(8);
9279 ins_cost(BRANCH_COST);
9280 format %{ "BP$cmp $pcc,$labl" %}
9281 ins_encode %{
9282 Label* L = $labl$$label;
9283 Assembler::Predict predict_taken =
9284 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9285
9286 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9287 __ delayed()->nop();
9288 %}
9289 ins_pc_relative(1);
9290 ins_pipe(br_cc);
9291 %}
9292
9293 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9294 match(If cmp fcc);
9295 effect(USE labl);
9296
9297 size(8);
9298 ins_cost(BRANCH_COST);
9299 format %{ "FBP$cmp $fcc,$labl" %}
9300 ins_encode %{
9301 Label* L = $labl$$label;
9302 Assembler::Predict predict_taken =
9303 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9304
9305 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9306 __ delayed()->nop();
9307 %}
9308 ins_pc_relative(1);
9309 ins_pipe(br_fcc);
9310 %}
9311
9312 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9313 match(CountedLoopEnd cmp icc);
9314 effect(USE labl);
9315
9316 size(8);
9317 ins_cost(BRANCH_COST);
9318 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9319 // Prim = bits 24-22, Secnd = bits 31-30
9320 ins_encode( enc_bp( labl, cmp, icc ) );
9321 ins_pc_relative(1);
9322 ins_pipe(br_cc);
9323 %}
9324
9325 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9326 match(CountedLoopEnd cmp icc);
9327 effect(USE labl);
9328
9329 size(8);
9330 ins_cost(BRANCH_COST);
9331 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9332 // Prim = bits 24-22, Secnd = bits 31-30
9333 ins_encode( enc_bp( labl, cmp, icc ) );
9334 ins_pc_relative(1);
9335 ins_pipe(br_cc);
9336 %}
9337
9338 // ============================================================================
9339 // Long Compare
9340 //
9341 // Currently we hold longs in 2 registers. Comparing such values efficiently
9342 // is tricky. The flavor of compare used depends on whether we are testing
9343 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9344 // The GE test is the negated LT test. The LE test can be had by commuting
9345 // the operands (yielding a GE test) and then negating; negate again for the
9346 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9347 // NE test is negated from that.
9348
9349 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9350 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9351 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9352 // are collapsed internally in the ADLC's dfa-gen code. The match for
9353 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9354 // foo match ends up with the wrong leaf. One fix is to not match both
9355 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9356 // both forms beat the trinary form of long-compare and both are very useful
9357 // on Intel which has so few registers.
9358
9359 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9360 match(If cmp xcc);
9361 effect(USE labl);
9362
9363 size(8);
9364 ins_cost(BRANCH_COST);
9365 format %{ "BP$cmp $xcc,$labl" %}
9366 ins_encode %{
9367 Label* L = $labl$$label;
9368 Assembler::Predict predict_taken =
9369 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9370
9371 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9372 __ delayed()->nop();
9373 %}
9374 ins_pc_relative(1);
9375 ins_pipe(br_cc);
9376 %}
9377
9378 // Manifest a CmpL3 result in an integer register. Very painful.
9379 // This is the test to avoid.
9380 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9381 match(Set dst (CmpL3 src1 src2) );
9382 effect( KILL ccr );
9383 ins_cost(6*DEFAULT_COST);
9384 size(24);
9385 format %{ "CMP $src1,$src2\t\t! long\n"
9386 "\tBLT,a,pn done\n"
9387 "\tMOV -1,$dst\t! delay slot\n"
9388 "\tBGT,a,pn done\n"
9389 "\tMOV 1,$dst\t! delay slot\n"
9390 "\tCLR $dst\n"
9391 "done:" %}
9392 ins_encode( cmpl_flag(src1,src2,dst) );
9393 ins_pipe(cmpL_reg);
9394 %}
9482 #endif
9483 ins_encode %{
9484 __ relocate(relocInfo::poll_type);
9485 __ ld_ptr($poll$$Register, 0, G0);
9486 %}
9487 ins_pipe(loadPollP);
9488 %}
9489
9490 // ============================================================================
9491 // Call Instructions
9492 // Call Java Static Instruction
9493 instruct CallStaticJavaDirect( method meth ) %{
9494 match(CallStaticJava);
9495 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9496 effect(USE meth);
9497
9498 size(8);
9499 ins_cost(CALL_COST);
9500 format %{ "CALL,static ; NOP ==> " %}
9501 ins_encode( Java_Static_Call( meth ), call_epilog );
9502 ins_pc_relative(1);
9503 ins_pipe(simple_call);
9504 %}
9505
9506 // Call Java Static Instruction (method handle version)
9507 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9508 match(CallStaticJava);
9509 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9510 effect(USE meth, KILL l7_mh_SP_save);
9511
9512 size(8);
9513 ins_cost(CALL_COST);
9514 format %{ "CALL,static/MethodHandle" %}
9515 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9516 ins_pc_relative(1);
9517 ins_pipe(simple_call);
9518 %}
9519
9520 // Call Java Dynamic Instruction
9521 instruct CallDynamicJavaDirect( method meth ) %{
9522 match(CallDynamicJava);
9523 effect(USE meth);
9524
9525 ins_cost(CALL_COST);
9526 format %{ "SET (empty),R_G5\n\t"
9527 "CALL,dynamic ; NOP ==> " %}
9528 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9529 ins_pc_relative(1);
9530 ins_pipe(call);
9531 %}
9532
9533 // Call Runtime Instruction
9534 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9535 match(CallRuntime);
9536 effect(USE meth, KILL l7);
9537 ins_cost(CALL_COST);
9538 format %{ "CALL,runtime" %}
9539 ins_encode( Java_To_Runtime( meth ),
9540 call_epilog, adjust_long_from_native_call );
9541 ins_pc_relative(1);
9542 ins_pipe(simple_call);
9543 %}
9544
9545 // Call runtime without safepoint - same as CallRuntime
9546 instruct CallLeafDirect(method meth, l7RegP l7) %{
9547 match(CallLeaf);
9548 effect(USE meth, KILL l7);
9549 ins_cost(CALL_COST);
9550 format %{ "CALL,runtime leaf" %}
9551 ins_encode( Java_To_Runtime( meth ),
9552 call_epilog,
9553 adjust_long_from_native_call );
9554 ins_pc_relative(1);
9555 ins_pipe(simple_call);
9556 %}
9557
9558 // Call runtime without safepoint - same as CallLeaf
9559 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9560 match(CallLeafNoFP);
9561 effect(USE meth, KILL l7);
9562 ins_cost(CALL_COST);
9563 format %{ "CALL,runtime leaf nofp" %}
9564 ins_encode( Java_To_Runtime( meth ),
9565 call_epilog,
9566 adjust_long_from_native_call );
9567 ins_pc_relative(1);
9568 ins_pipe(simple_call);
9569 %}
9570
9571 // Tail Call; Jump from runtime stub to Java code.
9572 // Also known as an 'interprocedural jump'.
9573 // Target of jump will eventually return to caller.
9574 // TailJump below removes the return address.
9575 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9576 match(TailCall jump_target method_oop );
9577
9578 ins_cost(CALL_COST);
9579 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9580 ins_encode(form_jmpl(jump_target));
9581 ins_pipe(tail_call);
9582 %}
9583
9584
9585 // Return Instruction
9586 instruct Ret() %{
9587 match(Return);
|
3298 #else // !_LP64
3299 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3300 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3301 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3302 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3303 #endif
3304 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3305 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3306 %}
3307
3308 %}
3309
3310
3311 //----------ATTRIBUTES---------------------------------------------------------
3312 //----------Operand Attributes-------------------------------------------------
3313 op_attrib op_cost(1); // Required cost attribute
3314
3315 //----------Instruction Attributes---------------------------------------------
3316 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3317 ins_attrib ins_size(32); // Required size attribute (in bits)
3318 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3319 // non-matching short branch variant of some
3320 // long branch?
3321
3322 //----------OPERANDS-----------------------------------------------------------
3323 // Operand definitions must precede instruction definitions for correct parsing
3324 // in the ADLC because operands constitute user defined types which are used in
3325 // instruction definitions.
3326
3327 //----------Simple Operands----------------------------------------------------
3328 // Immediate Operands
3329 // Integer Immediate: 32-bit
3330 operand immI() %{
3331 match(ConI);
3332
3333 op_cost(0);
3334 // formats are generated automatically for constants and base registers
3335 format %{ %}
3336 interface(CONST_INTER);
3337 %}
9164 "LD [O7 + $switch_val], O7\n\t"
9165 "JUMP O7"
9166 %}
9167 ins_encode %{
9168 // Calculate table address into a register.
9169 Register table_reg;
9170 Register label_reg = O7;
9171 if (constant_offset() == 0) {
9172 table_reg = $constanttablebase;
9173 } else {
9174 table_reg = O7;
9175 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9176 __ add($constanttablebase, con_offset, table_reg);
9177 }
9178
9179 // Jump to base address + switch value
9180 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9181 __ jmp(label_reg, G0);
9182 __ delayed()->nop();
9183 %}
9184 ins_pipe(ialu_reg_reg);
9185 %}
9186
9187 // Direct Branch. Use V8 version with longer range.
9188 instruct branch(label labl) %{
9189 match(Goto);
9190 effect(USE labl);
9191
9192 size(8);
9193 ins_cost(BRANCH_COST);
9194 format %{ "BA $labl" %}
9195 ins_encode %{
9196 Label* L = $labl$$label;
9197 __ ba(*L);
9198 __ delayed()->nop();
9199 %}
9200 ins_pipe(br);
9201 %}
9202
9203 // Conditional Direct Branch
9204 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9205 match(If cmp icc);
9206 effect(USE labl);
9207
9208 size(8);
9209 ins_cost(BRANCH_COST);
9210 format %{ "BP$cmp $icc,$labl" %}
9211 // Prim = bits 24-22, Secnd = bits 31-30
9212 ins_encode( enc_bp( labl, cmp, icc ) );
9213 ins_pipe(br_cc);
9214 %}
9215
9216 // Branch-on-register tests all 64 bits. We assume that values
9217 // in 64-bit registers always remains zero or sign extended
9218 // unless our code munges the high bits. Interrupts can chop
9219 // the high order bits to zero or sign at any time.
9220 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9221 match(If cmp (CmpI op1 zero));
9222 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9223 effect(USE labl);
9224
9225 size(8);
9226 ins_cost(BRANCH_COST);
9227 format %{ "BR$cmp $op1,$labl" %}
9228 ins_encode( enc_bpr( labl, cmp, op1 ) );
9229 ins_pipe(br_reg);
9230 %}
9231
9232 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9233 match(If cmp (CmpP op1 null));
9234 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9235 effect(USE labl);
9236
9237 size(8);
9238 ins_cost(BRANCH_COST);
9239 format %{ "BR$cmp $op1,$labl" %}
9240 ins_encode( enc_bpr( labl, cmp, op1 ) );
9241 ins_pipe(br_reg);
9242 %}
9243
9244 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9245 match(If cmp (CmpL op1 zero));
9246 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9247 effect(USE labl);
9248
9249 size(8);
9250 ins_cost(BRANCH_COST);
9251 format %{ "BR$cmp $op1,$labl" %}
9252 ins_encode( enc_bpr( labl, cmp, op1 ) );
9253 ins_pipe(br_reg);
9254 %}
9255
9256 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9257 match(If cmp icc);
9258 effect(USE labl);
9259
9260 format %{ "BP$cmp $icc,$labl" %}
9261 // Prim = bits 24-22, Secnd = bits 31-30
9262 ins_encode( enc_bp( labl, cmp, icc ) );
9263 ins_pipe(br_cc);
9264 %}
9265
9266 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9267 match(If cmp pcc);
9268 effect(USE labl);
9269
9270 size(8);
9271 ins_cost(BRANCH_COST);
9272 format %{ "BP$cmp $pcc,$labl" %}
9273 ins_encode %{
9274 Label* L = $labl$$label;
9275 Assembler::Predict predict_taken =
9276 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9277
9278 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9279 __ delayed()->nop();
9280 %}
9281 ins_pipe(br_cc);
9282 %}
9283
9284 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9285 match(If cmp fcc);
9286 effect(USE labl);
9287
9288 size(8);
9289 ins_cost(BRANCH_COST);
9290 format %{ "FBP$cmp $fcc,$labl" %}
9291 ins_encode %{
9292 Label* L = $labl$$label;
9293 Assembler::Predict predict_taken =
9294 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9295
9296 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9297 __ delayed()->nop();
9298 %}
9299 ins_pipe(br_fcc);
9300 %}
9301
9302 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9303 match(CountedLoopEnd cmp icc);
9304 effect(USE labl);
9305
9306 size(8);
9307 ins_cost(BRANCH_COST);
9308 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9309 // Prim = bits 24-22, Secnd = bits 31-30
9310 ins_encode( enc_bp( labl, cmp, icc ) );
9311 ins_pipe(br_cc);
9312 %}
9313
9314 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9315 match(CountedLoopEnd cmp icc);
9316 effect(USE labl);
9317
9318 size(8);
9319 ins_cost(BRANCH_COST);
9320 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9321 // Prim = bits 24-22, Secnd = bits 31-30
9322 ins_encode( enc_bp( labl, cmp, icc ) );
9323 ins_pipe(br_cc);
9324 %}
9325
9326 // ============================================================================
9327 // Long Compare
9328 //
9329 // Currently we hold longs in 2 registers. Comparing such values efficiently
9330 // is tricky. The flavor of compare used depends on whether we are testing
9331 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9332 // The GE test is the negated LT test. The LE test can be had by commuting
9333 // the operands (yielding a GE test) and then negating; negate again for the
9334 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9335 // NE test is negated from that.
9336
9337 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9338 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9339 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9340 // are collapsed internally in the ADLC's dfa-gen code. The match for
9341 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9342 // foo match ends up with the wrong leaf. One fix is to not match both
9343 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9344 // both forms beat the trinary form of long-compare and both are very useful
9345 // on Intel which has so few registers.
9346
9347 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9348 match(If cmp xcc);
9349 effect(USE labl);
9350
9351 size(8);
9352 ins_cost(BRANCH_COST);
9353 format %{ "BP$cmp $xcc,$labl" %}
9354 ins_encode %{
9355 Label* L = $labl$$label;
9356 Assembler::Predict predict_taken =
9357 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9358
9359 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9360 __ delayed()->nop();
9361 %}
9362 ins_pipe(br_cc);
9363 %}
9364
9365 // Manifest a CmpL3 result in an integer register. Very painful.
9366 // This is the test to avoid.
9367 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9368 match(Set dst (CmpL3 src1 src2) );
9369 effect( KILL ccr );
9370 ins_cost(6*DEFAULT_COST);
9371 size(24);
9372 format %{ "CMP $src1,$src2\t\t! long\n"
9373 "\tBLT,a,pn done\n"
9374 "\tMOV -1,$dst\t! delay slot\n"
9375 "\tBGT,a,pn done\n"
9376 "\tMOV 1,$dst\t! delay slot\n"
9377 "\tCLR $dst\n"
9378 "done:" %}
9379 ins_encode( cmpl_flag(src1,src2,dst) );
9380 ins_pipe(cmpL_reg);
9381 %}
9469 #endif
9470 ins_encode %{
9471 __ relocate(relocInfo::poll_type);
9472 __ ld_ptr($poll$$Register, 0, G0);
9473 %}
9474 ins_pipe(loadPollP);
9475 %}
9476
9477 // ============================================================================
9478 // Call Instructions
9479 // Call Java Static Instruction
9480 instruct CallStaticJavaDirect( method meth ) %{
9481 match(CallStaticJava);
9482 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9483 effect(USE meth);
9484
9485 size(8);
9486 ins_cost(CALL_COST);
9487 format %{ "CALL,static ; NOP ==> " %}
9488 ins_encode( Java_Static_Call( meth ), call_epilog );
9489 ins_pipe(simple_call);
9490 %}
9491
9492 // Call Java Static Instruction (method handle version)
9493 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9494 match(CallStaticJava);
9495 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9496 effect(USE meth, KILL l7_mh_SP_save);
9497
9498 size(8);
9499 ins_cost(CALL_COST);
9500 format %{ "CALL,static/MethodHandle" %}
9501 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9502 ins_pipe(simple_call);
9503 %}
9504
9505 // Call Java Dynamic Instruction
9506 instruct CallDynamicJavaDirect( method meth ) %{
9507 match(CallDynamicJava);
9508 effect(USE meth);
9509
9510 ins_cost(CALL_COST);
9511 format %{ "SET (empty),R_G5\n\t"
9512 "CALL,dynamic ; NOP ==> " %}
9513 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9514 ins_pipe(call);
9515 %}
9516
9517 // Call Runtime Instruction
9518 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9519 match(CallRuntime);
9520 effect(USE meth, KILL l7);
9521 ins_cost(CALL_COST);
9522 format %{ "CALL,runtime" %}
9523 ins_encode( Java_To_Runtime( meth ),
9524 call_epilog, adjust_long_from_native_call );
9525 ins_pipe(simple_call);
9526 %}
9527
9528 // Call runtime without safepoint - same as CallRuntime
9529 instruct CallLeafDirect(method meth, l7RegP l7) %{
9530 match(CallLeaf);
9531 effect(USE meth, KILL l7);
9532 ins_cost(CALL_COST);
9533 format %{ "CALL,runtime leaf" %}
9534 ins_encode( Java_To_Runtime( meth ),
9535 call_epilog,
9536 adjust_long_from_native_call );
9537 ins_pipe(simple_call);
9538 %}
9539
9540 // Call runtime without safepoint - same as CallLeaf
9541 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9542 match(CallLeafNoFP);
9543 effect(USE meth, KILL l7);
9544 ins_cost(CALL_COST);
9545 format %{ "CALL,runtime leaf nofp" %}
9546 ins_encode( Java_To_Runtime( meth ),
9547 call_epilog,
9548 adjust_long_from_native_call );
9549 ins_pipe(simple_call);
9550 %}
9551
9552 // Tail Call; Jump from runtime stub to Java code.
9553 // Also known as an 'interprocedural jump'.
9554 // Target of jump will eventually return to caller.
9555 // TailJump below removes the return address.
9556 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9557 match(TailCall jump_target method_oop );
9558
9559 ins_cost(CALL_COST);
9560 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9561 ins_encode(form_jmpl(jump_target));
9562 ins_pipe(tail_call);
9563 %}
9564
9565
9566 // Return Instruction
9567 instruct Ret() %{
9568 match(Return);
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