667 #ifdef ASSERT
668 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
669 tty->print_cr("State of YMM registers after signal handle:");
670 int nreg = 2 LP64_ONLY(+2);
671 const char* ymm_name[4] = {"0", "7", "8", "15"};
672 for (int i = 0; i < nreg; i++) {
673 tty->print("YMM%s:", ymm_name[i]);
674 for (int j = 7; j >=0; j--) {
675 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
676 }
677 tty->cr();
678 }
679 }
680 #endif
681 }
682
683 #ifdef _LP64
684 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
685 UseMultiplyToLenIntrinsic = true;
686 }
687 #else
688 if (UseMultiplyToLenIntrinsic) {
689 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
690 warning("multiplyToLen intrinsic is not available in 32-bit VM");
691 }
692 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
693 }
694 #endif
695 #endif // COMPILER2
696
697 // On new cpus instructions which update whole XMM register should be used
698 // to prevent partial register stall due to dependencies on high half.
699 //
700 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
701 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
702 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
703 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
704
705 if( is_amd() ) { // AMD cpus specific settings
706 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
707 // Use it on new AMD cpus starting from Opteron.
708 UseAddressNop = true;
709 }
710 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
711 // Use it on new AMD cpus starting from Opteron.
712 UseNewLongLShift = true;
713 }
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667 #ifdef ASSERT
668 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
669 tty->print_cr("State of YMM registers after signal handle:");
670 int nreg = 2 LP64_ONLY(+2);
671 const char* ymm_name[4] = {"0", "7", "8", "15"};
672 for (int i = 0; i < nreg; i++) {
673 tty->print("YMM%s:", ymm_name[i]);
674 for (int j = 7; j >=0; j--) {
675 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
676 }
677 tty->cr();
678 }
679 }
680 #endif
681 }
682
683 #ifdef _LP64
684 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
685 UseMultiplyToLenIntrinsic = true;
686 }
687 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
688 UseSquareToLenIntrinsic = true;
689 }
690 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
691 UseMulAddIntrinsic = true;
692 }
693 #else
694 if (UseMultiplyToLenIntrinsic) {
695 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
696 warning("multiplyToLen intrinsic is not available in 32-bit VM");
697 }
698 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
699 }
700 if (UseSquareToLenIntrinsic) {
701 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
702 warning("squareToLen intrinsic is not available in 32-bit VM");
703 }
704 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
705 }
706 if (UseMulAddIntrinsic) {
707 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
708 warning("mulAdd intrinsic is not available in 32-bit VM");
709 }
710 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
711 }
712 #endif
713 #endif // COMPILER2
714
715 // On new cpus instructions which update whole XMM register should be used
716 // to prevent partial register stall due to dependencies on high half.
717 //
718 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
719 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
720 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
721 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
722
723 if( is_amd() ) { // AMD cpus specific settings
724 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
725 // Use it on new AMD cpus starting from Opteron.
726 UseAddressNop = true;
727 }
728 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
729 // Use it on new AMD cpus starting from Opteron.
730 UseNewLongLShift = true;
731 }
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