111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 sha_op3 = 0x36,
127 alignaddr_op3 = 0x36,
128 faligndata_op3 = 0x36,
129 flog3_op3 = 0x36,
130 edge_op3 = 0x36,
131 fsrc_op3 = 0x36,
132 xmulx_op3 = 0x36,
133 impdep2_op3 = 0x37,
134 stpartialf_op3 = 0x37,
135 jmpl_op3 = 0x38,
136 rett_op3 = 0x39,
137 trap_op3 = 0x3a,
138 flush_op3 = 0x3b,
139 save_op3 = 0x3c,
140 restore_op3 = 0x3d,
141 done_op3 = 0x3e,
142 retry_op3 = 0x3e,
143
144 lduw_op3 = 0x00,
145 ldub_op3 = 0x01,
146 lduh_op3 = 0x02,
147 ldd_op3 = 0x03,
148 stw_op3 = 0x04,
149 stb_op3 = 0x05,
150 sth_op3 = 0x06,
151 std_op3 = 0x07,
152 ldsw_op3 = 0x08,
214 fitos_opf = 0xc4,
215 fdtos_opf = 0xc6,
216 fitod_opf = 0xc8,
217 fstod_opf = 0xc9,
218 fstoi_opf = 0xd1,
219 fdtoi_opf = 0xd2,
220
221 mdtox_opf = 0x110,
222 mstouw_opf = 0x111,
223 mstosw_opf = 0x113,
224 xmulx_opf = 0x115,
225 xmulxhi_opf = 0x116,
226 mxtod_opf = 0x118,
227 mwtos_opf = 0x119,
228
229 aes_kexpand0_opf = 0x130,
230 aes_kexpand2_opf = 0x131,
231
232 sha1_opf = 0x141,
233 sha256_opf = 0x142,
234 sha512_opf = 0x143
235 };
236
237 enum op5s {
238 aes_eround01_op5 = 0x00,
239 aes_eround23_op5 = 0x01,
240 aes_dround01_op5 = 0x02,
241 aes_dround23_op5 = 0x03,
242 aes_eround01_l_op5 = 0x04,
243 aes_eround23_l_op5 = 0x05,
244 aes_dround01_l_op5 = 0x06,
245 aes_dround23_l_op5 = 0x07,
246 aes_kexpand1_op5 = 0x08
247 };
248
249 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
250
251 enum Condition {
252 // for FBfcc & FBPfcc instruction
253 f_never = 0,
254 f_notEqual = 1,
583 return r;
584 }
585
586 // given a sethi instruction, extract the constant, left-justified
587 static int inv_hi22( int x ) {
588 return x << 10;
589 }
590
591 // create an imm22 field, given a 32-bit left-justified constant
592 static int hi22( int x ) {
593 int r = int( juint(x) >> 10 );
594 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
595 return r;
596 }
597
598 // create a low10 __value__ (not a field) for a given a 32-bit constant
599 static int low10( int x ) {
600 return x & ((1 << 10) - 1);
601 }
602
603 // AES crypto instructions supported only on certain processors
604 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
605
606 // SHA crypto instructions supported only on certain processors
607 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
608 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
609 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
610
611 // instruction only in VIS1
612 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
613
614 // instruction only in VIS2
615 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
616
617 // instruction only in VIS3
618 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
619
620 // instruction only in v9
621 static void v9_only() { } // do nothing
622
623 // instruction deprecated in v9
624 static void v9_dep() { } // do nothing for now
625
626 // v8 has no CC field
627 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
628
629 protected:
630 // Simple delay-slot scheme:
1005 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
1006 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1007 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
1008 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1009
1010 // pp 197
1011
1012 void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
1013 void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1014 void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
1015 void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1016 void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1017 void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1018 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1019 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1020
1021 // pp 201
1022
1023 void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
1024
1025
1026 // pp 202
1027
1028 void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1029 void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1030
1031 // pp 203
1032
1033 void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
1034 void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
1035
1036 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1037 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1038
1039 // pp 208
1040
1041 // not implementing read privileged register
1042
1043 inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1044 inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1181 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1182 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1183 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1184 rs1(s) |
1185 op3(wrreg_op3) |
1186 u_field(2, 29, 25) |
1187 immed(true) |
1188 simm(simm13a, 13)); }
1189 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1190 // wrasi(d, imm) stores (d xor imm) to asi
1191 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1192 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1193 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1194
1195 // VIS1 instructions
1196
1197 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1198
1199 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1200
1201 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1202
1203 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1204
1205 // VIS2 instructions
1206
1207 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1208
1209 // VIS3 instructions
1210
1211 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1212 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1213 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1214
1215 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1216 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1217
1218 void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); }
1219 void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); }
1220
1221 // Crypto SHA instructions
1222
1223 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1224 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1225 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
1226
1227 // Creation
1228 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1229 #ifdef CHECK_DELAY
1230 delay_state = no_delay;
1231 #endif
1232 }
1233 };
1234
1235 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
|
111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 sha_op3 = 0x36,
127 alignaddr_op3 = 0x36,
128 faligndata_op3 = 0x36,
129 flog3_op3 = 0x36,
130 edge_op3 = 0x36,
131 fzero_op3 = 0x36,
132 fsrc_op3 = 0x36,
133 fnot_op3 = 0x36,
134 xmulx_op3 = 0x36,
135 crc32c_op3 = 0x36,
136 impdep2_op3 = 0x37,
137 stpartialf_op3 = 0x37,
138 jmpl_op3 = 0x38,
139 rett_op3 = 0x39,
140 trap_op3 = 0x3a,
141 flush_op3 = 0x3b,
142 save_op3 = 0x3c,
143 restore_op3 = 0x3d,
144 done_op3 = 0x3e,
145 retry_op3 = 0x3e,
146
147 lduw_op3 = 0x00,
148 ldub_op3 = 0x01,
149 lduh_op3 = 0x02,
150 ldd_op3 = 0x03,
151 stw_op3 = 0x04,
152 stb_op3 = 0x05,
153 sth_op3 = 0x06,
154 std_op3 = 0x07,
155 ldsw_op3 = 0x08,
217 fitos_opf = 0xc4,
218 fdtos_opf = 0xc6,
219 fitod_opf = 0xc8,
220 fstod_opf = 0xc9,
221 fstoi_opf = 0xd1,
222 fdtoi_opf = 0xd2,
223
224 mdtox_opf = 0x110,
225 mstouw_opf = 0x111,
226 mstosw_opf = 0x113,
227 xmulx_opf = 0x115,
228 xmulxhi_opf = 0x116,
229 mxtod_opf = 0x118,
230 mwtos_opf = 0x119,
231
232 aes_kexpand0_opf = 0x130,
233 aes_kexpand2_opf = 0x131,
234
235 sha1_opf = 0x141,
236 sha256_opf = 0x142,
237 sha512_opf = 0x143,
238
239 crc32c_opf = 0x147
240 };
241
242 enum op5s {
243 aes_eround01_op5 = 0x00,
244 aes_eround23_op5 = 0x01,
245 aes_dround01_op5 = 0x02,
246 aes_dround23_op5 = 0x03,
247 aes_eround01_l_op5 = 0x04,
248 aes_eround23_l_op5 = 0x05,
249 aes_dround01_l_op5 = 0x06,
250 aes_dround23_l_op5 = 0x07,
251 aes_kexpand1_op5 = 0x08
252 };
253
254 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
255
256 enum Condition {
257 // for FBfcc & FBPfcc instruction
258 f_never = 0,
259 f_notEqual = 1,
588 return r;
589 }
590
591 // given a sethi instruction, extract the constant, left-justified
592 static int inv_hi22( int x ) {
593 return x << 10;
594 }
595
596 // create an imm22 field, given a 32-bit left-justified constant
597 static int hi22( int x ) {
598 int r = int( juint(x) >> 10 );
599 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
600 return r;
601 }
602
603 // create a low10 __value__ (not a field) for a given a 32-bit constant
604 static int low10( int x ) {
605 return x & ((1 << 10) - 1);
606 }
607
608 // create a low12 __value__ (not a field) for a given a 32-bit constant
609 static int low12( int x ) {
610 return x & ((1 << 12) - 1);
611 }
612
613 // AES crypto instructions supported only on certain processors
614 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
615
616 // SHA crypto instructions supported only on certain processors
617 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
618 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
619 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
620
621 // CRC32C instruction supported only on certain processors
622 static void crc32c_only() { assert( VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
623
624 // instruction only in VIS1
625 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
626
627 // instruction only in VIS2
628 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
629
630 // instruction only in VIS3
631 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
632
633 // instruction only in v9
634 static void v9_only() { } // do nothing
635
636 // instruction deprecated in v9
637 static void v9_dep() { } // do nothing for now
638
639 // v8 has no CC field
640 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
641
642 protected:
643 // Simple delay-slot scheme:
1018 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
1019 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1020 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
1021 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1022
1023 // pp 197
1024
1025 void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
1026 void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1027 void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
1028 void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1029 void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1030 void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1031 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1032 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1033
1034 // pp 201
1035
1036 void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
1037
1038 void sw_count() { emit_int32( op(branch_op) | op2(sethi_op2) | 0x3f0 ); }
1039
1040 // pp 202
1041
1042 void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1043 void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1044
1045 // pp 203
1046
1047 void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
1048 void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
1049
1050 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1051 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1052
1053 // pp 208
1054
1055 // not implementing read privileged register
1056
1057 inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1058 inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1195 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1196 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1197 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1198 rs1(s) |
1199 op3(wrreg_op3) |
1200 u_field(2, 29, 25) |
1201 immed(true) |
1202 simm(simm13a, 13)); }
1203 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1204 // wrasi(d, imm) stores (d xor imm) to asi
1205 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1206 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1207 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1208
1209 // VIS1 instructions
1210
1211 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1212
1213 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1214
1215 void fzero( FloatRegisterImpl::Width w, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w)); }
1216
1217 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1218
1219 void fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w)); }
1220
1221 void fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S)); }
1222
1223 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1224
1225 // VIS2 instructions
1226
1227 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1228
1229 // VIS3 instructions
1230
1231 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1232 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1233 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1234
1235 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1236 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1237
1238 void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); }
1239 void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); }
1240
1241 // Crypto SHA instructions
1242
1243 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1244 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1245 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
1246
1247 // CRC32C instruction
1248
1249 void crc32c( FloatRegister s1, FloatRegister s2, FloatRegister d ) { crc32c_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(crc32c_op3) | fs1(s1, FloatRegisterImpl::D) | opf(crc32c_opf) | fs2(s2, FloatRegisterImpl::D)); }
1250
1251 // Creation
1252 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1253 #ifdef CHECK_DELAY
1254 delay_state = no_delay;
1255 #endif
1256 }
1257 };
1258
1259 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
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