*** old/src/cpu/sparc/vm/assembler_sparc.hpp	Thu Jun 25 16:47:22 2015
--- new/src/cpu/sparc/vm/assembler_sparc.hpp	Thu Jun 25 16:47:22 2015

*** 126,137 ****
--- 126,140 ----
      sha_op3      = 0x36,
      alignaddr_op3  = 0x36,
      faligndata_op3 = 0x36,
      flog3_op3    = 0x36,
      edge_op3     = 0x36,
+     fzero_op3    = 0x36,
      fsrc_op3     = 0x36,
+     fnot_op3     = 0x36,
      xmulx_op3    = 0x36,
+     crc32c_op3   = 0x36,
      impdep2_op3  = 0x37,
      stpartialf_op3 = 0x37,
      jmpl_op3     = 0x38,
      rett_op3     = 0x39,
      trap_op3     = 0x3a,

*** 229,239 ****
--- 232,244 ----
      aes_kexpand0_opf   = 0x130,
      aes_kexpand2_opf   = 0x131,
  
      sha1_opf           = 0x141,
      sha256_opf         = 0x142,
!     sha512_opf         = 0x143,
+ 
+     crc32c_opf         = 0x147
    };
  
    enum op5s {
      aes_eround01_op5     = 0x00,
      aes_eround23_op5     = 0x01,

*** 598,615 ****
--- 603,628 ----
    // create a low10 __value__ (not a field) for a given a 32-bit constant
    static int low10( int x ) {
      return x & ((1 << 10) - 1);
    }
  
+   // create a low12 __value__ (not a field) for a given a 32-bit constant
+   static int low12( int x ) {
+     return x & ((1 << 12) - 1);
+   }
+ 
    // AES crypto instructions supported only on certain processors
    static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
  
    // SHA crypto instructions supported only on certain processors
    static void sha1_only()   { assert( VM_Version::has_sha1(),   "This instruction only works on SPARC with SHA1"); }
    static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
    static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
  
+   // CRC32C instruction supported only on certain processors
+   static void crc32c_only() { assert( VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
+ 
    // instruction only in VIS1
    static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
  
    // instruction only in VIS2
    static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }

*** 1020,1029 ****
--- 1033,1043 ----
  
    // pp 201
  
    void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
  
+   void sw_count() { emit_int32( op(branch_op) | op2(sethi_op2) | 0x3f0 ); }
  
    // pp 202
  
    void popc( Register s,  Register d) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
    void popc( int simm13a, Register d) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }

*** 1196,1207 ****
--- 1210,1227 ----
  
    void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
  
    void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
  
+   void fzero( FloatRegisterImpl::Width w, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w)); }
+ 
    void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
  
+   void fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w)); }
+ 
+   void fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S)); }
+ 
    void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
  
    //  VIS2 instructions
  
    void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }

*** 1222,1231 ****
--- 1242,1255 ----
  
    void sha1()   { sha1_only();    emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
    void sha256() { sha256_only();  emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
    void sha512() { sha512_only();  emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
  
+   // CRC32C instruction
+ 
+   void crc32c( FloatRegister s1, FloatRegister s2, FloatRegister d ) { crc32c_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(crc32c_op3) | fs1(s1, FloatRegisterImpl::D) | opf(crc32c_opf) | fs2(s2, FloatRegisterImpl::D)); }
+ 
    // Creation
    Assembler(CodeBuffer* code) : AbstractAssembler(code) {
  #ifdef CHECK_DELAY
      delay_state = no_delay;
  #endif