213 }
214
215 #ifdef COMPILER2
216 // T4 and newer Sparc cpus have fast RDPC.
217 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
218 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
219 }
220
221 // Currently not supported anywhere.
222 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
223
224 MaxVectorSize = 8;
225
226 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
227 #endif
228
229 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
230 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
231
232 char buf[512];
233 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
234 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
235 (has_hardware_popc() ? ", popc" : ""),
236 (has_vis1() ? ", vis1" : ""),
237 (has_vis2() ? ", vis2" : ""),
238 (has_vis3() ? ", vis3" : ""),
239 (has_blk_init() ? ", blk_init" : ""),
240 (has_cbcond() ? ", cbcond" : ""),
241 (has_aes() ? ", aes" : ""),
242 (has_sha1() ? ", sha1" : ""),
243 (has_sha256() ? ", sha256" : ""),
244 (has_sha512() ? ", sha512" : ""),
245 (is_ultra3() ? ", ultra3" : ""),
246 (is_sun4v() ? ", sun4v" : ""),
247 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
248 (is_sparc64() ? ", sparc64" : ""),
249 (!has_hardware_mul32() ? ", no-mul32" : ""),
250 (!has_hardware_div32() ? ", no-div32" : ""),
251 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
252
253 // buf is started with ", " or is empty
254 _features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
255
256 // UseVIS is set to the smallest of what hardware supports and what
257 // the command line requires. I.e., you cannot set UseVIS to 3 on
258 // older UltraSparc which do not support it.
259 if (UseVIS > 3) UseVIS=3;
260 if (UseVIS < 0) UseVIS=0;
261 if (!has_vis3()) // Drop to 2 if no VIS3 support
262 UseVIS = MIN2((intx)2,UseVIS);
263 if (!has_vis2()) // Drop to 1 if no VIS2 support
264 UseVIS = MIN2((intx)1,UseVIS);
346 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
347 }
348 } else if (UseSHA256Intrinsics) {
349 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
350 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
351 }
352
353 if (has_sha512()) {
354 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
355 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
356 }
357 } else if (UseSHA512Intrinsics) {
358 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
359 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
360 }
361 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
362 FLAG_SET_DEFAULT(UseSHA, false);
363 }
364 }
365
366 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
367 (cache_line_size > ContendedPaddingWidth))
368 ContendedPaddingWidth = cache_line_size;
369
370 // This machine does not allow unaligned memory accesses
371 if (UseUnalignedAccesses) {
372 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
373 warning("Unaligned memory access is not available on this CPU");
374 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
375 }
376
377 #ifndef PRODUCT
378 if (PrintMiscellaneous && Verbose) {
379 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
380 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
381 tty->print("Allocation");
382 if (AllocatePrefetchStyle <= 0) {
383 tty->print_cr(": no prefetching");
384 } else {
385 tty->print(" prefetching: ");
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213 }
214
215 #ifdef COMPILER2
216 // T4 and newer Sparc cpus have fast RDPC.
217 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
218 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
219 }
220
221 // Currently not supported anywhere.
222 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
223
224 MaxVectorSize = 8;
225
226 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
227 #endif
228
229 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
230 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
231
232 char buf[512];
233 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
234 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
235 (has_hardware_popc() ? ", popc" : ""),
236 (has_vis1() ? ", vis1" : ""),
237 (has_vis2() ? ", vis2" : ""),
238 (has_vis3() ? ", vis3" : ""),
239 (has_blk_init() ? ", blk_init" : ""),
240 (has_cbcond() ? ", cbcond" : ""),
241 (has_aes() ? ", aes" : ""),
242 (has_sha1() ? ", sha1" : ""),
243 (has_sha256() ? ", sha256" : ""),
244 (has_sha512() ? ", sha512" : ""),
245 (has_crc32c() ? ", crc32c" : ""),
246 (is_ultra3() ? ", ultra3" : ""),
247 (is_sun4v() ? ", sun4v" : ""),
248 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
249 (is_sparc64() ? ", sparc64" : ""),
250 (!has_hardware_mul32() ? ", no-mul32" : ""),
251 (!has_hardware_div32() ? ", no-div32" : ""),
252 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
253
254 // buf is started with ", " or is empty
255 _features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
256
257 // UseVIS is set to the smallest of what hardware supports and what
258 // the command line requires. I.e., you cannot set UseVIS to 3 on
259 // older UltraSparc which do not support it.
260 if (UseVIS > 3) UseVIS=3;
261 if (UseVIS < 0) UseVIS=0;
262 if (!has_vis3()) // Drop to 2 if no VIS3 support
263 UseVIS = MIN2((intx)2,UseVIS);
264 if (!has_vis2()) // Drop to 1 if no VIS2 support
265 UseVIS = MIN2((intx)1,UseVIS);
347 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
348 }
349 } else if (UseSHA256Intrinsics) {
350 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
351 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
352 }
353
354 if (has_sha512()) {
355 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
356 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
357 }
358 } else if (UseSHA512Intrinsics) {
359 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
360 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
361 }
362 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
363 FLAG_SET_DEFAULT(UseSHA, false);
364 }
365 }
366
367 // SPARC T4 and above should have support for CRC32C instruction
368 if (has_crc32c()) {
369 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
370 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
371 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
372 }
373 } else {
374 if (UseCRC32CIntrinsics) {
375 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
376 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
377 }
378 }
379 } else if (UseCRC32CIntrinsics) {
380 warning("CRC32C instruction is not available on this CPU");
381 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
382 }
383
384 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
385 (cache_line_size > ContendedPaddingWidth))
386 ContendedPaddingWidth = cache_line_size;
387
388 // This machine does not allow unaligned memory accesses
389 if (UseUnalignedAccesses) {
390 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
391 warning("Unaligned memory access is not available on this CPU");
392 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
393 }
394
395 #ifndef PRODUCT
396 if (PrintMiscellaneous && Verbose) {
397 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
398 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
399 tty->print("Allocation");
400 if (AllocatePrefetchStyle <= 0) {
401 tty->print_cr(": no prefetching");
402 } else {
403 tty->print(" prefetching: ");
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