1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_x86.hpp"
33
34
35 int VM_Version::_cpu;
36 int VM_Version::_model;
37 int VM_Version::_stepping;
38 uint64_t VM_Version::_cpuFeatures;
39 const char* VM_Version::_features_str = "";
40 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
41
42 // Address of instruction which causes SEGV
43 address VM_Version::_cpuinfo_segv_addr = 0;
44 // Address of instruction after the one which causes SEGV
45 address VM_Version::_cpuinfo_cont_addr = 0;
46
47 static BufferBlob* stub_blob;
48 static const int stub_size = 1000;
49
50 extern "C" {
51 typedef void (*get_cpu_info_stub_t)(void*);
52 }
53 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
54
55
56 class VM_Version_StubGenerator: public StubCodeGenerator {
57 public:
58
59 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
60
61 address generate_get_cpu_info() {
62 // Flags to test CPU type.
63 const uint32_t HS_EFL_AC = 0x40000;
64 const uint32_t HS_EFL_ID = 0x200000;
65 // Values for when we don't have a CPUID instruction.
66 const int CPU_FAMILY_SHIFT = 8;
67 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
68 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
69
70 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
71 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup;
72 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
73
74 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
75 # define __ _masm->
76
77 address start = __ pc();
78
79 //
80 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
81 //
82 // LP64: rcx and rdx are first and second argument registers on windows
83
84 __ push(rbp);
85 #ifdef _LP64
86 __ mov(rbp, c_rarg0); // cpuid_info address
87 #else
88 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
89 #endif
90 __ push(rbx);
91 __ push(rsi);
92 __ pushf(); // preserve rbx, and flags
93 __ pop(rax);
94 __ push(rax);
95 __ mov(rcx, rax);
96 //
97 // if we are unable to change the AC flag, we have a 386
98 //
99 __ xorl(rax, HS_EFL_AC);
100 __ push(rax);
101 __ popf();
102 __ pushf();
103 __ pop(rax);
104 __ cmpptr(rax, rcx);
105 __ jccb(Assembler::notEqual, detect_486);
106
107 __ movl(rax, CPU_FAMILY_386);
108 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
109 __ jmp(done);
110
111 //
112 // If we are unable to change the ID flag, we have a 486 which does
113 // not support the "cpuid" instruction.
114 //
115 __ bind(detect_486);
116 __ mov(rax, rcx);
117 __ xorl(rax, HS_EFL_ID);
118 __ push(rax);
119 __ popf();
120 __ pushf();
121 __ pop(rax);
122 __ cmpptr(rcx, rax);
123 __ jccb(Assembler::notEqual, detect_586);
124
125 __ bind(cpu486);
126 __ movl(rax, CPU_FAMILY_486);
127 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
128 __ jmp(done);
129
130 //
131 // At this point, we have a chip which supports the "cpuid" instruction
132 //
133 __ bind(detect_586);
134 __ xorl(rax, rax);
135 __ cpuid();
136 __ orl(rax, rax);
137 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
138 // value of at least 1, we give up and
139 // assume a 486
140 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
141 __ movl(Address(rsi, 0), rax);
142 __ movl(Address(rsi, 4), rbx);
143 __ movl(Address(rsi, 8), rcx);
144 __ movl(Address(rsi,12), rdx);
145
146 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
147 __ jccb(Assembler::belowEqual, std_cpuid4);
148
149 //
150 // cpuid(0xB) Processor Topology
151 //
152 __ movl(rax, 0xb);
153 __ xorl(rcx, rcx); // Threads level
154 __ cpuid();
155
156 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
157 __ movl(Address(rsi, 0), rax);
158 __ movl(Address(rsi, 4), rbx);
159 __ movl(Address(rsi, 8), rcx);
160 __ movl(Address(rsi,12), rdx);
161
162 __ movl(rax, 0xb);
163 __ movl(rcx, 1); // Cores level
164 __ cpuid();
165 __ push(rax);
166 __ andl(rax, 0x1f); // Determine if valid topology level
167 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
168 __ andl(rax, 0xffff);
169 __ pop(rax);
170 __ jccb(Assembler::equal, std_cpuid4);
171
172 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
173 __ movl(Address(rsi, 0), rax);
174 __ movl(Address(rsi, 4), rbx);
175 __ movl(Address(rsi, 8), rcx);
176 __ movl(Address(rsi,12), rdx);
177
178 __ movl(rax, 0xb);
179 __ movl(rcx, 2); // Packages level
180 __ cpuid();
181 __ push(rax);
182 __ andl(rax, 0x1f); // Determine if valid topology level
183 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
184 __ andl(rax, 0xffff);
185 __ pop(rax);
186 __ jccb(Assembler::equal, std_cpuid4);
187
188 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
189 __ movl(Address(rsi, 0), rax);
190 __ movl(Address(rsi, 4), rbx);
191 __ movl(Address(rsi, 8), rcx);
192 __ movl(Address(rsi,12), rdx);
193
194 //
195 // cpuid(0x4) Deterministic cache params
196 //
197 __ bind(std_cpuid4);
198 __ movl(rax, 4);
199 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
200 __ jccb(Assembler::greater, std_cpuid1);
201
202 __ xorl(rcx, rcx); // L1 cache
203 __ cpuid();
204 __ push(rax);
205 __ andl(rax, 0x1f); // Determine if valid cache parameters used
206 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
207 __ pop(rax);
208 __ jccb(Assembler::equal, std_cpuid1);
209
210 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
211 __ movl(Address(rsi, 0), rax);
212 __ movl(Address(rsi, 4), rbx);
213 __ movl(Address(rsi, 8), rcx);
214 __ movl(Address(rsi,12), rdx);
215
216 //
217 // Standard cpuid(0x1)
218 //
219 __ bind(std_cpuid1);
220 __ movl(rax, 1);
221 __ cpuid();
222 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
223 __ movl(Address(rsi, 0), rax);
224 __ movl(Address(rsi, 4), rbx);
225 __ movl(Address(rsi, 8), rcx);
226 __ movl(Address(rsi,12), rdx);
227
228 //
229 // Check if OS has enabled XGETBV instruction to access XCR0
230 // (OSXSAVE feature flag) and CPU supports AVX
231 //
232 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
233 __ cmpl(rcx, 0x18000000);
234 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
235
236 //
237 // XCR0, XFEATURE_ENABLED_MASK register
238 //
239 __ xorl(rcx, rcx); // zero for XCR0 register
240 __ xgetbv();
241 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
242 __ movl(Address(rsi, 0), rax);
243 __ movl(Address(rsi, 4), rdx);
244
245 //
246 // cpuid(0x7) Structured Extended Features
247 //
248 __ bind(sef_cpuid);
249 __ movl(rax, 7);
250 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
251 __ jccb(Assembler::greater, ext_cpuid);
252
253 __ xorl(rcx, rcx);
254 __ cpuid();
255 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
256 __ movl(Address(rsi, 0), rax);
257 __ movl(Address(rsi, 4), rbx);
258
259 //
260 // Extended cpuid(0x80000000)
261 //
262 __ bind(ext_cpuid);
263 __ movl(rax, 0x80000000);
264 __ cpuid();
265 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
266 __ jcc(Assembler::belowEqual, done);
267 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
268 __ jccb(Assembler::belowEqual, ext_cpuid1);
269 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
270 __ jccb(Assembler::belowEqual, ext_cpuid5);
271 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
272 __ jccb(Assembler::belowEqual, ext_cpuid7);
273 //
274 // Extended cpuid(0x80000008)
275 //
276 __ movl(rax, 0x80000008);
277 __ cpuid();
278 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
279 __ movl(Address(rsi, 0), rax);
280 __ movl(Address(rsi, 4), rbx);
281 __ movl(Address(rsi, 8), rcx);
282 __ movl(Address(rsi,12), rdx);
283
284 //
285 // Extended cpuid(0x80000007)
286 //
287 __ bind(ext_cpuid7);
288 __ movl(rax, 0x80000007);
289 __ cpuid();
290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
291 __ movl(Address(rsi, 0), rax);
292 __ movl(Address(rsi, 4), rbx);
293 __ movl(Address(rsi, 8), rcx);
294 __ movl(Address(rsi,12), rdx);
295
296 //
297 // Extended cpuid(0x80000005)
298 //
299 __ bind(ext_cpuid5);
300 __ movl(rax, 0x80000005);
301 __ cpuid();
302 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
303 __ movl(Address(rsi, 0), rax);
304 __ movl(Address(rsi, 4), rbx);
305 __ movl(Address(rsi, 8), rcx);
306 __ movl(Address(rsi,12), rdx);
307
308 //
309 // Extended cpuid(0x80000001)
310 //
311 __ bind(ext_cpuid1);
312 __ movl(rax, 0x80000001);
313 __ cpuid();
314 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
315 __ movl(Address(rsi, 0), rax);
316 __ movl(Address(rsi, 4), rbx);
317 __ movl(Address(rsi, 8), rcx);
318 __ movl(Address(rsi,12), rdx);
319
320 //
321 // Check if OS has enabled XGETBV instruction to access XCR0
322 // (OSXSAVE feature flag) and CPU supports AVX
323 //
324 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
325 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
326 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
327 __ cmpl(rcx, 0x18000000);
328 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
329
330 __ movl(rax, 0x6);
331 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
332 __ cmpl(rax, 0x6);
333 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
334
335 // we need to bridge farther than imm8, so we use this island as a thunk
336 __ bind(done);
337 __ jmp(wrapup);
338
339 __ bind(start_simd_check);
340 //
341 // Some OSs have a bug when upper 128/256bits of YMM/ZMM
342 // registers are not restored after a signal processing.
343 // Generate SEGV here (reference through NULL)
344 // and check upper YMM/ZMM bits after it.
345 //
346 intx saved_useavx = UseAVX;
347 intx saved_usesse = UseSSE;
348 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
349 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
350 __ movl(rax, 0x10000);
351 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
352 __ cmpl(rax, 0x10000);
353 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
354 // check _cpuid_info.xem_xcr0_eax.bits.opmask
355 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
356 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
357 __ movl(rax, 0xE0);
358 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
359 __ cmpl(rax, 0xE0);
360 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
361
362 // EVEX setup: run in lowest evex mode
363 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
364 UseAVX = 3;
365 UseSSE = 2;
366 // load value into all 64 bytes of zmm7 register
367 __ movl(rcx, VM_Version::ymm_test_value());
368 __ movdl(xmm0, rcx);
369 __ movl(rcx, 0xffff);
370 #ifdef _LP64
371 __ kmovql(k1, rcx);
372 #else
373 __ kmovdl(k1, rcx);
374 #endif
375 __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
376 __ evmovdqu(xmm7, xmm0, Assembler::AVX_512bit);
377 #ifdef _LP64
378 __ evmovdqu(xmm8, xmm0, Assembler::AVX_512bit);
379 __ evmovdqu(xmm31, xmm0, Assembler::AVX_512bit);
380 #endif
381 VM_Version::clean_cpuFeatures();
382 __ jmp(save_restore_except);
383
384 __ bind(legacy_setup);
385 // AVX setup
386 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
387 UseAVX = 1;
388 UseSSE = 2;
389 // load value into all 32 bytes of ymm7 register
390 __ movl(rcx, VM_Version::ymm_test_value());
391
392 __ movdl(xmm0, rcx);
393 __ pshufd(xmm0, xmm0, 0x00);
394 __ vinsertf128h(xmm0, xmm0, xmm0);
395 __ vmovdqu(xmm7, xmm0);
396 #ifdef _LP64
397 __ vmovdqu(xmm8, xmm0);
398 __ vmovdqu(xmm15, xmm0);
399 #endif
400 VM_Version::clean_cpuFeatures();
401
402 __ bind(save_restore_except);
403 __ xorl(rsi, rsi);
404 VM_Version::set_cpuinfo_segv_addr(__ pc());
405 // Generate SEGV
406 __ movl(rax, Address(rsi, 0));
407
408 VM_Version::set_cpuinfo_cont_addr(__ pc());
409 // Returns here after signal. Save xmm0 to check it later.
410
411 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
412 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
413 __ movl(rax, 0x10000);
414 __ andl(rax, Address(rsi, 4));
415 __ cmpl(rax, 0x10000);
416 __ jccb(Assembler::notEqual, legacy_save_restore);
417 // check _cpuid_info.xem_xcr0_eax.bits.opmask
418 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
419 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
420 __ movl(rax, 0xE0);
421 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
422 __ cmpl(rax, 0xE0);
423 __ jccb(Assembler::notEqual, legacy_save_restore);
424
425 // EVEX check: run in lowest evex mode
426 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
427 UseAVX = 3;
428 UseSSE = 2;
429 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
430 __ evmovdqu(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
431 __ evmovdqu(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
432 #ifdef _LP64
433 __ evmovdqu(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
434 __ evmovdqu(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
435 #endif
436 VM_Version::clean_cpuFeatures();
437 UseAVX = saved_useavx;
438 UseSSE = saved_usesse;
439 __ jmp(wrapup);
440
441 __ bind(legacy_save_restore);
442 // AVX check
443 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
444 UseAVX = 1;
445 UseSSE = 2;
446 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
447 __ vmovdqu(Address(rsi, 0), xmm0);
448 __ vmovdqu(Address(rsi, 32), xmm7);
449 #ifdef _LP64
450 __ vmovdqu(Address(rsi, 64), xmm8);
451 __ vmovdqu(Address(rsi, 96), xmm15);
452 #endif
453 VM_Version::clean_cpuFeatures();
454 UseAVX = saved_useavx;
455 UseSSE = saved_usesse;
456
457 __ bind(wrapup);
458 __ popf();
459 __ pop(rsi);
460 __ pop(rbx);
461 __ pop(rbp);
462 __ ret(0);
463
464 # undef __
465
466 return start;
467 };
468 };
469
470
471 void VM_Version::get_cpu_info_wrapper() {
472 get_cpu_info_stub(&_cpuid_info);
473 }
474
475 #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED
476 #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f()
477 #endif
478
479 void VM_Version::get_processor_features() {
480
481 _cpu = 4; // 486 by default
482 _model = 0;
483 _stepping = 0;
484 _cpuFeatures = 0;
485 _logical_processors_per_package = 1;
486 // i486 internal cache is both I&D and has a 16-byte line size
487 _L1_data_cache_line_size = 16;
488
489 if (!Use486InstrsOnly) {
490 // Get raw processor info
491
492 // Some platforms (like Win*) need a wrapper around here
493 // in order to properly handle SEGV for YMM registers test.
494 CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(get_cpu_info_wrapper);
495
496 assert_is_initialized();
497 _cpu = extended_cpu_family();
498 _model = extended_cpu_model();
499 _stepping = cpu_stepping();
500
501 if (cpu_family() > 4) { // it supports CPUID
502 _cpuFeatures = feature_flags();
503 // Logical processors are only available on P4s and above,
504 // and only if hyperthreading is available.
505 _logical_processors_per_package = logical_processor_count();
506 _L1_data_cache_line_size = L1_line_size();
507 }
508 }
509
510 _supports_cx8 = supports_cmpxchg8();
511 // xchg and xadd instructions
512 _supports_atomic_getset4 = true;
513 _supports_atomic_getadd4 = true;
514 LP64_ONLY(_supports_atomic_getset8 = true);
515 LP64_ONLY(_supports_atomic_getadd8 = true);
516
517 #ifdef _LP64
518 // OS should support SSE for x64 and hardware should support at least SSE2.
519 if (!VM_Version::supports_sse2()) {
520 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
521 }
522 // in 64 bit the use of SSE2 is the minimum
523 if (UseSSE < 2) UseSSE = 2;
524 #endif
525
526 #ifdef AMD64
527 // flush_icache_stub have to be generated first.
528 // That is why Icache line size is hard coded in ICache class,
529 // see icache_x86.hpp. It is also the reason why we can't use
530 // clflush instruction in 32-bit VM since it could be running
531 // on CPU which does not support it.
532 //
533 // The only thing we can do is to verify that flushed
534 // ICache::line_size has correct value.
535 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
536 // clflush_size is size in quadwords (8 bytes).
537 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
538 #endif
539
540 // If the OS doesn't support SSE, we can't use this feature even if the HW does
541 if (!os::supports_sse())
542 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
543
544 if (UseSSE < 4) {
545 _cpuFeatures &= ~CPU_SSE4_1;
546 _cpuFeatures &= ~CPU_SSE4_2;
547 }
548
549 if (UseSSE < 3) {
550 _cpuFeatures &= ~CPU_SSE3;
551 _cpuFeatures &= ~CPU_SSSE3;
552 _cpuFeatures &= ~CPU_SSE4A;
553 }
554
555 if (UseSSE < 2)
556 _cpuFeatures &= ~CPU_SSE2;
557
558 if (UseSSE < 1)
559 _cpuFeatures &= ~CPU_SSE;
560
561 // first try initial setting and detect what we can support
562 if (UseAVX > 0) {
563 if (UseAVX > 2 && supports_evex()) {
564 UseAVX = 3;
565 } else if (UseAVX > 1 && supports_avx2()) {
566 UseAVX = 2;
567 } else if (UseAVX > 0 && supports_avx()) {
568 UseAVX = 1;
569 } else {
570 UseAVX = 0;
571 }
572 } else if (UseAVX < 0) {
573 UseAVX = 0;
574 }
575
576 if (UseAVX < 3) {
577 _cpuFeatures &= ~CPU_AVX512F;
578 _cpuFeatures &= ~CPU_AVX512DQ;
579 _cpuFeatures &= ~CPU_AVX512CD;
580 _cpuFeatures &= ~CPU_AVX512BW;
581 _cpuFeatures &= ~CPU_AVX512VL;
582 }
583
584 if (UseAVX < 2)
585 _cpuFeatures &= ~CPU_AVX2;
586
587 if (UseAVX < 1)
588 _cpuFeatures &= ~CPU_AVX;
589
590 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
591 _cpuFeatures &= ~CPU_AES;
592
593 if (logical_processors_per_package() == 1) {
594 // HT processor could be installed on a system which doesn't support HT.
595 _cpuFeatures &= ~CPU_HT;
596 }
597
598 char buf[256];
599 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
600 cores_per_cpu(), threads_per_core(),
601 cpu_family(), _model, _stepping,
602 (supports_cmov() ? ", cmov" : ""),
603 (supports_cmpxchg8() ? ", cx8" : ""),
604 (supports_fxsr() ? ", fxsr" : ""),
605 (supports_mmx() ? ", mmx" : ""),
606 (supports_sse() ? ", sse" : ""),
607 (supports_sse2() ? ", sse2" : ""),
608 (supports_sse3() ? ", sse3" : ""),
609 (supports_ssse3()? ", ssse3": ""),
610 (supports_sse4_1() ? ", sse4.1" : ""),
611 (supports_sse4_2() ? ", sse4.2" : ""),
612 (supports_popcnt() ? ", popcnt" : ""),
613 (supports_avx() ? ", avx" : ""),
614 (supports_avx2() ? ", avx2" : ""),
615 (supports_aes() ? ", aes" : ""),
616 (supports_clmul() ? ", clmul" : ""),
617 (supports_erms() ? ", erms" : ""),
618 (supports_rtm() ? ", rtm" : ""),
619 (supports_mmx_ext() ? ", mmxext" : ""),
620 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
621 (supports_lzcnt() ? ", lzcnt": ""),
622 (supports_sse4a() ? ", sse4a": ""),
623 (supports_ht() ? ", ht": ""),
624 (supports_tsc() ? ", tsc": ""),
625 (supports_tscinv_bit() ? ", tscinvbit": ""),
626 (supports_tscinv() ? ", tscinv": ""),
627 (supports_bmi1() ? ", bmi1" : ""),
628 (supports_bmi2() ? ", bmi2" : ""),
629 (supports_adx() ? ", adx" : ""),
630 (supports_evex() ? ", evex" : ""));
631 _features_str = os::strdup(buf);
632
633 // UseSSE is set to the smaller of what hardware supports and what
634 // the command line requires. I.e., you cannot set UseSSE to 2 on
635 // older Pentiums which do not support it.
636 if (UseSSE > 4) UseSSE=4;
637 if (UseSSE < 0) UseSSE=0;
638 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
639 UseSSE = MIN2((intx)3,UseSSE);
640 if (!supports_sse3()) // Drop to 2 if no SSE3 support
641 UseSSE = MIN2((intx)2,UseSSE);
642 if (!supports_sse2()) // Drop to 1 if no SSE2 support
643 UseSSE = MIN2((intx)1,UseSSE);
644 if (!supports_sse ()) // Drop to 0 if no SSE support
645 UseSSE = 0;
646
647 // Use AES instructions if available.
648 if (supports_aes()) {
649 if (FLAG_IS_DEFAULT(UseAES)) {
650 UseAES = true;
651 }
652 } else if (UseAES) {
653 if (!FLAG_IS_DEFAULT(UseAES))
654 warning("AES instructions are not available on this CPU");
655 FLAG_SET_DEFAULT(UseAES, false);
656 }
657
658 // Use CLMUL instructions if available.
659 if (supports_clmul()) {
660 if (FLAG_IS_DEFAULT(UseCLMUL)) {
661 UseCLMUL = true;
662 }
663 } else if (UseCLMUL) {
664 if (!FLAG_IS_DEFAULT(UseCLMUL))
665 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
666 FLAG_SET_DEFAULT(UseCLMUL, false);
667 }
668
669 if (UseCLMUL && (UseSSE > 2)) {
670 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
671 UseCRC32Intrinsics = true;
672 }
673 } else if (UseCRC32Intrinsics) {
674 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
675 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
676 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
677 }
678
679 // The AES intrinsic stubs require AES instruction support (of course)
680 // but also require sse3 mode for instructions it use.
681 if (UseAES && (UseSSE > 2)) {
682 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
683 UseAESIntrinsics = true;
684 }
685 } else if (UseAESIntrinsics) {
686 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
687 warning("AES intrinsics are not available on this CPU");
688 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
689 }
690
691 if (UseSHA) {
692 warning("SHA instructions are not available on this CPU");
693 FLAG_SET_DEFAULT(UseSHA, false);
694 }
695 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
696 warning("SHA intrinsics are not available on this CPU");
697 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
698 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
699 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
700 }
701
702 // Adjust RTM (Restricted Transactional Memory) flags
703 if (!supports_rtm() && UseRTMLocking) {
704 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
705 // setting during arguments processing. See use_biased_locking().
706 // VM_Version_init() is executed after UseBiasedLocking is used
707 // in Thread::allocate().
708 vm_exit_during_initialization("RTM instructions are not available on this CPU");
709 }
710
711 #if INCLUDE_RTM_OPT
712 if (UseRTMLocking) {
713 if (is_intel_family_core()) {
714 if ((_model == CPU_MODEL_HASWELL_E3) ||
715 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
716 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
717 // currently a collision between SKL and HSW_E3
718 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
719 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
720 } else {
721 warning("UseRTMLocking is only available as experimental option on this platform.");
722 }
723 }
724 }
725 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
726 // RTM locking should be used only for applications with
727 // high lock contention. For now we do not use it by default.
728 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
729 }
730 if (!is_power_of_2(RTMTotalCountIncrRate)) {
731 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
732 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
733 }
734 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
735 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
736 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
737 }
738 } else { // !UseRTMLocking
739 if (UseRTMForStackLocks) {
740 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
741 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
742 }
743 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
744 }
745 if (UseRTMDeopt) {
746 FLAG_SET_DEFAULT(UseRTMDeopt, false);
747 }
748 if (PrintPreciseRTMLockingStatistics) {
749 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
750 }
751 }
752 #else
753 if (UseRTMLocking) {
754 // Only C2 does RTM locking optimization.
755 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
756 // setting during arguments processing. See use_biased_locking().
757 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
758 }
759 #endif
760
761 #ifdef COMPILER2
762 if (UseFPUForSpilling) {
763 if (UseSSE < 2) {
764 // Only supported with SSE2+
765 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
766 }
767 }
768 if (MaxVectorSize > 0) {
769 if (!is_power_of_2(MaxVectorSize)) {
770 warning("MaxVectorSize must be a power of 2");
771 FLAG_SET_DEFAULT(MaxVectorSize, 64);
772 }
773 if (MaxVectorSize > 64) {
774 FLAG_SET_DEFAULT(MaxVectorSize, 64);
775 }
776 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
777 // 32 bytes vectors (in YMM) are only supported with AVX+
778 FLAG_SET_DEFAULT(MaxVectorSize, 16);
779 }
780 if (UseSSE < 2) {
781 // Vectors (in XMM) are only supported with SSE2+
782 FLAG_SET_DEFAULT(MaxVectorSize, 0);
783 }
784 #ifdef ASSERT
785 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
786 tty->print_cr("State of YMM registers after signal handle:");
787 int nreg = 2 LP64_ONLY(+2);
788 const char* ymm_name[4] = {"0", "7", "8", "15"};
789 for (int i = 0; i < nreg; i++) {
790 tty->print("YMM%s:", ymm_name[i]);
791 for (int j = 7; j >=0; j--) {
792 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
793 }
794 tty->cr();
795 }
796 }
797 #endif
798 }
799
800 #ifdef _LP64
801 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
802 UseMultiplyToLenIntrinsic = true;
803 }
804 #else
805 if (UseMultiplyToLenIntrinsic) {
806 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
807 warning("multiplyToLen intrinsic is not available in 32-bit VM");
808 }
809 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
810 }
811 #endif
812 #endif // COMPILER2
813
814 // On new cpus instructions which update whole XMM register should be used
815 // to prevent partial register stall due to dependencies on high half.
816 //
817 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
818 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
819 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
820 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
821
822 if( is_amd() ) { // AMD cpus specific settings
823 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
824 // Use it on new AMD cpus starting from Opteron.
825 UseAddressNop = true;
826 }
827 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
828 // Use it on new AMD cpus starting from Opteron.
829 UseNewLongLShift = true;
830 }
831 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
832 if( supports_sse4a() ) {
833 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
834 } else {
835 UseXmmLoadAndClearUpper = false;
836 }
837 }
838 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
839 if( supports_sse4a() ) {
840 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
841 } else {
842 UseXmmRegToRegMoveAll = false;
843 }
844 }
845 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
846 if( supports_sse4a() ) {
847 UseXmmI2F = true;
848 } else {
849 UseXmmI2F = false;
850 }
851 }
852 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
853 if( supports_sse4a() ) {
854 UseXmmI2D = true;
855 } else {
856 UseXmmI2D = false;
857 }
858 }
859 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
860 if( supports_sse4_2() && UseSSE >= 4 ) {
861 UseSSE42Intrinsics = true;
862 }
863 }
864
865 // some defaults for AMD family 15h
866 if ( cpu_family() == 0x15 ) {
867 // On family 15h processors default is no sw prefetch
868 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
869 AllocatePrefetchStyle = 0;
870 }
871 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
872 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
873 AllocatePrefetchInstr = 3;
874 }
875 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
876 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
877 UseXMMForArrayCopy = true;
878 }
879 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
880 UseUnalignedLoadStores = true;
881 }
882 }
883
884 #ifdef COMPILER2
885 if (MaxVectorSize > 16) {
886 // Limit vectors size to 16 bytes on current AMD cpus.
887 FLAG_SET_DEFAULT(MaxVectorSize, 16);
888 }
889 #endif // COMPILER2
890 }
891
892 if( is_intel() ) { // Intel cpus specific settings
893 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
894 UseStoreImmI16 = false; // don't use it on Intel cpus
895 }
896 if( cpu_family() == 6 || cpu_family() == 15 ) {
897 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
898 // Use it on all Intel cpus starting from PentiumPro
899 UseAddressNop = true;
900 }
901 }
902 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
903 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
904 }
905 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
906 if( supports_sse3() ) {
907 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
908 } else {
909 UseXmmRegToRegMoveAll = false;
910 }
911 }
912 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
913 #ifdef COMPILER2
914 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
915 // For new Intel cpus do the next optimization:
916 // don't align the beginning of a loop if there are enough instructions
917 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
918 // in current fetch line (OptoLoopAlignment) or the padding
919 // is big (> MaxLoopPad).
920 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
921 // generated NOP instructions. 11 is the largest size of one
922 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
923 MaxLoopPad = 11;
924 }
925 #endif // COMPILER2
926 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
927 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
928 }
929 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
930 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
931 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
932 }
933 }
934 if (supports_sse4_2() && UseSSE >= 4) {
935 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
936 UseSSE42Intrinsics = true;
937 }
938 }
939 }
940 if ((cpu_family() == 0x06) &&
941 ((extended_cpu_model() == 0x36) || // Centerton
942 (extended_cpu_model() == 0x37) || // Silvermont
943 (extended_cpu_model() == 0x4D))) {
944 #ifdef COMPILER2
945 if (FLAG_IS_DEFAULT(OptoScheduling)) {
946 OptoScheduling = true;
947 }
948 #endif
949 if (supports_sse4_2()) { // Silvermont
950 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
951 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
952 }
953 }
954 }
955 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
956 AllocatePrefetchInstr = 3;
957 }
958 }
959
960 // Use count leading zeros count instruction if available.
961 if (supports_lzcnt()) {
962 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
963 UseCountLeadingZerosInstruction = true;
964 }
965 } else if (UseCountLeadingZerosInstruction) {
966 warning("lzcnt instruction is not available on this CPU");
967 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
968 }
969
970 // Use count trailing zeros instruction if available
971 if (supports_bmi1()) {
972 // tzcnt does not require VEX prefix
973 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
974 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
975 // Don't use tzcnt if BMI1 is switched off on command line.
976 UseCountTrailingZerosInstruction = false;
977 } else {
978 UseCountTrailingZerosInstruction = true;
979 }
980 }
981 } else if (UseCountTrailingZerosInstruction) {
982 warning("tzcnt instruction is not available on this CPU");
983 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
984 }
985
986 // BMI instructions (except tzcnt) use an encoding with VEX prefix.
987 // VEX prefix is generated only when AVX > 0.
988 if (supports_bmi1() && supports_avx()) {
989 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
990 UseBMI1Instructions = true;
991 }
992 } else if (UseBMI1Instructions) {
993 warning("BMI1 instructions are not available on this CPU (AVX is also required)");
994 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
995 }
996
997 if (supports_bmi2() && supports_avx()) {
998 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
999 UseBMI2Instructions = true;
1000 }
1001 } else if (UseBMI2Instructions) {
1002 warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1003 FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1004 }
1005
1006 // Use population count instruction if available.
1007 if (supports_popcnt()) {
1008 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1009 UsePopCountInstruction = true;
1010 }
1011 } else if (UsePopCountInstruction) {
1012 warning("POPCNT instruction is not available on this CPU");
1013 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1014 }
1015
1016 // Use fast-string operations if available.
1017 if (supports_erms()) {
1018 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1019 UseFastStosb = true;
1020 }
1021 } else if (UseFastStosb) {
1022 warning("fast-string operations are not available on this CPU");
1023 FLAG_SET_DEFAULT(UseFastStosb, false);
1024 }
1025
1026 #ifdef COMPILER2
1027 if (FLAG_IS_DEFAULT(AlignVector)) {
1028 // Modern processors allow misaligned memory operations for vectors.
1029 AlignVector = !UseUnalignedLoadStores;
1030 }
1031 #endif // COMPILER2
1032
1033 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
1034
1035 // set valid Prefetch instruction
1036 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
1037 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
1038 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
1039 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
1040
1041 // Allocation prefetch settings
1042 intx cache_line_size = prefetch_data_size();
1043 if( cache_line_size > AllocatePrefetchStepSize )
1044 AllocatePrefetchStepSize = cache_line_size;
1045
1046 assert(AllocatePrefetchLines > 0, "invalid value");
1047 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
1048 AllocatePrefetchLines = 3;
1049 assert(AllocateInstancePrefetchLines > 0, "invalid value");
1050 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
1051 AllocateInstancePrefetchLines = 1;
1052
1053 AllocatePrefetchDistance = allocate_prefetch_distance();
1054 AllocatePrefetchStyle = allocate_prefetch_style();
1055
1056 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1057 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
1058 #ifdef _LP64
1059 AllocatePrefetchDistance = 384;
1060 #else
1061 AllocatePrefetchDistance = 320;
1062 #endif
1063 }
1064 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1065 AllocatePrefetchDistance = 192;
1066 AllocatePrefetchLines = 4;
1067 }
1068 #ifdef COMPILER2
1069 if (supports_sse4_2()) {
1070 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1071 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1072 }
1073 }
1074 #endif
1075 }
1076 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
1077
1078 #ifdef _LP64
1079 // Prefetch settings
1080 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
1081 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
1082 PrefetchFieldsAhead = prefetch_fields_ahead();
1083 #endif
1084
1085 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1086 (cache_line_size > ContendedPaddingWidth))
1087 ContendedPaddingWidth = cache_line_size;
1088
1089 // This machine allows unaligned memory accesses
1090 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1091 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1092 }
1093
1094 #ifndef PRODUCT
1095 if (PrintMiscellaneous && Verbose) {
1096 tty->print_cr("Logical CPUs per core: %u",
1097 logical_processors_per_package());
1098 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1099 tty->print("UseSSE=%d", (int) UseSSE);
1100 if (UseAVX > 0) {
1101 tty->print(" UseAVX=%d", (int) UseAVX);
1102 }
1103 if (UseAES) {
1104 tty->print(" UseAES=1");
1105 }
1106 #ifdef COMPILER2
1107 if (MaxVectorSize > 0) {
1108 tty->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1109 }
1110 #endif
1111 tty->cr();
1112 tty->print("Allocation");
1113 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
1114 tty->print_cr(": no prefetching");
1115 } else {
1116 tty->print(" prefetching: ");
1117 if (UseSSE == 0 && supports_3dnow_prefetch()) {
1118 tty->print("PREFETCHW");
1119 } else if (UseSSE >= 1) {
1120 if (AllocatePrefetchInstr == 0) {
1121 tty->print("PREFETCHNTA");
1122 } else if (AllocatePrefetchInstr == 1) {
1123 tty->print("PREFETCHT0");
1124 } else if (AllocatePrefetchInstr == 2) {
1125 tty->print("PREFETCHT2");
1126 } else if (AllocatePrefetchInstr == 3) {
1127 tty->print("PREFETCHW");
1128 }
1129 }
1130 if (AllocatePrefetchLines > 1) {
1131 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1132 } else {
1133 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1134 }
1135 }
1136
1137 if (PrefetchCopyIntervalInBytes > 0) {
1138 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1139 }
1140 if (PrefetchScanIntervalInBytes > 0) {
1141 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1142 }
1143 if (PrefetchFieldsAhead > 0) {
1144 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1145 }
1146 if (ContendedPaddingWidth > 0) {
1147 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1148 }
1149 }
1150 #endif // !PRODUCT
1151 }
1152
1153 bool VM_Version::use_biased_locking() {
1154 #if INCLUDE_RTM_OPT
1155 // RTM locking is most useful when there is high lock contention and
1156 // low data contention. With high lock contention the lock is usually
1157 // inflated and biased locking is not suitable for that case.
1158 // RTM locking code requires that biased locking is off.
1159 // Note: we can't switch off UseBiasedLocking in get_processor_features()
1160 // because it is used by Thread::allocate() which is called before
1161 // VM_Version::initialize().
1162 if (UseRTMLocking && UseBiasedLocking) {
1163 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1164 FLAG_SET_DEFAULT(UseBiasedLocking, false);
1165 } else {
1166 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1167 UseBiasedLocking = false;
1168 }
1169 }
1170 #endif
1171 return UseBiasedLocking;
1172 }
1173
1174 void VM_Version::initialize() {
1175 ResourceMark rm;
1176 // Making this stub must be FIRST use of assembler
1177
1178 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1179 if (stub_blob == NULL) {
1180 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1181 }
1182 CodeBuffer c(stub_blob);
1183 VM_Version_StubGenerator g(&c);
1184 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1185 g.generate_get_cpu_info());
1186
1187 get_processor_features();
1188 }