1 //
2 // Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
492 ShouldNotReachHere();
493 }
494
495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
496 // Empty encoding
497 }
498
499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
500 return 0;
501 }
502
503 #ifndef PRODUCT
504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
505 st->print("# MachConstantBaseNode (empty encoding)");
506 }
507 #endif
508
509
510 //=============================================================================
511 #ifndef PRODUCT
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
513 Compile* C = ra_->C;
514
515 int framesize = C->frame_size_in_bytes();
516 int bangsize = C->bang_size_in_bytes();
517 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
518 // Remove wordSize for return addr which is already pushed.
519 framesize -= wordSize;
520
521 if (C->need_stack_bang(bangsize)) {
522 framesize -= wordSize;
523 st->print("# stack bang (%d bytes)", bangsize);
524 st->print("\n\t");
525 st->print("PUSH EBP\t# Save EBP");
526 if (framesize) {
527 st->print("\n\t");
528 st->print("SUB ESP, #%d\t# Create frame",framesize);
529 }
530 } else {
531 st->print("SUB ESP, #%d\t# Create frame",framesize);
532 st->print("\n\t");
533 framesize -= wordSize;
534 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
535 }
536
537 if (VerifyStackAtCalls) {
538 st->print("\n\t");
539 framesize -= wordSize;
540 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
541 }
542
543 if( C->in_24_bit_fp_mode() ) {
544 st->print("\n\t");
545 st->print("FLDCW \t# load 24 bit fpu control word");
546 }
547 if (UseSSE >= 2 && VerifyFPU) {
548 st->print("\n\t");
549 st->print("# verify FPU stack (must be clean on entry)");
550 }
551
552 #ifdef ASSERT
553 if (VerifyStackAtCalls) {
554 st->print("\n\t");
555 st->print("# stack alignment check");
556 }
557 #endif
558 st->cr();
559 }
560 #endif
561
562
563 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
564 Compile* C = ra_->C;
565 MacroAssembler _masm(&cbuf);
566
567 int framesize = C->frame_size_in_bytes();
568 int bangsize = C->bang_size_in_bytes();
569
570 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, C->in_24_bit_fp_mode());
571
572 C->set_frame_complete(cbuf.insts_size());
573
574 if (C->has_mach_constant_base_node()) {
575 // NOTE: We set the table base offset here because users might be
576 // emitted before MachConstantBaseNode.
577 Compile::ConstantTable& constant_table = C->constant_table();
578 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
579 }
580 }
581
582 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
583 return MachNode::size(ra_); // too many variables; just compute it the hard way
584 }
585
586 int MachPrologNode::reloc() const {
587 return 0; // a large enough number
588 }
589
590 //=============================================================================
591 #ifndef PRODUCT
592 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
593 Compile *C = ra_->C;
594 int framesize = C->frame_size_in_bytes();
595 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
596 // Remove two words for return addr and rbp,
597 framesize -= 2*wordSize;
598
599 if (C->max_vector_size() > 16) {
600 st->print("VZEROUPPER");
601 st->cr(); st->print("\t");
602 }
603 if (C->in_24_bit_fp_mode()) {
604 st->print("FLDCW standard control word");
605 st->cr(); st->print("\t");
606 }
607 if (framesize) {
608 st->print("ADD ESP,%d\t# Destroy frame",framesize);
609 st->cr(); st->print("\t");
610 }
611 st->print_cr("POPL EBP"); st->print("\t");
612 if (do_polling() && C->is_method_compilation()) {
613 st->print("TEST PollPage,EAX\t! Poll Safepoint");
614 st->cr(); st->print("\t");
615 }
616 }
617 #endif
618
619 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
620 Compile *C = ra_->C;
621
622 if (C->max_vector_size() > 16) {
623 // Clear upper bits of YMM registers when current compiled code uses
624 // wide vectors to avoid AVX <-> SSE transition penalty during call.
625 MacroAssembler masm(&cbuf);
626 masm.vzeroupper();
627 }
628 // If method set FPU control word, restore to standard control word
629 if (C->in_24_bit_fp_mode()) {
630 MacroAssembler masm(&cbuf);
631 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
632 }
633
634 int framesize = C->frame_size_in_bytes();
635 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
636 // Remove two words for return addr and rbp,
637 framesize -= 2*wordSize;
638
639 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
640
641 if (framesize >= 128) {
642 emit_opcode(cbuf, 0x81); // add SP, #framesize
643 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
644 emit_d32(cbuf, framesize);
645 } else if (framesize) {
646 emit_opcode(cbuf, 0x83); // add SP, #framesize
647 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
648 emit_d8(cbuf, framesize);
649 }
650
651 emit_opcode(cbuf, 0x58 | EBP_enc);
652
653 if (do_polling() && C->is_method_compilation()) {
654 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
655 emit_opcode(cbuf,0x85);
656 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
657 emit_d32(cbuf, (intptr_t)os::get_polling_page());
658 }
659 }
660
661 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
662 Compile *C = ra_->C;
663 // If method set FPU control word, restore to standard control word
664 int size = C->in_24_bit_fp_mode() ? 6 : 0;
665 if (C->max_vector_size() > 16) size += 3; // vzeroupper
666 if (do_polling() && C->is_method_compilation()) size += 6;
667
668 int framesize = C->frame_size_in_bytes();
669 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
670 // Remove two words for return addr and rbp,
671 framesize -= 2*wordSize;
672
673 size++; // popl rbp,
674
675 if (framesize >= 128) {
676 size += 6;
677 } else {
678 size += framesize ? 3 : 0;
679 }
680 return size;
681 }
682
683 int MachEpilogNode::reloc() const {
684 return 0; // a large enough number
685 }
686
687 const Pipeline * MachEpilogNode::pipeline() const {
688 return MachNode::pipeline_class();
689 }
690
691 int MachEpilogNode::safepoint_offset() const { return 0; }
692
693 //=============================================================================
694
695 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
696 static enum RC rc_class( OptoReg::Name reg ) {
697
698 if( !OptoReg::is_valid(reg) ) return rc_bad;
699 if (OptoReg::is_stack(reg)) return rc_stack;
700
701 VMReg r = OptoReg::as_VMReg(reg);
702 if (r->is_Register()) return rc_int;
703 if (r->is_FloatRegister()) {
704 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
705 return rc_float;
706 }
707 assert(r->is_XMMRegister(), "must be");
708 return rc_xmm;
709 }
710
711 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
712 int opcode, const char *op_str, int size, outputStream* st ) {
713 if( cbuf ) {
714 emit_opcode (*cbuf, opcode );
715 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
716 #ifndef PRODUCT
717 } else if( !do_size ) {
718 if( size != 0 ) st->print("\n\t");
719 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
720 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
721 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
722 } else { // FLD, FST, PUSH, POP
723 st->print("%s [ESP + #%d]",op_str,offset);
724 }
725 #endif
726 }
727 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
728 return size+3+offset_size;
729 }
730
731 // Helper for XMM registers. Extra opcode bits, limited syntax.
732 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
733 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
734 if (cbuf) {
735 MacroAssembler _masm(cbuf);
736 if (reg_lo+1 == reg_hi) { // double move?
737 if (is_load) {
738 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
739 } else {
740 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
741 }
742 } else {
743 if (is_load) {
744 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
745 } else {
746 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
747 }
748 }
749 #ifndef PRODUCT
750 } else if (!do_size) {
751 if (size != 0) st->print("\n\t");
752 if (reg_lo+1 == reg_hi) { // double move?
753 if (is_load) st->print("%s %s,[ESP + #%d]",
754 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
755 Matcher::regName[reg_lo], offset);
756 else st->print("MOVSD [ESP + #%d],%s",
757 offset, Matcher::regName[reg_lo]);
758 } else {
759 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
760 Matcher::regName[reg_lo], offset);
761 else st->print("MOVSS [ESP + #%d],%s",
762 offset, Matcher::regName[reg_lo]);
763 }
764 #endif
765 }
766 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
767 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
768 return size+5+offset_size;
769 }
770
771
772 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
773 int src_hi, int dst_hi, int size, outputStream* st ) {
774 if (cbuf) {
775 MacroAssembler _masm(cbuf);
776 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
777 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
778 as_XMMRegister(Matcher::_regEncode[src_lo]));
779 } else {
780 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
781 as_XMMRegister(Matcher::_regEncode[src_lo]));
782 }
783 #ifndef PRODUCT
784 } else if (!do_size) {
785 if (size != 0) st->print("\n\t");
786 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
787 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
788 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
789 } else {
790 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
791 }
792 } else {
793 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
794 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
795 } else {
796 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
797 }
798 }
799 #endif
800 }
801 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
802 // Only MOVAPS SSE prefix uses 1 byte.
803 int sz = 4;
804 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
805 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
806 return size + sz;
807 }
808
809 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
810 int src_hi, int dst_hi, int size, outputStream* st ) {
811 // 32-bit
812 if (cbuf) {
813 MacroAssembler _masm(cbuf);
814 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
815 as_Register(Matcher::_regEncode[src_lo]));
816 #ifndef PRODUCT
817 } else if (!do_size) {
818 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
819 #endif
820 }
821 return 4;
822 }
823
824
825 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
826 int src_hi, int dst_hi, int size, outputStream* st ) {
827 // 32-bit
828 if (cbuf) {
829 MacroAssembler _masm(cbuf);
830 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
831 as_XMMRegister(Matcher::_regEncode[src_lo]));
832 #ifndef PRODUCT
833 } else if (!do_size) {
834 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
835 #endif
836 }
837 return 4;
838 }
839
840 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
841 if( cbuf ) {
842 emit_opcode(*cbuf, 0x8B );
843 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
844 #ifndef PRODUCT
845 } else if( !do_size ) {
846 if( size != 0 ) st->print("\n\t");
847 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
848 #endif
849 }
850 return size+2;
851 }
852
853 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
854 int offset, int size, outputStream* st ) {
855 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
856 if( cbuf ) {
857 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
858 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
859 #ifndef PRODUCT
860 } else if( !do_size ) {
861 if( size != 0 ) st->print("\n\t");
862 st->print("FLD %s",Matcher::regName[src_lo]);
863 #endif
864 }
865 size += 2;
866 }
867
868 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
869 const char *op_str;
870 int op;
871 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
872 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
873 op = 0xDD;
874 } else { // 32-bit store
875 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
876 op = 0xD9;
877 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
878 }
879
880 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
881 }
882
883 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
884 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
885 int src_hi, int dst_hi, uint ireg, outputStream* st);
886
887 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
888 int stack_offset, int reg, uint ireg, outputStream* st);
889
890 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
891 int dst_offset, uint ireg, outputStream* st) {
892 int calc_size = 0;
893 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
894 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
895 switch (ireg) {
896 case Op_VecS:
897 calc_size = 3+src_offset_size + 3+dst_offset_size;
898 break;
899 case Op_VecD:
900 calc_size = 3+src_offset_size + 3+dst_offset_size;
901 src_offset += 4;
902 dst_offset += 4;
903 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
904 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
905 calc_size += 3+src_offset_size + 3+dst_offset_size;
906 break;
907 case Op_VecX:
908 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
909 break;
910 case Op_VecY:
911 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
912 break;
913 default:
914 ShouldNotReachHere();
915 }
916 if (cbuf) {
917 MacroAssembler _masm(cbuf);
918 int offset = __ offset();
919 switch (ireg) {
920 case Op_VecS:
921 __ pushl(Address(rsp, src_offset));
922 __ popl (Address(rsp, dst_offset));
923 break;
924 case Op_VecD:
925 __ pushl(Address(rsp, src_offset));
926 __ popl (Address(rsp, dst_offset));
927 __ pushl(Address(rsp, src_offset+4));
928 __ popl (Address(rsp, dst_offset+4));
929 break;
930 case Op_VecX:
931 __ movdqu(Address(rsp, -16), xmm0);
932 __ movdqu(xmm0, Address(rsp, src_offset));
933 __ movdqu(Address(rsp, dst_offset), xmm0);
934 __ movdqu(xmm0, Address(rsp, -16));
935 break;
936 case Op_VecY:
937 __ vmovdqu(Address(rsp, -32), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, src_offset));
939 __ vmovdqu(Address(rsp, dst_offset), xmm0);
940 __ vmovdqu(xmm0, Address(rsp, -32));
941 break;
942 default:
943 ShouldNotReachHere();
944 }
945 int size = __ offset() - offset;
946 assert(size == calc_size, "incorrect size calculattion");
947 return size;
948 #ifndef PRODUCT
949 } else if (!do_size) {
950 switch (ireg) {
951 case Op_VecS:
952 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
953 "popl [rsp + #%d]",
954 src_offset, dst_offset);
955 break;
956 case Op_VecD:
957 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
958 "popq [rsp + #%d]\n\t"
959 "pushl [rsp + #%d]\n\t"
960 "popq [rsp + #%d]",
961 src_offset, dst_offset, src_offset+4, dst_offset+4);
962 break;
963 case Op_VecX:
964 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
965 "movdqu xmm0, [rsp + #%d]\n\t"
966 "movdqu [rsp + #%d], xmm0\n\t"
967 "movdqu xmm0, [rsp - #16]",
968 src_offset, dst_offset);
969 break;
970 case Op_VecY:
971 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
972 "vmovdqu xmm0, [rsp + #%d]\n\t"
973 "vmovdqu [rsp + #%d], xmm0\n\t"
974 "vmovdqu xmm0, [rsp - #32]",
975 src_offset, dst_offset);
976 break;
977 default:
978 ShouldNotReachHere();
979 }
980 #endif
981 }
982 return calc_size;
983 }
984
985 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
986 // Get registers to move
987 OptoReg::Name src_second = ra_->get_reg_second(in(1));
988 OptoReg::Name src_first = ra_->get_reg_first(in(1));
989 OptoReg::Name dst_second = ra_->get_reg_second(this );
990 OptoReg::Name dst_first = ra_->get_reg_first(this );
991
992 enum RC src_second_rc = rc_class(src_second);
993 enum RC src_first_rc = rc_class(src_first);
994 enum RC dst_second_rc = rc_class(dst_second);
995 enum RC dst_first_rc = rc_class(dst_first);
996
997 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
998
999 // Generate spill code!
1000 int size = 0;
1001
1002 if( src_first == dst_first && src_second == dst_second )
1003 return size; // Self copy, no move
1004
1005 if (bottom_type()->isa_vect() != NULL) {
1006 uint ireg = ideal_reg();
1007 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1008 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1009 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1010 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1011 // mem -> mem
1012 int src_offset = ra_->reg2offset(src_first);
1013 int dst_offset = ra_->reg2offset(dst_first);
1014 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1016 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1017 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1018 int stack_offset = ra_->reg2offset(dst_first);
1019 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1020 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1021 int stack_offset = ra_->reg2offset(src_first);
1022 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1023 } else {
1024 ShouldNotReachHere();
1025 }
1026 }
1027
1028 // --------------------------------------
1029 // Check for mem-mem move. push/pop to move.
1030 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1031 if( src_second == dst_first ) { // overlapping stack copy ranges
1032 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1033 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1034 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1035 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1036 }
1037 // move low bits
1038 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1039 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1040 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1041 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1042 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1043 }
1044 return size;
1045 }
1046
1047 // --------------------------------------
1048 // Check for integer reg-reg copy
1049 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1050 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1051
1052 // Check for integer store
1053 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1054 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1055
1056 // Check for integer load
1057 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1058 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1059
1060 // Check for integer reg-xmm reg copy
1061 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1062 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1063 "no 64 bit integer-float reg moves" );
1064 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1065 }
1066 // --------------------------------------
1067 // Check for float reg-reg copy
1068 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1069 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1070 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1071 if( cbuf ) {
1072
1073 // Note the mucking with the register encode to compensate for the 0/1
1074 // indexing issue mentioned in a comment in the reg_def sections
1075 // for FPR registers many lines above here.
1076
1077 if( src_first != FPR1L_num ) {
1078 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1079 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1080 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1081 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1082 } else {
1083 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1084 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1085 }
1086 #ifndef PRODUCT
1087 } else if( !do_size ) {
1088 if( size != 0 ) st->print("\n\t");
1089 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1090 else st->print( "FST %s", Matcher::regName[dst_first]);
1091 #endif
1092 }
1093 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1094 }
1095
1096 // Check for float store
1097 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1098 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1099 }
1100
1101 // Check for float load
1102 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1103 int offset = ra_->reg2offset(src_first);
1104 const char *op_str;
1105 int op;
1106 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1107 op_str = "FLD_D";
1108 op = 0xDD;
1109 } else { // 32-bit load
1110 op_str = "FLD_S";
1111 op = 0xD9;
1112 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1113 }
1114 if( cbuf ) {
1115 emit_opcode (*cbuf, op );
1116 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1117 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1118 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1119 #ifndef PRODUCT
1120 } else if( !do_size ) {
1121 if( size != 0 ) st->print("\n\t");
1122 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1123 #endif
1124 }
1125 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1126 return size + 3+offset_size+2;
1127 }
1128
1129 // Check for xmm reg-reg copy
1130 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1131 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1132 (src_first+1 == src_second && dst_first+1 == dst_second),
1133 "no non-adjacent float-moves" );
1134 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1135 }
1136
1137 // Check for xmm reg-integer reg copy
1138 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1139 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1140 "no 64 bit float-integer reg moves" );
1141 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1142 }
1143
1144 // Check for xmm store
1145 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1146 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1147 }
1148
1149 // Check for float xmm load
1150 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1151 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1152 }
1153
1154 // Copy from float reg to xmm reg
1155 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1156 // copy to the top of stack from floating point reg
1157 // and use LEA to preserve flags
1158 if( cbuf ) {
1159 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1160 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1161 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1162 emit_d8(*cbuf,0xF8);
1163 #ifndef PRODUCT
1164 } else if( !do_size ) {
1165 if( size != 0 ) st->print("\n\t");
1166 st->print("LEA ESP,[ESP-8]");
1167 #endif
1168 }
1169 size += 4;
1170
1171 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1172
1173 // Copy from the temp memory to the xmm reg.
1174 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1175
1176 if( cbuf ) {
1177 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1178 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1179 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1180 emit_d8(*cbuf,0x08);
1181 #ifndef PRODUCT
1182 } else if( !do_size ) {
1183 if( size != 0 ) st->print("\n\t");
1184 st->print("LEA ESP,[ESP+8]");
1185 #endif
1186 }
1187 size += 4;
1188 return size;
1189 }
1190
1191 assert( size > 0, "missed a case" );
1192
1193 // --------------------------------------------------------------------
1194 // Check for second bits still needing moving.
1195 if( src_second == dst_second )
1196 return size; // Self copy; no move
1197 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1198
1199 // Check for second word int-int move
1200 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1201 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1202
1203 // Check for second word integer store
1204 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1205 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1206
1207 // Check for second word integer load
1208 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1209 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1210
1211
1212 Unimplemented();
1213 return 0; // Mute compiler
1214 }
1215
1216 #ifndef PRODUCT
1217 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1218 implementation( NULL, ra_, false, st );
1219 }
1220 #endif
1221
1222 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1223 implementation( &cbuf, ra_, false, NULL );
1224 }
1225
1226 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1227 return implementation( NULL, ra_, true, NULL );
1228 }
1229
1230
1231 //=============================================================================
1232 #ifndef PRODUCT
1233 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1235 int reg = ra_->get_reg_first(this);
1236 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1237 }
1238 #endif
1239
1240 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1241 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1242 int reg = ra_->get_encode(this);
1243 if( offset >= 128 ) {
1244 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1245 emit_rm(cbuf, 0x2, reg, 0x04);
1246 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1247 emit_d32(cbuf, offset);
1248 }
1249 else {
1250 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1251 emit_rm(cbuf, 0x1, reg, 0x04);
1252 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1253 emit_d8(cbuf, offset);
1254 }
1255 }
1256
1257 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1258 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1259 if( offset >= 128 ) {
1260 return 7;
1261 }
1262 else {
1263 return 4;
1264 }
1265 }
1266
1267 //=============================================================================
1268 #ifndef PRODUCT
1269 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1270 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1271 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1272 st->print_cr("\tNOP");
1273 st->print_cr("\tNOP");
1274 if( !OptoBreakpoint )
1275 st->print_cr("\tNOP");
1276 }
1277 #endif
1278
1279 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1280 MacroAssembler masm(&cbuf);
1281 #ifdef ASSERT
1282 uint insts_size = cbuf.insts_size();
1283 #endif
1284 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1285 masm.jump_cc(Assembler::notEqual,
1286 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1287 /* WARNING these NOPs are critical so that verified entry point is properly
1288 aligned for patching by NativeJump::patch_verified_entry() */
1289 int nops_cnt = 2;
1290 if( !OptoBreakpoint ) // Leave space for int3
1291 nops_cnt += 1;
1292 masm.nop(nops_cnt);
1293
1294 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1295 }
1296
1297 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1298 return OptoBreakpoint ? 11 : 12;
1299 }
1300
1301
1302 //=============================================================================
1303
1304 int Matcher::regnum_to_fpu_offset(int regnum) {
1305 return regnum - 32; // The FP registers are in the second chunk
1306 }
1307
1308 // This is UltraSparc specific, true just means we have fast l2f conversion
1309 const bool Matcher::convL2FSupported(void) {
1310 return true;
1311 }
1312
1313 // Is this branch offset short enough that a short branch can be used?
1314 //
1315 // NOTE: If the platform does not provide any short branch variants, then
1316 // this method should return false for offset 0.
1317 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1318 // The passed offset is relative to address of the branch.
1319 // On 86 a branch displacement is calculated relative to address
1320 // of a next instruction.
1321 offset -= br_size;
1322
1323 // the short version of jmpConUCF2 contains multiple branches,
1324 // making the reach slightly less
1325 if (rule == jmpConUCF2_rule)
1326 return (-126 <= offset && offset <= 125);
1327 return (-128 <= offset && offset <= 127);
1328 }
1329
1330 const bool Matcher::isSimpleConstant64(jlong value) {
1331 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1332 return false;
1333 }
1334
1335 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1336 const bool Matcher::init_array_count_is_in_bytes = false;
1337
1338 // Threshold size for cleararray.
1339 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1340
1341 // Needs 2 CMOV's for longs.
1342 const int Matcher::long_cmove_cost() { return 1; }
1343
1344 // No CMOVF/CMOVD with SSE/SSE2
1345 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1346
1347 // Does the CPU require late expand (see block.cpp for description of late expand)?
1348 const bool Matcher::require_postalloc_expand = false;
1349
1350 // Should the Matcher clone shifts on addressing modes, expecting them to
1351 // be subsumed into complex addressing expressions or compute them into
1352 // registers? True for Intel but false for most RISCs
1353 const bool Matcher::clone_shift_expressions = true;
1354
1355 // Do we need to mask the count passed to shift instructions or does
1356 // the cpu only look at the lower 5/6 bits anyway?
1357 const bool Matcher::need_masked_shift_count = false;
1358
1359 bool Matcher::narrow_oop_use_complex_address() {
1360 ShouldNotCallThis();
1361 return true;
1362 }
1363
1364 bool Matcher::narrow_klass_use_complex_address() {
1365 ShouldNotCallThis();
1366 return true;
1367 }
1368
1369
1370 // Is it better to copy float constants, or load them directly from memory?
1371 // Intel can load a float constant from a direct address, requiring no
1372 // extra registers. Most RISCs will have to materialize an address into a
1373 // register first, so they would do better to copy the constant from stack.
1374 const bool Matcher::rematerialize_float_constants = true;
1375
1376 // If CPU can load and store mis-aligned doubles directly then no fixup is
1377 // needed. Else we split the double into 2 integer pieces and move it
1378 // piece-by-piece. Only happens when passing doubles into C code as the
1379 // Java calling convention forces doubles to be aligned.
1380 const bool Matcher::misaligned_doubles_ok = true;
1381
1382
1383 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1384 // Get the memory operand from the node
1385 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1386 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1387 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1388 uint opcnt = 1; // First operand
1389 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1390 while( idx >= skipped+num_edges ) {
1391 skipped += num_edges;
1392 opcnt++; // Bump operand count
1393 assert( opcnt < numopnds, "Accessing non-existent operand" );
1394 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1395 }
1396
1397 MachOper *memory = node->_opnds[opcnt];
1398 MachOper *new_memory = NULL;
1399 switch (memory->opcode()) {
1400 case DIRECT:
1401 case INDOFFSET32X:
1402 // No transformation necessary.
1403 return;
1404 case INDIRECT:
1405 new_memory = new indirect_win95_safeOper( );
1406 break;
1407 case INDOFFSET8:
1408 new_memory = new indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1409 break;
1410 case INDOFFSET32:
1411 new_memory = new indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1412 break;
1413 case INDINDEXOFFSET:
1414 new_memory = new indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1415 break;
1416 case INDINDEXSCALE:
1417 new_memory = new indIndexScale_win95_safeOper(memory->scale());
1418 break;
1419 case INDINDEXSCALEOFFSET:
1420 new_memory = new indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1421 break;
1422 case LOAD_LONG_INDIRECT:
1423 case LOAD_LONG_INDOFFSET32:
1424 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1425 return;
1426 default:
1427 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1428 return;
1429 }
1430 node->_opnds[opcnt] = new_memory;
1431 }
1432
1433 // Advertise here if the CPU requires explicit rounding operations
1434 // to implement the UseStrictFP mode.
1435 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1436
1437 // Are floats conerted to double when stored to stack during deoptimization?
1438 // On x32 it is stored with convertion only when FPU is used for floats.
1439 bool Matcher::float_in_double() { return (UseSSE == 0); }
1440
1441 // Do ints take an entire long register or just half?
1442 const bool Matcher::int_in_long = false;
1443
1444 // Return whether or not this register is ever used as an argument. This
1445 // function is used on startup to build the trampoline stubs in generateOptoStub.
1446 // Registers not mentioned will be killed by the VM call in the trampoline, and
1447 // arguments in those registers not be available to the callee.
1448 bool Matcher::can_be_java_arg( int reg ) {
1449 if( reg == ECX_num || reg == EDX_num ) return true;
1450 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1451 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1452 return false;
1453 }
1454
1455 bool Matcher::is_spillable_arg( int reg ) {
1456 return can_be_java_arg(reg);
1457 }
1458
1459 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1460 // Use hardware integer DIV instruction when
1461 // it is faster than a code which use multiply.
1462 // Only when constant divisor fits into 32 bit
1463 // (min_jint is excluded to get only correct
1464 // positive 32 bit values from negative).
1465 return VM_Version::has_fast_idiv() &&
1466 (divisor == (int)divisor && divisor != min_jint);
1467 }
1468
1469 // Register for DIVI projection of divmodI
1470 RegMask Matcher::divI_proj_mask() {
1471 return EAX_REG_mask();
1472 }
1473
1474 // Register for MODI projection of divmodI
1475 RegMask Matcher::modI_proj_mask() {
1476 return EDX_REG_mask();
1477 }
1478
1479 // Register for DIVL projection of divmodL
1480 RegMask Matcher::divL_proj_mask() {
1481 ShouldNotReachHere();
1482 return RegMask();
1483 }
1484
1485 // Register for MODL projection of divmodL
1486 RegMask Matcher::modL_proj_mask() {
1487 ShouldNotReachHere();
1488 return RegMask();
1489 }
1490
1491 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1492 return EBP_REG_mask();
1493 }
1494
1495 // Returns true if the high 32 bits of the value is known to be zero.
1496 bool is_operand_hi32_zero(Node* n) {
1497 int opc = n->Opcode();
1498 if (opc == Op_AndL) {
1499 Node* o2 = n->in(2);
1500 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1501 return true;
1502 }
1503 }
1504 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1505 return true;
1506 }
1507 return false;
1508 }
1509
1510 %}
1511
1512 //----------ENCODING BLOCK-----------------------------------------------------
1513 // This block specifies the encoding classes used by the compiler to output
1514 // byte streams. Encoding classes generate functions which are called by
1515 // Machine Instruction Nodes in order to generate the bit encoding of the
1516 // instruction. Operands specify their base encoding interface with the
1517 // interface keyword. There are currently supported four interfaces,
1518 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1519 // operand to generate a function which returns its register number when
1520 // queried. CONST_INTER causes an operand to generate a function which
1521 // returns the value of the constant when queried. MEMORY_INTER causes an
1522 // operand to generate four functions which return the Base Register, the
1523 // Index Register, the Scale Value, and the Offset Value of the operand when
1524 // queried. COND_INTER causes an operand to generate six functions which
1525 // return the encoding code (ie - encoding bits for the instruction)
1526 // associated with each basic boolean condition for a conditional instruction.
1527 // Instructions specify two basic values for encoding. They use the
1528 // ins_encode keyword to specify their encoding class (which must be one of
1529 // the class names specified in the encoding block), and they use the
1530 // opcode keyword to specify, in order, their primary, secondary, and
1531 // tertiary opcode. Only the opcode sections which a particular instruction
1532 // needs for encoding need to be specified.
1533 encode %{
1534 // Build emit functions for each basic byte or larger field in the intel
1535 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1536 // code in the enc_class source block. Emit functions will live in the
1537 // main source block for now. In future, we can generalize this by
1538 // adding a syntax that specifies the sizes of fields in an order,
1539 // so that the adlc can build the emit functions automagically
1540
1541 // Emit primary opcode
1542 enc_class OpcP %{
1543 emit_opcode(cbuf, $primary);
1544 %}
1545
1546 // Emit secondary opcode
1547 enc_class OpcS %{
1548 emit_opcode(cbuf, $secondary);
1549 %}
1550
1551 // Emit opcode directly
1552 enc_class Opcode(immI d8) %{
1553 emit_opcode(cbuf, $d8$$constant);
1554 %}
1555
1556 enc_class SizePrefix %{
1557 emit_opcode(cbuf,0x66);
1558 %}
1559
1560 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1561 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1562 %}
1563
1564 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1565 emit_opcode(cbuf,$opcode$$constant);
1566 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1567 %}
1568
1569 enc_class mov_r32_imm0( rRegI dst ) %{
1570 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1571 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1572 %}
1573
1574 enc_class cdq_enc %{
1575 // Full implementation of Java idiv and irem; checks for
1576 // special case as described in JVM spec., p.243 & p.271.
1577 //
1578 // normal case special case
1579 //
1580 // input : rax,: dividend min_int
1581 // reg: divisor -1
1582 //
1583 // output: rax,: quotient (= rax, idiv reg) min_int
1584 // rdx: remainder (= rax, irem reg) 0
1585 //
1586 // Code sequnce:
1587 //
1588 // 81 F8 00 00 00 80 cmp rax,80000000h
1589 // 0F 85 0B 00 00 00 jne normal_case
1590 // 33 D2 xor rdx,edx
1591 // 83 F9 FF cmp rcx,0FFh
1592 // 0F 84 03 00 00 00 je done
1593 // normal_case:
1594 // 99 cdq
1595 // F7 F9 idiv rax,ecx
1596 // done:
1597 //
1598 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1599 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1600 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1601 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1602 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1603 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1604 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1605 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1606 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1607 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1608 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1609 // normal_case:
1610 emit_opcode(cbuf,0x99); // cdq
1611 // idiv (note: must be emitted by the user of this rule)
1612 // normal:
1613 %}
1614
1615 // Dense encoding for older common ops
1616 enc_class Opc_plus(immI opcode, rRegI reg) %{
1617 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1618 %}
1619
1620
1621 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1622 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1623 // Check for 8-bit immediate, and set sign extend bit in opcode
1624 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1625 emit_opcode(cbuf, $primary | 0x02);
1626 }
1627 else { // If 32-bit immediate
1628 emit_opcode(cbuf, $primary);
1629 }
1630 %}
1631
1632 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1633 // Emit primary opcode and set sign-extend bit
1634 // Check for 8-bit immediate, and set sign extend bit in opcode
1635 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1636 emit_opcode(cbuf, $primary | 0x02); }
1637 else { // If 32-bit immediate
1638 emit_opcode(cbuf, $primary);
1639 }
1640 // Emit r/m byte with secondary opcode, after primary opcode.
1641 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1642 %}
1643
1644 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1645 // Check for 8-bit immediate, and set sign extend bit in opcode
1646 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1647 $$$emit8$imm$$constant;
1648 }
1649 else { // If 32-bit immediate
1650 // Output immediate
1651 $$$emit32$imm$$constant;
1652 }
1653 %}
1654
1655 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1656 // Emit primary opcode and set sign-extend bit
1657 // Check for 8-bit immediate, and set sign extend bit in opcode
1658 int con = (int)$imm$$constant; // Throw away top bits
1659 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1660 // Emit r/m byte with secondary opcode, after primary opcode.
1661 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1662 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1663 else emit_d32(cbuf,con);
1664 %}
1665
1666 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1667 // Emit primary opcode and set sign-extend bit
1668 // Check for 8-bit immediate, and set sign extend bit in opcode
1669 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1670 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1671 // Emit r/m byte with tertiary opcode, after primary opcode.
1672 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1673 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1674 else emit_d32(cbuf,con);
1675 %}
1676
1677 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1678 emit_cc(cbuf, $secondary, $dst$$reg );
1679 %}
1680
1681 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1682 int destlo = $dst$$reg;
1683 int desthi = HIGH_FROM_LOW(destlo);
1684 // bswap lo
1685 emit_opcode(cbuf, 0x0F);
1686 emit_cc(cbuf, 0xC8, destlo);
1687 // bswap hi
1688 emit_opcode(cbuf, 0x0F);
1689 emit_cc(cbuf, 0xC8, desthi);
1690 // xchg lo and hi
1691 emit_opcode(cbuf, 0x87);
1692 emit_rm(cbuf, 0x3, destlo, desthi);
1693 %}
1694
1695 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1696 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1697 %}
1698
1699 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1700 $$$emit8$primary;
1701 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1702 %}
1703
1704 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1705 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1706 emit_d8(cbuf, op >> 8 );
1707 emit_d8(cbuf, op & 255);
1708 %}
1709
1710 // emulate a CMOV with a conditional branch around a MOV
1711 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1712 // Invert sense of branch from sense of CMOV
1713 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1714 emit_d8( cbuf, $brOffs$$constant );
1715 %}
1716
1717 enc_class enc_PartialSubtypeCheck( ) %{
1718 Register Redi = as_Register(EDI_enc); // result register
1719 Register Reax = as_Register(EAX_enc); // super class
1720 Register Recx = as_Register(ECX_enc); // killed
1721 Register Resi = as_Register(ESI_enc); // sub class
1722 Label miss;
1723
1724 MacroAssembler _masm(&cbuf);
1725 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1726 NULL, &miss,
1727 /*set_cond_codes:*/ true);
1728 if ($primary) {
1729 __ xorptr(Redi, Redi);
1730 }
1731 __ bind(miss);
1732 %}
1733
1734 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1735 MacroAssembler masm(&cbuf);
1736 int start = masm.offset();
1737 if (UseSSE >= 2) {
1738 if (VerifyFPU) {
1739 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1740 }
1741 } else {
1742 // External c_calling_convention expects the FPU stack to be 'clean'.
1743 // Compiled code leaves it dirty. Do cleanup now.
1744 masm.empty_FPU_stack();
1745 }
1746 if (sizeof_FFree_Float_Stack_All == -1) {
1747 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1748 } else {
1749 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1750 }
1751 %}
1752
1753 enc_class Verify_FPU_For_Leaf %{
1754 if( VerifyFPU ) {
1755 MacroAssembler masm(&cbuf);
1756 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1757 }
1758 %}
1759
1760 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1761 // This is the instruction starting address for relocation info.
1762 cbuf.set_insts_mark();
1763 $$$emit8$primary;
1764 // CALL directly to the runtime
1765 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1766 runtime_call_Relocation::spec(), RELOC_IMM32 );
1767
1768 if (UseSSE >= 2) {
1769 MacroAssembler _masm(&cbuf);
1770 BasicType rt = tf()->return_type();
1771
1772 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1773 // A C runtime call where the return value is unused. In SSE2+
1774 // mode the result needs to be removed from the FPU stack. It's
1775 // likely that this function call could be removed by the
1776 // optimizer if the C function is a pure function.
1777 __ ffree(0);
1778 } else if (rt == T_FLOAT) {
1779 __ lea(rsp, Address(rsp, -4));
1780 __ fstp_s(Address(rsp, 0));
1781 __ movflt(xmm0, Address(rsp, 0));
1782 __ lea(rsp, Address(rsp, 4));
1783 } else if (rt == T_DOUBLE) {
1784 __ lea(rsp, Address(rsp, -8));
1785 __ fstp_d(Address(rsp, 0));
1786 __ movdbl(xmm0, Address(rsp, 0));
1787 __ lea(rsp, Address(rsp, 8));
1788 }
1789 }
1790 %}
1791
1792
1793 enc_class pre_call_resets %{
1794 // If method sets FPU control word restore it here
1795 debug_only(int off0 = cbuf.insts_size());
1796 if (ra_->C->in_24_bit_fp_mode()) {
1797 MacroAssembler _masm(&cbuf);
1798 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1799 }
1800 if (ra_->C->max_vector_size() > 16) {
1801 // Clear upper bits of YMM registers when current compiled code uses
1802 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1803 MacroAssembler _masm(&cbuf);
1804 __ vzeroupper();
1805 }
1806 debug_only(int off1 = cbuf.insts_size());
1807 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1808 %}
1809
1810 enc_class post_call_FPU %{
1811 // If method sets FPU control word do it here also
1812 if (Compile::current()->in_24_bit_fp_mode()) {
1813 MacroAssembler masm(&cbuf);
1814 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1815 }
1816 %}
1817
1818 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1819 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1820 // who we intended to call.
1821 cbuf.set_insts_mark();
1822 $$$emit8$primary;
1823 if (!_method) {
1824 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1825 runtime_call_Relocation::spec(), RELOC_IMM32 );
1826 } else if (_optimized_virtual) {
1827 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1828 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1829 } else {
1830 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1831 static_call_Relocation::spec(), RELOC_IMM32 );
1832 }
1833 if (_method) { // Emit stub for static call.
1834 CompiledStaticCall::emit_to_interp_stub(cbuf);
1835 }
1836 %}
1837
1838 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1839 MacroAssembler _masm(&cbuf);
1840 __ ic_call((address)$meth$$method);
1841 %}
1842
1843 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1844 int disp = in_bytes(Method::from_compiled_offset());
1845 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1846
1847 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1848 cbuf.set_insts_mark();
1849 $$$emit8$primary;
1850 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1851 emit_d8(cbuf, disp); // Displacement
1852
1853 %}
1854
1855 // Following encoding is no longer used, but may be restored if calling
1856 // convention changes significantly.
1857 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1858 //
1859 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1860 // // int ic_reg = Matcher::inline_cache_reg();
1861 // // int ic_encode = Matcher::_regEncode[ic_reg];
1862 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1863 // // int imo_encode = Matcher::_regEncode[imo_reg];
1864 //
1865 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1866 // // // so we load it immediately before the call
1867 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1868 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1869 //
1870 // // xor rbp,ebp
1871 // emit_opcode(cbuf, 0x33);
1872 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1873 //
1874 // // CALL to interpreter.
1875 // cbuf.set_insts_mark();
1876 // $$$emit8$primary;
1877 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1878 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1879 // %}
1880
1881 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1882 $$$emit8$primary;
1883 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1884 $$$emit8$shift$$constant;
1885 %}
1886
1887 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1888 // Load immediate does not have a zero or sign extended version
1889 // for 8-bit immediates
1890 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1891 $$$emit32$src$$constant;
1892 %}
1893
1894 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1895 // Load immediate does not have a zero or sign extended version
1896 // for 8-bit immediates
1897 emit_opcode(cbuf, $primary + $dst$$reg);
1898 $$$emit32$src$$constant;
1899 %}
1900
1901 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1902 // Load immediate does not have a zero or sign extended version
1903 // for 8-bit immediates
1904 int dst_enc = $dst$$reg;
1905 int src_con = $src$$constant & 0x0FFFFFFFFL;
1906 if (src_con == 0) {
1907 // xor dst, dst
1908 emit_opcode(cbuf, 0x33);
1909 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1910 } else {
1911 emit_opcode(cbuf, $primary + dst_enc);
1912 emit_d32(cbuf, src_con);
1913 }
1914 %}
1915
1916 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1917 // Load immediate does not have a zero or sign extended version
1918 // for 8-bit immediates
1919 int dst_enc = $dst$$reg + 2;
1920 int src_con = ((julong)($src$$constant)) >> 32;
1921 if (src_con == 0) {
1922 // xor dst, dst
1923 emit_opcode(cbuf, 0x33);
1924 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1925 } else {
1926 emit_opcode(cbuf, $primary + dst_enc);
1927 emit_d32(cbuf, src_con);
1928 }
1929 %}
1930
1931
1932 // Encode a reg-reg copy. If it is useless, then empty encoding.
1933 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1934 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1935 %}
1936
1937 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1938 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1939 %}
1940
1941 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1942 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1943 %}
1944
1945 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1946 $$$emit8$primary;
1947 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1948 %}
1949
1950 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
1951 $$$emit8$secondary;
1952 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1953 %}
1954
1955 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
1956 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1957 %}
1958
1959 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
1960 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1961 %}
1962
1963 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
1964 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
1965 %}
1966
1967 enc_class Con32 (immI src) %{ // Con32(storeImmI)
1968 // Output immediate
1969 $$$emit32$src$$constant;
1970 %}
1971
1972 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
1973 // Output Float immediate bits
1974 jfloat jf = $src$$constant;
1975 int jf_as_bits = jint_cast( jf );
1976 emit_d32(cbuf, jf_as_bits);
1977 %}
1978
1979 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
1980 // Output Float immediate bits
1981 jfloat jf = $src$$constant;
1982 int jf_as_bits = jint_cast( jf );
1983 emit_d32(cbuf, jf_as_bits);
1984 %}
1985
1986 enc_class Con16 (immI src) %{ // Con16(storeImmI)
1987 // Output immediate
1988 $$$emit16$src$$constant;
1989 %}
1990
1991 enc_class Con_d32(immI src) %{
1992 emit_d32(cbuf,$src$$constant);
1993 %}
1994
1995 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
1996 // Output immediate memory reference
1997 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
1998 emit_d32(cbuf, 0x00);
1999 %}
2000
2001 enc_class lock_prefix( ) %{
2002 if( os::is_MP() )
2003 emit_opcode(cbuf,0xF0); // [Lock]
2004 %}
2005
2006 // Cmp-xchg long value.
2007 // Note: we need to swap rbx, and rcx before and after the
2008 // cmpxchg8 instruction because the instruction uses
2009 // rcx as the high order word of the new value to store but
2010 // our register encoding uses rbx,.
2011 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2012
2013 // XCHG rbx,ecx
2014 emit_opcode(cbuf,0x87);
2015 emit_opcode(cbuf,0xD9);
2016 // [Lock]
2017 if( os::is_MP() )
2018 emit_opcode(cbuf,0xF0);
2019 // CMPXCHG8 [Eptr]
2020 emit_opcode(cbuf,0x0F);
2021 emit_opcode(cbuf,0xC7);
2022 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2023 // XCHG rbx,ecx
2024 emit_opcode(cbuf,0x87);
2025 emit_opcode(cbuf,0xD9);
2026 %}
2027
2028 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2029 // [Lock]
2030 if( os::is_MP() )
2031 emit_opcode(cbuf,0xF0);
2032
2033 // CMPXCHG [Eptr]
2034 emit_opcode(cbuf,0x0F);
2035 emit_opcode(cbuf,0xB1);
2036 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2037 %}
2038
2039 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2040 int res_encoding = $res$$reg;
2041
2042 // MOV res,0
2043 emit_opcode( cbuf, 0xB8 + res_encoding);
2044 emit_d32( cbuf, 0 );
2045 // JNE,s fail
2046 emit_opcode(cbuf,0x75);
2047 emit_d8(cbuf, 5 );
2048 // MOV res,1
2049 emit_opcode( cbuf, 0xB8 + res_encoding);
2050 emit_d32( cbuf, 1 );
2051 // fail:
2052 %}
2053
2054 enc_class set_instruction_start( ) %{
2055 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2056 %}
2057
2058 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2059 int reg_encoding = $ereg$$reg;
2060 int base = $mem$$base;
2061 int index = $mem$$index;
2062 int scale = $mem$$scale;
2063 int displace = $mem$$disp;
2064 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2065 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2066 %}
2067
2068 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2069 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2070 int base = $mem$$base;
2071 int index = $mem$$index;
2072 int scale = $mem$$scale;
2073 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2074 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2075 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2076 %}
2077
2078 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2079 int r1, r2;
2080 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2081 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2082 emit_opcode(cbuf,0x0F);
2083 emit_opcode(cbuf,$tertiary);
2084 emit_rm(cbuf, 0x3, r1, r2);
2085 emit_d8(cbuf,$cnt$$constant);
2086 emit_d8(cbuf,$primary);
2087 emit_rm(cbuf, 0x3, $secondary, r1);
2088 emit_d8(cbuf,$cnt$$constant);
2089 %}
2090
2091 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2092 emit_opcode( cbuf, 0x8B ); // Move
2093 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2094 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2095 emit_d8(cbuf,$primary);
2096 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2097 emit_d8(cbuf,$cnt$$constant-32);
2098 }
2099 emit_d8(cbuf,$primary);
2100 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2101 emit_d8(cbuf,31);
2102 %}
2103
2104 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2105 int r1, r2;
2106 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2107 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2108
2109 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2110 emit_rm(cbuf, 0x3, r1, r2);
2111 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2112 emit_opcode(cbuf,$primary);
2113 emit_rm(cbuf, 0x3, $secondary, r1);
2114 emit_d8(cbuf,$cnt$$constant-32);
2115 }
2116 emit_opcode(cbuf,0x33); // XOR r2,r2
2117 emit_rm(cbuf, 0x3, r2, r2);
2118 %}
2119
2120 // Clone of RegMem but accepts an extra parameter to access each
2121 // half of a double in memory; it never needs relocation info.
2122 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2123 emit_opcode(cbuf,$opcode$$constant);
2124 int reg_encoding = $rm_reg$$reg;
2125 int base = $mem$$base;
2126 int index = $mem$$index;
2127 int scale = $mem$$scale;
2128 int displace = $mem$$disp + $disp_for_half$$constant;
2129 relocInfo::relocType disp_reloc = relocInfo::none;
2130 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2131 %}
2132
2133 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2134 //
2135 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2136 // and it never needs relocation information.
2137 // Frequently used to move data between FPU's Stack Top and memory.
2138 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2139 int rm_byte_opcode = $rm_opcode$$constant;
2140 int base = $mem$$base;
2141 int index = $mem$$index;
2142 int scale = $mem$$scale;
2143 int displace = $mem$$disp;
2144 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2145 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2146 %}
2147
2148 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2149 int rm_byte_opcode = $rm_opcode$$constant;
2150 int base = $mem$$base;
2151 int index = $mem$$index;
2152 int scale = $mem$$scale;
2153 int displace = $mem$$disp;
2154 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2155 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2156 %}
2157
2158 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2159 int reg_encoding = $dst$$reg;
2160 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2161 int index = 0x04; // 0x04 indicates no index
2162 int scale = 0x00; // 0x00 indicates no scale
2163 int displace = $src1$$constant; // 0x00 indicates no displacement
2164 relocInfo::relocType disp_reloc = relocInfo::none;
2165 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2166 %}
2167
2168 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2169 // Compare dst,src
2170 emit_opcode(cbuf,0x3B);
2171 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2172 // jmp dst < src around move
2173 emit_opcode(cbuf,0x7C);
2174 emit_d8(cbuf,2);
2175 // move dst,src
2176 emit_opcode(cbuf,0x8B);
2177 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2178 %}
2179
2180 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2181 // Compare dst,src
2182 emit_opcode(cbuf,0x3B);
2183 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2184 // jmp dst > src around move
2185 emit_opcode(cbuf,0x7F);
2186 emit_d8(cbuf,2);
2187 // move dst,src
2188 emit_opcode(cbuf,0x8B);
2189 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2190 %}
2191
2192 enc_class enc_FPR_store(memory mem, regDPR src) %{
2193 // If src is FPR1, we can just FST to store it.
2194 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2195 int reg_encoding = 0x2; // Just store
2196 int base = $mem$$base;
2197 int index = $mem$$index;
2198 int scale = $mem$$scale;
2199 int displace = $mem$$disp;
2200 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2201 if( $src$$reg != FPR1L_enc ) {
2202 reg_encoding = 0x3; // Store & pop
2203 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2204 emit_d8( cbuf, 0xC0-1+$src$$reg );
2205 }
2206 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2207 emit_opcode(cbuf,$primary);
2208 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2209 %}
2210
2211 enc_class neg_reg(rRegI dst) %{
2212 // NEG $dst
2213 emit_opcode(cbuf,0xF7);
2214 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2215 %}
2216
2217 enc_class setLT_reg(eCXRegI dst) %{
2218 // SETLT $dst
2219 emit_opcode(cbuf,0x0F);
2220 emit_opcode(cbuf,0x9C);
2221 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2222 %}
2223
2224 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2225 int tmpReg = $tmp$$reg;
2226
2227 // SUB $p,$q
2228 emit_opcode(cbuf,0x2B);
2229 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2230 // SBB $tmp,$tmp
2231 emit_opcode(cbuf,0x1B);
2232 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2233 // AND $tmp,$y
2234 emit_opcode(cbuf,0x23);
2235 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2236 // ADD $p,$tmp
2237 emit_opcode(cbuf,0x03);
2238 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2239 %}
2240
2241 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2242 // TEST shift,32
2243 emit_opcode(cbuf,0xF7);
2244 emit_rm(cbuf, 0x3, 0, ECX_enc);
2245 emit_d32(cbuf,0x20);
2246 // JEQ,s small
2247 emit_opcode(cbuf, 0x74);
2248 emit_d8(cbuf, 0x04);
2249 // MOV $dst.hi,$dst.lo
2250 emit_opcode( cbuf, 0x8B );
2251 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2252 // CLR $dst.lo
2253 emit_opcode(cbuf, 0x33);
2254 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2255 // small:
2256 // SHLD $dst.hi,$dst.lo,$shift
2257 emit_opcode(cbuf,0x0F);
2258 emit_opcode(cbuf,0xA5);
2259 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2260 // SHL $dst.lo,$shift"
2261 emit_opcode(cbuf,0xD3);
2262 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2263 %}
2264
2265 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2266 // TEST shift,32
2267 emit_opcode(cbuf,0xF7);
2268 emit_rm(cbuf, 0x3, 0, ECX_enc);
2269 emit_d32(cbuf,0x20);
2270 // JEQ,s small
2271 emit_opcode(cbuf, 0x74);
2272 emit_d8(cbuf, 0x04);
2273 // MOV $dst.lo,$dst.hi
2274 emit_opcode( cbuf, 0x8B );
2275 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2276 // CLR $dst.hi
2277 emit_opcode(cbuf, 0x33);
2278 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2279 // small:
2280 // SHRD $dst.lo,$dst.hi,$shift
2281 emit_opcode(cbuf,0x0F);
2282 emit_opcode(cbuf,0xAD);
2283 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2284 // SHR $dst.hi,$shift"
2285 emit_opcode(cbuf,0xD3);
2286 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2287 %}
2288
2289 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2290 // TEST shift,32
2291 emit_opcode(cbuf,0xF7);
2292 emit_rm(cbuf, 0x3, 0, ECX_enc);
2293 emit_d32(cbuf,0x20);
2294 // JEQ,s small
2295 emit_opcode(cbuf, 0x74);
2296 emit_d8(cbuf, 0x05);
2297 // MOV $dst.lo,$dst.hi
2298 emit_opcode( cbuf, 0x8B );
2299 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2300 // SAR $dst.hi,31
2301 emit_opcode(cbuf, 0xC1);
2302 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2303 emit_d8(cbuf, 0x1F );
2304 // small:
2305 // SHRD $dst.lo,$dst.hi,$shift
2306 emit_opcode(cbuf,0x0F);
2307 emit_opcode(cbuf,0xAD);
2308 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2309 // SAR $dst.hi,$shift"
2310 emit_opcode(cbuf,0xD3);
2311 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2312 %}
2313
2314
2315 // ----------------- Encodings for floating point unit -----------------
2316 // May leave result in FPU-TOS or FPU reg depending on opcodes
2317 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2318 $$$emit8$primary;
2319 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2320 %}
2321
2322 // Pop argument in FPR0 with FSTP ST(0)
2323 enc_class PopFPU() %{
2324 emit_opcode( cbuf, 0xDD );
2325 emit_d8( cbuf, 0xD8 );
2326 %}
2327
2328 // !!!!! equivalent to Pop_Reg_F
2329 enc_class Pop_Reg_DPR( regDPR dst ) %{
2330 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2331 emit_d8( cbuf, 0xD8+$dst$$reg );
2332 %}
2333
2334 enc_class Push_Reg_DPR( regDPR dst ) %{
2335 emit_opcode( cbuf, 0xD9 );
2336 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2337 %}
2338
2339 enc_class strictfp_bias1( regDPR dst ) %{
2340 emit_opcode( cbuf, 0xDB ); // FLD m80real
2341 emit_opcode( cbuf, 0x2D );
2342 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2343 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2344 emit_opcode( cbuf, 0xC8+$dst$$reg );
2345 %}
2346
2347 enc_class strictfp_bias2( regDPR dst ) %{
2348 emit_opcode( cbuf, 0xDB ); // FLD m80real
2349 emit_opcode( cbuf, 0x2D );
2350 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2351 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2352 emit_opcode( cbuf, 0xC8+$dst$$reg );
2353 %}
2354
2355 // Special case for moving an integer register to a stack slot.
2356 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2357 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2358 %}
2359
2360 // Special case for moving a register to a stack slot.
2361 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2362 // Opcode already emitted
2363 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2365 emit_d32(cbuf, $dst$$disp); // Displacement
2366 %}
2367
2368 // Push the integer in stackSlot 'src' onto FP-stack
2369 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2370 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2371 %}
2372
2373 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2374 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2375 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2376 %}
2377
2378 // Same as Pop_Mem_F except for opcode
2379 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2380 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2381 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2382 %}
2383
2384 enc_class Pop_Reg_FPR( regFPR dst ) %{
2385 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2386 emit_d8( cbuf, 0xD8+$dst$$reg );
2387 %}
2388
2389 enc_class Push_Reg_FPR( regFPR dst ) %{
2390 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2391 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2392 %}
2393
2394 // Push FPU's float to a stack-slot, and pop FPU-stack
2395 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2396 int pop = 0x02;
2397 if ($src$$reg != FPR1L_enc) {
2398 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2399 emit_d8( cbuf, 0xC0-1+$src$$reg );
2400 pop = 0x03;
2401 }
2402 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2403 %}
2404
2405 // Push FPU's double to a stack-slot, and pop FPU-stack
2406 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2407 int pop = 0x02;
2408 if ($src$$reg != FPR1L_enc) {
2409 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2410 emit_d8( cbuf, 0xC0-1+$src$$reg );
2411 pop = 0x03;
2412 }
2413 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2414 %}
2415
2416 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2417 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2418 int pop = 0xD0 - 1; // -1 since we skip FLD
2419 if ($src$$reg != FPR1L_enc) {
2420 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2421 emit_d8( cbuf, 0xC0-1+$src$$reg );
2422 pop = 0xD8;
2423 }
2424 emit_opcode( cbuf, 0xDD );
2425 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2426 %}
2427
2428
2429 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2430 // load dst in FPR0
2431 emit_opcode( cbuf, 0xD9 );
2432 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2433 if ($src$$reg != FPR1L_enc) {
2434 // fincstp
2435 emit_opcode (cbuf, 0xD9);
2436 emit_opcode (cbuf, 0xF7);
2437 // swap src with FPR1:
2438 // FXCH FPR1 with src
2439 emit_opcode(cbuf, 0xD9);
2440 emit_d8(cbuf, 0xC8-1+$src$$reg );
2441 // fdecstp
2442 emit_opcode (cbuf, 0xD9);
2443 emit_opcode (cbuf, 0xF6);
2444 }
2445 %}
2446
2447 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2448 MacroAssembler _masm(&cbuf);
2449 __ subptr(rsp, 8);
2450 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2451 __ fld_d(Address(rsp, 0));
2452 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2453 __ fld_d(Address(rsp, 0));
2454 %}
2455
2456 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2457 MacroAssembler _masm(&cbuf);
2458 __ subptr(rsp, 4);
2459 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2460 __ fld_s(Address(rsp, 0));
2461 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2462 __ fld_s(Address(rsp, 0));
2463 %}
2464
2465 enc_class Push_ResultD(regD dst) %{
2466 MacroAssembler _masm(&cbuf);
2467 __ fstp_d(Address(rsp, 0));
2468 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2469 __ addptr(rsp, 8);
2470 %}
2471
2472 enc_class Push_ResultF(regF dst, immI d8) %{
2473 MacroAssembler _masm(&cbuf);
2474 __ fstp_s(Address(rsp, 0));
2475 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2476 __ addptr(rsp, $d8$$constant);
2477 %}
2478
2479 enc_class Push_SrcD(regD src) %{
2480 MacroAssembler _masm(&cbuf);
2481 __ subptr(rsp, 8);
2482 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2483 __ fld_d(Address(rsp, 0));
2484 %}
2485
2486 enc_class push_stack_temp_qword() %{
2487 MacroAssembler _masm(&cbuf);
2488 __ subptr(rsp, 8);
2489 %}
2490
2491 enc_class pop_stack_temp_qword() %{
2492 MacroAssembler _masm(&cbuf);
2493 __ addptr(rsp, 8);
2494 %}
2495
2496 enc_class push_xmm_to_fpr1(regD src) %{
2497 MacroAssembler _masm(&cbuf);
2498 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2499 __ fld_d(Address(rsp, 0));
2500 %}
2501
2502 enc_class Push_Result_Mod_DPR( regDPR src) %{
2503 if ($src$$reg != FPR1L_enc) {
2504 // fincstp
2505 emit_opcode (cbuf, 0xD9);
2506 emit_opcode (cbuf, 0xF7);
2507 // FXCH FPR1 with src
2508 emit_opcode(cbuf, 0xD9);
2509 emit_d8(cbuf, 0xC8-1+$src$$reg );
2510 // fdecstp
2511 emit_opcode (cbuf, 0xD9);
2512 emit_opcode (cbuf, 0xF6);
2513 }
2514 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2515 // // FSTP FPR$dst$$reg
2516 // emit_opcode( cbuf, 0xDD );
2517 // emit_d8( cbuf, 0xD8+$dst$$reg );
2518 %}
2519
2520 enc_class fnstsw_sahf_skip_parity() %{
2521 // fnstsw ax
2522 emit_opcode( cbuf, 0xDF );
2523 emit_opcode( cbuf, 0xE0 );
2524 // sahf
2525 emit_opcode( cbuf, 0x9E );
2526 // jnp ::skip
2527 emit_opcode( cbuf, 0x7B );
2528 emit_opcode( cbuf, 0x05 );
2529 %}
2530
2531 enc_class emitModDPR() %{
2532 // fprem must be iterative
2533 // :: loop
2534 // fprem
2535 emit_opcode( cbuf, 0xD9 );
2536 emit_opcode( cbuf, 0xF8 );
2537 // wait
2538 emit_opcode( cbuf, 0x9b );
2539 // fnstsw ax
2540 emit_opcode( cbuf, 0xDF );
2541 emit_opcode( cbuf, 0xE0 );
2542 // sahf
2543 emit_opcode( cbuf, 0x9E );
2544 // jp ::loop
2545 emit_opcode( cbuf, 0x0F );
2546 emit_opcode( cbuf, 0x8A );
2547 emit_opcode( cbuf, 0xF4 );
2548 emit_opcode( cbuf, 0xFF );
2549 emit_opcode( cbuf, 0xFF );
2550 emit_opcode( cbuf, 0xFF );
2551 %}
2552
2553 enc_class fpu_flags() %{
2554 // fnstsw_ax
2555 emit_opcode( cbuf, 0xDF);
2556 emit_opcode( cbuf, 0xE0);
2557 // test ax,0x0400
2558 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2559 emit_opcode( cbuf, 0xA9 );
2560 emit_d16 ( cbuf, 0x0400 );
2561 // // // This sequence works, but stalls for 12-16 cycles on PPro
2562 // // test rax,0x0400
2563 // emit_opcode( cbuf, 0xA9 );
2564 // emit_d32 ( cbuf, 0x00000400 );
2565 //
2566 // jz exit (no unordered comparison)
2567 emit_opcode( cbuf, 0x74 );
2568 emit_d8 ( cbuf, 0x02 );
2569 // mov ah,1 - treat as LT case (set carry flag)
2570 emit_opcode( cbuf, 0xB4 );
2571 emit_d8 ( cbuf, 0x01 );
2572 // sahf
2573 emit_opcode( cbuf, 0x9E);
2574 %}
2575
2576 enc_class cmpF_P6_fixup() %{
2577 // Fixup the integer flags in case comparison involved a NaN
2578 //
2579 // JNP exit (no unordered comparison, P-flag is set by NaN)
2580 emit_opcode( cbuf, 0x7B );
2581 emit_d8 ( cbuf, 0x03 );
2582 // MOV AH,1 - treat as LT case (set carry flag)
2583 emit_opcode( cbuf, 0xB4 );
2584 emit_d8 ( cbuf, 0x01 );
2585 // SAHF
2586 emit_opcode( cbuf, 0x9E);
2587 // NOP // target for branch to avoid branch to branch
2588 emit_opcode( cbuf, 0x90);
2589 %}
2590
2591 // fnstsw_ax();
2592 // sahf();
2593 // movl(dst, nan_result);
2594 // jcc(Assembler::parity, exit);
2595 // movl(dst, less_result);
2596 // jcc(Assembler::below, exit);
2597 // movl(dst, equal_result);
2598 // jcc(Assembler::equal, exit);
2599 // movl(dst, greater_result);
2600
2601 // less_result = 1;
2602 // greater_result = -1;
2603 // equal_result = 0;
2604 // nan_result = -1;
2605
2606 enc_class CmpF_Result(rRegI dst) %{
2607 // fnstsw_ax();
2608 emit_opcode( cbuf, 0xDF);
2609 emit_opcode( cbuf, 0xE0);
2610 // sahf
2611 emit_opcode( cbuf, 0x9E);
2612 // movl(dst, nan_result);
2613 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2614 emit_d32( cbuf, -1 );
2615 // jcc(Assembler::parity, exit);
2616 emit_opcode( cbuf, 0x7A );
2617 emit_d8 ( cbuf, 0x13 );
2618 // movl(dst, less_result);
2619 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2620 emit_d32( cbuf, -1 );
2621 // jcc(Assembler::below, exit);
2622 emit_opcode( cbuf, 0x72 );
2623 emit_d8 ( cbuf, 0x0C );
2624 // movl(dst, equal_result);
2625 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2626 emit_d32( cbuf, 0 );
2627 // jcc(Assembler::equal, exit);
2628 emit_opcode( cbuf, 0x74 );
2629 emit_d8 ( cbuf, 0x05 );
2630 // movl(dst, greater_result);
2631 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2632 emit_d32( cbuf, 1 );
2633 %}
2634
2635
2636 // Compare the longs and set flags
2637 // BROKEN! Do Not use as-is
2638 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2639 // CMP $src1.hi,$src2.hi
2640 emit_opcode( cbuf, 0x3B );
2641 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2642 // JNE,s done
2643 emit_opcode(cbuf,0x75);
2644 emit_d8(cbuf, 2 );
2645 // CMP $src1.lo,$src2.lo
2646 emit_opcode( cbuf, 0x3B );
2647 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2648 // done:
2649 %}
2650
2651 enc_class convert_int_long( regL dst, rRegI src ) %{
2652 // mov $dst.lo,$src
2653 int dst_encoding = $dst$$reg;
2654 int src_encoding = $src$$reg;
2655 encode_Copy( cbuf, dst_encoding , src_encoding );
2656 // mov $dst.hi,$src
2657 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2658 // sar $dst.hi,31
2659 emit_opcode( cbuf, 0xC1 );
2660 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2661 emit_d8(cbuf, 0x1F );
2662 %}
2663
2664 enc_class convert_long_double( eRegL src ) %{
2665 // push $src.hi
2666 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2667 // push $src.lo
2668 emit_opcode(cbuf, 0x50+$src$$reg );
2669 // fild 64-bits at [SP]
2670 emit_opcode(cbuf,0xdf);
2671 emit_d8(cbuf, 0x6C);
2672 emit_d8(cbuf, 0x24);
2673 emit_d8(cbuf, 0x00);
2674 // pop stack
2675 emit_opcode(cbuf, 0x83); // add SP, #8
2676 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2677 emit_d8(cbuf, 0x8);
2678 %}
2679
2680 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2681 // IMUL EDX:EAX,$src1
2682 emit_opcode( cbuf, 0xF7 );
2683 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2684 // SAR EDX,$cnt-32
2685 int shift_count = ((int)$cnt$$constant) - 32;
2686 if (shift_count > 0) {
2687 emit_opcode(cbuf, 0xC1);
2688 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2689 emit_d8(cbuf, shift_count);
2690 }
2691 %}
2692
2693 // this version doesn't have add sp, 8
2694 enc_class convert_long_double2( eRegL src ) %{
2695 // push $src.hi
2696 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2697 // push $src.lo
2698 emit_opcode(cbuf, 0x50+$src$$reg );
2699 // fild 64-bits at [SP]
2700 emit_opcode(cbuf,0xdf);
2701 emit_d8(cbuf, 0x6C);
2702 emit_d8(cbuf, 0x24);
2703 emit_d8(cbuf, 0x00);
2704 %}
2705
2706 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2707 // Basic idea: long = (long)int * (long)int
2708 // IMUL EDX:EAX, src
2709 emit_opcode( cbuf, 0xF7 );
2710 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2711 %}
2712
2713 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2714 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2715 // MUL EDX:EAX, src
2716 emit_opcode( cbuf, 0xF7 );
2717 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2718 %}
2719
2720 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2721 // Basic idea: lo(result) = lo(x_lo * y_lo)
2722 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2723 // MOV $tmp,$src.lo
2724 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2725 // IMUL $tmp,EDX
2726 emit_opcode( cbuf, 0x0F );
2727 emit_opcode( cbuf, 0xAF );
2728 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2729 // MOV EDX,$src.hi
2730 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2731 // IMUL EDX,EAX
2732 emit_opcode( cbuf, 0x0F );
2733 emit_opcode( cbuf, 0xAF );
2734 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2735 // ADD $tmp,EDX
2736 emit_opcode( cbuf, 0x03 );
2737 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2738 // MUL EDX:EAX,$src.lo
2739 emit_opcode( cbuf, 0xF7 );
2740 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2741 // ADD EDX,ESI
2742 emit_opcode( cbuf, 0x03 );
2743 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2744 %}
2745
2746 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2747 // Basic idea: lo(result) = lo(src * y_lo)
2748 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2749 // IMUL $tmp,EDX,$src
2750 emit_opcode( cbuf, 0x6B );
2751 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2752 emit_d8( cbuf, (int)$src$$constant );
2753 // MOV EDX,$src
2754 emit_opcode(cbuf, 0xB8 + EDX_enc);
2755 emit_d32( cbuf, (int)$src$$constant );
2756 // MUL EDX:EAX,EDX
2757 emit_opcode( cbuf, 0xF7 );
2758 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2759 // ADD EDX,ESI
2760 emit_opcode( cbuf, 0x03 );
2761 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2762 %}
2763
2764 enc_class long_div( eRegL src1, eRegL src2 ) %{
2765 // PUSH src1.hi
2766 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2767 // PUSH src1.lo
2768 emit_opcode(cbuf, 0x50+$src1$$reg );
2769 // PUSH src2.hi
2770 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2771 // PUSH src2.lo
2772 emit_opcode(cbuf, 0x50+$src2$$reg );
2773 // CALL directly to the runtime
2774 cbuf.set_insts_mark();
2775 emit_opcode(cbuf,0xE8); // Call into runtime
2776 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2777 // Restore stack
2778 emit_opcode(cbuf, 0x83); // add SP, #framesize
2779 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2780 emit_d8(cbuf, 4*4);
2781 %}
2782
2783 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2784 // PUSH src1.hi
2785 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2786 // PUSH src1.lo
2787 emit_opcode(cbuf, 0x50+$src1$$reg );
2788 // PUSH src2.hi
2789 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2790 // PUSH src2.lo
2791 emit_opcode(cbuf, 0x50+$src2$$reg );
2792 // CALL directly to the runtime
2793 cbuf.set_insts_mark();
2794 emit_opcode(cbuf,0xE8); // Call into runtime
2795 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2796 // Restore stack
2797 emit_opcode(cbuf, 0x83); // add SP, #framesize
2798 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2799 emit_d8(cbuf, 4*4);
2800 %}
2801
2802 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2803 // MOV $tmp,$src.lo
2804 emit_opcode(cbuf, 0x8B);
2805 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2806 // OR $tmp,$src.hi
2807 emit_opcode(cbuf, 0x0B);
2808 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2809 %}
2810
2811 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2812 // CMP $src1.lo,$src2.lo
2813 emit_opcode( cbuf, 0x3B );
2814 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2815 // JNE,s skip
2816 emit_cc(cbuf, 0x70, 0x5);
2817 emit_d8(cbuf,2);
2818 // CMP $src1.hi,$src2.hi
2819 emit_opcode( cbuf, 0x3B );
2820 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2821 %}
2822
2823 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2824 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2825 emit_opcode( cbuf, 0x3B );
2826 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2827 // MOV $tmp,$src1.hi
2828 emit_opcode( cbuf, 0x8B );
2829 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2830 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2831 emit_opcode( cbuf, 0x1B );
2832 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2833 %}
2834
2835 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2836 // XOR $tmp,$tmp
2837 emit_opcode(cbuf,0x33); // XOR
2838 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2839 // CMP $tmp,$src.lo
2840 emit_opcode( cbuf, 0x3B );
2841 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2842 // SBB $tmp,$src.hi
2843 emit_opcode( cbuf, 0x1B );
2844 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2845 %}
2846
2847 // Sniff, sniff... smells like Gnu Superoptimizer
2848 enc_class neg_long( eRegL dst ) %{
2849 emit_opcode(cbuf,0xF7); // NEG hi
2850 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2851 emit_opcode(cbuf,0xF7); // NEG lo
2852 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2853 emit_opcode(cbuf,0x83); // SBB hi,0
2854 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2855 emit_d8 (cbuf,0 );
2856 %}
2857
2858 enc_class enc_pop_rdx() %{
2859 emit_opcode(cbuf,0x5A);
2860 %}
2861
2862 enc_class enc_rethrow() %{
2863 cbuf.set_insts_mark();
2864 emit_opcode(cbuf, 0xE9); // jmp entry
2865 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
2866 runtime_call_Relocation::spec(), RELOC_IMM32 );
2867 %}
2868
2869
2870 // Convert a double to an int. Java semantics require we do complex
2871 // manglelations in the corner cases. So we set the rounding mode to
2872 // 'zero', store the darned double down as an int, and reset the
2873 // rounding mode to 'nearest'. The hardware throws an exception which
2874 // patches up the correct value directly to the stack.
2875 enc_class DPR2I_encoding( regDPR src ) %{
2876 // Flip to round-to-zero mode. We attempted to allow invalid-op
2877 // exceptions here, so that a NAN or other corner-case value will
2878 // thrown an exception (but normal values get converted at full speed).
2879 // However, I2C adapters and other float-stack manglers leave pending
2880 // invalid-op exceptions hanging. We would have to clear them before
2881 // enabling them and that is more expensive than just testing for the
2882 // invalid value Intel stores down in the corner cases.
2883 emit_opcode(cbuf,0xD9); // FLDCW trunc
2884 emit_opcode(cbuf,0x2D);
2885 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2886 // Allocate a word
2887 emit_opcode(cbuf,0x83); // SUB ESP,4
2888 emit_opcode(cbuf,0xEC);
2889 emit_d8(cbuf,0x04);
2890 // Encoding assumes a double has been pushed into FPR0.
2891 // Store down the double as an int, popping the FPU stack
2892 emit_opcode(cbuf,0xDB); // FISTP [ESP]
2893 emit_opcode(cbuf,0x1C);
2894 emit_d8(cbuf,0x24);
2895 // Restore the rounding mode; mask the exception
2896 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2897 emit_opcode(cbuf,0x2D);
2898 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2899 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2900 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2901
2902 // Load the converted int; adjust CPU stack
2903 emit_opcode(cbuf,0x58); // POP EAX
2904 emit_opcode(cbuf,0x3D); // CMP EAX,imm
2905 emit_d32 (cbuf,0x80000000); // 0x80000000
2906 emit_opcode(cbuf,0x75); // JNE around_slow_call
2907 emit_d8 (cbuf,0x07); // Size of slow_call
2908 // Push src onto stack slow-path
2909 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
2910 emit_d8 (cbuf,0xC0-1+$src$$reg );
2911 // CALL directly to the runtime
2912 cbuf.set_insts_mark();
2913 emit_opcode(cbuf,0xE8); // Call into runtime
2914 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2915 // Carry on here...
2916 %}
2917
2918 enc_class DPR2L_encoding( regDPR src ) %{
2919 emit_opcode(cbuf,0xD9); // FLDCW trunc
2920 emit_opcode(cbuf,0x2D);
2921 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2922 // Allocate a word
2923 emit_opcode(cbuf,0x83); // SUB ESP,8
2924 emit_opcode(cbuf,0xEC);
2925 emit_d8(cbuf,0x08);
2926 // Encoding assumes a double has been pushed into FPR0.
2927 // Store down the double as a long, popping the FPU stack
2928 emit_opcode(cbuf,0xDF); // FISTP [ESP]
2929 emit_opcode(cbuf,0x3C);
2930 emit_d8(cbuf,0x24);
2931 // Restore the rounding mode; mask the exception
2932 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2933 emit_opcode(cbuf,0x2D);
2934 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2935 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2936 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2937
2938 // Load the converted int; adjust CPU stack
2939 emit_opcode(cbuf,0x58); // POP EAX
2940 emit_opcode(cbuf,0x5A); // POP EDX
2941 emit_opcode(cbuf,0x81); // CMP EDX,imm
2942 emit_d8 (cbuf,0xFA); // rdx
2943 emit_d32 (cbuf,0x80000000); // 0x80000000
2944 emit_opcode(cbuf,0x75); // JNE around_slow_call
2945 emit_d8 (cbuf,0x07+4); // Size of slow_call
2946 emit_opcode(cbuf,0x85); // TEST EAX,EAX
2947 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
2948 emit_opcode(cbuf,0x75); // JNE around_slow_call
2949 emit_d8 (cbuf,0x07); // Size of slow_call
2950 // Push src onto stack slow-path
2951 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
2952 emit_d8 (cbuf,0xC0-1+$src$$reg );
2953 // CALL directly to the runtime
2954 cbuf.set_insts_mark();
2955 emit_opcode(cbuf,0xE8); // Call into runtime
2956 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2957 // Carry on here...
2958 %}
2959
2960 enc_class FMul_ST_reg( eRegFPR src1 ) %{
2961 // Operand was loaded from memory into fp ST (stack top)
2962 // FMUL ST,$src /* D8 C8+i */
2963 emit_opcode(cbuf, 0xD8);
2964 emit_opcode(cbuf, 0xC8 + $src1$$reg);
2965 %}
2966
2967 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
2968 // FADDP ST,src2 /* D8 C0+i */
2969 emit_opcode(cbuf, 0xD8);
2970 emit_opcode(cbuf, 0xC0 + $src2$$reg);
2971 //could use FADDP src2,fpST /* DE C0+i */
2972 %}
2973
2974 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
2975 // FADDP src2,ST /* DE C0+i */
2976 emit_opcode(cbuf, 0xDE);
2977 emit_opcode(cbuf, 0xC0 + $src2$$reg);
2978 %}
2979
2980 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
2981 // Operand has been loaded into fp ST (stack top)
2982 // FSUB ST,$src1
2983 emit_opcode(cbuf, 0xD8);
2984 emit_opcode(cbuf, 0xE0 + $src1$$reg);
2985
2986 // FDIV
2987 emit_opcode(cbuf, 0xD8);
2988 emit_opcode(cbuf, 0xF0 + $src2$$reg);
2989 %}
2990
2991 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
2992 // Operand was loaded from memory into fp ST (stack top)
2993 // FADD ST,$src /* D8 C0+i */
2994 emit_opcode(cbuf, 0xD8);
2995 emit_opcode(cbuf, 0xC0 + $src1$$reg);
2996
2997 // FMUL ST,src2 /* D8 C*+i */
2998 emit_opcode(cbuf, 0xD8);
2999 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3000 %}
3001
3002
3003 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3004 // Operand was loaded from memory into fp ST (stack top)
3005 // FADD ST,$src /* D8 C0+i */
3006 emit_opcode(cbuf, 0xD8);
3007 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3008
3009 // FMULP src2,ST /* DE C8+i */
3010 emit_opcode(cbuf, 0xDE);
3011 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3012 %}
3013
3014 // Atomically load the volatile long
3015 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3016 emit_opcode(cbuf,0xDF);
3017 int rm_byte_opcode = 0x05;
3018 int base = $mem$$base;
3019 int index = $mem$$index;
3020 int scale = $mem$$scale;
3021 int displace = $mem$$disp;
3022 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3023 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3024 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3025 %}
3026
3027 // Volatile Store Long. Must be atomic, so move it into
3028 // the FP TOS and then do a 64-bit FIST. Has to probe the
3029 // target address before the store (for null-ptr checks)
3030 // so the memory operand is used twice in the encoding.
3031 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3032 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3033 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3034 emit_opcode(cbuf,0xDF);
3035 int rm_byte_opcode = 0x07;
3036 int base = $mem$$base;
3037 int index = $mem$$index;
3038 int scale = $mem$$scale;
3039 int displace = $mem$$disp;
3040 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3041 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3042 %}
3043
3044 // Safepoint Poll. This polls the safepoint page, and causes an
3045 // exception if it is not readable. Unfortunately, it kills the condition code
3046 // in the process
3047 // We current use TESTL [spp],EDI
3048 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3049
3050 enc_class Safepoint_Poll() %{
3051 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3052 emit_opcode(cbuf,0x85);
3053 emit_rm (cbuf, 0x0, 0x7, 0x5);
3054 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3055 %}
3056 %}
3057
3058
3059 //----------FRAME--------------------------------------------------------------
3060 // Definition of frame structure and management information.
3061 //
3062 // S T A C K L A Y O U T Allocators stack-slot number
3063 // | (to get allocators register number
3064 // G Owned by | | v add OptoReg::stack0())
3065 // r CALLER | |
3066 // o | +--------+ pad to even-align allocators stack-slot
3067 // w V | pad0 | numbers; owned by CALLER
3068 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3069 // h ^ | in | 5
3070 // | | args | 4 Holes in incoming args owned by SELF
3071 // | | | | 3
3072 // | | +--------+
3073 // V | | old out| Empty on Intel, window on Sparc
3074 // | old |preserve| Must be even aligned.
3075 // | SP-+--------+----> Matcher::_old_SP, even aligned
3076 // | | in | 3 area for Intel ret address
3077 // Owned by |preserve| Empty on Sparc.
3078 // SELF +--------+
3079 // | | pad2 | 2 pad to align old SP
3080 // | +--------+ 1
3081 // | | locks | 0
3082 // | +--------+----> OptoReg::stack0(), even aligned
3083 // | | pad1 | 11 pad to align new SP
3084 // | +--------+
3085 // | | | 10
3086 // | | spills | 9 spills
3087 // V | | 8 (pad0 slot for callee)
3088 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3089 // ^ | out | 7
3090 // | | args | 6 Holes in outgoing args owned by CALLEE
3091 // Owned by +--------+
3092 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3093 // | new |preserve| Must be even-aligned.
3094 // | SP-+--------+----> Matcher::_new_SP, even aligned
3095 // | | |
3096 //
3097 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3098 // known from SELF's arguments and the Java calling convention.
3099 // Region 6-7 is determined per call site.
3100 // Note 2: If the calling convention leaves holes in the incoming argument
3101 // area, those holes are owned by SELF. Holes in the outgoing area
3102 // are owned by the CALLEE. Holes should not be nessecary in the
3103 // incoming area, as the Java calling convention is completely under
3104 // the control of the AD file. Doubles can be sorted and packed to
3105 // avoid holes. Holes in the outgoing arguments may be nessecary for
3106 // varargs C calling conventions.
3107 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3108 // even aligned with pad0 as needed.
3109 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3110 // region 6-11 is even aligned; it may be padded out more so that
3111 // the region from SP to FP meets the minimum stack alignment.
3112
3113 frame %{
3114 // What direction does stack grow in (assumed to be same for C & Java)
3115 stack_direction(TOWARDS_LOW);
3116
3117 // These three registers define part of the calling convention
3118 // between compiled code and the interpreter.
3119 inline_cache_reg(EAX); // Inline Cache Register
3120 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3121
3122 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3123 cisc_spilling_operand_name(indOffset32);
3124
3125 // Number of stack slots consumed by locking an object
3126 sync_stack_slots(1);
3127
3128 // Compiled code's Frame Pointer
3129 frame_pointer(ESP);
3130 // Interpreter stores its frame pointer in a register which is
3131 // stored to the stack by I2CAdaptors.
3132 // I2CAdaptors convert from interpreted java to compiled java.
3133 interpreter_frame_pointer(EBP);
3134
3135 // Stack alignment requirement
3136 // Alignment size in bytes (128-bit -> 16 bytes)
3137 stack_alignment(StackAlignmentInBytes);
3138
3139 // Number of stack slots between incoming argument block and the start of
3140 // a new frame. The PROLOG must add this many slots to the stack. The
3141 // EPILOG must remove this many slots. Intel needs one slot for
3142 // return address and one for rbp, (must save rbp)
3143 in_preserve_stack_slots(2+VerifyStackAtCalls);
3144
3145 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3146 // for calls to C. Supports the var-args backing area for register parms.
3147 varargs_C_out_slots_killed(0);
3148
3149 // The after-PROLOG location of the return address. Location of
3150 // return address specifies a type (REG or STACK) and a number
3151 // representing the register number (i.e. - use a register name) or
3152 // stack slot.
3153 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3154 // Otherwise, it is above the locks and verification slot and alignment word
3155 return_addr(STACK - 1 +
3156 round_to((Compile::current()->in_preserve_stack_slots() +
3157 Compile::current()->fixed_slots()),
3158 stack_alignment_in_slots()));
3159
3160 // Body of function which returns an integer array locating
3161 // arguments either in registers or in stack slots. Passed an array
3162 // of ideal registers called "sig" and a "length" count. Stack-slot
3163 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3164 // arguments for a CALLEE. Incoming stack arguments are
3165 // automatically biased by the preserve_stack_slots field above.
3166 calling_convention %{
3167 // No difference between ingoing/outgoing just pass false
3168 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3169 %}
3170
3171
3172 // Body of function which returns an integer array locating
3173 // arguments either in registers or in stack slots. Passed an array
3174 // of ideal registers called "sig" and a "length" count. Stack-slot
3175 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3176 // arguments for a CALLEE. Incoming stack arguments are
3177 // automatically biased by the preserve_stack_slots field above.
3178 c_calling_convention %{
3179 // This is obviously always outgoing
3180 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3181 %}
3182
3183 // Location of C & interpreter return values
3184 c_return_value %{
3185 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3186 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3187 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3188
3189 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3190 // that C functions return float and double results in XMM0.
3191 if( ideal_reg == Op_RegD && UseSSE>=2 )
3192 return OptoRegPair(XMM0b_num,XMM0_num);
3193 if( ideal_reg == Op_RegF && UseSSE>=2 )
3194 return OptoRegPair(OptoReg::Bad,XMM0_num);
3195
3196 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3197 %}
3198
3199 // Location of return values
3200 return_value %{
3201 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3202 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3203 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3204 if( ideal_reg == Op_RegD && UseSSE>=2 )
3205 return OptoRegPair(XMM0b_num,XMM0_num);
3206 if( ideal_reg == Op_RegF && UseSSE>=1 )
3207 return OptoRegPair(OptoReg::Bad,XMM0_num);
3208 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3209 %}
3210
3211 %}
3212
3213 //----------ATTRIBUTES---------------------------------------------------------
3214 //----------Operand Attributes-------------------------------------------------
3215 op_attrib op_cost(0); // Required cost attribute
3216
3217 //----------Instruction Attributes---------------------------------------------
3218 ins_attrib ins_cost(100); // Required cost attribute
3219 ins_attrib ins_size(8); // Required size attribute (in bits)
3220 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3221 // non-matching short branch variant of some
3222 // long branch?
3223 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3224 // specifies the alignment that some part of the instruction (not
3225 // necessarily the start) requires. If > 1, a compute_padding()
3226 // function must be provided for the instruction
3227
3228 //----------OPERANDS-----------------------------------------------------------
3229 // Operand definitions must precede instruction definitions for correct parsing
3230 // in the ADLC because operands constitute user defined types which are used in
3231 // instruction definitions.
3232
3233 //----------Simple Operands----------------------------------------------------
3234 // Immediate Operands
3235 // Integer Immediate
3236 operand immI() %{
3237 match(ConI);
3238
3239 op_cost(10);
3240 format %{ %}
3241 interface(CONST_INTER);
3242 %}
3243
3244 // Constant for test vs zero
3245 operand immI0() %{
3246 predicate(n->get_int() == 0);
3247 match(ConI);
3248
3249 op_cost(0);
3250 format %{ %}
3251 interface(CONST_INTER);
3252 %}
3253
3254 // Constant for increment
3255 operand immI1() %{
3256 predicate(n->get_int() == 1);
3257 match(ConI);
3258
3259 op_cost(0);
3260 format %{ %}
3261 interface(CONST_INTER);
3262 %}
3263
3264 // Constant for decrement
3265 operand immI_M1() %{
3266 predicate(n->get_int() == -1);
3267 match(ConI);
3268
3269 op_cost(0);
3270 format %{ %}
3271 interface(CONST_INTER);
3272 %}
3273
3274 // Valid scale values for addressing modes
3275 operand immI2() %{
3276 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3277 match(ConI);
3278
3279 format %{ %}
3280 interface(CONST_INTER);
3281 %}
3282
3283 operand immI8() %{
3284 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3285 match(ConI);
3286
3287 op_cost(5);
3288 format %{ %}
3289 interface(CONST_INTER);
3290 %}
3291
3292 operand immI16() %{
3293 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3294 match(ConI);
3295
3296 op_cost(10);
3297 format %{ %}
3298 interface(CONST_INTER);
3299 %}
3300
3301 // Int Immediate non-negative
3302 operand immU31()
3303 %{
3304 predicate(n->get_int() >= 0);
3305 match(ConI);
3306
3307 op_cost(0);
3308 format %{ %}
3309 interface(CONST_INTER);
3310 %}
3311
3312 // Constant for long shifts
3313 operand immI_32() %{
3314 predicate( n->get_int() == 32 );
3315 match(ConI);
3316
3317 op_cost(0);
3318 format %{ %}
3319 interface(CONST_INTER);
3320 %}
3321
3322 operand immI_1_31() %{
3323 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3324 match(ConI);
3325
3326 op_cost(0);
3327 format %{ %}
3328 interface(CONST_INTER);
3329 %}
3330
3331 operand immI_32_63() %{
3332 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3333 match(ConI);
3334 op_cost(0);
3335
3336 format %{ %}
3337 interface(CONST_INTER);
3338 %}
3339
3340 operand immI_1() %{
3341 predicate( n->get_int() == 1 );
3342 match(ConI);
3343
3344 op_cost(0);
3345 format %{ %}
3346 interface(CONST_INTER);
3347 %}
3348
3349 operand immI_2() %{
3350 predicate( n->get_int() == 2 );
3351 match(ConI);
3352
3353 op_cost(0);
3354 format %{ %}
3355 interface(CONST_INTER);
3356 %}
3357
3358 operand immI_3() %{
3359 predicate( n->get_int() == 3 );
3360 match(ConI);
3361
3362 op_cost(0);
3363 format %{ %}
3364 interface(CONST_INTER);
3365 %}
3366
3367 // Pointer Immediate
3368 operand immP() %{
3369 match(ConP);
3370
3371 op_cost(10);
3372 format %{ %}
3373 interface(CONST_INTER);
3374 %}
3375
3376 // NULL Pointer Immediate
3377 operand immP0() %{
3378 predicate( n->get_ptr() == 0 );
3379 match(ConP);
3380 op_cost(0);
3381
3382 format %{ %}
3383 interface(CONST_INTER);
3384 %}
3385
3386 // Long Immediate
3387 operand immL() %{
3388 match(ConL);
3389
3390 op_cost(20);
3391 format %{ %}
3392 interface(CONST_INTER);
3393 %}
3394
3395 // Long Immediate zero
3396 operand immL0() %{
3397 predicate( n->get_long() == 0L );
3398 match(ConL);
3399 op_cost(0);
3400
3401 format %{ %}
3402 interface(CONST_INTER);
3403 %}
3404
3405 // Long Immediate zero
3406 operand immL_M1() %{
3407 predicate( n->get_long() == -1L );
3408 match(ConL);
3409 op_cost(0);
3410
3411 format %{ %}
3412 interface(CONST_INTER);
3413 %}
3414
3415 // Long immediate from 0 to 127.
3416 // Used for a shorter form of long mul by 10.
3417 operand immL_127() %{
3418 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3419 match(ConL);
3420 op_cost(0);
3421
3422 format %{ %}
3423 interface(CONST_INTER);
3424 %}
3425
3426 // Long Immediate: low 32-bit mask
3427 operand immL_32bits() %{
3428 predicate(n->get_long() == 0xFFFFFFFFL);
3429 match(ConL);
3430 op_cost(0);
3431
3432 format %{ %}
3433 interface(CONST_INTER);
3434 %}
3435
3436 // Long Immediate: low 32-bit mask
3437 operand immL32() %{
3438 predicate(n->get_long() == (int)(n->get_long()));
3439 match(ConL);
3440 op_cost(20);
3441
3442 format %{ %}
3443 interface(CONST_INTER);
3444 %}
3445
3446 //Double Immediate zero
3447 operand immDPR0() %{
3448 // Do additional (and counter-intuitive) test against NaN to work around VC++
3449 // bug that generates code such that NaNs compare equal to 0.0
3450 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
3451 match(ConD);
3452
3453 op_cost(5);
3454 format %{ %}
3455 interface(CONST_INTER);
3456 %}
3457
3458 // Double Immediate one
3459 operand immDPR1() %{
3460 predicate( UseSSE<=1 && n->getd() == 1.0 );
3461 match(ConD);
3462
3463 op_cost(5);
3464 format %{ %}
3465 interface(CONST_INTER);
3466 %}
3467
3468 // Double Immediate
3469 operand immDPR() %{
3470 predicate(UseSSE<=1);
3471 match(ConD);
3472
3473 op_cost(5);
3474 format %{ %}
3475 interface(CONST_INTER);
3476 %}
3477
3478 operand immD() %{
3479 predicate(UseSSE>=2);
3480 match(ConD);
3481
3482 op_cost(5);
3483 format %{ %}
3484 interface(CONST_INTER);
3485 %}
3486
3487 // Double Immediate zero
3488 operand immD0() %{
3489 // Do additional (and counter-intuitive) test against NaN to work around VC++
3490 // bug that generates code such that NaNs compare equal to 0.0 AND do not
3491 // compare equal to -0.0.
3492 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
3493 match(ConD);
3494
3495 format %{ %}
3496 interface(CONST_INTER);
3497 %}
3498
3499 // Float Immediate zero
3500 operand immFPR0() %{
3501 predicate(UseSSE == 0 && n->getf() == 0.0F);
3502 match(ConF);
3503
3504 op_cost(5);
3505 format %{ %}
3506 interface(CONST_INTER);
3507 %}
3508
3509 // Float Immediate one
3510 operand immFPR1() %{
3511 predicate(UseSSE == 0 && n->getf() == 1.0F);
3512 match(ConF);
3513
3514 op_cost(5);
3515 format %{ %}
3516 interface(CONST_INTER);
3517 %}
3518
3519 // Float Immediate
3520 operand immFPR() %{
3521 predicate( UseSSE == 0 );
3522 match(ConF);
3523
3524 op_cost(5);
3525 format %{ %}
3526 interface(CONST_INTER);
3527 %}
3528
3529 // Float Immediate
3530 operand immF() %{
3531 predicate(UseSSE >= 1);
3532 match(ConF);
3533
3534 op_cost(5);
3535 format %{ %}
3536 interface(CONST_INTER);
3537 %}
3538
3539 // Float Immediate zero. Zero and not -0.0
3540 operand immF0() %{
3541 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
3542 match(ConF);
3543
3544 op_cost(5);
3545 format %{ %}
3546 interface(CONST_INTER);
3547 %}
3548
3549 // Immediates for special shifts (sign extend)
3550
3551 // Constants for increment
3552 operand immI_16() %{
3553 predicate( n->get_int() == 16 );
3554 match(ConI);
3555
3556 format %{ %}
3557 interface(CONST_INTER);
3558 %}
3559
3560 operand immI_24() %{
3561 predicate( n->get_int() == 24 );
3562 match(ConI);
3563
3564 format %{ %}
3565 interface(CONST_INTER);
3566 %}
3567
3568 // Constant for byte-wide masking
3569 operand immI_255() %{
3570 predicate( n->get_int() == 255 );
3571 match(ConI);
3572
3573 format %{ %}
3574 interface(CONST_INTER);
3575 %}
3576
3577 // Constant for short-wide masking
3578 operand immI_65535() %{
3579 predicate(n->get_int() == 65535);
3580 match(ConI);
3581
3582 format %{ %}
3583 interface(CONST_INTER);
3584 %}
3585
3586 // Register Operands
3587 // Integer Register
3588 operand rRegI() %{
3589 constraint(ALLOC_IN_RC(int_reg));
3590 match(RegI);
3591 match(xRegI);
3592 match(eAXRegI);
3593 match(eBXRegI);
3594 match(eCXRegI);
3595 match(eDXRegI);
3596 match(eDIRegI);
3597 match(eSIRegI);
3598
3599 format %{ %}
3600 interface(REG_INTER);
3601 %}
3602
3603 // Subset of Integer Register
3604 operand xRegI(rRegI reg) %{
3605 constraint(ALLOC_IN_RC(int_x_reg));
3606 match(reg);
3607 match(eAXRegI);
3608 match(eBXRegI);
3609 match(eCXRegI);
3610 match(eDXRegI);
3611
3612 format %{ %}
3613 interface(REG_INTER);
3614 %}
3615
3616 // Special Registers
3617 operand eAXRegI(xRegI reg) %{
3618 constraint(ALLOC_IN_RC(eax_reg));
3619 match(reg);
3620 match(rRegI);
3621
3622 format %{ "EAX" %}
3623 interface(REG_INTER);
3624 %}
3625
3626 // Special Registers
3627 operand eBXRegI(xRegI reg) %{
3628 constraint(ALLOC_IN_RC(ebx_reg));
3629 match(reg);
3630 match(rRegI);
3631
3632 format %{ "EBX" %}
3633 interface(REG_INTER);
3634 %}
3635
3636 operand eCXRegI(xRegI reg) %{
3637 constraint(ALLOC_IN_RC(ecx_reg));
3638 match(reg);
3639 match(rRegI);
3640
3641 format %{ "ECX" %}
3642 interface(REG_INTER);
3643 %}
3644
3645 operand eDXRegI(xRegI reg) %{
3646 constraint(ALLOC_IN_RC(edx_reg));
3647 match(reg);
3648 match(rRegI);
3649
3650 format %{ "EDX" %}
3651 interface(REG_INTER);
3652 %}
3653
3654 operand eDIRegI(xRegI reg) %{
3655 constraint(ALLOC_IN_RC(edi_reg));
3656 match(reg);
3657 match(rRegI);
3658
3659 format %{ "EDI" %}
3660 interface(REG_INTER);
3661 %}
3662
3663 operand naxRegI() %{
3664 constraint(ALLOC_IN_RC(nax_reg));
3665 match(RegI);
3666 match(eCXRegI);
3667 match(eDXRegI);
3668 match(eSIRegI);
3669 match(eDIRegI);
3670
3671 format %{ %}
3672 interface(REG_INTER);
3673 %}
3674
3675 operand nadxRegI() %{
3676 constraint(ALLOC_IN_RC(nadx_reg));
3677 match(RegI);
3678 match(eBXRegI);
3679 match(eCXRegI);
3680 match(eSIRegI);
3681 match(eDIRegI);
3682
3683 format %{ %}
3684 interface(REG_INTER);
3685 %}
3686
3687 operand ncxRegI() %{
3688 constraint(ALLOC_IN_RC(ncx_reg));
3689 match(RegI);
3690 match(eAXRegI);
3691 match(eDXRegI);
3692 match(eSIRegI);
3693 match(eDIRegI);
3694
3695 format %{ %}
3696 interface(REG_INTER);
3697 %}
3698
3699 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
3700 // //
3701 operand eSIRegI(xRegI reg) %{
3702 constraint(ALLOC_IN_RC(esi_reg));
3703 match(reg);
3704 match(rRegI);
3705
3706 format %{ "ESI" %}
3707 interface(REG_INTER);
3708 %}
3709
3710 // Pointer Register
3711 operand anyRegP() %{
3712 constraint(ALLOC_IN_RC(any_reg));
3713 match(RegP);
3714 match(eAXRegP);
3715 match(eBXRegP);
3716 match(eCXRegP);
3717 match(eDIRegP);
3718 match(eRegP);
3719
3720 format %{ %}
3721 interface(REG_INTER);
3722 %}
3723
3724 operand eRegP() %{
3725 constraint(ALLOC_IN_RC(int_reg));
3726 match(RegP);
3727 match(eAXRegP);
3728 match(eBXRegP);
3729 match(eCXRegP);
3730 match(eDIRegP);
3731
3732 format %{ %}
3733 interface(REG_INTER);
3734 %}
3735
3736 // On windows95, EBP is not safe to use for implicit null tests.
3737 operand eRegP_no_EBP() %{
3738 constraint(ALLOC_IN_RC(int_reg_no_rbp));
3739 match(RegP);
3740 match(eAXRegP);
3741 match(eBXRegP);
3742 match(eCXRegP);
3743 match(eDIRegP);
3744
3745 op_cost(100);
3746 format %{ %}
3747 interface(REG_INTER);
3748 %}
3749
3750 operand naxRegP() %{
3751 constraint(ALLOC_IN_RC(nax_reg));
3752 match(RegP);
3753 match(eBXRegP);
3754 match(eDXRegP);
3755 match(eCXRegP);
3756 match(eSIRegP);
3757 match(eDIRegP);
3758
3759 format %{ %}
3760 interface(REG_INTER);
3761 %}
3762
3763 operand nabxRegP() %{
3764 constraint(ALLOC_IN_RC(nabx_reg));
3765 match(RegP);
3766 match(eCXRegP);
3767 match(eDXRegP);
3768 match(eSIRegP);
3769 match(eDIRegP);
3770
3771 format %{ %}
3772 interface(REG_INTER);
3773 %}
3774
3775 operand pRegP() %{
3776 constraint(ALLOC_IN_RC(p_reg));
3777 match(RegP);
3778 match(eBXRegP);
3779 match(eDXRegP);
3780 match(eSIRegP);
3781 match(eDIRegP);
3782
3783 format %{ %}
3784 interface(REG_INTER);
3785 %}
3786
3787 // Special Registers
3788 // Return a pointer value
3789 operand eAXRegP(eRegP reg) %{
3790 constraint(ALLOC_IN_RC(eax_reg));
3791 match(reg);
3792 format %{ "EAX" %}
3793 interface(REG_INTER);
3794 %}
3795
3796 // Used in AtomicAdd
3797 operand eBXRegP(eRegP reg) %{
3798 constraint(ALLOC_IN_RC(ebx_reg));
3799 match(reg);
3800 format %{ "EBX" %}
3801 interface(REG_INTER);
3802 %}
3803
3804 // Tail-call (interprocedural jump) to interpreter
3805 operand eCXRegP(eRegP reg) %{
3806 constraint(ALLOC_IN_RC(ecx_reg));
3807 match(reg);
3808 format %{ "ECX" %}
3809 interface(REG_INTER);
3810 %}
3811
3812 operand eSIRegP(eRegP reg) %{
3813 constraint(ALLOC_IN_RC(esi_reg));
3814 match(reg);
3815 format %{ "ESI" %}
3816 interface(REG_INTER);
3817 %}
3818
3819 // Used in rep stosw
3820 operand eDIRegP(eRegP reg) %{
3821 constraint(ALLOC_IN_RC(edi_reg));
3822 match(reg);
3823 format %{ "EDI" %}
3824 interface(REG_INTER);
3825 %}
3826
3827 operand eBPRegP() %{
3828 constraint(ALLOC_IN_RC(ebp_reg));
3829 match(RegP);
3830 format %{ "EBP" %}
3831 interface(REG_INTER);
3832 %}
3833
3834 operand eRegL() %{
3835 constraint(ALLOC_IN_RC(long_reg));
3836 match(RegL);
3837 match(eADXRegL);
3838
3839 format %{ %}
3840 interface(REG_INTER);
3841 %}
3842
3843 operand eADXRegL( eRegL reg ) %{
3844 constraint(ALLOC_IN_RC(eadx_reg));
3845 match(reg);
3846
3847 format %{ "EDX:EAX" %}
3848 interface(REG_INTER);
3849 %}
3850
3851 operand eBCXRegL( eRegL reg ) %{
3852 constraint(ALLOC_IN_RC(ebcx_reg));
3853 match(reg);
3854
3855 format %{ "EBX:ECX" %}
3856 interface(REG_INTER);
3857 %}
3858
3859 // Special case for integer high multiply
3860 operand eADXRegL_low_only() %{
3861 constraint(ALLOC_IN_RC(eadx_reg));
3862 match(RegL);
3863
3864 format %{ "EAX" %}
3865 interface(REG_INTER);
3866 %}
3867
3868 // Flags register, used as output of compare instructions
3869 operand eFlagsReg() %{
3870 constraint(ALLOC_IN_RC(int_flags));
3871 match(RegFlags);
3872
3873 format %{ "EFLAGS" %}
3874 interface(REG_INTER);
3875 %}
3876
3877 // Flags register, used as output of FLOATING POINT compare instructions
3878 operand eFlagsRegU() %{
3879 constraint(ALLOC_IN_RC(int_flags));
3880 match(RegFlags);
3881
3882 format %{ "EFLAGS_U" %}
3883 interface(REG_INTER);
3884 %}
3885
3886 operand eFlagsRegUCF() %{
3887 constraint(ALLOC_IN_RC(int_flags));
3888 match(RegFlags);
3889 predicate(false);
3890
3891 format %{ "EFLAGS_U_CF" %}
3892 interface(REG_INTER);
3893 %}
3894
3895 // Condition Code Register used by long compare
3896 operand flagsReg_long_LTGE() %{
3897 constraint(ALLOC_IN_RC(int_flags));
3898 match(RegFlags);
3899 format %{ "FLAGS_LTGE" %}
3900 interface(REG_INTER);
3901 %}
3902 operand flagsReg_long_EQNE() %{
3903 constraint(ALLOC_IN_RC(int_flags));
3904 match(RegFlags);
3905 format %{ "FLAGS_EQNE" %}
3906 interface(REG_INTER);
3907 %}
3908 operand flagsReg_long_LEGT() %{
3909 constraint(ALLOC_IN_RC(int_flags));
3910 match(RegFlags);
3911 format %{ "FLAGS_LEGT" %}
3912 interface(REG_INTER);
3913 %}
3914
3915 // Float register operands
3916 operand regDPR() %{
3917 predicate( UseSSE < 2 );
3918 constraint(ALLOC_IN_RC(fp_dbl_reg));
3919 match(RegD);
3920 match(regDPR1);
3921 match(regDPR2);
3922 format %{ %}
3923 interface(REG_INTER);
3924 %}
3925
3926 operand regDPR1(regDPR reg) %{
3927 predicate( UseSSE < 2 );
3928 constraint(ALLOC_IN_RC(fp_dbl_reg0));
3929 match(reg);
3930 format %{ "FPR1" %}
3931 interface(REG_INTER);
3932 %}
3933
3934 operand regDPR2(regDPR reg) %{
3935 predicate( UseSSE < 2 );
3936 constraint(ALLOC_IN_RC(fp_dbl_reg1));
3937 match(reg);
3938 format %{ "FPR2" %}
3939 interface(REG_INTER);
3940 %}
3941
3942 operand regnotDPR1(regDPR reg) %{
3943 predicate( UseSSE < 2 );
3944 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
3945 match(reg);
3946 format %{ %}
3947 interface(REG_INTER);
3948 %}
3949
3950 // Float register operands
3951 operand regFPR() %{
3952 predicate( UseSSE < 2 );
3953 constraint(ALLOC_IN_RC(fp_flt_reg));
3954 match(RegF);
3955 match(regFPR1);
3956 format %{ %}
3957 interface(REG_INTER);
3958 %}
3959
3960 // Float register operands
3961 operand regFPR1(regFPR reg) %{
3962 predicate( UseSSE < 2 );
3963 constraint(ALLOC_IN_RC(fp_flt_reg0));
3964 match(reg);
3965 format %{ "FPR1" %}
3966 interface(REG_INTER);
3967 %}
3968
3969 // XMM Float register operands
3970 operand regF() %{
3971 predicate( UseSSE>=1 );
3972 constraint(ALLOC_IN_RC(float_reg));
3973 match(RegF);
3974 format %{ %}
3975 interface(REG_INTER);
3976 %}
3977
3978 // XMM Double register operands
3979 operand regD() %{
3980 predicate( UseSSE>=2 );
3981 constraint(ALLOC_IN_RC(double_reg));
3982 match(RegD);
3983 format %{ %}
3984 interface(REG_INTER);
3985 %}
3986
3987
3988 //----------Memory Operands----------------------------------------------------
3989 // Direct Memory Operand
3990 operand direct(immP addr) %{
3991 match(addr);
3992
3993 format %{ "[$addr]" %}
3994 interface(MEMORY_INTER) %{
3995 base(0xFFFFFFFF);
3996 index(0x4);
3997 scale(0x0);
3998 disp($addr);
3999 %}
4000 %}
4001
4002 // Indirect Memory Operand
4003 operand indirect(eRegP reg) %{
4004 constraint(ALLOC_IN_RC(int_reg));
4005 match(reg);
4006
4007 format %{ "[$reg]" %}
4008 interface(MEMORY_INTER) %{
4009 base($reg);
4010 index(0x4);
4011 scale(0x0);
4012 disp(0x0);
4013 %}
4014 %}
4015
4016 // Indirect Memory Plus Short Offset Operand
4017 operand indOffset8(eRegP reg, immI8 off) %{
4018 match(AddP reg off);
4019
4020 format %{ "[$reg + $off]" %}
4021 interface(MEMORY_INTER) %{
4022 base($reg);
4023 index(0x4);
4024 scale(0x0);
4025 disp($off);
4026 %}
4027 %}
4028
4029 // Indirect Memory Plus Long Offset Operand
4030 operand indOffset32(eRegP reg, immI off) %{
4031 match(AddP reg off);
4032
4033 format %{ "[$reg + $off]" %}
4034 interface(MEMORY_INTER) %{
4035 base($reg);
4036 index(0x4);
4037 scale(0x0);
4038 disp($off);
4039 %}
4040 %}
4041
4042 // Indirect Memory Plus Long Offset Operand
4043 operand indOffset32X(rRegI reg, immP off) %{
4044 match(AddP off reg);
4045
4046 format %{ "[$reg + $off]" %}
4047 interface(MEMORY_INTER) %{
4048 base($reg);
4049 index(0x4);
4050 scale(0x0);
4051 disp($off);
4052 %}
4053 %}
4054
4055 // Indirect Memory Plus Index Register Plus Offset Operand
4056 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4057 match(AddP (AddP reg ireg) off);
4058
4059 op_cost(10);
4060 format %{"[$reg + $off + $ireg]" %}
4061 interface(MEMORY_INTER) %{
4062 base($reg);
4063 index($ireg);
4064 scale(0x0);
4065 disp($off);
4066 %}
4067 %}
4068
4069 // Indirect Memory Plus Index Register Plus Offset Operand
4070 operand indIndex(eRegP reg, rRegI ireg) %{
4071 match(AddP reg ireg);
4072
4073 op_cost(10);
4074 format %{"[$reg + $ireg]" %}
4075 interface(MEMORY_INTER) %{
4076 base($reg);
4077 index($ireg);
4078 scale(0x0);
4079 disp(0x0);
4080 %}
4081 %}
4082
4083 // // -------------------------------------------------------------------------
4084 // // 486 architecture doesn't support "scale * index + offset" with out a base
4085 // // -------------------------------------------------------------------------
4086 // // Scaled Memory Operands
4087 // // Indirect Memory Times Scale Plus Offset Operand
4088 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4089 // match(AddP off (LShiftI ireg scale));
4090 //
4091 // op_cost(10);
4092 // format %{"[$off + $ireg << $scale]" %}
4093 // interface(MEMORY_INTER) %{
4094 // base(0x4);
4095 // index($ireg);
4096 // scale($scale);
4097 // disp($off);
4098 // %}
4099 // %}
4100
4101 // Indirect Memory Times Scale Plus Index Register
4102 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4103 match(AddP reg (LShiftI ireg scale));
4104
4105 op_cost(10);
4106 format %{"[$reg + $ireg << $scale]" %}
4107 interface(MEMORY_INTER) %{
4108 base($reg);
4109 index($ireg);
4110 scale($scale);
4111 disp(0x0);
4112 %}
4113 %}
4114
4115 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4116 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4117 match(AddP (AddP reg (LShiftI ireg scale)) off);
4118
4119 op_cost(10);
4120 format %{"[$reg + $off + $ireg << $scale]" %}
4121 interface(MEMORY_INTER) %{
4122 base($reg);
4123 index($ireg);
4124 scale($scale);
4125 disp($off);
4126 %}
4127 %}
4128
4129 //----------Load Long Memory Operands------------------------------------------
4130 // The load-long idiom will use it's address expression again after loading
4131 // the first word of the long. If the load-long destination overlaps with
4132 // registers used in the addressing expression, the 2nd half will be loaded
4133 // from a clobbered address. Fix this by requiring that load-long use
4134 // address registers that do not overlap with the load-long target.
4135
4136 // load-long support
4137 operand load_long_RegP() %{
4138 constraint(ALLOC_IN_RC(esi_reg));
4139 match(RegP);
4140 match(eSIRegP);
4141 op_cost(100);
4142 format %{ %}
4143 interface(REG_INTER);
4144 %}
4145
4146 // Indirect Memory Operand Long
4147 operand load_long_indirect(load_long_RegP reg) %{
4148 constraint(ALLOC_IN_RC(esi_reg));
4149 match(reg);
4150
4151 format %{ "[$reg]" %}
4152 interface(MEMORY_INTER) %{
4153 base($reg);
4154 index(0x4);
4155 scale(0x0);
4156 disp(0x0);
4157 %}
4158 %}
4159
4160 // Indirect Memory Plus Long Offset Operand
4161 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4162 match(AddP reg off);
4163
4164 format %{ "[$reg + $off]" %}
4165 interface(MEMORY_INTER) %{
4166 base($reg);
4167 index(0x4);
4168 scale(0x0);
4169 disp($off);
4170 %}
4171 %}
4172
4173 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4174
4175
4176 //----------Special Memory Operands--------------------------------------------
4177 // Stack Slot Operand - This operand is used for loading and storing temporary
4178 // values on the stack where a match requires a value to
4179 // flow through memory.
4180 operand stackSlotP(sRegP reg) %{
4181 constraint(ALLOC_IN_RC(stack_slots));
4182 // No match rule because this operand is only generated in matching
4183 format %{ "[$reg]" %}
4184 interface(MEMORY_INTER) %{
4185 base(0x4); // ESP
4186 index(0x4); // No Index
4187 scale(0x0); // No Scale
4188 disp($reg); // Stack Offset
4189 %}
4190 %}
4191
4192 operand stackSlotI(sRegI reg) %{
4193 constraint(ALLOC_IN_RC(stack_slots));
4194 // No match rule because this operand is only generated in matching
4195 format %{ "[$reg]" %}
4196 interface(MEMORY_INTER) %{
4197 base(0x4); // ESP
4198 index(0x4); // No Index
4199 scale(0x0); // No Scale
4200 disp($reg); // Stack Offset
4201 %}
4202 %}
4203
4204 operand stackSlotF(sRegF reg) %{
4205 constraint(ALLOC_IN_RC(stack_slots));
4206 // No match rule because this operand is only generated in matching
4207 format %{ "[$reg]" %}
4208 interface(MEMORY_INTER) %{
4209 base(0x4); // ESP
4210 index(0x4); // No Index
4211 scale(0x0); // No Scale
4212 disp($reg); // Stack Offset
4213 %}
4214 %}
4215
4216 operand stackSlotD(sRegD reg) %{
4217 constraint(ALLOC_IN_RC(stack_slots));
4218 // No match rule because this operand is only generated in matching
4219 format %{ "[$reg]" %}
4220 interface(MEMORY_INTER) %{
4221 base(0x4); // ESP
4222 index(0x4); // No Index
4223 scale(0x0); // No Scale
4224 disp($reg); // Stack Offset
4225 %}
4226 %}
4227
4228 operand stackSlotL(sRegL reg) %{
4229 constraint(ALLOC_IN_RC(stack_slots));
4230 // No match rule because this operand is only generated in matching
4231 format %{ "[$reg]" %}
4232 interface(MEMORY_INTER) %{
4233 base(0x4); // ESP
4234 index(0x4); // No Index
4235 scale(0x0); // No Scale
4236 disp($reg); // Stack Offset
4237 %}
4238 %}
4239
4240 //----------Memory Operands - Win95 Implicit Null Variants----------------
4241 // Indirect Memory Operand
4242 operand indirect_win95_safe(eRegP_no_EBP reg)
4243 %{
4244 constraint(ALLOC_IN_RC(int_reg));
4245 match(reg);
4246
4247 op_cost(100);
4248 format %{ "[$reg]" %}
4249 interface(MEMORY_INTER) %{
4250 base($reg);
4251 index(0x4);
4252 scale(0x0);
4253 disp(0x0);
4254 %}
4255 %}
4256
4257 // Indirect Memory Plus Short Offset Operand
4258 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4259 %{
4260 match(AddP reg off);
4261
4262 op_cost(100);
4263 format %{ "[$reg + $off]" %}
4264 interface(MEMORY_INTER) %{
4265 base($reg);
4266 index(0x4);
4267 scale(0x0);
4268 disp($off);
4269 %}
4270 %}
4271
4272 // Indirect Memory Plus Long Offset Operand
4273 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4274 %{
4275 match(AddP reg off);
4276
4277 op_cost(100);
4278 format %{ "[$reg + $off]" %}
4279 interface(MEMORY_INTER) %{
4280 base($reg);
4281 index(0x4);
4282 scale(0x0);
4283 disp($off);
4284 %}
4285 %}
4286
4287 // Indirect Memory Plus Index Register Plus Offset Operand
4288 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4289 %{
4290 match(AddP (AddP reg ireg) off);
4291
4292 op_cost(100);
4293 format %{"[$reg + $off + $ireg]" %}
4294 interface(MEMORY_INTER) %{
4295 base($reg);
4296 index($ireg);
4297 scale(0x0);
4298 disp($off);
4299 %}
4300 %}
4301
4302 // Indirect Memory Times Scale Plus Index Register
4303 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4304 %{
4305 match(AddP reg (LShiftI ireg scale));
4306
4307 op_cost(100);
4308 format %{"[$reg + $ireg << $scale]" %}
4309 interface(MEMORY_INTER) %{
4310 base($reg);
4311 index($ireg);
4312 scale($scale);
4313 disp(0x0);
4314 %}
4315 %}
4316
4317 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4318 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4319 %{
4320 match(AddP (AddP reg (LShiftI ireg scale)) off);
4321
4322 op_cost(100);
4323 format %{"[$reg + $off + $ireg << $scale]" %}
4324 interface(MEMORY_INTER) %{
4325 base($reg);
4326 index($ireg);
4327 scale($scale);
4328 disp($off);
4329 %}
4330 %}
4331
4332 //----------Conditional Branch Operands----------------------------------------
4333 // Comparison Op - This is the operation of the comparison, and is limited to
4334 // the following set of codes:
4335 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4336 //
4337 // Other attributes of the comparison, such as unsignedness, are specified
4338 // by the comparison instruction that sets a condition code flags register.
4339 // That result is represented by a flags operand whose subtype is appropriate
4340 // to the unsignedness (etc.) of the comparison.
4341 //
4342 // Later, the instruction which matches both the Comparison Op (a Bool) and
4343 // the flags (produced by the Cmp) specifies the coding of the comparison op
4344 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4345
4346 // Comparision Code
4347 operand cmpOp() %{
4348 match(Bool);
4349
4350 format %{ "" %}
4351 interface(COND_INTER) %{
4352 equal(0x4, "e");
4353 not_equal(0x5, "ne");
4354 less(0xC, "l");
4355 greater_equal(0xD, "ge");
4356 less_equal(0xE, "le");
4357 greater(0xF, "g");
4358 overflow(0x0, "o");
4359 no_overflow(0x1, "no");
4360 %}
4361 %}
4362
4363 // Comparison Code, unsigned compare. Used by FP also, with
4364 // C2 (unordered) turned into GT or LT already. The other bits
4365 // C0 and C3 are turned into Carry & Zero flags.
4366 operand cmpOpU() %{
4367 match(Bool);
4368
4369 format %{ "" %}
4370 interface(COND_INTER) %{
4371 equal(0x4, "e");
4372 not_equal(0x5, "ne");
4373 less(0x2, "b");
4374 greater_equal(0x3, "nb");
4375 less_equal(0x6, "be");
4376 greater(0x7, "nbe");
4377 overflow(0x0, "o");
4378 no_overflow(0x1, "no");
4379 %}
4380 %}
4381
4382 // Floating comparisons that don't require any fixup for the unordered case
4383 operand cmpOpUCF() %{
4384 match(Bool);
4385 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4386 n->as_Bool()->_test._test == BoolTest::ge ||
4387 n->as_Bool()->_test._test == BoolTest::le ||
4388 n->as_Bool()->_test._test == BoolTest::gt);
4389 format %{ "" %}
4390 interface(COND_INTER) %{
4391 equal(0x4, "e");
4392 not_equal(0x5, "ne");
4393 less(0x2, "b");
4394 greater_equal(0x3, "nb");
4395 less_equal(0x6, "be");
4396 greater(0x7, "nbe");
4397 overflow(0x0, "o");
4398 no_overflow(0x1, "no");
4399 %}
4400 %}
4401
4402
4403 // Floating comparisons that can be fixed up with extra conditional jumps
4404 operand cmpOpUCF2() %{
4405 match(Bool);
4406 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4407 n->as_Bool()->_test._test == BoolTest::eq);
4408 format %{ "" %}
4409 interface(COND_INTER) %{
4410 equal(0x4, "e");
4411 not_equal(0x5, "ne");
4412 less(0x2, "b");
4413 greater_equal(0x3, "nb");
4414 less_equal(0x6, "be");
4415 greater(0x7, "nbe");
4416 overflow(0x0, "o");
4417 no_overflow(0x1, "no");
4418 %}
4419 %}
4420
4421 // Comparison Code for FP conditional move
4422 operand cmpOp_fcmov() %{
4423 match(Bool);
4424
4425 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4426 n->as_Bool()->_test._test != BoolTest::no_overflow);
4427 format %{ "" %}
4428 interface(COND_INTER) %{
4429 equal (0x0C8);
4430 not_equal (0x1C8);
4431 less (0x0C0);
4432 greater_equal(0x1C0);
4433 less_equal (0x0D0);
4434 greater (0x1D0);
4435 overflow(0x0, "o"); // not really supported by the instruction
4436 no_overflow(0x1, "no"); // not really supported by the instruction
4437 %}
4438 %}
4439
4440 // Comparision Code used in long compares
4441 operand cmpOp_commute() %{
4442 match(Bool);
4443
4444 format %{ "" %}
4445 interface(COND_INTER) %{
4446 equal(0x4, "e");
4447 not_equal(0x5, "ne");
4448 less(0xF, "g");
4449 greater_equal(0xE, "le");
4450 less_equal(0xD, "ge");
4451 greater(0xC, "l");
4452 overflow(0x0, "o");
4453 no_overflow(0x1, "no");
4454 %}
4455 %}
4456
4457 //----------OPERAND CLASSES----------------------------------------------------
4458 // Operand Classes are groups of operands that are used as to simplify
4459 // instruction definitions by not requiring the AD writer to specify separate
4460 // instructions for every form of operand when the instruction accepts
4461 // multiple operand types with the same basic encoding and format. The classic
4462 // case of this is memory operands.
4463
4464 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
4465 indIndex, indIndexScale, indIndexScaleOffset);
4466
4467 // Long memory operations are encoded in 2 instructions and a +4 offset.
4468 // This means some kind of offset is always required and you cannot use
4469 // an oop as the offset (done when working on static globals).
4470 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
4471 indIndex, indIndexScale, indIndexScaleOffset);
4472
4473
4474 //----------PIPELINE-----------------------------------------------------------
4475 // Rules which define the behavior of the target architectures pipeline.
4476 pipeline %{
4477
4478 //----------ATTRIBUTES---------------------------------------------------------
4479 attributes %{
4480 variable_size_instructions; // Fixed size instructions
4481 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4482 instruction_unit_size = 1; // An instruction is 1 bytes long
4483 instruction_fetch_unit_size = 16; // The processor fetches one line
4484 instruction_fetch_units = 1; // of 16 bytes
4485
4486 // List of nop instructions
4487 nops( MachNop );
4488 %}
4489
4490 //----------RESOURCES----------------------------------------------------------
4491 // Resources are the functional units available to the machine
4492
4493 // Generic P2/P3 pipeline
4494 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4495 // 3 instructions decoded per cycle.
4496 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4497 // 2 ALU op, only ALU0 handles mul/div instructions.
4498 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4499 MS0, MS1, MEM = MS0 | MS1,
4500 BR, FPU,
4501 ALU0, ALU1, ALU = ALU0 | ALU1 );
4502
4503 //----------PIPELINE DESCRIPTION-----------------------------------------------
4504 // Pipeline Description specifies the stages in the machine's pipeline
4505
4506 // Generic P2/P3 pipeline
4507 pipe_desc(S0, S1, S2, S3, S4, S5);
4508
4509 //----------PIPELINE CLASSES---------------------------------------------------
4510 // Pipeline Classes describe the stages in which input and output are
4511 // referenced by the hardware pipeline.
4512
4513 // Naming convention: ialu or fpu
4514 // Then: _reg
4515 // Then: _reg if there is a 2nd register
4516 // Then: _long if it's a pair of instructions implementing a long
4517 // Then: _fat if it requires the big decoder
4518 // Or: _mem if it requires the big decoder and a memory unit.
4519
4520 // Integer ALU reg operation
4521 pipe_class ialu_reg(rRegI dst) %{
4522 single_instruction;
4523 dst : S4(write);
4524 dst : S3(read);
4525 DECODE : S0; // any decoder
4526 ALU : S3; // any alu
4527 %}
4528
4529 // Long ALU reg operation
4530 pipe_class ialu_reg_long(eRegL dst) %{
4531 instruction_count(2);
4532 dst : S4(write);
4533 dst : S3(read);
4534 DECODE : S0(2); // any 2 decoders
4535 ALU : S3(2); // both alus
4536 %}
4537
4538 // Integer ALU reg operation using big decoder
4539 pipe_class ialu_reg_fat(rRegI dst) %{
4540 single_instruction;
4541 dst : S4(write);
4542 dst : S3(read);
4543 D0 : S0; // big decoder only
4544 ALU : S3; // any alu
4545 %}
4546
4547 // Long ALU reg operation using big decoder
4548 pipe_class ialu_reg_long_fat(eRegL dst) %{
4549 instruction_count(2);
4550 dst : S4(write);
4551 dst : S3(read);
4552 D0 : S0(2); // big decoder only; twice
4553 ALU : S3(2); // any 2 alus
4554 %}
4555
4556 // Integer ALU reg-reg operation
4557 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
4558 single_instruction;
4559 dst : S4(write);
4560 src : S3(read);
4561 DECODE : S0; // any decoder
4562 ALU : S3; // any alu
4563 %}
4564
4565 // Long ALU reg-reg operation
4566 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
4567 instruction_count(2);
4568 dst : S4(write);
4569 src : S3(read);
4570 DECODE : S0(2); // any 2 decoders
4571 ALU : S3(2); // both alus
4572 %}
4573
4574 // Integer ALU reg-reg operation
4575 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
4576 single_instruction;
4577 dst : S4(write);
4578 src : S3(read);
4579 D0 : S0; // big decoder only
4580 ALU : S3; // any alu
4581 %}
4582
4583 // Long ALU reg-reg operation
4584 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
4585 instruction_count(2);
4586 dst : S4(write);
4587 src : S3(read);
4588 D0 : S0(2); // big decoder only; twice
4589 ALU : S3(2); // both alus
4590 %}
4591
4592 // Integer ALU reg-mem operation
4593 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
4594 single_instruction;
4595 dst : S5(write);
4596 mem : S3(read);
4597 D0 : S0; // big decoder only
4598 ALU : S4; // any alu
4599 MEM : S3; // any mem
4600 %}
4601
4602 // Long ALU reg-mem operation
4603 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
4604 instruction_count(2);
4605 dst : S5(write);
4606 mem : S3(read);
4607 D0 : S0(2); // big decoder only; twice
4608 ALU : S4(2); // any 2 alus
4609 MEM : S3(2); // both mems
4610 %}
4611
4612 // Integer mem operation (prefetch)
4613 pipe_class ialu_mem(memory mem)
4614 %{
4615 single_instruction;
4616 mem : S3(read);
4617 D0 : S0; // big decoder only
4618 MEM : S3; // any mem
4619 %}
4620
4621 // Integer Store to Memory
4622 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
4623 single_instruction;
4624 mem : S3(read);
4625 src : S5(read);
4626 D0 : S0; // big decoder only
4627 ALU : S4; // any alu
4628 MEM : S3;
4629 %}
4630
4631 // Long Store to Memory
4632 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
4633 instruction_count(2);
4634 mem : S3(read);
4635 src : S5(read);
4636 D0 : S0(2); // big decoder only; twice
4637 ALU : S4(2); // any 2 alus
4638 MEM : S3(2); // Both mems
4639 %}
4640
4641 // Integer Store to Memory
4642 pipe_class ialu_mem_imm(memory mem) %{
4643 single_instruction;
4644 mem : S3(read);
4645 D0 : S0; // big decoder only
4646 ALU : S4; // any alu
4647 MEM : S3;
4648 %}
4649
4650 // Integer ALU0 reg-reg operation
4651 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
4652 single_instruction;
4653 dst : S4(write);
4654 src : S3(read);
4655 D0 : S0; // Big decoder only
4656 ALU0 : S3; // only alu0
4657 %}
4658
4659 // Integer ALU0 reg-mem operation
4660 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
4661 single_instruction;
4662 dst : S5(write);
4663 mem : S3(read);
4664 D0 : S0; // big decoder only
4665 ALU0 : S4; // ALU0 only
4666 MEM : S3; // any mem
4667 %}
4668
4669 // Integer ALU reg-reg operation
4670 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
4671 single_instruction;
4672 cr : S4(write);
4673 src1 : S3(read);
4674 src2 : S3(read);
4675 DECODE : S0; // any decoder
4676 ALU : S3; // any alu
4677 %}
4678
4679 // Integer ALU reg-imm operation
4680 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
4681 single_instruction;
4682 cr : S4(write);
4683 src1 : S3(read);
4684 DECODE : S0; // any decoder
4685 ALU : S3; // any alu
4686 %}
4687
4688 // Integer ALU reg-mem operation
4689 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
4690 single_instruction;
4691 cr : S4(write);
4692 src1 : S3(read);
4693 src2 : S3(read);
4694 D0 : S0; // big decoder only
4695 ALU : S4; // any alu
4696 MEM : S3;
4697 %}
4698
4699 // Conditional move reg-reg
4700 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
4701 instruction_count(4);
4702 y : S4(read);
4703 q : S3(read);
4704 p : S3(read);
4705 DECODE : S0(4); // any decoder
4706 %}
4707
4708 // Conditional move reg-reg
4709 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
4710 single_instruction;
4711 dst : S4(write);
4712 src : S3(read);
4713 cr : S3(read);
4714 DECODE : S0; // any decoder
4715 %}
4716
4717 // Conditional move reg-mem
4718 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
4719 single_instruction;
4720 dst : S4(write);
4721 src : S3(read);
4722 cr : S3(read);
4723 DECODE : S0; // any decoder
4724 MEM : S3;
4725 %}
4726
4727 // Conditional move reg-reg long
4728 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
4729 single_instruction;
4730 dst : S4(write);
4731 src : S3(read);
4732 cr : S3(read);
4733 DECODE : S0(2); // any 2 decoders
4734 %}
4735
4736 // Conditional move double reg-reg
4737 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
4738 single_instruction;
4739 dst : S4(write);
4740 src : S3(read);
4741 cr : S3(read);
4742 DECODE : S0; // any decoder
4743 %}
4744
4745 // Float reg-reg operation
4746 pipe_class fpu_reg(regDPR dst) %{
4747 instruction_count(2);
4748 dst : S3(read);
4749 DECODE : S0(2); // any 2 decoders
4750 FPU : S3;
4751 %}
4752
4753 // Float reg-reg operation
4754 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
4755 instruction_count(2);
4756 dst : S4(write);
4757 src : S3(read);
4758 DECODE : S0(2); // any 2 decoders
4759 FPU : S3;
4760 %}
4761
4762 // Float reg-reg operation
4763 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
4764 instruction_count(3);
4765 dst : S4(write);
4766 src1 : S3(read);
4767 src2 : S3(read);
4768 DECODE : S0(3); // any 3 decoders
4769 FPU : S3(2);
4770 %}
4771
4772 // Float reg-reg operation
4773 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
4774 instruction_count(4);
4775 dst : S4(write);
4776 src1 : S3(read);
4777 src2 : S3(read);
4778 src3 : S3(read);
4779 DECODE : S0(4); // any 3 decoders
4780 FPU : S3(2);
4781 %}
4782
4783 // Float reg-reg operation
4784 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
4785 instruction_count(4);
4786 dst : S4(write);
4787 src1 : S3(read);
4788 src2 : S3(read);
4789 src3 : S3(read);
4790 DECODE : S1(3); // any 3 decoders
4791 D0 : S0; // Big decoder only
4792 FPU : S3(2);
4793 MEM : S3;
4794 %}
4795
4796 // Float reg-mem operation
4797 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
4798 instruction_count(2);
4799 dst : S5(write);
4800 mem : S3(read);
4801 D0 : S0; // big decoder only
4802 DECODE : S1; // any decoder for FPU POP
4803 FPU : S4;
4804 MEM : S3; // any mem
4805 %}
4806
4807 // Float reg-mem operation
4808 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
4809 instruction_count(3);
4810 dst : S5(write);
4811 src1 : S3(read);
4812 mem : S3(read);
4813 D0 : S0; // big decoder only
4814 DECODE : S1(2); // any decoder for FPU POP
4815 FPU : S4;
4816 MEM : S3; // any mem
4817 %}
4818
4819 // Float mem-reg operation
4820 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
4821 instruction_count(2);
4822 src : S5(read);
4823 mem : S3(read);
4824 DECODE : S0; // any decoder for FPU PUSH
4825 D0 : S1; // big decoder only
4826 FPU : S4;
4827 MEM : S3; // any mem
4828 %}
4829
4830 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
4831 instruction_count(3);
4832 src1 : S3(read);
4833 src2 : S3(read);
4834 mem : S3(read);
4835 DECODE : S0(2); // any decoder for FPU PUSH
4836 D0 : S1; // big decoder only
4837 FPU : S4;
4838 MEM : S3; // any mem
4839 %}
4840
4841 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
4842 instruction_count(3);
4843 src1 : S3(read);
4844 src2 : S3(read);
4845 mem : S4(read);
4846 DECODE : S0; // any decoder for FPU PUSH
4847 D0 : S0(2); // big decoder only
4848 FPU : S4;
4849 MEM : S3(2); // any mem
4850 %}
4851
4852 pipe_class fpu_mem_mem(memory dst, memory src1) %{
4853 instruction_count(2);
4854 src1 : S3(read);
4855 dst : S4(read);
4856 D0 : S0(2); // big decoder only
4857 MEM : S3(2); // any mem
4858 %}
4859
4860 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
4861 instruction_count(3);
4862 src1 : S3(read);
4863 src2 : S3(read);
4864 dst : S4(read);
4865 D0 : S0(3); // big decoder only
4866 FPU : S4;
4867 MEM : S3(3); // any mem
4868 %}
4869
4870 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
4871 instruction_count(3);
4872 src1 : S4(read);
4873 mem : S4(read);
4874 DECODE : S0; // any decoder for FPU PUSH
4875 D0 : S0(2); // big decoder only
4876 FPU : S4;
4877 MEM : S3(2); // any mem
4878 %}
4879
4880 // Float load constant
4881 pipe_class fpu_reg_con(regDPR dst) %{
4882 instruction_count(2);
4883 dst : S5(write);
4884 D0 : S0; // big decoder only for the load
4885 DECODE : S1; // any decoder for FPU POP
4886 FPU : S4;
4887 MEM : S3; // any mem
4888 %}
4889
4890 // Float load constant
4891 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
4892 instruction_count(3);
4893 dst : S5(write);
4894 src : S3(read);
4895 D0 : S0; // big decoder only for the load
4896 DECODE : S1(2); // any decoder for FPU POP
4897 FPU : S4;
4898 MEM : S3; // any mem
4899 %}
4900
4901 // UnConditional branch
4902 pipe_class pipe_jmp( label labl ) %{
4903 single_instruction;
4904 BR : S3;
4905 %}
4906
4907 // Conditional branch
4908 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
4909 single_instruction;
4910 cr : S1(read);
4911 BR : S3;
4912 %}
4913
4914 // Allocation idiom
4915 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
4916 instruction_count(1); force_serialization;
4917 fixed_latency(6);
4918 heap_ptr : S3(read);
4919 DECODE : S0(3);
4920 D0 : S2;
4921 MEM : S3;
4922 ALU : S3(2);
4923 dst : S5(write);
4924 BR : S5;
4925 %}
4926
4927 // Generic big/slow expanded idiom
4928 pipe_class pipe_slow( ) %{
4929 instruction_count(10); multiple_bundles; force_serialization;
4930 fixed_latency(100);
4931 D0 : S0(2);
4932 MEM : S3(2);
4933 %}
4934
4935 // The real do-nothing guy
4936 pipe_class empty( ) %{
4937 instruction_count(0);
4938 %}
4939
4940 // Define the class for the Nop node
4941 define %{
4942 MachNop = empty;
4943 %}
4944
4945 %}
4946
4947 //----------INSTRUCTIONS-------------------------------------------------------
4948 //
4949 // match -- States which machine-independent subtree may be replaced
4950 // by this instruction.
4951 // ins_cost -- The estimated cost of this instruction is used by instruction
4952 // selection to identify a minimum cost tree of machine
4953 // instructions that matches a tree of machine-independent
4954 // instructions.
4955 // format -- A string providing the disassembly for this instruction.
4956 // The value of an instruction's operand may be inserted
4957 // by referring to it with a '$' prefix.
4958 // opcode -- Three instruction opcodes may be provided. These are referred
4959 // to within an encode class as $primary, $secondary, and $tertiary
4960 // respectively. The primary opcode is commonly used to
4961 // indicate the type of machine instruction, while secondary
4962 // and tertiary are often used for prefix options or addressing
4963 // modes.
4964 // ins_encode -- A list of encode classes with parameters. The encode class
4965 // name must have been defined in an 'enc_class' specification
4966 // in the encode section of the architecture description.
4967
4968 //----------BSWAP-Instruction--------------------------------------------------
4969 instruct bytes_reverse_int(rRegI dst) %{
4970 match(Set dst (ReverseBytesI dst));
4971
4972 format %{ "BSWAP $dst" %}
4973 opcode(0x0F, 0xC8);
4974 ins_encode( OpcP, OpcSReg(dst) );
4975 ins_pipe( ialu_reg );
4976 %}
4977
4978 instruct bytes_reverse_long(eRegL dst) %{
4979 match(Set dst (ReverseBytesL dst));
4980
4981 format %{ "BSWAP $dst.lo\n\t"
4982 "BSWAP $dst.hi\n\t"
4983 "XCHG $dst.lo $dst.hi" %}
4984
4985 ins_cost(125);
4986 ins_encode( bswap_long_bytes(dst) );
4987 ins_pipe( ialu_reg_reg);
4988 %}
4989
4990 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
4991 match(Set dst (ReverseBytesUS dst));
4992 effect(KILL cr);
4993
4994 format %{ "BSWAP $dst\n\t"
4995 "SHR $dst,16\n\t" %}
4996 ins_encode %{
4997 __ bswapl($dst$$Register);
4998 __ shrl($dst$$Register, 16);
4999 %}
5000 ins_pipe( ialu_reg );
5001 %}
5002
5003 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5004 match(Set dst (ReverseBytesS dst));
5005 effect(KILL cr);
5006
5007 format %{ "BSWAP $dst\n\t"
5008 "SAR $dst,16\n\t" %}
5009 ins_encode %{
5010 __ bswapl($dst$$Register);
5011 __ sarl($dst$$Register, 16);
5012 %}
5013 ins_pipe( ialu_reg );
5014 %}
5015
5016
5017 //---------- Zeros Count Instructions ------------------------------------------
5018
5019 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5020 predicate(UseCountLeadingZerosInstruction);
5021 match(Set dst (CountLeadingZerosI src));
5022 effect(KILL cr);
5023
5024 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5025 ins_encode %{
5026 __ lzcntl($dst$$Register, $src$$Register);
5027 %}
5028 ins_pipe(ialu_reg);
5029 %}
5030
5031 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5032 predicate(!UseCountLeadingZerosInstruction);
5033 match(Set dst (CountLeadingZerosI src));
5034 effect(KILL cr);
5035
5036 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5037 "JNZ skip\n\t"
5038 "MOV $dst, -1\n"
5039 "skip:\n\t"
5040 "NEG $dst\n\t"
5041 "ADD $dst, 31" %}
5042 ins_encode %{
5043 Register Rdst = $dst$$Register;
5044 Register Rsrc = $src$$Register;
5045 Label skip;
5046 __ bsrl(Rdst, Rsrc);
5047 __ jccb(Assembler::notZero, skip);
5048 __ movl(Rdst, -1);
5049 __ bind(skip);
5050 __ negl(Rdst);
5051 __ addl(Rdst, BitsPerInt - 1);
5052 %}
5053 ins_pipe(ialu_reg);
5054 %}
5055
5056 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5057 predicate(UseCountLeadingZerosInstruction);
5058 match(Set dst (CountLeadingZerosL src));
5059 effect(TEMP dst, KILL cr);
5060
5061 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5062 "JNC done\n\t"
5063 "LZCNT $dst, $src.lo\n\t"
5064 "ADD $dst, 32\n"
5065 "done:" %}
5066 ins_encode %{
5067 Register Rdst = $dst$$Register;
5068 Register Rsrc = $src$$Register;
5069 Label done;
5070 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5071 __ jccb(Assembler::carryClear, done);
5072 __ lzcntl(Rdst, Rsrc);
5073 __ addl(Rdst, BitsPerInt);
5074 __ bind(done);
5075 %}
5076 ins_pipe(ialu_reg);
5077 %}
5078
5079 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5080 predicate(!UseCountLeadingZerosInstruction);
5081 match(Set dst (CountLeadingZerosL src));
5082 effect(TEMP dst, KILL cr);
5083
5084 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5085 "JZ msw_is_zero\n\t"
5086 "ADD $dst, 32\n\t"
5087 "JMP not_zero\n"
5088 "msw_is_zero:\n\t"
5089 "BSR $dst, $src.lo\n\t"
5090 "JNZ not_zero\n\t"
5091 "MOV $dst, -1\n"
5092 "not_zero:\n\t"
5093 "NEG $dst\n\t"
5094 "ADD $dst, 63\n" %}
5095 ins_encode %{
5096 Register Rdst = $dst$$Register;
5097 Register Rsrc = $src$$Register;
5098 Label msw_is_zero;
5099 Label not_zero;
5100 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5101 __ jccb(Assembler::zero, msw_is_zero);
5102 __ addl(Rdst, BitsPerInt);
5103 __ jmpb(not_zero);
5104 __ bind(msw_is_zero);
5105 __ bsrl(Rdst, Rsrc);
5106 __ jccb(Assembler::notZero, not_zero);
5107 __ movl(Rdst, -1);
5108 __ bind(not_zero);
5109 __ negl(Rdst);
5110 __ addl(Rdst, BitsPerLong - 1);
5111 %}
5112 ins_pipe(ialu_reg);
5113 %}
5114
5115 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5116 predicate(UseCountTrailingZerosInstruction);
5117 match(Set dst (CountTrailingZerosI src));
5118 effect(KILL cr);
5119
5120 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)" %}
5121 ins_encode %{
5122 __ tzcntl($dst$$Register, $src$$Register);
5123 %}
5124 ins_pipe(ialu_reg);
5125 %}
5126
5127 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{
5128 predicate(!UseCountTrailingZerosInstruction);
5129 match(Set dst (CountTrailingZerosI src));
5130 effect(KILL cr);
5131
5132 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5133 "JNZ done\n\t"
5134 "MOV $dst, 32\n"
5135 "done:" %}
5136 ins_encode %{
5137 Register Rdst = $dst$$Register;
5138 Label done;
5139 __ bsfl(Rdst, $src$$Register);
5140 __ jccb(Assembler::notZero, done);
5141 __ movl(Rdst, BitsPerInt);
5142 __ bind(done);
5143 %}
5144 ins_pipe(ialu_reg);
5145 %}
5146
5147 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5148 predicate(UseCountTrailingZerosInstruction);
5149 match(Set dst (CountTrailingZerosL src));
5150 effect(TEMP dst, KILL cr);
5151
5152 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t"
5153 "JNC done\n\t"
5154 "TZCNT $dst, $src.hi\n\t"
5155 "ADD $dst, 32\n"
5156 "done:" %}
5157 ins_encode %{
5158 Register Rdst = $dst$$Register;
5159 Register Rsrc = $src$$Register;
5160 Label done;
5161 __ tzcntl(Rdst, Rsrc);
5162 __ jccb(Assembler::carryClear, done);
5163 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5164 __ addl(Rdst, BitsPerInt);
5165 __ bind(done);
5166 %}
5167 ins_pipe(ialu_reg);
5168 %}
5169
5170 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{
5171 predicate(!UseCountTrailingZerosInstruction);
5172 match(Set dst (CountTrailingZerosL src));
5173 effect(TEMP dst, KILL cr);
5174
5175 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5176 "JNZ done\n\t"
5177 "BSF $dst, $src.hi\n\t"
5178 "JNZ msw_not_zero\n\t"
5179 "MOV $dst, 32\n"
5180 "msw_not_zero:\n\t"
5181 "ADD $dst, 32\n"
5182 "done:" %}
5183 ins_encode %{
5184 Register Rdst = $dst$$Register;
5185 Register Rsrc = $src$$Register;
5186 Label msw_not_zero;
5187 Label done;
5188 __ bsfl(Rdst, Rsrc);
5189 __ jccb(Assembler::notZero, done);
5190 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5191 __ jccb(Assembler::notZero, msw_not_zero);
5192 __ movl(Rdst, BitsPerInt);
5193 __ bind(msw_not_zero);
5194 __ addl(Rdst, BitsPerInt);
5195 __ bind(done);
5196 %}
5197 ins_pipe(ialu_reg);
5198 %}
5199
5200
5201 //---------- Population Count Instructions -------------------------------------
5202
5203 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5204 predicate(UsePopCountInstruction);
5205 match(Set dst (PopCountI src));
5206 effect(KILL cr);
5207
5208 format %{ "POPCNT $dst, $src" %}
5209 ins_encode %{
5210 __ popcntl($dst$$Register, $src$$Register);
5211 %}
5212 ins_pipe(ialu_reg);
5213 %}
5214
5215 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5216 predicate(UsePopCountInstruction);
5217 match(Set dst (PopCountI (LoadI mem)));
5218 effect(KILL cr);
5219
5220 format %{ "POPCNT $dst, $mem" %}
5221 ins_encode %{
5222 __ popcntl($dst$$Register, $mem$$Address);
5223 %}
5224 ins_pipe(ialu_reg);
5225 %}
5226
5227 // Note: Long.bitCount(long) returns an int.
5228 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5229 predicate(UsePopCountInstruction);
5230 match(Set dst (PopCountL src));
5231 effect(KILL cr, TEMP tmp, TEMP dst);
5232
5233 format %{ "POPCNT $dst, $src.lo\n\t"
5234 "POPCNT $tmp, $src.hi\n\t"
5235 "ADD $dst, $tmp" %}
5236 ins_encode %{
5237 __ popcntl($dst$$Register, $src$$Register);
5238 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5239 __ addl($dst$$Register, $tmp$$Register);
5240 %}
5241 ins_pipe(ialu_reg);
5242 %}
5243
5244 // Note: Long.bitCount(long) returns an int.
5245 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5246 predicate(UsePopCountInstruction);
5247 match(Set dst (PopCountL (LoadL mem)));
5248 effect(KILL cr, TEMP tmp, TEMP dst);
5249
5250 format %{ "POPCNT $dst, $mem\n\t"
5251 "POPCNT $tmp, $mem+4\n\t"
5252 "ADD $dst, $tmp" %}
5253 ins_encode %{
5254 //__ popcntl($dst$$Register, $mem$$Address$$first);
5255 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5256 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5257 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5258 __ addl($dst$$Register, $tmp$$Register);
5259 %}
5260 ins_pipe(ialu_reg);
5261 %}
5262
5263
5264 //----------Load/Store/Move Instructions---------------------------------------
5265 //----------Load Instructions--------------------------------------------------
5266 // Load Byte (8bit signed)
5267 instruct loadB(xRegI dst, memory mem) %{
5268 match(Set dst (LoadB mem));
5269
5270 ins_cost(125);
5271 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5272
5273 ins_encode %{
5274 __ movsbl($dst$$Register, $mem$$Address);
5275 %}
5276
5277 ins_pipe(ialu_reg_mem);
5278 %}
5279
5280 // Load Byte (8bit signed) into Long Register
5281 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5282 match(Set dst (ConvI2L (LoadB mem)));
5283 effect(KILL cr);
5284
5285 ins_cost(375);
5286 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5287 "MOV $dst.hi,$dst.lo\n\t"
5288 "SAR $dst.hi,7" %}
5289
5290 ins_encode %{
5291 __ movsbl($dst$$Register, $mem$$Address);
5292 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5293 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5294 %}
5295
5296 ins_pipe(ialu_reg_mem);
5297 %}
5298
5299 // Load Unsigned Byte (8bit UNsigned)
5300 instruct loadUB(xRegI dst, memory mem) %{
5301 match(Set dst (LoadUB mem));
5302
5303 ins_cost(125);
5304 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5305
5306 ins_encode %{
5307 __ movzbl($dst$$Register, $mem$$Address);
5308 %}
5309
5310 ins_pipe(ialu_reg_mem);
5311 %}
5312
5313 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5314 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5315 match(Set dst (ConvI2L (LoadUB mem)));
5316 effect(KILL cr);
5317
5318 ins_cost(250);
5319 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5320 "XOR $dst.hi,$dst.hi" %}
5321
5322 ins_encode %{
5323 Register Rdst = $dst$$Register;
5324 __ movzbl(Rdst, $mem$$Address);
5325 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5326 %}
5327
5328 ins_pipe(ialu_reg_mem);
5329 %}
5330
5331 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5332 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5333 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5334 effect(KILL cr);
5335
5336 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5337 "XOR $dst.hi,$dst.hi\n\t"
5338 "AND $dst.lo,$mask" %}
5339 ins_encode %{
5340 Register Rdst = $dst$$Register;
5341 __ movzbl(Rdst, $mem$$Address);
5342 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5343 __ andl(Rdst, $mask$$constant);
5344 %}
5345 ins_pipe(ialu_reg_mem);
5346 %}
5347
5348 // Load Short (16bit signed)
5349 instruct loadS(rRegI dst, memory mem) %{
5350 match(Set dst (LoadS mem));
5351
5352 ins_cost(125);
5353 format %{ "MOVSX $dst,$mem\t# short" %}
5354
5355 ins_encode %{
5356 __ movswl($dst$$Register, $mem$$Address);
5357 %}
5358
5359 ins_pipe(ialu_reg_mem);
5360 %}
5361
5362 // Load Short (16 bit signed) to Byte (8 bit signed)
5363 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5364 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5365
5366 ins_cost(125);
5367 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5368 ins_encode %{
5369 __ movsbl($dst$$Register, $mem$$Address);
5370 %}
5371 ins_pipe(ialu_reg_mem);
5372 %}
5373
5374 // Load Short (16bit signed) into Long Register
5375 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5376 match(Set dst (ConvI2L (LoadS mem)));
5377 effect(KILL cr);
5378
5379 ins_cost(375);
5380 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5381 "MOV $dst.hi,$dst.lo\n\t"
5382 "SAR $dst.hi,15" %}
5383
5384 ins_encode %{
5385 __ movswl($dst$$Register, $mem$$Address);
5386 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5387 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5388 %}
5389
5390 ins_pipe(ialu_reg_mem);
5391 %}
5392
5393 // Load Unsigned Short/Char (16bit unsigned)
5394 instruct loadUS(rRegI dst, memory mem) %{
5395 match(Set dst (LoadUS mem));
5396
5397 ins_cost(125);
5398 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5399
5400 ins_encode %{
5401 __ movzwl($dst$$Register, $mem$$Address);
5402 %}
5403
5404 ins_pipe(ialu_reg_mem);
5405 %}
5406
5407 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5408 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5409 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5410
5411 ins_cost(125);
5412 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5413 ins_encode %{
5414 __ movsbl($dst$$Register, $mem$$Address);
5415 %}
5416 ins_pipe(ialu_reg_mem);
5417 %}
5418
5419 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5420 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5421 match(Set dst (ConvI2L (LoadUS mem)));
5422 effect(KILL cr);
5423
5424 ins_cost(250);
5425 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5426 "XOR $dst.hi,$dst.hi" %}
5427
5428 ins_encode %{
5429 __ movzwl($dst$$Register, $mem$$Address);
5430 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5431 %}
5432
5433 ins_pipe(ialu_reg_mem);
5434 %}
5435
5436 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5437 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5438 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5439 effect(KILL cr);
5440
5441 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5442 "XOR $dst.hi,$dst.hi" %}
5443 ins_encode %{
5444 Register Rdst = $dst$$Register;
5445 __ movzbl(Rdst, $mem$$Address);
5446 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5447 %}
5448 ins_pipe(ialu_reg_mem);
5449 %}
5450
5451 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5452 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5453 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5454 effect(KILL cr);
5455
5456 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5457 "XOR $dst.hi,$dst.hi\n\t"
5458 "AND $dst.lo,$mask" %}
5459 ins_encode %{
5460 Register Rdst = $dst$$Register;
5461 __ movzwl(Rdst, $mem$$Address);
5462 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5463 __ andl(Rdst, $mask$$constant);
5464 %}
5465 ins_pipe(ialu_reg_mem);
5466 %}
5467
5468 // Load Integer
5469 instruct loadI(rRegI dst, memory mem) %{
5470 match(Set dst (LoadI mem));
5471
5472 ins_cost(125);
5473 format %{ "MOV $dst,$mem\t# int" %}
5474
5475 ins_encode %{
5476 __ movl($dst$$Register, $mem$$Address);
5477 %}
5478
5479 ins_pipe(ialu_reg_mem);
5480 %}
5481
5482 // Load Integer (32 bit signed) to Byte (8 bit signed)
5483 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5484 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5485
5486 ins_cost(125);
5487 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
5488 ins_encode %{
5489 __ movsbl($dst$$Register, $mem$$Address);
5490 %}
5491 ins_pipe(ialu_reg_mem);
5492 %}
5493
5494 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5495 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5496 match(Set dst (AndI (LoadI mem) mask));
5497
5498 ins_cost(125);
5499 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
5500 ins_encode %{
5501 __ movzbl($dst$$Register, $mem$$Address);
5502 %}
5503 ins_pipe(ialu_reg_mem);
5504 %}
5505
5506 // Load Integer (32 bit signed) to Short (16 bit signed)
5507 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5508 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5509
5510 ins_cost(125);
5511 format %{ "MOVSX $dst, $mem\t# int -> short" %}
5512 ins_encode %{
5513 __ movswl($dst$$Register, $mem$$Address);
5514 %}
5515 ins_pipe(ialu_reg_mem);
5516 %}
5517
5518 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5519 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5520 match(Set dst (AndI (LoadI mem) mask));
5521
5522 ins_cost(125);
5523 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
5524 ins_encode %{
5525 __ movzwl($dst$$Register, $mem$$Address);
5526 %}
5527 ins_pipe(ialu_reg_mem);
5528 %}
5529
5530 // Load Integer into Long Register
5531 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
5532 match(Set dst (ConvI2L (LoadI mem)));
5533 effect(KILL cr);
5534
5535 ins_cost(375);
5536 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
5537 "MOV $dst.hi,$dst.lo\n\t"
5538 "SAR $dst.hi,31" %}
5539
5540 ins_encode %{
5541 __ movl($dst$$Register, $mem$$Address);
5542 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5543 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
5544 %}
5545
5546 ins_pipe(ialu_reg_mem);
5547 %}
5548
5549 // Load Integer with mask 0xFF into Long Register
5550 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5551 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5552 effect(KILL cr);
5553
5554 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
5555 "XOR $dst.hi,$dst.hi" %}
5556 ins_encode %{
5557 Register Rdst = $dst$$Register;
5558 __ movzbl(Rdst, $mem$$Address);
5559 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5560 %}
5561 ins_pipe(ialu_reg_mem);
5562 %}
5563
5564 // Load Integer with mask 0xFFFF into Long Register
5565 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
5566 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5567 effect(KILL cr);
5568
5569 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
5570 "XOR $dst.hi,$dst.hi" %}
5571 ins_encode %{
5572 Register Rdst = $dst$$Register;
5573 __ movzwl(Rdst, $mem$$Address);
5574 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5575 %}
5576 ins_pipe(ialu_reg_mem);
5577 %}
5578
5579 // Load Integer with 31-bit mask into Long Register
5580 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
5581 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5582 effect(KILL cr);
5583
5584 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
5585 "XOR $dst.hi,$dst.hi\n\t"
5586 "AND $dst.lo,$mask" %}
5587 ins_encode %{
5588 Register Rdst = $dst$$Register;
5589 __ movl(Rdst, $mem$$Address);
5590 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5591 __ andl(Rdst, $mask$$constant);
5592 %}
5593 ins_pipe(ialu_reg_mem);
5594 %}
5595
5596 // Load Unsigned Integer into Long Register
5597 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
5598 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5599 effect(KILL cr);
5600
5601 ins_cost(250);
5602 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
5603 "XOR $dst.hi,$dst.hi" %}
5604
5605 ins_encode %{
5606 __ movl($dst$$Register, $mem$$Address);
5607 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5608 %}
5609
5610 ins_pipe(ialu_reg_mem);
5611 %}
5612
5613 // Load Long. Cannot clobber address while loading, so restrict address
5614 // register to ESI
5615 instruct loadL(eRegL dst, load_long_memory mem) %{
5616 predicate(!((LoadLNode*)n)->require_atomic_access());
5617 match(Set dst (LoadL mem));
5618
5619 ins_cost(250);
5620 format %{ "MOV $dst.lo,$mem\t# long\n\t"
5621 "MOV $dst.hi,$mem+4" %}
5622
5623 ins_encode %{
5624 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
5625 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
5626 __ movl($dst$$Register, Amemlo);
5627 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
5628 %}
5629
5630 ins_pipe(ialu_reg_long_mem);
5631 %}
5632
5633 // Volatile Load Long. Must be atomic, so do 64-bit FILD
5634 // then store it down to the stack and reload on the int
5635 // side.
5636 instruct loadL_volatile(stackSlotL dst, memory mem) %{
5637 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
5638 match(Set dst (LoadL mem));
5639
5640 ins_cost(200);
5641 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
5642 "FISTp $dst" %}
5643 ins_encode(enc_loadL_volatile(mem,dst));
5644 ins_pipe( fpu_reg_mem );
5645 %}
5646
5647 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
5648 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5649 match(Set dst (LoadL mem));
5650 effect(TEMP tmp);
5651 ins_cost(180);
5652 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5653 "MOVSD $dst,$tmp" %}
5654 ins_encode %{
5655 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5656 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
5657 %}
5658 ins_pipe( pipe_slow );
5659 %}
5660
5661 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
5662 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5663 match(Set dst (LoadL mem));
5664 effect(TEMP tmp);
5665 ins_cost(160);
5666 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5667 "MOVD $dst.lo,$tmp\n\t"
5668 "PSRLQ $tmp,32\n\t"
5669 "MOVD $dst.hi,$tmp" %}
5670 ins_encode %{
5671 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5672 __ movdl($dst$$Register, $tmp$$XMMRegister);
5673 __ psrlq($tmp$$XMMRegister, 32);
5674 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
5675 %}
5676 ins_pipe( pipe_slow );
5677 %}
5678
5679 // Load Range
5680 instruct loadRange(rRegI dst, memory mem) %{
5681 match(Set dst (LoadRange mem));
5682
5683 ins_cost(125);
5684 format %{ "MOV $dst,$mem" %}
5685 opcode(0x8B);
5686 ins_encode( OpcP, RegMem(dst,mem));
5687 ins_pipe( ialu_reg_mem );
5688 %}
5689
5690
5691 // Load Pointer
5692 instruct loadP(eRegP dst, memory mem) %{
5693 match(Set dst (LoadP mem));
5694
5695 ins_cost(125);
5696 format %{ "MOV $dst,$mem" %}
5697 opcode(0x8B);
5698 ins_encode( OpcP, RegMem(dst,mem));
5699 ins_pipe( ialu_reg_mem );
5700 %}
5701
5702 // Load Klass Pointer
5703 instruct loadKlass(eRegP dst, memory mem) %{
5704 match(Set dst (LoadKlass mem));
5705
5706 ins_cost(125);
5707 format %{ "MOV $dst,$mem" %}
5708 opcode(0x8B);
5709 ins_encode( OpcP, RegMem(dst,mem));
5710 ins_pipe( ialu_reg_mem );
5711 %}
5712
5713 // Load Double
5714 instruct loadDPR(regDPR dst, memory mem) %{
5715 predicate(UseSSE<=1);
5716 match(Set dst (LoadD mem));
5717
5718 ins_cost(150);
5719 format %{ "FLD_D ST,$mem\n\t"
5720 "FSTP $dst" %}
5721 opcode(0xDD); /* DD /0 */
5722 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5723 Pop_Reg_DPR(dst) );
5724 ins_pipe( fpu_reg_mem );
5725 %}
5726
5727 // Load Double to XMM
5728 instruct loadD(regD dst, memory mem) %{
5729 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
5730 match(Set dst (LoadD mem));
5731 ins_cost(145);
5732 format %{ "MOVSD $dst,$mem" %}
5733 ins_encode %{
5734 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5735 %}
5736 ins_pipe( pipe_slow );
5737 %}
5738
5739 instruct loadD_partial(regD dst, memory mem) %{
5740 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
5741 match(Set dst (LoadD mem));
5742 ins_cost(145);
5743 format %{ "MOVLPD $dst,$mem" %}
5744 ins_encode %{
5745 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5746 %}
5747 ins_pipe( pipe_slow );
5748 %}
5749
5750 // Load to XMM register (single-precision floating point)
5751 // MOVSS instruction
5752 instruct loadF(regF dst, memory mem) %{
5753 predicate(UseSSE>=1);
5754 match(Set dst (LoadF mem));
5755 ins_cost(145);
5756 format %{ "MOVSS $dst,$mem" %}
5757 ins_encode %{
5758 __ movflt ($dst$$XMMRegister, $mem$$Address);
5759 %}
5760 ins_pipe( pipe_slow );
5761 %}
5762
5763 // Load Float
5764 instruct loadFPR(regFPR dst, memory mem) %{
5765 predicate(UseSSE==0);
5766 match(Set dst (LoadF mem));
5767
5768 ins_cost(150);
5769 format %{ "FLD_S ST,$mem\n\t"
5770 "FSTP $dst" %}
5771 opcode(0xD9); /* D9 /0 */
5772 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5773 Pop_Reg_FPR(dst) );
5774 ins_pipe( fpu_reg_mem );
5775 %}
5776
5777 // Load Effective Address
5778 instruct leaP8(eRegP dst, indOffset8 mem) %{
5779 match(Set dst mem);
5780
5781 ins_cost(110);
5782 format %{ "LEA $dst,$mem" %}
5783 opcode(0x8D);
5784 ins_encode( OpcP, RegMem(dst,mem));
5785 ins_pipe( ialu_reg_reg_fat );
5786 %}
5787
5788 instruct leaP32(eRegP dst, indOffset32 mem) %{
5789 match(Set dst mem);
5790
5791 ins_cost(110);
5792 format %{ "LEA $dst,$mem" %}
5793 opcode(0x8D);
5794 ins_encode( OpcP, RegMem(dst,mem));
5795 ins_pipe( ialu_reg_reg_fat );
5796 %}
5797
5798 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
5799 match(Set dst mem);
5800
5801 ins_cost(110);
5802 format %{ "LEA $dst,$mem" %}
5803 opcode(0x8D);
5804 ins_encode( OpcP, RegMem(dst,mem));
5805 ins_pipe( ialu_reg_reg_fat );
5806 %}
5807
5808 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
5809 match(Set dst mem);
5810
5811 ins_cost(110);
5812 format %{ "LEA $dst,$mem" %}
5813 opcode(0x8D);
5814 ins_encode( OpcP, RegMem(dst,mem));
5815 ins_pipe( ialu_reg_reg_fat );
5816 %}
5817
5818 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
5819 match(Set dst mem);
5820
5821 ins_cost(110);
5822 format %{ "LEA $dst,$mem" %}
5823 opcode(0x8D);
5824 ins_encode( OpcP, RegMem(dst,mem));
5825 ins_pipe( ialu_reg_reg_fat );
5826 %}
5827
5828 // Load Constant
5829 instruct loadConI(rRegI dst, immI src) %{
5830 match(Set dst src);
5831
5832 format %{ "MOV $dst,$src" %}
5833 ins_encode( LdImmI(dst, src) );
5834 ins_pipe( ialu_reg_fat );
5835 %}
5836
5837 // Load Constant zero
5838 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
5839 match(Set dst src);
5840 effect(KILL cr);
5841
5842 ins_cost(50);
5843 format %{ "XOR $dst,$dst" %}
5844 opcode(0x33); /* + rd */
5845 ins_encode( OpcP, RegReg( dst, dst ) );
5846 ins_pipe( ialu_reg );
5847 %}
5848
5849 instruct loadConP(eRegP dst, immP src) %{
5850 match(Set dst src);
5851
5852 format %{ "MOV $dst,$src" %}
5853 opcode(0xB8); /* + rd */
5854 ins_encode( LdImmP(dst, src) );
5855 ins_pipe( ialu_reg_fat );
5856 %}
5857
5858 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
5859 match(Set dst src);
5860 effect(KILL cr);
5861 ins_cost(200);
5862 format %{ "MOV $dst.lo,$src.lo\n\t"
5863 "MOV $dst.hi,$src.hi" %}
5864 opcode(0xB8);
5865 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
5866 ins_pipe( ialu_reg_long_fat );
5867 %}
5868
5869 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
5870 match(Set dst src);
5871 effect(KILL cr);
5872 ins_cost(150);
5873 format %{ "XOR $dst.lo,$dst.lo\n\t"
5874 "XOR $dst.hi,$dst.hi" %}
5875 opcode(0x33,0x33);
5876 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
5877 ins_pipe( ialu_reg_long );
5878 %}
5879
5880 // The instruction usage is guarded by predicate in operand immFPR().
5881 instruct loadConFPR(regFPR dst, immFPR con) %{
5882 match(Set dst con);
5883 ins_cost(125);
5884 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
5885 "FSTP $dst" %}
5886 ins_encode %{
5887 __ fld_s($constantaddress($con));
5888 __ fstp_d($dst$$reg);
5889 %}
5890 ins_pipe(fpu_reg_con);
5891 %}
5892
5893 // The instruction usage is guarded by predicate in operand immFPR0().
5894 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
5895 match(Set dst con);
5896 ins_cost(125);
5897 format %{ "FLDZ ST\n\t"
5898 "FSTP $dst" %}
5899 ins_encode %{
5900 __ fldz();
5901 __ fstp_d($dst$$reg);
5902 %}
5903 ins_pipe(fpu_reg_con);
5904 %}
5905
5906 // The instruction usage is guarded by predicate in operand immFPR1().
5907 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
5908 match(Set dst con);
5909 ins_cost(125);
5910 format %{ "FLD1 ST\n\t"
5911 "FSTP $dst" %}
5912 ins_encode %{
5913 __ fld1();
5914 __ fstp_d($dst$$reg);
5915 %}
5916 ins_pipe(fpu_reg_con);
5917 %}
5918
5919 // The instruction usage is guarded by predicate in operand immF().
5920 instruct loadConF(regF dst, immF con) %{
5921 match(Set dst con);
5922 ins_cost(125);
5923 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
5924 ins_encode %{
5925 __ movflt($dst$$XMMRegister, $constantaddress($con));
5926 %}
5927 ins_pipe(pipe_slow);
5928 %}
5929
5930 // The instruction usage is guarded by predicate in operand immF0().
5931 instruct loadConF0(regF dst, immF0 src) %{
5932 match(Set dst src);
5933 ins_cost(100);
5934 format %{ "XORPS $dst,$dst\t# float 0.0" %}
5935 ins_encode %{
5936 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5937 %}
5938 ins_pipe(pipe_slow);
5939 %}
5940
5941 // The instruction usage is guarded by predicate in operand immDPR().
5942 instruct loadConDPR(regDPR dst, immDPR con) %{
5943 match(Set dst con);
5944 ins_cost(125);
5945
5946 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
5947 "FSTP $dst" %}
5948 ins_encode %{
5949 __ fld_d($constantaddress($con));
5950 __ fstp_d($dst$$reg);
5951 %}
5952 ins_pipe(fpu_reg_con);
5953 %}
5954
5955 // The instruction usage is guarded by predicate in operand immDPR0().
5956 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
5957 match(Set dst con);
5958 ins_cost(125);
5959
5960 format %{ "FLDZ ST\n\t"
5961 "FSTP $dst" %}
5962 ins_encode %{
5963 __ fldz();
5964 __ fstp_d($dst$$reg);
5965 %}
5966 ins_pipe(fpu_reg_con);
5967 %}
5968
5969 // The instruction usage is guarded by predicate in operand immDPR1().
5970 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
5971 match(Set dst con);
5972 ins_cost(125);
5973
5974 format %{ "FLD1 ST\n\t"
5975 "FSTP $dst" %}
5976 ins_encode %{
5977 __ fld1();
5978 __ fstp_d($dst$$reg);
5979 %}
5980 ins_pipe(fpu_reg_con);
5981 %}
5982
5983 // The instruction usage is guarded by predicate in operand immD().
5984 instruct loadConD(regD dst, immD con) %{
5985 match(Set dst con);
5986 ins_cost(125);
5987 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
5988 ins_encode %{
5989 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5990 %}
5991 ins_pipe(pipe_slow);
5992 %}
5993
5994 // The instruction usage is guarded by predicate in operand immD0().
5995 instruct loadConD0(regD dst, immD0 src) %{
5996 match(Set dst src);
5997 ins_cost(100);
5998 format %{ "XORPD $dst,$dst\t# double 0.0" %}
5999 ins_encode %{
6000 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6001 %}
6002 ins_pipe( pipe_slow );
6003 %}
6004
6005 // Load Stack Slot
6006 instruct loadSSI(rRegI dst, stackSlotI src) %{
6007 match(Set dst src);
6008 ins_cost(125);
6009
6010 format %{ "MOV $dst,$src" %}
6011 opcode(0x8B);
6012 ins_encode( OpcP, RegMem(dst,src));
6013 ins_pipe( ialu_reg_mem );
6014 %}
6015
6016 instruct loadSSL(eRegL dst, stackSlotL src) %{
6017 match(Set dst src);
6018
6019 ins_cost(200);
6020 format %{ "MOV $dst,$src.lo\n\t"
6021 "MOV $dst+4,$src.hi" %}
6022 opcode(0x8B, 0x8B);
6023 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6024 ins_pipe( ialu_mem_long_reg );
6025 %}
6026
6027 // Load Stack Slot
6028 instruct loadSSP(eRegP dst, stackSlotP src) %{
6029 match(Set dst src);
6030 ins_cost(125);
6031
6032 format %{ "MOV $dst,$src" %}
6033 opcode(0x8B);
6034 ins_encode( OpcP, RegMem(dst,src));
6035 ins_pipe( ialu_reg_mem );
6036 %}
6037
6038 // Load Stack Slot
6039 instruct loadSSF(regFPR dst, stackSlotF src) %{
6040 match(Set dst src);
6041 ins_cost(125);
6042
6043 format %{ "FLD_S $src\n\t"
6044 "FSTP $dst" %}
6045 opcode(0xD9); /* D9 /0, FLD m32real */
6046 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6047 Pop_Reg_FPR(dst) );
6048 ins_pipe( fpu_reg_mem );
6049 %}
6050
6051 // Load Stack Slot
6052 instruct loadSSD(regDPR dst, stackSlotD src) %{
6053 match(Set dst src);
6054 ins_cost(125);
6055
6056 format %{ "FLD_D $src\n\t"
6057 "FSTP $dst" %}
6058 opcode(0xDD); /* DD /0, FLD m64real */
6059 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6060 Pop_Reg_DPR(dst) );
6061 ins_pipe( fpu_reg_mem );
6062 %}
6063
6064 // Prefetch instructions for allocation.
6065 // Must be safe to execute with invalid address (cannot fault).
6066
6067 instruct prefetchAlloc0( memory mem ) %{
6068 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6069 match(PrefetchAllocation mem);
6070 ins_cost(0);
6071 size(0);
6072 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6073 ins_encode();
6074 ins_pipe(empty);
6075 %}
6076
6077 instruct prefetchAlloc( memory mem ) %{
6078 predicate(AllocatePrefetchInstr==3);
6079 match( PrefetchAllocation mem );
6080 ins_cost(100);
6081
6082 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6083 ins_encode %{
6084 __ prefetchw($mem$$Address);
6085 %}
6086 ins_pipe(ialu_mem);
6087 %}
6088
6089 instruct prefetchAllocNTA( memory mem ) %{
6090 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6091 match(PrefetchAllocation mem);
6092 ins_cost(100);
6093
6094 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6095 ins_encode %{
6096 __ prefetchnta($mem$$Address);
6097 %}
6098 ins_pipe(ialu_mem);
6099 %}
6100
6101 instruct prefetchAllocT0( memory mem ) %{
6102 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6103 match(PrefetchAllocation mem);
6104 ins_cost(100);
6105
6106 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6107 ins_encode %{
6108 __ prefetcht0($mem$$Address);
6109 %}
6110 ins_pipe(ialu_mem);
6111 %}
6112
6113 instruct prefetchAllocT2( memory mem ) %{
6114 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6115 match(PrefetchAllocation mem);
6116 ins_cost(100);
6117
6118 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6119 ins_encode %{
6120 __ prefetcht2($mem$$Address);
6121 %}
6122 ins_pipe(ialu_mem);
6123 %}
6124
6125 //----------Store Instructions-------------------------------------------------
6126
6127 // Store Byte
6128 instruct storeB(memory mem, xRegI src) %{
6129 match(Set mem (StoreB mem src));
6130
6131 ins_cost(125);
6132 format %{ "MOV8 $mem,$src" %}
6133 opcode(0x88);
6134 ins_encode( OpcP, RegMem( src, mem ) );
6135 ins_pipe( ialu_mem_reg );
6136 %}
6137
6138 // Store Char/Short
6139 instruct storeC(memory mem, rRegI src) %{
6140 match(Set mem (StoreC mem src));
6141
6142 ins_cost(125);
6143 format %{ "MOV16 $mem,$src" %}
6144 opcode(0x89, 0x66);
6145 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6146 ins_pipe( ialu_mem_reg );
6147 %}
6148
6149 // Store Integer
6150 instruct storeI(memory mem, rRegI src) %{
6151 match(Set mem (StoreI mem src));
6152
6153 ins_cost(125);
6154 format %{ "MOV $mem,$src" %}
6155 opcode(0x89);
6156 ins_encode( OpcP, RegMem( src, mem ) );
6157 ins_pipe( ialu_mem_reg );
6158 %}
6159
6160 // Store Long
6161 instruct storeL(long_memory mem, eRegL src) %{
6162 predicate(!((StoreLNode*)n)->require_atomic_access());
6163 match(Set mem (StoreL mem src));
6164
6165 ins_cost(200);
6166 format %{ "MOV $mem,$src.lo\n\t"
6167 "MOV $mem+4,$src.hi" %}
6168 opcode(0x89, 0x89);
6169 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6170 ins_pipe( ialu_mem_long_reg );
6171 %}
6172
6173 // Store Long to Integer
6174 instruct storeL2I(memory mem, eRegL src) %{
6175 match(Set mem (StoreI mem (ConvL2I src)));
6176
6177 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6178 ins_encode %{
6179 __ movl($mem$$Address, $src$$Register);
6180 %}
6181 ins_pipe(ialu_mem_reg);
6182 %}
6183
6184 // Volatile Store Long. Must be atomic, so move it into
6185 // the FP TOS and then do a 64-bit FIST. Has to probe the
6186 // target address before the store (for null-ptr checks)
6187 // so the memory operand is used twice in the encoding.
6188 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6189 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6190 match(Set mem (StoreL mem src));
6191 effect( KILL cr );
6192 ins_cost(400);
6193 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6194 "FILD $src\n\t"
6195 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6196 opcode(0x3B);
6197 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6198 ins_pipe( fpu_reg_mem );
6199 %}
6200
6201 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6202 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6203 match(Set mem (StoreL mem src));
6204 effect( TEMP tmp, KILL cr );
6205 ins_cost(380);
6206 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6207 "MOVSD $tmp,$src\n\t"
6208 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6209 ins_encode %{
6210 __ cmpl(rax, $mem$$Address);
6211 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6212 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6213 %}
6214 ins_pipe( pipe_slow );
6215 %}
6216
6217 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6218 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6219 match(Set mem (StoreL mem src));
6220 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6221 ins_cost(360);
6222 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6223 "MOVD $tmp,$src.lo\n\t"
6224 "MOVD $tmp2,$src.hi\n\t"
6225 "PUNPCKLDQ $tmp,$tmp2\n\t"
6226 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6227 ins_encode %{
6228 __ cmpl(rax, $mem$$Address);
6229 __ movdl($tmp$$XMMRegister, $src$$Register);
6230 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6231 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6232 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6233 %}
6234 ins_pipe( pipe_slow );
6235 %}
6236
6237 // Store Pointer; for storing unknown oops and raw pointers
6238 instruct storeP(memory mem, anyRegP src) %{
6239 match(Set mem (StoreP mem src));
6240
6241 ins_cost(125);
6242 format %{ "MOV $mem,$src" %}
6243 opcode(0x89);
6244 ins_encode( OpcP, RegMem( src, mem ) );
6245 ins_pipe( ialu_mem_reg );
6246 %}
6247
6248 // Store Integer Immediate
6249 instruct storeImmI(memory mem, immI src) %{
6250 match(Set mem (StoreI mem src));
6251
6252 ins_cost(150);
6253 format %{ "MOV $mem,$src" %}
6254 opcode(0xC7); /* C7 /0 */
6255 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6256 ins_pipe( ialu_mem_imm );
6257 %}
6258
6259 // Store Short/Char Immediate
6260 instruct storeImmI16(memory mem, immI16 src) %{
6261 predicate(UseStoreImmI16);
6262 match(Set mem (StoreC mem src));
6263
6264 ins_cost(150);
6265 format %{ "MOV16 $mem,$src" %}
6266 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6267 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6268 ins_pipe( ialu_mem_imm );
6269 %}
6270
6271 // Store Pointer Immediate; null pointers or constant oops that do not
6272 // need card-mark barriers.
6273 instruct storeImmP(memory mem, immP src) %{
6274 match(Set mem (StoreP mem src));
6275
6276 ins_cost(150);
6277 format %{ "MOV $mem,$src" %}
6278 opcode(0xC7); /* C7 /0 */
6279 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6280 ins_pipe( ialu_mem_imm );
6281 %}
6282
6283 // Store Byte Immediate
6284 instruct storeImmB(memory mem, immI8 src) %{
6285 match(Set mem (StoreB mem src));
6286
6287 ins_cost(150);
6288 format %{ "MOV8 $mem,$src" %}
6289 opcode(0xC6); /* C6 /0 */
6290 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6291 ins_pipe( ialu_mem_imm );
6292 %}
6293
6294 // Store CMS card-mark Immediate
6295 instruct storeImmCM(memory mem, immI8 src) %{
6296 match(Set mem (StoreCM mem src));
6297
6298 ins_cost(150);
6299 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6300 opcode(0xC6); /* C6 /0 */
6301 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6302 ins_pipe( ialu_mem_imm );
6303 %}
6304
6305 // Store Double
6306 instruct storeDPR( memory mem, regDPR1 src) %{
6307 predicate(UseSSE<=1);
6308 match(Set mem (StoreD mem src));
6309
6310 ins_cost(100);
6311 format %{ "FST_D $mem,$src" %}
6312 opcode(0xDD); /* DD /2 */
6313 ins_encode( enc_FPR_store(mem,src) );
6314 ins_pipe( fpu_mem_reg );
6315 %}
6316
6317 // Store double does rounding on x86
6318 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6319 predicate(UseSSE<=1);
6320 match(Set mem (StoreD mem (RoundDouble src)));
6321
6322 ins_cost(100);
6323 format %{ "FST_D $mem,$src\t# round" %}
6324 opcode(0xDD); /* DD /2 */
6325 ins_encode( enc_FPR_store(mem,src) );
6326 ins_pipe( fpu_mem_reg );
6327 %}
6328
6329 // Store XMM register to memory (double-precision floating points)
6330 // MOVSD instruction
6331 instruct storeD(memory mem, regD src) %{
6332 predicate(UseSSE>=2);
6333 match(Set mem (StoreD mem src));
6334 ins_cost(95);
6335 format %{ "MOVSD $mem,$src" %}
6336 ins_encode %{
6337 __ movdbl($mem$$Address, $src$$XMMRegister);
6338 %}
6339 ins_pipe( pipe_slow );
6340 %}
6341
6342 // Store XMM register to memory (single-precision floating point)
6343 // MOVSS instruction
6344 instruct storeF(memory mem, regF src) %{
6345 predicate(UseSSE>=1);
6346 match(Set mem (StoreF mem src));
6347 ins_cost(95);
6348 format %{ "MOVSS $mem,$src" %}
6349 ins_encode %{
6350 __ movflt($mem$$Address, $src$$XMMRegister);
6351 %}
6352 ins_pipe( pipe_slow );
6353 %}
6354
6355 // Store Float
6356 instruct storeFPR( memory mem, regFPR1 src) %{
6357 predicate(UseSSE==0);
6358 match(Set mem (StoreF mem src));
6359
6360 ins_cost(100);
6361 format %{ "FST_S $mem,$src" %}
6362 opcode(0xD9); /* D9 /2 */
6363 ins_encode( enc_FPR_store(mem,src) );
6364 ins_pipe( fpu_mem_reg );
6365 %}
6366
6367 // Store Float does rounding on x86
6368 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
6369 predicate(UseSSE==0);
6370 match(Set mem (StoreF mem (RoundFloat src)));
6371
6372 ins_cost(100);
6373 format %{ "FST_S $mem,$src\t# round" %}
6374 opcode(0xD9); /* D9 /2 */
6375 ins_encode( enc_FPR_store(mem,src) );
6376 ins_pipe( fpu_mem_reg );
6377 %}
6378
6379 // Store Float does rounding on x86
6380 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
6381 predicate(UseSSE<=1);
6382 match(Set mem (StoreF mem (ConvD2F src)));
6383
6384 ins_cost(100);
6385 format %{ "FST_S $mem,$src\t# D-round" %}
6386 opcode(0xD9); /* D9 /2 */
6387 ins_encode( enc_FPR_store(mem,src) );
6388 ins_pipe( fpu_mem_reg );
6389 %}
6390
6391 // Store immediate Float value (it is faster than store from FPU register)
6392 // The instruction usage is guarded by predicate in operand immFPR().
6393 instruct storeFPR_imm( memory mem, immFPR src) %{
6394 match(Set mem (StoreF mem src));
6395
6396 ins_cost(50);
6397 format %{ "MOV $mem,$src\t# store float" %}
6398 opcode(0xC7); /* C7 /0 */
6399 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
6400 ins_pipe( ialu_mem_imm );
6401 %}
6402
6403 // Store immediate Float value (it is faster than store from XMM register)
6404 // The instruction usage is guarded by predicate in operand immF().
6405 instruct storeF_imm( memory mem, immF src) %{
6406 match(Set mem (StoreF mem src));
6407
6408 ins_cost(50);
6409 format %{ "MOV $mem,$src\t# store float" %}
6410 opcode(0xC7); /* C7 /0 */
6411 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
6412 ins_pipe( ialu_mem_imm );
6413 %}
6414
6415 // Store Integer to stack slot
6416 instruct storeSSI(stackSlotI dst, rRegI src) %{
6417 match(Set dst src);
6418
6419 ins_cost(100);
6420 format %{ "MOV $dst,$src" %}
6421 opcode(0x89);
6422 ins_encode( OpcPRegSS( dst, src ) );
6423 ins_pipe( ialu_mem_reg );
6424 %}
6425
6426 // Store Integer to stack slot
6427 instruct storeSSP(stackSlotP dst, eRegP src) %{
6428 match(Set dst src);
6429
6430 ins_cost(100);
6431 format %{ "MOV $dst,$src" %}
6432 opcode(0x89);
6433 ins_encode( OpcPRegSS( dst, src ) );
6434 ins_pipe( ialu_mem_reg );
6435 %}
6436
6437 // Store Long to stack slot
6438 instruct storeSSL(stackSlotL dst, eRegL src) %{
6439 match(Set dst src);
6440
6441 ins_cost(200);
6442 format %{ "MOV $dst,$src.lo\n\t"
6443 "MOV $dst+4,$src.hi" %}
6444 opcode(0x89, 0x89);
6445 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
6446 ins_pipe( ialu_mem_long_reg );
6447 %}
6448
6449 //----------MemBar Instructions-----------------------------------------------
6450 // Memory barrier flavors
6451
6452 instruct membar_acquire() %{
6453 match(MemBarAcquire);
6454 match(LoadFence);
6455 ins_cost(400);
6456
6457 size(0);
6458 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6459 ins_encode();
6460 ins_pipe(empty);
6461 %}
6462
6463 instruct membar_acquire_lock() %{
6464 match(MemBarAcquireLock);
6465 ins_cost(0);
6466
6467 size(0);
6468 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6469 ins_encode( );
6470 ins_pipe(empty);
6471 %}
6472
6473 instruct membar_release() %{
6474 match(MemBarRelease);
6475 match(StoreFence);
6476 ins_cost(400);
6477
6478 size(0);
6479 format %{ "MEMBAR-release ! (empty encoding)" %}
6480 ins_encode( );
6481 ins_pipe(empty);
6482 %}
6483
6484 instruct membar_release_lock() %{
6485 match(MemBarReleaseLock);
6486 ins_cost(0);
6487
6488 size(0);
6489 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6490 ins_encode( );
6491 ins_pipe(empty);
6492 %}
6493
6494 instruct membar_volatile(eFlagsReg cr) %{
6495 match(MemBarVolatile);
6496 effect(KILL cr);
6497 ins_cost(400);
6498
6499 format %{
6500 $$template
6501 if (os::is_MP()) {
6502 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
6503 } else {
6504 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6505 }
6506 %}
6507 ins_encode %{
6508 __ membar(Assembler::StoreLoad);
6509 %}
6510 ins_pipe(pipe_slow);
6511 %}
6512
6513 instruct unnecessary_membar_volatile() %{
6514 match(MemBarVolatile);
6515 predicate(Matcher::post_store_load_barrier(n));
6516 ins_cost(0);
6517
6518 size(0);
6519 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6520 ins_encode( );
6521 ins_pipe(empty);
6522 %}
6523
6524 instruct membar_storestore() %{
6525 match(MemBarStoreStore);
6526 ins_cost(0);
6527
6528 size(0);
6529 format %{ "MEMBAR-storestore (empty encoding)" %}
6530 ins_encode( );
6531 ins_pipe(empty);
6532 %}
6533
6534 //----------Move Instructions--------------------------------------------------
6535 instruct castX2P(eAXRegP dst, eAXRegI src) %{
6536 match(Set dst (CastX2P src));
6537 format %{ "# X2P $dst, $src" %}
6538 ins_encode( /*empty encoding*/ );
6539 ins_cost(0);
6540 ins_pipe(empty);
6541 %}
6542
6543 instruct castP2X(rRegI dst, eRegP src ) %{
6544 match(Set dst (CastP2X src));
6545 ins_cost(50);
6546 format %{ "MOV $dst, $src\t# CastP2X" %}
6547 ins_encode( enc_Copy( dst, src) );
6548 ins_pipe( ialu_reg_reg );
6549 %}
6550
6551 //----------Conditional Move---------------------------------------------------
6552 // Conditional move
6553 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
6554 predicate(!VM_Version::supports_cmov() );
6555 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6556 ins_cost(200);
6557 format %{ "J$cop,us skip\t# signed cmove\n\t"
6558 "MOV $dst,$src\n"
6559 "skip:" %}
6560 ins_encode %{
6561 Label Lskip;
6562 // Invert sense of branch from sense of CMOV
6563 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6564 __ movl($dst$$Register, $src$$Register);
6565 __ bind(Lskip);
6566 %}
6567 ins_pipe( pipe_cmov_reg );
6568 %}
6569
6570 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
6571 predicate(!VM_Version::supports_cmov() );
6572 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6573 ins_cost(200);
6574 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
6575 "MOV $dst,$src\n"
6576 "skip:" %}
6577 ins_encode %{
6578 Label Lskip;
6579 // Invert sense of branch from sense of CMOV
6580 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6581 __ movl($dst$$Register, $src$$Register);
6582 __ bind(Lskip);
6583 %}
6584 ins_pipe( pipe_cmov_reg );
6585 %}
6586
6587 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
6588 predicate(VM_Version::supports_cmov() );
6589 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6590 ins_cost(200);
6591 format %{ "CMOV$cop $dst,$src" %}
6592 opcode(0x0F,0x40);
6593 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6594 ins_pipe( pipe_cmov_reg );
6595 %}
6596
6597 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
6598 predicate(VM_Version::supports_cmov() );
6599 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6600 ins_cost(200);
6601 format %{ "CMOV$cop $dst,$src" %}
6602 opcode(0x0F,0x40);
6603 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6604 ins_pipe( pipe_cmov_reg );
6605 %}
6606
6607 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
6608 predicate(VM_Version::supports_cmov() );
6609 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6610 ins_cost(200);
6611 expand %{
6612 cmovI_regU(cop, cr, dst, src);
6613 %}
6614 %}
6615
6616 // Conditional move
6617 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
6618 predicate(VM_Version::supports_cmov() );
6619 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6620 ins_cost(250);
6621 format %{ "CMOV$cop $dst,$src" %}
6622 opcode(0x0F,0x40);
6623 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6624 ins_pipe( pipe_cmov_mem );
6625 %}
6626
6627 // Conditional move
6628 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
6629 predicate(VM_Version::supports_cmov() );
6630 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6631 ins_cost(250);
6632 format %{ "CMOV$cop $dst,$src" %}
6633 opcode(0x0F,0x40);
6634 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6635 ins_pipe( pipe_cmov_mem );
6636 %}
6637
6638 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
6639 predicate(VM_Version::supports_cmov() );
6640 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6641 ins_cost(250);
6642 expand %{
6643 cmovI_memU(cop, cr, dst, src);
6644 %}
6645 %}
6646
6647 // Conditional move
6648 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6649 predicate(VM_Version::supports_cmov() );
6650 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6651 ins_cost(200);
6652 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6653 opcode(0x0F,0x40);
6654 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6655 ins_pipe( pipe_cmov_reg );
6656 %}
6657
6658 // Conditional move (non-P6 version)
6659 // Note: a CMoveP is generated for stubs and native wrappers
6660 // regardless of whether we are on a P6, so we
6661 // emulate a cmov here
6662 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6663 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6664 ins_cost(300);
6665 format %{ "Jn$cop skip\n\t"
6666 "MOV $dst,$src\t# pointer\n"
6667 "skip:" %}
6668 opcode(0x8b);
6669 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
6670 ins_pipe( pipe_cmov_reg );
6671 %}
6672
6673 // Conditional move
6674 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
6675 predicate(VM_Version::supports_cmov() );
6676 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6677 ins_cost(200);
6678 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6679 opcode(0x0F,0x40);
6680 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6681 ins_pipe( pipe_cmov_reg );
6682 %}
6683
6684 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
6685 predicate(VM_Version::supports_cmov() );
6686 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6687 ins_cost(200);
6688 expand %{
6689 cmovP_regU(cop, cr, dst, src);
6690 %}
6691 %}
6692
6693 // DISABLED: Requires the ADLC to emit a bottom_type call that
6694 // correctly meets the two pointer arguments; one is an incoming
6695 // register but the other is a memory operand. ALSO appears to
6696 // be buggy with implicit null checks.
6697 //
6698 //// Conditional move
6699 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
6700 // predicate(VM_Version::supports_cmov() );
6701 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6702 // ins_cost(250);
6703 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6704 // opcode(0x0F,0x40);
6705 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6706 // ins_pipe( pipe_cmov_mem );
6707 //%}
6708 //
6709 //// Conditional move
6710 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
6711 // predicate(VM_Version::supports_cmov() );
6712 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6713 // ins_cost(250);
6714 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6715 // opcode(0x0F,0x40);
6716 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6717 // ins_pipe( pipe_cmov_mem );
6718 //%}
6719
6720 // Conditional move
6721 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
6722 predicate(UseSSE<=1);
6723 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6724 ins_cost(200);
6725 format %{ "FCMOV$cop $dst,$src\t# double" %}
6726 opcode(0xDA);
6727 ins_encode( enc_cmov_dpr(cop,src) );
6728 ins_pipe( pipe_cmovDPR_reg );
6729 %}
6730
6731 // Conditional move
6732 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
6733 predicate(UseSSE==0);
6734 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6735 ins_cost(200);
6736 format %{ "FCMOV$cop $dst,$src\t# float" %}
6737 opcode(0xDA);
6738 ins_encode( enc_cmov_dpr(cop,src) );
6739 ins_pipe( pipe_cmovDPR_reg );
6740 %}
6741
6742 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6743 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
6744 predicate(UseSSE<=1);
6745 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6746 ins_cost(200);
6747 format %{ "Jn$cop skip\n\t"
6748 "MOV $dst,$src\t# double\n"
6749 "skip:" %}
6750 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6751 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
6752 ins_pipe( pipe_cmovDPR_reg );
6753 %}
6754
6755 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6756 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
6757 predicate(UseSSE==0);
6758 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6759 ins_cost(200);
6760 format %{ "Jn$cop skip\n\t"
6761 "MOV $dst,$src\t# float\n"
6762 "skip:" %}
6763 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6764 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
6765 ins_pipe( pipe_cmovDPR_reg );
6766 %}
6767
6768 // No CMOVE with SSE/SSE2
6769 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
6770 predicate (UseSSE>=1);
6771 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6772 ins_cost(200);
6773 format %{ "Jn$cop skip\n\t"
6774 "MOVSS $dst,$src\t# float\n"
6775 "skip:" %}
6776 ins_encode %{
6777 Label skip;
6778 // Invert sense of branch from sense of CMOV
6779 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6780 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6781 __ bind(skip);
6782 %}
6783 ins_pipe( pipe_slow );
6784 %}
6785
6786 // No CMOVE with SSE/SSE2
6787 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
6788 predicate (UseSSE>=2);
6789 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6790 ins_cost(200);
6791 format %{ "Jn$cop skip\n\t"
6792 "MOVSD $dst,$src\t# float\n"
6793 "skip:" %}
6794 ins_encode %{
6795 Label skip;
6796 // Invert sense of branch from sense of CMOV
6797 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6798 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6799 __ bind(skip);
6800 %}
6801 ins_pipe( pipe_slow );
6802 %}
6803
6804 // unsigned version
6805 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
6806 predicate (UseSSE>=1);
6807 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6808 ins_cost(200);
6809 format %{ "Jn$cop skip\n\t"
6810 "MOVSS $dst,$src\t# float\n"
6811 "skip:" %}
6812 ins_encode %{
6813 Label skip;
6814 // Invert sense of branch from sense of CMOV
6815 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6816 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6817 __ bind(skip);
6818 %}
6819 ins_pipe( pipe_slow );
6820 %}
6821
6822 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
6823 predicate (UseSSE>=1);
6824 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6825 ins_cost(200);
6826 expand %{
6827 fcmovF_regU(cop, cr, dst, src);
6828 %}
6829 %}
6830
6831 // unsigned version
6832 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
6833 predicate (UseSSE>=2);
6834 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6835 ins_cost(200);
6836 format %{ "Jn$cop skip\n\t"
6837 "MOVSD $dst,$src\t# float\n"
6838 "skip:" %}
6839 ins_encode %{
6840 Label skip;
6841 // Invert sense of branch from sense of CMOV
6842 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6843 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6844 __ bind(skip);
6845 %}
6846 ins_pipe( pipe_slow );
6847 %}
6848
6849 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
6850 predicate (UseSSE>=2);
6851 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6852 ins_cost(200);
6853 expand %{
6854 fcmovD_regU(cop, cr, dst, src);
6855 %}
6856 %}
6857
6858 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
6859 predicate(VM_Version::supports_cmov() );
6860 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6861 ins_cost(200);
6862 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
6863 "CMOV$cop $dst.hi,$src.hi" %}
6864 opcode(0x0F,0x40);
6865 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
6866 ins_pipe( pipe_cmov_reg_long );
6867 %}
6868
6869 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
6870 predicate(VM_Version::supports_cmov() );
6871 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6872 ins_cost(200);
6873 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
6874 "CMOV$cop $dst.hi,$src.hi" %}
6875 opcode(0x0F,0x40);
6876 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
6877 ins_pipe( pipe_cmov_reg_long );
6878 %}
6879
6880 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
6881 predicate(VM_Version::supports_cmov() );
6882 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6883 ins_cost(200);
6884 expand %{
6885 cmovL_regU(cop, cr, dst, src);
6886 %}
6887 %}
6888
6889 //----------Arithmetic Instructions--------------------------------------------
6890 //----------Addition Instructions----------------------------------------------
6891
6892 // Integer Addition Instructions
6893 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
6894 match(Set dst (AddI dst src));
6895 effect(KILL cr);
6896
6897 size(2);
6898 format %{ "ADD $dst,$src" %}
6899 opcode(0x03);
6900 ins_encode( OpcP, RegReg( dst, src) );
6901 ins_pipe( ialu_reg_reg );
6902 %}
6903
6904 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
6905 match(Set dst (AddI dst src));
6906 effect(KILL cr);
6907
6908 format %{ "ADD $dst,$src" %}
6909 opcode(0x81, 0x00); /* /0 id */
6910 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
6911 ins_pipe( ialu_reg );
6912 %}
6913
6914 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
6915 predicate(UseIncDec);
6916 match(Set dst (AddI dst src));
6917 effect(KILL cr);
6918
6919 size(1);
6920 format %{ "INC $dst" %}
6921 opcode(0x40); /* */
6922 ins_encode( Opc_plus( primary, dst ) );
6923 ins_pipe( ialu_reg );
6924 %}
6925
6926 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
6927 match(Set dst (AddI src0 src1));
6928 ins_cost(110);
6929
6930 format %{ "LEA $dst,[$src0 + $src1]" %}
6931 opcode(0x8D); /* 0x8D /r */
6932 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
6933 ins_pipe( ialu_reg_reg );
6934 %}
6935
6936 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
6937 match(Set dst (AddP src0 src1));
6938 ins_cost(110);
6939
6940 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
6941 opcode(0x8D); /* 0x8D /r */
6942 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
6943 ins_pipe( ialu_reg_reg );
6944 %}
6945
6946 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
6947 predicate(UseIncDec);
6948 match(Set dst (AddI dst src));
6949 effect(KILL cr);
6950
6951 size(1);
6952 format %{ "DEC $dst" %}
6953 opcode(0x48); /* */
6954 ins_encode( Opc_plus( primary, dst ) );
6955 ins_pipe( ialu_reg );
6956 %}
6957
6958 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
6959 match(Set dst (AddP dst src));
6960 effect(KILL cr);
6961
6962 size(2);
6963 format %{ "ADD $dst,$src" %}
6964 opcode(0x03);
6965 ins_encode( OpcP, RegReg( dst, src) );
6966 ins_pipe( ialu_reg_reg );
6967 %}
6968
6969 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
6970 match(Set dst (AddP dst src));
6971 effect(KILL cr);
6972
6973 format %{ "ADD $dst,$src" %}
6974 opcode(0x81,0x00); /* Opcode 81 /0 id */
6975 // ins_encode( RegImm( dst, src) );
6976 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
6977 ins_pipe( ialu_reg );
6978 %}
6979
6980 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
6981 match(Set dst (AddI dst (LoadI src)));
6982 effect(KILL cr);
6983
6984 ins_cost(125);
6985 format %{ "ADD $dst,$src" %}
6986 opcode(0x03);
6987 ins_encode( OpcP, RegMem( dst, src) );
6988 ins_pipe( ialu_reg_mem );
6989 %}
6990
6991 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
6992 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6993 effect(KILL cr);
6994
6995 ins_cost(150);
6996 format %{ "ADD $dst,$src" %}
6997 opcode(0x01); /* Opcode 01 /r */
6998 ins_encode( OpcP, RegMem( src, dst ) );
6999 ins_pipe( ialu_mem_reg );
7000 %}
7001
7002 // Add Memory with Immediate
7003 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7004 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7005 effect(KILL cr);
7006
7007 ins_cost(125);
7008 format %{ "ADD $dst,$src" %}
7009 opcode(0x81); /* Opcode 81 /0 id */
7010 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7011 ins_pipe( ialu_mem_imm );
7012 %}
7013
7014 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7015 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7016 effect(KILL cr);
7017
7018 ins_cost(125);
7019 format %{ "INC $dst" %}
7020 opcode(0xFF); /* Opcode FF /0 */
7021 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7022 ins_pipe( ialu_mem_imm );
7023 %}
7024
7025 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7026 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7027 effect(KILL cr);
7028
7029 ins_cost(125);
7030 format %{ "DEC $dst" %}
7031 opcode(0xFF); /* Opcode FF /1 */
7032 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7033 ins_pipe( ialu_mem_imm );
7034 %}
7035
7036
7037 instruct checkCastPP( eRegP dst ) %{
7038 match(Set dst (CheckCastPP dst));
7039
7040 size(0);
7041 format %{ "#checkcastPP of $dst" %}
7042 ins_encode( /*empty encoding*/ );
7043 ins_pipe( empty );
7044 %}
7045
7046 instruct castPP( eRegP dst ) %{
7047 match(Set dst (CastPP dst));
7048 format %{ "#castPP of $dst" %}
7049 ins_encode( /*empty encoding*/ );
7050 ins_pipe( empty );
7051 %}
7052
7053 instruct castII( rRegI dst ) %{
7054 match(Set dst (CastII dst));
7055 format %{ "#castII of $dst" %}
7056 ins_encode( /*empty encoding*/ );
7057 ins_cost(0);
7058 ins_pipe( empty );
7059 %}
7060
7061
7062 // Load-locked - same as a regular pointer load when used with compare-swap
7063 instruct loadPLocked(eRegP dst, memory mem) %{
7064 match(Set dst (LoadPLocked mem));
7065
7066 ins_cost(125);
7067 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7068 opcode(0x8B);
7069 ins_encode( OpcP, RegMem(dst,mem));
7070 ins_pipe( ialu_reg_mem );
7071 %}
7072
7073 // Conditional-store of the updated heap-top.
7074 // Used during allocation of the shared heap.
7075 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7076 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7077 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7078 // EAX is killed if there is contention, but then it's also unused.
7079 // In the common case of no contention, EAX holds the new oop address.
7080 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7081 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7082 ins_pipe( pipe_cmpxchg );
7083 %}
7084
7085 // Conditional-store of an int value.
7086 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7087 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7088 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7089 effect(KILL oldval);
7090 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7091 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7092 ins_pipe( pipe_cmpxchg );
7093 %}
7094
7095 // Conditional-store of a long value.
7096 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7097 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7098 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7099 effect(KILL oldval);
7100 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7101 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7102 "XCHG EBX,ECX"
7103 %}
7104 ins_encode %{
7105 // Note: we need to swap rbx, and rcx before and after the
7106 // cmpxchg8 instruction because the instruction uses
7107 // rcx as the high order word of the new value to store but
7108 // our register encoding uses rbx.
7109 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7110 if( os::is_MP() )
7111 __ lock();
7112 __ cmpxchg8($mem$$Address);
7113 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7114 %}
7115 ins_pipe( pipe_cmpxchg );
7116 %}
7117
7118 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7119
7120 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7121 predicate(VM_Version::supports_cx8());
7122 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7123 effect(KILL cr, KILL oldval);
7124 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7125 "MOV $res,0\n\t"
7126 "JNE,s fail\n\t"
7127 "MOV $res,1\n"
7128 "fail:" %}
7129 ins_encode( enc_cmpxchg8(mem_ptr),
7130 enc_flags_ne_to_boolean(res) );
7131 ins_pipe( pipe_cmpxchg );
7132 %}
7133
7134 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7135 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7136 effect(KILL cr, KILL oldval);
7137 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7138 "MOV $res,0\n\t"
7139 "JNE,s fail\n\t"
7140 "MOV $res,1\n"
7141 "fail:" %}
7142 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7143 ins_pipe( pipe_cmpxchg );
7144 %}
7145
7146 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7147 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7148 effect(KILL cr, KILL oldval);
7149 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7150 "MOV $res,0\n\t"
7151 "JNE,s fail\n\t"
7152 "MOV $res,1\n"
7153 "fail:" %}
7154 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7155 ins_pipe( pipe_cmpxchg );
7156 %}
7157
7158 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7159 predicate(n->as_LoadStore()->result_not_used());
7160 match(Set dummy (GetAndAddI mem add));
7161 effect(KILL cr);
7162 format %{ "ADDL [$mem],$add" %}
7163 ins_encode %{
7164 if (os::is_MP()) { __ lock(); }
7165 __ addl($mem$$Address, $add$$constant);
7166 %}
7167 ins_pipe( pipe_cmpxchg );
7168 %}
7169
7170 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7171 match(Set newval (GetAndAddI mem newval));
7172 effect(KILL cr);
7173 format %{ "XADDL [$mem],$newval" %}
7174 ins_encode %{
7175 if (os::is_MP()) { __ lock(); }
7176 __ xaddl($mem$$Address, $newval$$Register);
7177 %}
7178 ins_pipe( pipe_cmpxchg );
7179 %}
7180
7181 instruct xchgI( memory mem, rRegI newval) %{
7182 match(Set newval (GetAndSetI mem newval));
7183 format %{ "XCHGL $newval,[$mem]" %}
7184 ins_encode %{
7185 __ xchgl($newval$$Register, $mem$$Address);
7186 %}
7187 ins_pipe( pipe_cmpxchg );
7188 %}
7189
7190 instruct xchgP( memory mem, pRegP newval) %{
7191 match(Set newval (GetAndSetP mem newval));
7192 format %{ "XCHGL $newval,[$mem]" %}
7193 ins_encode %{
7194 __ xchgl($newval$$Register, $mem$$Address);
7195 %}
7196 ins_pipe( pipe_cmpxchg );
7197 %}
7198
7199 //----------Subtraction Instructions-------------------------------------------
7200
7201 // Integer Subtraction Instructions
7202 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7203 match(Set dst (SubI dst src));
7204 effect(KILL cr);
7205
7206 size(2);
7207 format %{ "SUB $dst,$src" %}
7208 opcode(0x2B);
7209 ins_encode( OpcP, RegReg( dst, src) );
7210 ins_pipe( ialu_reg_reg );
7211 %}
7212
7213 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7214 match(Set dst (SubI dst src));
7215 effect(KILL cr);
7216
7217 format %{ "SUB $dst,$src" %}
7218 opcode(0x81,0x05); /* Opcode 81 /5 */
7219 // ins_encode( RegImm( dst, src) );
7220 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7221 ins_pipe( ialu_reg );
7222 %}
7223
7224 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7225 match(Set dst (SubI dst (LoadI src)));
7226 effect(KILL cr);
7227
7228 ins_cost(125);
7229 format %{ "SUB $dst,$src" %}
7230 opcode(0x2B);
7231 ins_encode( OpcP, RegMem( dst, src) );
7232 ins_pipe( ialu_reg_mem );
7233 %}
7234
7235 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7236 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7237 effect(KILL cr);
7238
7239 ins_cost(150);
7240 format %{ "SUB $dst,$src" %}
7241 opcode(0x29); /* Opcode 29 /r */
7242 ins_encode( OpcP, RegMem( src, dst ) );
7243 ins_pipe( ialu_mem_reg );
7244 %}
7245
7246 // Subtract from a pointer
7247 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7248 match(Set dst (AddP dst (SubI zero src)));
7249 effect(KILL cr);
7250
7251 size(2);
7252 format %{ "SUB $dst,$src" %}
7253 opcode(0x2B);
7254 ins_encode( OpcP, RegReg( dst, src) );
7255 ins_pipe( ialu_reg_reg );
7256 %}
7257
7258 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7259 match(Set dst (SubI zero dst));
7260 effect(KILL cr);
7261
7262 size(2);
7263 format %{ "NEG $dst" %}
7264 opcode(0xF7,0x03); // Opcode F7 /3
7265 ins_encode( OpcP, RegOpc( dst ) );
7266 ins_pipe( ialu_reg );
7267 %}
7268
7269 //----------Multiplication/Division Instructions-------------------------------
7270 // Integer Multiplication Instructions
7271 // Multiply Register
7272 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7273 match(Set dst (MulI dst src));
7274 effect(KILL cr);
7275
7276 size(3);
7277 ins_cost(300);
7278 format %{ "IMUL $dst,$src" %}
7279 opcode(0xAF, 0x0F);
7280 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7281 ins_pipe( ialu_reg_reg_alu0 );
7282 %}
7283
7284 // Multiply 32-bit Immediate
7285 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7286 match(Set dst (MulI src imm));
7287 effect(KILL cr);
7288
7289 ins_cost(300);
7290 format %{ "IMUL $dst,$src,$imm" %}
7291 opcode(0x69); /* 69 /r id */
7292 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7293 ins_pipe( ialu_reg_reg_alu0 );
7294 %}
7295
7296 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7297 match(Set dst src);
7298 effect(KILL cr);
7299
7300 // Note that this is artificially increased to make it more expensive than loadConL
7301 ins_cost(250);
7302 format %{ "MOV EAX,$src\t// low word only" %}
7303 opcode(0xB8);
7304 ins_encode( LdImmL_Lo(dst, src) );
7305 ins_pipe( ialu_reg_fat );
7306 %}
7307
7308 // Multiply by 32-bit Immediate, taking the shifted high order results
7309 // (special case for shift by 32)
7310 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7311 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7312 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7313 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7314 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7315 effect(USE src1, KILL cr);
7316
7317 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7318 ins_cost(0*100 + 1*400 - 150);
7319 format %{ "IMUL EDX:EAX,$src1" %}
7320 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7321 ins_pipe( pipe_slow );
7322 %}
7323
7324 // Multiply by 32-bit Immediate, taking the shifted high order results
7325 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7326 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7327 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7328 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7329 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7330 effect(USE src1, KILL cr);
7331
7332 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7333 ins_cost(1*100 + 1*400 - 150);
7334 format %{ "IMUL EDX:EAX,$src1\n\t"
7335 "SAR EDX,$cnt-32" %}
7336 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7337 ins_pipe( pipe_slow );
7338 %}
7339
7340 // Multiply Memory 32-bit Immediate
7341 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7342 match(Set dst (MulI (LoadI src) imm));
7343 effect(KILL cr);
7344
7345 ins_cost(300);
7346 format %{ "IMUL $dst,$src,$imm" %}
7347 opcode(0x69); /* 69 /r id */
7348 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7349 ins_pipe( ialu_reg_mem_alu0 );
7350 %}
7351
7352 // Multiply Memory
7353 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7354 match(Set dst (MulI dst (LoadI src)));
7355 effect(KILL cr);
7356
7357 ins_cost(350);
7358 format %{ "IMUL $dst,$src" %}
7359 opcode(0xAF, 0x0F);
7360 ins_encode( OpcS, OpcP, RegMem( dst, src) );
7361 ins_pipe( ialu_reg_mem_alu0 );
7362 %}
7363
7364 // Multiply Register Int to Long
7365 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7366 // Basic Idea: long = (long)int * (long)int
7367 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7368 effect(DEF dst, USE src, USE src1, KILL flags);
7369
7370 ins_cost(300);
7371 format %{ "IMUL $dst,$src1" %}
7372
7373 ins_encode( long_int_multiply( dst, src1 ) );
7374 ins_pipe( ialu_reg_reg_alu0 );
7375 %}
7376
7377 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
7378 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
7379 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
7380 effect(KILL flags);
7381
7382 ins_cost(300);
7383 format %{ "MUL $dst,$src1" %}
7384
7385 ins_encode( long_uint_multiply(dst, src1) );
7386 ins_pipe( ialu_reg_reg_alu0 );
7387 %}
7388
7389 // Multiply Register Long
7390 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7391 match(Set dst (MulL dst src));
7392 effect(KILL cr, TEMP tmp);
7393 ins_cost(4*100+3*400);
7394 // Basic idea: lo(result) = lo(x_lo * y_lo)
7395 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
7396 format %{ "MOV $tmp,$src.lo\n\t"
7397 "IMUL $tmp,EDX\n\t"
7398 "MOV EDX,$src.hi\n\t"
7399 "IMUL EDX,EAX\n\t"
7400 "ADD $tmp,EDX\n\t"
7401 "MUL EDX:EAX,$src.lo\n\t"
7402 "ADD EDX,$tmp" %}
7403 ins_encode( long_multiply( dst, src, tmp ) );
7404 ins_pipe( pipe_slow );
7405 %}
7406
7407 // Multiply Register Long where the left operand's high 32 bits are zero
7408 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7409 predicate(is_operand_hi32_zero(n->in(1)));
7410 match(Set dst (MulL dst src));
7411 effect(KILL cr, TEMP tmp);
7412 ins_cost(2*100+2*400);
7413 // Basic idea: lo(result) = lo(x_lo * y_lo)
7414 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
7415 format %{ "MOV $tmp,$src.hi\n\t"
7416 "IMUL $tmp,EAX\n\t"
7417 "MUL EDX:EAX,$src.lo\n\t"
7418 "ADD EDX,$tmp" %}
7419 ins_encode %{
7420 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
7421 __ imull($tmp$$Register, rax);
7422 __ mull($src$$Register);
7423 __ addl(rdx, $tmp$$Register);
7424 %}
7425 ins_pipe( pipe_slow );
7426 %}
7427
7428 // Multiply Register Long where the right operand's high 32 bits are zero
7429 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7430 predicate(is_operand_hi32_zero(n->in(2)));
7431 match(Set dst (MulL dst src));
7432 effect(KILL cr, TEMP tmp);
7433 ins_cost(2*100+2*400);
7434 // Basic idea: lo(result) = lo(x_lo * y_lo)
7435 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
7436 format %{ "MOV $tmp,$src.lo\n\t"
7437 "IMUL $tmp,EDX\n\t"
7438 "MUL EDX:EAX,$src.lo\n\t"
7439 "ADD EDX,$tmp" %}
7440 ins_encode %{
7441 __ movl($tmp$$Register, $src$$Register);
7442 __ imull($tmp$$Register, rdx);
7443 __ mull($src$$Register);
7444 __ addl(rdx, $tmp$$Register);
7445 %}
7446 ins_pipe( pipe_slow );
7447 %}
7448
7449 // Multiply Register Long where the left and the right operands' high 32 bits are zero
7450 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
7451 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
7452 match(Set dst (MulL dst src));
7453 effect(KILL cr);
7454 ins_cost(1*400);
7455 // Basic idea: lo(result) = lo(x_lo * y_lo)
7456 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
7457 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
7458 ins_encode %{
7459 __ mull($src$$Register);
7460 %}
7461 ins_pipe( pipe_slow );
7462 %}
7463
7464 // Multiply Register Long by small constant
7465 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
7466 match(Set dst (MulL dst src));
7467 effect(KILL cr, TEMP tmp);
7468 ins_cost(2*100+2*400);
7469 size(12);
7470 // Basic idea: lo(result) = lo(src * EAX)
7471 // hi(result) = hi(src * EAX) + lo(src * EDX)
7472 format %{ "IMUL $tmp,EDX,$src\n\t"
7473 "MOV EDX,$src\n\t"
7474 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
7475 "ADD EDX,$tmp" %}
7476 ins_encode( long_multiply_con( dst, src, tmp ) );
7477 ins_pipe( pipe_slow );
7478 %}
7479
7480 // Integer DIV with Register
7481 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7482 match(Set rax (DivI rax div));
7483 effect(KILL rdx, KILL cr);
7484 size(26);
7485 ins_cost(30*100+10*100);
7486 format %{ "CMP EAX,0x80000000\n\t"
7487 "JNE,s normal\n\t"
7488 "XOR EDX,EDX\n\t"
7489 "CMP ECX,-1\n\t"
7490 "JE,s done\n"
7491 "normal: CDQ\n\t"
7492 "IDIV $div\n\t"
7493 "done:" %}
7494 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7495 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7496 ins_pipe( ialu_reg_reg_alu0 );
7497 %}
7498
7499 // Divide Register Long
7500 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7501 match(Set dst (DivL src1 src2));
7502 effect( KILL cr, KILL cx, KILL bx );
7503 ins_cost(10000);
7504 format %{ "PUSH $src1.hi\n\t"
7505 "PUSH $src1.lo\n\t"
7506 "PUSH $src2.hi\n\t"
7507 "PUSH $src2.lo\n\t"
7508 "CALL SharedRuntime::ldiv\n\t"
7509 "ADD ESP,16" %}
7510 ins_encode( long_div(src1,src2) );
7511 ins_pipe( pipe_slow );
7512 %}
7513
7514 // Integer DIVMOD with Register, both quotient and mod results
7515 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7516 match(DivModI rax div);
7517 effect(KILL cr);
7518 size(26);
7519 ins_cost(30*100+10*100);
7520 format %{ "CMP EAX,0x80000000\n\t"
7521 "JNE,s normal\n\t"
7522 "XOR EDX,EDX\n\t"
7523 "CMP ECX,-1\n\t"
7524 "JE,s done\n"
7525 "normal: CDQ\n\t"
7526 "IDIV $div\n\t"
7527 "done:" %}
7528 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7529 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7530 ins_pipe( pipe_slow );
7531 %}
7532
7533 // Integer MOD with Register
7534 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
7535 match(Set rdx (ModI rax div));
7536 effect(KILL rax, KILL cr);
7537
7538 size(26);
7539 ins_cost(300);
7540 format %{ "CDQ\n\t"
7541 "IDIV $div" %}
7542 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7543 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7544 ins_pipe( ialu_reg_reg_alu0 );
7545 %}
7546
7547 // Remainder Register Long
7548 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7549 match(Set dst (ModL src1 src2));
7550 effect( KILL cr, KILL cx, KILL bx );
7551 ins_cost(10000);
7552 format %{ "PUSH $src1.hi\n\t"
7553 "PUSH $src1.lo\n\t"
7554 "PUSH $src2.hi\n\t"
7555 "PUSH $src2.lo\n\t"
7556 "CALL SharedRuntime::lrem\n\t"
7557 "ADD ESP,16" %}
7558 ins_encode( long_mod(src1,src2) );
7559 ins_pipe( pipe_slow );
7560 %}
7561
7562 // Divide Register Long (no special case since divisor != -1)
7563 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7564 match(Set dst (DivL dst imm));
7565 effect( TEMP tmp, TEMP tmp2, KILL cr );
7566 ins_cost(1000);
7567 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
7568 "XOR $tmp2,$tmp2\n\t"
7569 "CMP $tmp,EDX\n\t"
7570 "JA,s fast\n\t"
7571 "MOV $tmp2,EAX\n\t"
7572 "MOV EAX,EDX\n\t"
7573 "MOV EDX,0\n\t"
7574 "JLE,s pos\n\t"
7575 "LNEG EAX : $tmp2\n\t"
7576 "DIV $tmp # unsigned division\n\t"
7577 "XCHG EAX,$tmp2\n\t"
7578 "DIV $tmp\n\t"
7579 "LNEG $tmp2 : EAX\n\t"
7580 "JMP,s done\n"
7581 "pos:\n\t"
7582 "DIV $tmp\n\t"
7583 "XCHG EAX,$tmp2\n"
7584 "fast:\n\t"
7585 "DIV $tmp\n"
7586 "done:\n\t"
7587 "MOV EDX,$tmp2\n\t"
7588 "NEG EDX:EAX # if $imm < 0" %}
7589 ins_encode %{
7590 int con = (int)$imm$$constant;
7591 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7592 int pcon = (con > 0) ? con : -con;
7593 Label Lfast, Lpos, Ldone;
7594
7595 __ movl($tmp$$Register, pcon);
7596 __ xorl($tmp2$$Register,$tmp2$$Register);
7597 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7598 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
7599
7600 __ movl($tmp2$$Register, $dst$$Register); // save
7601 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7602 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7603 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7604
7605 // Negative dividend.
7606 // convert value to positive to use unsigned division
7607 __ lneg($dst$$Register, $tmp2$$Register);
7608 __ divl($tmp$$Register);
7609 __ xchgl($dst$$Register, $tmp2$$Register);
7610 __ divl($tmp$$Register);
7611 // revert result back to negative
7612 __ lneg($tmp2$$Register, $dst$$Register);
7613 __ jmpb(Ldone);
7614
7615 __ bind(Lpos);
7616 __ divl($tmp$$Register); // Use unsigned division
7617 __ xchgl($dst$$Register, $tmp2$$Register);
7618 // Fallthrow for final divide, tmp2 has 32 bit hi result
7619
7620 __ bind(Lfast);
7621 // fast path: src is positive
7622 __ divl($tmp$$Register); // Use unsigned division
7623
7624 __ bind(Ldone);
7625 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
7626 if (con < 0) {
7627 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
7628 }
7629 %}
7630 ins_pipe( pipe_slow );
7631 %}
7632
7633 // Remainder Register Long (remainder fit into 32 bits)
7634 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7635 match(Set dst (ModL dst imm));
7636 effect( TEMP tmp, TEMP tmp2, KILL cr );
7637 ins_cost(1000);
7638 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
7639 "CMP $tmp,EDX\n\t"
7640 "JA,s fast\n\t"
7641 "MOV $tmp2,EAX\n\t"
7642 "MOV EAX,EDX\n\t"
7643 "MOV EDX,0\n\t"
7644 "JLE,s pos\n\t"
7645 "LNEG EAX : $tmp2\n\t"
7646 "DIV $tmp # unsigned division\n\t"
7647 "MOV EAX,$tmp2\n\t"
7648 "DIV $tmp\n\t"
7649 "NEG EDX\n\t"
7650 "JMP,s done\n"
7651 "pos:\n\t"
7652 "DIV $tmp\n\t"
7653 "MOV EAX,$tmp2\n"
7654 "fast:\n\t"
7655 "DIV $tmp\n"
7656 "done:\n\t"
7657 "MOV EAX,EDX\n\t"
7658 "SAR EDX,31\n\t" %}
7659 ins_encode %{
7660 int con = (int)$imm$$constant;
7661 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7662 int pcon = (con > 0) ? con : -con;
7663 Label Lfast, Lpos, Ldone;
7664
7665 __ movl($tmp$$Register, pcon);
7666 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7667 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
7668
7669 __ movl($tmp2$$Register, $dst$$Register); // save
7670 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7671 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7672 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7673
7674 // Negative dividend.
7675 // convert value to positive to use unsigned division
7676 __ lneg($dst$$Register, $tmp2$$Register);
7677 __ divl($tmp$$Register);
7678 __ movl($dst$$Register, $tmp2$$Register);
7679 __ divl($tmp$$Register);
7680 // revert remainder back to negative
7681 __ negl(HIGH_FROM_LOW($dst$$Register));
7682 __ jmpb(Ldone);
7683
7684 __ bind(Lpos);
7685 __ divl($tmp$$Register);
7686 __ movl($dst$$Register, $tmp2$$Register);
7687
7688 __ bind(Lfast);
7689 // fast path: src is positive
7690 __ divl($tmp$$Register);
7691
7692 __ bind(Ldone);
7693 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7694 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
7695
7696 %}
7697 ins_pipe( pipe_slow );
7698 %}
7699
7700 // Integer Shift Instructions
7701 // Shift Left by one
7702 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7703 match(Set dst (LShiftI dst shift));
7704 effect(KILL cr);
7705
7706 size(2);
7707 format %{ "SHL $dst,$shift" %}
7708 opcode(0xD1, 0x4); /* D1 /4 */
7709 ins_encode( OpcP, RegOpc( dst ) );
7710 ins_pipe( ialu_reg );
7711 %}
7712
7713 // Shift Left by 8-bit immediate
7714 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7715 match(Set dst (LShiftI dst shift));
7716 effect(KILL cr);
7717
7718 size(3);
7719 format %{ "SHL $dst,$shift" %}
7720 opcode(0xC1, 0x4); /* C1 /4 ib */
7721 ins_encode( RegOpcImm( dst, shift) );
7722 ins_pipe( ialu_reg );
7723 %}
7724
7725 // Shift Left by variable
7726 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7727 match(Set dst (LShiftI dst shift));
7728 effect(KILL cr);
7729
7730 size(2);
7731 format %{ "SHL $dst,$shift" %}
7732 opcode(0xD3, 0x4); /* D3 /4 */
7733 ins_encode( OpcP, RegOpc( dst ) );
7734 ins_pipe( ialu_reg_reg );
7735 %}
7736
7737 // Arithmetic shift right by one
7738 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7739 match(Set dst (RShiftI dst shift));
7740 effect(KILL cr);
7741
7742 size(2);
7743 format %{ "SAR $dst,$shift" %}
7744 opcode(0xD1, 0x7); /* D1 /7 */
7745 ins_encode( OpcP, RegOpc( dst ) );
7746 ins_pipe( ialu_reg );
7747 %}
7748
7749 // Arithmetic shift right by one
7750 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
7751 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7752 effect(KILL cr);
7753 format %{ "SAR $dst,$shift" %}
7754 opcode(0xD1, 0x7); /* D1 /7 */
7755 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
7756 ins_pipe( ialu_mem_imm );
7757 %}
7758
7759 // Arithmetic Shift Right by 8-bit immediate
7760 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7761 match(Set dst (RShiftI dst shift));
7762 effect(KILL cr);
7763
7764 size(3);
7765 format %{ "SAR $dst,$shift" %}
7766 opcode(0xC1, 0x7); /* C1 /7 ib */
7767 ins_encode( RegOpcImm( dst, shift ) );
7768 ins_pipe( ialu_mem_imm );
7769 %}
7770
7771 // Arithmetic Shift Right by 8-bit immediate
7772 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
7773 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7774 effect(KILL cr);
7775
7776 format %{ "SAR $dst,$shift" %}
7777 opcode(0xC1, 0x7); /* C1 /7 ib */
7778 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
7779 ins_pipe( ialu_mem_imm );
7780 %}
7781
7782 // Arithmetic Shift Right by variable
7783 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7784 match(Set dst (RShiftI dst shift));
7785 effect(KILL cr);
7786
7787 size(2);
7788 format %{ "SAR $dst,$shift" %}
7789 opcode(0xD3, 0x7); /* D3 /7 */
7790 ins_encode( OpcP, RegOpc( dst ) );
7791 ins_pipe( ialu_reg_reg );
7792 %}
7793
7794 // Logical shift right by one
7795 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7796 match(Set dst (URShiftI dst shift));
7797 effect(KILL cr);
7798
7799 size(2);
7800 format %{ "SHR $dst,$shift" %}
7801 opcode(0xD1, 0x5); /* D1 /5 */
7802 ins_encode( OpcP, RegOpc( dst ) );
7803 ins_pipe( ialu_reg );
7804 %}
7805
7806 // Logical Shift Right by 8-bit immediate
7807 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7808 match(Set dst (URShiftI dst shift));
7809 effect(KILL cr);
7810
7811 size(3);
7812 format %{ "SHR $dst,$shift" %}
7813 opcode(0xC1, 0x5); /* C1 /5 ib */
7814 ins_encode( RegOpcImm( dst, shift) );
7815 ins_pipe( ialu_reg );
7816 %}
7817
7818
7819 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
7820 // This idiom is used by the compiler for the i2b bytecode.
7821 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
7822 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
7823
7824 size(3);
7825 format %{ "MOVSX $dst,$src :8" %}
7826 ins_encode %{
7827 __ movsbl($dst$$Register, $src$$Register);
7828 %}
7829 ins_pipe(ialu_reg_reg);
7830 %}
7831
7832 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
7833 // This idiom is used by the compiler the i2s bytecode.
7834 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
7835 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
7836
7837 size(3);
7838 format %{ "MOVSX $dst,$src :16" %}
7839 ins_encode %{
7840 __ movswl($dst$$Register, $src$$Register);
7841 %}
7842 ins_pipe(ialu_reg_reg);
7843 %}
7844
7845
7846 // Logical Shift Right by variable
7847 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7848 match(Set dst (URShiftI dst shift));
7849 effect(KILL cr);
7850
7851 size(2);
7852 format %{ "SHR $dst,$shift" %}
7853 opcode(0xD3, 0x5); /* D3 /5 */
7854 ins_encode( OpcP, RegOpc( dst ) );
7855 ins_pipe( ialu_reg_reg );
7856 %}
7857
7858
7859 //----------Logical Instructions-----------------------------------------------
7860 //----------Integer Logical Instructions---------------------------------------
7861 // And Instructions
7862 // And Register with Register
7863 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7864 match(Set dst (AndI dst src));
7865 effect(KILL cr);
7866
7867 size(2);
7868 format %{ "AND $dst,$src" %}
7869 opcode(0x23);
7870 ins_encode( OpcP, RegReg( dst, src) );
7871 ins_pipe( ialu_reg_reg );
7872 %}
7873
7874 // And Register with Immediate
7875 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7876 match(Set dst (AndI dst src));
7877 effect(KILL cr);
7878
7879 format %{ "AND $dst,$src" %}
7880 opcode(0x81,0x04); /* Opcode 81 /4 */
7881 // ins_encode( RegImm( dst, src) );
7882 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7883 ins_pipe( ialu_reg );
7884 %}
7885
7886 // And Register with Memory
7887 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7888 match(Set dst (AndI dst (LoadI src)));
7889 effect(KILL cr);
7890
7891 ins_cost(125);
7892 format %{ "AND $dst,$src" %}
7893 opcode(0x23);
7894 ins_encode( OpcP, RegMem( dst, src) );
7895 ins_pipe( ialu_reg_mem );
7896 %}
7897
7898 // And Memory with Register
7899 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7900 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
7901 effect(KILL cr);
7902
7903 ins_cost(150);
7904 format %{ "AND $dst,$src" %}
7905 opcode(0x21); /* Opcode 21 /r */
7906 ins_encode( OpcP, RegMem( src, dst ) );
7907 ins_pipe( ialu_mem_reg );
7908 %}
7909
7910 // And Memory with Immediate
7911 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7912 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
7913 effect(KILL cr);
7914
7915 ins_cost(125);
7916 format %{ "AND $dst,$src" %}
7917 opcode(0x81, 0x4); /* Opcode 81 /4 id */
7918 // ins_encode( MemImm( dst, src) );
7919 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
7920 ins_pipe( ialu_mem_imm );
7921 %}
7922
7923 // BMI1 instructions
7924 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{
7925 match(Set dst (AndI (XorI src1 minus_1) src2));
7926 predicate(UseBMI1Instructions);
7927 effect(KILL cr);
7928
7929 format %{ "ANDNL $dst, $src1, $src2" %}
7930
7931 ins_encode %{
7932 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
7933 %}
7934 ins_pipe(ialu_reg);
7935 %}
7936
7937 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{
7938 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));
7939 predicate(UseBMI1Instructions);
7940 effect(KILL cr);
7941
7942 ins_cost(125);
7943 format %{ "ANDNL $dst, $src1, $src2" %}
7944
7945 ins_encode %{
7946 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
7947 %}
7948 ins_pipe(ialu_reg_mem);
7949 %}
7950
7951 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{
7952 match(Set dst (AndI (SubI imm_zero src) src));
7953 predicate(UseBMI1Instructions);
7954 effect(KILL cr);
7955
7956 format %{ "BLSIL $dst, $src" %}
7957
7958 ins_encode %{
7959 __ blsil($dst$$Register, $src$$Register);
7960 %}
7961 ins_pipe(ialu_reg);
7962 %}
7963
7964 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{
7965 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
7966 predicate(UseBMI1Instructions);
7967 effect(KILL cr);
7968
7969 ins_cost(125);
7970 format %{ "BLSIL $dst, $src" %}
7971
7972 ins_encode %{
7973 __ blsil($dst$$Register, $src$$Address);
7974 %}
7975 ins_pipe(ialu_reg_mem);
7976 %}
7977
7978 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
7979 %{
7980 match(Set dst (XorI (AddI src minus_1) src));
7981 predicate(UseBMI1Instructions);
7982 effect(KILL cr);
7983
7984 format %{ "BLSMSKL $dst, $src" %}
7985
7986 ins_encode %{
7987 __ blsmskl($dst$$Register, $src$$Register);
7988 %}
7989
7990 ins_pipe(ialu_reg);
7991 %}
7992
7993 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
7994 %{
7995 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ));
7996 predicate(UseBMI1Instructions);
7997 effect(KILL cr);
7998
7999 ins_cost(125);
8000 format %{ "BLSMSKL $dst, $src" %}
8001
8002 ins_encode %{
8003 __ blsmskl($dst$$Register, $src$$Address);
8004 %}
8005
8006 ins_pipe(ialu_reg_mem);
8007 %}
8008
8009 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8010 %{
8011 match(Set dst (AndI (AddI src minus_1) src) );
8012 predicate(UseBMI1Instructions);
8013 effect(KILL cr);
8014
8015 format %{ "BLSRL $dst, $src" %}
8016
8017 ins_encode %{
8018 __ blsrl($dst$$Register, $src$$Register);
8019 %}
8020
8021 ins_pipe(ialu_reg);
8022 %}
8023
8024 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8025 %{
8026 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ));
8027 predicate(UseBMI1Instructions);
8028 effect(KILL cr);
8029
8030 ins_cost(125);
8031 format %{ "BLSRL $dst, $src" %}
8032
8033 ins_encode %{
8034 __ blsrl($dst$$Register, $src$$Address);
8035 %}
8036
8037 ins_pipe(ialu_reg_mem);
8038 %}
8039
8040 // Or Instructions
8041 // Or Register with Register
8042 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8043 match(Set dst (OrI dst src));
8044 effect(KILL cr);
8045
8046 size(2);
8047 format %{ "OR $dst,$src" %}
8048 opcode(0x0B);
8049 ins_encode( OpcP, RegReg( dst, src) );
8050 ins_pipe( ialu_reg_reg );
8051 %}
8052
8053 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8054 match(Set dst (OrI dst (CastP2X src)));
8055 effect(KILL cr);
8056
8057 size(2);
8058 format %{ "OR $dst,$src" %}
8059 opcode(0x0B);
8060 ins_encode( OpcP, RegReg( dst, src) );
8061 ins_pipe( ialu_reg_reg );
8062 %}
8063
8064
8065 // Or Register with Immediate
8066 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8067 match(Set dst (OrI dst src));
8068 effect(KILL cr);
8069
8070 format %{ "OR $dst,$src" %}
8071 opcode(0x81,0x01); /* Opcode 81 /1 id */
8072 // ins_encode( RegImm( dst, src) );
8073 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8074 ins_pipe( ialu_reg );
8075 %}
8076
8077 // Or Register with Memory
8078 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8079 match(Set dst (OrI dst (LoadI src)));
8080 effect(KILL cr);
8081
8082 ins_cost(125);
8083 format %{ "OR $dst,$src" %}
8084 opcode(0x0B);
8085 ins_encode( OpcP, RegMem( dst, src) );
8086 ins_pipe( ialu_reg_mem );
8087 %}
8088
8089 // Or Memory with Register
8090 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8091 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8092 effect(KILL cr);
8093
8094 ins_cost(150);
8095 format %{ "OR $dst,$src" %}
8096 opcode(0x09); /* Opcode 09 /r */
8097 ins_encode( OpcP, RegMem( src, dst ) );
8098 ins_pipe( ialu_mem_reg );
8099 %}
8100
8101 // Or Memory with Immediate
8102 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8103 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8104 effect(KILL cr);
8105
8106 ins_cost(125);
8107 format %{ "OR $dst,$src" %}
8108 opcode(0x81,0x1); /* Opcode 81 /1 id */
8109 // ins_encode( MemImm( dst, src) );
8110 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8111 ins_pipe( ialu_mem_imm );
8112 %}
8113
8114 // ROL/ROR
8115 // ROL expand
8116 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8117 effect(USE_DEF dst, USE shift, KILL cr);
8118
8119 format %{ "ROL $dst, $shift" %}
8120 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8121 ins_encode( OpcP, RegOpc( dst ));
8122 ins_pipe( ialu_reg );
8123 %}
8124
8125 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8126 effect(USE_DEF dst, USE shift, KILL cr);
8127
8128 format %{ "ROL $dst, $shift" %}
8129 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8130 ins_encode( RegOpcImm(dst, shift) );
8131 ins_pipe(ialu_reg);
8132 %}
8133
8134 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8135 effect(USE_DEF dst, USE shift, KILL cr);
8136
8137 format %{ "ROL $dst, $shift" %}
8138 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8139 ins_encode(OpcP, RegOpc(dst));
8140 ins_pipe( ialu_reg_reg );
8141 %}
8142 // end of ROL expand
8143
8144 // ROL 32bit by one once
8145 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8146 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8147
8148 expand %{
8149 rolI_eReg_imm1(dst, lshift, cr);
8150 %}
8151 %}
8152
8153 // ROL 32bit var by imm8 once
8154 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8155 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8156 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8157
8158 expand %{
8159 rolI_eReg_imm8(dst, lshift, cr);
8160 %}
8161 %}
8162
8163 // ROL 32bit var by var once
8164 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8165 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8166
8167 expand %{
8168 rolI_eReg_CL(dst, shift, cr);
8169 %}
8170 %}
8171
8172 // ROL 32bit var by var once
8173 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8174 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8175
8176 expand %{
8177 rolI_eReg_CL(dst, shift, cr);
8178 %}
8179 %}
8180
8181 // ROR expand
8182 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8183 effect(USE_DEF dst, USE shift, KILL cr);
8184
8185 format %{ "ROR $dst, $shift" %}
8186 opcode(0xD1,0x1); /* Opcode D1 /1 */
8187 ins_encode( OpcP, RegOpc( dst ) );
8188 ins_pipe( ialu_reg );
8189 %}
8190
8191 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8192 effect (USE_DEF dst, USE shift, KILL cr);
8193
8194 format %{ "ROR $dst, $shift" %}
8195 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8196 ins_encode( RegOpcImm(dst, shift) );
8197 ins_pipe( ialu_reg );
8198 %}
8199
8200 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8201 effect(USE_DEF dst, USE shift, KILL cr);
8202
8203 format %{ "ROR $dst, $shift" %}
8204 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8205 ins_encode(OpcP, RegOpc(dst));
8206 ins_pipe( ialu_reg_reg );
8207 %}
8208 // end of ROR expand
8209
8210 // ROR right once
8211 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8212 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8213
8214 expand %{
8215 rorI_eReg_imm1(dst, rshift, cr);
8216 %}
8217 %}
8218
8219 // ROR 32bit by immI8 once
8220 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8221 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8222 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8223
8224 expand %{
8225 rorI_eReg_imm8(dst, rshift, cr);
8226 %}
8227 %}
8228
8229 // ROR 32bit var by var once
8230 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8231 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8232
8233 expand %{
8234 rorI_eReg_CL(dst, shift, cr);
8235 %}
8236 %}
8237
8238 // ROR 32bit var by var once
8239 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8240 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8241
8242 expand %{
8243 rorI_eReg_CL(dst, shift, cr);
8244 %}
8245 %}
8246
8247 // Xor Instructions
8248 // Xor Register with Register
8249 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8250 match(Set dst (XorI dst src));
8251 effect(KILL cr);
8252
8253 size(2);
8254 format %{ "XOR $dst,$src" %}
8255 opcode(0x33);
8256 ins_encode( OpcP, RegReg( dst, src) );
8257 ins_pipe( ialu_reg_reg );
8258 %}
8259
8260 // Xor Register with Immediate -1
8261 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8262 match(Set dst (XorI dst imm));
8263
8264 size(2);
8265 format %{ "NOT $dst" %}
8266 ins_encode %{
8267 __ notl($dst$$Register);
8268 %}
8269 ins_pipe( ialu_reg );
8270 %}
8271
8272 // Xor Register with Immediate
8273 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8274 match(Set dst (XorI dst src));
8275 effect(KILL cr);
8276
8277 format %{ "XOR $dst,$src" %}
8278 opcode(0x81,0x06); /* Opcode 81 /6 id */
8279 // ins_encode( RegImm( dst, src) );
8280 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8281 ins_pipe( ialu_reg );
8282 %}
8283
8284 // Xor Register with Memory
8285 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8286 match(Set dst (XorI dst (LoadI src)));
8287 effect(KILL cr);
8288
8289 ins_cost(125);
8290 format %{ "XOR $dst,$src" %}
8291 opcode(0x33);
8292 ins_encode( OpcP, RegMem(dst, src) );
8293 ins_pipe( ialu_reg_mem );
8294 %}
8295
8296 // Xor Memory with Register
8297 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8298 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8299 effect(KILL cr);
8300
8301 ins_cost(150);
8302 format %{ "XOR $dst,$src" %}
8303 opcode(0x31); /* Opcode 31 /r */
8304 ins_encode( OpcP, RegMem( src, dst ) );
8305 ins_pipe( ialu_mem_reg );
8306 %}
8307
8308 // Xor Memory with Immediate
8309 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8310 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8311 effect(KILL cr);
8312
8313 ins_cost(125);
8314 format %{ "XOR $dst,$src" %}
8315 opcode(0x81,0x6); /* Opcode 81 /6 id */
8316 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8317 ins_pipe( ialu_mem_imm );
8318 %}
8319
8320 //----------Convert Int to Boolean---------------------------------------------
8321
8322 instruct movI_nocopy(rRegI dst, rRegI src) %{
8323 effect( DEF dst, USE src );
8324 format %{ "MOV $dst,$src" %}
8325 ins_encode( enc_Copy( dst, src) );
8326 ins_pipe( ialu_reg_reg );
8327 %}
8328
8329 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8330 effect( USE_DEF dst, USE src, KILL cr );
8331
8332 size(4);
8333 format %{ "NEG $dst\n\t"
8334 "ADC $dst,$src" %}
8335 ins_encode( neg_reg(dst),
8336 OpcRegReg(0x13,dst,src) );
8337 ins_pipe( ialu_reg_reg_long );
8338 %}
8339
8340 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8341 match(Set dst (Conv2B src));
8342
8343 expand %{
8344 movI_nocopy(dst,src);
8345 ci2b(dst,src,cr);
8346 %}
8347 %}
8348
8349 instruct movP_nocopy(rRegI dst, eRegP src) %{
8350 effect( DEF dst, USE src );
8351 format %{ "MOV $dst,$src" %}
8352 ins_encode( enc_Copy( dst, src) );
8353 ins_pipe( ialu_reg_reg );
8354 %}
8355
8356 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8357 effect( USE_DEF dst, USE src, KILL cr );
8358 format %{ "NEG $dst\n\t"
8359 "ADC $dst,$src" %}
8360 ins_encode( neg_reg(dst),
8361 OpcRegReg(0x13,dst,src) );
8362 ins_pipe( ialu_reg_reg_long );
8363 %}
8364
8365 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8366 match(Set dst (Conv2B src));
8367
8368 expand %{
8369 movP_nocopy(dst,src);
8370 cp2b(dst,src,cr);
8371 %}
8372 %}
8373
8374 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8375 match(Set dst (CmpLTMask p q));
8376 effect(KILL cr);
8377 ins_cost(400);
8378
8379 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8380 format %{ "XOR $dst,$dst\n\t"
8381 "CMP $p,$q\n\t"
8382 "SETlt $dst\n\t"
8383 "NEG $dst" %}
8384 ins_encode %{
8385 Register Rp = $p$$Register;
8386 Register Rq = $q$$Register;
8387 Register Rd = $dst$$Register;
8388 Label done;
8389 __ xorl(Rd, Rd);
8390 __ cmpl(Rp, Rq);
8391 __ setb(Assembler::less, Rd);
8392 __ negl(Rd);
8393 %}
8394
8395 ins_pipe(pipe_slow);
8396 %}
8397
8398 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8399 match(Set dst (CmpLTMask dst zero));
8400 effect(DEF dst, KILL cr);
8401 ins_cost(100);
8402
8403 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8404 ins_encode %{
8405 __ sarl($dst$$Register, 31);
8406 %}
8407 ins_pipe(ialu_reg);
8408 %}
8409
8410 /* better to save a register than avoid a branch */
8411 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8412 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8413 effect(KILL cr);
8414 ins_cost(400);
8415 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8416 "JGE done\n\t"
8417 "ADD $p,$y\n"
8418 "done: " %}
8419 ins_encode %{
8420 Register Rp = $p$$Register;
8421 Register Rq = $q$$Register;
8422 Register Ry = $y$$Register;
8423 Label done;
8424 __ subl(Rp, Rq);
8425 __ jccb(Assembler::greaterEqual, done);
8426 __ addl(Rp, Ry);
8427 __ bind(done);
8428 %}
8429
8430 ins_pipe(pipe_cmplt);
8431 %}
8432
8433 /* better to save a register than avoid a branch */
8434 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8435 match(Set y (AndI (CmpLTMask p q) y));
8436 effect(KILL cr);
8437
8438 ins_cost(300);
8439
8440 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
8441 "JLT done\n\t"
8442 "XORL $y, $y\n"
8443 "done: " %}
8444 ins_encode %{
8445 Register Rp = $p$$Register;
8446 Register Rq = $q$$Register;
8447 Register Ry = $y$$Register;
8448 Label done;
8449 __ cmpl(Rp, Rq);
8450 __ jccb(Assembler::less, done);
8451 __ xorl(Ry, Ry);
8452 __ bind(done);
8453 %}
8454
8455 ins_pipe(pipe_cmplt);
8456 %}
8457
8458 /* If I enable this, I encourage spilling in the inner loop of compress.
8459 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8460 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8461 */
8462 //----------Overflow Math Instructions-----------------------------------------
8463
8464 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8465 %{
8466 match(Set cr (OverflowAddI op1 op2));
8467 effect(DEF cr, USE_KILL op1, USE op2);
8468
8469 format %{ "ADD $op1, $op2\t# overflow check int" %}
8470
8471 ins_encode %{
8472 __ addl($op1$$Register, $op2$$Register);
8473 %}
8474 ins_pipe(ialu_reg_reg);
8475 %}
8476
8477 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
8478 %{
8479 match(Set cr (OverflowAddI op1 op2));
8480 effect(DEF cr, USE_KILL op1, USE op2);
8481
8482 format %{ "ADD $op1, $op2\t# overflow check int" %}
8483
8484 ins_encode %{
8485 __ addl($op1$$Register, $op2$$constant);
8486 %}
8487 ins_pipe(ialu_reg_reg);
8488 %}
8489
8490 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2)
8491 %{
8492 match(Set cr (OverflowSubI op1 op2));
8493
8494 format %{ "CMP $op1, $op2\t# overflow check int" %}
8495 ins_encode %{
8496 __ cmpl($op1$$Register, $op2$$Register);
8497 %}
8498 ins_pipe(ialu_reg_reg);
8499 %}
8500
8501 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2)
8502 %{
8503 match(Set cr (OverflowSubI op1 op2));
8504
8505 format %{ "CMP $op1, $op2\t# overflow check int" %}
8506 ins_encode %{
8507 __ cmpl($op1$$Register, $op2$$constant);
8508 %}
8509 ins_pipe(ialu_reg_reg);
8510 %}
8511
8512 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
8513 %{
8514 match(Set cr (OverflowSubI zero op2));
8515 effect(DEF cr, USE_KILL op2);
8516
8517 format %{ "NEG $op2\t# overflow check int" %}
8518 ins_encode %{
8519 __ negl($op2$$Register);
8520 %}
8521 ins_pipe(ialu_reg_reg);
8522 %}
8523
8524 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8525 %{
8526 match(Set cr (OverflowMulI op1 op2));
8527 effect(DEF cr, USE_KILL op1, USE op2);
8528
8529 format %{ "IMUL $op1, $op2\t# overflow check int" %}
8530 ins_encode %{
8531 __ imull($op1$$Register, $op2$$Register);
8532 %}
8533 ins_pipe(ialu_reg_reg_alu0);
8534 %}
8535
8536 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
8537 %{
8538 match(Set cr (OverflowMulI op1 op2));
8539 effect(DEF cr, TEMP tmp, USE op1, USE op2);
8540
8541 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %}
8542 ins_encode %{
8543 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
8544 %}
8545 ins_pipe(ialu_reg_reg_alu0);
8546 %}
8547
8548 //----------Long Instructions------------------------------------------------
8549 // Add Long Register with Register
8550 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8551 match(Set dst (AddL dst src));
8552 effect(KILL cr);
8553 ins_cost(200);
8554 format %{ "ADD $dst.lo,$src.lo\n\t"
8555 "ADC $dst.hi,$src.hi" %}
8556 opcode(0x03, 0x13);
8557 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8558 ins_pipe( ialu_reg_reg_long );
8559 %}
8560
8561 // Add Long Register with Immediate
8562 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8563 match(Set dst (AddL dst src));
8564 effect(KILL cr);
8565 format %{ "ADD $dst.lo,$src.lo\n\t"
8566 "ADC $dst.hi,$src.hi" %}
8567 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8568 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8569 ins_pipe( ialu_reg_long );
8570 %}
8571
8572 // Add Long Register with Memory
8573 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8574 match(Set dst (AddL dst (LoadL mem)));
8575 effect(KILL cr);
8576 ins_cost(125);
8577 format %{ "ADD $dst.lo,$mem\n\t"
8578 "ADC $dst.hi,$mem+4" %}
8579 opcode(0x03, 0x13);
8580 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8581 ins_pipe( ialu_reg_long_mem );
8582 %}
8583
8584 // Subtract Long Register with Register.
8585 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8586 match(Set dst (SubL dst src));
8587 effect(KILL cr);
8588 ins_cost(200);
8589 format %{ "SUB $dst.lo,$src.lo\n\t"
8590 "SBB $dst.hi,$src.hi" %}
8591 opcode(0x2B, 0x1B);
8592 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8593 ins_pipe( ialu_reg_reg_long );
8594 %}
8595
8596 // Subtract Long Register with Immediate
8597 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8598 match(Set dst (SubL dst src));
8599 effect(KILL cr);
8600 format %{ "SUB $dst.lo,$src.lo\n\t"
8601 "SBB $dst.hi,$src.hi" %}
8602 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8603 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8604 ins_pipe( ialu_reg_long );
8605 %}
8606
8607 // Subtract Long Register with Memory
8608 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8609 match(Set dst (SubL dst (LoadL mem)));
8610 effect(KILL cr);
8611 ins_cost(125);
8612 format %{ "SUB $dst.lo,$mem\n\t"
8613 "SBB $dst.hi,$mem+4" %}
8614 opcode(0x2B, 0x1B);
8615 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8616 ins_pipe( ialu_reg_long_mem );
8617 %}
8618
8619 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8620 match(Set dst (SubL zero dst));
8621 effect(KILL cr);
8622 ins_cost(300);
8623 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
8624 ins_encode( neg_long(dst) );
8625 ins_pipe( ialu_reg_reg_long );
8626 %}
8627
8628 // And Long Register with Register
8629 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8630 match(Set dst (AndL dst src));
8631 effect(KILL cr);
8632 format %{ "AND $dst.lo,$src.lo\n\t"
8633 "AND $dst.hi,$src.hi" %}
8634 opcode(0x23,0x23);
8635 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8636 ins_pipe( ialu_reg_reg_long );
8637 %}
8638
8639 // And Long Register with Immediate
8640 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8641 match(Set dst (AndL dst src));
8642 effect(KILL cr);
8643 format %{ "AND $dst.lo,$src.lo\n\t"
8644 "AND $dst.hi,$src.hi" %}
8645 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
8646 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8647 ins_pipe( ialu_reg_long );
8648 %}
8649
8650 // And Long Register with Memory
8651 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8652 match(Set dst (AndL dst (LoadL mem)));
8653 effect(KILL cr);
8654 ins_cost(125);
8655 format %{ "AND $dst.lo,$mem\n\t"
8656 "AND $dst.hi,$mem+4" %}
8657 opcode(0x23, 0x23);
8658 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8659 ins_pipe( ialu_reg_long_mem );
8660 %}
8661
8662 // BMI1 instructions
8663 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{
8664 match(Set dst (AndL (XorL src1 minus_1) src2));
8665 predicate(UseBMI1Instructions);
8666 effect(KILL cr, TEMP dst);
8667
8668 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t"
8669 "ANDNL $dst.hi, $src1.hi, $src2.hi"
8670 %}
8671
8672 ins_encode %{
8673 Register Rdst = $dst$$Register;
8674 Register Rsrc1 = $src1$$Register;
8675 Register Rsrc2 = $src2$$Register;
8676 __ andnl(Rdst, Rsrc1, Rsrc2);
8677 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2));
8678 %}
8679 ins_pipe(ialu_reg_reg_long);
8680 %}
8681
8682 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{
8683 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) ));
8684 predicate(UseBMI1Instructions);
8685 effect(KILL cr, TEMP dst);
8686
8687 ins_cost(125);
8688 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t"
8689 "ANDNL $dst.hi, $src1.hi, $src2+4"
8690 %}
8691
8692 ins_encode %{
8693 Register Rdst = $dst$$Register;
8694 Register Rsrc1 = $src1$$Register;
8695 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none);
8696
8697 __ andnl(Rdst, Rsrc1, $src2$$Address);
8698 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi);
8699 %}
8700 ins_pipe(ialu_reg_mem);
8701 %}
8702
8703 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{
8704 match(Set dst (AndL (SubL imm_zero src) src));
8705 predicate(UseBMI1Instructions);
8706 effect(KILL cr, TEMP dst);
8707
8708 format %{ "MOVL $dst.hi, 0\n\t"
8709 "BLSIL $dst.lo, $src.lo\n\t"
8710 "JNZ done\n\t"
8711 "BLSIL $dst.hi, $src.hi\n"
8712 "done:"
8713 %}
8714
8715 ins_encode %{
8716 Label done;
8717 Register Rdst = $dst$$Register;
8718 Register Rsrc = $src$$Register;
8719 __ movl(HIGH_FROM_LOW(Rdst), 0);
8720 __ blsil(Rdst, Rsrc);
8721 __ jccb(Assembler::notZero, done);
8722 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8723 __ bind(done);
8724 %}
8725 ins_pipe(ialu_reg);
8726 %}
8727
8728 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{
8729 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
8730 predicate(UseBMI1Instructions);
8731 effect(KILL cr, TEMP dst);
8732
8733 ins_cost(125);
8734 format %{ "MOVL $dst.hi, 0\n\t"
8735 "BLSIL $dst.lo, $src\n\t"
8736 "JNZ done\n\t"
8737 "BLSIL $dst.hi, $src+4\n"
8738 "done:"
8739 %}
8740
8741 ins_encode %{
8742 Label done;
8743 Register Rdst = $dst$$Register;
8744 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8745
8746 __ movl(HIGH_FROM_LOW(Rdst), 0);
8747 __ blsil(Rdst, $src$$Address);
8748 __ jccb(Assembler::notZero, done);
8749 __ blsil(HIGH_FROM_LOW(Rdst), src_hi);
8750 __ bind(done);
8751 %}
8752 ins_pipe(ialu_reg_mem);
8753 %}
8754
8755 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8756 %{
8757 match(Set dst (XorL (AddL src minus_1) src));
8758 predicate(UseBMI1Instructions);
8759 effect(KILL cr, TEMP dst);
8760
8761 format %{ "MOVL $dst.hi, 0\n\t"
8762 "BLSMSKL $dst.lo, $src.lo\n\t"
8763 "JNC done\n\t"
8764 "BLSMSKL $dst.hi, $src.hi\n"
8765 "done:"
8766 %}
8767
8768 ins_encode %{
8769 Label done;
8770 Register Rdst = $dst$$Register;
8771 Register Rsrc = $src$$Register;
8772 __ movl(HIGH_FROM_LOW(Rdst), 0);
8773 __ blsmskl(Rdst, Rsrc);
8774 __ jccb(Assembler::carryClear, done);
8775 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8776 __ bind(done);
8777 %}
8778
8779 ins_pipe(ialu_reg);
8780 %}
8781
8782 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8783 %{
8784 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ));
8785 predicate(UseBMI1Instructions);
8786 effect(KILL cr, TEMP dst);
8787
8788 ins_cost(125);
8789 format %{ "MOVL $dst.hi, 0\n\t"
8790 "BLSMSKL $dst.lo, $src\n\t"
8791 "JNC done\n\t"
8792 "BLSMSKL $dst.hi, $src+4\n"
8793 "done:"
8794 %}
8795
8796 ins_encode %{
8797 Label done;
8798 Register Rdst = $dst$$Register;
8799 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8800
8801 __ movl(HIGH_FROM_LOW(Rdst), 0);
8802 __ blsmskl(Rdst, $src$$Address);
8803 __ jccb(Assembler::carryClear, done);
8804 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi);
8805 __ bind(done);
8806 %}
8807
8808 ins_pipe(ialu_reg_mem);
8809 %}
8810
8811 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8812 %{
8813 match(Set dst (AndL (AddL src minus_1) src) );
8814 predicate(UseBMI1Instructions);
8815 effect(KILL cr, TEMP dst);
8816
8817 format %{ "MOVL $dst.hi, $src.hi\n\t"
8818 "BLSRL $dst.lo, $src.lo\n\t"
8819 "JNC done\n\t"
8820 "BLSRL $dst.hi, $src.hi\n"
8821 "done:"
8822 %}
8823
8824 ins_encode %{
8825 Label done;
8826 Register Rdst = $dst$$Register;
8827 Register Rsrc = $src$$Register;
8828 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8829 __ blsrl(Rdst, Rsrc);
8830 __ jccb(Assembler::carryClear, done);
8831 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8832 __ bind(done);
8833 %}
8834
8835 ins_pipe(ialu_reg);
8836 %}
8837
8838 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8839 %{
8840 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) ));
8841 predicate(UseBMI1Instructions);
8842 effect(KILL cr, TEMP dst);
8843
8844 ins_cost(125);
8845 format %{ "MOVL $dst.hi, $src+4\n\t"
8846 "BLSRL $dst.lo, $src\n\t"
8847 "JNC done\n\t"
8848 "BLSRL $dst.hi, $src+4\n"
8849 "done:"
8850 %}
8851
8852 ins_encode %{
8853 Label done;
8854 Register Rdst = $dst$$Register;
8855 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8856 __ movl(HIGH_FROM_LOW(Rdst), src_hi);
8857 __ blsrl(Rdst, $src$$Address);
8858 __ jccb(Assembler::carryClear, done);
8859 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi);
8860 __ bind(done);
8861 %}
8862
8863 ins_pipe(ialu_reg_mem);
8864 %}
8865
8866 // Or Long Register with Register
8867 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8868 match(Set dst (OrL dst src));
8869 effect(KILL cr);
8870 format %{ "OR $dst.lo,$src.lo\n\t"
8871 "OR $dst.hi,$src.hi" %}
8872 opcode(0x0B,0x0B);
8873 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8874 ins_pipe( ialu_reg_reg_long );
8875 %}
8876
8877 // Or Long Register with Immediate
8878 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8879 match(Set dst (OrL dst src));
8880 effect(KILL cr);
8881 format %{ "OR $dst.lo,$src.lo\n\t"
8882 "OR $dst.hi,$src.hi" %}
8883 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
8884 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8885 ins_pipe( ialu_reg_long );
8886 %}
8887
8888 // Or Long Register with Memory
8889 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8890 match(Set dst (OrL dst (LoadL mem)));
8891 effect(KILL cr);
8892 ins_cost(125);
8893 format %{ "OR $dst.lo,$mem\n\t"
8894 "OR $dst.hi,$mem+4" %}
8895 opcode(0x0B,0x0B);
8896 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8897 ins_pipe( ialu_reg_long_mem );
8898 %}
8899
8900 // Xor Long Register with Register
8901 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8902 match(Set dst (XorL dst src));
8903 effect(KILL cr);
8904 format %{ "XOR $dst.lo,$src.lo\n\t"
8905 "XOR $dst.hi,$src.hi" %}
8906 opcode(0x33,0x33);
8907 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8908 ins_pipe( ialu_reg_reg_long );
8909 %}
8910
8911 // Xor Long Register with Immediate -1
8912 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
8913 match(Set dst (XorL dst imm));
8914 format %{ "NOT $dst.lo\n\t"
8915 "NOT $dst.hi" %}
8916 ins_encode %{
8917 __ notl($dst$$Register);
8918 __ notl(HIGH_FROM_LOW($dst$$Register));
8919 %}
8920 ins_pipe( ialu_reg_long );
8921 %}
8922
8923 // Xor Long Register with Immediate
8924 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8925 match(Set dst (XorL dst src));
8926 effect(KILL cr);
8927 format %{ "XOR $dst.lo,$src.lo\n\t"
8928 "XOR $dst.hi,$src.hi" %}
8929 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
8930 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8931 ins_pipe( ialu_reg_long );
8932 %}
8933
8934 // Xor Long Register with Memory
8935 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8936 match(Set dst (XorL dst (LoadL mem)));
8937 effect(KILL cr);
8938 ins_cost(125);
8939 format %{ "XOR $dst.lo,$mem\n\t"
8940 "XOR $dst.hi,$mem+4" %}
8941 opcode(0x33,0x33);
8942 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8943 ins_pipe( ialu_reg_long_mem );
8944 %}
8945
8946 // Shift Left Long by 1
8947 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
8948 predicate(UseNewLongLShift);
8949 match(Set dst (LShiftL dst cnt));
8950 effect(KILL cr);
8951 ins_cost(100);
8952 format %{ "ADD $dst.lo,$dst.lo\n\t"
8953 "ADC $dst.hi,$dst.hi" %}
8954 ins_encode %{
8955 __ addl($dst$$Register,$dst$$Register);
8956 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8957 %}
8958 ins_pipe( ialu_reg_long );
8959 %}
8960
8961 // Shift Left Long by 2
8962 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
8963 predicate(UseNewLongLShift);
8964 match(Set dst (LShiftL dst cnt));
8965 effect(KILL cr);
8966 ins_cost(100);
8967 format %{ "ADD $dst.lo,$dst.lo\n\t"
8968 "ADC $dst.hi,$dst.hi\n\t"
8969 "ADD $dst.lo,$dst.lo\n\t"
8970 "ADC $dst.hi,$dst.hi" %}
8971 ins_encode %{
8972 __ addl($dst$$Register,$dst$$Register);
8973 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8974 __ addl($dst$$Register,$dst$$Register);
8975 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8976 %}
8977 ins_pipe( ialu_reg_long );
8978 %}
8979
8980 // Shift Left Long by 3
8981 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
8982 predicate(UseNewLongLShift);
8983 match(Set dst (LShiftL dst cnt));
8984 effect(KILL cr);
8985 ins_cost(100);
8986 format %{ "ADD $dst.lo,$dst.lo\n\t"
8987 "ADC $dst.hi,$dst.hi\n\t"
8988 "ADD $dst.lo,$dst.lo\n\t"
8989 "ADC $dst.hi,$dst.hi\n\t"
8990 "ADD $dst.lo,$dst.lo\n\t"
8991 "ADC $dst.hi,$dst.hi" %}
8992 ins_encode %{
8993 __ addl($dst$$Register,$dst$$Register);
8994 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8995 __ addl($dst$$Register,$dst$$Register);
8996 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8997 __ addl($dst$$Register,$dst$$Register);
8998 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8999 %}
9000 ins_pipe( ialu_reg_long );
9001 %}
9002
9003 // Shift Left Long by 1-31
9004 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9005 match(Set dst (LShiftL dst cnt));
9006 effect(KILL cr);
9007 ins_cost(200);
9008 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9009 "SHL $dst.lo,$cnt" %}
9010 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9011 ins_encode( move_long_small_shift(dst,cnt) );
9012 ins_pipe( ialu_reg_long );
9013 %}
9014
9015 // Shift Left Long by 32-63
9016 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9017 match(Set dst (LShiftL dst cnt));
9018 effect(KILL cr);
9019 ins_cost(300);
9020 format %{ "MOV $dst.hi,$dst.lo\n"
9021 "\tSHL $dst.hi,$cnt-32\n"
9022 "\tXOR $dst.lo,$dst.lo" %}
9023 opcode(0xC1, 0x4); /* C1 /4 ib */
9024 ins_encode( move_long_big_shift_clr(dst,cnt) );
9025 ins_pipe( ialu_reg_long );
9026 %}
9027
9028 // Shift Left Long by variable
9029 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9030 match(Set dst (LShiftL dst shift));
9031 effect(KILL cr);
9032 ins_cost(500+200);
9033 size(17);
9034 format %{ "TEST $shift,32\n\t"
9035 "JEQ,s small\n\t"
9036 "MOV $dst.hi,$dst.lo\n\t"
9037 "XOR $dst.lo,$dst.lo\n"
9038 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9039 "SHL $dst.lo,$shift" %}
9040 ins_encode( shift_left_long( dst, shift ) );
9041 ins_pipe( pipe_slow );
9042 %}
9043
9044 // Shift Right Long by 1-31
9045 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9046 match(Set dst (URShiftL dst cnt));
9047 effect(KILL cr);
9048 ins_cost(200);
9049 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9050 "SHR $dst.hi,$cnt" %}
9051 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9052 ins_encode( move_long_small_shift(dst,cnt) );
9053 ins_pipe( ialu_reg_long );
9054 %}
9055
9056 // Shift Right Long by 32-63
9057 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9058 match(Set dst (URShiftL dst cnt));
9059 effect(KILL cr);
9060 ins_cost(300);
9061 format %{ "MOV $dst.lo,$dst.hi\n"
9062 "\tSHR $dst.lo,$cnt-32\n"
9063 "\tXOR $dst.hi,$dst.hi" %}
9064 opcode(0xC1, 0x5); /* C1 /5 ib */
9065 ins_encode( move_long_big_shift_clr(dst,cnt) );
9066 ins_pipe( ialu_reg_long );
9067 %}
9068
9069 // Shift Right Long by variable
9070 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9071 match(Set dst (URShiftL dst shift));
9072 effect(KILL cr);
9073 ins_cost(600);
9074 size(17);
9075 format %{ "TEST $shift,32\n\t"
9076 "JEQ,s small\n\t"
9077 "MOV $dst.lo,$dst.hi\n\t"
9078 "XOR $dst.hi,$dst.hi\n"
9079 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9080 "SHR $dst.hi,$shift" %}
9081 ins_encode( shift_right_long( dst, shift ) );
9082 ins_pipe( pipe_slow );
9083 %}
9084
9085 // Shift Right Long by 1-31
9086 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9087 match(Set dst (RShiftL dst cnt));
9088 effect(KILL cr);
9089 ins_cost(200);
9090 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9091 "SAR $dst.hi,$cnt" %}
9092 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9093 ins_encode( move_long_small_shift(dst,cnt) );
9094 ins_pipe( ialu_reg_long );
9095 %}
9096
9097 // Shift Right Long by 32-63
9098 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9099 match(Set dst (RShiftL dst cnt));
9100 effect(KILL cr);
9101 ins_cost(300);
9102 format %{ "MOV $dst.lo,$dst.hi\n"
9103 "\tSAR $dst.lo,$cnt-32\n"
9104 "\tSAR $dst.hi,31" %}
9105 opcode(0xC1, 0x7); /* C1 /7 ib */
9106 ins_encode( move_long_big_shift_sign(dst,cnt) );
9107 ins_pipe( ialu_reg_long );
9108 %}
9109
9110 // Shift Right arithmetic Long by variable
9111 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9112 match(Set dst (RShiftL dst shift));
9113 effect(KILL cr);
9114 ins_cost(600);
9115 size(18);
9116 format %{ "TEST $shift,32\n\t"
9117 "JEQ,s small\n\t"
9118 "MOV $dst.lo,$dst.hi\n\t"
9119 "SAR $dst.hi,31\n"
9120 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9121 "SAR $dst.hi,$shift" %}
9122 ins_encode( shift_right_arith_long( dst, shift ) );
9123 ins_pipe( pipe_slow );
9124 %}
9125
9126
9127 //----------Double Instructions------------------------------------------------
9128 // Double Math
9129
9130 // Compare & branch
9131
9132 // P6 version of float compare, sets condition codes in EFLAGS
9133 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9134 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9135 match(Set cr (CmpD src1 src2));
9136 effect(KILL rax);
9137 ins_cost(150);
9138 format %{ "FLD $src1\n\t"
9139 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9140 "JNP exit\n\t"
9141 "MOV ah,1 // saw a NaN, set CF\n\t"
9142 "SAHF\n"
9143 "exit:\tNOP // avoid branch to branch" %}
9144 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9145 ins_encode( Push_Reg_DPR(src1),
9146 OpcP, RegOpc(src2),
9147 cmpF_P6_fixup );
9148 ins_pipe( pipe_slow );
9149 %}
9150
9151 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9152 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9153 match(Set cr (CmpD src1 src2));
9154 ins_cost(150);
9155 format %{ "FLD $src1\n\t"
9156 "FUCOMIP ST,$src2 // P6 instruction" %}
9157 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9158 ins_encode( Push_Reg_DPR(src1),
9159 OpcP, RegOpc(src2));
9160 ins_pipe( pipe_slow );
9161 %}
9162
9163 // Compare & branch
9164 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9165 predicate(UseSSE<=1);
9166 match(Set cr (CmpD src1 src2));
9167 effect(KILL rax);
9168 ins_cost(200);
9169 format %{ "FLD $src1\n\t"
9170 "FCOMp $src2\n\t"
9171 "FNSTSW AX\n\t"
9172 "TEST AX,0x400\n\t"
9173 "JZ,s flags\n\t"
9174 "MOV AH,1\t# unordered treat as LT\n"
9175 "flags:\tSAHF" %}
9176 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9177 ins_encode( Push_Reg_DPR(src1),
9178 OpcP, RegOpc(src2),
9179 fpu_flags);
9180 ins_pipe( pipe_slow );
9181 %}
9182
9183 // Compare vs zero into -1,0,1
9184 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9185 predicate(UseSSE<=1);
9186 match(Set dst (CmpD3 src1 zero));
9187 effect(KILL cr, KILL rax);
9188 ins_cost(280);
9189 format %{ "FTSTD $dst,$src1" %}
9190 opcode(0xE4, 0xD9);
9191 ins_encode( Push_Reg_DPR(src1),
9192 OpcS, OpcP, PopFPU,
9193 CmpF_Result(dst));
9194 ins_pipe( pipe_slow );
9195 %}
9196
9197 // Compare into -1,0,1
9198 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9199 predicate(UseSSE<=1);
9200 match(Set dst (CmpD3 src1 src2));
9201 effect(KILL cr, KILL rax);
9202 ins_cost(300);
9203 format %{ "FCMPD $dst,$src1,$src2" %}
9204 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9205 ins_encode( Push_Reg_DPR(src1),
9206 OpcP, RegOpc(src2),
9207 CmpF_Result(dst));
9208 ins_pipe( pipe_slow );
9209 %}
9210
9211 // float compare and set condition codes in EFLAGS by XMM regs
9212 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9213 predicate(UseSSE>=2);
9214 match(Set cr (CmpD src1 src2));
9215 ins_cost(145);
9216 format %{ "UCOMISD $src1,$src2\n\t"
9217 "JNP,s exit\n\t"
9218 "PUSHF\t# saw NaN, set CF\n\t"
9219 "AND [rsp], #0xffffff2b\n\t"
9220 "POPF\n"
9221 "exit:" %}
9222 ins_encode %{
9223 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9224 emit_cmpfp_fixup(_masm);
9225 %}
9226 ins_pipe( pipe_slow );
9227 %}
9228
9229 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9230 predicate(UseSSE>=2);
9231 match(Set cr (CmpD src1 src2));
9232 ins_cost(100);
9233 format %{ "UCOMISD $src1,$src2" %}
9234 ins_encode %{
9235 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9236 %}
9237 ins_pipe( pipe_slow );
9238 %}
9239
9240 // float compare and set condition codes in EFLAGS by XMM regs
9241 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9242 predicate(UseSSE>=2);
9243 match(Set cr (CmpD src1 (LoadD src2)));
9244 ins_cost(145);
9245 format %{ "UCOMISD $src1,$src2\n\t"
9246 "JNP,s exit\n\t"
9247 "PUSHF\t# saw NaN, set CF\n\t"
9248 "AND [rsp], #0xffffff2b\n\t"
9249 "POPF\n"
9250 "exit:" %}
9251 ins_encode %{
9252 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9253 emit_cmpfp_fixup(_masm);
9254 %}
9255 ins_pipe( pipe_slow );
9256 %}
9257
9258 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9259 predicate(UseSSE>=2);
9260 match(Set cr (CmpD src1 (LoadD src2)));
9261 ins_cost(100);
9262 format %{ "UCOMISD $src1,$src2" %}
9263 ins_encode %{
9264 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9265 %}
9266 ins_pipe( pipe_slow );
9267 %}
9268
9269 // Compare into -1,0,1 in XMM
9270 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9271 predicate(UseSSE>=2);
9272 match(Set dst (CmpD3 src1 src2));
9273 effect(KILL cr);
9274 ins_cost(255);
9275 format %{ "UCOMISD $src1, $src2\n\t"
9276 "MOV $dst, #-1\n\t"
9277 "JP,s done\n\t"
9278 "JB,s done\n\t"
9279 "SETNE $dst\n\t"
9280 "MOVZB $dst, $dst\n"
9281 "done:" %}
9282 ins_encode %{
9283 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9284 emit_cmpfp3(_masm, $dst$$Register);
9285 %}
9286 ins_pipe( pipe_slow );
9287 %}
9288
9289 // Compare into -1,0,1 in XMM and memory
9290 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9291 predicate(UseSSE>=2);
9292 match(Set dst (CmpD3 src1 (LoadD src2)));
9293 effect(KILL cr);
9294 ins_cost(275);
9295 format %{ "UCOMISD $src1, $src2\n\t"
9296 "MOV $dst, #-1\n\t"
9297 "JP,s done\n\t"
9298 "JB,s done\n\t"
9299 "SETNE $dst\n\t"
9300 "MOVZB $dst, $dst\n"
9301 "done:" %}
9302 ins_encode %{
9303 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9304 emit_cmpfp3(_masm, $dst$$Register);
9305 %}
9306 ins_pipe( pipe_slow );
9307 %}
9308
9309
9310 instruct subDPR_reg(regDPR dst, regDPR src) %{
9311 predicate (UseSSE <=1);
9312 match(Set dst (SubD dst src));
9313
9314 format %{ "FLD $src\n\t"
9315 "DSUBp $dst,ST" %}
9316 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9317 ins_cost(150);
9318 ins_encode( Push_Reg_DPR(src),
9319 OpcP, RegOpc(dst) );
9320 ins_pipe( fpu_reg_reg );
9321 %}
9322
9323 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9324 predicate (UseSSE <=1);
9325 match(Set dst (RoundDouble (SubD src1 src2)));
9326 ins_cost(250);
9327
9328 format %{ "FLD $src2\n\t"
9329 "DSUB ST,$src1\n\t"
9330 "FSTP_D $dst\t# D-round" %}
9331 opcode(0xD8, 0x5);
9332 ins_encode( Push_Reg_DPR(src2),
9333 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9334 ins_pipe( fpu_mem_reg_reg );
9335 %}
9336
9337
9338 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9339 predicate (UseSSE <=1);
9340 match(Set dst (SubD dst (LoadD src)));
9341 ins_cost(150);
9342
9343 format %{ "FLD $src\n\t"
9344 "DSUBp $dst,ST" %}
9345 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9346 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9347 OpcP, RegOpc(dst) );
9348 ins_pipe( fpu_reg_mem );
9349 %}
9350
9351 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9352 predicate (UseSSE<=1);
9353 match(Set dst (AbsD src));
9354 ins_cost(100);
9355 format %{ "FABS" %}
9356 opcode(0xE1, 0xD9);
9357 ins_encode( OpcS, OpcP );
9358 ins_pipe( fpu_reg_reg );
9359 %}
9360
9361 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9362 predicate(UseSSE<=1);
9363 match(Set dst (NegD src));
9364 ins_cost(100);
9365 format %{ "FCHS" %}
9366 opcode(0xE0, 0xD9);
9367 ins_encode( OpcS, OpcP );
9368 ins_pipe( fpu_reg_reg );
9369 %}
9370
9371 instruct addDPR_reg(regDPR dst, regDPR src) %{
9372 predicate(UseSSE<=1);
9373 match(Set dst (AddD dst src));
9374 format %{ "FLD $src\n\t"
9375 "DADD $dst,ST" %}
9376 size(4);
9377 ins_cost(150);
9378 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9379 ins_encode( Push_Reg_DPR(src),
9380 OpcP, RegOpc(dst) );
9381 ins_pipe( fpu_reg_reg );
9382 %}
9383
9384
9385 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9386 predicate(UseSSE<=1);
9387 match(Set dst (RoundDouble (AddD src1 src2)));
9388 ins_cost(250);
9389
9390 format %{ "FLD $src2\n\t"
9391 "DADD ST,$src1\n\t"
9392 "FSTP_D $dst\t# D-round" %}
9393 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9394 ins_encode( Push_Reg_DPR(src2),
9395 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9396 ins_pipe( fpu_mem_reg_reg );
9397 %}
9398
9399
9400 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9401 predicate(UseSSE<=1);
9402 match(Set dst (AddD dst (LoadD src)));
9403 ins_cost(150);
9404
9405 format %{ "FLD $src\n\t"
9406 "DADDp $dst,ST" %}
9407 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9408 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9409 OpcP, RegOpc(dst) );
9410 ins_pipe( fpu_reg_mem );
9411 %}
9412
9413 // add-to-memory
9414 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9415 predicate(UseSSE<=1);
9416 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9417 ins_cost(150);
9418
9419 format %{ "FLD_D $dst\n\t"
9420 "DADD ST,$src\n\t"
9421 "FST_D $dst" %}
9422 opcode(0xDD, 0x0);
9423 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9424 Opcode(0xD8), RegOpc(src),
9425 set_instruction_start,
9426 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9427 ins_pipe( fpu_reg_mem );
9428 %}
9429
9430 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9431 predicate(UseSSE<=1);
9432 match(Set dst (AddD dst con));
9433 ins_cost(125);
9434 format %{ "FLD1\n\t"
9435 "DADDp $dst,ST" %}
9436 ins_encode %{
9437 __ fld1();
9438 __ faddp($dst$$reg);
9439 %}
9440 ins_pipe(fpu_reg);
9441 %}
9442
9443 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9444 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9445 match(Set dst (AddD dst con));
9446 ins_cost(200);
9447 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9448 "DADDp $dst,ST" %}
9449 ins_encode %{
9450 __ fld_d($constantaddress($con));
9451 __ faddp($dst$$reg);
9452 %}
9453 ins_pipe(fpu_reg_mem);
9454 %}
9455
9456 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9457 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9458 match(Set dst (RoundDouble (AddD src con)));
9459 ins_cost(200);
9460 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9461 "DADD ST,$src\n\t"
9462 "FSTP_D $dst\t# D-round" %}
9463 ins_encode %{
9464 __ fld_d($constantaddress($con));
9465 __ fadd($src$$reg);
9466 __ fstp_d(Address(rsp, $dst$$disp));
9467 %}
9468 ins_pipe(fpu_mem_reg_con);
9469 %}
9470
9471 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9472 predicate(UseSSE<=1);
9473 match(Set dst (MulD dst src));
9474 format %{ "FLD $src\n\t"
9475 "DMULp $dst,ST" %}
9476 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9477 ins_cost(150);
9478 ins_encode( Push_Reg_DPR(src),
9479 OpcP, RegOpc(dst) );
9480 ins_pipe( fpu_reg_reg );
9481 %}
9482
9483 // Strict FP instruction biases argument before multiply then
9484 // biases result to avoid double rounding of subnormals.
9485 //
9486 // scale arg1 by multiplying arg1 by 2^(-15360)
9487 // load arg2
9488 // multiply scaled arg1 by arg2
9489 // rescale product by 2^(15360)
9490 //
9491 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9492 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9493 match(Set dst (MulD dst src));
9494 ins_cost(1); // Select this instruction for all strict FP double multiplies
9495
9496 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9497 "DMULp $dst,ST\n\t"
9498 "FLD $src\n\t"
9499 "DMULp $dst,ST\n\t"
9500 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9501 "DMULp $dst,ST\n\t" %}
9502 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9503 ins_encode( strictfp_bias1(dst),
9504 Push_Reg_DPR(src),
9505 OpcP, RegOpc(dst),
9506 strictfp_bias2(dst) );
9507 ins_pipe( fpu_reg_reg );
9508 %}
9509
9510 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9511 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9512 match(Set dst (MulD dst con));
9513 ins_cost(200);
9514 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9515 "DMULp $dst,ST" %}
9516 ins_encode %{
9517 __ fld_d($constantaddress($con));
9518 __ fmulp($dst$$reg);
9519 %}
9520 ins_pipe(fpu_reg_mem);
9521 %}
9522
9523
9524 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9525 predicate( UseSSE<=1 );
9526 match(Set dst (MulD dst (LoadD src)));
9527 ins_cost(200);
9528 format %{ "FLD_D $src\n\t"
9529 "DMULp $dst,ST" %}
9530 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9531 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9532 OpcP, RegOpc(dst) );
9533 ins_pipe( fpu_reg_mem );
9534 %}
9535
9536 //
9537 // Cisc-alternate to reg-reg multiply
9538 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9539 predicate( UseSSE<=1 );
9540 match(Set dst (MulD src (LoadD mem)));
9541 ins_cost(250);
9542 format %{ "FLD_D $mem\n\t"
9543 "DMUL ST,$src\n\t"
9544 "FSTP_D $dst" %}
9545 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9546 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9547 OpcReg_FPR(src),
9548 Pop_Reg_DPR(dst) );
9549 ins_pipe( fpu_reg_reg_mem );
9550 %}
9551
9552
9553 // MACRO3 -- addDPR a mulDPR
9554 // This instruction is a '2-address' instruction in that the result goes
9555 // back to src2. This eliminates a move from the macro; possibly the
9556 // register allocator will have to add it back (and maybe not).
9557 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9558 predicate( UseSSE<=1 );
9559 match(Set src2 (AddD (MulD src0 src1) src2));
9560 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9561 "DMUL ST,$src1\n\t"
9562 "DADDp $src2,ST" %}
9563 ins_cost(250);
9564 opcode(0xDD); /* LoadD DD /0 */
9565 ins_encode( Push_Reg_FPR(src0),
9566 FMul_ST_reg(src1),
9567 FAddP_reg_ST(src2) );
9568 ins_pipe( fpu_reg_reg_reg );
9569 %}
9570
9571
9572 // MACRO3 -- subDPR a mulDPR
9573 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9574 predicate( UseSSE<=1 );
9575 match(Set src2 (SubD (MulD src0 src1) src2));
9576 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9577 "DMUL ST,$src1\n\t"
9578 "DSUBRp $src2,ST" %}
9579 ins_cost(250);
9580 ins_encode( Push_Reg_FPR(src0),
9581 FMul_ST_reg(src1),
9582 Opcode(0xDE), Opc_plus(0xE0,src2));
9583 ins_pipe( fpu_reg_reg_reg );
9584 %}
9585
9586
9587 instruct divDPR_reg(regDPR dst, regDPR src) %{
9588 predicate( UseSSE<=1 );
9589 match(Set dst (DivD dst src));
9590
9591 format %{ "FLD $src\n\t"
9592 "FDIVp $dst,ST" %}
9593 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9594 ins_cost(150);
9595 ins_encode( Push_Reg_DPR(src),
9596 OpcP, RegOpc(dst) );
9597 ins_pipe( fpu_reg_reg );
9598 %}
9599
9600 // Strict FP instruction biases argument before division then
9601 // biases result, to avoid double rounding of subnormals.
9602 //
9603 // scale dividend by multiplying dividend by 2^(-15360)
9604 // load divisor
9605 // divide scaled dividend by divisor
9606 // rescale quotient by 2^(15360)
9607 //
9608 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9609 predicate (UseSSE<=1);
9610 match(Set dst (DivD dst src));
9611 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9612 ins_cost(01);
9613
9614 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9615 "DMULp $dst,ST\n\t"
9616 "FLD $src\n\t"
9617 "FDIVp $dst,ST\n\t"
9618 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9619 "DMULp $dst,ST\n\t" %}
9620 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9621 ins_encode( strictfp_bias1(dst),
9622 Push_Reg_DPR(src),
9623 OpcP, RegOpc(dst),
9624 strictfp_bias2(dst) );
9625 ins_pipe( fpu_reg_reg );
9626 %}
9627
9628 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9629 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9630 match(Set dst (RoundDouble (DivD src1 src2)));
9631
9632 format %{ "FLD $src1\n\t"
9633 "FDIV ST,$src2\n\t"
9634 "FSTP_D $dst\t# D-round" %}
9635 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9636 ins_encode( Push_Reg_DPR(src1),
9637 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9638 ins_pipe( fpu_mem_reg_reg );
9639 %}
9640
9641
9642 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9643 predicate(UseSSE<=1);
9644 match(Set dst (ModD dst src));
9645 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9646
9647 format %{ "DMOD $dst,$src" %}
9648 ins_cost(250);
9649 ins_encode(Push_Reg_Mod_DPR(dst, src),
9650 emitModDPR(),
9651 Push_Result_Mod_DPR(src),
9652 Pop_Reg_DPR(dst));
9653 ins_pipe( pipe_slow );
9654 %}
9655
9656 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9657 predicate(UseSSE>=2);
9658 match(Set dst (ModD src0 src1));
9659 effect(KILL rax, KILL cr);
9660
9661 format %{ "SUB ESP,8\t # DMOD\n"
9662 "\tMOVSD [ESP+0],$src1\n"
9663 "\tFLD_D [ESP+0]\n"
9664 "\tMOVSD [ESP+0],$src0\n"
9665 "\tFLD_D [ESP+0]\n"
9666 "loop:\tFPREM\n"
9667 "\tFWAIT\n"
9668 "\tFNSTSW AX\n"
9669 "\tSAHF\n"
9670 "\tJP loop\n"
9671 "\tFSTP_D [ESP+0]\n"
9672 "\tMOVSD $dst,[ESP+0]\n"
9673 "\tADD ESP,8\n"
9674 "\tFSTP ST0\t # Restore FPU Stack"
9675 %}
9676 ins_cost(250);
9677 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9678 ins_pipe( pipe_slow );
9679 %}
9680
9681 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9682 predicate (UseSSE<=1);
9683 match(Set dst (SinD src));
9684 ins_cost(1800);
9685 format %{ "DSIN $dst" %}
9686 opcode(0xD9, 0xFE);
9687 ins_encode( OpcP, OpcS );
9688 ins_pipe( pipe_slow );
9689 %}
9690
9691 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9692 predicate (UseSSE>=2);
9693 match(Set dst (SinD dst));
9694 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9695 ins_cost(1800);
9696 format %{ "DSIN $dst" %}
9697 opcode(0xD9, 0xFE);
9698 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9699 ins_pipe( pipe_slow );
9700 %}
9701
9702 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9703 predicate (UseSSE<=1);
9704 match(Set dst (CosD src));
9705 ins_cost(1800);
9706 format %{ "DCOS $dst" %}
9707 opcode(0xD9, 0xFF);
9708 ins_encode( OpcP, OpcS );
9709 ins_pipe( pipe_slow );
9710 %}
9711
9712 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9713 predicate (UseSSE>=2);
9714 match(Set dst (CosD dst));
9715 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9716 ins_cost(1800);
9717 format %{ "DCOS $dst" %}
9718 opcode(0xD9, 0xFF);
9719 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9720 ins_pipe( pipe_slow );
9721 %}
9722
9723 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9724 predicate (UseSSE<=1);
9725 match(Set dst(TanD src));
9726 format %{ "DTAN $dst" %}
9727 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9728 Opcode(0xDD), Opcode(0xD8)); // fstp st
9729 ins_pipe( pipe_slow );
9730 %}
9731
9732 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9733 predicate (UseSSE>=2);
9734 match(Set dst(TanD dst));
9735 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9736 format %{ "DTAN $dst" %}
9737 ins_encode( Push_SrcD(dst),
9738 Opcode(0xD9), Opcode(0xF2), // fptan
9739 Opcode(0xDD), Opcode(0xD8), // fstp st
9740 Push_ResultD(dst) );
9741 ins_pipe( pipe_slow );
9742 %}
9743
9744 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9745 predicate (UseSSE<=1);
9746 match(Set dst(AtanD dst src));
9747 format %{ "DATA $dst,$src" %}
9748 opcode(0xD9, 0xF3);
9749 ins_encode( Push_Reg_DPR(src),
9750 OpcP, OpcS, RegOpc(dst) );
9751 ins_pipe( pipe_slow );
9752 %}
9753
9754 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9755 predicate (UseSSE>=2);
9756 match(Set dst(AtanD dst src));
9757 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9758 format %{ "DATA $dst,$src" %}
9759 opcode(0xD9, 0xF3);
9760 ins_encode( Push_SrcD(src),
9761 OpcP, OpcS, Push_ResultD(dst) );
9762 ins_pipe( pipe_slow );
9763 %}
9764
9765 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9766 predicate (UseSSE<=1);
9767 match(Set dst (SqrtD src));
9768 format %{ "DSQRT $dst,$src" %}
9769 opcode(0xFA, 0xD9);
9770 ins_encode( Push_Reg_DPR(src),
9771 OpcS, OpcP, Pop_Reg_DPR(dst) );
9772 ins_pipe( pipe_slow );
9773 %}
9774
9775 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9776 predicate (UseSSE<=1);
9777 match(Set Y (PowD X Y)); // Raise X to the Yth power
9778 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9779 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9780 ins_encode %{
9781 __ subptr(rsp, 8);
9782 __ fld_s($X$$reg - 1);
9783 __ fast_pow();
9784 __ addptr(rsp, 8);
9785 %}
9786 ins_pipe( pipe_slow );
9787 %}
9788
9789 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9790 predicate (UseSSE>=2);
9791 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9792 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9793 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9794 ins_encode %{
9795 __ subptr(rsp, 8);
9796 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9797 __ fld_d(Address(rsp, 0));
9798 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9799 __ fld_d(Address(rsp, 0));
9800 __ fast_pow();
9801 __ fstp_d(Address(rsp, 0));
9802 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9803 __ addptr(rsp, 8);
9804 %}
9805 ins_pipe( pipe_slow );
9806 %}
9807
9808
9809 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9810 predicate (UseSSE<=1);
9811 match(Set dpr1 (ExpD dpr1));
9812 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9813 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
9814 ins_encode %{
9815 __ fast_exp();
9816 %}
9817 ins_pipe( pipe_slow );
9818 %}
9819
9820 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9821 predicate (UseSSE>=2);
9822 match(Set dst (ExpD src));
9823 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9824 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9825 ins_encode %{
9826 __ subptr(rsp, 8);
9827 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9828 __ fld_d(Address(rsp, 0));
9829 __ fast_exp();
9830 __ fstp_d(Address(rsp, 0));
9831 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9832 __ addptr(rsp, 8);
9833 %}
9834 ins_pipe( pipe_slow );
9835 %}
9836
9837 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9838 predicate (UseSSE<=1);
9839 // The source Double operand on FPU stack
9840 match(Set dst (Log10D src));
9841 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9842 // fxch ; swap ST(0) with ST(1)
9843 // fyl2x ; compute log_10(2) * log_2(x)
9844 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9845 "FXCH \n\t"
9846 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9847 %}
9848 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9849 Opcode(0xD9), Opcode(0xC9), // fxch
9850 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9851
9852 ins_pipe( pipe_slow );
9853 %}
9854
9855 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9856 predicate (UseSSE>=2);
9857 effect(KILL cr);
9858 match(Set dst (Log10D src));
9859 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9860 // fyl2x ; compute log_10(2) * log_2(x)
9861 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9862 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9863 %}
9864 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9865 Push_SrcD(src),
9866 Opcode(0xD9), Opcode(0xF1), // fyl2x
9867 Push_ResultD(dst));
9868
9869 ins_pipe( pipe_slow );
9870 %}
9871
9872 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
9873 predicate (UseSSE<=1);
9874 // The source Double operand on FPU stack
9875 match(Set dst (LogD src));
9876 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9877 // fxch ; swap ST(0) with ST(1)
9878 // fyl2x ; compute log_e(2) * log_2(x)
9879 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9880 "FXCH \n\t"
9881 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
9882 %}
9883 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9884 Opcode(0xD9), Opcode(0xC9), // fxch
9885 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9886
9887 ins_pipe( pipe_slow );
9888 %}
9889
9890 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
9891 predicate (UseSSE>=2);
9892 effect(KILL cr);
9893 // The source and result Double operands in XMM registers
9894 match(Set dst (LogD src));
9895 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9896 // fyl2x ; compute log_e(2) * log_2(x)
9897 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9898 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
9899 %}
9900 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9901 Push_SrcD(src),
9902 Opcode(0xD9), Opcode(0xF1), // fyl2x
9903 Push_ResultD(dst));
9904 ins_pipe( pipe_slow );
9905 %}
9906
9907 //-------------Float Instructions-------------------------------
9908 // Float Math
9909
9910 // Code for float compare:
9911 // fcompp();
9912 // fwait(); fnstsw_ax();
9913 // sahf();
9914 // movl(dst, unordered_result);
9915 // jcc(Assembler::parity, exit);
9916 // movl(dst, less_result);
9917 // jcc(Assembler::below, exit);
9918 // movl(dst, equal_result);
9919 // jcc(Assembler::equal, exit);
9920 // movl(dst, greater_result);
9921 // exit:
9922
9923 // P6 version of float compare, sets condition codes in EFLAGS
9924 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
9925 predicate(VM_Version::supports_cmov() && UseSSE == 0);
9926 match(Set cr (CmpF src1 src2));
9927 effect(KILL rax);
9928 ins_cost(150);
9929 format %{ "FLD $src1\n\t"
9930 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9931 "JNP exit\n\t"
9932 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
9933 "SAHF\n"
9934 "exit:\tNOP // avoid branch to branch" %}
9935 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9936 ins_encode( Push_Reg_DPR(src1),
9937 OpcP, RegOpc(src2),
9938 cmpF_P6_fixup );
9939 ins_pipe( pipe_slow );
9940 %}
9941
9942 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
9943 predicate(VM_Version::supports_cmov() && UseSSE == 0);
9944 match(Set cr (CmpF src1 src2));
9945 ins_cost(100);
9946 format %{ "FLD $src1\n\t"
9947 "FUCOMIP ST,$src2 // P6 instruction" %}
9948 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9949 ins_encode( Push_Reg_DPR(src1),
9950 OpcP, RegOpc(src2));
9951 ins_pipe( pipe_slow );
9952 %}
9953
9954
9955 // Compare & branch
9956 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
9957 predicate(UseSSE == 0);
9958 match(Set cr (CmpF src1 src2));
9959 effect(KILL rax);
9960 ins_cost(200);
9961 format %{ "FLD $src1\n\t"
9962 "FCOMp $src2\n\t"
9963 "FNSTSW AX\n\t"
9964 "TEST AX,0x400\n\t"
9965 "JZ,s flags\n\t"
9966 "MOV AH,1\t# unordered treat as LT\n"
9967 "flags:\tSAHF" %}
9968 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9969 ins_encode( Push_Reg_DPR(src1),
9970 OpcP, RegOpc(src2),
9971 fpu_flags);
9972 ins_pipe( pipe_slow );
9973 %}
9974
9975 // Compare vs zero into -1,0,1
9976 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9977 predicate(UseSSE == 0);
9978 match(Set dst (CmpF3 src1 zero));
9979 effect(KILL cr, KILL rax);
9980 ins_cost(280);
9981 format %{ "FTSTF $dst,$src1" %}
9982 opcode(0xE4, 0xD9);
9983 ins_encode( Push_Reg_DPR(src1),
9984 OpcS, OpcP, PopFPU,
9985 CmpF_Result(dst));
9986 ins_pipe( pipe_slow );
9987 %}
9988
9989 // Compare into -1,0,1
9990 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
9991 predicate(UseSSE == 0);
9992 match(Set dst (CmpF3 src1 src2));
9993 effect(KILL cr, KILL rax);
9994 ins_cost(300);
9995 format %{ "FCMPF $dst,$src1,$src2" %}
9996 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9997 ins_encode( Push_Reg_DPR(src1),
9998 OpcP, RegOpc(src2),
9999 CmpF_Result(dst));
10000 ins_pipe( pipe_slow );
10001 %}
10002
10003 // float compare and set condition codes in EFLAGS by XMM regs
10004 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10005 predicate(UseSSE>=1);
10006 match(Set cr (CmpF src1 src2));
10007 ins_cost(145);
10008 format %{ "UCOMISS $src1,$src2\n\t"
10009 "JNP,s exit\n\t"
10010 "PUSHF\t# saw NaN, set CF\n\t"
10011 "AND [rsp], #0xffffff2b\n\t"
10012 "POPF\n"
10013 "exit:" %}
10014 ins_encode %{
10015 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10016 emit_cmpfp_fixup(_masm);
10017 %}
10018 ins_pipe( pipe_slow );
10019 %}
10020
10021 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10022 predicate(UseSSE>=1);
10023 match(Set cr (CmpF src1 src2));
10024 ins_cost(100);
10025 format %{ "UCOMISS $src1,$src2" %}
10026 ins_encode %{
10027 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10028 %}
10029 ins_pipe( pipe_slow );
10030 %}
10031
10032 // float compare and set condition codes in EFLAGS by XMM regs
10033 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10034 predicate(UseSSE>=1);
10035 match(Set cr (CmpF src1 (LoadF src2)));
10036 ins_cost(165);
10037 format %{ "UCOMISS $src1,$src2\n\t"
10038 "JNP,s exit\n\t"
10039 "PUSHF\t# saw NaN, set CF\n\t"
10040 "AND [rsp], #0xffffff2b\n\t"
10041 "POPF\n"
10042 "exit:" %}
10043 ins_encode %{
10044 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10045 emit_cmpfp_fixup(_masm);
10046 %}
10047 ins_pipe( pipe_slow );
10048 %}
10049
10050 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10051 predicate(UseSSE>=1);
10052 match(Set cr (CmpF src1 (LoadF src2)));
10053 ins_cost(100);
10054 format %{ "UCOMISS $src1,$src2" %}
10055 ins_encode %{
10056 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10057 %}
10058 ins_pipe( pipe_slow );
10059 %}
10060
10061 // Compare into -1,0,1 in XMM
10062 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10063 predicate(UseSSE>=1);
10064 match(Set dst (CmpF3 src1 src2));
10065 effect(KILL cr);
10066 ins_cost(255);
10067 format %{ "UCOMISS $src1, $src2\n\t"
10068 "MOV $dst, #-1\n\t"
10069 "JP,s done\n\t"
10070 "JB,s done\n\t"
10071 "SETNE $dst\n\t"
10072 "MOVZB $dst, $dst\n"
10073 "done:" %}
10074 ins_encode %{
10075 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10076 emit_cmpfp3(_masm, $dst$$Register);
10077 %}
10078 ins_pipe( pipe_slow );
10079 %}
10080
10081 // Compare into -1,0,1 in XMM and memory
10082 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10083 predicate(UseSSE>=1);
10084 match(Set dst (CmpF3 src1 (LoadF src2)));
10085 effect(KILL cr);
10086 ins_cost(275);
10087 format %{ "UCOMISS $src1, $src2\n\t"
10088 "MOV $dst, #-1\n\t"
10089 "JP,s done\n\t"
10090 "JB,s done\n\t"
10091 "SETNE $dst\n\t"
10092 "MOVZB $dst, $dst\n"
10093 "done:" %}
10094 ins_encode %{
10095 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10096 emit_cmpfp3(_masm, $dst$$Register);
10097 %}
10098 ins_pipe( pipe_slow );
10099 %}
10100
10101 // Spill to obtain 24-bit precision
10102 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10103 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10104 match(Set dst (SubF src1 src2));
10105
10106 format %{ "FSUB $dst,$src1 - $src2" %}
10107 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10108 ins_encode( Push_Reg_FPR(src1),
10109 OpcReg_FPR(src2),
10110 Pop_Mem_FPR(dst) );
10111 ins_pipe( fpu_mem_reg_reg );
10112 %}
10113 //
10114 // This instruction does not round to 24-bits
10115 instruct subFPR_reg(regFPR dst, regFPR src) %{
10116 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10117 match(Set dst (SubF dst src));
10118
10119 format %{ "FSUB $dst,$src" %}
10120 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10121 ins_encode( Push_Reg_FPR(src),
10122 OpcP, RegOpc(dst) );
10123 ins_pipe( fpu_reg_reg );
10124 %}
10125
10126 // Spill to obtain 24-bit precision
10127 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10128 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10129 match(Set dst (AddF src1 src2));
10130
10131 format %{ "FADD $dst,$src1,$src2" %}
10132 opcode(0xD8, 0x0); /* D8 C0+i */
10133 ins_encode( Push_Reg_FPR(src2),
10134 OpcReg_FPR(src1),
10135 Pop_Mem_FPR(dst) );
10136 ins_pipe( fpu_mem_reg_reg );
10137 %}
10138 //
10139 // This instruction does not round to 24-bits
10140 instruct addFPR_reg(regFPR dst, regFPR src) %{
10141 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10142 match(Set dst (AddF dst src));
10143
10144 format %{ "FLD $src\n\t"
10145 "FADDp $dst,ST" %}
10146 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10147 ins_encode( Push_Reg_FPR(src),
10148 OpcP, RegOpc(dst) );
10149 ins_pipe( fpu_reg_reg );
10150 %}
10151
10152 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10153 predicate(UseSSE==0);
10154 match(Set dst (AbsF src));
10155 ins_cost(100);
10156 format %{ "FABS" %}
10157 opcode(0xE1, 0xD9);
10158 ins_encode( OpcS, OpcP );
10159 ins_pipe( fpu_reg_reg );
10160 %}
10161
10162 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10163 predicate(UseSSE==0);
10164 match(Set dst (NegF src));
10165 ins_cost(100);
10166 format %{ "FCHS" %}
10167 opcode(0xE0, 0xD9);
10168 ins_encode( OpcS, OpcP );
10169 ins_pipe( fpu_reg_reg );
10170 %}
10171
10172 // Cisc-alternate to addFPR_reg
10173 // Spill to obtain 24-bit precision
10174 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10175 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10176 match(Set dst (AddF src1 (LoadF src2)));
10177
10178 format %{ "FLD $src2\n\t"
10179 "FADD ST,$src1\n\t"
10180 "FSTP_S $dst" %}
10181 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10182 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10183 OpcReg_FPR(src1),
10184 Pop_Mem_FPR(dst) );
10185 ins_pipe( fpu_mem_reg_mem );
10186 %}
10187 //
10188 // Cisc-alternate to addFPR_reg
10189 // This instruction does not round to 24-bits
10190 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10191 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10192 match(Set dst (AddF dst (LoadF src)));
10193
10194 format %{ "FADD $dst,$src" %}
10195 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10196 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10197 OpcP, RegOpc(dst) );
10198 ins_pipe( fpu_reg_mem );
10199 %}
10200
10201 // // Following two instructions for _222_mpegaudio
10202 // Spill to obtain 24-bit precision
10203 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10204 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10205 match(Set dst (AddF src1 src2));
10206
10207 format %{ "FADD $dst,$src1,$src2" %}
10208 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10209 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10210 OpcReg_FPR(src2),
10211 Pop_Mem_FPR(dst) );
10212 ins_pipe( fpu_mem_reg_mem );
10213 %}
10214
10215 // Cisc-spill variant
10216 // Spill to obtain 24-bit precision
10217 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10218 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10219 match(Set dst (AddF src1 (LoadF src2)));
10220
10221 format %{ "FADD $dst,$src1,$src2 cisc" %}
10222 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10223 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10224 set_instruction_start,
10225 OpcP, RMopc_Mem(secondary,src1),
10226 Pop_Mem_FPR(dst) );
10227 ins_pipe( fpu_mem_mem_mem );
10228 %}
10229
10230 // Spill to obtain 24-bit precision
10231 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10232 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10233 match(Set dst (AddF src1 src2));
10234
10235 format %{ "FADD $dst,$src1,$src2" %}
10236 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10237 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10238 set_instruction_start,
10239 OpcP, RMopc_Mem(secondary,src1),
10240 Pop_Mem_FPR(dst) );
10241 ins_pipe( fpu_mem_mem_mem );
10242 %}
10243
10244
10245 // Spill to obtain 24-bit precision
10246 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10247 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10248 match(Set dst (AddF src con));
10249 format %{ "FLD $src\n\t"
10250 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10251 "FSTP_S $dst" %}
10252 ins_encode %{
10253 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10254 __ fadd_s($constantaddress($con));
10255 __ fstp_s(Address(rsp, $dst$$disp));
10256 %}
10257 ins_pipe(fpu_mem_reg_con);
10258 %}
10259 //
10260 // This instruction does not round to 24-bits
10261 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10262 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10263 match(Set dst (AddF src con));
10264 format %{ "FLD $src\n\t"
10265 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10266 "FSTP $dst" %}
10267 ins_encode %{
10268 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10269 __ fadd_s($constantaddress($con));
10270 __ fstp_d($dst$$reg);
10271 %}
10272 ins_pipe(fpu_reg_reg_con);
10273 %}
10274
10275 // Spill to obtain 24-bit precision
10276 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10277 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10278 match(Set dst (MulF src1 src2));
10279
10280 format %{ "FLD $src1\n\t"
10281 "FMUL $src2\n\t"
10282 "FSTP_S $dst" %}
10283 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10284 ins_encode( Push_Reg_FPR(src1),
10285 OpcReg_FPR(src2),
10286 Pop_Mem_FPR(dst) );
10287 ins_pipe( fpu_mem_reg_reg );
10288 %}
10289 //
10290 // This instruction does not round to 24-bits
10291 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10292 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10293 match(Set dst (MulF src1 src2));
10294
10295 format %{ "FLD $src1\n\t"
10296 "FMUL $src2\n\t"
10297 "FSTP_S $dst" %}
10298 opcode(0xD8, 0x1); /* D8 C8+i */
10299 ins_encode( Push_Reg_FPR(src2),
10300 OpcReg_FPR(src1),
10301 Pop_Reg_FPR(dst) );
10302 ins_pipe( fpu_reg_reg_reg );
10303 %}
10304
10305
10306 // Spill to obtain 24-bit precision
10307 // Cisc-alternate to reg-reg multiply
10308 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10309 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10310 match(Set dst (MulF src1 (LoadF src2)));
10311
10312 format %{ "FLD_S $src2\n\t"
10313 "FMUL $src1\n\t"
10314 "FSTP_S $dst" %}
10315 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10316 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10317 OpcReg_FPR(src1),
10318 Pop_Mem_FPR(dst) );
10319 ins_pipe( fpu_mem_reg_mem );
10320 %}
10321 //
10322 // This instruction does not round to 24-bits
10323 // Cisc-alternate to reg-reg multiply
10324 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10325 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10326 match(Set dst (MulF src1 (LoadF src2)));
10327
10328 format %{ "FMUL $dst,$src1,$src2" %}
10329 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10330 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10331 OpcReg_FPR(src1),
10332 Pop_Reg_FPR(dst) );
10333 ins_pipe( fpu_reg_reg_mem );
10334 %}
10335
10336 // Spill to obtain 24-bit precision
10337 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10338 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10339 match(Set dst (MulF src1 src2));
10340
10341 format %{ "FMUL $dst,$src1,$src2" %}
10342 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10343 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10344 set_instruction_start,
10345 OpcP, RMopc_Mem(secondary,src1),
10346 Pop_Mem_FPR(dst) );
10347 ins_pipe( fpu_mem_mem_mem );
10348 %}
10349
10350 // Spill to obtain 24-bit precision
10351 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10352 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10353 match(Set dst (MulF src con));
10354
10355 format %{ "FLD $src\n\t"
10356 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10357 "FSTP_S $dst" %}
10358 ins_encode %{
10359 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10360 __ fmul_s($constantaddress($con));
10361 __ fstp_s(Address(rsp, $dst$$disp));
10362 %}
10363 ins_pipe(fpu_mem_reg_con);
10364 %}
10365 //
10366 // This instruction does not round to 24-bits
10367 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10368 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10369 match(Set dst (MulF src con));
10370
10371 format %{ "FLD $src\n\t"
10372 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10373 "FSTP $dst" %}
10374 ins_encode %{
10375 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10376 __ fmul_s($constantaddress($con));
10377 __ fstp_d($dst$$reg);
10378 %}
10379 ins_pipe(fpu_reg_reg_con);
10380 %}
10381
10382
10383 //
10384 // MACRO1 -- subsume unshared load into mulFPR
10385 // This instruction does not round to 24-bits
10386 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10387 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10388 match(Set dst (MulF (LoadF mem1) src));
10389
10390 format %{ "FLD $mem1 ===MACRO1===\n\t"
10391 "FMUL ST,$src\n\t"
10392 "FSTP $dst" %}
10393 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10394 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10395 OpcReg_FPR(src),
10396 Pop_Reg_FPR(dst) );
10397 ins_pipe( fpu_reg_reg_mem );
10398 %}
10399 //
10400 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10401 // This instruction does not round to 24-bits
10402 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10403 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10404 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10405 ins_cost(95);
10406
10407 format %{ "FLD $mem1 ===MACRO2===\n\t"
10408 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10409 "FADD ST,$src2\n\t"
10410 "FSTP $dst" %}
10411 opcode(0xD9); /* LoadF D9 /0 */
10412 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10413 FMul_ST_reg(src1),
10414 FAdd_ST_reg(src2),
10415 Pop_Reg_FPR(dst) );
10416 ins_pipe( fpu_reg_mem_reg_reg );
10417 %}
10418
10419 // MACRO3 -- addFPR a mulFPR
10420 // This instruction does not round to 24-bits. It is a '2-address'
10421 // instruction in that the result goes back to src2. This eliminates
10422 // a move from the macro; possibly the register allocator will have
10423 // to add it back (and maybe not).
10424 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10425 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10426 match(Set src2 (AddF (MulF src0 src1) src2));
10427
10428 format %{ "FLD $src0 ===MACRO3===\n\t"
10429 "FMUL ST,$src1\n\t"
10430 "FADDP $src2,ST" %}
10431 opcode(0xD9); /* LoadF D9 /0 */
10432 ins_encode( Push_Reg_FPR(src0),
10433 FMul_ST_reg(src1),
10434 FAddP_reg_ST(src2) );
10435 ins_pipe( fpu_reg_reg_reg );
10436 %}
10437
10438 // MACRO4 -- divFPR subFPR
10439 // This instruction does not round to 24-bits
10440 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10441 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10442 match(Set dst (DivF (SubF src2 src1) src3));
10443
10444 format %{ "FLD $src2 ===MACRO4===\n\t"
10445 "FSUB ST,$src1\n\t"
10446 "FDIV ST,$src3\n\t"
10447 "FSTP $dst" %}
10448 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10449 ins_encode( Push_Reg_FPR(src2),
10450 subFPR_divFPR_encode(src1,src3),
10451 Pop_Reg_FPR(dst) );
10452 ins_pipe( fpu_reg_reg_reg_reg );
10453 %}
10454
10455 // Spill to obtain 24-bit precision
10456 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10457 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10458 match(Set dst (DivF src1 src2));
10459
10460 format %{ "FDIV $dst,$src1,$src2" %}
10461 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10462 ins_encode( Push_Reg_FPR(src1),
10463 OpcReg_FPR(src2),
10464 Pop_Mem_FPR(dst) );
10465 ins_pipe( fpu_mem_reg_reg );
10466 %}
10467 //
10468 // This instruction does not round to 24-bits
10469 instruct divFPR_reg(regFPR dst, regFPR src) %{
10470 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10471 match(Set dst (DivF dst src));
10472
10473 format %{ "FDIV $dst,$src" %}
10474 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10475 ins_encode( Push_Reg_FPR(src),
10476 OpcP, RegOpc(dst) );
10477 ins_pipe( fpu_reg_reg );
10478 %}
10479
10480
10481 // Spill to obtain 24-bit precision
10482 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10483 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10484 match(Set dst (ModF src1 src2));
10485 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10486
10487 format %{ "FMOD $dst,$src1,$src2" %}
10488 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10489 emitModDPR(),
10490 Push_Result_Mod_DPR(src2),
10491 Pop_Mem_FPR(dst));
10492 ins_pipe( pipe_slow );
10493 %}
10494 //
10495 // This instruction does not round to 24-bits
10496 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10497 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10498 match(Set dst (ModF dst src));
10499 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10500
10501 format %{ "FMOD $dst,$src" %}
10502 ins_encode(Push_Reg_Mod_DPR(dst, src),
10503 emitModDPR(),
10504 Push_Result_Mod_DPR(src),
10505 Pop_Reg_FPR(dst));
10506 ins_pipe( pipe_slow );
10507 %}
10508
10509 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10510 predicate(UseSSE>=1);
10511 match(Set dst (ModF src0 src1));
10512 effect(KILL rax, KILL cr);
10513 format %{ "SUB ESP,4\t # FMOD\n"
10514 "\tMOVSS [ESP+0],$src1\n"
10515 "\tFLD_S [ESP+0]\n"
10516 "\tMOVSS [ESP+0],$src0\n"
10517 "\tFLD_S [ESP+0]\n"
10518 "loop:\tFPREM\n"
10519 "\tFWAIT\n"
10520 "\tFNSTSW AX\n"
10521 "\tSAHF\n"
10522 "\tJP loop\n"
10523 "\tFSTP_S [ESP+0]\n"
10524 "\tMOVSS $dst,[ESP+0]\n"
10525 "\tADD ESP,4\n"
10526 "\tFSTP ST0\t # Restore FPU Stack"
10527 %}
10528 ins_cost(250);
10529 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10530 ins_pipe( pipe_slow );
10531 %}
10532
10533
10534 //----------Arithmetic Conversion Instructions---------------------------------
10535 // The conversions operations are all Alpha sorted. Please keep it that way!
10536
10537 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10538 predicate(UseSSE==0);
10539 match(Set dst (RoundFloat src));
10540 ins_cost(125);
10541 format %{ "FST_S $dst,$src\t# F-round" %}
10542 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10543 ins_pipe( fpu_mem_reg );
10544 %}
10545
10546 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10547 predicate(UseSSE<=1);
10548 match(Set dst (RoundDouble src));
10549 ins_cost(125);
10550 format %{ "FST_D $dst,$src\t# D-round" %}
10551 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10552 ins_pipe( fpu_mem_reg );
10553 %}
10554
10555 // Force rounding to 24-bit precision and 6-bit exponent
10556 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10557 predicate(UseSSE==0);
10558 match(Set dst (ConvD2F src));
10559 format %{ "FST_S $dst,$src\t# F-round" %}
10560 expand %{
10561 roundFloat_mem_reg(dst,src);
10562 %}
10563 %}
10564
10565 // Force rounding to 24-bit precision and 6-bit exponent
10566 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10567 predicate(UseSSE==1);
10568 match(Set dst (ConvD2F src));
10569 effect( KILL cr );
10570 format %{ "SUB ESP,4\n\t"
10571 "FST_S [ESP],$src\t# F-round\n\t"
10572 "MOVSS $dst,[ESP]\n\t"
10573 "ADD ESP,4" %}
10574 ins_encode %{
10575 __ subptr(rsp, 4);
10576 if ($src$$reg != FPR1L_enc) {
10577 __ fld_s($src$$reg-1);
10578 __ fstp_s(Address(rsp, 0));
10579 } else {
10580 __ fst_s(Address(rsp, 0));
10581 }
10582 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10583 __ addptr(rsp, 4);
10584 %}
10585 ins_pipe( pipe_slow );
10586 %}
10587
10588 // Force rounding double precision to single precision
10589 instruct convD2F_reg(regF dst, regD src) %{
10590 predicate(UseSSE>=2);
10591 match(Set dst (ConvD2F src));
10592 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10593 ins_encode %{
10594 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10595 %}
10596 ins_pipe( pipe_slow );
10597 %}
10598
10599 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10600 predicate(UseSSE==0);
10601 match(Set dst (ConvF2D src));
10602 format %{ "FST_S $dst,$src\t# D-round" %}
10603 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10604 ins_pipe( fpu_reg_reg );
10605 %}
10606
10607 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10608 predicate(UseSSE==1);
10609 match(Set dst (ConvF2D src));
10610 format %{ "FST_D $dst,$src\t# D-round" %}
10611 expand %{
10612 roundDouble_mem_reg(dst,src);
10613 %}
10614 %}
10615
10616 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10617 predicate(UseSSE==1);
10618 match(Set dst (ConvF2D src));
10619 effect( KILL cr );
10620 format %{ "SUB ESP,4\n\t"
10621 "MOVSS [ESP] $src\n\t"
10622 "FLD_S [ESP]\n\t"
10623 "ADD ESP,4\n\t"
10624 "FSTP $dst\t# D-round" %}
10625 ins_encode %{
10626 __ subptr(rsp, 4);
10627 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10628 __ fld_s(Address(rsp, 0));
10629 __ addptr(rsp, 4);
10630 __ fstp_d($dst$$reg);
10631 %}
10632 ins_pipe( pipe_slow );
10633 %}
10634
10635 instruct convF2D_reg(regD dst, regF src) %{
10636 predicate(UseSSE>=2);
10637 match(Set dst (ConvF2D src));
10638 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10639 ins_encode %{
10640 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10641 %}
10642 ins_pipe( pipe_slow );
10643 %}
10644
10645 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10646 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10647 predicate(UseSSE<=1);
10648 match(Set dst (ConvD2I src));
10649 effect( KILL tmp, KILL cr );
10650 format %{ "FLD $src\t# Convert double to int \n\t"
10651 "FLDCW trunc mode\n\t"
10652 "SUB ESP,4\n\t"
10653 "FISTp [ESP + #0]\n\t"
10654 "FLDCW std/24-bit mode\n\t"
10655 "POP EAX\n\t"
10656 "CMP EAX,0x80000000\n\t"
10657 "JNE,s fast\n\t"
10658 "FLD_D $src\n\t"
10659 "CALL d2i_wrapper\n"
10660 "fast:" %}
10661 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10662 ins_pipe( pipe_slow );
10663 %}
10664
10665 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10666 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10667 predicate(UseSSE>=2);
10668 match(Set dst (ConvD2I src));
10669 effect( KILL tmp, KILL cr );
10670 format %{ "CVTTSD2SI $dst, $src\n\t"
10671 "CMP $dst,0x80000000\n\t"
10672 "JNE,s fast\n\t"
10673 "SUB ESP, 8\n\t"
10674 "MOVSD [ESP], $src\n\t"
10675 "FLD_D [ESP]\n\t"
10676 "ADD ESP, 8\n\t"
10677 "CALL d2i_wrapper\n"
10678 "fast:" %}
10679 ins_encode %{
10680 Label fast;
10681 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10682 __ cmpl($dst$$Register, 0x80000000);
10683 __ jccb(Assembler::notEqual, fast);
10684 __ subptr(rsp, 8);
10685 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10686 __ fld_d(Address(rsp, 0));
10687 __ addptr(rsp, 8);
10688 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10689 __ bind(fast);
10690 %}
10691 ins_pipe( pipe_slow );
10692 %}
10693
10694 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10695 predicate(UseSSE<=1);
10696 match(Set dst (ConvD2L src));
10697 effect( KILL cr );
10698 format %{ "FLD $src\t# Convert double to long\n\t"
10699 "FLDCW trunc mode\n\t"
10700 "SUB ESP,8\n\t"
10701 "FISTp [ESP + #0]\n\t"
10702 "FLDCW std/24-bit mode\n\t"
10703 "POP EAX\n\t"
10704 "POP EDX\n\t"
10705 "CMP EDX,0x80000000\n\t"
10706 "JNE,s fast\n\t"
10707 "TEST EAX,EAX\n\t"
10708 "JNE,s fast\n\t"
10709 "FLD $src\n\t"
10710 "CALL d2l_wrapper\n"
10711 "fast:" %}
10712 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10713 ins_pipe( pipe_slow );
10714 %}
10715
10716 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10717 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10718 predicate (UseSSE>=2);
10719 match(Set dst (ConvD2L src));
10720 effect( KILL cr );
10721 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10722 "MOVSD [ESP],$src\n\t"
10723 "FLD_D [ESP]\n\t"
10724 "FLDCW trunc mode\n\t"
10725 "FISTp [ESP + #0]\n\t"
10726 "FLDCW std/24-bit mode\n\t"
10727 "POP EAX\n\t"
10728 "POP EDX\n\t"
10729 "CMP EDX,0x80000000\n\t"
10730 "JNE,s fast\n\t"
10731 "TEST EAX,EAX\n\t"
10732 "JNE,s fast\n\t"
10733 "SUB ESP,8\n\t"
10734 "MOVSD [ESP],$src\n\t"
10735 "FLD_D [ESP]\n\t"
10736 "ADD ESP,8\n\t"
10737 "CALL d2l_wrapper\n"
10738 "fast:" %}
10739 ins_encode %{
10740 Label fast;
10741 __ subptr(rsp, 8);
10742 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10743 __ fld_d(Address(rsp, 0));
10744 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10745 __ fistp_d(Address(rsp, 0));
10746 // Restore the rounding mode, mask the exception
10747 if (Compile::current()->in_24_bit_fp_mode()) {
10748 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10749 } else {
10750 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10751 }
10752 // Load the converted long, adjust CPU stack
10753 __ pop(rax);
10754 __ pop(rdx);
10755 __ cmpl(rdx, 0x80000000);
10756 __ jccb(Assembler::notEqual, fast);
10757 __ testl(rax, rax);
10758 __ jccb(Assembler::notEqual, fast);
10759 __ subptr(rsp, 8);
10760 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10761 __ fld_d(Address(rsp, 0));
10762 __ addptr(rsp, 8);
10763 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10764 __ bind(fast);
10765 %}
10766 ins_pipe( pipe_slow );
10767 %}
10768
10769 // Convert a double to an int. Java semantics require we do complex
10770 // manglations in the corner cases. So we set the rounding mode to
10771 // 'zero', store the darned double down as an int, and reset the
10772 // rounding mode to 'nearest'. The hardware stores a flag value down
10773 // if we would overflow or converted a NAN; we check for this and
10774 // and go the slow path if needed.
10775 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10776 predicate(UseSSE==0);
10777 match(Set dst (ConvF2I src));
10778 effect( KILL tmp, KILL cr );
10779 format %{ "FLD $src\t# Convert float to int \n\t"
10780 "FLDCW trunc mode\n\t"
10781 "SUB ESP,4\n\t"
10782 "FISTp [ESP + #0]\n\t"
10783 "FLDCW std/24-bit mode\n\t"
10784 "POP EAX\n\t"
10785 "CMP EAX,0x80000000\n\t"
10786 "JNE,s fast\n\t"
10787 "FLD $src\n\t"
10788 "CALL d2i_wrapper\n"
10789 "fast:" %}
10790 // DPR2I_encoding works for FPR2I
10791 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10792 ins_pipe( pipe_slow );
10793 %}
10794
10795 // Convert a float in xmm to an int reg.
10796 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10797 predicate(UseSSE>=1);
10798 match(Set dst (ConvF2I src));
10799 effect( KILL tmp, KILL cr );
10800 format %{ "CVTTSS2SI $dst, $src\n\t"
10801 "CMP $dst,0x80000000\n\t"
10802 "JNE,s fast\n\t"
10803 "SUB ESP, 4\n\t"
10804 "MOVSS [ESP], $src\n\t"
10805 "FLD [ESP]\n\t"
10806 "ADD ESP, 4\n\t"
10807 "CALL d2i_wrapper\n"
10808 "fast:" %}
10809 ins_encode %{
10810 Label fast;
10811 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10812 __ cmpl($dst$$Register, 0x80000000);
10813 __ jccb(Assembler::notEqual, fast);
10814 __ subptr(rsp, 4);
10815 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10816 __ fld_s(Address(rsp, 0));
10817 __ addptr(rsp, 4);
10818 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10819 __ bind(fast);
10820 %}
10821 ins_pipe( pipe_slow );
10822 %}
10823
10824 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
10825 predicate(UseSSE==0);
10826 match(Set dst (ConvF2L src));
10827 effect( KILL cr );
10828 format %{ "FLD $src\t# Convert float to long\n\t"
10829 "FLDCW trunc mode\n\t"
10830 "SUB ESP,8\n\t"
10831 "FISTp [ESP + #0]\n\t"
10832 "FLDCW std/24-bit mode\n\t"
10833 "POP EAX\n\t"
10834 "POP EDX\n\t"
10835 "CMP EDX,0x80000000\n\t"
10836 "JNE,s fast\n\t"
10837 "TEST EAX,EAX\n\t"
10838 "JNE,s fast\n\t"
10839 "FLD $src\n\t"
10840 "CALL d2l_wrapper\n"
10841 "fast:" %}
10842 // DPR2L_encoding works for FPR2L
10843 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
10844 ins_pipe( pipe_slow );
10845 %}
10846
10847 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10848 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
10849 predicate (UseSSE>=1);
10850 match(Set dst (ConvF2L src));
10851 effect( KILL cr );
10852 format %{ "SUB ESP,8\t# Convert float to long\n\t"
10853 "MOVSS [ESP],$src\n\t"
10854 "FLD_S [ESP]\n\t"
10855 "FLDCW trunc mode\n\t"
10856 "FISTp [ESP + #0]\n\t"
10857 "FLDCW std/24-bit mode\n\t"
10858 "POP EAX\n\t"
10859 "POP EDX\n\t"
10860 "CMP EDX,0x80000000\n\t"
10861 "JNE,s fast\n\t"
10862 "TEST EAX,EAX\n\t"
10863 "JNE,s fast\n\t"
10864 "SUB ESP,4\t# Convert float to long\n\t"
10865 "MOVSS [ESP],$src\n\t"
10866 "FLD_S [ESP]\n\t"
10867 "ADD ESP,4\n\t"
10868 "CALL d2l_wrapper\n"
10869 "fast:" %}
10870 ins_encode %{
10871 Label fast;
10872 __ subptr(rsp, 8);
10873 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10874 __ fld_s(Address(rsp, 0));
10875 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10876 __ fistp_d(Address(rsp, 0));
10877 // Restore the rounding mode, mask the exception
10878 if (Compile::current()->in_24_bit_fp_mode()) {
10879 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10880 } else {
10881 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10882 }
10883 // Load the converted long, adjust CPU stack
10884 __ pop(rax);
10885 __ pop(rdx);
10886 __ cmpl(rdx, 0x80000000);
10887 __ jccb(Assembler::notEqual, fast);
10888 __ testl(rax, rax);
10889 __ jccb(Assembler::notEqual, fast);
10890 __ subptr(rsp, 4);
10891 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10892 __ fld_s(Address(rsp, 0));
10893 __ addptr(rsp, 4);
10894 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10895 __ bind(fast);
10896 %}
10897 ins_pipe( pipe_slow );
10898 %}
10899
10900 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
10901 predicate( UseSSE<=1 );
10902 match(Set dst (ConvI2D src));
10903 format %{ "FILD $src\n\t"
10904 "FSTP $dst" %}
10905 opcode(0xDB, 0x0); /* DB /0 */
10906 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
10907 ins_pipe( fpu_reg_mem );
10908 %}
10909
10910 instruct convI2D_reg(regD dst, rRegI src) %{
10911 predicate( UseSSE>=2 && !UseXmmI2D );
10912 match(Set dst (ConvI2D src));
10913 format %{ "CVTSI2SD $dst,$src" %}
10914 ins_encode %{
10915 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10916 %}
10917 ins_pipe( pipe_slow );
10918 %}
10919
10920 instruct convI2D_mem(regD dst, memory mem) %{
10921 predicate( UseSSE>=2 );
10922 match(Set dst (ConvI2D (LoadI mem)));
10923 format %{ "CVTSI2SD $dst,$mem" %}
10924 ins_encode %{
10925 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
10926 %}
10927 ins_pipe( pipe_slow );
10928 %}
10929
10930 instruct convXI2D_reg(regD dst, rRegI src)
10931 %{
10932 predicate( UseSSE>=2 && UseXmmI2D );
10933 match(Set dst (ConvI2D src));
10934
10935 format %{ "MOVD $dst,$src\n\t"
10936 "CVTDQ2PD $dst,$dst\t# i2d" %}
10937 ins_encode %{
10938 __ movdl($dst$$XMMRegister, $src$$Register);
10939 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10940 %}
10941 ins_pipe(pipe_slow); // XXX
10942 %}
10943
10944 instruct convI2DPR_mem(regDPR dst, memory mem) %{
10945 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
10946 match(Set dst (ConvI2D (LoadI mem)));
10947 format %{ "FILD $mem\n\t"
10948 "FSTP $dst" %}
10949 opcode(0xDB); /* DB /0 */
10950 ins_encode( OpcP, RMopc_Mem(0x00,mem),
10951 Pop_Reg_DPR(dst));
10952 ins_pipe( fpu_reg_mem );
10953 %}
10954
10955 // Convert a byte to a float; no rounding step needed.
10956 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
10957 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
10958 match(Set dst (ConvI2F src));
10959 format %{ "FILD $src\n\t"
10960 "FSTP $dst" %}
10961
10962 opcode(0xDB, 0x0); /* DB /0 */
10963 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
10964 ins_pipe( fpu_reg_mem );
10965 %}
10966
10967 // In 24-bit mode, force exponent rounding by storing back out
10968 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
10969 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10970 match(Set dst (ConvI2F src));
10971 ins_cost(200);
10972 format %{ "FILD $src\n\t"
10973 "FSTP_S $dst" %}
10974 opcode(0xDB, 0x0); /* DB /0 */
10975 ins_encode( Push_Mem_I(src),
10976 Pop_Mem_FPR(dst));
10977 ins_pipe( fpu_mem_mem );
10978 %}
10979
10980 // In 24-bit mode, force exponent rounding by storing back out
10981 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
10982 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10983 match(Set dst (ConvI2F (LoadI mem)));
10984 ins_cost(200);
10985 format %{ "FILD $mem\n\t"
10986 "FSTP_S $dst" %}
10987 opcode(0xDB); /* DB /0 */
10988 ins_encode( OpcP, RMopc_Mem(0x00,mem),
10989 Pop_Mem_FPR(dst));
10990 ins_pipe( fpu_mem_mem );
10991 %}
10992
10993 // This instruction does not round to 24-bits
10994 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
10995 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10996 match(Set dst (ConvI2F src));
10997 format %{ "FILD $src\n\t"
10998 "FSTP $dst" %}
10999 opcode(0xDB, 0x0); /* DB /0 */
11000 ins_encode( Push_Mem_I(src),
11001 Pop_Reg_FPR(dst));
11002 ins_pipe( fpu_reg_mem );
11003 %}
11004
11005 // This instruction does not round to 24-bits
11006 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11007 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11008 match(Set dst (ConvI2F (LoadI mem)));
11009 format %{ "FILD $mem\n\t"
11010 "FSTP $dst" %}
11011 opcode(0xDB); /* DB /0 */
11012 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11013 Pop_Reg_FPR(dst));
11014 ins_pipe( fpu_reg_mem );
11015 %}
11016
11017 // Convert an int to a float in xmm; no rounding step needed.
11018 instruct convI2F_reg(regF dst, rRegI src) %{
11019 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11020 match(Set dst (ConvI2F src));
11021 format %{ "CVTSI2SS $dst, $src" %}
11022 ins_encode %{
11023 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11024 %}
11025 ins_pipe( pipe_slow );
11026 %}
11027
11028 instruct convXI2F_reg(regF dst, rRegI src)
11029 %{
11030 predicate( UseSSE>=2 && UseXmmI2F );
11031 match(Set dst (ConvI2F src));
11032
11033 format %{ "MOVD $dst,$src\n\t"
11034 "CVTDQ2PS $dst,$dst\t# i2f" %}
11035 ins_encode %{
11036 __ movdl($dst$$XMMRegister, $src$$Register);
11037 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11038 %}
11039 ins_pipe(pipe_slow); // XXX
11040 %}
11041
11042 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11043 match(Set dst (ConvI2L src));
11044 effect(KILL cr);
11045 ins_cost(375);
11046 format %{ "MOV $dst.lo,$src\n\t"
11047 "MOV $dst.hi,$src\n\t"
11048 "SAR $dst.hi,31" %}
11049 ins_encode(convert_int_long(dst,src));
11050 ins_pipe( ialu_reg_reg_long );
11051 %}
11052
11053 // Zero-extend convert int to long
11054 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11055 match(Set dst (AndL (ConvI2L src) mask) );
11056 effect( KILL flags );
11057 ins_cost(250);
11058 format %{ "MOV $dst.lo,$src\n\t"
11059 "XOR $dst.hi,$dst.hi" %}
11060 opcode(0x33); // XOR
11061 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11062 ins_pipe( ialu_reg_reg_long );
11063 %}
11064
11065 // Zero-extend long
11066 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11067 match(Set dst (AndL src mask) );
11068 effect( KILL flags );
11069 ins_cost(250);
11070 format %{ "MOV $dst.lo,$src.lo\n\t"
11071 "XOR $dst.hi,$dst.hi\n\t" %}
11072 opcode(0x33); // XOR
11073 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11074 ins_pipe( ialu_reg_reg_long );
11075 %}
11076
11077 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11078 predicate (UseSSE<=1);
11079 match(Set dst (ConvL2D src));
11080 effect( KILL cr );
11081 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11082 "PUSH $src.lo\n\t"
11083 "FILD ST,[ESP + #0]\n\t"
11084 "ADD ESP,8\n\t"
11085 "FSTP_D $dst\t# D-round" %}
11086 opcode(0xDF, 0x5); /* DF /5 */
11087 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11088 ins_pipe( pipe_slow );
11089 %}
11090
11091 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11092 predicate (UseSSE>=2);
11093 match(Set dst (ConvL2D src));
11094 effect( KILL cr );
11095 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11096 "PUSH $src.lo\n\t"
11097 "FILD_D [ESP]\n\t"
11098 "FSTP_D [ESP]\n\t"
11099 "MOVSD $dst,[ESP]\n\t"
11100 "ADD ESP,8" %}
11101 opcode(0xDF, 0x5); /* DF /5 */
11102 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11103 ins_pipe( pipe_slow );
11104 %}
11105
11106 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11107 predicate (UseSSE>=1);
11108 match(Set dst (ConvL2F src));
11109 effect( KILL cr );
11110 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11111 "PUSH $src.lo\n\t"
11112 "FILD_D [ESP]\n\t"
11113 "FSTP_S [ESP]\n\t"
11114 "MOVSS $dst,[ESP]\n\t"
11115 "ADD ESP,8" %}
11116 opcode(0xDF, 0x5); /* DF /5 */
11117 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11118 ins_pipe( pipe_slow );
11119 %}
11120
11121 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11122 match(Set dst (ConvL2F src));
11123 effect( KILL cr );
11124 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11125 "PUSH $src.lo\n\t"
11126 "FILD ST,[ESP + #0]\n\t"
11127 "ADD ESP,8\n\t"
11128 "FSTP_S $dst\t# F-round" %}
11129 opcode(0xDF, 0x5); /* DF /5 */
11130 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11131 ins_pipe( pipe_slow );
11132 %}
11133
11134 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11135 match(Set dst (ConvL2I src));
11136 effect( DEF dst, USE src );
11137 format %{ "MOV $dst,$src.lo" %}
11138 ins_encode(enc_CopyL_Lo(dst,src));
11139 ins_pipe( ialu_reg_reg );
11140 %}
11141
11142
11143 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11144 match(Set dst (MoveF2I src));
11145 effect( DEF dst, USE src );
11146 ins_cost(100);
11147 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11148 ins_encode %{
11149 __ movl($dst$$Register, Address(rsp, $src$$disp));
11150 %}
11151 ins_pipe( ialu_reg_mem );
11152 %}
11153
11154 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11155 predicate(UseSSE==0);
11156 match(Set dst (MoveF2I src));
11157 effect( DEF dst, USE src );
11158
11159 ins_cost(125);
11160 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11161 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11162 ins_pipe( fpu_mem_reg );
11163 %}
11164
11165 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11166 predicate(UseSSE>=1);
11167 match(Set dst (MoveF2I src));
11168 effect( DEF dst, USE src );
11169
11170 ins_cost(95);
11171 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11172 ins_encode %{
11173 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11174 %}
11175 ins_pipe( pipe_slow );
11176 %}
11177
11178 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11179 predicate(UseSSE>=2);
11180 match(Set dst (MoveF2I src));
11181 effect( DEF dst, USE src );
11182 ins_cost(85);
11183 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11184 ins_encode %{
11185 __ movdl($dst$$Register, $src$$XMMRegister);
11186 %}
11187 ins_pipe( pipe_slow );
11188 %}
11189
11190 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11191 match(Set dst (MoveI2F src));
11192 effect( DEF dst, USE src );
11193
11194 ins_cost(100);
11195 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11196 ins_encode %{
11197 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11198 %}
11199 ins_pipe( ialu_mem_reg );
11200 %}
11201
11202
11203 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11204 predicate(UseSSE==0);
11205 match(Set dst (MoveI2F src));
11206 effect(DEF dst, USE src);
11207
11208 ins_cost(125);
11209 format %{ "FLD_S $src\n\t"
11210 "FSTP $dst\t# MoveI2F_stack_reg" %}
11211 opcode(0xD9); /* D9 /0, FLD m32real */
11212 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11213 Pop_Reg_FPR(dst) );
11214 ins_pipe( fpu_reg_mem );
11215 %}
11216
11217 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11218 predicate(UseSSE>=1);
11219 match(Set dst (MoveI2F src));
11220 effect( DEF dst, USE src );
11221
11222 ins_cost(95);
11223 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11224 ins_encode %{
11225 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11226 %}
11227 ins_pipe( pipe_slow );
11228 %}
11229
11230 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11231 predicate(UseSSE>=2);
11232 match(Set dst (MoveI2F src));
11233 effect( DEF dst, USE src );
11234
11235 ins_cost(85);
11236 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11237 ins_encode %{
11238 __ movdl($dst$$XMMRegister, $src$$Register);
11239 %}
11240 ins_pipe( pipe_slow );
11241 %}
11242
11243 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11244 match(Set dst (MoveD2L src));
11245 effect(DEF dst, USE src);
11246
11247 ins_cost(250);
11248 format %{ "MOV $dst.lo,$src\n\t"
11249 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11250 opcode(0x8B, 0x8B);
11251 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11252 ins_pipe( ialu_mem_long_reg );
11253 %}
11254
11255 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11256 predicate(UseSSE<=1);
11257 match(Set dst (MoveD2L src));
11258 effect(DEF dst, USE src);
11259
11260 ins_cost(125);
11261 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11262 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11263 ins_pipe( fpu_mem_reg );
11264 %}
11265
11266 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11267 predicate(UseSSE>=2);
11268 match(Set dst (MoveD2L src));
11269 effect(DEF dst, USE src);
11270 ins_cost(95);
11271 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11272 ins_encode %{
11273 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11274 %}
11275 ins_pipe( pipe_slow );
11276 %}
11277
11278 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11279 predicate(UseSSE>=2);
11280 match(Set dst (MoveD2L src));
11281 effect(DEF dst, USE src, TEMP tmp);
11282 ins_cost(85);
11283 format %{ "MOVD $dst.lo,$src\n\t"
11284 "PSHUFLW $tmp,$src,0x4E\n\t"
11285 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11286 ins_encode %{
11287 __ movdl($dst$$Register, $src$$XMMRegister);
11288 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11289 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11290 %}
11291 ins_pipe( pipe_slow );
11292 %}
11293
11294 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11295 match(Set dst (MoveL2D src));
11296 effect(DEF dst, USE src);
11297
11298 ins_cost(200);
11299 format %{ "MOV $dst,$src.lo\n\t"
11300 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11301 opcode(0x89, 0x89);
11302 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11303 ins_pipe( ialu_mem_long_reg );
11304 %}
11305
11306
11307 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11308 predicate(UseSSE<=1);
11309 match(Set dst (MoveL2D src));
11310 effect(DEF dst, USE src);
11311 ins_cost(125);
11312
11313 format %{ "FLD_D $src\n\t"
11314 "FSTP $dst\t# MoveL2D_stack_reg" %}
11315 opcode(0xDD); /* DD /0, FLD m64real */
11316 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11317 Pop_Reg_DPR(dst) );
11318 ins_pipe( fpu_reg_mem );
11319 %}
11320
11321
11322 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11323 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11324 match(Set dst (MoveL2D src));
11325 effect(DEF dst, USE src);
11326
11327 ins_cost(95);
11328 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11329 ins_encode %{
11330 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11331 %}
11332 ins_pipe( pipe_slow );
11333 %}
11334
11335 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11336 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11337 match(Set dst (MoveL2D src));
11338 effect(DEF dst, USE src);
11339
11340 ins_cost(95);
11341 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11342 ins_encode %{
11343 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11344 %}
11345 ins_pipe( pipe_slow );
11346 %}
11347
11348 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11349 predicate(UseSSE>=2);
11350 match(Set dst (MoveL2D src));
11351 effect(TEMP dst, USE src, TEMP tmp);
11352 ins_cost(85);
11353 format %{ "MOVD $dst,$src.lo\n\t"
11354 "MOVD $tmp,$src.hi\n\t"
11355 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11356 ins_encode %{
11357 __ movdl($dst$$XMMRegister, $src$$Register);
11358 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11359 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11360 %}
11361 ins_pipe( pipe_slow );
11362 %}
11363
11364
11365 // =======================================================================
11366 // fast clearing of an array
11367 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11368 predicate(!UseFastStosb);
11369 match(Set dummy (ClearArray cnt base));
11370 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11371 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11372 "SHL ECX,1\t# Convert doublewords to words\n\t"
11373 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11374 ins_encode %{
11375 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11376 %}
11377 ins_pipe( pipe_slow );
11378 %}
11379
11380 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11381 predicate(UseFastStosb);
11382 match(Set dummy (ClearArray cnt base));
11383 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11384 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11385 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11386 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11387 ins_encode %{
11388 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11389 %}
11390 ins_pipe( pipe_slow );
11391 %}
11392
11393 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11394 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11395 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11396 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11397
11398 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11399 ins_encode %{
11400 __ string_compare($str1$$Register, $str2$$Register,
11401 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11402 $tmp1$$XMMRegister);
11403 %}
11404 ins_pipe( pipe_slow );
11405 %}
11406
11407 // fast string equals
11408 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11409 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11410 match(Set result (StrEquals (Binary str1 str2) cnt));
11411 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11412
11413 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11414 ins_encode %{
11415 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11416 $cnt$$Register, $result$$Register, $tmp3$$Register,
11417 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11418 %}
11419 ins_pipe( pipe_slow );
11420 %}
11421
11422 // fast search of substring with known size.
11423 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11424 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11425 predicate(UseSSE42Intrinsics);
11426 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11427 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11428
11429 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11430 ins_encode %{
11431 int icnt2 = (int)$int_cnt2$$constant;
11432 if (icnt2 >= 8) {
11433 // IndexOf for constant substrings with size >= 8 elements
11434 // which don't need to be loaded through stack.
11435 __ string_indexofC8($str1$$Register, $str2$$Register,
11436 $cnt1$$Register, $cnt2$$Register,
11437 icnt2, $result$$Register,
11438 $vec$$XMMRegister, $tmp$$Register);
11439 } else {
11440 // Small strings are loaded through stack if they cross page boundary.
11441 __ string_indexof($str1$$Register, $str2$$Register,
11442 $cnt1$$Register, $cnt2$$Register,
11443 icnt2, $result$$Register,
11444 $vec$$XMMRegister, $tmp$$Register);
11445 }
11446 %}
11447 ins_pipe( pipe_slow );
11448 %}
11449
11450 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11451 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11452 predicate(UseSSE42Intrinsics);
11453 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11454 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11455
11456 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11457 ins_encode %{
11458 __ string_indexof($str1$$Register, $str2$$Register,
11459 $cnt1$$Register, $cnt2$$Register,
11460 (-1), $result$$Register,
11461 $vec$$XMMRegister, $tmp$$Register);
11462 %}
11463 ins_pipe( pipe_slow );
11464 %}
11465
11466 // fast array equals
11467 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11468 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11469 %{
11470 match(Set result (AryEq ary1 ary2));
11471 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11472 //ins_cost(300);
11473
11474 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11475 ins_encode %{
11476 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11477 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11478 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11479 %}
11480 ins_pipe( pipe_slow );
11481 %}
11482
11483 // encode char[] to byte[] in ISO_8859_1
11484 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11485 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11486 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11487 match(Set result (EncodeISOArray src (Binary dst len)));
11488 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11489
11490 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11491 ins_encode %{
11492 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11493 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11494 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11495 %}
11496 ins_pipe( pipe_slow );
11497 %}
11498
11499
11500 //----------Control Flow Instructions------------------------------------------
11501 // Signed compare Instructions
11502 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11503 match(Set cr (CmpI op1 op2));
11504 effect( DEF cr, USE op1, USE op2 );
11505 format %{ "CMP $op1,$op2" %}
11506 opcode(0x3B); /* Opcode 3B /r */
11507 ins_encode( OpcP, RegReg( op1, op2) );
11508 ins_pipe( ialu_cr_reg_reg );
11509 %}
11510
11511 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11512 match(Set cr (CmpI op1 op2));
11513 effect( DEF cr, USE op1 );
11514 format %{ "CMP $op1,$op2" %}
11515 opcode(0x81,0x07); /* Opcode 81 /7 */
11516 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11517 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11518 ins_pipe( ialu_cr_reg_imm );
11519 %}
11520
11521 // Cisc-spilled version of cmpI_eReg
11522 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11523 match(Set cr (CmpI op1 (LoadI op2)));
11524
11525 format %{ "CMP $op1,$op2" %}
11526 ins_cost(500);
11527 opcode(0x3B); /* Opcode 3B /r */
11528 ins_encode( OpcP, RegMem( op1, op2) );
11529 ins_pipe( ialu_cr_reg_mem );
11530 %}
11531
11532 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11533 match(Set cr (CmpI src zero));
11534 effect( DEF cr, USE src );
11535
11536 format %{ "TEST $src,$src" %}
11537 opcode(0x85);
11538 ins_encode( OpcP, RegReg( src, src ) );
11539 ins_pipe( ialu_cr_reg_imm );
11540 %}
11541
11542 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11543 match(Set cr (CmpI (AndI src con) zero));
11544
11545 format %{ "TEST $src,$con" %}
11546 opcode(0xF7,0x00);
11547 ins_encode( OpcP, RegOpc(src), Con32(con) );
11548 ins_pipe( ialu_cr_reg_imm );
11549 %}
11550
11551 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11552 match(Set cr (CmpI (AndI src mem) zero));
11553
11554 format %{ "TEST $src,$mem" %}
11555 opcode(0x85);
11556 ins_encode( OpcP, RegMem( src, mem ) );
11557 ins_pipe( ialu_cr_reg_mem );
11558 %}
11559
11560 // Unsigned compare Instructions; really, same as signed except they
11561 // produce an eFlagsRegU instead of eFlagsReg.
11562 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11563 match(Set cr (CmpU op1 op2));
11564
11565 format %{ "CMPu $op1,$op2" %}
11566 opcode(0x3B); /* Opcode 3B /r */
11567 ins_encode( OpcP, RegReg( op1, op2) );
11568 ins_pipe( ialu_cr_reg_reg );
11569 %}
11570
11571 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11572 match(Set cr (CmpU op1 op2));
11573
11574 format %{ "CMPu $op1,$op2" %}
11575 opcode(0x81,0x07); /* Opcode 81 /7 */
11576 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11577 ins_pipe( ialu_cr_reg_imm );
11578 %}
11579
11580 // // Cisc-spilled version of cmpU_eReg
11581 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11582 match(Set cr (CmpU op1 (LoadI op2)));
11583
11584 format %{ "CMPu $op1,$op2" %}
11585 ins_cost(500);
11586 opcode(0x3B); /* Opcode 3B /r */
11587 ins_encode( OpcP, RegMem( op1, op2) );
11588 ins_pipe( ialu_cr_reg_mem );
11589 %}
11590
11591 // // Cisc-spilled version of cmpU_eReg
11592 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11593 // match(Set cr (CmpU (LoadI op1) op2));
11594 //
11595 // format %{ "CMPu $op1,$op2" %}
11596 // ins_cost(500);
11597 // opcode(0x39); /* Opcode 39 /r */
11598 // ins_encode( OpcP, RegMem( op1, op2) );
11599 //%}
11600
11601 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11602 match(Set cr (CmpU src zero));
11603
11604 format %{ "TESTu $src,$src" %}
11605 opcode(0x85);
11606 ins_encode( OpcP, RegReg( src, src ) );
11607 ins_pipe( ialu_cr_reg_imm );
11608 %}
11609
11610 // Unsigned pointer compare Instructions
11611 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11612 match(Set cr (CmpP op1 op2));
11613
11614 format %{ "CMPu $op1,$op2" %}
11615 opcode(0x3B); /* Opcode 3B /r */
11616 ins_encode( OpcP, RegReg( op1, op2) );
11617 ins_pipe( ialu_cr_reg_reg );
11618 %}
11619
11620 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11621 match(Set cr (CmpP op1 op2));
11622
11623 format %{ "CMPu $op1,$op2" %}
11624 opcode(0x81,0x07); /* Opcode 81 /7 */
11625 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11626 ins_pipe( ialu_cr_reg_imm );
11627 %}
11628
11629 // // Cisc-spilled version of cmpP_eReg
11630 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11631 match(Set cr (CmpP op1 (LoadP op2)));
11632
11633 format %{ "CMPu $op1,$op2" %}
11634 ins_cost(500);
11635 opcode(0x3B); /* Opcode 3B /r */
11636 ins_encode( OpcP, RegMem( op1, op2) );
11637 ins_pipe( ialu_cr_reg_mem );
11638 %}
11639
11640 // // Cisc-spilled version of cmpP_eReg
11641 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11642 // match(Set cr (CmpP (LoadP op1) op2));
11643 //
11644 // format %{ "CMPu $op1,$op2" %}
11645 // ins_cost(500);
11646 // opcode(0x39); /* Opcode 39 /r */
11647 // ins_encode( OpcP, RegMem( op1, op2) );
11648 //%}
11649
11650 // Compare raw pointer (used in out-of-heap check).
11651 // Only works because non-oop pointers must be raw pointers
11652 // and raw pointers have no anti-dependencies.
11653 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11654 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11655 match(Set cr (CmpP op1 (LoadP op2)));
11656
11657 format %{ "CMPu $op1,$op2" %}
11658 opcode(0x3B); /* Opcode 3B /r */
11659 ins_encode( OpcP, RegMem( op1, op2) );
11660 ins_pipe( ialu_cr_reg_mem );
11661 %}
11662
11663 //
11664 // This will generate a signed flags result. This should be ok
11665 // since any compare to a zero should be eq/neq.
11666 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11667 match(Set cr (CmpP src zero));
11668
11669 format %{ "TEST $src,$src" %}
11670 opcode(0x85);
11671 ins_encode( OpcP, RegReg( src, src ) );
11672 ins_pipe( ialu_cr_reg_imm );
11673 %}
11674
11675 // Cisc-spilled version of testP_reg
11676 // This will generate a signed flags result. This should be ok
11677 // since any compare to a zero should be eq/neq.
11678 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11679 match(Set cr (CmpP (LoadP op) zero));
11680
11681 format %{ "TEST $op,0xFFFFFFFF" %}
11682 ins_cost(500);
11683 opcode(0xF7); /* Opcode F7 /0 */
11684 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11685 ins_pipe( ialu_cr_reg_imm );
11686 %}
11687
11688 // Yanked all unsigned pointer compare operations.
11689 // Pointer compares are done with CmpP which is already unsigned.
11690
11691 //----------Max and Min--------------------------------------------------------
11692 // Min Instructions
11693 ////
11694 // *** Min and Max using the conditional move are slower than the
11695 // *** branch version on a Pentium III.
11696 // // Conditional move for min
11697 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11698 // effect( USE_DEF op2, USE op1, USE cr );
11699 // format %{ "CMOVlt $op2,$op1\t! min" %}
11700 // opcode(0x4C,0x0F);
11701 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11702 // ins_pipe( pipe_cmov_reg );
11703 //%}
11704 //
11705 //// Min Register with Register (P6 version)
11706 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11707 // predicate(VM_Version::supports_cmov() );
11708 // match(Set op2 (MinI op1 op2));
11709 // ins_cost(200);
11710 // expand %{
11711 // eFlagsReg cr;
11712 // compI_eReg(cr,op1,op2);
11713 // cmovI_reg_lt(op2,op1,cr);
11714 // %}
11715 //%}
11716
11717 // Min Register with Register (generic version)
11718 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11719 match(Set dst (MinI dst src));
11720 effect(KILL flags);
11721 ins_cost(300);
11722
11723 format %{ "MIN $dst,$src" %}
11724 opcode(0xCC);
11725 ins_encode( min_enc(dst,src) );
11726 ins_pipe( pipe_slow );
11727 %}
11728
11729 // Max Register with Register
11730 // *** Min and Max using the conditional move are slower than the
11731 // *** branch version on a Pentium III.
11732 // // Conditional move for max
11733 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11734 // effect( USE_DEF op2, USE op1, USE cr );
11735 // format %{ "CMOVgt $op2,$op1\t! max" %}
11736 // opcode(0x4F,0x0F);
11737 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11738 // ins_pipe( pipe_cmov_reg );
11739 //%}
11740 //
11741 // // Max Register with Register (P6 version)
11742 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11743 // predicate(VM_Version::supports_cmov() );
11744 // match(Set op2 (MaxI op1 op2));
11745 // ins_cost(200);
11746 // expand %{
11747 // eFlagsReg cr;
11748 // compI_eReg(cr,op1,op2);
11749 // cmovI_reg_gt(op2,op1,cr);
11750 // %}
11751 //%}
11752
11753 // Max Register with Register (generic version)
11754 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11755 match(Set dst (MaxI dst src));
11756 effect(KILL flags);
11757 ins_cost(300);
11758
11759 format %{ "MAX $dst,$src" %}
11760 opcode(0xCC);
11761 ins_encode( max_enc(dst,src) );
11762 ins_pipe( pipe_slow );
11763 %}
11764
11765 // ============================================================================
11766 // Counted Loop limit node which represents exact final iterator value.
11767 // Note: the resulting value should fit into integer range since
11768 // counted loops have limit check on overflow.
11769 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11770 match(Set limit (LoopLimit (Binary init limit) stride));
11771 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11772 ins_cost(300);
11773
11774 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11775 ins_encode %{
11776 int strd = (int)$stride$$constant;
11777 assert(strd != 1 && strd != -1, "sanity");
11778 int m1 = (strd > 0) ? 1 : -1;
11779 // Convert limit to long (EAX:EDX)
11780 __ cdql();
11781 // Convert init to long (init:tmp)
11782 __ movl($tmp$$Register, $init$$Register);
11783 __ sarl($tmp$$Register, 31);
11784 // $limit - $init
11785 __ subl($limit$$Register, $init$$Register);
11786 __ sbbl($limit_hi$$Register, $tmp$$Register);
11787 // + ($stride - 1)
11788 if (strd > 0) {
11789 __ addl($limit$$Register, (strd - 1));
11790 __ adcl($limit_hi$$Register, 0);
11791 __ movl($tmp$$Register, strd);
11792 } else {
11793 __ addl($limit$$Register, (strd + 1));
11794 __ adcl($limit_hi$$Register, -1);
11795 __ lneg($limit_hi$$Register, $limit$$Register);
11796 __ movl($tmp$$Register, -strd);
11797 }
11798 // signed devision: (EAX:EDX) / pos_stride
11799 __ idivl($tmp$$Register);
11800 if (strd < 0) {
11801 // restore sign
11802 __ negl($tmp$$Register);
11803 }
11804 // (EAX) * stride
11805 __ mull($tmp$$Register);
11806 // + init (ignore upper bits)
11807 __ addl($limit$$Register, $init$$Register);
11808 %}
11809 ins_pipe( pipe_slow );
11810 %}
11811
11812 // ============================================================================
11813 // Branch Instructions
11814 // Jump Table
11815 instruct jumpXtnd(rRegI switch_val) %{
11816 match(Jump switch_val);
11817 ins_cost(350);
11818 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
11819 ins_encode %{
11820 // Jump to Address(table_base + switch_reg)
11821 Address index(noreg, $switch_val$$Register, Address::times_1);
11822 __ jump(ArrayAddress($constantaddress, index));
11823 %}
11824 ins_pipe(pipe_jmp);
11825 %}
11826
11827 // Jump Direct - Label defines a relative address from JMP+1
11828 instruct jmpDir(label labl) %{
11829 match(Goto);
11830 effect(USE labl);
11831
11832 ins_cost(300);
11833 format %{ "JMP $labl" %}
11834 size(5);
11835 ins_encode %{
11836 Label* L = $labl$$label;
11837 __ jmp(*L, false); // Always long jump
11838 %}
11839 ins_pipe( pipe_jmp );
11840 %}
11841
11842 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11843 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
11844 match(If cop cr);
11845 effect(USE labl);
11846
11847 ins_cost(300);
11848 format %{ "J$cop $labl" %}
11849 size(6);
11850 ins_encode %{
11851 Label* L = $labl$$label;
11852 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11853 %}
11854 ins_pipe( pipe_jcc );
11855 %}
11856
11857 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11858 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
11859 match(CountedLoopEnd cop cr);
11860 effect(USE labl);
11861
11862 ins_cost(300);
11863 format %{ "J$cop $labl\t# Loop end" %}
11864 size(6);
11865 ins_encode %{
11866 Label* L = $labl$$label;
11867 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11868 %}
11869 ins_pipe( pipe_jcc );
11870 %}
11871
11872 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11873 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11874 match(CountedLoopEnd cop cmp);
11875 effect(USE labl);
11876
11877 ins_cost(300);
11878 format %{ "J$cop,u $labl\t# Loop end" %}
11879 size(6);
11880 ins_encode %{
11881 Label* L = $labl$$label;
11882 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11883 %}
11884 ins_pipe( pipe_jcc );
11885 %}
11886
11887 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
11888 match(CountedLoopEnd cop cmp);
11889 effect(USE labl);
11890
11891 ins_cost(200);
11892 format %{ "J$cop,u $labl\t# Loop end" %}
11893 size(6);
11894 ins_encode %{
11895 Label* L = $labl$$label;
11896 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11897 %}
11898 ins_pipe( pipe_jcc );
11899 %}
11900
11901 // Jump Direct Conditional - using unsigned comparison
11902 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11903 match(If cop cmp);
11904 effect(USE labl);
11905
11906 ins_cost(300);
11907 format %{ "J$cop,u $labl" %}
11908 size(6);
11909 ins_encode %{
11910 Label* L = $labl$$label;
11911 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11912 %}
11913 ins_pipe(pipe_jcc);
11914 %}
11915
11916 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
11917 match(If cop cmp);
11918 effect(USE labl);
11919
11920 ins_cost(200);
11921 format %{ "J$cop,u $labl" %}
11922 size(6);
11923 ins_encode %{
11924 Label* L = $labl$$label;
11925 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11926 %}
11927 ins_pipe(pipe_jcc);
11928 %}
11929
11930 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
11931 match(If cop cmp);
11932 effect(USE labl);
11933
11934 ins_cost(200);
11935 format %{ $$template
11936 if ($cop$$cmpcode == Assembler::notEqual) {
11937 $$emit$$"JP,u $labl\n\t"
11938 $$emit$$"J$cop,u $labl"
11939 } else {
11940 $$emit$$"JP,u done\n\t"
11941 $$emit$$"J$cop,u $labl\n\t"
11942 $$emit$$"done:"
11943 }
11944 %}
11945 ins_encode %{
11946 Label* l = $labl$$label;
11947 if ($cop$$cmpcode == Assembler::notEqual) {
11948 __ jcc(Assembler::parity, *l, false);
11949 __ jcc(Assembler::notEqual, *l, false);
11950 } else if ($cop$$cmpcode == Assembler::equal) {
11951 Label done;
11952 __ jccb(Assembler::parity, done);
11953 __ jcc(Assembler::equal, *l, false);
11954 __ bind(done);
11955 } else {
11956 ShouldNotReachHere();
11957 }
11958 %}
11959 ins_pipe(pipe_jcc);
11960 %}
11961
11962 // ============================================================================
11963 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
11964 // array for an instance of the superklass. Set a hidden internal cache on a
11965 // hit (cache is checked with exposed code in gen_subtype_check()). Return
11966 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
11967 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
11968 match(Set result (PartialSubtypeCheck sub super));
11969 effect( KILL rcx, KILL cr );
11970
11971 ins_cost(1100); // slightly larger than the next version
11972 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
11973 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
11974 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
11975 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
11976 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
11977 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
11978 "XOR $result,$result\t\t Hit: EDI zero\n\t"
11979 "miss:\t" %}
11980
11981 opcode(0x1); // Force a XOR of EDI
11982 ins_encode( enc_PartialSubtypeCheck() );
11983 ins_pipe( pipe_slow );
11984 %}
11985
11986 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
11987 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11988 effect( KILL rcx, KILL result );
11989
11990 ins_cost(1000);
11991 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
11992 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
11993 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
11994 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
11995 "JNE,s miss\t\t# Missed: flags NZ\n\t"
11996 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
11997 "miss:\t" %}
11998
11999 opcode(0x0); // No need to XOR EDI
12000 ins_encode( enc_PartialSubtypeCheck() );
12001 ins_pipe( pipe_slow );
12002 %}
12003
12004 // ============================================================================
12005 // Branch Instructions -- short offset versions
12006 //
12007 // These instructions are used to replace jumps of a long offset (the default
12008 // match) with jumps of a shorter offset. These instructions are all tagged
12009 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12010 // match rules in general matching. Instead, the ADLC generates a conversion
12011 // method in the MachNode which can be used to do in-place replacement of the
12012 // long variant with the shorter variant. The compiler will determine if a
12013 // branch can be taken by the is_short_branch_offset() predicate in the machine
12014 // specific code section of the file.
12015
12016 // Jump Direct - Label defines a relative address from JMP+1
12017 instruct jmpDir_short(label labl) %{
12018 match(Goto);
12019 effect(USE labl);
12020
12021 ins_cost(300);
12022 format %{ "JMP,s $labl" %}
12023 size(2);
12024 ins_encode %{
12025 Label* L = $labl$$label;
12026 __ jmpb(*L);
12027 %}
12028 ins_pipe( pipe_jmp );
12029 ins_short_branch(1);
12030 %}
12031
12032 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12033 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12034 match(If cop cr);
12035 effect(USE labl);
12036
12037 ins_cost(300);
12038 format %{ "J$cop,s $labl" %}
12039 size(2);
12040 ins_encode %{
12041 Label* L = $labl$$label;
12042 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12043 %}
12044 ins_pipe( pipe_jcc );
12045 ins_short_branch(1);
12046 %}
12047
12048 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12049 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12050 match(CountedLoopEnd cop cr);
12051 effect(USE labl);
12052
12053 ins_cost(300);
12054 format %{ "J$cop,s $labl\t# Loop end" %}
12055 size(2);
12056 ins_encode %{
12057 Label* L = $labl$$label;
12058 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12059 %}
12060 ins_pipe( pipe_jcc );
12061 ins_short_branch(1);
12062 %}
12063
12064 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12065 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12066 match(CountedLoopEnd cop cmp);
12067 effect(USE labl);
12068
12069 ins_cost(300);
12070 format %{ "J$cop,us $labl\t# Loop end" %}
12071 size(2);
12072 ins_encode %{
12073 Label* L = $labl$$label;
12074 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12075 %}
12076 ins_pipe( pipe_jcc );
12077 ins_short_branch(1);
12078 %}
12079
12080 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12081 match(CountedLoopEnd cop cmp);
12082 effect(USE labl);
12083
12084 ins_cost(300);
12085 format %{ "J$cop,us $labl\t# Loop end" %}
12086 size(2);
12087 ins_encode %{
12088 Label* L = $labl$$label;
12089 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12090 %}
12091 ins_pipe( pipe_jcc );
12092 ins_short_branch(1);
12093 %}
12094
12095 // Jump Direct Conditional - using unsigned comparison
12096 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12097 match(If cop cmp);
12098 effect(USE labl);
12099
12100 ins_cost(300);
12101 format %{ "J$cop,us $labl" %}
12102 size(2);
12103 ins_encode %{
12104 Label* L = $labl$$label;
12105 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12106 %}
12107 ins_pipe( pipe_jcc );
12108 ins_short_branch(1);
12109 %}
12110
12111 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12112 match(If cop cmp);
12113 effect(USE labl);
12114
12115 ins_cost(300);
12116 format %{ "J$cop,us $labl" %}
12117 size(2);
12118 ins_encode %{
12119 Label* L = $labl$$label;
12120 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12121 %}
12122 ins_pipe( pipe_jcc );
12123 ins_short_branch(1);
12124 %}
12125
12126 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12127 match(If cop cmp);
12128 effect(USE labl);
12129
12130 ins_cost(300);
12131 format %{ $$template
12132 if ($cop$$cmpcode == Assembler::notEqual) {
12133 $$emit$$"JP,u,s $labl\n\t"
12134 $$emit$$"J$cop,u,s $labl"
12135 } else {
12136 $$emit$$"JP,u,s done\n\t"
12137 $$emit$$"J$cop,u,s $labl\n\t"
12138 $$emit$$"done:"
12139 }
12140 %}
12141 size(4);
12142 ins_encode %{
12143 Label* l = $labl$$label;
12144 if ($cop$$cmpcode == Assembler::notEqual) {
12145 __ jccb(Assembler::parity, *l);
12146 __ jccb(Assembler::notEqual, *l);
12147 } else if ($cop$$cmpcode == Assembler::equal) {
12148 Label done;
12149 __ jccb(Assembler::parity, done);
12150 __ jccb(Assembler::equal, *l);
12151 __ bind(done);
12152 } else {
12153 ShouldNotReachHere();
12154 }
12155 %}
12156 ins_pipe(pipe_jcc);
12157 ins_short_branch(1);
12158 %}
12159
12160 // ============================================================================
12161 // Long Compare
12162 //
12163 // Currently we hold longs in 2 registers. Comparing such values efficiently
12164 // is tricky. The flavor of compare used depends on whether we are testing
12165 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12166 // The GE test is the negated LT test. The LE test can be had by commuting
12167 // the operands (yielding a GE test) and then negating; negate again for the
12168 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12169 // NE test is negated from that.
12170
12171 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12172 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12173 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12174 // are collapsed internally in the ADLC's dfa-gen code. The match for
12175 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12176 // foo match ends up with the wrong leaf. One fix is to not match both
12177 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12178 // both forms beat the trinary form of long-compare and both are very useful
12179 // on Intel which has so few registers.
12180
12181 // Manifest a CmpL result in an integer register. Very painful.
12182 // This is the test to avoid.
12183 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12184 match(Set dst (CmpL3 src1 src2));
12185 effect( KILL flags );
12186 ins_cost(1000);
12187 format %{ "XOR $dst,$dst\n\t"
12188 "CMP $src1.hi,$src2.hi\n\t"
12189 "JLT,s m_one\n\t"
12190 "JGT,s p_one\n\t"
12191 "CMP $src1.lo,$src2.lo\n\t"
12192 "JB,s m_one\n\t"
12193 "JEQ,s done\n"
12194 "p_one:\tINC $dst\n\t"
12195 "JMP,s done\n"
12196 "m_one:\tDEC $dst\n"
12197 "done:" %}
12198 ins_encode %{
12199 Label p_one, m_one, done;
12200 __ xorptr($dst$$Register, $dst$$Register);
12201 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12202 __ jccb(Assembler::less, m_one);
12203 __ jccb(Assembler::greater, p_one);
12204 __ cmpl($src1$$Register, $src2$$Register);
12205 __ jccb(Assembler::below, m_one);
12206 __ jccb(Assembler::equal, done);
12207 __ bind(p_one);
12208 __ incrementl($dst$$Register);
12209 __ jmpb(done);
12210 __ bind(m_one);
12211 __ decrementl($dst$$Register);
12212 __ bind(done);
12213 %}
12214 ins_pipe( pipe_slow );
12215 %}
12216
12217 //======
12218 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12219 // compares. Can be used for LE or GT compares by reversing arguments.
12220 // NOT GOOD FOR EQ/NE tests.
12221 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12222 match( Set flags (CmpL src zero ));
12223 ins_cost(100);
12224 format %{ "TEST $src.hi,$src.hi" %}
12225 opcode(0x85);
12226 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12227 ins_pipe( ialu_cr_reg_reg );
12228 %}
12229
12230 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12231 // compares. Can be used for LE or GT compares by reversing arguments.
12232 // NOT GOOD FOR EQ/NE tests.
12233 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12234 match( Set flags (CmpL src1 src2 ));
12235 effect( TEMP tmp );
12236 ins_cost(300);
12237 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12238 "MOV $tmp,$src1.hi\n\t"
12239 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12240 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12241 ins_pipe( ialu_cr_reg_reg );
12242 %}
12243
12244 // Long compares reg < zero/req OR reg >= zero/req.
12245 // Just a wrapper for a normal branch, plus the predicate test.
12246 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12247 match(If cmp flags);
12248 effect(USE labl);
12249 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12250 expand %{
12251 jmpCon(cmp,flags,labl); // JLT or JGE...
12252 %}
12253 %}
12254
12255 // Compare 2 longs and CMOVE longs.
12256 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12257 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12258 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12259 ins_cost(400);
12260 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12261 "CMOV$cmp $dst.hi,$src.hi" %}
12262 opcode(0x0F,0x40);
12263 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12264 ins_pipe( pipe_cmov_reg_long );
12265 %}
12266
12267 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12268 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12269 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12270 ins_cost(500);
12271 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12272 "CMOV$cmp $dst.hi,$src.hi" %}
12273 opcode(0x0F,0x40);
12274 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12275 ins_pipe( pipe_cmov_reg_long );
12276 %}
12277
12278 // Compare 2 longs and CMOVE ints.
12279 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12280 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12281 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12282 ins_cost(200);
12283 format %{ "CMOV$cmp $dst,$src" %}
12284 opcode(0x0F,0x40);
12285 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12286 ins_pipe( pipe_cmov_reg );
12287 %}
12288
12289 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12290 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12291 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12292 ins_cost(250);
12293 format %{ "CMOV$cmp $dst,$src" %}
12294 opcode(0x0F,0x40);
12295 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12296 ins_pipe( pipe_cmov_mem );
12297 %}
12298
12299 // Compare 2 longs and CMOVE ints.
12300 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12301 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12302 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12303 ins_cost(200);
12304 format %{ "CMOV$cmp $dst,$src" %}
12305 opcode(0x0F,0x40);
12306 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12307 ins_pipe( pipe_cmov_reg );
12308 %}
12309
12310 // Compare 2 longs and CMOVE doubles
12311 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12312 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12313 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12314 ins_cost(200);
12315 expand %{
12316 fcmovDPR_regS(cmp,flags,dst,src);
12317 %}
12318 %}
12319
12320 // Compare 2 longs and CMOVE doubles
12321 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12322 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12323 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12324 ins_cost(200);
12325 expand %{
12326 fcmovD_regS(cmp,flags,dst,src);
12327 %}
12328 %}
12329
12330 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12331 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12332 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12333 ins_cost(200);
12334 expand %{
12335 fcmovFPR_regS(cmp,flags,dst,src);
12336 %}
12337 %}
12338
12339 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12340 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12341 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12342 ins_cost(200);
12343 expand %{
12344 fcmovF_regS(cmp,flags,dst,src);
12345 %}
12346 %}
12347
12348 //======
12349 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12350 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12351 match( Set flags (CmpL src zero ));
12352 effect(TEMP tmp);
12353 ins_cost(200);
12354 format %{ "MOV $tmp,$src.lo\n\t"
12355 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12356 ins_encode( long_cmp_flags0( src, tmp ) );
12357 ins_pipe( ialu_reg_reg_long );
12358 %}
12359
12360 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12361 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12362 match( Set flags (CmpL src1 src2 ));
12363 ins_cost(200+300);
12364 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12365 "JNE,s skip\n\t"
12366 "CMP $src1.hi,$src2.hi\n\t"
12367 "skip:\t" %}
12368 ins_encode( long_cmp_flags1( src1, src2 ) );
12369 ins_pipe( ialu_cr_reg_reg );
12370 %}
12371
12372 // Long compare reg == zero/reg OR reg != zero/reg
12373 // Just a wrapper for a normal branch, plus the predicate test.
12374 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12375 match(If cmp flags);
12376 effect(USE labl);
12377 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12378 expand %{
12379 jmpCon(cmp,flags,labl); // JEQ or JNE...
12380 %}
12381 %}
12382
12383 // Compare 2 longs and CMOVE longs.
12384 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12385 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12386 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12387 ins_cost(400);
12388 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12389 "CMOV$cmp $dst.hi,$src.hi" %}
12390 opcode(0x0F,0x40);
12391 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12392 ins_pipe( pipe_cmov_reg_long );
12393 %}
12394
12395 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12396 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12397 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12398 ins_cost(500);
12399 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12400 "CMOV$cmp $dst.hi,$src.hi" %}
12401 opcode(0x0F,0x40);
12402 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12403 ins_pipe( pipe_cmov_reg_long );
12404 %}
12405
12406 // Compare 2 longs and CMOVE ints.
12407 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12408 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12409 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12410 ins_cost(200);
12411 format %{ "CMOV$cmp $dst,$src" %}
12412 opcode(0x0F,0x40);
12413 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12414 ins_pipe( pipe_cmov_reg );
12415 %}
12416
12417 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12418 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12419 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12420 ins_cost(250);
12421 format %{ "CMOV$cmp $dst,$src" %}
12422 opcode(0x0F,0x40);
12423 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12424 ins_pipe( pipe_cmov_mem );
12425 %}
12426
12427 // Compare 2 longs and CMOVE ints.
12428 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12429 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12430 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12431 ins_cost(200);
12432 format %{ "CMOV$cmp $dst,$src" %}
12433 opcode(0x0F,0x40);
12434 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12435 ins_pipe( pipe_cmov_reg );
12436 %}
12437
12438 // Compare 2 longs and CMOVE doubles
12439 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12440 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12441 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12442 ins_cost(200);
12443 expand %{
12444 fcmovDPR_regS(cmp,flags,dst,src);
12445 %}
12446 %}
12447
12448 // Compare 2 longs and CMOVE doubles
12449 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12450 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12451 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12452 ins_cost(200);
12453 expand %{
12454 fcmovD_regS(cmp,flags,dst,src);
12455 %}
12456 %}
12457
12458 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12459 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12460 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12461 ins_cost(200);
12462 expand %{
12463 fcmovFPR_regS(cmp,flags,dst,src);
12464 %}
12465 %}
12466
12467 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12468 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12469 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12470 ins_cost(200);
12471 expand %{
12472 fcmovF_regS(cmp,flags,dst,src);
12473 %}
12474 %}
12475
12476 //======
12477 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12478 // Same as cmpL_reg_flags_LEGT except must negate src
12479 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12480 match( Set flags (CmpL src zero ));
12481 effect( TEMP tmp );
12482 ins_cost(300);
12483 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12484 "CMP $tmp,$src.lo\n\t"
12485 "SBB $tmp,$src.hi\n\t" %}
12486 ins_encode( long_cmp_flags3(src, tmp) );
12487 ins_pipe( ialu_reg_reg_long );
12488 %}
12489
12490 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12491 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12492 // requires a commuted test to get the same result.
12493 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12494 match( Set flags (CmpL src1 src2 ));
12495 effect( TEMP tmp );
12496 ins_cost(300);
12497 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12498 "MOV $tmp,$src2.hi\n\t"
12499 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12500 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12501 ins_pipe( ialu_cr_reg_reg );
12502 %}
12503
12504 // Long compares reg < zero/req OR reg >= zero/req.
12505 // Just a wrapper for a normal branch, plus the predicate test
12506 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12507 match(If cmp flags);
12508 effect(USE labl);
12509 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12510 ins_cost(300);
12511 expand %{
12512 jmpCon(cmp,flags,labl); // JGT or JLE...
12513 %}
12514 %}
12515
12516 // Compare 2 longs and CMOVE longs.
12517 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12518 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12519 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12520 ins_cost(400);
12521 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12522 "CMOV$cmp $dst.hi,$src.hi" %}
12523 opcode(0x0F,0x40);
12524 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12525 ins_pipe( pipe_cmov_reg_long );
12526 %}
12527
12528 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12529 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12530 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12531 ins_cost(500);
12532 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12533 "CMOV$cmp $dst.hi,$src.hi+4" %}
12534 opcode(0x0F,0x40);
12535 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12536 ins_pipe( pipe_cmov_reg_long );
12537 %}
12538
12539 // Compare 2 longs and CMOVE ints.
12540 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12541 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12542 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12543 ins_cost(200);
12544 format %{ "CMOV$cmp $dst,$src" %}
12545 opcode(0x0F,0x40);
12546 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12547 ins_pipe( pipe_cmov_reg );
12548 %}
12549
12550 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12551 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12552 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12553 ins_cost(250);
12554 format %{ "CMOV$cmp $dst,$src" %}
12555 opcode(0x0F,0x40);
12556 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12557 ins_pipe( pipe_cmov_mem );
12558 %}
12559
12560 // Compare 2 longs and CMOVE ptrs.
12561 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12562 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12563 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12564 ins_cost(200);
12565 format %{ "CMOV$cmp $dst,$src" %}
12566 opcode(0x0F,0x40);
12567 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12568 ins_pipe( pipe_cmov_reg );
12569 %}
12570
12571 // Compare 2 longs and CMOVE doubles
12572 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12573 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12574 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12575 ins_cost(200);
12576 expand %{
12577 fcmovDPR_regS(cmp,flags,dst,src);
12578 %}
12579 %}
12580
12581 // Compare 2 longs and CMOVE doubles
12582 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12583 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12584 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12585 ins_cost(200);
12586 expand %{
12587 fcmovD_regS(cmp,flags,dst,src);
12588 %}
12589 %}
12590
12591 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12592 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12593 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12594 ins_cost(200);
12595 expand %{
12596 fcmovFPR_regS(cmp,flags,dst,src);
12597 %}
12598 %}
12599
12600
12601 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12602 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12603 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12604 ins_cost(200);
12605 expand %{
12606 fcmovF_regS(cmp,flags,dst,src);
12607 %}
12608 %}
12609
12610
12611 // ============================================================================
12612 // Procedure Call/Return Instructions
12613 // Call Java Static Instruction
12614 // Note: If this code changes, the corresponding ret_addr_offset() and
12615 // compute_padding() functions will have to be adjusted.
12616 instruct CallStaticJavaDirect(method meth) %{
12617 match(CallStaticJava);
12618 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12619 effect(USE meth);
12620
12621 ins_cost(300);
12622 format %{ "CALL,static " %}
12623 opcode(0xE8); /* E8 cd */
12624 ins_encode( pre_call_resets,
12625 Java_Static_Call( meth ),
12626 call_epilog,
12627 post_call_FPU );
12628 ins_pipe( pipe_slow );
12629 ins_alignment(4);
12630 %}
12631
12632 // Call Java Static Instruction (method handle version)
12633 // Note: If this code changes, the corresponding ret_addr_offset() and
12634 // compute_padding() functions will have to be adjusted.
12635 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12636 match(CallStaticJava);
12637 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12638 effect(USE meth);
12639 // EBP is saved by all callees (for interpreter stack correction).
12640 // We use it here for a similar purpose, in {preserve,restore}_SP.
12641
12642 ins_cost(300);
12643 format %{ "CALL,static/MethodHandle " %}
12644 opcode(0xE8); /* E8 cd */
12645 ins_encode( pre_call_resets,
12646 preserve_SP,
12647 Java_Static_Call( meth ),
12648 restore_SP,
12649 call_epilog,
12650 post_call_FPU );
12651 ins_pipe( pipe_slow );
12652 ins_alignment(4);
12653 %}
12654
12655 // Call Java Dynamic Instruction
12656 // Note: If this code changes, the corresponding ret_addr_offset() and
12657 // compute_padding() functions will have to be adjusted.
12658 instruct CallDynamicJavaDirect(method meth) %{
12659 match(CallDynamicJava);
12660 effect(USE meth);
12661
12662 ins_cost(300);
12663 format %{ "MOV EAX,(oop)-1\n\t"
12664 "CALL,dynamic" %}
12665 opcode(0xE8); /* E8 cd */
12666 ins_encode( pre_call_resets,
12667 Java_Dynamic_Call( meth ),
12668 call_epilog,
12669 post_call_FPU );
12670 ins_pipe( pipe_slow );
12671 ins_alignment(4);
12672 %}
12673
12674 // Call Runtime Instruction
12675 instruct CallRuntimeDirect(method meth) %{
12676 match(CallRuntime );
12677 effect(USE meth);
12678
12679 ins_cost(300);
12680 format %{ "CALL,runtime " %}
12681 opcode(0xE8); /* E8 cd */
12682 // Use FFREEs to clear entries in float stack
12683 ins_encode( pre_call_resets,
12684 FFree_Float_Stack_All,
12685 Java_To_Runtime( meth ),
12686 post_call_FPU );
12687 ins_pipe( pipe_slow );
12688 %}
12689
12690 // Call runtime without safepoint
12691 instruct CallLeafDirect(method meth) %{
12692 match(CallLeaf);
12693 effect(USE meth);
12694
12695 ins_cost(300);
12696 format %{ "CALL_LEAF,runtime " %}
12697 opcode(0xE8); /* E8 cd */
12698 ins_encode( pre_call_resets,
12699 FFree_Float_Stack_All,
12700 Java_To_Runtime( meth ),
12701 Verify_FPU_For_Leaf, post_call_FPU );
12702 ins_pipe( pipe_slow );
12703 %}
12704
12705 instruct CallLeafNoFPDirect(method meth) %{
12706 match(CallLeafNoFP);
12707 effect(USE meth);
12708
12709 ins_cost(300);
12710 format %{ "CALL_LEAF_NOFP,runtime " %}
12711 opcode(0xE8); /* E8 cd */
12712 ins_encode(Java_To_Runtime(meth));
12713 ins_pipe( pipe_slow );
12714 %}
12715
12716
12717 // Return Instruction
12718 // Remove the return address & jump to it.
12719 instruct Ret() %{
12720 match(Return);
12721 format %{ "RET" %}
12722 opcode(0xC3);
12723 ins_encode(OpcP);
12724 ins_pipe( pipe_jmp );
12725 %}
12726
12727 // Tail Call; Jump from runtime stub to Java code.
12728 // Also known as an 'interprocedural jump'.
12729 // Target of jump will eventually return to caller.
12730 // TailJump below removes the return address.
12731 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12732 match(TailCall jump_target method_oop );
12733 ins_cost(300);
12734 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12735 opcode(0xFF, 0x4); /* Opcode FF /4 */
12736 ins_encode( OpcP, RegOpc(jump_target) );
12737 ins_pipe( pipe_jmp );
12738 %}
12739
12740
12741 // Tail Jump; remove the return address; jump to target.
12742 // TailCall above leaves the return address around.
12743 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12744 match( TailJump jump_target ex_oop );
12745 ins_cost(300);
12746 format %{ "POP EDX\t# pop return address into dummy\n\t"
12747 "JMP $jump_target " %}
12748 opcode(0xFF, 0x4); /* Opcode FF /4 */
12749 ins_encode( enc_pop_rdx,
12750 OpcP, RegOpc(jump_target) );
12751 ins_pipe( pipe_jmp );
12752 %}
12753
12754 // Create exception oop: created by stack-crawling runtime code.
12755 // Created exception is now available to this handler, and is setup
12756 // just prior to jumping to this handler. No code emitted.
12757 instruct CreateException( eAXRegP ex_oop )
12758 %{
12759 match(Set ex_oop (CreateEx));
12760
12761 size(0);
12762 // use the following format syntax
12763 format %{ "# exception oop is in EAX; no code emitted" %}
12764 ins_encode();
12765 ins_pipe( empty );
12766 %}
12767
12768
12769 // Rethrow exception:
12770 // The exception oop will come in the first argument position.
12771 // Then JUMP (not call) to the rethrow stub code.
12772 instruct RethrowException()
12773 %{
12774 match(Rethrow);
12775
12776 // use the following format syntax
12777 format %{ "JMP rethrow_stub" %}
12778 ins_encode(enc_rethrow);
12779 ins_pipe( pipe_jmp );
12780 %}
12781
12782 // inlined locking and unlocking
12783
12784 instruct cmpFastLockRTM(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eDXRegI scr, rRegI cx1, rRegI cx2) %{
12785 predicate(Compile::current()->use_rtm());
12786 match(Set cr (FastLock object box));
12787 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12788 ins_cost(300);
12789 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12790 ins_encode %{
12791 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12792 $scr$$Register, $cx1$$Register, $cx2$$Register,
12793 _counters, _rtm_counters, _stack_rtm_counters,
12794 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12795 true, ra_->C->profile_rtm());
12796 %}
12797 ins_pipe(pipe_slow);
12798 %}
12799
12800 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12801 predicate(!Compile::current()->use_rtm());
12802 match(Set cr (FastLock object box));
12803 effect(TEMP tmp, TEMP scr, USE_KILL box);
12804 ins_cost(300);
12805 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12806 ins_encode %{
12807 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12808 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12809 %}
12810 ins_pipe(pipe_slow);
12811 %}
12812
12813 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12814 match(Set cr (FastUnlock object box));
12815 effect(TEMP tmp, USE_KILL box);
12816 ins_cost(300);
12817 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12818 ins_encode %{
12819 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12820 %}
12821 ins_pipe(pipe_slow);
12822 %}
12823
12824
12825
12826 // ============================================================================
12827 // Safepoint Instruction
12828 instruct safePoint_poll(eFlagsReg cr) %{
12829 match(SafePoint);
12830 effect(KILL cr);
12831
12832 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12833 // On SPARC that might be acceptable as we can generate the address with
12834 // just a sethi, saving an or. By polling at offset 0 we can end up
12835 // putting additional pressure on the index-0 in the D$. Because of
12836 // alignment (just like the situation at hand) the lower indices tend
12837 // to see more traffic. It'd be better to change the polling address
12838 // to offset 0 of the last $line in the polling page.
12839
12840 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12841 ins_cost(125);
12842 size(6) ;
12843 ins_encode( Safepoint_Poll() );
12844 ins_pipe( ialu_reg_mem );
12845 %}
12846
12847
12848 // ============================================================================
12849 // This name is KNOWN by the ADLC and cannot be changed.
12850 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12851 // for this guy.
12852 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
12853 match(Set dst (ThreadLocal));
12854 effect(DEF dst, KILL cr);
12855
12856 format %{ "MOV $dst, Thread::current()" %}
12857 ins_encode %{
12858 Register dstReg = as_Register($dst$$reg);
12859 __ get_thread(dstReg);
12860 %}
12861 ins_pipe( ialu_reg_fat );
12862 %}
12863
12864
12865
12866 //----------PEEPHOLE RULES-----------------------------------------------------
12867 // These must follow all instruction definitions as they use the names
12868 // defined in the instructions definitions.
12869 //
12870 // peepmatch ( root_instr_name [preceding_instruction]* );
12871 //
12872 // peepconstraint %{
12873 // (instruction_number.operand_name relational_op instruction_number.operand_name
12874 // [, ...] );
12875 // // instruction numbers are zero-based using left to right order in peepmatch
12876 //
12877 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12878 // // provide an instruction_number.operand_name for each operand that appears
12879 // // in the replacement instruction's match rule
12880 //
12881 // ---------VM FLAGS---------------------------------------------------------
12882 //
12883 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12884 //
12885 // Each peephole rule is given an identifying number starting with zero and
12886 // increasing by one in the order seen by the parser. An individual peephole
12887 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12888 // on the command-line.
12889 //
12890 // ---------CURRENT LIMITATIONS----------------------------------------------
12891 //
12892 // Only match adjacent instructions in same basic block
12893 // Only equality constraints
12894 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12895 // Only one replacement instruction
12896 //
12897 // ---------EXAMPLE----------------------------------------------------------
12898 //
12899 // // pertinent parts of existing instructions in architecture description
12900 // instruct movI(rRegI dst, rRegI src) %{
12901 // match(Set dst (CopyI src));
12902 // %}
12903 //
12904 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
12905 // match(Set dst (AddI dst src));
12906 // effect(KILL cr);
12907 // %}
12908 //
12909 // // Change (inc mov) to lea
12910 // peephole %{
12911 // // increment preceeded by register-register move
12912 // peepmatch ( incI_eReg movI );
12913 // // require that the destination register of the increment
12914 // // match the destination register of the move
12915 // peepconstraint ( 0.dst == 1.dst );
12916 // // construct a replacement instruction that sets
12917 // // the destination to ( move's source register + one )
12918 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12919 // %}
12920 //
12921 // Implementation no longer uses movX instructions since
12922 // machine-independent system no longer uses CopyX nodes.
12923 //
12924 // peephole %{
12925 // peepmatch ( incI_eReg movI );
12926 // peepconstraint ( 0.dst == 1.dst );
12927 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12928 // %}
12929 //
12930 // peephole %{
12931 // peepmatch ( decI_eReg movI );
12932 // peepconstraint ( 0.dst == 1.dst );
12933 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12934 // %}
12935 //
12936 // peephole %{
12937 // peepmatch ( addI_eReg_imm movI );
12938 // peepconstraint ( 0.dst == 1.dst );
12939 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12940 // %}
12941 //
12942 // peephole %{
12943 // peepmatch ( addP_eReg_imm movP );
12944 // peepconstraint ( 0.dst == 1.dst );
12945 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12946 // %}
12947
12948 // // Change load of spilled value to only a spill
12949 // instruct storeI(memory mem, rRegI src) %{
12950 // match(Set mem (StoreI mem src));
12951 // %}
12952 //
12953 // instruct loadI(rRegI dst, memory mem) %{
12954 // match(Set dst (LoadI mem));
12955 // %}
12956 //
12957 peephole %{
12958 peepmatch ( loadI storeI );
12959 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12960 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12961 %}
12962
12963 //----------SMARTSPILL RULES---------------------------------------------------
12964 // These must follow all instruction definitions as they use the names
12965 // defined in the instructions definitions.