1 /*
   2  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "vm_version_x86.hpp"
  30 
  31 class BiasedLockingCounters;
  32 
  33 // Contains all the definitions needed for x86 assembly code generation.
  34 
  35 // Calling convention
  36 class Argument VALUE_OBJ_CLASS_SPEC {
  37  public:
  38   enum {
  39 #ifdef _LP64
  40 #ifdef _WIN64
  41     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  42     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  43 #else
  44     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  45     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  46 #endif // _WIN64
  47     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  48     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  49 #else
  50     n_register_parameters = 0   // 0 registers used to pass arguments
  51 #endif // _LP64
  52   };
  53 };
  54 
  55 
  56 #ifdef _LP64
  57 // Symbolically name the register arguments used by the c calling convention.
  58 // Windows is different from linux/solaris. So much for standards...
  59 
  60 #ifdef _WIN64
  61 
  62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  64 REGISTER_DECLARATION(Register, c_rarg2, r8);
  65 REGISTER_DECLARATION(Register, c_rarg3, r9);
  66 
  67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  71 
  72 #else
  73 
  74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  78 REGISTER_DECLARATION(Register, c_rarg4, r8);
  79 REGISTER_DECLARATION(Register, c_rarg5, r9);
  80 
  81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  89 
  90 #endif // _WIN64
  91 
  92 // Symbolically name the register arguments used by the Java calling convention.
  93 // We have control over the convention for java so we can do what we please.
  94 // What pleases us is to offset the java calling convention so that when
  95 // we call a suitable jni method the arguments are lined up and we don't
  96 // have to do little shuffling. A suitable jni method is non-static and a
  97 // small number of arguments (two fewer args on windows)
  98 //
  99 //        |-------------------------------------------------------|
 100 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
 101 //        |-------------------------------------------------------|
 102 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 103 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 104 //        |-------------------------------------------------------|
 105 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 106 //        |-------------------------------------------------------|
 107 
 108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 111 // Windows runs out of register args here
 112 #ifdef _WIN64
 113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 115 #else
 116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 118 #endif /* _WIN64 */
 119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 120 
 121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 129 
 130 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 131 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 132 
 133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 135 
 136 #else
 137 // rscratch1 will apear in 32bit code that is dead but of course must compile
 138 // Using noreg ensures if the dead code is incorrectly live and executed it
 139 // will cause an assertion failure
 140 #define rscratch1 noreg
 141 #define rscratch2 noreg
 142 
 143 #endif // _LP64
 144 
 145 // JSR 292
 146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
 149 
 150 // Address is an abstraction used to represent a memory location
 151 // using any of the amd64 addressing modes with one object.
 152 //
 153 // Note: A register location is represented via a Register, not
 154 //       via an address for efficiency & simplicity reasons.
 155 
 156 class ArrayAddress;
 157 
 158 class Address VALUE_OBJ_CLASS_SPEC {
 159  public:
 160   enum ScaleFactor {
 161     no_scale = -1,
 162     times_1  =  0,
 163     times_2  =  1,
 164     times_4  =  2,
 165     times_8  =  3,
 166     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 167   };
 168   static ScaleFactor times(int size) {
 169     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 170     if (size == 8)  return times_8;
 171     if (size == 4)  return times_4;
 172     if (size == 2)  return times_2;
 173     return times_1;
 174   }
 175   static int scale_size(ScaleFactor scale) {
 176     assert(scale != no_scale, "");
 177     assert(((1 << (int)times_1) == 1 &&
 178             (1 << (int)times_2) == 2 &&
 179             (1 << (int)times_4) == 4 &&
 180             (1 << (int)times_8) == 8), "");
 181     return (1 << (int)scale);
 182   }
 183 
 184  private:
 185   Register         _base;
 186   Register         _index;
 187   ScaleFactor      _scale;
 188   int              _disp;
 189   RelocationHolder _rspec;
 190 
 191   // Easily misused constructors make them private
 192   // %%% can we make these go away?
 193   NOT_LP64(Address(address loc, RelocationHolder spec);)
 194   Address(int disp, address loc, relocInfo::relocType rtype);
 195   Address(int disp, address loc, RelocationHolder spec);
 196 
 197  public:
 198 
 199  int disp() { return _disp; }
 200   // creation
 201   Address()
 202     : _base(noreg),
 203       _index(noreg),
 204       _scale(no_scale),
 205       _disp(0) {
 206   }
 207 
 208   // No default displacement otherwise Register can be implicitly
 209   // converted to 0(Register) which is quite a different animal.
 210 
 211   Address(Register base, int disp)
 212     : _base(base),
 213       _index(noreg),
 214       _scale(no_scale),
 215       _disp(disp) {
 216   }
 217 
 218   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 219     : _base (base),
 220       _index(index),
 221       _scale(scale),
 222       _disp (disp) {
 223     assert(!index->is_valid() == (scale == Address::no_scale),
 224            "inconsistent address");
 225   }
 226 
 227   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 228     : _base (base),
 229       _index(index.register_or_noreg()),
 230       _scale(scale),
 231       _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
 232     if (!index.is_register())  scale = Address::no_scale;
 233     assert(!_index->is_valid() == (scale == Address::no_scale),
 234            "inconsistent address");
 235   }
 236 
 237   Address plus_disp(int disp) const {
 238     Address a = (*this);
 239     a._disp += disp;
 240     return a;
 241   }
 242   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 243     Address a = (*this);
 244     a._disp += disp.constant_or_zero() * scale_size(scale);
 245     if (disp.is_register()) {
 246       assert(!a.index()->is_valid(), "competing indexes");
 247       a._index = disp.as_register();
 248       a._scale = scale;
 249     }
 250     return a;
 251   }
 252   bool is_same_address(Address a) const {
 253     // disregard _rspec
 254     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 255   }
 256 
 257   // The following two overloads are used in connection with the
 258   // ByteSize type (see sizes.hpp).  They simplify the use of
 259   // ByteSize'd arguments in assembly code. Note that their equivalent
 260   // for the optimized build are the member functions with int disp
 261   // argument since ByteSize is mapped to an int type in that case.
 262   //
 263   // Note: DO NOT introduce similar overloaded functions for WordSize
 264   // arguments as in the optimized mode, both ByteSize and WordSize
 265   // are mapped to the same type and thus the compiler cannot make a
 266   // distinction anymore (=> compiler errors).
 267 
 268 #ifdef ASSERT
 269   Address(Register base, ByteSize disp)
 270     : _base(base),
 271       _index(noreg),
 272       _scale(no_scale),
 273       _disp(in_bytes(disp)) {
 274   }
 275 
 276   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 277     : _base(base),
 278       _index(index),
 279       _scale(scale),
 280       _disp(in_bytes(disp)) {
 281     assert(!index->is_valid() == (scale == Address::no_scale),
 282            "inconsistent address");
 283   }
 284 
 285   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 286     : _base (base),
 287       _index(index.register_or_noreg()),
 288       _scale(scale),
 289       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
 290     if (!index.is_register())  scale = Address::no_scale;
 291     assert(!_index->is_valid() == (scale == Address::no_scale),
 292            "inconsistent address");
 293   }
 294 
 295 #endif // ASSERT
 296 
 297   // accessors
 298   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 299   Register    base()             const { return _base;  }
 300   Register    index()            const { return _index; }
 301   ScaleFactor scale()            const { return _scale; }
 302   int         disp()             const { return _disp;  }
 303 
 304   // Convert the raw encoding form into the form expected by the constructor for
 305   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 306   // that to noreg for the Address constructor.
 307   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 308 
 309   static Address make_array(ArrayAddress);
 310 
 311  private:
 312   bool base_needs_rex() const {
 313     return _base != noreg && _base->encoding() >= 8;
 314   }
 315 
 316   bool index_needs_rex() const {
 317     return _index != noreg &&_index->encoding() >= 8;
 318   }
 319 
 320   relocInfo::relocType reloc() const { return _rspec.type(); }
 321 
 322   friend class Assembler;
 323   friend class MacroAssembler;
 324   friend class LIR_Assembler; // base/index/scale/disp
 325 };
 326 
 327 //
 328 // AddressLiteral has been split out from Address because operands of this type
 329 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 330 // the few instructions that need to deal with address literals are unique and the
 331 // MacroAssembler does not have to implement every instruction in the Assembler
 332 // in order to search for address literals that may need special handling depending
 333 // on the instruction and the platform. As small step on the way to merging i486/amd64
 334 // directories.
 335 //
 336 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
 337   friend class ArrayAddress;
 338   RelocationHolder _rspec;
 339   // Typically we use AddressLiterals we want to use their rval
 340   // However in some situations we want the lval (effect address) of the item.
 341   // We provide a special factory for making those lvals.
 342   bool _is_lval;
 343 
 344   // If the target is far we'll need to load the ea of this to
 345   // a register to reach it. Otherwise if near we can do rip
 346   // relative addressing.
 347 
 348   address          _target;
 349 
 350  protected:
 351   // creation
 352   AddressLiteral()
 353     : _is_lval(false),
 354       _target(NULL)
 355   {}
 356 
 357   public:
 358 
 359 
 360   AddressLiteral(address target, relocInfo::relocType rtype);
 361 
 362   AddressLiteral(address target, RelocationHolder const& rspec)
 363     : _rspec(rspec),
 364       _is_lval(false),
 365       _target(target)
 366   {}
 367 
 368   AddressLiteral addr() {
 369     AddressLiteral ret = *this;
 370     ret._is_lval = true;
 371     return ret;
 372   }
 373 
 374 
 375  private:
 376 
 377   address target() { return _target; }
 378   bool is_lval() { return _is_lval; }
 379 
 380   relocInfo::relocType reloc() const { return _rspec.type(); }
 381   const RelocationHolder& rspec() const { return _rspec; }
 382 
 383   friend class Assembler;
 384   friend class MacroAssembler;
 385   friend class Address;
 386   friend class LIR_Assembler;
 387 };
 388 
 389 // Convience classes
 390 class RuntimeAddress: public AddressLiteral {
 391 
 392   public:
 393 
 394   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 395 
 396 };
 397 
 398 class ExternalAddress: public AddressLiteral {
 399  private:
 400   static relocInfo::relocType reloc_for_target(address target) {
 401     // Sometimes ExternalAddress is used for values which aren't
 402     // exactly addresses, like the card table base.
 403     // external_word_type can't be used for values in the first page
 404     // so just skip the reloc in that case.
 405     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 406   }
 407 
 408  public:
 409 
 410   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 411 
 412 };
 413 
 414 class InternalAddress: public AddressLiteral {
 415 
 416   public:
 417 
 418   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 419 
 420 };
 421 
 422 // x86 can do array addressing as a single operation since disp can be an absolute
 423 // address amd64 can't. We create a class that expresses the concept but does extra
 424 // magic on amd64 to get the final result
 425 
 426 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
 427   private:
 428 
 429   AddressLiteral _base;
 430   Address        _index;
 431 
 432   public:
 433 
 434   ArrayAddress() {};
 435   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 436   AddressLiteral base() { return _base; }
 437   Address index() { return _index; }
 438 
 439 };
 440 
 441 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
 442 
 443 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 444 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 445 // is what you get. The Assembler is generating code into a CodeBuffer.
 446 
 447 class Assembler : public AbstractAssembler  {
 448   friend class AbstractAssembler; // for the non-virtual hack
 449   friend class LIR_Assembler; // as_Address()
 450   friend class StubGenerator;
 451 
 452  public:
 453   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 454     zero          = 0x4,
 455     notZero       = 0x5,
 456     equal         = 0x4,
 457     notEqual      = 0x5,
 458     less          = 0xc,
 459     lessEqual     = 0xe,
 460     greater       = 0xf,
 461     greaterEqual  = 0xd,
 462     below         = 0x2,
 463     belowEqual    = 0x6,
 464     above         = 0x7,
 465     aboveEqual    = 0x3,
 466     overflow      = 0x0,
 467     noOverflow    = 0x1,
 468     carrySet      = 0x2,
 469     carryClear    = 0x3,
 470     negative      = 0x8,
 471     positive      = 0x9,
 472     parity        = 0xa,
 473     noParity      = 0xb
 474   };
 475 
 476   enum Prefix {
 477     // segment overrides
 478     CS_segment = 0x2e,
 479     SS_segment = 0x36,
 480     DS_segment = 0x3e,
 481     ES_segment = 0x26,
 482     FS_segment = 0x64,
 483     GS_segment = 0x65,
 484 
 485     REX        = 0x40,
 486 
 487     REX_B      = 0x41,
 488     REX_X      = 0x42,
 489     REX_XB     = 0x43,
 490     REX_R      = 0x44,
 491     REX_RB     = 0x45,
 492     REX_RX     = 0x46,
 493     REX_RXB    = 0x47,
 494 
 495     REX_W      = 0x48,
 496 
 497     REX_WB     = 0x49,
 498     REX_WX     = 0x4A,
 499     REX_WXB    = 0x4B,
 500     REX_WR     = 0x4C,
 501     REX_WRB    = 0x4D,
 502     REX_WRX    = 0x4E,
 503     REX_WRXB   = 0x4F,
 504 
 505     VEX_3bytes = 0xC4,
 506     VEX_2bytes = 0xC5
 507   };
 508 
 509   enum VexPrefix {
 510     VEX_B = 0x20,
 511     VEX_X = 0x40,
 512     VEX_R = 0x80,
 513     VEX_W = 0x80
 514   };
 515 
 516   enum VexSimdPrefix {
 517     VEX_SIMD_NONE = 0x0,
 518     VEX_SIMD_66   = 0x1,
 519     VEX_SIMD_F3   = 0x2,
 520     VEX_SIMD_F2   = 0x3
 521   };
 522 
 523   enum VexOpcode {
 524     VEX_OPCODE_NONE  = 0x0,
 525     VEX_OPCODE_0F    = 0x1,
 526     VEX_OPCODE_0F_38 = 0x2,
 527     VEX_OPCODE_0F_3A = 0x3
 528   };
 529 
 530   enum WhichOperand {
 531     // input to locate_operand, and format code for relocations
 532     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 533     disp32_operand = 1,          // embedded 32-bit displacement or address
 534     call32_operand = 2,          // embedded 32-bit self-relative displacement
 535 #ifndef _LP64
 536     _WhichOperand_limit = 3
 537 #else
 538      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 539     _WhichOperand_limit = 4
 540 #endif
 541   };
 542 
 543 
 544 
 545   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 546   // of instructions are freely declared without the need for wrapping them an ifdef.
 547   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 548   // In the .cpp file the implementations are wrapped so that they are dropped out
 549   // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
 550   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 551   //
 552   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 553   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 554 
 555 private:
 556 
 557 
 558   // 64bit prefixes
 559   int prefix_and_encode(int reg_enc, bool byteinst = false);
 560   int prefixq_and_encode(int reg_enc);
 561 
 562   int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
 563   int prefixq_and_encode(int dst_enc, int src_enc);
 564 
 565   void prefix(Register reg);
 566   void prefix(Address adr);
 567   void prefixq(Address adr);
 568 
 569   void prefix(Address adr, Register reg,  bool byteinst = false);
 570   void prefix(Address adr, XMMRegister reg);
 571   void prefixq(Address adr, Register reg);
 572   void prefixq(Address adr, XMMRegister reg);
 573 
 574   void prefetch_prefix(Address src);
 575 
 576   void rex_prefix(Address adr, XMMRegister xreg,
 577                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 578   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 579                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 580 
 581   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
 582                   int nds_enc, VexSimdPrefix pre, VexOpcode opc,
 583                   bool vector256);
 584 
 585   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 586                   VexSimdPrefix pre, VexOpcode opc,
 587                   bool vex_w, bool vector256);
 588 
 589   void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
 590                   VexSimdPrefix pre, bool vector256 = false) {
 591     int dst_enc = dst->encoding();
 592     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
 593     vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256);
 594   }
 595 
 596   void vex_prefix_0F38(Register dst, Register nds, Address src) {
 597     bool vex_w = false;
 598     bool vector256 = false;
 599     vex_prefix(src, nds->encoding(), dst->encoding(),
 600                VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
 601   }
 602 
 603   void vex_prefix_0F38_q(Register dst, Register nds, Address src) {
 604     bool vex_w = true;
 605     bool vector256 = false;
 606     vex_prefix(src, nds->encoding(), dst->encoding(),
 607                VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
 608   }
 609   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 610                              VexSimdPrefix pre, VexOpcode opc,
 611                              bool vex_w, bool vector256);
 612 
 613   int  vex_prefix_0F38_and_encode(Register dst, Register nds, Register src) {
 614     bool vex_w = false;
 615     bool vector256 = false;
 616     return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
 617                                  VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
 618   }
 619   int  vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src) {
 620     bool vex_w = true;
 621     bool vector256 = false;
 622     return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
 623                                  VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
 624   }
 625   int  vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
 626                              VexSimdPrefix pre, bool vector256 = false,
 627                              VexOpcode opc = VEX_OPCODE_0F) {
 628     int src_enc = src->encoding();
 629     int dst_enc = dst->encoding();
 630     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
 631     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256);
 632   }
 633 
 634   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
 635                    VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
 636                    bool rex_w = false, bool vector256 = false);
 637 
 638   void simd_prefix(XMMRegister dst, Address src,
 639                    VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
 640     simd_prefix(dst, xnoreg, src, pre, opc);
 641   }
 642 
 643   void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
 644     simd_prefix(src, dst, pre);
 645   }
 646   void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
 647                      VexSimdPrefix pre) {
 648     bool rex_w = true;
 649     simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
 650   }
 651 
 652   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
 653                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
 654                              bool rex_w = false, bool vector256 = false);
 655 
 656   // Move/convert 32-bit integer value.
 657   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
 658                              VexSimdPrefix pre) {
 659     // It is OK to cast from Register to XMMRegister to pass argument here
 660     // since only encoding is used in simd_prefix_and_encode() and number of
 661     // Gen and Xmm registers are the same.
 662     return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre);
 663   }
 664   int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) {
 665     return simd_prefix_and_encode(dst, xnoreg, src, pre);
 666   }
 667   int simd_prefix_and_encode(Register dst, XMMRegister src,
 668                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
 669     return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc);
 670   }
 671 
 672   // Move/convert 64-bit integer value.
 673   int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
 674                                VexSimdPrefix pre) {
 675     bool rex_w = true;
 676     return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w);
 677   }
 678   int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) {
 679     return simd_prefix_and_encode_q(dst, xnoreg, src, pre);
 680   }
 681   int simd_prefix_and_encode_q(Register dst, XMMRegister src,
 682                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
 683     bool rex_w = true;
 684     return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w);
 685   }
 686 
 687   // Helper functions for groups of instructions
 688   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 689 
 690   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 691   // Force generation of a 4 byte immediate value even if it fits into 8bit
 692   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 693   void emit_arith(int op1, int op2, Register dst, Register src);
 694 
 695   void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
 696   void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
 697   void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
 698   void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
 699   void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
 700                       Address src, VexSimdPrefix pre, bool vector256);
 701   void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
 702                       XMMRegister src, VexSimdPrefix pre, bool vector256);
 703 
 704   void emit_operand(Register reg,
 705                     Register base, Register index, Address::ScaleFactor scale,
 706                     int disp,
 707                     RelocationHolder const& rspec,
 708                     int rip_relative_correction = 0);
 709 
 710   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 711 
 712   // operands that only take the original 32bit registers
 713   void emit_operand32(Register reg, Address adr);
 714 
 715   void emit_operand(XMMRegister reg,
 716                     Register base, Register index, Address::ScaleFactor scale,
 717                     int disp,
 718                     RelocationHolder const& rspec);
 719 
 720   void emit_operand(XMMRegister reg, Address adr);
 721 
 722   void emit_operand(MMXRegister reg, Address adr);
 723 
 724   // workaround gcc (3.2.1-7) bug
 725   void emit_operand(Address adr, MMXRegister reg);
 726 
 727 
 728   // Immediate-to-memory forms
 729   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 730 
 731   void emit_farith(int b1, int b2, int i);
 732 
 733 
 734  protected:
 735   #ifdef ASSERT
 736   void check_relocation(RelocationHolder const& rspec, int format);
 737   #endif
 738 
 739   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 740   void emit_data(jint data, RelocationHolder const& rspec, int format);
 741   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 742   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 743 
 744   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 745 
 746   // These are all easily abused and hence protected
 747 
 748   // 32BIT ONLY SECTION
 749 #ifndef _LP64
 750   // Make these disappear in 64bit mode since they would never be correct
 751   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 752   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 753 
 754   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 755   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 756 
 757   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 758 #else
 759   // 64BIT ONLY SECTION
 760   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 761 
 762   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 763   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 764 
 765   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 766   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 767 #endif // _LP64
 768 
 769   // These are unique in that we are ensured by the caller that the 32bit
 770   // relative in these instructions will always be able to reach the potentially
 771   // 64bit address described by entry. Since they can take a 64bit address they
 772   // don't have the 32 suffix like the other instructions in this class.
 773 
 774   void call_literal(address entry, RelocationHolder const& rspec);
 775   void jmp_literal(address entry, RelocationHolder const& rspec);
 776 
 777   // Avoid using directly section
 778   // Instructions in this section are actually usable by anyone without danger
 779   // of failure but have performance issues that are addressed my enhanced
 780   // instructions which will do the proper thing base on the particular cpu.
 781   // We protect them because we don't trust you...
 782 
 783   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 784   // could cause a partial flag stall since they don't set CF flag.
 785   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 786   // which call inc() & dec() or add() & sub() in accordance with
 787   // the product flag UseIncDec value.
 788 
 789   void decl(Register dst);
 790   void decl(Address dst);
 791   void decq(Register dst);
 792   void decq(Address dst);
 793 
 794   void incl(Register dst);
 795   void incl(Address dst);
 796   void incq(Register dst);
 797   void incq(Address dst);
 798 
 799   // New cpus require use of movsd and movss to avoid partial register stall
 800   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 801   // The selection is done in MacroAssembler::movdbl() and movflt().
 802 
 803   // Move Scalar Single-Precision Floating-Point Values
 804   void movss(XMMRegister dst, Address src);
 805   void movss(XMMRegister dst, XMMRegister src);
 806   void movss(Address dst, XMMRegister src);
 807 
 808   // Move Scalar Double-Precision Floating-Point Values
 809   void movsd(XMMRegister dst, Address src);
 810   void movsd(XMMRegister dst, XMMRegister src);
 811   void movsd(Address dst, XMMRegister src);
 812   void movlpd(XMMRegister dst, Address src);
 813 
 814   // New cpus require use of movaps and movapd to avoid partial register stall
 815   // when moving between registers.
 816   void movaps(XMMRegister dst, XMMRegister src);
 817   void movapd(XMMRegister dst, XMMRegister src);
 818 
 819   // End avoid using directly
 820 
 821 
 822   // Instruction prefixes
 823   void prefix(Prefix p);
 824 
 825   public:
 826 
 827   // Creation
 828   Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
 829 
 830   // Decoding
 831   static address locate_operand(address inst, WhichOperand which);
 832   static address locate_next_instruction(address inst);
 833 
 834   // Utilities
 835   static bool is_polling_page_far() NOT_LP64({ return false;});
 836 
 837   // Generic instructions
 838   // Does 32bit or 64bit as needed for the platform. In some sense these
 839   // belong in macro assembler but there is no need for both varieties to exist
 840 
 841   void lea(Register dst, Address src);
 842 
 843   void mov(Register dst, Register src);
 844 
 845   void pusha();
 846   void popa();
 847 
 848   void pushf();
 849   void popf();
 850 
 851   void push(int32_t imm32);
 852 
 853   void push(Register src);
 854 
 855   void pop(Register dst);
 856 
 857   // These are dummies to prevent surprise implicit conversions to Register
 858   void push(void* v);
 859   void pop(void* v);
 860 
 861   // These do register sized moves/scans
 862   void rep_mov();
 863   void rep_stos();
 864   void rep_stosb();
 865   void repne_scan();
 866 #ifdef _LP64
 867   void repne_scanl();
 868 #endif
 869 
 870   // Vanilla instructions in lexical order
 871 
 872   void adcl(Address dst, int32_t imm32);
 873   void adcl(Address dst, Register src);
 874   void adcl(Register dst, int32_t imm32);
 875   void adcl(Register dst, Address src);
 876   void adcl(Register dst, Register src);
 877 
 878   void adcq(Register dst, int32_t imm32);
 879   void adcq(Register dst, Address src);
 880   void adcq(Register dst, Register src);
 881 
 882   void addl(Address dst, int32_t imm32);
 883   void addl(Address dst, Register src);
 884   void addl(Register dst, int32_t imm32);
 885   void addl(Register dst, Address src);
 886   void addl(Register dst, Register src);
 887 
 888   void addq(Address dst, int32_t imm32);
 889   void addq(Address dst, Register src);
 890   void addq(Register dst, int32_t imm32);
 891   void addq(Register dst, Address src);
 892   void addq(Register dst, Register src);
 893 
 894 #ifdef _LP64
 895  //Add Unsigned Integers with Carry Flag
 896   void adcxq(Register dst, Register src);
 897 
 898  //Add Unsigned Integers with Overflow Flag
 899   void adoxq(Register dst, Register src);
 900 #endif
 901 
 902   void addr_nop_4();
 903   void addr_nop_5();
 904   void addr_nop_7();
 905   void addr_nop_8();
 906 
 907   // Add Scalar Double-Precision Floating-Point Values
 908   void addsd(XMMRegister dst, Address src);
 909   void addsd(XMMRegister dst, XMMRegister src);
 910 
 911   // Add Scalar Single-Precision Floating-Point Values
 912   void addss(XMMRegister dst, Address src);
 913   void addss(XMMRegister dst, XMMRegister src);
 914 
 915   // AES instructions
 916   void aesdec(XMMRegister dst, Address src);
 917   void aesdec(XMMRegister dst, XMMRegister src);
 918   void aesdeclast(XMMRegister dst, Address src);
 919   void aesdeclast(XMMRegister dst, XMMRegister src);
 920   void aesenc(XMMRegister dst, Address src);
 921   void aesenc(XMMRegister dst, XMMRegister src);
 922   void aesenclast(XMMRegister dst, Address src);
 923   void aesenclast(XMMRegister dst, XMMRegister src);
 924 
 925 
 926   void andl(Address  dst, int32_t imm32);
 927   void andl(Register dst, int32_t imm32);
 928   void andl(Register dst, Address src);
 929   void andl(Register dst, Register src);
 930 
 931   void andq(Address  dst, int32_t imm32);
 932   void andq(Register dst, int32_t imm32);
 933   void andq(Register dst, Address src);
 934   void andq(Register dst, Register src);
 935 
 936   // BMI instructions
 937   void andnl(Register dst, Register src1, Register src2);
 938   void andnl(Register dst, Register src1, Address src2);
 939   void andnq(Register dst, Register src1, Register src2);
 940   void andnq(Register dst, Register src1, Address src2);
 941 
 942   void blsil(Register dst, Register src);
 943   void blsil(Register dst, Address src);
 944   void blsiq(Register dst, Register src);
 945   void blsiq(Register dst, Address src);
 946 
 947   void blsmskl(Register dst, Register src);
 948   void blsmskl(Register dst, Address src);
 949   void blsmskq(Register dst, Register src);
 950   void blsmskq(Register dst, Address src);
 951 
 952   void blsrl(Register dst, Register src);
 953   void blsrl(Register dst, Address src);
 954   void blsrq(Register dst, Register src);
 955   void blsrq(Register dst, Address src);
 956 
 957   void bsfl(Register dst, Register src);
 958   void bsrl(Register dst, Register src);
 959 
 960 #ifdef _LP64
 961   void bsfq(Register dst, Register src);
 962   void bsrq(Register dst, Register src);
 963 #endif
 964 
 965   void bswapl(Register reg);
 966 
 967   void bswapq(Register reg);
 968 
 969   void call(Label& L, relocInfo::relocType rtype);
 970   void call(Register reg);  // push pc; pc <- reg
 971   void call(Address adr);   // push pc; pc <- adr
 972 
 973   void cdql();
 974 
 975   void cdqq();
 976 
 977   void cld();
 978 
 979   void clflush(Address adr);
 980 
 981   void cmovl(Condition cc, Register dst, Register src);
 982   void cmovl(Condition cc, Register dst, Address src);
 983 
 984   void cmovq(Condition cc, Register dst, Register src);
 985   void cmovq(Condition cc, Register dst, Address src);
 986 
 987 
 988   void cmpb(Address dst, int imm8);
 989 
 990   void cmpl(Address dst, int32_t imm32);
 991 
 992   void cmpl(Register dst, int32_t imm32);
 993   void cmpl(Register dst, Register src);
 994   void cmpl(Register dst, Address src);
 995 
 996   void cmpq(Address dst, int32_t imm32);
 997   void cmpq(Address dst, Register src);
 998 
 999   void cmpq(Register dst, int32_t imm32);
1000   void cmpq(Register dst, Register src);
1001   void cmpq(Register dst, Address src);
1002 
1003   // these are dummies used to catch attempting to convert NULL to Register
1004   void cmpl(Register dst, void* junk); // dummy
1005   void cmpq(Register dst, void* junk); // dummy
1006 
1007   void cmpw(Address dst, int imm16);
1008 
1009   void cmpxchg8 (Address adr);
1010 
1011   void cmpxchgb(Register reg, Address adr);
1012   void cmpxchgl(Register reg, Address adr);
1013 
1014   void cmpxchgq(Register reg, Address adr);
1015 
1016   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1017   void comisd(XMMRegister dst, Address src);
1018   void comisd(XMMRegister dst, XMMRegister src);
1019 
1020   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1021   void comiss(XMMRegister dst, Address src);
1022   void comiss(XMMRegister dst, XMMRegister src);
1023 
1024   // Identify processor type and features
1025   void cpuid();
1026 
1027   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1028   void cvtsd2ss(XMMRegister dst, XMMRegister src);
1029   void cvtsd2ss(XMMRegister dst, Address src);
1030 
1031   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1032   void cvtsi2sdl(XMMRegister dst, Register src);
1033   void cvtsi2sdl(XMMRegister dst, Address src);
1034   void cvtsi2sdq(XMMRegister dst, Register src);
1035   void cvtsi2sdq(XMMRegister dst, Address src);
1036 
1037   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1038   void cvtsi2ssl(XMMRegister dst, Register src);
1039   void cvtsi2ssl(XMMRegister dst, Address src);
1040   void cvtsi2ssq(XMMRegister dst, Register src);
1041   void cvtsi2ssq(XMMRegister dst, Address src);
1042 
1043   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1044   void cvtdq2pd(XMMRegister dst, XMMRegister src);
1045 
1046   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1047   void cvtdq2ps(XMMRegister dst, XMMRegister src);
1048 
1049   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1050   void cvtss2sd(XMMRegister dst, XMMRegister src);
1051   void cvtss2sd(XMMRegister dst, Address src);
1052 
1053   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1054   void cvttsd2sil(Register dst, Address src);
1055   void cvttsd2sil(Register dst, XMMRegister src);
1056   void cvttsd2siq(Register dst, XMMRegister src);
1057 
1058   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1059   void cvttss2sil(Register dst, XMMRegister src);
1060   void cvttss2siq(Register dst, XMMRegister src);
1061 
1062   // Divide Scalar Double-Precision Floating-Point Values
1063   void divsd(XMMRegister dst, Address src);
1064   void divsd(XMMRegister dst, XMMRegister src);
1065 
1066   // Divide Scalar Single-Precision Floating-Point Values
1067   void divss(XMMRegister dst, Address src);
1068   void divss(XMMRegister dst, XMMRegister src);
1069 
1070   void emms();
1071 
1072   void fabs();
1073 
1074   void fadd(int i);
1075 
1076   void fadd_d(Address src);
1077   void fadd_s(Address src);
1078 
1079   // "Alternate" versions of x87 instructions place result down in FPU
1080   // stack instead of on TOS
1081 
1082   void fadda(int i); // "alternate" fadd
1083   void faddp(int i = 1);
1084 
1085   void fchs();
1086 
1087   void fcom(int i);
1088 
1089   void fcomp(int i = 1);
1090   void fcomp_d(Address src);
1091   void fcomp_s(Address src);
1092 
1093   void fcompp();
1094 
1095   void fcos();
1096 
1097   void fdecstp();
1098 
1099   void fdiv(int i);
1100   void fdiv_d(Address src);
1101   void fdivr_s(Address src);
1102   void fdiva(int i);  // "alternate" fdiv
1103   void fdivp(int i = 1);
1104 
1105   void fdivr(int i);
1106   void fdivr_d(Address src);
1107   void fdiv_s(Address src);
1108 
1109   void fdivra(int i); // "alternate" reversed fdiv
1110 
1111   void fdivrp(int i = 1);
1112 
1113   void ffree(int i = 0);
1114 
1115   void fild_d(Address adr);
1116   void fild_s(Address adr);
1117 
1118   void fincstp();
1119 
1120   void finit();
1121 
1122   void fist_s (Address adr);
1123   void fistp_d(Address adr);
1124   void fistp_s(Address adr);
1125 
1126   void fld1();
1127 
1128   void fld_d(Address adr);
1129   void fld_s(Address adr);
1130   void fld_s(int index);
1131   void fld_x(Address adr);  // extended-precision (80-bit) format
1132 
1133   void fldcw(Address src);
1134 
1135   void fldenv(Address src);
1136 
1137   void fldlg2();
1138 
1139   void fldln2();
1140 
1141   void fldz();
1142 
1143   void flog();
1144   void flog10();
1145 
1146   void fmul(int i);
1147 
1148   void fmul_d(Address src);
1149   void fmul_s(Address src);
1150 
1151   void fmula(int i);  // "alternate" fmul
1152 
1153   void fmulp(int i = 1);
1154 
1155   void fnsave(Address dst);
1156 
1157   void fnstcw(Address src);
1158 
1159   void fnstsw_ax();
1160 
1161   void fprem();
1162   void fprem1();
1163 
1164   void frstor(Address src);
1165 
1166   void fsin();
1167 
1168   void fsqrt();
1169 
1170   void fst_d(Address adr);
1171   void fst_s(Address adr);
1172 
1173   void fstp_d(Address adr);
1174   void fstp_d(int index);
1175   void fstp_s(Address adr);
1176   void fstp_x(Address adr); // extended-precision (80-bit) format
1177 
1178   void fsub(int i);
1179   void fsub_d(Address src);
1180   void fsub_s(Address src);
1181 
1182   void fsuba(int i);  // "alternate" fsub
1183 
1184   void fsubp(int i = 1);
1185 
1186   void fsubr(int i);
1187   void fsubr_d(Address src);
1188   void fsubr_s(Address src);
1189 
1190   void fsubra(int i); // "alternate" reversed fsub
1191 
1192   void fsubrp(int i = 1);
1193 
1194   void ftan();
1195 
1196   void ftst();
1197 
1198   void fucomi(int i = 1);
1199   void fucomip(int i = 1);
1200 
1201   void fwait();
1202 
1203   void fxch(int i = 1);
1204 
1205   void fxrstor(Address src);
1206 
1207   void fxsave(Address dst);
1208 
1209   void fyl2x();
1210   void frndint();
1211   void f2xm1();
1212   void fldl2e();
1213 
1214   void hlt();
1215 
1216   void idivl(Register src);
1217   void divl(Register src); // Unsigned division
1218 
1219 #ifdef _LP64
1220   void idivq(Register src);
1221 #endif
1222 
1223   void imull(Register dst, Register src);
1224   void imull(Register dst, Register src, int value);
1225   void imull(Register dst, Address src);
1226 
1227 #ifdef _LP64
1228   void imulq(Register dst, Register src);
1229   void imulq(Register dst, Register src, int value);
1230   void imulq(Register dst, Address src);
1231 #endif
1232 
1233   // jcc is the generic conditional branch generator to run-
1234   // time routines, jcc is used for branches to labels. jcc
1235   // takes a branch opcode (cc) and a label (L) and generates
1236   // either a backward branch or a forward branch and links it
1237   // to the label fixup chain. Usage:
1238   //
1239   // Label L;      // unbound label
1240   // jcc(cc, L);   // forward branch to unbound label
1241   // bind(L);      // bind label to the current pc
1242   // jcc(cc, L);   // backward branch to bound label
1243   // bind(L);      // illegal: a label may be bound only once
1244   //
1245   // Note: The same Label can be used for forward and backward branches
1246   // but it may be bound only once.
1247 
1248   void jcc(Condition cc, Label& L, bool maybe_short = true);
1249 
1250   // Conditional jump to a 8-bit offset to L.
1251   // WARNING: be very careful using this for forward jumps.  If the label is
1252   // not bound within an 8-bit offset of this instruction, a run-time error
1253   // will occur.
1254   void jccb(Condition cc, Label& L);
1255 
1256   void jmp(Address entry);    // pc <- entry
1257 
1258   // Label operations & relative jumps (PPUM Appendix D)
1259   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1260 
1261   void jmp(Register entry); // pc <- entry
1262 
1263   // Unconditional 8-bit offset jump to L.
1264   // WARNING: be very careful using this for forward jumps.  If the label is
1265   // not bound within an 8-bit offset of this instruction, a run-time error
1266   // will occur.
1267   void jmpb(Label& L);
1268 
1269   void ldmxcsr( Address src );
1270 
1271   void leal(Register dst, Address src);
1272 
1273   void leaq(Register dst, Address src);
1274 
1275   void lfence();
1276 
1277   void lock();
1278 
1279   void lzcntl(Register dst, Register src);
1280 
1281 #ifdef _LP64
1282   void lzcntq(Register dst, Register src);
1283 #endif
1284 
1285   enum Membar_mask_bits {
1286     StoreStore = 1 << 3,
1287     LoadStore  = 1 << 2,
1288     StoreLoad  = 1 << 1,
1289     LoadLoad   = 1 << 0
1290   };
1291 
1292   // Serializes memory and blows flags
1293   void membar(Membar_mask_bits order_constraint) {
1294     if (os::is_MP()) {
1295       // We only have to handle StoreLoad
1296       if (order_constraint & StoreLoad) {
1297         // All usable chips support "locked" instructions which suffice
1298         // as barriers, and are much faster than the alternative of
1299         // using cpuid instruction. We use here a locked add [esp-C],0.
1300         // This is conveniently otherwise a no-op except for blowing
1301         // flags, and introducing a false dependency on target memory
1302         // location. We can't do anything with flags, but we can avoid
1303         // memory dependencies in the current method by locked-adding
1304         // somewhere else on the stack. Doing [esp+C] will collide with
1305         // something on stack in current method, hence we go for [esp-C].
1306         // It is convenient since it is almost always in data cache, for
1307         // any small C.  We need to step back from SP to avoid data
1308         // dependencies with other things on below SP (callee-saves, for
1309         // example). Without a clear way to figure out the minimal safe
1310         // distance from SP, it makes sense to step back the complete
1311         // cache line, as this will also avoid possible second-order effects
1312         // with locked ops against the cache line. Our choice of offset
1313         // is bounded by x86 operand encoding, which should stay within
1314         // [-128; +127] to have the 8-byte displacement encoding.
1315         //
1316         // Any change to this code may need to revisit other places in
1317         // the code where this idiom is used, in particular the
1318         // orderAccess code.
1319 
1320         int offset = -VM_Version::L1_line_size();
1321         if (offset < -128) {
1322           offset = -128;
1323         }
1324 
1325         lock();
1326         addl(Address(rsp, offset), 0);// Assert the lock# signal here
1327       }
1328     }
1329   }
1330 
1331   void mfence();
1332 
1333   // Moves
1334 
1335   void mov64(Register dst, int64_t imm64);
1336 
1337   void movb(Address dst, Register src);
1338   void movb(Address dst, int imm8);
1339   void movb(Register dst, Address src);
1340 
1341   void movdl(XMMRegister dst, Register src);
1342   void movdl(Register dst, XMMRegister src);
1343   void movdl(XMMRegister dst, Address src);
1344   void movdl(Address dst, XMMRegister src);
1345 
1346   // Move Double Quadword
1347   void movdq(XMMRegister dst, Register src);
1348   void movdq(Register dst, XMMRegister src);
1349 
1350   // Move Aligned Double Quadword
1351   void movdqa(XMMRegister dst, XMMRegister src);
1352   void movdqa(XMMRegister dst, Address src);
1353 
1354   // Move Unaligned Double Quadword
1355   void movdqu(Address     dst, XMMRegister src);
1356   void movdqu(XMMRegister dst, Address src);
1357   void movdqu(XMMRegister dst, XMMRegister src);
1358 
1359   // Move Unaligned 256bit Vector
1360   void vmovdqu(Address dst, XMMRegister src);
1361   void vmovdqu(XMMRegister dst, Address src);
1362   void vmovdqu(XMMRegister dst, XMMRegister src);
1363 
1364   // Move lower 64bit to high 64bit in 128bit register
1365   void movlhps(XMMRegister dst, XMMRegister src);
1366 
1367   void movl(Register dst, int32_t imm32);
1368   void movl(Address dst, int32_t imm32);
1369   void movl(Register dst, Register src);
1370   void movl(Register dst, Address src);
1371   void movl(Address dst, Register src);
1372 
1373   // These dummies prevent using movl from converting a zero (like NULL) into Register
1374   // by giving the compiler two choices it can't resolve
1375 
1376   void movl(Address  dst, void* junk);
1377   void movl(Register dst, void* junk);
1378 
1379 #ifdef _LP64
1380   void movq(Register dst, Register src);
1381   void movq(Register dst, Address src);
1382   void movq(Address  dst, Register src);
1383 #endif
1384 
1385   void movq(Address     dst, MMXRegister src );
1386   void movq(MMXRegister dst, Address src );
1387 
1388 #ifdef _LP64
1389   // These dummies prevent using movq from converting a zero (like NULL) into Register
1390   // by giving the compiler two choices it can't resolve
1391 
1392   void movq(Address  dst, void* dummy);
1393   void movq(Register dst, void* dummy);
1394 #endif
1395 
1396   // Move Quadword
1397   void movq(Address     dst, XMMRegister src);
1398   void movq(XMMRegister dst, Address src);
1399 
1400   void movsbl(Register dst, Address src);
1401   void movsbl(Register dst, Register src);
1402 
1403 #ifdef _LP64
1404   void movsbq(Register dst, Address src);
1405   void movsbq(Register dst, Register src);
1406 
1407   // Move signed 32bit immediate to 64bit extending sign
1408   void movslq(Address  dst, int32_t imm64);
1409   void movslq(Register dst, int32_t imm64);
1410 
1411   void movslq(Register dst, Address src);
1412   void movslq(Register dst, Register src);
1413   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1414 #endif
1415 
1416   void movswl(Register dst, Address src);
1417   void movswl(Register dst, Register src);
1418 
1419 #ifdef _LP64
1420   void movswq(Register dst, Address src);
1421   void movswq(Register dst, Register src);
1422 #endif
1423 
1424   void movw(Address dst, int imm16);
1425   void movw(Register dst, Address src);
1426   void movw(Address dst, Register src);
1427 
1428   void movzbl(Register dst, Address src);
1429   void movzbl(Register dst, Register src);
1430 
1431 #ifdef _LP64
1432   void movzbq(Register dst, Address src);
1433   void movzbq(Register dst, Register src);
1434 #endif
1435 
1436   void movzwl(Register dst, Address src);
1437   void movzwl(Register dst, Register src);
1438 
1439 #ifdef _LP64
1440   void movzwq(Register dst, Address src);
1441   void movzwq(Register dst, Register src);
1442 #endif
1443 
1444   // Unsigned multiply with RAX destination register
1445   void mull(Address src);
1446   void mull(Register src);
1447 
1448 #ifdef _LP64
1449   void mulq(Address src);
1450   void mulq(Register src);
1451   void mulxq(Register dst1, Register dst2, Register src);
1452 #endif
1453 
1454   // Multiply Scalar Double-Precision Floating-Point Values
1455   void mulsd(XMMRegister dst, Address src);
1456   void mulsd(XMMRegister dst, XMMRegister src);
1457 
1458   // Multiply Scalar Single-Precision Floating-Point Values
1459   void mulss(XMMRegister dst, Address src);
1460   void mulss(XMMRegister dst, XMMRegister src);
1461 
1462   void negl(Register dst);
1463 
1464 #ifdef _LP64
1465   void negq(Register dst);
1466 #endif
1467 
1468   void nop(int i = 1);
1469 
1470   void notl(Register dst);
1471 
1472 #ifdef _LP64
1473   void notq(Register dst);
1474 #endif
1475 
1476   void orl(Address dst, int32_t imm32);
1477   void orl(Register dst, int32_t imm32);
1478   void orl(Register dst, Address src);
1479   void orl(Register dst, Register src);
1480 
1481   void orq(Address dst, int32_t imm32);
1482   void orq(Register dst, int32_t imm32);
1483   void orq(Register dst, Address src);
1484   void orq(Register dst, Register src);
1485 
1486   // Pack with unsigned saturation
1487   void packuswb(XMMRegister dst, XMMRegister src);
1488   void packuswb(XMMRegister dst, Address src);
1489   void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1490 
1491   // Pemutation of 64bit words
1492   void vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256);
1493 
1494   void pause();
1495 
1496   // SSE4.2 string instructions
1497   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1498   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1499 
1500   // SSE 4.1 extract
1501   void pextrd(Register dst, XMMRegister src, int imm8);
1502   void pextrq(Register dst, XMMRegister src, int imm8);
1503 
1504   // SSE 4.1 insert
1505   void pinsrd(XMMRegister dst, Register src, int imm8);
1506   void pinsrq(XMMRegister dst, Register src, int imm8);
1507 
1508   // SSE4.1 packed move
1509   void pmovzxbw(XMMRegister dst, XMMRegister src);
1510   void pmovzxbw(XMMRegister dst, Address src);
1511 
1512 #ifndef _LP64 // no 32bit push/pop on amd64
1513   void popl(Address dst);
1514 #endif
1515 
1516 #ifdef _LP64
1517   void popq(Address dst);
1518 #endif
1519 
1520   void popcntl(Register dst, Address src);
1521   void popcntl(Register dst, Register src);
1522 
1523 #ifdef _LP64
1524   void popcntq(Register dst, Address src);
1525   void popcntq(Register dst, Register src);
1526 #endif
1527 
1528   // Prefetches (SSE, SSE2, 3DNOW only)
1529 
1530   void prefetchnta(Address src);
1531   void prefetchr(Address src);
1532   void prefetcht0(Address src);
1533   void prefetcht1(Address src);
1534   void prefetcht2(Address src);
1535   void prefetchw(Address src);
1536 
1537   // Shuffle Bytes
1538   void pshufb(XMMRegister dst, XMMRegister src);
1539   void pshufb(XMMRegister dst, Address src);
1540 
1541   // Shuffle Packed Doublewords
1542   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1543   void pshufd(XMMRegister dst, Address src,     int mode);
1544 
1545   // Shuffle Packed Low Words
1546   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1547   void pshuflw(XMMRegister dst, Address src,     int mode);
1548 
1549   // Shift Right by bytes Logical DoubleQuadword Immediate
1550   void psrldq(XMMRegister dst, int shift);
1551 
1552   // Logical Compare 128bit
1553   void ptest(XMMRegister dst, XMMRegister src);
1554   void ptest(XMMRegister dst, Address src);
1555   // Logical Compare 256bit
1556   void vptest(XMMRegister dst, XMMRegister src);
1557   void vptest(XMMRegister dst, Address src);
1558 
1559   // Interleave Low Bytes
1560   void punpcklbw(XMMRegister dst, XMMRegister src);
1561   void punpcklbw(XMMRegister dst, Address src);
1562 
1563   // Interleave Low Doublewords
1564   void punpckldq(XMMRegister dst, XMMRegister src);
1565   void punpckldq(XMMRegister dst, Address src);
1566 
1567   // Interleave Low Quadwords
1568   void punpcklqdq(XMMRegister dst, XMMRegister src);
1569 
1570 #ifndef _LP64 // no 32bit push/pop on amd64
1571   void pushl(Address src);
1572 #endif
1573 
1574   void pushq(Address src);
1575 
1576   void rcll(Register dst, int imm8);
1577 
1578   void rclq(Register dst, int imm8);
1579 
1580   void rdtsc();
1581 
1582   void ret(int imm16);
1583 
1584 #ifdef _LP64
1585   void rorq(Register dst, int imm8);
1586   void rorxq(Register dst, Register src, int imm8);
1587 #endif
1588 
1589   void sahf();
1590 
1591   void sarl(Register dst, int imm8);
1592   void sarl(Register dst);
1593 
1594   void sarq(Register dst, int imm8);
1595   void sarq(Register dst);
1596 
1597   void sbbl(Address dst, int32_t imm32);
1598   void sbbl(Register dst, int32_t imm32);
1599   void sbbl(Register dst, Address src);
1600   void sbbl(Register dst, Register src);
1601 
1602   void sbbq(Address dst, int32_t imm32);
1603   void sbbq(Register dst, int32_t imm32);
1604   void sbbq(Register dst, Address src);
1605   void sbbq(Register dst, Register src);
1606 
1607   void setb(Condition cc, Register dst);
1608 
1609   void shldl(Register dst, Register src);
1610 
1611   void shll(Register dst, int imm8);
1612   void shll(Register dst);
1613 
1614   void shlq(Register dst, int imm8);
1615   void shlq(Register dst);
1616 
1617   void shrdl(Register dst, Register src);
1618 
1619   void shrl(Register dst, int imm8);
1620   void shrl(Register dst);
1621 
1622   void shrq(Register dst, int imm8);
1623   void shrq(Register dst);
1624 
1625   void smovl(); // QQQ generic?
1626 
1627   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1628   void sqrtsd(XMMRegister dst, Address src);
1629   void sqrtsd(XMMRegister dst, XMMRegister src);
1630 
1631   // Compute Square Root of Scalar Single-Precision Floating-Point Value
1632   void sqrtss(XMMRegister dst, Address src);
1633   void sqrtss(XMMRegister dst, XMMRegister src);
1634 
1635   void std();
1636 
1637   void stmxcsr( Address dst );
1638 
1639   void subl(Address dst, int32_t imm32);
1640   void subl(Address dst, Register src);
1641   void subl(Register dst, int32_t imm32);
1642   void subl(Register dst, Address src);
1643   void subl(Register dst, Register src);
1644 
1645   void subq(Address dst, int32_t imm32);
1646   void subq(Address dst, Register src);
1647   void subq(Register dst, int32_t imm32);
1648   void subq(Register dst, Address src);
1649   void subq(Register dst, Register src);
1650 
1651   // Force generation of a 4 byte immediate value even if it fits into 8bit
1652   void subl_imm32(Register dst, int32_t imm32);
1653   void subq_imm32(Register dst, int32_t imm32);
1654 
1655   // Subtract Scalar Double-Precision Floating-Point Values
1656   void subsd(XMMRegister dst, Address src);
1657   void subsd(XMMRegister dst, XMMRegister src);
1658 
1659   // Subtract Scalar Single-Precision Floating-Point Values
1660   void subss(XMMRegister dst, Address src);
1661   void subss(XMMRegister dst, XMMRegister src);
1662 
1663   void testb(Register dst, int imm8);
1664 
1665   void testl(Register dst, int32_t imm32);
1666   void testl(Register dst, Register src);
1667   void testl(Register dst, Address src);
1668 
1669   void testq(Register dst, int32_t imm32);
1670   void testq(Register dst, Register src);
1671 
1672   // BMI - count trailing zeros
1673   void tzcntl(Register dst, Register src);
1674   void tzcntq(Register dst, Register src);
1675 
1676   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1677   void ucomisd(XMMRegister dst, Address src);
1678   void ucomisd(XMMRegister dst, XMMRegister src);
1679 
1680   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1681   void ucomiss(XMMRegister dst, Address src);
1682   void ucomiss(XMMRegister dst, XMMRegister src);
1683 
1684   void xabort(int8_t imm8);
1685 
1686   void xaddl(Address dst, Register src);
1687 
1688   void xaddq(Address dst, Register src);
1689 
1690   void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1691 
1692   void xchgl(Register reg, Address adr);
1693   void xchgl(Register dst, Register src);
1694 
1695   void xchgq(Register reg, Address adr);
1696   void xchgq(Register dst, Register src);
1697 
1698   void xend();
1699 
1700   // Get Value of Extended Control Register
1701   void xgetbv();
1702 
1703   void xorl(Register dst, int32_t imm32);
1704   void xorl(Register dst, Address src);
1705   void xorl(Register dst, Register src);
1706 
1707   void xorq(Register dst, Address src);
1708   void xorq(Register dst, Register src);
1709 
1710   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1711 
1712   // AVX 3-operands scalar instructions (encoded with VEX prefix)
1713 
1714   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1715   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1716   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1717   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1718   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1719   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1720   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1721   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1722   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1723   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1724   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1725   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1726   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1727   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1728   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1729   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1730 
1731 
1732   //====================VECTOR ARITHMETIC=====================================
1733 
1734   // Add Packed Floating-Point Values
1735   void addpd(XMMRegister dst, XMMRegister src);
1736   void addps(XMMRegister dst, XMMRegister src);
1737   void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1738   void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1739   void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1740   void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1741 
1742   // Subtract Packed Floating-Point Values
1743   void subpd(XMMRegister dst, XMMRegister src);
1744   void subps(XMMRegister dst, XMMRegister src);
1745   void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1746   void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1747   void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1748   void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1749 
1750   // Multiply Packed Floating-Point Values
1751   void mulpd(XMMRegister dst, XMMRegister src);
1752   void mulps(XMMRegister dst, XMMRegister src);
1753   void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1754   void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1755   void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1756   void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1757 
1758   // Divide Packed Floating-Point Values
1759   void divpd(XMMRegister dst, XMMRegister src);
1760   void divps(XMMRegister dst, XMMRegister src);
1761   void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1762   void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1763   void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1764   void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1765 
1766   // Bitwise Logical AND of Packed Floating-Point Values
1767   void andpd(XMMRegister dst, XMMRegister src);
1768   void andps(XMMRegister dst, XMMRegister src);
1769   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1770   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1771   void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1772   void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1773 
1774   // Bitwise Logical XOR of Packed Floating-Point Values
1775   void xorpd(XMMRegister dst, XMMRegister src);
1776   void xorps(XMMRegister dst, XMMRegister src);
1777   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1778   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1779   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1780   void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1781 
1782   // Add horizontal packed integers
1783   void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1784   void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1785   void phaddw(XMMRegister dst, XMMRegister src);
1786   void phaddd(XMMRegister dst, XMMRegister src);
1787 
1788   // Add packed integers
1789   void paddb(XMMRegister dst, XMMRegister src);
1790   void paddw(XMMRegister dst, XMMRegister src);
1791   void paddd(XMMRegister dst, XMMRegister src);
1792   void paddq(XMMRegister dst, XMMRegister src);
1793   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1794   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1795   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1796   void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1797   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1798   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1799   void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1800   void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1801 
1802   // Sub packed integers
1803   void psubb(XMMRegister dst, XMMRegister src);
1804   void psubw(XMMRegister dst, XMMRegister src);
1805   void psubd(XMMRegister dst, XMMRegister src);
1806   void psubq(XMMRegister dst, XMMRegister src);
1807   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1808   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1809   void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1810   void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1811   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1812   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1813   void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1814   void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1815 
1816   // Multiply packed integers (only shorts and ints)
1817   void pmullw(XMMRegister dst, XMMRegister src);
1818   void pmulld(XMMRegister dst, XMMRegister src);
1819   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1820   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1821   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1822   void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1823 
1824   // Shift left packed integers
1825   void psllw(XMMRegister dst, int shift);
1826   void pslld(XMMRegister dst, int shift);
1827   void psllq(XMMRegister dst, int shift);
1828   void psllw(XMMRegister dst, XMMRegister shift);
1829   void pslld(XMMRegister dst, XMMRegister shift);
1830   void psllq(XMMRegister dst, XMMRegister shift);
1831   void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1832   void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1833   void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1834   void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1835   void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1836   void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1837 
1838   // Logical shift right packed integers
1839   void psrlw(XMMRegister dst, int shift);
1840   void psrld(XMMRegister dst, int shift);
1841   void psrlq(XMMRegister dst, int shift);
1842   void psrlw(XMMRegister dst, XMMRegister shift);
1843   void psrld(XMMRegister dst, XMMRegister shift);
1844   void psrlq(XMMRegister dst, XMMRegister shift);
1845   void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1846   void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1847   void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1848   void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1849   void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1850   void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1851 
1852   // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
1853   void psraw(XMMRegister dst, int shift);
1854   void psrad(XMMRegister dst, int shift);
1855   void psraw(XMMRegister dst, XMMRegister shift);
1856   void psrad(XMMRegister dst, XMMRegister shift);
1857   void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1858   void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1859   void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1860   void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1861 
1862   // And packed integers
1863   void pand(XMMRegister dst, XMMRegister src);
1864   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1865   void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1866 
1867   // Or packed integers
1868   void por(XMMRegister dst, XMMRegister src);
1869   void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1870   void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1871 
1872   // Xor packed integers
1873   void pxor(XMMRegister dst, XMMRegister src);
1874   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1875   void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1876 
1877   // Copy low 128bit into high 128bit of YMM registers.
1878   void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1879   void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1880   void vextractf128h(XMMRegister dst, XMMRegister src);
1881 
1882   // Load/store high 128bit of YMM registers which does not destroy other half.
1883   void vinsertf128h(XMMRegister dst, Address src);
1884   void vinserti128h(XMMRegister dst, Address src);
1885   void vextractf128h(Address dst, XMMRegister src);
1886   void vextracti128h(Address dst, XMMRegister src);
1887 
1888   // duplicate 4-bytes integer data from src into 8 locations in dest
1889   void vpbroadcastd(XMMRegister dst, XMMRegister src);
1890 
1891   // Carry-Less Multiplication Quadword
1892   void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
1893   void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
1894 
1895   // AVX instruction which is used to clear upper 128 bits of YMM registers and
1896   // to avoid transaction penalty between AVX and SSE states. There is no
1897   // penalty if legacy SSE instructions are encoded using VEX prefix because
1898   // they always clear upper 128 bits. It should be used before calling
1899   // runtime code and native libraries.
1900   void vzeroupper();
1901 
1902  protected:
1903   // Next instructions require address alignment 16 bytes SSE mode.
1904   // They should be called only from corresponding MacroAssembler instructions.
1905   void andpd(XMMRegister dst, Address src);
1906   void andps(XMMRegister dst, Address src);
1907   void xorpd(XMMRegister dst, Address src);
1908   void xorps(XMMRegister dst, Address src);
1909 
1910 };
1911 
1912 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP