1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VM_VERSION_X86_HPP
27
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
30
31 class VM_Version : public Abstract_VM_Version {
32 public:
33 // cpuid result register layouts. These are all unions of a uint32_t
34 // (in case anyone wants access to the register as a whole) and a bitfield.
35
36 union StdCpuid1Eax {
37 uint32_t value;
38 struct {
39 uint32_t stepping : 4,
40 model : 4,
41 family : 4,
42 proc_type : 2,
43 : 2,
44 ext_model : 4,
45 ext_family : 8,
46 : 4;
47 } bits;
48 };
49
50 union StdCpuid1Ebx { // example, unused
51 uint32_t value;
52 struct {
53 uint32_t brand_id : 8,
54 clflush_size : 8,
55 threads_per_cpu : 8,
56 apic_id : 8;
57 } bits;
58 };
59
60 union StdCpuid1Ecx {
61 uint32_t value;
62 struct {
63 uint32_t sse3 : 1,
64 clmul : 1,
65 : 1,
66 monitor : 1,
67 : 1,
68 vmx : 1,
69 : 1,
70 est : 1,
71 : 1,
72 ssse3 : 1,
73 cid : 1,
74 : 2,
75 cmpxchg16: 1,
76 : 4,
77 dca : 1,
78 sse4_1 : 1,
79 sse4_2 : 1,
80 : 2,
81 popcnt : 1,
82 : 1,
83 aes : 1,
84 : 1,
85 osxsave : 1,
86 avx : 1,
87 : 3;
88 } bits;
89 };
90
91 union StdCpuid1Edx {
92 uint32_t value;
93 struct {
94 uint32_t : 4,
95 tsc : 1,
96 : 3,
97 cmpxchg8 : 1,
98 : 6,
99 cmov : 1,
100 : 3,
101 clflush : 1,
102 : 3,
103 mmx : 1,
104 fxsr : 1,
105 sse : 1,
106 sse2 : 1,
107 : 1,
108 ht : 1,
109 : 3;
110 } bits;
111 };
112
113 union DcpCpuid4Eax {
114 uint32_t value;
115 struct {
116 uint32_t cache_type : 5,
117 : 21,
118 cores_per_cpu : 6;
119 } bits;
120 };
121
122 union DcpCpuid4Ebx {
123 uint32_t value;
124 struct {
125 uint32_t L1_line_size : 12,
126 partitions : 10,
127 associativity : 10;
128 } bits;
129 };
130
131 union TplCpuidBEbx {
132 uint32_t value;
133 struct {
134 uint32_t logical_cpus : 16,
135 : 16;
136 } bits;
137 };
138
139 union ExtCpuid1Ecx {
140 uint32_t value;
141 struct {
142 uint32_t LahfSahf : 1,
143 CmpLegacy : 1,
144 : 3,
145 lzcnt_intel : 1,
146 lzcnt : 1,
147 sse4a : 1,
148 misalignsse : 1,
149 prefetchw : 1,
150 : 22;
151 } bits;
152 };
153
154 union ExtCpuid1Edx {
155 uint32_t value;
156 struct {
157 uint32_t : 22,
158 mmx_amd : 1,
159 mmx : 1,
160 fxsr : 1,
161 : 4,
162 long_mode : 1,
163 tdnow2 : 1,
164 tdnow : 1;
165 } bits;
166 };
167
168 union ExtCpuid5Ex {
169 uint32_t value;
170 struct {
171 uint32_t L1_line_size : 8,
172 L1_tag_lines : 8,
173 L1_assoc : 8,
174 L1_size : 8;
175 } bits;
176 };
177
178 union ExtCpuid7Edx {
179 uint32_t value;
180 struct {
181 uint32_t : 8,
182 tsc_invariance : 1,
183 : 23;
184 } bits;
185 };
186
187 union ExtCpuid8Ecx {
188 uint32_t value;
189 struct {
190 uint32_t cores_per_cpu : 8,
191 : 24;
192 } bits;
193 };
194
195 union SefCpuid7Eax {
196 uint32_t value;
197 };
198
199 union SefCpuid7Ebx {
200 uint32_t value;
201 struct {
202 uint32_t fsgsbase : 1,
203 : 2,
204 bmi1 : 1,
205 : 1,
206 avx2 : 1,
207 : 2,
208 bmi2 : 1,
209 erms : 1,
210 : 1,
211 rtm : 1,
212 : 4,
213 avx512f : 1,
214 avx512dq : 1,
215 : 1,
216 adx : 1,
217 : 6,
218 avx512pf : 1,
219 avx512er : 1,
220 avx512cd : 1,
221 : 1,
222 avx512bw : 1,
223 avx512vl : 1;
224 } bits;
225 };
226
227 union XemXcr0Eax {
228 uint32_t value;
229 struct {
230 uint32_t x87 : 1,
231 sse : 1,
232 ymm : 1,
233 : 2,
234 opmask : 1,
235 zmm512 : 1,
236 zmm32 : 1,
237 : 24;
238 } bits;
239 };
240
241 protected:
242 static int _cpu;
243 static int _model;
244 static int _stepping;
245 static uint64_t _cpuFeatures; // features returned by the "cpuid" instruction
246 // 0 if this instruction is not available
247 static const char* _features_str;
248
249 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
250 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
251
252 enum {
253 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
254 CPU_CMOV = (1 << 1),
255 CPU_FXSR = (1 << 2),
256 CPU_HT = (1 << 3),
257 CPU_MMX = (1 << 4),
258 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
259 // may not necessarily support other 3dnow instructions
260 CPU_SSE = (1 << 6),
261 CPU_SSE2 = (1 << 7),
262 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
263 CPU_SSSE3 = (1 << 9),
264 CPU_SSE4A = (1 << 10),
265 CPU_SSE4_1 = (1 << 11),
266 CPU_SSE4_2 = (1 << 12),
267 CPU_POPCNT = (1 << 13),
268 CPU_LZCNT = (1 << 14),
269 CPU_TSC = (1 << 15),
270 CPU_TSCINV = (1 << 16),
271 CPU_AVX = (1 << 17),
272 CPU_AVX2 = (1 << 18),
273 CPU_AES = (1 << 19),
274 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
275 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
276 CPU_BMI1 = (1 << 22),
277 CPU_BMI2 = (1 << 23),
278 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
279 CPU_ADX = (1 << 25),
280 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
281 CPU_AVX512DQ = (1 << 27),
282 CPU_AVX512PF = (1 << 28),
283 CPU_AVX512ER = (1 << 29),
284 CPU_AVX512CD = (1 << 30),
285 CPU_AVX512BW = (1 << 31)
286 } cpuFeatureFlags;
287
288 #define CPU_AVX512VL 0x100000000 // EVEX instructions with smaller vector length : enums are limited to 32bit
289
290 enum {
291 // AMD
292 CPU_FAMILY_AMD_11H = 0x11,
293 // Intel
294 CPU_FAMILY_INTEL_CORE = 6,
295 CPU_MODEL_NEHALEM = 0x1e,
296 CPU_MODEL_NEHALEM_EP = 0x1a,
297 CPU_MODEL_NEHALEM_EX = 0x2e,
298 CPU_MODEL_WESTMERE = 0x25,
299 CPU_MODEL_WESTMERE_EP = 0x2c,
300 CPU_MODEL_WESTMERE_EX = 0x2f,
301 CPU_MODEL_SANDYBRIDGE = 0x2a,
302 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
303 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
304 CPU_MODEL_HASWELL_E3 = 0x3c,
305 CPU_MODEL_HASWELL_E7 = 0x3f,
306 CPU_MODEL_BROADWELL = 0x3d,
307 CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3
308 } cpuExtendedFamily;
309
310 // cpuid information block. All info derived from executing cpuid with
311 // various function numbers is stored here. Intel and AMD info is
312 // merged in this block: accessor methods disentangle it.
313 //
314 // The info block is laid out in subblocks of 4 dwords corresponding to
315 // eax, ebx, ecx and edx, whether or not they contain anything useful.
316 struct CpuidInfo {
317 // cpuid function 0
318 uint32_t std_max_function;
319 uint32_t std_vendor_name_0;
320 uint32_t std_vendor_name_1;
321 uint32_t std_vendor_name_2;
322
323 // cpuid function 1
324 StdCpuid1Eax std_cpuid1_eax;
325 StdCpuid1Ebx std_cpuid1_ebx;
326 StdCpuid1Ecx std_cpuid1_ecx;
327 StdCpuid1Edx std_cpuid1_edx;
328
329 // cpuid function 4 (deterministic cache parameters)
330 DcpCpuid4Eax dcp_cpuid4_eax;
331 DcpCpuid4Ebx dcp_cpuid4_ebx;
332 uint32_t dcp_cpuid4_ecx; // unused currently
333 uint32_t dcp_cpuid4_edx; // unused currently
334
335 // cpuid function 7 (structured extended features)
336 SefCpuid7Eax sef_cpuid7_eax;
337 SefCpuid7Ebx sef_cpuid7_ebx;
338 uint32_t sef_cpuid7_ecx; // unused currently
339 uint32_t sef_cpuid7_edx; // unused currently
340
341 // cpuid function 0xB (processor topology)
342 // ecx = 0
343 uint32_t tpl_cpuidB0_eax;
344 TplCpuidBEbx tpl_cpuidB0_ebx;
345 uint32_t tpl_cpuidB0_ecx; // unused currently
346 uint32_t tpl_cpuidB0_edx; // unused currently
347
348 // ecx = 1
349 uint32_t tpl_cpuidB1_eax;
350 TplCpuidBEbx tpl_cpuidB1_ebx;
351 uint32_t tpl_cpuidB1_ecx; // unused currently
352 uint32_t tpl_cpuidB1_edx; // unused currently
353
354 // ecx = 2
355 uint32_t tpl_cpuidB2_eax;
356 TplCpuidBEbx tpl_cpuidB2_ebx;
357 uint32_t tpl_cpuidB2_ecx; // unused currently
358 uint32_t tpl_cpuidB2_edx; // unused currently
359
360 // cpuid function 0x80000000 // example, unused
361 uint32_t ext_max_function;
362 uint32_t ext_vendor_name_0;
363 uint32_t ext_vendor_name_1;
364 uint32_t ext_vendor_name_2;
365
366 // cpuid function 0x80000001
367 uint32_t ext_cpuid1_eax; // reserved
368 uint32_t ext_cpuid1_ebx; // reserved
369 ExtCpuid1Ecx ext_cpuid1_ecx;
370 ExtCpuid1Edx ext_cpuid1_edx;
371
372 // cpuid functions 0x80000002 thru 0x80000004: example, unused
373 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
374 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
375 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
376
377 // cpuid function 0x80000005 // AMD L1, Intel reserved
378 uint32_t ext_cpuid5_eax; // unused currently
379 uint32_t ext_cpuid5_ebx; // reserved
380 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
381 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
382
383 // cpuid function 0x80000007
384 uint32_t ext_cpuid7_eax; // reserved
385 uint32_t ext_cpuid7_ebx; // reserved
386 uint32_t ext_cpuid7_ecx; // reserved
387 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
388
389 // cpuid function 0x80000008
390 uint32_t ext_cpuid8_eax; // unused currently
391 uint32_t ext_cpuid8_ebx; // reserved
392 ExtCpuid8Ecx ext_cpuid8_ecx;
393 uint32_t ext_cpuid8_edx; // reserved
394
395 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
396 XemXcr0Eax xem_xcr0_eax;
397 uint32_t xem_xcr0_edx; // reserved
398
399 // Space to save ymm registers after signal handle
400 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
401
402 // Space to save zmm registers after signal handle
403 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
404 };
405
406 // The actual cpuid info block
407 static CpuidInfo _cpuid_info;
408
409 // Extractors and predicates
410 static uint32_t extended_cpu_family() {
411 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
412 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
413 return result;
414 }
415
416 static uint32_t extended_cpu_model() {
417 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
418 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
419 return result;
420 }
421
422 static uint32_t cpu_stepping() {
423 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
424 return result;
425 }
426
427 static uint logical_processor_count() {
428 uint result = threads_per_core();
429 return result;
430 }
431
432 static uint64_t feature_flags() {
433 uint64_t result = 0;
434 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
435 result |= CPU_CX8;
436 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
437 result |= CPU_CMOV;
438 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
439 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
440 result |= CPU_FXSR;
441 // HT flag is set for multi-core processors also.
442 if (threads_per_core() > 1)
443 result |= CPU_HT;
444 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
445 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
446 result |= CPU_MMX;
447 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
448 result |= CPU_SSE;
449 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
450 result |= CPU_SSE2;
451 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
452 result |= CPU_SSE3;
453 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
454 result |= CPU_SSSE3;
455 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
456 result |= CPU_SSE4_1;
457 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
458 result |= CPU_SSE4_2;
459 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
460 result |= CPU_POPCNT;
461 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
462 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
463 _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
464 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
465 result |= CPU_AVX;
466 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
467 result |= CPU_AVX2;
468 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
469 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
470 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
471 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
472 result |= CPU_AVX512F;
473 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
474 result |= CPU_AVX512CD;
475 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
476 result |= CPU_AVX512DQ;
477 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
478 result |= CPU_AVX512PF;
479 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
480 result |= CPU_AVX512ER;
481 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
482 result |= CPU_AVX512BW;
483 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
484 result |= CPU_AVX512VL;
485 }
486 }
487 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
488 result |= CPU_BMI1;
489 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
490 result |= CPU_TSC;
491 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
492 result |= CPU_TSCINV;
493 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
494 result |= CPU_AES;
495 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
496 result |= CPU_ERMS;
497 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
498 result |= CPU_CLMUL;
499 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
500 result |= CPU_RTM;
501
502 // AMD features.
503 if (is_amd()) {
504 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
505 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
506 result |= CPU_3DNOW_PREFETCH;
507 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
508 result |= CPU_LZCNT;
509 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
510 result |= CPU_SSE4A;
511 }
512 // Intel features.
513 if(is_intel()) {
514 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
515 result |= CPU_ADX;
516 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
517 result |= CPU_BMI2;
518 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
519 result |= CPU_LZCNT;
520 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
521 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
522 result |= CPU_3DNOW_PREFETCH;
523 }
524 }
525
526 return result;
527 }
528
529 static bool os_supports_avx_vectors() {
530 bool retVal = false;
531 if (supports_evex()) {
532 // Verify that OS save/restore all bits of EVEX registers
533 // during signal processing.
534 int nreg = 2 LP64_ONLY(+2);
535 retVal = true;
536 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
537 if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
538 retVal = false;
539 break;
540 }
541 }
542 } else if (supports_avx()) {
543 // Verify that OS save/restore all bits of AVX registers
544 // during signal processing.
545 int nreg = 2 LP64_ONLY(+2);
546 retVal = true;
547 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
548 if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
549 retVal = false;
550 break;
551 }
552 }
553 }
554 return retVal;
555 }
556
557 static void get_processor_features();
558
559 public:
560 // Offsets for cpuid asm stub
561 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
562 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
563 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
564 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
565 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
566 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
567 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
568 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
569 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
570 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
571 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
572 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
573 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
574 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
575
576 // The value used to check ymm register after signal handle
577 static int ymm_test_value() { return 0xCAFEBABE; }
578
579 static void get_cpu_info_wrapper();
580 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
581 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
582 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
583 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
584
585 static void clean_cpuFeatures() { _cpuFeatures = 0; }
586 static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); }
587 static void set_evex_cpuFeatures() { _cpuFeatures = (CPU_AVX512F | CPU_SSE | CPU_SSE2 ); }
588
589
590 // Initialization
591 static void initialize();
592
593 // Override Abstract_VM_Version implementation
594 static bool use_biased_locking();
595
596 // Asserts
597 static void assert_is_initialized() {
598 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
599 }
600
601 //
602 // Processor family:
603 // 3 - 386
604 // 4 - 486
605 // 5 - Pentium
606 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
607 // Pentium M, Core Solo, Core Duo, Core2 Duo
608 // family 6 model: 9, 13, 14, 15
609 // 0x0f - Pentium 4, Opteron
610 //
611 // Note: The cpu family should be used to select between
612 // instruction sequences which are valid on all Intel
613 // processors. Use the feature test functions below to
614 // determine whether a particular instruction is supported.
615 //
616 static int cpu_family() { return _cpu;}
617 static bool is_P6() { return cpu_family() >= 6; }
618 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
619 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
620
621 static bool supports_processor_topology() {
622 return (_cpuid_info.std_max_function >= 0xB) &&
623 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
624 // Some cpus have max cpuid >= 0xB but do not support processor topology.
625 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
626 }
627
628 static uint cores_per_cpu() {
629 uint result = 1;
630 if (is_intel()) {
631 bool supports_topology = supports_processor_topology();
632 if (supports_topology) {
633 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
634 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
635 }
636 if (!supports_topology || result == 0) {
637 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
638 }
639 } else if (is_amd()) {
640 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
641 }
642 return result;
643 }
644
645 static uint threads_per_core() {
646 uint result = 1;
647 if (is_intel() && supports_processor_topology()) {
648 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
649 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
650 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
651 cores_per_cpu();
652 }
653 return result;
654 }
655
656 static intx L1_line_size() {
657 intx result = 0;
658 if (is_intel()) {
659 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
660 } else if (is_amd()) {
661 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
662 }
663 if (result < 32) // not defined ?
664 result = 32; // 32 bytes by default on x86 and other x64
665 return result;
666 }
667
668 static intx prefetch_data_size() {
669 return L1_line_size();
670 }
671
672 //
673 // Feature identification
674 //
675 static bool supports_cpuid() { return _cpuFeatures != 0; }
676 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
677 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
678 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
679 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
680 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
681 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
682 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
683 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
684 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
685 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
686 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
687 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
688 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; }
689 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; }
690 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
691 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; }
692 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; }
693 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; }
694 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; }
695 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; }
696 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; }
697 static bool supports_adx() { return (_cpuFeatures & CPU_ADX) != 0; }
698 static bool supports_evex() { return (_cpuFeatures & CPU_AVX512F) != 0; }
699 static bool supports_avx512dq() { return (_cpuFeatures & CPU_AVX512DQ) != 0; }
700 static bool supports_avx512pf() { return (_cpuFeatures & CPU_AVX512PF) != 0; }
701 static bool supports_avx512er() { return (_cpuFeatures & CPU_AVX512ER) != 0; }
702 static bool supports_avx512cd() { return (_cpuFeatures & CPU_AVX512CD) != 0; }
703 static bool supports_avx512bw() { return (_cpuFeatures & CPU_AVX512BW) != 0; }
704 static bool supports_avx512vl() { return (_cpuFeatures & CPU_AVX512VL) != 0; }
705 // Intel features
706 static bool is_intel_family_core() { return is_intel() &&
707 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
708
709 static bool is_intel_tsc_synched_at_init() {
710 if (is_intel_family_core()) {
711 uint32_t ext_model = extended_cpu_model();
712 if (ext_model == CPU_MODEL_NEHALEM_EP ||
713 ext_model == CPU_MODEL_WESTMERE_EP ||
714 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
715 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
716 // <= 2-socket invariant tsc support. EX versions are usually used
717 // in > 2-socket systems and likely don't synchronize tscs at
718 // initialization.
719 // Code that uses tsc values must be prepared for them to arbitrarily
720 // jump forward or backward.
721 return true;
722 }
723 }
724 return false;
725 }
726
727 // AMD features
728 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
729 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
730 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
731 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
732
733 static bool is_amd_Barcelona() { return is_amd() &&
734 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
735
736 // Intel and AMD newer cores support fast timestamps well
737 static bool supports_tscinv_bit() {
738 return (_cpuFeatures & CPU_TSCINV) != 0;
739 }
740 static bool supports_tscinv() {
741 return supports_tscinv_bit() &&
742 ( (is_amd() && !is_amd_Barcelona()) ||
743 is_intel_tsc_synched_at_init() );
744 }
745
746 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
747 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
748 supports_sse3() && _model != 0x1C; }
749
750 static bool supports_compare_and_exchange() { return true; }
751
752 static const char* cpu_features() { return _features_str; }
753
754 static intx allocate_prefetch_distance() {
755 // This method should be called before allocate_prefetch_style().
756 //
757 // Hardware prefetching (distance/size in bytes):
758 // Pentium 3 - 64 / 32
759 // Pentium 4 - 256 / 128
760 // Athlon - 64 / 32 ????
761 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
762 // Core - 128 / 64
763 //
764 // Software prefetching (distance in bytes / instruction with best score):
765 // Pentium 3 - 128 / prefetchnta
766 // Pentium 4 - 512 / prefetchnta
767 // Athlon - 128 / prefetchnta
768 // Opteron - 256 / prefetchnta
769 // Core - 256 / prefetchnta
770 // It will be used only when AllocatePrefetchStyle > 0
771
772 intx count = AllocatePrefetchDistance;
773 if (count < 0) { // default ?
774 if (is_amd()) { // AMD
775 if (supports_sse2())
776 count = 256; // Opteron
777 else
778 count = 128; // Athlon
779 } else { // Intel
780 if (supports_sse2())
781 if (cpu_family() == 6) {
782 count = 256; // Pentium M, Core, Core2
783 } else {
784 count = 512; // Pentium 4
785 }
786 else
787 count = 128; // Pentium 3 (and all other old CPUs)
788 }
789 }
790 return count;
791 }
792 static intx allocate_prefetch_style() {
793 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
794 // Return 0 if AllocatePrefetchDistance was not defined.
795 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
796 }
797
798 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
799 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
800 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
801 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
802
803 // gc copy/scan is disabled if prefetchw isn't supported, because
804 // Prefetch::write emits an inlined prefetchw on Linux.
805 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
806 // The used prefetcht0 instruction works for both amd64 and em64t.
807 static intx prefetch_copy_interval_in_bytes() {
808 intx interval = PrefetchCopyIntervalInBytes;
809 return interval >= 0 ? interval : 576;
810 }
811 static intx prefetch_scan_interval_in_bytes() {
812 intx interval = PrefetchScanIntervalInBytes;
813 return interval >= 0 ? interval : 576;
814 }
815 static intx prefetch_fields_ahead() {
816 intx count = PrefetchFieldsAhead;
817 return count >= 0 ? count : 1;
818 }
819 };
820
821 #endif // CPU_X86_VM_VM_VERSION_X86_HPP