src/share/vm/adlc/formssel.cpp
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src/share/vm/adlc/formssel.cpp

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rev 8344 : 8076276: Add support for AVX512
Reviewed-by: kvn, roland
Contributed-by: michael.c.berg@intel.com

*** 3917,3926 **** --- 3917,3927 ---- strcmp(opType,"RegD")==0 || strcmp(opType,"VecS")==0 || strcmp(opType,"VecD")==0 || strcmp(opType,"VecX")==0 || strcmp(opType,"VecY")==0 || + strcmp(opType,"VecZ")==0 || strcmp(opType,"Reg" )==0) ) { return 1; } } return 0;
*** 4046,4055 **** --- 4047,4057 ---- strcmp(opType,"AddReductionVI")==0 || strcmp(opType,"AddReductionVL")==0 || strcmp(opType,"AddReductionVF")==0 || strcmp(opType,"AddReductionVD")==0 || strcmp(opType,"MulReductionVI")==0 || + strcmp(opType,"MulReductionVL")==0 || strcmp(opType,"MulReductionVF")==0 || strcmp(opType,"MulReductionVD")==0 || 0 /* 0 to line up columns nicely */ ) return 1; }
*** 4137,4152 **** bool MatchRule::is_vector() const { static const char *vector_list[] = { "AddVB","AddVS","AddVI","AddVL","AddVF","AddVD", "SubVB","SubVS","SubVI","SubVL","SubVF","SubVD", ! "MulVS","MulVI","MulVF","MulVD", "DivVF","DivVD", "AndV" ,"XorV" ,"OrV", "AddReductionVI", "AddReductionVL", "AddReductionVF", "AddReductionVD", ! "MulReductionVI", "MulReductionVF", "MulReductionVD", "LShiftCntV","RShiftCntV", "LShiftVB","LShiftVS","LShiftVI","LShiftVL", "RShiftVB","RShiftVS","RShiftVI","RShiftVL", "URShiftVB","URShiftVS","URShiftVI","URShiftVL", --- 4139,4154 ---- bool MatchRule::is_vector() const { static const char *vector_list[] = { "AddVB","AddVS","AddVI","AddVL","AddVF","AddVD", "SubVB","SubVS","SubVI","SubVL","SubVF","SubVD", ! "MulVS","MulVI","MulVL","MulVF","MulVD", "DivVF","DivVD", "AndV" ,"XorV" ,"OrV", "AddReductionVI", "AddReductionVL", "AddReductionVF", "AddReductionVD", ! "MulReductionVI", "MulReductionVL", "MulReductionVF", "MulReductionVD", "LShiftCntV","RShiftCntV", "LShiftVB","LShiftVS","LShiftVI","LShiftVL", "RShiftVB","RShiftVS","RShiftVI","RShiftVL", "URShiftVB","URShiftVS","URShiftVI","URShiftVL",
src/share/vm/adlc/formssel.cpp
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