1 /*
   2  * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CFGPrinter.hpp"
  27 #include "c1/c1_CodeStubs.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_FrameMap.hpp"
  30 #include "c1/c1_IR.hpp"
  31 #include "c1/c1_LIRGenerator.hpp"
  32 #include "c1/c1_LinearScan.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "code/vmreg.inline.hpp"
  35 #include "utilities/bitMap.inline.hpp"
  36 
  37 #ifndef PRODUCT
  38 
  39   static LinearScanStatistic _stat_before_alloc;
  40   static LinearScanStatistic _stat_after_asign;
  41   static LinearScanStatistic _stat_final;
  42 
  43   static LinearScanTimers _total_timer;
  44 
  45   // helper macro for short definition of timer
  46   #define TIME_LINEAR_SCAN(timer_name)  TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
  47 
  48   // helper macro for short definition of trace-output inside code
  49   #define TRACE_LINEAR_SCAN(level, code)       \
  50     if (TraceLinearScanLevel >= level) {       \
  51       code;                                    \
  52     }
  53 
  54 #else
  55 
  56   #define TIME_LINEAR_SCAN(timer_name)
  57   #define TRACE_LINEAR_SCAN(level, code)
  58 
  59 #endif
  60 
  61 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
  62 #ifdef _LP64
  63 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2,  1, 2, 1, -1};
  64 #else
  65 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
  66 #endif
  67 
  68 
  69 // Implementation of LinearScan
  70 
  71 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
  72  : _compilation(ir->compilation())
  73  , _ir(ir)
  74  , _gen(gen)
  75  , _frame_map(frame_map)
  76  , _num_virtual_regs(gen->max_virtual_register_number())
  77  , _has_fpu_registers(false)
  78  , _num_calls(-1)
  79  , _max_spills(0)
  80  , _unused_spill_slot(-1)
  81  , _intervals(0)   // initialized later with correct length
  82  , _new_intervals_from_allocation(new IntervalList())
  83  , _sorted_intervals(NULL)
  84  , _needs_full_resort(false)
  85  , _lir_ops(0)     // initialized later with correct length
  86  , _block_of_op(0) // initialized later with correct length
  87  , _has_info(0)
  88  , _has_call(0)
  89  , _scope_value_cache(0) // initialized later with correct length
  90  , _interval_in_loop(0, 0) // initialized later with correct length
  91  , _cached_blocks(*ir->linear_scan_order())
  92 #ifdef X86
  93  , _fpu_stack_allocator(NULL)
  94 #endif
  95 {
  96   assert(this->ir() != NULL,          "check if valid");
  97   assert(this->compilation() != NULL, "check if valid");
  98   assert(this->gen() != NULL,         "check if valid");
  99   assert(this->frame_map() != NULL,   "check if valid");
 100 }
 101 
 102 
 103 // ********** functions for converting LIR-Operands to register numbers
 104 //
 105 // Emulate a flat register file comprising physical integer registers,
 106 // physical floating-point registers and virtual registers, in that order.
 107 // Virtual registers already have appropriate numbers, since V0 is
 108 // the number of physical registers.
 109 // Returns -1 for hi word if opr is a single word operand.
 110 //
 111 // Note: the inverse operation (calculating an operand for register numbers)
 112 //       is done in calc_operand_for_interval()
 113 
 114 int LinearScan::reg_num(LIR_Opr opr) {
 115   assert(opr->is_register(), "should not call this otherwise");
 116 
 117   if (opr->is_virtual_register()) {
 118     assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
 119     return opr->vreg_number();
 120   } else if (opr->is_single_cpu()) {
 121     return opr->cpu_regnr();
 122   } else if (opr->is_double_cpu()) {
 123     return opr->cpu_regnrLo();
 124 #ifdef X86
 125   } else if (opr->is_single_xmm()) {
 126     return opr->fpu_regnr() + pd_first_xmm_reg;
 127   } else if (opr->is_double_xmm()) {
 128     return opr->fpu_regnrLo() + pd_first_xmm_reg;
 129 #endif
 130   } else if (opr->is_single_fpu()) {
 131     return opr->fpu_regnr() + pd_first_fpu_reg;
 132   } else if (opr->is_double_fpu()) {
 133     return opr->fpu_regnrLo() + pd_first_fpu_reg;
 134   } else {
 135     ShouldNotReachHere();
 136     return -1;
 137   }
 138 }
 139 
 140 int LinearScan::reg_numHi(LIR_Opr opr) {
 141   assert(opr->is_register(), "should not call this otherwise");
 142 
 143   if (opr->is_virtual_register()) {
 144     return -1;
 145   } else if (opr->is_single_cpu()) {
 146     return -1;
 147   } else if (opr->is_double_cpu()) {
 148     return opr->cpu_regnrHi();
 149 #ifdef X86
 150   } else if (opr->is_single_xmm()) {
 151     return -1;
 152   } else if (opr->is_double_xmm()) {
 153     return -1;
 154 #endif
 155   } else if (opr->is_single_fpu()) {
 156     return -1;
 157   } else if (opr->is_double_fpu()) {
 158     return opr->fpu_regnrHi() + pd_first_fpu_reg;
 159   } else {
 160     ShouldNotReachHere();
 161     return -1;
 162   }
 163 }
 164 
 165 
 166 // ********** functions for classification of intervals
 167 
 168 bool LinearScan::is_precolored_interval(const Interval* i) {
 169   return i->reg_num() < LinearScan::nof_regs;
 170 }
 171 
 172 bool LinearScan::is_virtual_interval(const Interval* i) {
 173   return i->reg_num() >= LIR_OprDesc::vreg_base;
 174 }
 175 
 176 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
 177   return i->reg_num() < LinearScan::nof_cpu_regs;
 178 }
 179 
 180 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
 181 #if defined(__SOFTFP__) || defined(E500V2)
 182   return i->reg_num() >= LIR_OprDesc::vreg_base;
 183 #else
 184   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
 185 #endif // __SOFTFP__ or E500V2
 186 }
 187 
 188 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
 189   return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
 190 }
 191 
 192 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
 193 #if defined(__SOFTFP__) || defined(E500V2)
 194   return false;
 195 #else
 196   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
 197 #endif // __SOFTFP__ or E500V2
 198 }
 199 
 200 bool LinearScan::is_in_fpu_register(const Interval* i) {
 201   // fixed intervals not needed for FPU stack allocation
 202   return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
 203 }
 204 
 205 bool LinearScan::is_oop_interval(const Interval* i) {
 206   // fixed intervals never contain oops
 207   return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
 208 }
 209 
 210 
 211 // ********** General helper functions
 212 
 213 // compute next unused stack index that can be used for spilling
 214 int LinearScan::allocate_spill_slot(bool double_word) {
 215   int spill_slot;
 216   if (double_word) {
 217     if ((_max_spills & 1) == 1) {
 218       // alignment of double-word values
 219       // the hole because of the alignment is filled with the next single-word value
 220       assert(_unused_spill_slot == -1, "wasting a spill slot");
 221       _unused_spill_slot = _max_spills;
 222       _max_spills++;
 223     }
 224     spill_slot = _max_spills;
 225     _max_spills += 2;
 226 
 227   } else if (_unused_spill_slot != -1) {
 228     // re-use hole that was the result of a previous double-word alignment
 229     spill_slot = _unused_spill_slot;
 230     _unused_spill_slot = -1;
 231 
 232   } else {
 233     spill_slot = _max_spills;
 234     _max_spills++;
 235   }
 236 
 237   int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
 238 
 239   // the class OopMapValue uses only 11 bits for storing the name of the
 240   // oop location. So a stack slot bigger than 2^11 leads to an overflow
 241   // that is not reported in product builds. Prevent this by checking the
 242   // spill slot here (altough this value and the later used location name
 243   // are slightly different)
 244   if (result > 2000) {
 245     bailout("too many stack slots used");
 246   }
 247 
 248   return result;
 249 }
 250 
 251 void LinearScan::assign_spill_slot(Interval* it) {
 252   // assign the canonical spill slot of the parent (if a part of the interval
 253   // is already spilled) or allocate a new spill slot
 254   if (it->canonical_spill_slot() >= 0) {
 255     it->assign_reg(it->canonical_spill_slot());
 256   } else {
 257     int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
 258     it->set_canonical_spill_slot(spill);
 259     it->assign_reg(spill);
 260   }
 261 }
 262 
 263 void LinearScan::propagate_spill_slots() {
 264   if (!frame_map()->finalize_frame(max_spills())) {
 265     bailout("frame too large");
 266   }
 267 }
 268 
 269 // create a new interval with a predefined reg_num
 270 // (only used for parent intervals that are created during the building phase)
 271 Interval* LinearScan::create_interval(int reg_num) {
 272   assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
 273 
 274   Interval* interval = new Interval(reg_num);
 275   _intervals.at_put(reg_num, interval);
 276 
 277   // assign register number for precolored intervals
 278   if (reg_num < LIR_OprDesc::vreg_base) {
 279     interval->assign_reg(reg_num);
 280   }
 281   return interval;
 282 }
 283 
 284 // assign a new reg_num to the interval and append it to the list of intervals
 285 // (only used for child intervals that are created during register allocation)
 286 void LinearScan::append_interval(Interval* it) {
 287   it->set_reg_num(_intervals.length());
 288   _intervals.append(it);
 289   _new_intervals_from_allocation->append(it);
 290 }
 291 
 292 // copy the vreg-flags if an interval is split
 293 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
 294   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
 295     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
 296   }
 297   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
 298     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
 299   }
 300 
 301   // Note: do not copy the must_start_in_memory flag because it is not necessary for child
 302   //       intervals (only the very beginning of the interval must be in memory)
 303 }
 304 
 305 
 306 // ********** spill move optimization
 307 // eliminate moves from register to stack if stack slot is known to be correct
 308 
 309 // called during building of intervals
 310 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
 311   assert(interval->is_split_parent(), "can only be called for split parents");
 312 
 313   switch (interval->spill_state()) {
 314     case noDefinitionFound:
 315       assert(interval->spill_definition_pos() == -1, "must no be set before");
 316       interval->set_spill_definition_pos(def_pos);
 317       interval->set_spill_state(oneDefinitionFound);
 318       break;
 319 
 320     case oneDefinitionFound:
 321       assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
 322       if (def_pos < interval->spill_definition_pos() - 2) {
 323         // second definition found, so no spill optimization possible for this interval
 324         interval->set_spill_state(noOptimization);
 325       } else {
 326         // two consecutive definitions (because of two-operand LIR form)
 327         assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
 328       }
 329       break;
 330 
 331     case noOptimization:
 332       // nothing to do
 333       break;
 334 
 335     default:
 336       assert(false, "other states not allowed at this time");
 337   }
 338 }
 339 
 340 // called during register allocation
 341 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
 342   switch (interval->spill_state()) {
 343     case oneDefinitionFound: {
 344       int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
 345       int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
 346 
 347       if (def_loop_depth < spill_loop_depth) {
 348         // the loop depth of the spilling position is higher then the loop depth
 349         // at the definition of the interval -> move write to memory out of loop
 350         // by storing at definitin of the interval
 351         interval->set_spill_state(storeAtDefinition);
 352       } else {
 353         // the interval is currently spilled only once, so for now there is no
 354         // reason to store the interval at the definition
 355         interval->set_spill_state(oneMoveInserted);
 356       }
 357       break;
 358     }
 359 
 360     case oneMoveInserted: {
 361       // the interval is spilled more then once, so it is better to store it to
 362       // memory at the definition
 363       interval->set_spill_state(storeAtDefinition);
 364       break;
 365     }
 366 
 367     case storeAtDefinition:
 368     case startInMemory:
 369     case noOptimization:
 370     case noDefinitionFound:
 371       // nothing to do
 372       break;
 373 
 374     default:
 375       assert(false, "other states not allowed at this time");
 376   }
 377 }
 378 
 379 
 380 bool LinearScan::must_store_at_definition(const Interval* i) {
 381   return i->is_split_parent() && i->spill_state() == storeAtDefinition;
 382 }
 383 
 384 // called once before asignment of register numbers
 385 void LinearScan::eliminate_spill_moves() {
 386   TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
 387   TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
 388 
 389   // collect all intervals that must be stored after their definion.
 390   // the list is sorted by Interval::spill_definition_pos
 391   Interval* interval;
 392   Interval* temp_list;
 393   create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
 394 
 395 #ifdef ASSERT
 396   Interval* prev = NULL;
 397   Interval* temp = interval;
 398   while (temp != Interval::end()) {
 399     assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
 400     if (prev != NULL) {
 401       assert(temp->from() >= prev->from(), "intervals not sorted");
 402       assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
 403     }
 404 
 405     assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
 406     assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
 407     assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
 408 
 409     TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
 410 
 411     temp = temp->next();
 412   }
 413 #endif
 414 
 415   LIR_InsertionBuffer insertion_buffer;
 416   int num_blocks = block_count();
 417   for (int i = 0; i < num_blocks; i++) {
 418     BlockBegin* block = block_at(i);
 419     LIR_OpList* instructions = block->lir()->instructions_list();
 420     int         num_inst = instructions->length();
 421     bool        has_new = false;
 422 
 423     // iterate all instructions of the block. skip the first because it is always a label
 424     for (int j = 1; j < num_inst; j++) {
 425       LIR_Op* op = instructions->at(j);
 426       int op_id = op->id();
 427 
 428       if (op_id == -1) {
 429         // remove move from register to stack if the stack slot is guaranteed to be correct.
 430         // only moves that have been inserted by LinearScan can be removed.
 431         assert(op->code() == lir_move, "only moves can have a op_id of -1");
 432         assert(op->as_Op1() != NULL, "move must be LIR_Op1");
 433         assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
 434 
 435         LIR_Op1* op1 = (LIR_Op1*)op;
 436         Interval* interval = interval_at(op1->result_opr()->vreg_number());
 437 
 438         if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
 439           // move target is a stack slot that is always correct, so eliminate instruction
 440           TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
 441           instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
 442         }
 443 
 444       } else {
 445         // insert move from register to stack just after the beginning of the interval
 446         assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
 447         assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
 448 
 449         while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
 450           if (!has_new) {
 451             // prepare insertion buffer (appended when all instructions of the block are processed)
 452             insertion_buffer.init(block->lir());
 453             has_new = true;
 454           }
 455 
 456           LIR_Opr from_opr = operand_for_interval(interval);
 457           LIR_Opr to_opr = canonical_spill_opr(interval);
 458           assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
 459           assert(to_opr->is_stack(), "to operand must be a stack slot");
 460 
 461           insertion_buffer.move(j, from_opr, to_opr);
 462           TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
 463 
 464           interval = interval->next();
 465         }
 466       }
 467     } // end of instruction iteration
 468 
 469     if (has_new) {
 470       block->lir()->append(&insertion_buffer);
 471     }
 472   } // end of block iteration
 473 
 474   assert(interval == Interval::end(), "missed an interval");
 475 }
 476 
 477 
 478 // ********** Phase 1: number all instructions in all blocks
 479 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
 480 
 481 void LinearScan::number_instructions() {
 482   {
 483     // dummy-timer to measure the cost of the timer itself
 484     // (this time is then subtracted from all other timers to get the real value)
 485     TIME_LINEAR_SCAN(timer_do_nothing);
 486   }
 487   TIME_LINEAR_SCAN(timer_number_instructions);
 488 
 489   // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
 490   int num_blocks = block_count();
 491   int num_instructions = 0;
 492   int i;
 493   for (i = 0; i < num_blocks; i++) {
 494     num_instructions += block_at(i)->lir()->instructions_list()->length();
 495   }
 496 
 497   // initialize with correct length
 498   _lir_ops = LIR_OpArray(num_instructions);
 499   _block_of_op = BlockBeginArray(num_instructions);
 500 
 501   int op_id = 0;
 502   int idx = 0;
 503 
 504   for (i = 0; i < num_blocks; i++) {
 505     BlockBegin* block = block_at(i);
 506     block->set_first_lir_instruction_id(op_id);
 507     LIR_OpList* instructions = block->lir()->instructions_list();
 508 
 509     int num_inst = instructions->length();
 510     for (int j = 0; j < num_inst; j++) {
 511       LIR_Op* op = instructions->at(j);
 512       op->set_id(op_id);
 513 
 514       _lir_ops.at_put(idx, op);
 515       _block_of_op.at_put(idx, block);
 516       assert(lir_op_with_id(op_id) == op, "must match");
 517 
 518       idx++;
 519       op_id += 2; // numbering of lir_ops by two
 520     }
 521     block->set_last_lir_instruction_id(op_id - 2);
 522   }
 523   assert(idx == num_instructions, "must match");
 524   assert(idx * 2 == op_id, "must match");
 525 
 526   _has_call = BitMap(num_instructions); _has_call.clear();
 527   _has_info = BitMap(num_instructions); _has_info.clear();
 528 }
 529 
 530 
 531 // ********** Phase 2: compute local live sets separately for each block
 532 // (sets live_gen and live_kill for each block)
 533 
 534 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
 535   LIR_Opr opr = value->operand();
 536   Constant* con = value->as_Constant();
 537 
 538   // check some asumptions about debug information
 539   assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
 540   assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
 541   assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
 542 
 543   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 544     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 545     int reg = opr->vreg_number();
 546     if (!live_kill.at(reg)) {
 547       live_gen.set_bit(reg);
 548       TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
 549     }
 550   }
 551 }
 552 
 553 
 554 void LinearScan::compute_local_live_sets() {
 555   TIME_LINEAR_SCAN(timer_compute_local_live_sets);
 556 
 557   int  num_blocks = block_count();
 558   int  live_size = live_set_size();
 559   bool local_has_fpu_registers = false;
 560   int  local_num_calls = 0;
 561   LIR_OpVisitState visitor;
 562 
 563   BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
 564   local_interval_in_loop.clear();
 565 
 566   // iterate all blocks
 567   for (int i = 0; i < num_blocks; i++) {
 568     BlockBegin* block = block_at(i);
 569 
 570     BitMap live_gen(live_size);  live_gen.clear();
 571     BitMap live_kill(live_size); live_kill.clear();
 572 
 573     if (block->is_set(BlockBegin::exception_entry_flag)) {
 574       // Phi functions at the begin of an exception handler are
 575       // implicitly defined (= killed) at the beginning of the block.
 576       for_each_phi_fun(block, phi,
 577         live_kill.set_bit(phi->operand()->vreg_number())
 578       );
 579     }
 580 
 581     LIR_OpList* instructions = block->lir()->instructions_list();
 582     int num_inst = instructions->length();
 583 
 584     // iterate all instructions of the block. skip the first because it is always a label
 585     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
 586     for (int j = 1; j < num_inst; j++) {
 587       LIR_Op* op = instructions->at(j);
 588 
 589       // visit operation to collect all operands
 590       visitor.visit(op);
 591 
 592       if (visitor.has_call()) {
 593         _has_call.set_bit(op->id() >> 1);
 594         local_num_calls++;
 595       }
 596       if (visitor.info_count() > 0) {
 597         _has_info.set_bit(op->id() >> 1);
 598       }
 599 
 600       // iterate input operands of instruction
 601       int k, n, reg;
 602       n = visitor.opr_count(LIR_OpVisitState::inputMode);
 603       for (k = 0; k < n; k++) {
 604         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
 605         assert(opr->is_register(), "visitor should only return register operands");
 606 
 607         if (opr->is_virtual_register()) {
 608           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 609           reg = opr->vreg_number();
 610           if (!live_kill.at(reg)) {
 611             live_gen.set_bit(reg);
 612             TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for register %d at instruction %d", reg, op->id()));
 613           }
 614           if (block->loop_index() >= 0) {
 615             local_interval_in_loop.set_bit(reg, block->loop_index());
 616           }
 617           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 618         }
 619 
 620 #ifdef ASSERT
 621         // fixed intervals are never live at block boundaries, so
 622         // they need not be processed in live sets.
 623         // this is checked by these assertions to be sure about it.
 624         // the entry block may have incoming values in registers, which is ok.
 625         if (!opr->is_virtual_register() && block != ir()->start()) {
 626           reg = reg_num(opr);
 627           if (is_processed_reg_num(reg)) {
 628             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 629           }
 630           reg = reg_numHi(opr);
 631           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 632             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 633           }
 634         }
 635 #endif
 636       }
 637 
 638       // Add uses of live locals from interpreter's point of view for proper debug information generation
 639       n = visitor.info_count();
 640       for (k = 0; k < n; k++) {
 641         CodeEmitInfo* info = visitor.info_at(k);
 642         ValueStack* stack = info->stack();
 643         for_each_state_value(stack, value,
 644           set_live_gen_kill(value, op, live_gen, live_kill)
 645         );
 646       }
 647 
 648       // iterate temp operands of instruction
 649       n = visitor.opr_count(LIR_OpVisitState::tempMode);
 650       for (k = 0; k < n; k++) {
 651         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
 652         assert(opr->is_register(), "visitor should only return register operands");
 653 
 654         if (opr->is_virtual_register()) {
 655           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 656           reg = opr->vreg_number();
 657           live_kill.set_bit(reg);
 658           if (block->loop_index() >= 0) {
 659             local_interval_in_loop.set_bit(reg, block->loop_index());
 660           }
 661           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 662         }
 663 
 664 #ifdef ASSERT
 665         // fixed intervals are never live at block boundaries, so
 666         // they need not be processed in live sets
 667         // process them only in debug mode so that this can be checked
 668         if (!opr->is_virtual_register()) {
 669           reg = reg_num(opr);
 670           if (is_processed_reg_num(reg)) {
 671             live_kill.set_bit(reg_num(opr));
 672           }
 673           reg = reg_numHi(opr);
 674           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 675             live_kill.set_bit(reg);
 676           }
 677         }
 678 #endif
 679       }
 680 
 681       // iterate output operands of instruction
 682       n = visitor.opr_count(LIR_OpVisitState::outputMode);
 683       for (k = 0; k < n; k++) {
 684         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
 685         assert(opr->is_register(), "visitor should only return register operands");
 686 
 687         if (opr->is_virtual_register()) {
 688           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 689           reg = opr->vreg_number();
 690           live_kill.set_bit(reg);
 691           if (block->loop_index() >= 0) {
 692             local_interval_in_loop.set_bit(reg, block->loop_index());
 693           }
 694           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 695         }
 696 
 697 #ifdef ASSERT
 698         // fixed intervals are never live at block boundaries, so
 699         // they need not be processed in live sets
 700         // process them only in debug mode so that this can be checked
 701         if (!opr->is_virtual_register()) {
 702           reg = reg_num(opr);
 703           if (is_processed_reg_num(reg)) {
 704             live_kill.set_bit(reg_num(opr));
 705           }
 706           reg = reg_numHi(opr);
 707           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 708             live_kill.set_bit(reg);
 709           }
 710         }
 711 #endif
 712       }
 713     } // end of instruction iteration
 714 
 715     block->set_live_gen (live_gen);
 716     block->set_live_kill(live_kill);
 717     block->set_live_in  (BitMap(live_size)); block->live_in().clear();
 718     block->set_live_out (BitMap(live_size)); block->live_out().clear();
 719 
 720     TRACE_LINEAR_SCAN(4, tty->print("live_gen  B%d ", block->block_id()); print_bitmap(block->live_gen()));
 721     TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
 722   } // end of block iteration
 723 
 724   // propagate local calculated information into LinearScan object
 725   _has_fpu_registers = local_has_fpu_registers;
 726   compilation()->set_has_fpu_code(local_has_fpu_registers);
 727 
 728   _num_calls = local_num_calls;
 729   _interval_in_loop = local_interval_in_loop;
 730 }
 731 
 732 
 733 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
 734 // (sets live_in and live_out for each block)
 735 
 736 void LinearScan::compute_global_live_sets() {
 737   TIME_LINEAR_SCAN(timer_compute_global_live_sets);
 738 
 739   int  num_blocks = block_count();
 740   bool change_occurred;
 741   bool change_occurred_in_block;
 742   int  iteration_count = 0;
 743   BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations
 744 
 745   // Perform a backward dataflow analysis to compute live_out and live_in for each block.
 746   // The loop is executed until a fixpoint is reached (no changes in an iteration)
 747   // Exception handlers must be processed because not all live values are
 748   // present in the state array, e.g. because of global value numbering
 749   do {
 750     change_occurred = false;
 751 
 752     // iterate all blocks in reverse order
 753     for (int i = num_blocks - 1; i >= 0; i--) {
 754       BlockBegin* block = block_at(i);
 755 
 756       change_occurred_in_block = false;
 757 
 758       // live_out(block) is the union of live_in(sux), for successors sux of block
 759       int n = block->number_of_sux();
 760       int e = block->number_of_exception_handlers();
 761       if (n + e > 0) {
 762         // block has successors
 763         if (n > 0) {
 764           live_out.set_from(block->sux_at(0)->live_in());
 765           for (int j = 1; j < n; j++) {
 766             live_out.set_union(block->sux_at(j)->live_in());
 767           }
 768         } else {
 769           live_out.clear();
 770         }
 771         for (int j = 0; j < e; j++) {
 772           live_out.set_union(block->exception_handler_at(j)->live_in());
 773         }
 774 
 775         if (!block->live_out().is_same(live_out)) {
 776           // A change occurred.  Swap the old and new live out sets to avoid copying.
 777           BitMap temp = block->live_out();
 778           block->set_live_out(live_out);
 779           live_out = temp;
 780 
 781           change_occurred = true;
 782           change_occurred_in_block = true;
 783         }
 784       }
 785 
 786       if (iteration_count == 0 || change_occurred_in_block) {
 787         // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
 788         // note: live_in has to be computed only in first iteration or if live_out has changed!
 789         BitMap live_in = block->live_in();
 790         live_in.set_from(block->live_out());
 791         live_in.set_difference(block->live_kill());
 792         live_in.set_union(block->live_gen());
 793       }
 794 
 795 #ifndef PRODUCT
 796       if (TraceLinearScanLevel >= 4) {
 797         char c = ' ';
 798         if (iteration_count == 0 || change_occurred_in_block) {
 799           c = '*';
 800         }
 801         tty->print("(%d) live_in%c  B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
 802         tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
 803       }
 804 #endif
 805     }
 806     iteration_count++;
 807 
 808     if (change_occurred && iteration_count > 50) {
 809       BAILOUT("too many iterations in compute_global_live_sets");
 810     }
 811   } while (change_occurred);
 812 
 813 
 814 #ifdef ASSERT
 815   // check that fixed intervals are not live at block boundaries
 816   // (live set must be empty at fixed intervals)
 817   for (int i = 0; i < num_blocks; i++) {
 818     BlockBegin* block = block_at(i);
 819     for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
 820       assert(block->live_in().at(j)  == false, "live_in  set of fixed register must be empty");
 821       assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
 822       assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
 823     }
 824   }
 825 #endif
 826 
 827   // check that the live_in set of the first block is empty
 828   BitMap live_in_args(ir()->start()->live_in().size());
 829   live_in_args.clear();
 830   if (!ir()->start()->live_in().is_same(live_in_args)) {
 831 #ifdef ASSERT
 832     tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
 833     tty->print_cr("affected registers:");
 834     print_bitmap(ir()->start()->live_in());
 835 
 836     // print some additional information to simplify debugging
 837     for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
 838       if (ir()->start()->live_in().at(i)) {
 839         Instruction* instr = gen()->instruction_for_vreg(i);
 840         tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
 841 
 842         for (int j = 0; j < num_blocks; j++) {
 843           BlockBegin* block = block_at(j);
 844           if (block->live_gen().at(i)) {
 845             tty->print_cr("  used in block B%d", block->block_id());
 846           }
 847           if (block->live_kill().at(i)) {
 848             tty->print_cr("  defined in block B%d", block->block_id());
 849           }
 850         }
 851       }
 852     }
 853 
 854 #endif
 855     // when this fails, virtual registers are used before they are defined.
 856     assert(false, "live_in set of first block must be empty");
 857     // bailout of if this occurs in product mode.
 858     bailout("live_in set of first block not empty");
 859   }
 860 }
 861 
 862 
 863 // ********** Phase 4: build intervals
 864 // (fills the list _intervals)
 865 
 866 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
 867   assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
 868   LIR_Opr opr = value->operand();
 869   Constant* con = value->as_Constant();
 870 
 871   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 872     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 873     add_use(opr, from, to, use_kind);
 874   }
 875 }
 876 
 877 
 878 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
 879   TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
 880   assert(opr->is_register(), "should not be called otherwise");
 881 
 882   if (opr->is_virtual_register()) {
 883     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 884     add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
 885 
 886   } else {
 887     int reg = reg_num(opr);
 888     if (is_processed_reg_num(reg)) {
 889       add_def(reg, def_pos, use_kind, opr->type_register());
 890     }
 891     reg = reg_numHi(opr);
 892     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 893       add_def(reg, def_pos, use_kind, opr->type_register());
 894     }
 895   }
 896 }
 897 
 898 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
 899   TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
 900   assert(opr->is_register(), "should not be called otherwise");
 901 
 902   if (opr->is_virtual_register()) {
 903     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 904     add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
 905 
 906   } else {
 907     int reg = reg_num(opr);
 908     if (is_processed_reg_num(reg)) {
 909       add_use(reg, from, to, use_kind, opr->type_register());
 910     }
 911     reg = reg_numHi(opr);
 912     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 913       add_use(reg, from, to, use_kind, opr->type_register());
 914     }
 915   }
 916 }
 917 
 918 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
 919   TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
 920   assert(opr->is_register(), "should not be called otherwise");
 921 
 922   if (opr->is_virtual_register()) {
 923     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 924     add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
 925 
 926   } else {
 927     int reg = reg_num(opr);
 928     if (is_processed_reg_num(reg)) {
 929       add_temp(reg, temp_pos, use_kind, opr->type_register());
 930     }
 931     reg = reg_numHi(opr);
 932     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 933       add_temp(reg, temp_pos, use_kind, opr->type_register());
 934     }
 935   }
 936 }
 937 
 938 
 939 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
 940   Interval* interval = interval_at(reg_num);
 941   if (interval != NULL) {
 942     assert(interval->reg_num() == reg_num, "wrong interval");
 943 
 944     if (type != T_ILLEGAL) {
 945       interval->set_type(type);
 946     }
 947 
 948     Range* r = interval->first();
 949     if (r->from() <= def_pos) {
 950       // Update the starting point (when a range is first created for a use, its
 951       // start is the beginning of the current block until a def is encountered.)
 952       r->set_from(def_pos);
 953       interval->add_use_pos(def_pos, use_kind);
 954 
 955     } else {
 956       // Dead value - make vacuous interval
 957       // also add use_kind for dead intervals
 958       interval->add_range(def_pos, def_pos + 1);
 959       interval->add_use_pos(def_pos, use_kind);
 960       TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
 961     }
 962 
 963   } else {
 964     // Dead value - make vacuous interval
 965     // also add use_kind for dead intervals
 966     interval = create_interval(reg_num);
 967     if (type != T_ILLEGAL) {
 968       interval->set_type(type);
 969     }
 970 
 971     interval->add_range(def_pos, def_pos + 1);
 972     interval->add_use_pos(def_pos, use_kind);
 973     TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
 974   }
 975 
 976   change_spill_definition_pos(interval, def_pos);
 977   if (use_kind == noUse && interval->spill_state() <= startInMemory) {
 978         // detection of method-parameters and roundfp-results
 979         // TODO: move this directly to position where use-kind is computed
 980     interval->set_spill_state(startInMemory);
 981   }
 982 }
 983 
 984 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
 985   Interval* interval = interval_at(reg_num);
 986   if (interval == NULL) {
 987     interval = create_interval(reg_num);
 988   }
 989   assert(interval->reg_num() == reg_num, "wrong interval");
 990 
 991   if (type != T_ILLEGAL) {
 992     interval->set_type(type);
 993   }
 994 
 995   interval->add_range(from, to);
 996   interval->add_use_pos(to, use_kind);
 997 }
 998 
 999 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1000   Interval* interval = interval_at(reg_num);
1001   if (interval == NULL) {
1002     interval = create_interval(reg_num);
1003   }
1004   assert(interval->reg_num() == reg_num, "wrong interval");
1005 
1006   if (type != T_ILLEGAL) {
1007     interval->set_type(type);
1008   }
1009 
1010   interval->add_range(temp_pos, temp_pos + 1);
1011   interval->add_use_pos(temp_pos, use_kind);
1012 }
1013 
1014 
1015 // the results of this functions are used for optimizing spilling and reloading
1016 // if the functions return shouldHaveRegister and the interval is spilled,
1017 // it is not reloaded to a register.
1018 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1019   if (op->code() == lir_move) {
1020     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1021     LIR_Op1* move = (LIR_Op1*)op;
1022     LIR_Opr res = move->result_opr();
1023     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1024 
1025     if (result_in_memory) {
1026       // Begin of an interval with must_start_in_memory set.
1027       // This interval will always get a stack slot first, so return noUse.
1028       return noUse;
1029 
1030     } else if (move->in_opr()->is_stack()) {
1031       // method argument (condition must be equal to handle_method_arguments)
1032       return noUse;
1033 
1034     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1035       // Move from register to register
1036       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1037         // special handling of phi-function moves inside osr-entry blocks
1038         // input operand must have a register instead of output operand (leads to better register allocation)
1039         return shouldHaveRegister;
1040       }
1041     }
1042   }
1043 
1044   if (opr->is_virtual() &&
1045       gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1046     // result is a stack-slot, so prevent immediate reloading
1047     return noUse;
1048   }
1049 
1050   // all other operands require a register
1051   return mustHaveRegister;
1052 }
1053 
1054 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1055   if (op->code() == lir_move) {
1056     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1057     LIR_Op1* move = (LIR_Op1*)op;
1058     LIR_Opr res = move->result_opr();
1059     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1060 
1061     if (result_in_memory) {
1062       // Move to an interval with must_start_in_memory set.
1063       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1064       return mustHaveRegister;
1065 
1066     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1067       // Move from register to register
1068       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1069         // special handling of phi-function moves inside osr-entry blocks
1070         // input operand must have a register instead of output operand (leads to better register allocation)
1071         return mustHaveRegister;
1072       }
1073 
1074       // The input operand is not forced to a register (moves from stack to register are allowed),
1075       // but it is faster if the input operand is in a register
1076       return shouldHaveRegister;
1077     }
1078   }
1079 
1080 
1081 #ifdef X86
1082   if (op->code() == lir_cmove) {
1083     // conditional moves can handle stack operands
1084     assert(op->result_opr()->is_register(), "result must always be in a register");
1085     return shouldHaveRegister;
1086   }
1087 
1088   // optimizations for second input operand of arithmehtic operations on Intel
1089   // this operand is allowed to be on the stack in some cases
1090   BasicType opr_type = opr->type_register();
1091   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1092     if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) {
1093       // SSE float instruction (T_DOUBLE only supported with SSE2)
1094       switch (op->code()) {
1095         case lir_cmp:
1096         case lir_add:
1097         case lir_sub:
1098         case lir_mul:
1099         case lir_div:
1100         {
1101           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1102           LIR_Op2* op2 = (LIR_Op2*)op;
1103           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1104             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1105             return shouldHaveRegister;
1106           }
1107         }
1108       }
1109     } else {
1110       // FPU stack float instruction
1111       switch (op->code()) {
1112         case lir_add:
1113         case lir_sub:
1114         case lir_mul:
1115         case lir_div:
1116         {
1117           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1118           LIR_Op2* op2 = (LIR_Op2*)op;
1119           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1120             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1121             return shouldHaveRegister;
1122           }
1123         }
1124       }
1125     }
1126     // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1127     // Since 64bit logical operations do not current support operands on stack, we have to make sure
1128     // T_OBJECT doesn't get spilled along with T_LONG.
1129   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1130     // integer instruction (note: long operands must always be in register)
1131     switch (op->code()) {
1132       case lir_cmp:
1133       case lir_add:
1134       case lir_sub:
1135       case lir_logic_and:
1136       case lir_logic_or:
1137       case lir_logic_xor:
1138       {
1139         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1140         LIR_Op2* op2 = (LIR_Op2*)op;
1141         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1142           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1143           return shouldHaveRegister;
1144         }
1145       }
1146     }
1147   }
1148 #endif // X86
1149 
1150   // all other operands require a register
1151   return mustHaveRegister;
1152 }
1153 
1154 
1155 void LinearScan::handle_method_arguments(LIR_Op* op) {
1156   // special handling for method arguments (moves from stack to virtual register):
1157   // the interval gets no register assigned, but the stack slot.
1158   // it is split before the first use by the register allocator.
1159 
1160   if (op->code() == lir_move) {
1161     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1162     LIR_Op1* move = (LIR_Op1*)op;
1163 
1164     if (move->in_opr()->is_stack()) {
1165 #ifdef ASSERT
1166       int arg_size = compilation()->method()->arg_size();
1167       LIR_Opr o = move->in_opr();
1168       if (o->is_single_stack()) {
1169         assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1170       } else if (o->is_double_stack()) {
1171         assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1172       } else {
1173         ShouldNotReachHere();
1174       }
1175 
1176       assert(move->id() > 0, "invalid id");
1177       assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1178       assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1179 
1180       TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1181 #endif
1182 
1183       Interval* interval = interval_at(reg_num(move->result_opr()));
1184 
1185       int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1186       interval->set_canonical_spill_slot(stack_slot);
1187       interval->assign_reg(stack_slot);
1188     }
1189   }
1190 }
1191 
1192 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1193   // special handling for doubleword move from memory to register:
1194   // in this case the registers of the input address and the result
1195   // registers must not overlap -> add a temp range for the input registers
1196   if (op->code() == lir_move) {
1197     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1198     LIR_Op1* move = (LIR_Op1*)op;
1199 
1200     if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1201       LIR_Address* address = move->in_opr()->as_address_ptr();
1202       if (address != NULL) {
1203         if (address->base()->is_valid()) {
1204           add_temp(address->base(), op->id(), noUse);
1205         }
1206         if (address->index()->is_valid()) {
1207           add_temp(address->index(), op->id(), noUse);
1208         }
1209       }
1210     }
1211   }
1212 }
1213 
1214 void LinearScan::add_register_hints(LIR_Op* op) {
1215   switch (op->code()) {
1216     case lir_move:      // fall through
1217     case lir_convert: {
1218       assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1219       LIR_Op1* move = (LIR_Op1*)op;
1220 
1221       LIR_Opr move_from = move->in_opr();
1222       LIR_Opr move_to = move->result_opr();
1223 
1224       if (move_to->is_register() && move_from->is_register()) {
1225         Interval* from = interval_at(reg_num(move_from));
1226         Interval* to = interval_at(reg_num(move_to));
1227         if (from != NULL && to != NULL) {
1228           to->set_register_hint(from);
1229           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1230         }
1231       }
1232       break;
1233     }
1234     case lir_cmove: {
1235       assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1236       LIR_Op2* cmove = (LIR_Op2*)op;
1237 
1238       LIR_Opr move_from = cmove->in_opr1();
1239       LIR_Opr move_to = cmove->result_opr();
1240 
1241       if (move_to->is_register() && move_from->is_register()) {
1242         Interval* from = interval_at(reg_num(move_from));
1243         Interval* to = interval_at(reg_num(move_to));
1244         if (from != NULL && to != NULL) {
1245           to->set_register_hint(from);
1246           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1247         }
1248       }
1249       break;
1250     }
1251   }
1252 }
1253 
1254 
1255 void LinearScan::build_intervals() {
1256   TIME_LINEAR_SCAN(timer_build_intervals);
1257 
1258   // initialize interval list with expected number of intervals
1259   // (32 is added to have some space for split children without having to resize the list)
1260   _intervals = IntervalList(num_virtual_regs() + 32);
1261   // initialize all slots that are used by build_intervals
1262   _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1263 
1264   // create a list with all caller-save registers (cpu, fpu, xmm)
1265   // when an instruction is a call, a temp range is created for all these registers
1266   int num_caller_save_registers = 0;
1267   int caller_save_registers[LinearScan::nof_regs];
1268 
1269   int i;
1270   for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1271     LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1272     assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1273     assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1274     caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1275   }
1276 
1277   // temp ranges for fpu registers are only created when the method has
1278   // virtual fpu operands. Otherwise no allocation for fpu registers is
1279   // perfomed and so the temp ranges would be useless
1280   if (has_fpu_registers()) {
1281 #ifdef X86
1282     if (UseSSE < 2) {
1283 #endif
1284       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1285         LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1286         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1287         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1288         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1289       }
1290 #ifdef X86
1291     }
1292     if (UseSSE > 0) {
1293       for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) {
1294         LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1295         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1296         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1297         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1298       }
1299     }
1300 #endif
1301   }
1302   assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1303 
1304 
1305   LIR_OpVisitState visitor;
1306 
1307   // iterate all blocks in reverse order
1308   for (i = block_count() - 1; i >= 0; i--) {
1309     BlockBegin* block = block_at(i);
1310     LIR_OpList* instructions = block->lir()->instructions_list();
1311     int         block_from =   block->first_lir_instruction_id();
1312     int         block_to =     block->last_lir_instruction_id();
1313 
1314     assert(block_from == instructions->at(0)->id(), "must be");
1315     assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
1316 
1317     // Update intervals for registers live at the end of this block;
1318     BitMap live = block->live_out();
1319     int size = (int)live.size();
1320     for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1321       assert(live.at(number), "should not stop here otherwise");
1322       assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1323       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1324 
1325       add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1326 
1327       // add special use positions for loop-end blocks when the
1328       // interval is used anywhere inside this loop.  It's possible
1329       // that the block was part of a non-natural loop, so it might
1330       // have an invalid loop index.
1331       if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1332           block->loop_index() != -1 &&
1333           is_interval_in_loop(number, block->loop_index())) {
1334         interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1335       }
1336     }
1337 
1338     // iterate all instructions of the block in reverse order.
1339     // skip the first instruction because it is always a label
1340     // definitions of intervals are processed before uses
1341     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1342     for (int j = instructions->length() - 1; j >= 1; j--) {
1343       LIR_Op* op = instructions->at(j);
1344       int op_id = op->id();
1345 
1346       // visit operation to collect all operands
1347       visitor.visit(op);
1348 
1349       // add a temp range for each register if operation destroys caller-save registers
1350       if (visitor.has_call()) {
1351         for (int k = 0; k < num_caller_save_registers; k++) {
1352           add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1353         }
1354         TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1355       }
1356 
1357       // Add any platform dependent temps
1358       pd_add_temps(op);
1359 
1360       // visit definitions (output and temp operands)
1361       int k, n;
1362       n = visitor.opr_count(LIR_OpVisitState::outputMode);
1363       for (k = 0; k < n; k++) {
1364         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1365         assert(opr->is_register(), "visitor should only return register operands");
1366         add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1367       }
1368 
1369       n = visitor.opr_count(LIR_OpVisitState::tempMode);
1370       for (k = 0; k < n; k++) {
1371         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1372         assert(opr->is_register(), "visitor should only return register operands");
1373         add_temp(opr, op_id, mustHaveRegister);
1374       }
1375 
1376       // visit uses (input operands)
1377       n = visitor.opr_count(LIR_OpVisitState::inputMode);
1378       for (k = 0; k < n; k++) {
1379         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1380         assert(opr->is_register(), "visitor should only return register operands");
1381         add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1382       }
1383 
1384       // Add uses of live locals from interpreter's point of view for proper
1385       // debug information generation
1386       // Treat these operands as temp values (if the life range is extended
1387       // to a call site, the value would be in a register at the call otherwise)
1388       n = visitor.info_count();
1389       for (k = 0; k < n; k++) {
1390         CodeEmitInfo* info = visitor.info_at(k);
1391         ValueStack* stack = info->stack();
1392         for_each_state_value(stack, value,
1393           add_use(value, block_from, op_id + 1, noUse);
1394         );
1395       }
1396 
1397       // special steps for some instructions (especially moves)
1398       handle_method_arguments(op);
1399       handle_doubleword_moves(op);
1400       add_register_hints(op);
1401 
1402     } // end of instruction iteration
1403   } // end of block iteration
1404 
1405 
1406   // add the range [0, 1[ to all fixed intervals
1407   // -> the register allocator need not handle unhandled fixed intervals
1408   for (int n = 0; n < LinearScan::nof_regs; n++) {
1409     Interval* interval = interval_at(n);
1410     if (interval != NULL) {
1411       interval->add_range(0, 1);
1412     }
1413   }
1414 }
1415 
1416 
1417 // ********** Phase 5: actual register allocation
1418 
1419 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1420   if (*a != NULL) {
1421     if (*b != NULL) {
1422       return (*a)->from() - (*b)->from();
1423     } else {
1424       return -1;
1425     }
1426   } else {
1427     if (*b != NULL) {
1428       return 1;
1429     } else {
1430       return 0;
1431     }
1432   }
1433 }
1434 
1435 #ifndef PRODUCT
1436 bool LinearScan::is_sorted(IntervalArray* intervals) {
1437   int from = -1;
1438   int i, j;
1439   for (i = 0; i < intervals->length(); i ++) {
1440     Interval* it = intervals->at(i);
1441     if (it != NULL) {
1442       if (from > it->from()) {
1443         assert(false, "");
1444         return false;
1445       }
1446       from = it->from();
1447     }
1448   }
1449 
1450   // check in both directions if sorted list and unsorted list contain same intervals
1451   for (i = 0; i < interval_count(); i++) {
1452     if (interval_at(i) != NULL) {
1453       int num_found = 0;
1454       for (j = 0; j < intervals->length(); j++) {
1455         if (interval_at(i) == intervals->at(j)) {
1456           num_found++;
1457         }
1458       }
1459       assert(num_found == 1, "lists do not contain same intervals");
1460     }
1461   }
1462   for (j = 0; j < intervals->length(); j++) {
1463     int num_found = 0;
1464     for (i = 0; i < interval_count(); i++) {
1465       if (interval_at(i) == intervals->at(j)) {
1466         num_found++;
1467       }
1468     }
1469     assert(num_found == 1, "lists do not contain same intervals");
1470   }
1471 
1472   return true;
1473 }
1474 #endif
1475 
1476 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1477   if (*prev != NULL) {
1478     (*prev)->set_next(interval);
1479   } else {
1480     *first = interval;
1481   }
1482   *prev = interval;
1483 }
1484 
1485 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1486   assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1487 
1488   *list1 = *list2 = Interval::end();
1489 
1490   Interval* list1_prev = NULL;
1491   Interval* list2_prev = NULL;
1492   Interval* v;
1493 
1494   const int n = _sorted_intervals->length();
1495   for (int i = 0; i < n; i++) {
1496     v = _sorted_intervals->at(i);
1497     if (v == NULL) continue;
1498 
1499     if (is_list1(v)) {
1500       add_to_list(list1, &list1_prev, v);
1501     } else if (is_list2 == NULL || is_list2(v)) {
1502       add_to_list(list2, &list2_prev, v);
1503     }
1504   }
1505 
1506   if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1507   if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1508 
1509   assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1510   assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1511 }
1512 
1513 
1514 void LinearScan::sort_intervals_before_allocation() {
1515   TIME_LINEAR_SCAN(timer_sort_intervals_before);
1516 
1517   if (_needs_full_resort) {
1518     // There is no known reason why this should occur but just in case...
1519     assert(false, "should never occur");
1520     // Re-sort existing interval list because an Interval::from() has changed
1521     _sorted_intervals->sort(interval_cmp);
1522     _needs_full_resort = false;
1523   }
1524 
1525   IntervalList* unsorted_list = &_intervals;
1526   int unsorted_len = unsorted_list->length();
1527   int sorted_len = 0;
1528   int unsorted_idx;
1529   int sorted_idx = 0;
1530   int sorted_from_max = -1;
1531 
1532   // calc number of items for sorted list (sorted list must not contain NULL values)
1533   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1534     if (unsorted_list->at(unsorted_idx) != NULL) {
1535       sorted_len++;
1536     }
1537   }
1538   IntervalArray* sorted_list = new IntervalArray(sorted_len);
1539 
1540   // special sorting algorithm: the original interval-list is almost sorted,
1541   // only some intervals are swapped. So this is much faster than a complete QuickSort
1542   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1543     Interval* cur_interval = unsorted_list->at(unsorted_idx);
1544 
1545     if (cur_interval != NULL) {
1546       int cur_from = cur_interval->from();
1547 
1548       if (sorted_from_max <= cur_from) {
1549         sorted_list->at_put(sorted_idx++, cur_interval);
1550         sorted_from_max = cur_interval->from();
1551       } else {
1552         // the asumption that the intervals are already sorted failed,
1553         // so this interval must be sorted in manually
1554         int j;
1555         for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1556           sorted_list->at_put(j + 1, sorted_list->at(j));
1557         }
1558         sorted_list->at_put(j + 1, cur_interval);
1559         sorted_idx++;
1560       }
1561     }
1562   }
1563   _sorted_intervals = sorted_list;
1564   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1565 }
1566 
1567 void LinearScan::sort_intervals_after_allocation() {
1568   TIME_LINEAR_SCAN(timer_sort_intervals_after);
1569 
1570   if (_needs_full_resort) {
1571     // Re-sort existing interval list because an Interval::from() has changed
1572     _sorted_intervals->sort(interval_cmp);
1573     _needs_full_resort = false;
1574   }
1575 
1576   IntervalArray* old_list      = _sorted_intervals;
1577   IntervalList*  new_list      = _new_intervals_from_allocation;
1578   int old_len = old_list->length();
1579   int new_len = new_list->length();
1580 
1581   if (new_len == 0) {
1582     // no intervals have been added during allocation, so sorted list is already up to date
1583     assert(is_sorted(_sorted_intervals), "intervals unsorted");
1584     return;
1585   }
1586 
1587   // conventional sort-algorithm for new intervals
1588   new_list->sort(interval_cmp);
1589 
1590   // merge old and new list (both already sorted) into one combined list
1591   IntervalArray* combined_list = new IntervalArray(old_len + new_len);
1592   int old_idx = 0;
1593   int new_idx = 0;
1594 
1595   while (old_idx + new_idx < old_len + new_len) {
1596     if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1597       combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1598       old_idx++;
1599     } else {
1600       combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1601       new_idx++;
1602     }
1603   }
1604 
1605   _sorted_intervals = combined_list;
1606   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1607 }
1608 
1609 
1610 void LinearScan::allocate_registers() {
1611   TIME_LINEAR_SCAN(timer_allocate_registers);
1612 
1613   Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1614   Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1615 
1616   // allocate cpu registers
1617   create_unhandled_lists(&precolored_cpu_intervals, &not_precolored_cpu_intervals,
1618                          is_precolored_cpu_interval, is_virtual_cpu_interval);
1619 
1620   // allocate fpu registers
1621   create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals,
1622                          is_precolored_fpu_interval, is_virtual_fpu_interval);
1623 
1624   // the fpu interval allocation cannot be moved down below with the fpu section as
1625   // the cpu_lsw.walk() changes interval positions.
1626 
1627   LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1628   cpu_lsw.walk();
1629   cpu_lsw.finish_allocation();
1630 
1631   if (has_fpu_registers()) {
1632     LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1633     fpu_lsw.walk();
1634     fpu_lsw.finish_allocation();
1635   }
1636 }
1637 
1638 
1639 // ********** Phase 6: resolve data flow
1640 // (insert moves at edges between blocks if intervals have been split)
1641 
1642 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1643 // instead of returning NULL
1644 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1645   Interval* result = interval->split_child_at_op_id(op_id, mode);
1646   if (result != NULL) {
1647     return result;
1648   }
1649 
1650   assert(false, "must find an interval, but do a clean bailout in product mode");
1651   result = new Interval(LIR_OprDesc::vreg_base);
1652   result->assign_reg(0);
1653   result->set_type(T_INT);
1654   BAILOUT_("LinearScan: interval is NULL", result);
1655 }
1656 
1657 
1658 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1659   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1660   assert(interval_at(reg_num) != NULL, "no interval found");
1661 
1662   return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1663 }
1664 
1665 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1666   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1667   assert(interval_at(reg_num) != NULL, "no interval found");
1668 
1669   return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1670 }
1671 
1672 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1673   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1674   assert(interval_at(reg_num) != NULL, "no interval found");
1675 
1676   return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1677 }
1678 
1679 
1680 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1681   DEBUG_ONLY(move_resolver.check_empty());
1682 
1683   const int num_regs = num_virtual_regs();
1684   const int size = live_set_size();
1685   const BitMap live_at_edge = to_block->live_in();
1686 
1687   // visit all registers where the live_at_edge bit is set
1688   for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1689     assert(r < num_regs, "live information set for not exisiting interval");
1690     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1691 
1692     Interval* from_interval = interval_at_block_end(from_block, r);
1693     Interval* to_interval = interval_at_block_begin(to_block, r);
1694 
1695     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1696       // need to insert move instruction
1697       move_resolver.add_mapping(from_interval, to_interval);
1698     }
1699   }
1700 }
1701 
1702 
1703 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1704   if (from_block->number_of_sux() <= 1) {
1705     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1706 
1707     LIR_OpList* instructions = from_block->lir()->instructions_list();
1708     LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1709     if (branch != NULL) {
1710       // insert moves before branch
1711       assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1712       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1713     } else {
1714       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1715     }
1716 
1717   } else {
1718     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1719 #ifdef ASSERT
1720     assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1721 
1722     // because the number of predecessor edges matches the number of
1723     // successor edges, blocks which are reached by switch statements
1724     // may have be more than one predecessor but it will be guaranteed
1725     // that all predecessors will be the same.
1726     for (int i = 0; i < to_block->number_of_preds(); i++) {
1727       assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1728     }
1729 #endif
1730 
1731     move_resolver.set_insert_position(to_block->lir(), 0);
1732   }
1733 }
1734 
1735 
1736 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1737 void LinearScan::resolve_data_flow() {
1738   TIME_LINEAR_SCAN(timer_resolve_data_flow);
1739 
1740   int num_blocks = block_count();
1741   MoveResolver move_resolver(this);
1742   BitMap block_completed(num_blocks);  block_completed.clear();
1743   BitMap already_resolved(num_blocks); already_resolved.clear();
1744 
1745   int i;
1746   for (i = 0; i < num_blocks; i++) {
1747     BlockBegin* block = block_at(i);
1748 
1749     // check if block has only one predecessor and only one successor
1750     if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1751       LIR_OpList* instructions = block->lir()->instructions_list();
1752       assert(instructions->at(0)->code() == lir_label, "block must start with label");
1753       assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1754       assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1755 
1756       // check if block is empty (only label and branch)
1757       if (instructions->length() == 2) {
1758         BlockBegin* pred = block->pred_at(0);
1759         BlockBegin* sux = block->sux_at(0);
1760 
1761         // prevent optimization of two consecutive blocks
1762         if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1763           TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1764           block_completed.set_bit(block->linear_scan_number());
1765 
1766           // directly resolve between pred and sux (without looking at the empty block between)
1767           resolve_collect_mappings(pred, sux, move_resolver);
1768           if (move_resolver.has_mappings()) {
1769             move_resolver.set_insert_position(block->lir(), 0);
1770             move_resolver.resolve_and_append_moves();
1771           }
1772         }
1773       }
1774     }
1775   }
1776 
1777 
1778   for (i = 0; i < num_blocks; i++) {
1779     if (!block_completed.at(i)) {
1780       BlockBegin* from_block = block_at(i);
1781       already_resolved.set_from(block_completed);
1782 
1783       int num_sux = from_block->number_of_sux();
1784       for (int s = 0; s < num_sux; s++) {
1785         BlockBegin* to_block = from_block->sux_at(s);
1786 
1787         // check for duplicate edges between the same blocks (can happen with switch blocks)
1788         if (!already_resolved.at(to_block->linear_scan_number())) {
1789           TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1790           already_resolved.set_bit(to_block->linear_scan_number());
1791 
1792           // collect all intervals that have been split between from_block and to_block
1793           resolve_collect_mappings(from_block, to_block, move_resolver);
1794           if (move_resolver.has_mappings()) {
1795             resolve_find_insert_pos(from_block, to_block, move_resolver);
1796             move_resolver.resolve_and_append_moves();
1797           }
1798         }
1799       }
1800     }
1801   }
1802 }
1803 
1804 
1805 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1806   if (interval_at(reg_num) == NULL) {
1807     // if a phi function is never used, no interval is created -> ignore this
1808     return;
1809   }
1810 
1811   Interval* interval = interval_at_block_begin(block, reg_num);
1812   int reg = interval->assigned_reg();
1813   int regHi = interval->assigned_regHi();
1814 
1815   if ((reg < nof_regs && interval->always_in_memory()) ||
1816       (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1817     // the interval is split to get a short range that is located on the stack
1818     // in the following two cases:
1819     // * the interval started in memory (e.g. method parameter), but is currently in a register
1820     //   this is an optimization for exception handling that reduces the number of moves that
1821     //   are necessary for resolving the states when an exception uses this exception handler
1822     // * the interval would be on the fpu stack at the begin of the exception handler
1823     //   this is not allowed because of the complicated fpu stack handling on Intel
1824 
1825     // range that will be spilled to memory
1826     int from_op_id = block->first_lir_instruction_id();
1827     int to_op_id = from_op_id + 1;  // short live range of length 1
1828     assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1829            "no split allowed between exception entry and first instruction");
1830 
1831     if (interval->from() != from_op_id) {
1832       // the part before from_op_id is unchanged
1833       interval = interval->split(from_op_id);
1834       interval->assign_reg(reg, regHi);
1835       append_interval(interval);
1836     } else {
1837       _needs_full_resort = true;
1838     }
1839     assert(interval->from() == from_op_id, "must be true now");
1840 
1841     Interval* spilled_part = interval;
1842     if (interval->to() != to_op_id) {
1843       // the part after to_op_id is unchanged
1844       spilled_part = interval->split_from_start(to_op_id);
1845       append_interval(spilled_part);
1846       move_resolver.add_mapping(spilled_part, interval);
1847     }
1848     assign_spill_slot(spilled_part);
1849 
1850     assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1851   }
1852 }
1853 
1854 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1855   assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1856   DEBUG_ONLY(move_resolver.check_empty());
1857 
1858   // visit all registers where the live_in bit is set
1859   int size = live_set_size();
1860   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1861     resolve_exception_entry(block, r, move_resolver);
1862   }
1863 
1864   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1865   for_each_phi_fun(block, phi,
1866     resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver)
1867   );
1868 
1869   if (move_resolver.has_mappings()) {
1870     // insert moves after first instruction
1871     move_resolver.set_insert_position(block->lir(), 0);
1872     move_resolver.resolve_and_append_moves();
1873   }
1874 }
1875 
1876 
1877 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1878   if (interval_at(reg_num) == NULL) {
1879     // if a phi function is never used, no interval is created -> ignore this
1880     return;
1881   }
1882 
1883   // the computation of to_interval is equal to resolve_collect_mappings,
1884   // but from_interval is more complicated because of phi functions
1885   BlockBegin* to_block = handler->entry_block();
1886   Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1887 
1888   if (phi != NULL) {
1889     // phi function of the exception entry block
1890     // no moves are created for this phi function in the LIR_Generator, so the
1891     // interval at the throwing instruction must be searched using the operands
1892     // of the phi function
1893     Value from_value = phi->operand_at(handler->phi_operand());
1894 
1895     // with phi functions it can happen that the same from_value is used in
1896     // multiple mappings, so notify move-resolver that this is allowed
1897     move_resolver.set_multiple_reads_allowed();
1898 
1899     Constant* con = from_value->as_Constant();
1900     if (con != NULL && !con->is_pinned()) {
1901       // unpinned constants may have no register, so add mapping from constant to interval
1902       move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1903     } else {
1904       // search split child at the throwing op_id
1905       Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1906       move_resolver.add_mapping(from_interval, to_interval);
1907     }
1908 
1909   } else {
1910     // no phi function, so use reg_num also for from_interval
1911     // search split child at the throwing op_id
1912     Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1913     if (from_interval != to_interval) {
1914       // optimization to reduce number of moves: when to_interval is on stack and
1915       // the stack slot is known to be always correct, then no move is necessary
1916       if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1917         move_resolver.add_mapping(from_interval, to_interval);
1918       }
1919     }
1920   }
1921 }
1922 
1923 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1924   TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1925 
1926   DEBUG_ONLY(move_resolver.check_empty());
1927   assert(handler->lir_op_id() == -1, "already processed this xhandler");
1928   DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1929   assert(handler->entry_code() == NULL, "code already present");
1930 
1931   // visit all registers where the live_in bit is set
1932   BlockBegin* block = handler->entry_block();
1933   int size = live_set_size();
1934   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1935     resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1936   }
1937 
1938   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1939   for_each_phi_fun(block, phi,
1940     resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
1941   );
1942 
1943   if (move_resolver.has_mappings()) {
1944     LIR_List* entry_code = new LIR_List(compilation());
1945     move_resolver.set_insert_position(entry_code, 0);
1946     move_resolver.resolve_and_append_moves();
1947 
1948     entry_code->jump(handler->entry_block());
1949     handler->set_entry_code(entry_code);
1950   }
1951 }
1952 
1953 
1954 void LinearScan::resolve_exception_handlers() {
1955   MoveResolver move_resolver(this);
1956   LIR_OpVisitState visitor;
1957   int num_blocks = block_count();
1958 
1959   int i;
1960   for (i = 0; i < num_blocks; i++) {
1961     BlockBegin* block = block_at(i);
1962     if (block->is_set(BlockBegin::exception_entry_flag)) {
1963       resolve_exception_entry(block, move_resolver);
1964     }
1965   }
1966 
1967   for (i = 0; i < num_blocks; i++) {
1968     BlockBegin* block = block_at(i);
1969     LIR_List* ops = block->lir();
1970     int num_ops = ops->length();
1971 
1972     // iterate all instructions of the block. skip the first because it is always a label
1973     assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
1974     for (int j = 1; j < num_ops; j++) {
1975       LIR_Op* op = ops->at(j);
1976       int op_id = op->id();
1977 
1978       if (op_id != -1 && has_info(op_id)) {
1979         // visit operation to collect all operands
1980         visitor.visit(op);
1981         assert(visitor.info_count() > 0, "should not visit otherwise");
1982 
1983         XHandlers* xhandlers = visitor.all_xhandler();
1984         int n = xhandlers->length();
1985         for (int k = 0; k < n; k++) {
1986           resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
1987         }
1988 
1989 #ifdef ASSERT
1990       } else {
1991         visitor.visit(op);
1992         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
1993 #endif
1994       }
1995     }
1996   }
1997 }
1998 
1999 
2000 // ********** Phase 7: assign register numbers back to LIR
2001 // (includes computation of debug information and oop maps)
2002 
2003 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2004   VMReg reg = interval->cached_vm_reg();
2005   if (!reg->is_valid() ) {
2006     reg = vm_reg_for_operand(operand_for_interval(interval));
2007     interval->set_cached_vm_reg(reg);
2008   }
2009   assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2010   return reg;
2011 }
2012 
2013 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2014   assert(opr->is_oop(), "currently only implemented for oop operands");
2015   return frame_map()->regname(opr);
2016 }
2017 
2018 
2019 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2020   LIR_Opr opr = interval->cached_opr();
2021   if (opr->is_illegal()) {
2022     opr = calc_operand_for_interval(interval);
2023     interval->set_cached_opr(opr);
2024   }
2025 
2026   assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2027   return opr;
2028 }
2029 
2030 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2031   int assigned_reg = interval->assigned_reg();
2032   BasicType type = interval->type();
2033 
2034   if (assigned_reg >= nof_regs) {
2035     // stack slot
2036     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2037     return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2038 
2039   } else {
2040     // register
2041     switch (type) {
2042       case T_OBJECT: {
2043         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2044         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2045         return LIR_OprFact::single_cpu_oop(assigned_reg);
2046       }
2047 
2048       case T_ADDRESS: {
2049         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2050         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2051         return LIR_OprFact::single_cpu_address(assigned_reg);
2052       }
2053 
2054       case T_METADATA: {
2055         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2056         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2057         return LIR_OprFact::single_cpu_metadata(assigned_reg);
2058       }
2059 
2060 #ifdef __SOFTFP__
2061       case T_FLOAT:  // fall through
2062 #endif // __SOFTFP__
2063       case T_INT: {
2064         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2065         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2066         return LIR_OprFact::single_cpu(assigned_reg);
2067       }
2068 
2069 #ifdef __SOFTFP__
2070       case T_DOUBLE:  // fall through
2071 #endif // __SOFTFP__
2072       case T_LONG: {
2073         int assigned_regHi = interval->assigned_regHi();
2074         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2075         assert(num_physical_regs(T_LONG) == 1 ||
2076                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2077 
2078         assert(assigned_reg != assigned_regHi, "invalid allocation");
2079         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2080                "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2081         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2082         if (requires_adjacent_regs(T_LONG)) {
2083           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2084         }
2085 
2086 #ifdef _LP64
2087         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2088 #else
2089 #if defined(SPARC) || defined(PPC)
2090         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2091 #else
2092         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2093 #endif // SPARC
2094 #endif // LP64
2095       }
2096 
2097 #ifndef __SOFTFP__
2098       case T_FLOAT: {
2099 #ifdef X86
2100         if (UseSSE >= 1) {
2101           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2102           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2103           return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2104         }
2105 #endif
2106 
2107         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2108         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2109         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2110       }
2111 
2112       case T_DOUBLE: {
2113 #ifdef X86
2114         if (UseSSE >= 2) {
2115           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2116           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2117           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2118         }
2119 #endif
2120 
2121 #ifdef SPARC
2122         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2123         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2124         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2125         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2126 #elif defined(ARM32)
2127         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2128         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2129         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2130         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2131 #else
2132         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2133         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2134         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2135 #endif
2136         return result;
2137       }
2138 #endif // __SOFTFP__
2139 
2140       default: {
2141         ShouldNotReachHere();
2142         return LIR_OprFact::illegalOpr;
2143       }
2144     }
2145   }
2146 }
2147 
2148 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2149   assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2150   return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2151 }
2152 
2153 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2154   assert(opr->is_virtual(), "should not call this otherwise");
2155 
2156   Interval* interval = interval_at(opr->vreg_number());
2157   assert(interval != NULL, "interval must exist");
2158 
2159   if (op_id != -1) {
2160 #ifdef ASSERT
2161     BlockBegin* block = block_of_op_with_id(op_id);
2162     if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2163       // check if spill moves could have been appended at the end of this block, but
2164       // before the branch instruction. So the split child information for this branch would
2165       // be incorrect.
2166       LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2167       if (branch != NULL) {
2168         if (block->live_out().at(opr->vreg_number())) {
2169           assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2170           assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2171         }
2172       }
2173     }
2174 #endif
2175 
2176     // operands are not changed when an interval is split during allocation,
2177     // so search the right interval here
2178     interval = split_child_at_op_id(interval, op_id, mode);
2179   }
2180 
2181   LIR_Opr res = operand_for_interval(interval);
2182 
2183 #ifdef X86
2184   // new semantic for is_last_use: not only set on definite end of interval,
2185   // but also before hole
2186   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2187   // last use information is completely correct
2188   // information is only needed for fpu stack allocation
2189   if (res->is_fpu_register()) {
2190     if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2191       assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2192       res = res->make_last_use();
2193     }
2194   }
2195 #endif
2196 
2197   assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2198 
2199   return res;
2200 }
2201 
2202 
2203 #ifdef ASSERT
2204 // some methods used to check correctness of debug information
2205 
2206 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2207   if (values == NULL) {
2208     return;
2209   }
2210 
2211   for (int i = 0; i < values->length(); i++) {
2212     ScopeValue* value = values->at(i);
2213 
2214     if (value->is_location()) {
2215       Location location = ((LocationValue*)value)->location();
2216       assert(location.where() == Location::on_stack, "value is in register");
2217     }
2218   }
2219 }
2220 
2221 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2222   if (values == NULL) {
2223     return;
2224   }
2225 
2226   for (int i = 0; i < values->length(); i++) {
2227     MonitorValue* value = values->at(i);
2228 
2229     if (value->owner()->is_location()) {
2230       Location location = ((LocationValue*)value->owner())->location();
2231       assert(location.where() == Location::on_stack, "owner is in register");
2232     }
2233     assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2234   }
2235 }
2236 
2237 void assert_equal(Location l1, Location l2) {
2238   assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2239 }
2240 
2241 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2242   if (v1->is_location()) {
2243     assert(v2->is_location(), "");
2244     assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2245   } else if (v1->is_constant_int()) {
2246     assert(v2->is_constant_int(), "");
2247     assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2248   } else if (v1->is_constant_double()) {
2249     assert(v2->is_constant_double(), "");
2250     assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2251   } else if (v1->is_constant_long()) {
2252     assert(v2->is_constant_long(), "");
2253     assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2254   } else if (v1->is_constant_oop()) {
2255     assert(v2->is_constant_oop(), "");
2256     assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2257   } else {
2258     ShouldNotReachHere();
2259   }
2260 }
2261 
2262 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2263   assert_equal(m1->owner(), m2->owner());
2264   assert_equal(m1->basic_lock(), m2->basic_lock());
2265 }
2266 
2267 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2268   assert(d1->scope() == d2->scope(), "not equal");
2269   assert(d1->bci() == d2->bci(), "not equal");
2270 
2271   if (d1->locals() != NULL) {
2272     assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2273     assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2274     for (int i = 0; i < d1->locals()->length(); i++) {
2275       assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2276     }
2277   } else {
2278     assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2279   }
2280 
2281   if (d1->expressions() != NULL) {
2282     assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2283     assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2284     for (int i = 0; i < d1->expressions()->length(); i++) {
2285       assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2286     }
2287   } else {
2288     assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2289   }
2290 
2291   if (d1->monitors() != NULL) {
2292     assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2293     assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2294     for (int i = 0; i < d1->monitors()->length(); i++) {
2295       assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2296     }
2297   } else {
2298     assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2299   }
2300 
2301   if (d1->caller() != NULL) {
2302     assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2303     assert_equal(d1->caller(), d2->caller());
2304   } else {
2305     assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2306   }
2307 }
2308 
2309 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2310   if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2311     Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2312     switch (code) {
2313       case Bytecodes::_ifnull    : // fall through
2314       case Bytecodes::_ifnonnull : // fall through
2315       case Bytecodes::_ifeq      : // fall through
2316       case Bytecodes::_ifne      : // fall through
2317       case Bytecodes::_iflt      : // fall through
2318       case Bytecodes::_ifge      : // fall through
2319       case Bytecodes::_ifgt      : // fall through
2320       case Bytecodes::_ifle      : // fall through
2321       case Bytecodes::_if_icmpeq : // fall through
2322       case Bytecodes::_if_icmpne : // fall through
2323       case Bytecodes::_if_icmplt : // fall through
2324       case Bytecodes::_if_icmpge : // fall through
2325       case Bytecodes::_if_icmpgt : // fall through
2326       case Bytecodes::_if_icmple : // fall through
2327       case Bytecodes::_if_acmpeq : // fall through
2328       case Bytecodes::_if_acmpne :
2329         assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2330         break;
2331     }
2332   }
2333 }
2334 
2335 #endif // ASSERT
2336 
2337 
2338 IntervalWalker* LinearScan::init_compute_oop_maps() {
2339   // setup lists of potential oops for walking
2340   Interval* oop_intervals;
2341   Interval* non_oop_intervals;
2342 
2343   create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2344 
2345   // intervals that have no oops inside need not to be processed
2346   // to ensure a walking until the last instruction id, add a dummy interval
2347   // with a high operation id
2348   non_oop_intervals = new Interval(any_reg);
2349   non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2350 
2351   return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2352 }
2353 
2354 
2355 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2356   TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2357 
2358   // walk before the current operation -> intervals that start at
2359   // the operation (= output operands of the operation) are not
2360   // included in the oop map
2361   iw->walk_before(op->id());
2362 
2363   int frame_size = frame_map()->framesize();
2364   int arg_count = frame_map()->oop_map_arg_count();
2365   OopMap* map = new OopMap(frame_size, arg_count);
2366 
2367   // Iterate through active intervals
2368   for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2369     int assigned_reg = interval->assigned_reg();
2370 
2371     assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2372     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2373     assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2374 
2375     // Check if this range covers the instruction. Intervals that
2376     // start or end at the current operation are not included in the
2377     // oop map, except in the case of patching moves.  For patching
2378     // moves, any intervals which end at this instruction are included
2379     // in the oop map since we may safepoint while doing the patch
2380     // before we've consumed the inputs.
2381     if (op->is_patching() || op->id() < interval->current_to()) {
2382 
2383       // caller-save registers must not be included into oop-maps at calls
2384       assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2385 
2386       VMReg name = vm_reg_for_interval(interval);
2387       set_oop(map, name);
2388 
2389       // Spill optimization: when the stack value is guaranteed to be always correct,
2390       // then it must be added to the oop map even if the interval is currently in a register
2391       if (interval->always_in_memory() &&
2392           op->id() > interval->spill_definition_pos() &&
2393           interval->assigned_reg() != interval->canonical_spill_slot()) {
2394         assert(interval->spill_definition_pos() > 0, "position not set correctly");
2395         assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2396         assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2397 
2398         set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2399       }
2400     }
2401   }
2402 
2403   // add oops from lock stack
2404   assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2405   int locks_count = info->stack()->total_locks_size();
2406   for (int i = 0; i < locks_count; i++) {
2407     set_oop(map, frame_map()->monitor_object_regname(i));
2408   }
2409 
2410   return map;
2411 }
2412 
2413 
2414 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2415   assert(visitor.info_count() > 0, "no oop map needed");
2416 
2417   // compute oop_map only for first CodeEmitInfo
2418   // because it is (in most cases) equal for all other infos of the same operation
2419   CodeEmitInfo* first_info = visitor.info_at(0);
2420   OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2421 
2422   for (int i = 0; i < visitor.info_count(); i++) {
2423     CodeEmitInfo* info = visitor.info_at(i);
2424     OopMap* oop_map = first_oop_map;
2425 
2426     // compute worst case interpreter size in case of a deoptimization
2427     _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2428 
2429     if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2430       // this info has a different number of locks then the precomputed oop map
2431       // (possible for lock and unlock instructions) -> compute oop map with
2432       // correct lock information
2433       oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2434     }
2435 
2436     if (info->_oop_map == NULL) {
2437       info->_oop_map = oop_map;
2438     } else {
2439       // a CodeEmitInfo can not be shared between different LIR-instructions
2440       // because interval splitting can occur anywhere between two instructions
2441       // and so the oop maps must be different
2442       // -> check if the already set oop_map is exactly the one calculated for this operation
2443       assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2444     }
2445   }
2446 }
2447 
2448 
2449 // frequently used constants
2450 // Allocate them with new so they are never destroyed (otherwise, a
2451 // forced exit could destroy these objects while they are still in
2452 // use).
2453 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2454 ConstantIntValue*      LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2455 ConstantIntValue*      LinearScan::_int_0_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0);
2456 ConstantIntValue*      LinearScan::_int_1_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2457 ConstantIntValue*      LinearScan::_int_2_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2458 LocationValue*         _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2459 
2460 void LinearScan::init_compute_debug_info() {
2461   // cache for frequently used scope values
2462   // (cpu registers and stack slots)
2463   _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL);
2464 }
2465 
2466 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2467   Location loc;
2468   if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2469     bailout("too large frame");
2470   }
2471   ScopeValue* object_scope_value = new LocationValue(loc);
2472 
2473   if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2474     bailout("too large frame");
2475   }
2476   return new MonitorValue(object_scope_value, loc);
2477 }
2478 
2479 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2480   Location loc;
2481   if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2482     bailout("too large frame");
2483   }
2484   return new LocationValue(loc);
2485 }
2486 
2487 
2488 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2489   assert(opr->is_constant(), "should not be called otherwise");
2490 
2491   LIR_Const* c = opr->as_constant_ptr();
2492   BasicType t = c->type();
2493   switch (t) {
2494     case T_OBJECT: {
2495       jobject value = c->as_jobject();
2496       if (value == NULL) {
2497         scope_values->append(_oop_null_scope_value);
2498       } else {
2499         scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2500       }
2501       return 1;
2502     }
2503 
2504     case T_INT: // fall through
2505     case T_FLOAT: {
2506       int value = c->as_jint_bits();
2507       switch (value) {
2508         case -1: scope_values->append(_int_m1_scope_value); break;
2509         case 0:  scope_values->append(_int_0_scope_value); break;
2510         case 1:  scope_values->append(_int_1_scope_value); break;
2511         case 2:  scope_values->append(_int_2_scope_value); break;
2512         default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2513       }
2514       return 1;
2515     }
2516 
2517     case T_LONG: // fall through
2518     case T_DOUBLE: {
2519 #ifdef _LP64
2520       scope_values->append(_int_0_scope_value);
2521       scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2522 #else
2523       if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2524         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2525         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2526       } else {
2527         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2528         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2529       }
2530 #endif
2531       return 2;
2532     }
2533 
2534     case T_ADDRESS: {
2535 #ifdef _LP64
2536       scope_values->append(new ConstantLongValue(c->as_jint()));
2537 #else
2538       scope_values->append(new ConstantIntValue(c->as_jint()));
2539 #endif
2540       return 1;
2541     }
2542 
2543     default:
2544       ShouldNotReachHere();
2545       return -1;
2546   }
2547 }
2548 
2549 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2550   if (opr->is_single_stack()) {
2551     int stack_idx = opr->single_stack_ix();
2552     bool is_oop = opr->is_oop_register();
2553     int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2554 
2555     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2556     if (sv == NULL) {
2557       Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2558       sv = location_for_name(stack_idx, loc_type);
2559       _scope_value_cache.at_put(cache_idx, sv);
2560     }
2561 
2562     // check if cached value is correct
2563     DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2564 
2565     scope_values->append(sv);
2566     return 1;
2567 
2568   } else if (opr->is_single_cpu()) {
2569     bool is_oop = opr->is_oop_register();
2570     int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2571     Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2572 
2573     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2574     if (sv == NULL) {
2575       Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2576       VMReg rname = frame_map()->regname(opr);
2577       sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2578       _scope_value_cache.at_put(cache_idx, sv);
2579     }
2580 
2581     // check if cached value is correct
2582     DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2583 
2584     scope_values->append(sv);
2585     return 1;
2586 
2587 #ifdef X86
2588   } else if (opr->is_single_xmm()) {
2589     VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2590     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2591 
2592     scope_values->append(sv);
2593     return 1;
2594 #endif
2595 
2596   } else if (opr->is_single_fpu()) {
2597 #ifdef X86
2598     // the exact location of fpu stack values is only known
2599     // during fpu stack allocation, so the stack allocator object
2600     // must be present
2601     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2602     assert(_fpu_stack_allocator != NULL, "must be present");
2603     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2604 #endif
2605 
2606     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2607     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2608 #ifndef __SOFTFP__
2609 #ifndef VM_LITTLE_ENDIAN
2610     if (! float_saved_as_double) {
2611       // On big endian system, we may have an issue if float registers use only
2612       // the low half of the (same) double registers.
2613       // Both the float and the double could have the same regnr but would correspond
2614       // to two different addresses once saved.
2615 
2616       // get next safely (no assertion checks)
2617       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2618       if (next->is_reg() &&
2619           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2620         // the back-end does use the same numbering for the double and the float
2621         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2622       }
2623     }
2624 #endif
2625 #endif
2626     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2627 
2628     scope_values->append(sv);
2629     return 1;
2630 
2631   } else {
2632     // double-size operands
2633 
2634     ScopeValue* first;
2635     ScopeValue* second;
2636 
2637     if (opr->is_double_stack()) {
2638 #ifdef _LP64
2639       Location loc1;
2640       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2641       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2642         bailout("too large frame");
2643       }
2644       // Does this reverse on x86 vs. sparc?
2645       first =  new LocationValue(loc1);
2646       second = _int_0_scope_value;
2647 #else
2648       Location loc1, loc2;
2649       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2650         bailout("too large frame");
2651       }
2652       first =  new LocationValue(loc1);
2653       second = new LocationValue(loc2);
2654 #endif // _LP64
2655 
2656     } else if (opr->is_double_cpu()) {
2657 #ifdef _LP64
2658       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2659       first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2660       second = _int_0_scope_value;
2661 #else
2662       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2663       VMReg rname_second = opr->as_register_hi()->as_VMReg();
2664 
2665       if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2666         // lo/hi and swapped relative to first and second, so swap them
2667         VMReg tmp = rname_first;
2668         rname_first = rname_second;
2669         rname_second = tmp;
2670       }
2671 
2672       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2673       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2674 #endif //_LP64
2675 
2676 
2677 #ifdef X86
2678     } else if (opr->is_double_xmm()) {
2679       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2680       VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
2681 #  ifdef _LP64
2682       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2683       second = _int_0_scope_value;
2684 #  else
2685       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2686       // %%% This is probably a waste but we'll keep things as they were for now
2687       if (true) {
2688         VMReg rname_second = rname_first->next();
2689         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2690       }
2691 #  endif
2692 #endif
2693 
2694     } else if (opr->is_double_fpu()) {
2695       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2696       // the double as float registers in the native ordering. On X86,
2697       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2698       // the low-order word of the double and fpu_regnrLo + 1 is the
2699       // name for the other half.  *first and *second must represent the
2700       // least and most significant words, respectively.
2701 
2702 #ifdef X86
2703       // the exact location of fpu stack values is only known
2704       // during fpu stack allocation, so the stack allocator object
2705       // must be present
2706       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2707       assert(_fpu_stack_allocator != NULL, "must be present");
2708       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2709 
2710       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2711 #endif
2712 #ifdef SPARC
2713       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2714 #endif
2715 #ifdef ARM32
2716       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2717 #endif
2718 #ifdef PPC
2719       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2720 #endif
2721 
2722 #ifdef VM_LITTLE_ENDIAN
2723       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2724 #else
2725       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2726 #endif
2727 
2728 #ifdef _LP64
2729       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2730       second = _int_0_scope_value;
2731 #else
2732       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2733       // %%% This is probably a waste but we'll keep things as they were for now
2734       if (true) {
2735         VMReg rname_second = rname_first->next();
2736         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2737       }
2738 #endif
2739 
2740     } else {
2741       ShouldNotReachHere();
2742       first = NULL;
2743       second = NULL;
2744     }
2745 
2746     assert(first != NULL && second != NULL, "must be set");
2747     // The convention the interpreter uses is that the second local
2748     // holds the first raw word of the native double representation.
2749     // This is actually reasonable, since locals and stack arrays
2750     // grow downwards in all implementations.
2751     // (If, on some machine, the interpreter's Java locals or stack
2752     // were to grow upwards, the embedded doubles would be word-swapped.)
2753     scope_values->append(second);
2754     scope_values->append(first);
2755     return 2;
2756   }
2757 }
2758 
2759 
2760 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2761   if (value != NULL) {
2762     LIR_Opr opr = value->operand();
2763     Constant* con = value->as_Constant();
2764 
2765     assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2766     assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2767 
2768     if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2769       // Unpinned constants may have a virtual operand for a part of the lifetime
2770       // or may be illegal when it was optimized away,
2771       // so always use a constant operand
2772       opr = LIR_OprFact::value_type(con->type());
2773     }
2774     assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2775 
2776     if (opr->is_virtual()) {
2777       LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2778 
2779       BlockBegin* block = block_of_op_with_id(op_id);
2780       if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2781         // generating debug information for the last instruction of a block.
2782         // if this instruction is a branch, spill moves are inserted before this branch
2783         // and so the wrong operand would be returned (spill moves at block boundaries are not
2784         // considered in the live ranges of intervals)
2785         // Solution: use the first op_id of the branch target block instead.
2786         if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2787           if (block->live_out().at(opr->vreg_number())) {
2788             op_id = block->sux_at(0)->first_lir_instruction_id();
2789             mode = LIR_OpVisitState::outputMode;
2790           }
2791         }
2792       }
2793 
2794       // Get current location of operand
2795       // The operand must be live because debug information is considered when building the intervals
2796       // if the interval is not live, color_lir_opr will cause an assertion failure
2797       opr = color_lir_opr(opr, op_id, mode);
2798       assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2799 
2800       // Append to ScopeValue array
2801       return append_scope_value_for_operand(opr, scope_values);
2802 
2803     } else {
2804       assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2805       assert(opr->is_constant(), "operand must be constant");
2806 
2807       return append_scope_value_for_constant(opr, scope_values);
2808     }
2809   } else {
2810     // append a dummy value because real value not needed
2811     scope_values->append(_illegal_value);
2812     return 1;
2813   }
2814 }
2815 
2816 
2817 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2818   IRScopeDebugInfo* caller_debug_info = NULL;
2819 
2820   ValueStack* caller_state = cur_state->caller_state();
2821   if (caller_state != NULL) {
2822     // process recursively to compute outermost scope first
2823     caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2824   }
2825 
2826   // initialize these to null.
2827   // If we don't need deopt info or there are no locals, expressions or monitors,
2828   // then these get recorded as no information and avoids the allocation of 0 length arrays.
2829   GrowableArray<ScopeValue*>*   locals      = NULL;
2830   GrowableArray<ScopeValue*>*   expressions = NULL;
2831   GrowableArray<MonitorValue*>* monitors    = NULL;
2832 
2833   // describe local variable values
2834   int nof_locals = cur_state->locals_size();
2835   if (nof_locals > 0) {
2836     locals = new GrowableArray<ScopeValue*>(nof_locals);
2837 
2838     int pos = 0;
2839     while (pos < nof_locals) {
2840       assert(pos < cur_state->locals_size(), "why not?");
2841 
2842       Value local = cur_state->local_at(pos);
2843       pos += append_scope_value(op_id, local, locals);
2844 
2845       assert(locals->length() == pos, "must match");
2846     }
2847     assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2848     assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2849   } else if (cur_scope->method()->max_locals() > 0) {
2850     assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2851     nof_locals = cur_scope->method()->max_locals();
2852     locals = new GrowableArray<ScopeValue*>(nof_locals);
2853     for(int i = 0; i < nof_locals; i++) {
2854       locals->append(_illegal_value);
2855     }
2856   }
2857 
2858   // describe expression stack
2859   int nof_stack = cur_state->stack_size();
2860   if (nof_stack > 0) {
2861     expressions = new GrowableArray<ScopeValue*>(nof_stack);
2862 
2863     int pos = 0;
2864     while (pos < nof_stack) {
2865       Value expression = cur_state->stack_at_inc(pos);
2866       append_scope_value(op_id, expression, expressions);
2867 
2868       assert(expressions->length() == pos, "must match");
2869     }
2870     assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2871   }
2872 
2873   // describe monitors
2874   int nof_locks = cur_state->locks_size();
2875   if (nof_locks > 0) {
2876     int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2877     monitors = new GrowableArray<MonitorValue*>(nof_locks);
2878     for (int i = 0; i < nof_locks; i++) {
2879       monitors->append(location_for_monitor_index(lock_offset + i));
2880     }
2881   }
2882 
2883   return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2884 }
2885 
2886 
2887 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2888   TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2889 
2890   IRScope* innermost_scope = info->scope();
2891   ValueStack* innermost_state = info->stack();
2892 
2893   assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2894 
2895   DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2896 
2897   if (info->_scope_debug_info == NULL) {
2898     // compute debug information
2899     info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2900   } else {
2901     // debug information already set. Check that it is correct from the current point of view
2902     DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2903   }
2904 }
2905 
2906 
2907 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2908   LIR_OpVisitState visitor;
2909   int num_inst = instructions->length();
2910   bool has_dead = false;
2911 
2912   for (int j = 0; j < num_inst; j++) {
2913     LIR_Op* op = instructions->at(j);
2914     if (op == NULL) {  // this can happen when spill-moves are removed in eliminate_spill_moves
2915       has_dead = true;
2916       continue;
2917     }
2918     int op_id = op->id();
2919 
2920     // visit instruction to get list of operands
2921     visitor.visit(op);
2922 
2923     // iterate all modes of the visitor and process all virtual operands
2924     for_each_visitor_mode(mode) {
2925       int n = visitor.opr_count(mode);
2926       for (int k = 0; k < n; k++) {
2927         LIR_Opr opr = visitor.opr_at(mode, k);
2928         if (opr->is_virtual_register()) {
2929           visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
2930         }
2931       }
2932     }
2933 
2934     if (visitor.info_count() > 0) {
2935       // exception handling
2936       if (compilation()->has_exception_handlers()) {
2937         XHandlers* xhandlers = visitor.all_xhandler();
2938         int n = xhandlers->length();
2939         for (int k = 0; k < n; k++) {
2940           XHandler* handler = xhandlers->handler_at(k);
2941           if (handler->entry_code() != NULL) {
2942             assign_reg_num(handler->entry_code()->instructions_list(), NULL);
2943           }
2944         }
2945       } else {
2946         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2947       }
2948 
2949       // compute oop map
2950       assert(iw != NULL, "needed for compute_oop_map");
2951       compute_oop_map(iw, visitor, op);
2952 
2953       // compute debug information
2954       if (!use_fpu_stack_allocation()) {
2955         // compute debug information if fpu stack allocation is not needed.
2956         // when fpu stack allocation is needed, the debug information can not
2957         // be computed here because the exact location of fpu operands is not known
2958         // -> debug information is created inside the fpu stack allocator
2959         int n = visitor.info_count();
2960         for (int k = 0; k < n; k++) {
2961           compute_debug_info(visitor.info_at(k), op_id);
2962         }
2963       }
2964     }
2965 
2966 #ifdef ASSERT
2967     // make sure we haven't made the op invalid.
2968     op->verify();
2969 #endif
2970 
2971     // remove useless moves
2972     if (op->code() == lir_move) {
2973       assert(op->as_Op1() != NULL, "move must be LIR_Op1");
2974       LIR_Op1* move = (LIR_Op1*)op;
2975       LIR_Opr src = move->in_opr();
2976       LIR_Opr dst = move->result_opr();
2977       if (dst == src ||
2978           !dst->is_pointer() && !src->is_pointer() &&
2979           src->is_same_register(dst)) {
2980         instructions->at_put(j, NULL);
2981         has_dead = true;
2982       }
2983     }
2984   }
2985 
2986   if (has_dead) {
2987     // iterate all instructions of the block and remove all null-values.
2988     int insert_point = 0;
2989     for (int j = 0; j < num_inst; j++) {
2990       LIR_Op* op = instructions->at(j);
2991       if (op != NULL) {
2992         if (insert_point != j) {
2993           instructions->at_put(insert_point, op);
2994         }
2995         insert_point++;
2996       }
2997     }
2998     instructions->truncate(insert_point);
2999   }
3000 }
3001 
3002 void LinearScan::assign_reg_num() {
3003   TIME_LINEAR_SCAN(timer_assign_reg_num);
3004 
3005   init_compute_debug_info();
3006   IntervalWalker* iw = init_compute_oop_maps();
3007 
3008   int num_blocks = block_count();
3009   for (int i = 0; i < num_blocks; i++) {
3010     BlockBegin* block = block_at(i);
3011     assign_reg_num(block->lir()->instructions_list(), iw);
3012   }
3013 }
3014 
3015 
3016 void LinearScan::do_linear_scan() {
3017   NOT_PRODUCT(_total_timer.begin_method());
3018 
3019   number_instructions();
3020 
3021   NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3022 
3023   compute_local_live_sets();
3024   compute_global_live_sets();
3025   CHECK_BAILOUT();
3026 
3027   build_intervals();
3028   CHECK_BAILOUT();
3029   sort_intervals_before_allocation();
3030 
3031   NOT_PRODUCT(print_intervals("Before Register Allocation"));
3032   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3033 
3034   allocate_registers();
3035   CHECK_BAILOUT();
3036 
3037   resolve_data_flow();
3038   if (compilation()->has_exception_handlers()) {
3039     resolve_exception_handlers();
3040   }
3041   // fill in number of spill slots into frame_map
3042   propagate_spill_slots();
3043   CHECK_BAILOUT();
3044 
3045   NOT_PRODUCT(print_intervals("After Register Allocation"));
3046   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3047 
3048   sort_intervals_after_allocation();
3049 
3050   DEBUG_ONLY(verify());
3051 
3052   eliminate_spill_moves();
3053   assign_reg_num();
3054   CHECK_BAILOUT();
3055 
3056   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3057   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3058 
3059   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3060 
3061     if (use_fpu_stack_allocation()) {
3062       allocate_fpu_stack(); // Only has effect on Intel
3063       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3064     }
3065   }
3066 
3067   { TIME_LINEAR_SCAN(timer_optimize_lir);
3068 
3069     EdgeMoveOptimizer::optimize(ir()->code());
3070     ControlFlowOptimizer::optimize(ir()->code());
3071     // check that cfg is still correct after optimizations
3072     ir()->verify();
3073   }
3074 
3075   NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3076   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3077   NOT_PRODUCT(_total_timer.end_method(this));
3078 }
3079 
3080 
3081 // ********** Printing functions
3082 
3083 #ifndef PRODUCT
3084 
3085 void LinearScan::print_timers(double total) {
3086   _total_timer.print(total);
3087 }
3088 
3089 void LinearScan::print_statistics() {
3090   _stat_before_alloc.print("before allocation");
3091   _stat_after_asign.print("after assignment of register");
3092   _stat_final.print("after optimization");
3093 }
3094 
3095 void LinearScan::print_bitmap(BitMap& b) {
3096   for (unsigned int i = 0; i < b.size(); i++) {
3097     if (b.at(i)) tty->print("%d ", i);
3098   }
3099   tty->cr();
3100 }
3101 
3102 void LinearScan::print_intervals(const char* label) {
3103   if (TraceLinearScanLevel >= 1) {
3104     int i;
3105     tty->cr();
3106     tty->print_cr("%s", label);
3107 
3108     for (i = 0; i < interval_count(); i++) {
3109       Interval* interval = interval_at(i);
3110       if (interval != NULL) {
3111         interval->print();
3112       }
3113     }
3114 
3115     tty->cr();
3116     tty->print_cr("--- Basic Blocks ---");
3117     for (i = 0; i < block_count(); i++) {
3118       BlockBegin* block = block_at(i);
3119       tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3120     }
3121     tty->cr();
3122     tty->cr();
3123   }
3124 
3125   if (PrintCFGToFile) {
3126     CFGPrinter::print_intervals(&_intervals, label);
3127   }
3128 }
3129 
3130 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3131   if (TraceLinearScanLevel >= level) {
3132     tty->cr();
3133     tty->print_cr("%s", label);
3134     print_LIR(ir()->linear_scan_order());
3135     tty->cr();
3136   }
3137 
3138   if (level == 1 && PrintCFGToFile) {
3139     CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3140   }
3141 }
3142 
3143 #endif //PRODUCT
3144 
3145 
3146 // ********** verification functions for allocation
3147 // (check that all intervals have a correct register and that no registers are overwritten)
3148 #ifdef ASSERT
3149 
3150 void LinearScan::verify() {
3151   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3152   verify_intervals();
3153 
3154   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3155   verify_no_oops_in_fixed_intervals();
3156 
3157   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3158   verify_constants();
3159 
3160   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3161   verify_registers();
3162 
3163   TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3164 }
3165 
3166 void LinearScan::verify_intervals() {
3167   int len = interval_count();
3168   bool has_error = false;
3169 
3170   for (int i = 0; i < len; i++) {
3171     Interval* i1 = interval_at(i);
3172     if (i1 == NULL) continue;
3173 
3174     i1->check_split_children();
3175 
3176     if (i1->reg_num() != i) {
3177       tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3178       has_error = true;
3179     }
3180 
3181     if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3182       tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3183       has_error = true;
3184     }
3185 
3186     if (i1->assigned_reg() == any_reg) {
3187       tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3188       has_error = true;
3189     }
3190 
3191     if (i1->assigned_reg() == i1->assigned_regHi()) {
3192       tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3193       has_error = true;
3194     }
3195 
3196     if (!is_processed_reg_num(i1->assigned_reg())) {
3197       tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3198       has_error = true;
3199     }
3200 
3201     if (i1->first() == Range::end()) {
3202       tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3203       has_error = true;
3204     }
3205 
3206     for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3207       if (r->from() >= r->to()) {
3208         tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3209         has_error = true;
3210       }
3211     }
3212 
3213     for (int j = i + 1; j < len; j++) {
3214       Interval* i2 = interval_at(j);
3215       if (i2 == NULL) continue;
3216 
3217       // special intervals that are created in MoveResolver
3218       // -> ignore them because the range information has no meaning there
3219       if (i1->from() == 1 && i1->to() == 2) continue;
3220       if (i2->from() == 1 && i2->to() == 2) continue;
3221 
3222       int r1 = i1->assigned_reg();
3223       int r1Hi = i1->assigned_regHi();
3224       int r2 = i2->assigned_reg();
3225       int r2Hi = i2->assigned_regHi();
3226       if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
3227         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3228         i1->print(); tty->cr();
3229         i2->print(); tty->cr();
3230         has_error = true;
3231       }
3232     }
3233   }
3234 
3235   assert(has_error == false, "register allocation invalid");
3236 }
3237 
3238 
3239 void LinearScan::verify_no_oops_in_fixed_intervals() {
3240   Interval* fixed_intervals;
3241   Interval* other_intervals;
3242   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3243 
3244   // to ensure a walking until the last instruction id, add a dummy interval
3245   // with a high operation id
3246   other_intervals = new Interval(any_reg);
3247   other_intervals->add_range(max_jint - 2, max_jint - 1);
3248   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3249 
3250   LIR_OpVisitState visitor;
3251   for (int i = 0; i < block_count(); i++) {
3252     BlockBegin* block = block_at(i);
3253 
3254     LIR_OpList* instructions = block->lir()->instructions_list();
3255 
3256     for (int j = 0; j < instructions->length(); j++) {
3257       LIR_Op* op = instructions->at(j);
3258       int op_id = op->id();
3259 
3260       visitor.visit(op);
3261 
3262       if (visitor.info_count() > 0) {
3263         iw->walk_before(op->id());
3264         bool check_live = true;
3265         if (op->code() == lir_move) {
3266           LIR_Op1* move = (LIR_Op1*)op;
3267           check_live = (move->patch_code() == lir_patch_none);
3268         }
3269         LIR_OpBranch* branch = op->as_OpBranch();
3270         if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3271           // Don't bother checking the stub in this case since the
3272           // exception stub will never return to normal control flow.
3273           check_live = false;
3274         }
3275 
3276         // Make sure none of the fixed registers is live across an
3277         // oopmap since we can't handle that correctly.
3278         if (check_live) {
3279           for (Interval* interval = iw->active_first(fixedKind);
3280                interval != Interval::end();
3281                interval = interval->next()) {
3282             if (interval->current_to() > op->id() + 1) {
3283               // This interval is live out of this op so make sure
3284               // that this interval represents some value that's
3285               // referenced by this op either as an input or output.
3286               bool ok = false;
3287               for_each_visitor_mode(mode) {
3288                 int n = visitor.opr_count(mode);
3289                 for (int k = 0; k < n; k++) {
3290                   LIR_Opr opr = visitor.opr_at(mode, k);
3291                   if (opr->is_fixed_cpu()) {
3292                     if (interval_at(reg_num(opr)) == interval) {
3293                       ok = true;
3294                       break;
3295                     }
3296                     int hi = reg_numHi(opr);
3297                     if (hi != -1 && interval_at(hi) == interval) {
3298                       ok = true;
3299                       break;
3300                     }
3301                   }
3302                 }
3303               }
3304               assert(ok, "fixed intervals should never be live across an oopmap point");
3305             }
3306           }
3307         }
3308       }
3309 
3310       // oop-maps at calls do not contain registers, so check is not needed
3311       if (!visitor.has_call()) {
3312 
3313         for_each_visitor_mode(mode) {
3314           int n = visitor.opr_count(mode);
3315           for (int k = 0; k < n; k++) {
3316             LIR_Opr opr = visitor.opr_at(mode, k);
3317 
3318             if (opr->is_fixed_cpu() && opr->is_oop()) {
3319               // operand is a non-virtual cpu register and contains an oop
3320               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3321 
3322               Interval* interval = interval_at(reg_num(opr));
3323               assert(interval != NULL, "no interval");
3324 
3325               if (mode == LIR_OpVisitState::inputMode) {
3326                 if (interval->to() >= op_id + 1) {
3327                   assert(interval->to() < op_id + 2 ||
3328                          interval->has_hole_between(op_id, op_id + 2),
3329                          "oop input operand live after instruction");
3330                 }
3331               } else if (mode == LIR_OpVisitState::outputMode) {
3332                 if (interval->from() <= op_id - 1) {
3333                   assert(interval->has_hole_between(op_id - 1, op_id),
3334                          "oop input operand live after instruction");
3335                 }
3336               }
3337             }
3338           }
3339         }
3340       }
3341     }
3342   }
3343 }
3344 
3345 
3346 void LinearScan::verify_constants() {
3347   int num_regs = num_virtual_regs();
3348   int size = live_set_size();
3349   int num_blocks = block_count();
3350 
3351   for (int i = 0; i < num_blocks; i++) {
3352     BlockBegin* block = block_at(i);
3353     BitMap live_at_edge = block->live_in();
3354 
3355     // visit all registers where the live_at_edge bit is set
3356     for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3357       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3358 
3359       Value value = gen()->instruction_for_vreg(r);
3360 
3361       assert(value != NULL, "all intervals live across block boundaries must have Value");
3362       assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3363       assert(value->operand()->vreg_number() == r, "register number must match");
3364       // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3365     }
3366   }
3367 }
3368 
3369 
3370 class RegisterVerifier: public StackObj {
3371  private:
3372   LinearScan*   _allocator;
3373   BlockList     _work_list;      // all blocks that must be processed
3374   IntervalsList _saved_states;   // saved information of previous check
3375 
3376   // simplified access to methods of LinearScan
3377   Compilation*  compilation() const              { return _allocator->compilation(); }
3378   Interval*     interval_at(int reg_num) const   { return _allocator->interval_at(reg_num); }
3379   int           reg_num(LIR_Opr opr) const       { return _allocator->reg_num(opr); }
3380 
3381   // currently, only registers are processed
3382   int           state_size()                     { return LinearScan::nof_regs; }
3383 
3384   // accessors
3385   IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3386   void          set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3387   void          add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3388 
3389   // helper functions
3390   IntervalList* copy(IntervalList* input_state);
3391   void          state_put(IntervalList* input_state, int reg, Interval* interval);
3392   bool          check_state(IntervalList* input_state, int reg, Interval* interval);
3393 
3394   void process_block(BlockBegin* block);
3395   void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3396   void process_successor(BlockBegin* block, IntervalList* input_state);
3397   void process_operations(LIR_List* ops, IntervalList* input_state);
3398 
3399  public:
3400   RegisterVerifier(LinearScan* allocator)
3401     : _allocator(allocator)
3402     , _work_list(16)
3403     , _saved_states(BlockBegin::number_of_blocks(), NULL)
3404   { }
3405 
3406   void verify(BlockBegin* start);
3407 };
3408 
3409 
3410 // entry function from LinearScan that starts the verification
3411 void LinearScan::verify_registers() {
3412   RegisterVerifier verifier(this);
3413   verifier.verify(block_at(0));
3414 }
3415 
3416 
3417 void RegisterVerifier::verify(BlockBegin* start) {
3418   // setup input registers (method arguments) for first block
3419   IntervalList* input_state = new IntervalList(state_size(), NULL);
3420   CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3421   for (int n = 0; n < args->length(); n++) {
3422     LIR_Opr opr = args->at(n);
3423     if (opr->is_register()) {
3424       Interval* interval = interval_at(reg_num(opr));
3425 
3426       if (interval->assigned_reg() < state_size()) {
3427         input_state->at_put(interval->assigned_reg(), interval);
3428       }
3429       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3430         input_state->at_put(interval->assigned_regHi(), interval);
3431       }
3432     }
3433   }
3434 
3435   set_state_for_block(start, input_state);
3436   add_to_work_list(start);
3437 
3438   // main loop for verification
3439   do {
3440     BlockBegin* block = _work_list.at(0);
3441     _work_list.remove_at(0);
3442 
3443     process_block(block);
3444   } while (!_work_list.is_empty());
3445 }
3446 
3447 void RegisterVerifier::process_block(BlockBegin* block) {
3448   TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3449 
3450   // must copy state because it is modified
3451   IntervalList* input_state = copy(state_for_block(block));
3452 
3453   if (TraceLinearScanLevel >= 4) {
3454     tty->print_cr("Input-State of intervals:");
3455     tty->print("    ");
3456     for (int i = 0; i < state_size(); i++) {
3457       if (input_state->at(i) != NULL) {
3458         tty->print(" %4d", input_state->at(i)->reg_num());
3459       } else {
3460         tty->print("   __");
3461       }
3462     }
3463     tty->cr();
3464     tty->cr();
3465   }
3466 
3467   // process all operations of the block
3468   process_operations(block->lir(), input_state);
3469 
3470   // iterate all successors
3471   for (int i = 0; i < block->number_of_sux(); i++) {
3472     process_successor(block->sux_at(i), input_state);
3473   }
3474 }
3475 
3476 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3477   TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3478 
3479   // must copy state because it is modified
3480   input_state = copy(input_state);
3481 
3482   if (xhandler->entry_code() != NULL) {
3483     process_operations(xhandler->entry_code(), input_state);
3484   }
3485   process_successor(xhandler->entry_block(), input_state);
3486 }
3487 
3488 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3489   IntervalList* saved_state = state_for_block(block);
3490 
3491   if (saved_state != NULL) {
3492     // this block was already processed before.
3493     // check if new input_state is consistent with saved_state
3494 
3495     bool saved_state_correct = true;
3496     for (int i = 0; i < state_size(); i++) {
3497       if (input_state->at(i) != saved_state->at(i)) {
3498         // current input_state and previous saved_state assume a different
3499         // interval in this register -> assume that this register is invalid
3500         if (saved_state->at(i) != NULL) {
3501           // invalidate old calculation only if it assumed that
3502           // register was valid. when the register was already invalid,
3503           // then the old calculation was correct.
3504           saved_state_correct = false;
3505           saved_state->at_put(i, NULL);
3506 
3507           TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3508         }
3509       }
3510     }
3511 
3512     if (saved_state_correct) {
3513       // already processed block with correct input_state
3514       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3515     } else {
3516       // must re-visit this block
3517       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3518       add_to_work_list(block);
3519     }
3520 
3521   } else {
3522     // block was not processed before, so set initial input_state
3523     TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3524 
3525     set_state_for_block(block, copy(input_state));
3526     add_to_work_list(block);
3527   }
3528 }
3529 
3530 
3531 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3532   IntervalList* copy_state = new IntervalList(input_state->length());
3533   copy_state->push_all(input_state);
3534   return copy_state;
3535 }
3536 
3537 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3538   if (reg != LinearScan::any_reg && reg < state_size()) {
3539     if (interval != NULL) {
3540       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = %d", reg, interval->reg_num()));
3541     } else if (input_state->at(reg) != NULL) {
3542       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = NULL", reg));
3543     }
3544 
3545     input_state->at_put(reg, interval);
3546   }
3547 }
3548 
3549 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3550   if (reg != LinearScan::any_reg && reg < state_size()) {
3551     if (input_state->at(reg) != interval) {
3552       tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3553       return true;
3554     }
3555   }
3556   return false;
3557 }
3558 
3559 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3560   // visit all instructions of the block
3561   LIR_OpVisitState visitor;
3562   bool has_error = false;
3563 
3564   for (int i = 0; i < ops->length(); i++) {
3565     LIR_Op* op = ops->at(i);
3566     visitor.visit(op);
3567 
3568     TRACE_LINEAR_SCAN(4, op->print_on(tty));
3569 
3570     // check if input operands are correct
3571     int j;
3572     int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3573     for (j = 0; j < n; j++) {
3574       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3575       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3576         Interval* interval = interval_at(reg_num(opr));
3577         if (op->id() != -1) {
3578           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3579         }
3580 
3581         has_error |= check_state(input_state, interval->assigned_reg(),   interval->split_parent());
3582         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3583 
3584         // When an operand is marked with is_last_use, then the fpu stack allocator
3585         // removes the register from the fpu stack -> the register contains no value
3586         if (opr->is_last_use()) {
3587           state_put(input_state, interval->assigned_reg(),   NULL);
3588           state_put(input_state, interval->assigned_regHi(), NULL);
3589         }
3590       }
3591     }
3592 
3593     // invalidate all caller save registers at calls
3594     if (visitor.has_call()) {
3595       for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3596         state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3597       }
3598       for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3599         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3600       }
3601 
3602 #ifdef X86
3603       for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) {
3604         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3605       }
3606 #endif
3607     }
3608 
3609     // process xhandler before output and temp operands
3610     XHandlers* xhandlers = visitor.all_xhandler();
3611     n = xhandlers->length();
3612     for (int k = 0; k < n; k++) {
3613       process_xhandler(xhandlers->handler_at(k), input_state);
3614     }
3615 
3616     // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3617     n = visitor.opr_count(LIR_OpVisitState::tempMode);
3618     for (j = 0; j < n; j++) {
3619       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3620       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3621         Interval* interval = interval_at(reg_num(opr));
3622         if (op->id() != -1) {
3623           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3624         }
3625 
3626         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3627         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3628       }
3629     }
3630 
3631     // set output operands
3632     n = visitor.opr_count(LIR_OpVisitState::outputMode);
3633     for (j = 0; j < n; j++) {
3634       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3635       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3636         Interval* interval = interval_at(reg_num(opr));
3637         if (op->id() != -1) {
3638           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3639         }
3640 
3641         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3642         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3643       }
3644     }
3645   }
3646   assert(has_error == false, "Error in register allocation");
3647 }
3648 
3649 #endif // ASSERT
3650 
3651 
3652 
3653 // **** Implementation of MoveResolver ******************************
3654 
3655 MoveResolver::MoveResolver(LinearScan* allocator) :
3656   _allocator(allocator),
3657   _multiple_reads_allowed(false),
3658   _mapping_from(8),
3659   _mapping_from_opr(8),
3660   _mapping_to(8),
3661   _insert_list(NULL),
3662   _insert_idx(-1),
3663   _insertion_buffer()
3664 {
3665   for (int i = 0; i < LinearScan::nof_regs; i++) {
3666     _register_blocked[i] = 0;
3667   }
3668   DEBUG_ONLY(check_empty());
3669 }
3670 
3671 
3672 #ifdef ASSERT
3673 
3674 void MoveResolver::check_empty() {
3675   assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3676   for (int i = 0; i < LinearScan::nof_regs; i++) {
3677     assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3678   }
3679   assert(_multiple_reads_allowed == false, "must have default value");
3680 }
3681 
3682 void MoveResolver::verify_before_resolve() {
3683   assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3684   assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3685   assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3686 
3687   int i, j;
3688   if (!_multiple_reads_allowed) {
3689     for (i = 0; i < _mapping_from.length(); i++) {
3690       for (j = i + 1; j < _mapping_from.length(); j++) {
3691         assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3692       }
3693     }
3694   }
3695 
3696   for (i = 0; i < _mapping_to.length(); i++) {
3697     for (j = i + 1; j < _mapping_to.length(); j++) {
3698       assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3699     }
3700   }
3701 
3702 
3703   BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3704   used_regs.clear();
3705   if (!_multiple_reads_allowed) {
3706     for (i = 0; i < _mapping_from.length(); i++) {
3707       Interval* it = _mapping_from.at(i);
3708       if (it != NULL) {
3709         assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3710         used_regs.set_bit(it->assigned_reg());
3711 
3712         if (it->assigned_regHi() != LinearScan::any_reg) {
3713           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3714           used_regs.set_bit(it->assigned_regHi());
3715         }
3716       }
3717     }
3718   }
3719 
3720   used_regs.clear();
3721   for (i = 0; i < _mapping_to.length(); i++) {
3722     Interval* it = _mapping_to.at(i);
3723     assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3724     used_regs.set_bit(it->assigned_reg());
3725 
3726     if (it->assigned_regHi() != LinearScan::any_reg) {
3727       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3728       used_regs.set_bit(it->assigned_regHi());
3729     }
3730   }
3731 
3732   used_regs.clear();
3733   for (i = 0; i < _mapping_from.length(); i++) {
3734     Interval* it = _mapping_from.at(i);
3735     if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3736       used_regs.set_bit(it->assigned_reg());
3737     }
3738   }
3739   for (i = 0; i < _mapping_to.length(); i++) {
3740     Interval* it = _mapping_to.at(i);
3741     assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3742   }
3743 }
3744 
3745 #endif // ASSERT
3746 
3747 
3748 // mark assigned_reg and assigned_regHi of the interval as blocked
3749 void MoveResolver::block_registers(Interval* it) {
3750   int reg = it->assigned_reg();
3751   if (reg < LinearScan::nof_regs) {
3752     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3753     set_register_blocked(reg, 1);
3754   }
3755   reg = it->assigned_regHi();
3756   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3757     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3758     set_register_blocked(reg, 1);
3759   }
3760 }
3761 
3762 // mark assigned_reg and assigned_regHi of the interval as unblocked
3763 void MoveResolver::unblock_registers(Interval* it) {
3764   int reg = it->assigned_reg();
3765   if (reg < LinearScan::nof_regs) {
3766     assert(register_blocked(reg) > 0, "register already marked as unused");
3767     set_register_blocked(reg, -1);
3768   }
3769   reg = it->assigned_regHi();
3770   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3771     assert(register_blocked(reg) > 0, "register already marked as unused");
3772     set_register_blocked(reg, -1);
3773   }
3774 }
3775 
3776 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3777 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3778   int from_reg = -1;
3779   int from_regHi = -1;
3780   if (from != NULL) {
3781     from_reg = from->assigned_reg();
3782     from_regHi = from->assigned_regHi();
3783   }
3784 
3785   int reg = to->assigned_reg();
3786   if (reg < LinearScan::nof_regs) {
3787     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3788       return false;
3789     }
3790   }
3791   reg = to->assigned_regHi();
3792   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3793     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3794       return false;
3795     }
3796   }
3797 
3798   return true;
3799 }
3800 
3801 
3802 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3803   assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3804   _insertion_buffer.init(list);
3805 }
3806 
3807 void MoveResolver::append_insertion_buffer() {
3808   if (_insertion_buffer.initialized()) {
3809     _insertion_buffer.lir_list()->append(&_insertion_buffer);
3810   }
3811   assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3812 
3813   _insert_list = NULL;
3814   _insert_idx = -1;
3815 }
3816 
3817 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3818   assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3819   assert(from_interval->type() == to_interval->type(), "move between different types");
3820   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3821   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3822 
3823   LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
3824   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3825 
3826   if (!_multiple_reads_allowed) {
3827     // the last_use flag is an optimization for FPU stack allocation. When the same
3828     // input interval is used in more than one move, then it is too difficult to determine
3829     // if this move is really the last use.
3830     from_opr = from_opr->make_last_use();
3831   }
3832   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3833 
3834   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3835 }
3836 
3837 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3838   assert(from_opr->type() == to_interval->type(), "move between different types");
3839   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3840   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3841 
3842   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3843   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3844 
3845   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3846 }
3847 
3848 
3849 void MoveResolver::resolve_mappings() {
3850   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3851   DEBUG_ONLY(verify_before_resolve());
3852 
3853   // Block all registers that are used as input operands of a move.
3854   // When a register is blocked, no move to this register is emitted.
3855   // This is necessary for detecting cycles in moves.
3856   int i;
3857   for (i = _mapping_from.length() - 1; i >= 0; i--) {
3858     Interval* from_interval = _mapping_from.at(i);
3859     if (from_interval != NULL) {
3860       block_registers(from_interval);
3861     }
3862   }
3863 
3864   int spill_candidate = -1;
3865   while (_mapping_from.length() > 0) {
3866     bool processed_interval = false;
3867 
3868     for (i = _mapping_from.length() - 1; i >= 0; i--) {
3869       Interval* from_interval = _mapping_from.at(i);
3870       Interval* to_interval = _mapping_to.at(i);
3871 
3872       if (save_to_process_move(from_interval, to_interval)) {
3873         // this inverval can be processed because target is free
3874         if (from_interval != NULL) {
3875           insert_move(from_interval, to_interval);
3876           unblock_registers(from_interval);
3877         } else {
3878           insert_move(_mapping_from_opr.at(i), to_interval);
3879         }
3880         _mapping_from.remove_at(i);
3881         _mapping_from_opr.remove_at(i);
3882         _mapping_to.remove_at(i);
3883 
3884         processed_interval = true;
3885       } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
3886         // this interval cannot be processed now because target is not free
3887         // it starts in a register, so it is a possible candidate for spilling
3888         spill_candidate = i;
3889       }
3890     }
3891 
3892     if (!processed_interval) {
3893       // no move could be processed because there is a cycle in the move list
3894       // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
3895       assert(spill_candidate != -1, "no interval in register for spilling found");
3896 
3897       // create a new spill interval and assign a stack slot to it
3898       Interval* from_interval = _mapping_from.at(spill_candidate);
3899       Interval* spill_interval = new Interval(-1);
3900       spill_interval->set_type(from_interval->type());
3901 
3902       // add a dummy range because real position is difficult to calculate
3903       // Note: this range is a special case when the integrity of the allocation is checked
3904       spill_interval->add_range(1, 2);
3905 
3906       //       do not allocate a new spill slot for temporary interval, but
3907       //       use spill slot assigned to from_interval. Otherwise moves from
3908       //       one stack slot to another can happen (not allowed by LIR_Assembler
3909       int spill_slot = from_interval->canonical_spill_slot();
3910       if (spill_slot < 0) {
3911         spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
3912         from_interval->set_canonical_spill_slot(spill_slot);
3913       }
3914       spill_interval->assign_reg(spill_slot);
3915       allocator()->append_interval(spill_interval);
3916 
3917       TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
3918 
3919       // insert a move from register to stack and update the mapping
3920       insert_move(from_interval, spill_interval);
3921       _mapping_from.at_put(spill_candidate, spill_interval);
3922       unblock_registers(from_interval);
3923     }
3924   }
3925 
3926   // reset to default value
3927   _multiple_reads_allowed = false;
3928 
3929   // check that all intervals have been processed
3930   DEBUG_ONLY(check_empty());
3931 }
3932 
3933 
3934 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
3935   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3936   assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
3937 
3938   create_insertion_buffer(insert_list);
3939   _insert_list = insert_list;
3940   _insert_idx = insert_idx;
3941 }
3942 
3943 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
3944   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3945 
3946   if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
3947     // insert position changed -> resolve current mappings
3948     resolve_mappings();
3949   }
3950 
3951   if (insert_list != _insert_list) {
3952     // block changed -> append insertion_buffer because it is
3953     // bound to a specific block and create a new insertion_buffer
3954     append_insertion_buffer();
3955     create_insertion_buffer(insert_list);
3956   }
3957 
3958   _insert_list = insert_list;
3959   _insert_idx = insert_idx;
3960 }
3961 
3962 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
3963   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3964 
3965   _mapping_from.append(from_interval);
3966   _mapping_from_opr.append(LIR_OprFact::illegalOpr);
3967   _mapping_to.append(to_interval);
3968 }
3969 
3970 
3971 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
3972   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3973   assert(from_opr->is_constant(), "only for constants");
3974 
3975   _mapping_from.append(NULL);
3976   _mapping_from_opr.append(from_opr);
3977   _mapping_to.append(to_interval);
3978 }
3979 
3980 void MoveResolver::resolve_and_append_moves() {
3981   if (has_mappings()) {
3982     resolve_mappings();
3983   }
3984   append_insertion_buffer();
3985 }
3986 
3987 
3988 
3989 // **** Implementation of Range *************************************
3990 
3991 Range::Range(int from, int to, Range* next) :
3992   _from(from),
3993   _to(to),
3994   _next(next)
3995 {
3996 }
3997 
3998 // initialize sentinel
3999 Range* Range::_end = NULL;
4000 void Range::initialize(Arena* arena) {
4001   _end = new (arena) Range(max_jint, max_jint, NULL);
4002 }
4003 
4004 int Range::intersects_at(Range* r2) const {
4005   const Range* r1 = this;
4006 
4007   assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4008   assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4009 
4010   do {
4011     if (r1->from() < r2->from()) {
4012       if (r1->to() <= r2->from()) {
4013         r1 = r1->next(); if (r1 == _end) return -1;
4014       } else {
4015         return r2->from();
4016       }
4017     } else if (r2->from() < r1->from()) {
4018       if (r2->to() <= r1->from()) {
4019         r2 = r2->next(); if (r2 == _end) return -1;
4020       } else {
4021         return r1->from();
4022       }
4023     } else { // r1->from() == r2->from()
4024       if (r1->from() == r1->to()) {
4025         r1 = r1->next(); if (r1 == _end) return -1;
4026       } else if (r2->from() == r2->to()) {
4027         r2 = r2->next(); if (r2 == _end) return -1;
4028       } else {
4029         return r1->from();
4030       }
4031     }
4032   } while (true);
4033 }
4034 
4035 #ifndef PRODUCT
4036 void Range::print(outputStream* out) const {
4037   out->print("[%d, %d[ ", _from, _to);
4038 }
4039 #endif
4040 
4041 
4042 
4043 // **** Implementation of Interval **********************************
4044 
4045 // initialize sentinel
4046 Interval* Interval::_end = NULL;
4047 void Interval::initialize(Arena* arena) {
4048   Range::initialize(arena);
4049   _end = new (arena) Interval(-1);
4050 }
4051 
4052 Interval::Interval(int reg_num) :
4053   _reg_num(reg_num),
4054   _type(T_ILLEGAL),
4055   _first(Range::end()),
4056   _use_pos_and_kinds(12),
4057   _current(Range::end()),
4058   _next(_end),
4059   _state(invalidState),
4060   _assigned_reg(LinearScan::any_reg),
4061   _assigned_regHi(LinearScan::any_reg),
4062   _cached_to(-1),
4063   _cached_opr(LIR_OprFact::illegalOpr),
4064   _cached_vm_reg(VMRegImpl::Bad()),
4065   _split_children(0),
4066   _canonical_spill_slot(-1),
4067   _insert_move_when_activated(false),
4068   _register_hint(NULL),
4069   _spill_state(noDefinitionFound),
4070   _spill_definition_pos(-1)
4071 {
4072   _split_parent = this;
4073   _current_split_child = this;
4074 }
4075 
4076 int Interval::calc_to() {
4077   assert(_first != Range::end(), "interval has no range");
4078 
4079   Range* r = _first;
4080   while (r->next() != Range::end()) {
4081     r = r->next();
4082   }
4083   return r->to();
4084 }
4085 
4086 
4087 #ifdef ASSERT
4088 // consistency check of split-children
4089 void Interval::check_split_children() {
4090   if (_split_children.length() > 0) {
4091     assert(is_split_parent(), "only split parents can have children");
4092 
4093     for (int i = 0; i < _split_children.length(); i++) {
4094       Interval* i1 = _split_children.at(i);
4095 
4096       assert(i1->split_parent() == this, "not a split child of this interval");
4097       assert(i1->type() == type(), "must be equal for all split children");
4098       assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4099 
4100       for (int j = i + 1; j < _split_children.length(); j++) {
4101         Interval* i2 = _split_children.at(j);
4102 
4103         assert(i1->reg_num() != i2->reg_num(), "same register number");
4104 
4105         if (i1->from() < i2->from()) {
4106           assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4107         } else {
4108           assert(i2->from() < i1->from(), "intervals start at same op_id");
4109           assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4110         }
4111       }
4112     }
4113   }
4114 }
4115 #endif // ASSERT
4116 
4117 Interval* Interval::register_hint(bool search_split_child) const {
4118   if (!search_split_child) {
4119     return _register_hint;
4120   }
4121 
4122   if (_register_hint != NULL) {
4123     assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4124 
4125     if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4126       return _register_hint;
4127 
4128     } else if (_register_hint->_split_children.length() > 0) {
4129       // search the first split child that has a register assigned
4130       int len = _register_hint->_split_children.length();
4131       for (int i = 0; i < len; i++) {
4132         Interval* cur = _register_hint->_split_children.at(i);
4133 
4134         if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4135           return cur;
4136         }
4137       }
4138     }
4139   }
4140 
4141   // no hint interval found that has a register assigned
4142   return NULL;
4143 }
4144 
4145 
4146 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4147   assert(is_split_parent(), "can only be called for split parents");
4148   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4149 
4150   Interval* result;
4151   if (_split_children.length() == 0) {
4152     result = this;
4153   } else {
4154     result = NULL;
4155     int len = _split_children.length();
4156 
4157     // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4158     int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4159 
4160     int i;
4161     for (i = 0; i < len; i++) {
4162       Interval* cur = _split_children.at(i);
4163       if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4164         if (i > 0) {
4165           // exchange current split child to start of list (faster access for next call)
4166           _split_children.at_put(i, _split_children.at(0));
4167           _split_children.at_put(0, cur);
4168         }
4169 
4170         // interval found
4171         result = cur;
4172         break;
4173       }
4174     }
4175 
4176 #ifdef ASSERT
4177     for (i = 0; i < len; i++) {
4178       Interval* tmp = _split_children.at(i);
4179       if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4180         tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4181         result->print();
4182         tmp->print();
4183         assert(false, "two valid result intervals found");
4184       }
4185     }
4186 #endif
4187   }
4188 
4189   assert(result != NULL, "no matching interval found");
4190   assert(result->covers(op_id, mode), "op_id not covered by interval");
4191 
4192   return result;
4193 }
4194 
4195 
4196 // returns the last split child that ends before the given op_id
4197 Interval* Interval::split_child_before_op_id(int op_id) {
4198   assert(op_id >= 0, "invalid op_id");
4199 
4200   Interval* parent = split_parent();
4201   Interval* result = NULL;
4202 
4203   int len = parent->_split_children.length();
4204   assert(len > 0, "no split children available");
4205 
4206   for (int i = len - 1; i >= 0; i--) {
4207     Interval* cur = parent->_split_children.at(i);
4208     if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4209       result = cur;
4210     }
4211   }
4212 
4213   assert(result != NULL, "no split child found");
4214   return result;
4215 }
4216 
4217 
4218 // checks if op_id is covered by any split child
4219 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) {
4220   assert(is_split_parent(), "can only be called for split parents");
4221   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4222 
4223   if (_split_children.length() == 0) {
4224     // simple case if interval was not split
4225     return covers(op_id, mode);
4226 
4227   } else {
4228     // extended case: check all split children
4229     int len = _split_children.length();
4230     for (int i = 0; i < len; i++) {
4231       Interval* cur = _split_children.at(i);
4232       if (cur->covers(op_id, mode)) {
4233         return true;
4234       }
4235     }
4236     return false;
4237   }
4238 }
4239 
4240 
4241 // Note: use positions are sorted descending -> first use has highest index
4242 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4243   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4244 
4245   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4246     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4247       return _use_pos_and_kinds.at(i);
4248     }
4249   }
4250   return max_jint;
4251 }
4252 
4253 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4254   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4255 
4256   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4257     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4258       return _use_pos_and_kinds.at(i);
4259     }
4260   }
4261   return max_jint;
4262 }
4263 
4264 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4265   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4266 
4267   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4268     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4269       return _use_pos_and_kinds.at(i);
4270     }
4271   }
4272   return max_jint;
4273 }
4274 
4275 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4276   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4277 
4278   int prev = 0;
4279   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4280     if (_use_pos_and_kinds.at(i) > from) {
4281       return prev;
4282     }
4283     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4284       prev = _use_pos_and_kinds.at(i);
4285     }
4286   }
4287   return prev;
4288 }
4289 
4290 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4291   assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4292 
4293   // do not add use positions for precolored intervals because
4294   // they are never used
4295   if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4296 #ifdef ASSERT
4297     assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4298     for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4299       assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4300       assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4301       if (i > 0) {
4302         assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4303       }
4304     }
4305 #endif
4306 
4307     // Note: add_use is called in descending order, so list gets sorted
4308     //       automatically by just appending new use positions
4309     int len = _use_pos_and_kinds.length();
4310     if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4311       _use_pos_and_kinds.append(pos);
4312       _use_pos_and_kinds.append(use_kind);
4313     } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4314       assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4315       _use_pos_and_kinds.at_put(len - 1, use_kind);
4316     }
4317   }
4318 }
4319 
4320 void Interval::add_range(int from, int to) {
4321   assert(from < to, "invalid range");
4322   assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4323   assert(from <= first()->to(), "not inserting at begin of interval");
4324 
4325   if (first()->from() <= to) {
4326     // join intersecting ranges
4327     first()->set_from(MIN2(from, first()->from()));
4328     first()->set_to  (MAX2(to,   first()->to()));
4329   } else {
4330     // insert new range
4331     _first = new Range(from, to, first());
4332   }
4333 }
4334 
4335 Interval* Interval::new_split_child() {
4336   // allocate new interval
4337   Interval* result = new Interval(-1);
4338   result->set_type(type());
4339 
4340   Interval* parent = split_parent();
4341   result->_split_parent = parent;
4342   result->set_register_hint(parent);
4343 
4344   // insert new interval in children-list of parent
4345   if (parent->_split_children.length() == 0) {
4346     assert(is_split_parent(), "list must be initialized at first split");
4347 
4348     parent->_split_children = IntervalList(4);
4349     parent->_split_children.append(this);
4350   }
4351   parent->_split_children.append(result);
4352 
4353   return result;
4354 }
4355 
4356 // split this interval at the specified position and return
4357 // the remainder as a new interval.
4358 //
4359 // when an interval is split, a bi-directional link is established between the original interval
4360 // (the split parent) and the intervals that are split off this interval (the split children)
4361 // When a split child is split again, the new created interval is also a direct child
4362 // of the original parent (there is no tree of split children stored, but a flat list)
4363 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4364 //
4365 // Note: The new interval has no valid reg_num
4366 Interval* Interval::split(int split_pos) {
4367   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4368 
4369   // allocate new interval
4370   Interval* result = new_split_child();
4371 
4372   // split the ranges
4373   Range* prev = NULL;
4374   Range* cur = _first;
4375   while (cur != Range::end() && cur->to() <= split_pos) {
4376     prev = cur;
4377     cur = cur->next();
4378   }
4379   assert(cur != Range::end(), "split interval after end of last range");
4380 
4381   if (cur->from() < split_pos) {
4382     result->_first = new Range(split_pos, cur->to(), cur->next());
4383     cur->set_to(split_pos);
4384     cur->set_next(Range::end());
4385 
4386   } else {
4387     assert(prev != NULL, "split before start of first range");
4388     result->_first = cur;
4389     prev->set_next(Range::end());
4390   }
4391   result->_current = result->_first;
4392   _cached_to = -1; // clear cached value
4393 
4394   // split list of use positions
4395   int total_len = _use_pos_and_kinds.length();
4396   int start_idx = total_len - 2;
4397   while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4398     start_idx -= 2;
4399   }
4400 
4401   intStack new_use_pos_and_kinds(total_len - start_idx);
4402   int i;
4403   for (i = start_idx + 2; i < total_len; i++) {
4404     new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4405   }
4406 
4407   _use_pos_and_kinds.truncate(start_idx + 2);
4408   result->_use_pos_and_kinds = _use_pos_and_kinds;
4409   _use_pos_and_kinds = new_use_pos_and_kinds;
4410 
4411 #ifdef ASSERT
4412   assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4413   assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4414   assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4415 
4416   for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4417     assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4418     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4419   }
4420   for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4421     assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4422     assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4423   }
4424 #endif
4425 
4426   return result;
4427 }
4428 
4429 // split this interval at the specified position and return
4430 // the head as a new interval (the original interval is the tail)
4431 //
4432 // Currently, only the first range can be split, and the new interval
4433 // must not have split positions
4434 Interval* Interval::split_from_start(int split_pos) {
4435   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4436   assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4437   assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4438   assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4439 
4440   // allocate new interval
4441   Interval* result = new_split_child();
4442 
4443   // the new created interval has only one range (checked by assertion above),
4444   // so the splitting of the ranges is very simple
4445   result->add_range(_first->from(), split_pos);
4446 
4447   if (split_pos == _first->to()) {
4448     assert(_first->next() != Range::end(), "must not be at end");
4449     _first = _first->next();
4450   } else {
4451     _first->set_from(split_pos);
4452   }
4453 
4454   return result;
4455 }
4456 
4457 
4458 // returns true if the op_id is inside the interval
4459 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4460   Range* cur  = _first;
4461 
4462   while (cur != Range::end() && cur->to() < op_id) {
4463     cur = cur->next();
4464   }
4465   if (cur != Range::end()) {
4466     assert(cur->to() != cur->next()->from(), "ranges not separated");
4467 
4468     if (mode == LIR_OpVisitState::outputMode) {
4469       return cur->from() <= op_id && op_id < cur->to();
4470     } else {
4471       return cur->from() <= op_id && op_id <= cur->to();
4472     }
4473   }
4474   return false;
4475 }
4476 
4477 // returns true if the interval has any hole between hole_from and hole_to
4478 // (even if the hole has only the length 1)
4479 bool Interval::has_hole_between(int hole_from, int hole_to) {
4480   assert(hole_from < hole_to, "check");
4481   assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4482 
4483   Range* cur  = _first;
4484   while (cur != Range::end()) {
4485     assert(cur->to() < cur->next()->from(), "no space between ranges");
4486 
4487     // hole-range starts before this range -> hole
4488     if (hole_from < cur->from()) {
4489       return true;
4490 
4491     // hole-range completely inside this range -> no hole
4492     } else if (hole_to <= cur->to()) {
4493       return false;
4494 
4495     // overlapping of hole-range with this range -> hole
4496     } else if (hole_from <= cur->to()) {
4497       return true;
4498     }
4499 
4500     cur = cur->next();
4501   }
4502 
4503   return false;
4504 }
4505 
4506 
4507 #ifndef PRODUCT
4508 void Interval::print(outputStream* out) const {
4509   const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4510   const char* UseKind2Name[] = { "N", "L", "S", "M" };
4511 
4512   const char* type_name;
4513   LIR_Opr opr = LIR_OprFact::illegal();
4514   if (reg_num() < LIR_OprDesc::vreg_base) {
4515     type_name = "fixed";
4516     // need a temporary operand for fixed intervals because type() cannot be called
4517     if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4518       opr = LIR_OprFact::single_cpu(assigned_reg());
4519     } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4520       opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4521 #ifdef X86
4522     } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) {
4523       opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4524 #endif
4525     } else {
4526       ShouldNotReachHere();
4527     }
4528   } else {
4529     type_name = type2name(type());
4530     if (assigned_reg() != -1 &&
4531         (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4532       opr = LinearScan::calc_operand_for_interval(this);
4533     }
4534   }
4535 
4536   out->print("%d %s ", reg_num(), type_name);
4537   if (opr->is_valid()) {
4538     out->print("\"");
4539     opr->print(out);
4540     out->print("\" ");
4541   }
4542   out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4543 
4544   // print ranges
4545   Range* cur = _first;
4546   while (cur != Range::end()) {
4547     cur->print(out);
4548     cur = cur->next();
4549     assert(cur != NULL, "range list not closed with range sentinel");
4550   }
4551 
4552   // print use positions
4553   int prev = 0;
4554   assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4555   for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4556     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4557     assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4558 
4559     out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4560     prev = _use_pos_and_kinds.at(i);
4561   }
4562 
4563   out->print(" \"%s\"", SpillState2Name[spill_state()]);
4564   out->cr();
4565 }
4566 #endif
4567 
4568 
4569 
4570 // **** Implementation of IntervalWalker ****************************
4571 
4572 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4573  : _compilation(allocator->compilation())
4574  , _allocator(allocator)
4575 {
4576   _unhandled_first[fixedKind] = unhandled_fixed_first;
4577   _unhandled_first[anyKind]   = unhandled_any_first;
4578   _active_first[fixedKind]    = Interval::end();
4579   _inactive_first[fixedKind]  = Interval::end();
4580   _active_first[anyKind]      = Interval::end();
4581   _inactive_first[anyKind]    = Interval::end();
4582   _current_position = -1;
4583   _current = NULL;
4584   next_interval();
4585 }
4586 
4587 
4588 // append interval at top of list
4589 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) {
4590   interval->set_next(*list); *list = interval;
4591 }
4592 
4593 
4594 // append interval in order of current range from()
4595 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4596   Interval* prev = NULL;
4597   Interval* cur  = *list;
4598   while (cur->current_from() < interval->current_from()) {
4599     prev = cur; cur = cur->next();
4600   }
4601   if (prev == NULL) {
4602     *list = interval;
4603   } else {
4604     prev->set_next(interval);
4605   }
4606   interval->set_next(cur);
4607 }
4608 
4609 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4610   assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4611 
4612   Interval* prev = NULL;
4613   Interval* cur  = *list;
4614   while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4615     prev = cur; cur = cur->next();
4616   }
4617   if (prev == NULL) {
4618     *list = interval;
4619   } else {
4620     prev->set_next(interval);
4621   }
4622   interval->set_next(cur);
4623 }
4624 
4625 
4626 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4627   while (*list != Interval::end() && *list != i) {
4628     list = (*list)->next_addr();
4629   }
4630   if (*list != Interval::end()) {
4631     assert(*list == i, "check");
4632     *list = (*list)->next();
4633     return true;
4634   } else {
4635     return false;
4636   }
4637 }
4638 
4639 void IntervalWalker::remove_from_list(Interval* i) {
4640   bool deleted;
4641 
4642   if (i->state() == activeState) {
4643     deleted = remove_from_list(active_first_addr(anyKind), i);
4644   } else {
4645     assert(i->state() == inactiveState, "invalid state");
4646     deleted = remove_from_list(inactive_first_addr(anyKind), i);
4647   }
4648 
4649   assert(deleted, "interval has not been found in list");
4650 }
4651 
4652 
4653 void IntervalWalker::walk_to(IntervalState state, int from) {
4654   assert (state == activeState || state == inactiveState, "wrong state");
4655   for_each_interval_kind(kind) {
4656     Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4657     Interval* next   = *prev;
4658     while (next->current_from() <= from) {
4659       Interval* cur = next;
4660       next = cur->next();
4661 
4662       bool range_has_changed = false;
4663       while (cur->current_to() <= from) {
4664         cur->next_range();
4665         range_has_changed = true;
4666       }
4667 
4668       // also handle move from inactive list to active list
4669       range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4670 
4671       if (range_has_changed) {
4672         // remove cur from list
4673         *prev = next;
4674         if (cur->current_at_end()) {
4675           // move to handled state (not maintained as a list)
4676           cur->set_state(handledState);
4677           interval_moved(cur, kind, state, handledState);
4678         } else if (cur->current_from() <= from){
4679           // sort into active list
4680           append_sorted(active_first_addr(kind), cur);
4681           cur->set_state(activeState);
4682           if (*prev == cur) {
4683             assert(state == activeState, "check");
4684             prev = cur->next_addr();
4685           }
4686           interval_moved(cur, kind, state, activeState);
4687         } else {
4688           // sort into inactive list
4689           append_sorted(inactive_first_addr(kind), cur);
4690           cur->set_state(inactiveState);
4691           if (*prev == cur) {
4692             assert(state == inactiveState, "check");
4693             prev = cur->next_addr();
4694           }
4695           interval_moved(cur, kind, state, inactiveState);
4696         }
4697       } else {
4698         prev = cur->next_addr();
4699         continue;
4700       }
4701     }
4702   }
4703 }
4704 
4705 
4706 void IntervalWalker::next_interval() {
4707   IntervalKind kind;
4708   Interval* any   = _unhandled_first[anyKind];
4709   Interval* fixed = _unhandled_first[fixedKind];
4710 
4711   if (any != Interval::end()) {
4712     // intervals may start at same position -> prefer fixed interval
4713     kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4714 
4715     assert (kind == fixedKind && fixed->from() <= any->from() ||
4716             kind == anyKind   && any->from() <= fixed->from(), "wrong interval!!!");
4717     assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4718 
4719   } else if (fixed != Interval::end()) {
4720     kind = fixedKind;
4721   } else {
4722     _current = NULL; return;
4723   }
4724   _current_kind = kind;
4725   _current = _unhandled_first[kind];
4726   _unhandled_first[kind] = _current->next();
4727   _current->set_next(Interval::end());
4728   _current->rewind_range();
4729 }
4730 
4731 
4732 void IntervalWalker::walk_to(int lir_op_id) {
4733   assert(_current_position <= lir_op_id, "can not walk backwards");
4734   while (current() != NULL) {
4735     bool is_active = current()->from() <= lir_op_id;
4736     int id = is_active ? current()->from() : lir_op_id;
4737 
4738     TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4739 
4740     // set _current_position prior to call of walk_to
4741     _current_position = id;
4742 
4743     // call walk_to even if _current_position == id
4744     walk_to(activeState, id);
4745     walk_to(inactiveState, id);
4746 
4747     if (is_active) {
4748       current()->set_state(activeState);
4749       if (activate_current()) {
4750         append_sorted(active_first_addr(current_kind()), current());
4751         interval_moved(current(), current_kind(), unhandledState, activeState);
4752       }
4753 
4754       next_interval();
4755     } else {
4756       return;
4757     }
4758   }
4759 }
4760 
4761 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4762 #ifndef PRODUCT
4763   if (TraceLinearScanLevel >= 4) {
4764     #define print_state(state) \
4765     switch(state) {\
4766       case unhandledState: tty->print("unhandled"); break;\
4767       case activeState: tty->print("active"); break;\
4768       case inactiveState: tty->print("inactive"); break;\
4769       case handledState: tty->print("handled"); break;\
4770       default: ShouldNotReachHere(); \
4771     }
4772 
4773     print_state(from); tty->print(" to "); print_state(to);
4774     tty->fill_to(23);
4775     interval->print();
4776 
4777     #undef print_state
4778   }
4779 #endif
4780 }
4781 
4782 
4783 
4784 // **** Implementation of LinearScanWalker **************************
4785 
4786 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4787   : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4788   , _move_resolver(allocator)
4789 {
4790   for (int i = 0; i < LinearScan::nof_regs; i++) {
4791     _spill_intervals[i] = new IntervalList(2);
4792   }
4793 }
4794 
4795 
4796 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4797   for (int i = _first_reg; i <= _last_reg; i++) {
4798     _use_pos[i] = max_jint;
4799 
4800     if (!only_process_use_pos) {
4801       _block_pos[i] = max_jint;
4802       _spill_intervals[i]->clear();
4803     }
4804   }
4805 }
4806 
4807 inline void LinearScanWalker::exclude_from_use(int reg) {
4808   assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4809   if (reg >= _first_reg && reg <= _last_reg) {
4810     _use_pos[reg] = 0;
4811   }
4812 }
4813 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4814   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4815 
4816   exclude_from_use(i->assigned_reg());
4817   exclude_from_use(i->assigned_regHi());
4818 }
4819 
4820 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4821   assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4822 
4823   if (reg >= _first_reg && reg <= _last_reg) {
4824     if (_use_pos[reg] > use_pos) {
4825       _use_pos[reg] = use_pos;
4826     }
4827     if (!only_process_use_pos) {
4828       _spill_intervals[reg]->append(i);
4829     }
4830   }
4831 }
4832 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4833   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4834   if (use_pos != -1) {
4835     set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4836     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4837   }
4838 }
4839 
4840 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4841   if (reg >= _first_reg && reg <= _last_reg) {
4842     if (_block_pos[reg] > block_pos) {
4843       _block_pos[reg] = block_pos;
4844     }
4845     if (_use_pos[reg] > block_pos) {
4846       _use_pos[reg] = block_pos;
4847     }
4848   }
4849 }
4850 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4851   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4852   if (block_pos != -1) {
4853     set_block_pos(i->assigned_reg(), i, block_pos);
4854     set_block_pos(i->assigned_regHi(), i, block_pos);
4855   }
4856 }
4857 
4858 
4859 void LinearScanWalker::free_exclude_active_fixed() {
4860   Interval* list = active_first(fixedKind);
4861   while (list != Interval::end()) {
4862     assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4863     exclude_from_use(list);
4864     list = list->next();
4865   }
4866 }
4867 
4868 void LinearScanWalker::free_exclude_active_any() {
4869   Interval* list = active_first(anyKind);
4870   while (list != Interval::end()) {
4871     exclude_from_use(list);
4872     list = list->next();
4873   }
4874 }
4875 
4876 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
4877   Interval* list = inactive_first(fixedKind);
4878   while (list != Interval::end()) {
4879     if (cur->to() <= list->current_from()) {
4880       assert(list->current_intersects_at(cur) == -1, "must not intersect");
4881       set_use_pos(list, list->current_from(), true);
4882     } else {
4883       set_use_pos(list, list->current_intersects_at(cur), true);
4884     }
4885     list = list->next();
4886   }
4887 }
4888 
4889 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
4890   Interval* list = inactive_first(anyKind);
4891   while (list != Interval::end()) {
4892     set_use_pos(list, list->current_intersects_at(cur), true);
4893     list = list->next();
4894   }
4895 }
4896 
4897 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) {
4898   Interval* list = unhandled_first(kind);
4899   while (list != Interval::end()) {
4900     set_use_pos(list, list->intersects_at(cur), true);
4901     if (kind == fixedKind && cur->to() <= list->from()) {
4902       set_use_pos(list, list->from(), true);
4903     }
4904     list = list->next();
4905   }
4906 }
4907 
4908 void LinearScanWalker::spill_exclude_active_fixed() {
4909   Interval* list = active_first(fixedKind);
4910   while (list != Interval::end()) {
4911     exclude_from_use(list);
4912     list = list->next();
4913   }
4914 }
4915 
4916 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) {
4917   Interval* list = unhandled_first(fixedKind);
4918   while (list != Interval::end()) {
4919     set_block_pos(list, list->intersects_at(cur));
4920     list = list->next();
4921   }
4922 }
4923 
4924 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
4925   Interval* list = inactive_first(fixedKind);
4926   while (list != Interval::end()) {
4927     if (cur->to() > list->current_from()) {
4928       set_block_pos(list, list->current_intersects_at(cur));
4929     } else {
4930       assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
4931     }
4932 
4933     list = list->next();
4934   }
4935 }
4936 
4937 void LinearScanWalker::spill_collect_active_any() {
4938   Interval* list = active_first(anyKind);
4939   while (list != Interval::end()) {
4940     set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4941     list = list->next();
4942   }
4943 }
4944 
4945 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
4946   Interval* list = inactive_first(anyKind);
4947   while (list != Interval::end()) {
4948     if (list->current_intersects(cur)) {
4949       set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4950     }
4951     list = list->next();
4952   }
4953 }
4954 
4955 
4956 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
4957   // output all moves here. When source and target are equal, the move is
4958   // optimized away later in assign_reg_nums
4959 
4960   op_id = (op_id + 1) & ~1;
4961   BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
4962   assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
4963 
4964   // calculate index of instruction inside instruction list of current block
4965   // the minimal index (for a block with no spill moves) can be calculated because the
4966   // numbering of instructions is known.
4967   // When the block already contains spill moves, the index must be increased until the
4968   // correct index is reached.
4969   LIR_OpList* list = op_block->lir()->instructions_list();
4970   int index = (op_id - list->at(0)->id()) / 2;
4971   assert(list->at(index)->id() <= op_id, "error in calculation");
4972 
4973   while (list->at(index)->id() != op_id) {
4974     index++;
4975     assert(0 <= index && index < list->length(), "index out of bounds");
4976   }
4977   assert(1 <= index && index < list->length(), "index out of bounds");
4978   assert(list->at(index)->id() == op_id, "error in calculation");
4979 
4980   // insert new instruction before instruction at position index
4981   _move_resolver.move_insert_position(op_block->lir(), index - 1);
4982   _move_resolver.add_mapping(src_it, dst_it);
4983 }
4984 
4985 
4986 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
4987   int from_block_nr = min_block->linear_scan_number();
4988   int to_block_nr = max_block->linear_scan_number();
4989 
4990   assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
4991   assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
4992   assert(from_block_nr < to_block_nr, "must cross block boundary");
4993 
4994   // Try to split at end of max_block. If this would be after
4995   // max_split_pos, then use the begin of max_block
4996   int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
4997   if (optimal_split_pos > max_split_pos) {
4998     optimal_split_pos = max_block->first_lir_instruction_id();
4999   }
5000 
5001   int min_loop_depth = max_block->loop_depth();
5002   for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5003     BlockBegin* cur = block_at(i);
5004 
5005     if (cur->loop_depth() < min_loop_depth) {
5006       // block with lower loop-depth found -> split at the end of this block
5007       min_loop_depth = cur->loop_depth();
5008       optimal_split_pos = cur->last_lir_instruction_id() + 2;
5009     }
5010   }
5011   assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5012 
5013   return optimal_split_pos;
5014 }
5015 
5016 
5017 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5018   int optimal_split_pos = -1;
5019   if (min_split_pos == max_split_pos) {
5020     // trivial case, no optimization of split position possible
5021     TRACE_LINEAR_SCAN(4, tty->print_cr("      min-pos and max-pos are equal, no optimization possible"));
5022     optimal_split_pos = min_split_pos;
5023 
5024   } else {
5025     assert(min_split_pos < max_split_pos, "must be true then");
5026     assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5027 
5028     // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5029     // beginning of a block, then min_split_pos is also a possible split position.
5030     // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5031     BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5032 
5033     // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5034     // when an interval ends at the end of the last block of the method
5035     // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5036     // block at this op_id)
5037     BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5038 
5039     assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5040     if (min_block == max_block) {
5041       // split position cannot be moved to block boundary, so split as late as possible
5042       TRACE_LINEAR_SCAN(4, tty->print_cr("      cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5043       optimal_split_pos = max_split_pos;
5044 
5045     } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5046       // Do not move split position if the interval has a hole before max_split_pos.
5047       // Intervals resulting from Phi-Functions have more than one definition (marked
5048       // as mustHaveRegister) with a hole before each definition. When the register is needed
5049       // for the second definition, an earlier reloading is unnecessary.
5050       TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has hole just before max_split_pos, so splitting at max_split_pos"));
5051       optimal_split_pos = max_split_pos;
5052 
5053     } else {
5054       // seach optimal block boundary between min_split_pos and max_split_pos
5055       TRACE_LINEAR_SCAN(4, tty->print_cr("      moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5056 
5057       if (do_loop_optimization) {
5058         // Loop optimization: if a loop-end marker is found between min- and max-position,
5059         // then split before this loop
5060         int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5061         TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization: loop end found at pos %d", loop_end_pos));
5062 
5063         assert(loop_end_pos > min_split_pos, "invalid order");
5064         if (loop_end_pos < max_split_pos) {
5065           // loop-end marker found between min- and max-position
5066           // if it is not the end marker for the same loop as the min-position, then move
5067           // the max-position to this loop block.
5068           // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5069           // of the interval (normally, only mustHaveRegister causes a reloading)
5070           BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5071 
5072           TRACE_LINEAR_SCAN(4, tty->print_cr("      interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5073           assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5074 
5075           optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5076           if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5077             optimal_split_pos = -1;
5078             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization not necessary"));
5079           } else {
5080             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization successful"));
5081           }
5082         }
5083       }
5084 
5085       if (optimal_split_pos == -1) {
5086         // not calculated by loop optimization
5087         optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5088       }
5089     }
5090   }
5091   TRACE_LINEAR_SCAN(4, tty->print_cr("      optimal split position: %d", optimal_split_pos));
5092 
5093   return optimal_split_pos;
5094 }
5095 
5096 
5097 /*
5098   split an interval at the optimal position between min_split_pos and
5099   max_split_pos in two parts:
5100   1) the left part has already a location assigned
5101   2) the right part is sorted into to the unhandled-list
5102 */
5103 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5104   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting interval: "); it->print());
5105   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5106 
5107   assert(it->from() < min_split_pos,         "cannot split at start of interval");
5108   assert(current_position() < min_split_pos, "cannot split before current position");
5109   assert(min_split_pos <= max_split_pos,     "invalid order");
5110   assert(max_split_pos <= it->to(),          "cannot split after end of interval");
5111 
5112   int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5113 
5114   assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5115   assert(optimal_split_pos <= it->to(),  "cannot split after end of interval");
5116   assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5117 
5118   if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5119     // the split position would be just before the end of the interval
5120     // -> no split at all necessary
5121     TRACE_LINEAR_SCAN(4, tty->print_cr("      no split necessary because optimal split position is at end of interval"));
5122     return;
5123   }
5124 
5125   // must calculate this before the actual split is performed and before split position is moved to odd op_id
5126   bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5127 
5128   if (!allocator()->is_block_begin(optimal_split_pos)) {
5129     // move position before actual instruction (odd op_id)
5130     optimal_split_pos = (optimal_split_pos - 1) | 1;
5131   }
5132 
5133   TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5134   assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5135   assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5136 
5137   Interval* split_part = it->split(optimal_split_pos);
5138 
5139   allocator()->append_interval(split_part);
5140   allocator()->copy_register_flags(it, split_part);
5141   split_part->set_insert_move_when_activated(move_necessary);
5142   append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5143 
5144   TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5145   TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5146   TRACE_LINEAR_SCAN(2, tty->print   ("      "); split_part->print());
5147 }
5148 
5149 /*
5150   split an interval at the optimal position between min_split_pos and
5151   max_split_pos in two parts:
5152   1) the left part has already a location assigned
5153   2) the right part is always on the stack and therefore ignored in further processing
5154 */
5155 void LinearScanWalker::split_for_spilling(Interval* it) {
5156   // calculate allowed range of splitting position
5157   int max_split_pos = current_position();
5158   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5159 
5160   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting and spilling interval: "); it->print());
5161   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5162 
5163   assert(it->state() == activeState,     "why spill interval that is not active?");
5164   assert(it->from() <= min_split_pos,    "cannot split before start of interval");
5165   assert(min_split_pos <= max_split_pos, "invalid order");
5166   assert(max_split_pos < it->to(),       "cannot split at end end of interval");
5167   assert(current_position() < it->to(),  "interval must not end before current position");
5168 
5169   if (min_split_pos == it->from()) {
5170     // the whole interval is never used, so spill it entirely to memory
5171     TRACE_LINEAR_SCAN(2, tty->print_cr("      spilling entire interval because split pos is at beginning of interval"));
5172     assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5173 
5174     allocator()->assign_spill_slot(it);
5175     allocator()->change_spill_state(it, min_split_pos);
5176 
5177     // Also kick parent intervals out of register to memory when they have no use
5178     // position. This avoids short interval in register surrounded by intervals in
5179     // memory -> avoid useless moves from memory to register and back
5180     Interval* parent = it;
5181     while (parent != NULL && parent->is_split_child()) {
5182       parent = parent->split_child_before_op_id(parent->from());
5183 
5184       if (parent->assigned_reg() < LinearScan::nof_regs) {
5185         if (parent->first_usage(shouldHaveRegister) == max_jint) {
5186           // parent is never used, so kick it out of its assigned register
5187           TRACE_LINEAR_SCAN(4, tty->print_cr("      kicking out interval %d out of its register because it is never used", parent->reg_num()));
5188           allocator()->assign_spill_slot(parent);
5189         } else {
5190           // do not go further back because the register is actually used by the interval
5191           parent = NULL;
5192         }
5193       }
5194     }
5195 
5196   } else {
5197     // search optimal split pos, split interval and spill only the right hand part
5198     int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5199 
5200     assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5201     assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5202     assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5203 
5204     if (!allocator()->is_block_begin(optimal_split_pos)) {
5205       // move position before actual instruction (odd op_id)
5206       optimal_split_pos = (optimal_split_pos - 1) | 1;
5207     }
5208 
5209     TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5210     assert(allocator()->is_block_begin(optimal_split_pos)  || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5211     assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5212 
5213     Interval* spilled_part = it->split(optimal_split_pos);
5214     allocator()->append_interval(spilled_part);
5215     allocator()->assign_spill_slot(spilled_part);
5216     allocator()->change_spill_state(spilled_part, optimal_split_pos);
5217 
5218     if (!allocator()->is_block_begin(optimal_split_pos)) {
5219       TRACE_LINEAR_SCAN(4, tty->print_cr("      inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5220       insert_move(optimal_split_pos, it, spilled_part);
5221     }
5222 
5223     // the current_split_child is needed later when moves are inserted for reloading
5224     assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5225     spilled_part->make_current_split_child();
5226 
5227     TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts"));
5228     TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5229     TRACE_LINEAR_SCAN(2, tty->print   ("      "); spilled_part->print());
5230   }
5231 }
5232 
5233 
5234 void LinearScanWalker::split_stack_interval(Interval* it) {
5235   int min_split_pos = current_position() + 1;
5236   int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5237 
5238   split_before_usage(it, min_split_pos, max_split_pos);
5239 }
5240 
5241 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5242   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5243   int max_split_pos = register_available_until;
5244 
5245   split_before_usage(it, min_split_pos, max_split_pos);
5246 }
5247 
5248 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5249   assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5250 
5251   int current_pos = current_position();
5252   if (it->state() == inactiveState) {
5253     // the interval is currently inactive, so no spill slot is needed for now.
5254     // when the split part is activated, the interval has a new chance to get a register,
5255     // so in the best case no stack slot is necessary
5256     assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5257     split_before_usage(it, current_pos + 1, current_pos + 1);
5258 
5259   } else {
5260     // search the position where the interval must have a register and split
5261     // at the optimal position before.
5262     // The new created part is added to the unhandled list and will get a register
5263     // when it is activated
5264     int min_split_pos = current_pos + 1;
5265     int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5266 
5267     split_before_usage(it, min_split_pos, max_split_pos);
5268 
5269     assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5270     split_for_spilling(it);
5271   }
5272 }
5273 
5274 
5275 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5276   int min_full_reg = any_reg;
5277   int max_partial_reg = any_reg;
5278 
5279   for (int i = _first_reg; i <= _last_reg; i++) {
5280     if (i == ignore_reg) {
5281       // this register must be ignored
5282 
5283     } else if (_use_pos[i] >= interval_to) {
5284       // this register is free for the full interval
5285       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5286         min_full_reg = i;
5287       }
5288     } else if (_use_pos[i] > reg_needed_until) {
5289       // this register is at least free until reg_needed_until
5290       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5291         max_partial_reg = i;
5292       }
5293     }
5294   }
5295 
5296   if (min_full_reg != any_reg) {
5297     return min_full_reg;
5298   } else if (max_partial_reg != any_reg) {
5299     *need_split = true;
5300     return max_partial_reg;
5301   } else {
5302     return any_reg;
5303   }
5304 }
5305 
5306 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5307   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5308 
5309   int min_full_reg = any_reg;
5310   int max_partial_reg = any_reg;
5311 
5312   for (int i = _first_reg; i < _last_reg; i+=2) {
5313     if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5314       // this register is free for the full interval
5315       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5316         min_full_reg = i;
5317       }
5318     } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5319       // this register is at least free until reg_needed_until
5320       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5321         max_partial_reg = i;
5322       }
5323     }
5324   }
5325 
5326   if (min_full_reg != any_reg) {
5327     return min_full_reg;
5328   } else if (max_partial_reg != any_reg) {
5329     *need_split = true;
5330     return max_partial_reg;
5331   } else {
5332     return any_reg;
5333   }
5334 }
5335 
5336 
5337 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5338   TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5339 
5340   init_use_lists(true);
5341   free_exclude_active_fixed();
5342   free_exclude_active_any();
5343   free_collect_inactive_fixed(cur);
5344   free_collect_inactive_any(cur);
5345 //  free_collect_unhandled(fixedKind, cur);
5346   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5347 
5348   // _use_pos contains the start of the next interval that has this register assigned
5349   // (either as a fixed register or a normal allocated register in the past)
5350   // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5351   TRACE_LINEAR_SCAN(4, tty->print_cr("      state of registers:"));
5352   TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr("      reg %d: use_pos: %d", i, _use_pos[i]));
5353 
5354   int hint_reg, hint_regHi;
5355   Interval* register_hint = cur->register_hint();
5356   if (register_hint != NULL) {
5357     hint_reg = register_hint->assigned_reg();
5358     hint_regHi = register_hint->assigned_regHi();
5359 
5360     if (allocator()->is_precolored_cpu_interval(register_hint)) {
5361       assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5362       hint_regHi = hint_reg + 1;  // connect e.g. eax-edx
5363     }
5364     TRACE_LINEAR_SCAN(4, tty->print("      hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
5365 
5366   } else {
5367     hint_reg = any_reg;
5368     hint_regHi = any_reg;
5369   }
5370   assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5371   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5372 
5373   // the register must be free at least until this position
5374   int reg_needed_until = cur->from() + 1;
5375   int interval_to = cur->to();
5376 
5377   bool need_split = false;
5378   int split_pos = -1;
5379   int reg = any_reg;
5380   int regHi = any_reg;
5381 
5382   if (_adjacent_regs) {
5383     reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5384     regHi = reg + 1;
5385     if (reg == any_reg) {
5386       return false;
5387     }
5388     split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5389 
5390   } else {
5391     reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5392     if (reg == any_reg) {
5393       return false;
5394     }
5395     split_pos = _use_pos[reg];
5396 
5397     if (_num_phys_regs == 2) {
5398       regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5399 
5400       if (_use_pos[reg] < interval_to && regHi == any_reg) {
5401         // do not split interval if only one register can be assigned until the split pos
5402         // (when one register is found for the whole interval, split&spill is only
5403         // performed for the hi register)
5404         return false;
5405 
5406       } else if (regHi != any_reg) {
5407         split_pos = MIN2(split_pos, _use_pos[regHi]);
5408 
5409         // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5410         if (reg > regHi) {
5411           int temp = reg;
5412           reg = regHi;
5413           regHi = temp;
5414         }
5415       }
5416     }
5417   }
5418 
5419   cur->assign_reg(reg, regHi);
5420   TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi));
5421 
5422   assert(split_pos > 0, "invalid split_pos");
5423   if (need_split) {
5424     // register not available for full interval, so split it
5425     split_when_partial_register_available(cur, split_pos);
5426   }
5427 
5428   // only return true if interval is completely assigned
5429   return _num_phys_regs == 1 || regHi != any_reg;
5430 }
5431 
5432 
5433 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5434   int max_reg = any_reg;
5435 
5436   for (int i = _first_reg; i <= _last_reg; i++) {
5437     if (i == ignore_reg) {
5438       // this register must be ignored
5439 
5440     } else if (_use_pos[i] > reg_needed_until) {
5441       if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
5442         max_reg = i;
5443       }
5444     }
5445   }
5446 
5447   if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5448     *need_split = true;
5449   }
5450 
5451   return max_reg;
5452 }
5453 
5454 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5455   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5456 
5457   int max_reg = any_reg;
5458 
5459   for (int i = _first_reg; i < _last_reg; i+=2) {
5460     if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5461       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5462         max_reg = i;
5463       }
5464     }
5465   }
5466 
5467   if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) {
5468     *need_split = true;
5469   }
5470 
5471   return max_reg;
5472 }
5473 
5474 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5475   assert(reg != any_reg, "no register assigned");
5476 
5477   for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5478     Interval* it = _spill_intervals[reg]->at(i);
5479     remove_from_list(it);
5480     split_and_spill_interval(it);
5481   }
5482 
5483   if (regHi != any_reg) {
5484     IntervalList* processed = _spill_intervals[reg];
5485     for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5486       Interval* it = _spill_intervals[regHi]->at(i);
5487       if (processed->index_of(it) == -1) {
5488         remove_from_list(it);
5489         split_and_spill_interval(it);
5490       }
5491     }
5492   }
5493 }
5494 
5495 
5496 // Split an Interval and spill it to memory so that cur can be placed in a register
5497 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5498   TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5499 
5500   // collect current usage of registers
5501   init_use_lists(false);
5502   spill_exclude_active_fixed();
5503 //  spill_block_unhandled_fixed(cur);
5504   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5505   spill_block_inactive_fixed(cur);
5506   spill_collect_active_any();
5507   spill_collect_inactive_any(cur);
5508 
5509 #ifndef PRODUCT
5510   if (TraceLinearScanLevel >= 4) {
5511     tty->print_cr("      state of registers:");
5512     for (int i = _first_reg; i <= _last_reg; i++) {
5513       tty->print("      reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]);
5514       for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5515         tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5516       }
5517       tty->cr();
5518     }
5519   }
5520 #endif
5521 
5522   // the register must be free at least until this position
5523   int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5524   int interval_to = cur->to();
5525   assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5526 
5527   int split_pos = 0;
5528   int use_pos = 0;
5529   bool need_split = false;
5530   int reg, regHi;
5531 
5532   if (_adjacent_regs) {
5533     reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split);
5534     regHi = reg + 1;
5535 
5536     if (reg != any_reg) {
5537       use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5538       split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5539     }
5540   } else {
5541     reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split);
5542     regHi = any_reg;
5543 
5544     if (reg != any_reg) {
5545       use_pos = _use_pos[reg];
5546       split_pos = _block_pos[reg];
5547 
5548       if (_num_phys_regs == 2) {
5549         if (cur->assigned_reg() != any_reg) {
5550           regHi = reg;
5551           reg = cur->assigned_reg();
5552         } else {
5553           regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split);
5554           if (regHi != any_reg) {
5555             use_pos = MIN2(use_pos, _use_pos[regHi]);
5556             split_pos = MIN2(split_pos, _block_pos[regHi]);
5557           }
5558         }
5559 
5560         if (regHi != any_reg && reg > regHi) {
5561           // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5562           int temp = reg;
5563           reg = regHi;
5564           regHi = temp;
5565         }
5566       }
5567     }
5568   }
5569 
5570   if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5571     // the first use of cur is later than the spilling position -> spill cur
5572     TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5573 
5574     if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5575       assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5576       // assign a reasonable register and do a bailout in product mode to avoid errors
5577       allocator()->assign_spill_slot(cur);
5578       BAILOUT("LinearScan: no register found");
5579     }
5580 
5581     split_and_spill_interval(cur);
5582   } else {
5583     TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi));
5584     assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5585     assert(split_pos > 0, "invalid split_pos");
5586     assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5587 
5588     cur->assign_reg(reg, regHi);
5589     if (need_split) {
5590       // register not available for full interval, so split it
5591       split_when_partial_register_available(cur, split_pos);
5592     }
5593 
5594     // perform splitting and spilling for all affected intervalls
5595     split_and_spill_intersecting_intervals(reg, regHi);
5596   }
5597 }
5598 
5599 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5600 #ifdef X86
5601   // fast calculation of intervals that can never get a register because the
5602   // the next instruction is a call that blocks all registers
5603   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5604 
5605   // check if this interval is the result of a split operation
5606   // (an interval got a register until this position)
5607   int pos = cur->from();
5608   if ((pos & 1) == 1) {
5609     // the current instruction is a call that blocks all registers
5610     if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5611       TRACE_LINEAR_SCAN(4, tty->print_cr("      free register cannot be available because all registers blocked by following call"));
5612 
5613       // safety check that there is really no register available
5614       assert(alloc_free_reg(cur) == false, "found a register for this interval");
5615       return true;
5616     }
5617 
5618   }
5619 #endif
5620   return false;
5621 }
5622 
5623 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5624   BasicType type = cur->type();
5625   _num_phys_regs = LinearScan::num_physical_regs(type);
5626   _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5627 
5628   if (pd_init_regs_for_alloc(cur)) {
5629     // the appropriate register range was selected.
5630   } else if (type == T_FLOAT || type == T_DOUBLE) {
5631     _first_reg = pd_first_fpu_reg;
5632     _last_reg = pd_last_fpu_reg;
5633   } else {
5634     _first_reg = pd_first_cpu_reg;
5635     _last_reg = FrameMap::last_cpu_reg();
5636   }
5637 
5638   assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5639   assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5640 }
5641 
5642 
5643 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5644   if (op->code() != lir_move) {
5645     return false;
5646   }
5647   assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5648 
5649   LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5650   LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5651   return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5652 }
5653 
5654 // optimization (especially for phi functions of nested loops):
5655 // assign same spill slot to non-intersecting intervals
5656 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5657   if (cur->is_split_child()) {
5658     // optimization is only suitable for split parents
5659     return;
5660   }
5661 
5662   Interval* register_hint = cur->register_hint(false);
5663   if (register_hint == NULL) {
5664     // cur is not the target of a move, otherwise register_hint would be set
5665     return;
5666   }
5667   assert(register_hint->is_split_parent(), "register hint must be split parent");
5668 
5669   if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5670     // combining the stack slots for intervals where spill move optimization is applied
5671     // is not benefitial and would cause problems
5672     return;
5673   }
5674 
5675   int begin_pos = cur->from();
5676   int end_pos = cur->to();
5677   if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5678     // safety check that lir_op_with_id is allowed
5679     return;
5680   }
5681 
5682   if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5683     // cur and register_hint are not connected with two moves
5684     return;
5685   }
5686 
5687   Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5688   Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5689   if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5690     // register_hint must be split, otherwise the re-writing of use positions does not work
5691     return;
5692   }
5693 
5694   assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5695   assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5696   assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5697   assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5698 
5699   if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5700     // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5701     return;
5702   }
5703   assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5704 
5705   // modify intervals such that cur gets the same stack slot as register_hint
5706   // delete use positions to prevent the intervals to get a register at beginning
5707   cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5708   cur->remove_first_use_pos();
5709   end_hint->remove_first_use_pos();
5710 }
5711 
5712 
5713 // allocate a physical register or memory location to an interval
5714 bool LinearScanWalker::activate_current() {
5715   Interval* cur = current();
5716   bool result = true;
5717 
5718   TRACE_LINEAR_SCAN(2, tty->print   ("+++++ activating interval "); cur->print());
5719   TRACE_LINEAR_SCAN(4, tty->print_cr("      split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5720 
5721   if (cur->assigned_reg() >= LinearScan::nof_regs) {
5722     // activating an interval that has a stack slot assigned -> split it at first use position
5723     // used for method parameters
5724     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has spill slot assigned (method parameter) -> split it before first use"));
5725 
5726     split_stack_interval(cur);
5727     result = false;
5728 
5729   } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5730     // activating an interval that must start in a stack slot, but may get a register later
5731     // used for lir_roundfp: rounding is done by store to stack and reload later
5732     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval must start in stack slot -> split it before first use"));
5733     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5734 
5735     allocator()->assign_spill_slot(cur);
5736     split_stack_interval(cur);
5737     result = false;
5738 
5739   } else if (cur->assigned_reg() == any_reg) {
5740     // interval has not assigned register -> normal allocation
5741     // (this is the normal case for most intervals)
5742     TRACE_LINEAR_SCAN(4, tty->print_cr("      normal allocation of register"));
5743 
5744     // assign same spill slot to non-intersecting intervals
5745     combine_spilled_intervals(cur);
5746 
5747     init_vars_for_alloc(cur);
5748     if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5749       // no empty register available.
5750       // split and spill another interval so that this interval gets a register
5751       alloc_locked_reg(cur);
5752     }
5753 
5754     // spilled intervals need not be move to active-list
5755     if (cur->assigned_reg() >= LinearScan::nof_regs) {
5756       result = false;
5757     }
5758   }
5759 
5760   // load spilled values that become active from stack slot to register
5761   if (cur->insert_move_when_activated()) {
5762     assert(cur->is_split_child(), "must be");
5763     assert(cur->current_split_child() != NULL, "must be");
5764     assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5765     TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5766 
5767     insert_move(cur->from(), cur->current_split_child(), cur);
5768   }
5769   cur->make_current_split_child();
5770 
5771   return result; // true = interval is moved to active list
5772 }
5773 
5774 
5775 // Implementation of EdgeMoveOptimizer
5776 
5777 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5778   _edge_instructions(4),
5779   _edge_instructions_idx(4)
5780 {
5781 }
5782 
5783 void EdgeMoveOptimizer::optimize(BlockList* code) {
5784   EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5785 
5786   // ignore the first block in the list (index 0 is not processed)
5787   for (int i = code->length() - 1; i >= 1; i--) {
5788     BlockBegin* block = code->at(i);
5789 
5790     if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5791       optimizer.optimize_moves_at_block_end(block);
5792     }
5793     if (block->number_of_sux() == 2) {
5794       optimizer.optimize_moves_at_block_begin(block);
5795     }
5796   }
5797 }
5798 
5799 
5800 // clear all internal data structures
5801 void EdgeMoveOptimizer::init_instructions() {
5802   _edge_instructions.clear();
5803   _edge_instructions_idx.clear();
5804 }
5805 
5806 // append a lir-instruction-list and the index of the current operation in to the list
5807 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5808   _edge_instructions.append(instructions);
5809   _edge_instructions_idx.append(instructions_idx);
5810 }
5811 
5812 // return the current operation of the given edge (predecessor or successor)
5813 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5814   LIR_OpList* instructions = _edge_instructions.at(edge);
5815   int idx = _edge_instructions_idx.at(edge);
5816 
5817   if (idx < instructions->length()) {
5818     return instructions->at(idx);
5819   } else {
5820     return NULL;
5821   }
5822 }
5823 
5824 // removes the current operation of the given edge (predecessor or successor)
5825 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5826   LIR_OpList* instructions = _edge_instructions.at(edge);
5827   int idx = _edge_instructions_idx.at(edge);
5828   instructions->remove_at(idx);
5829 
5830   if (decrement_index) {
5831     _edge_instructions_idx.at_put(edge, idx - 1);
5832   }
5833 }
5834 
5835 
5836 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5837   if (op1 == NULL || op2 == NULL) {
5838     // at least one block is already empty -> no optimization possible
5839     return true;
5840   }
5841 
5842   if (op1->code() == lir_move && op2->code() == lir_move) {
5843     assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5844     assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5845     LIR_Op1* move1 = (LIR_Op1*)op1;
5846     LIR_Op1* move2 = (LIR_Op1*)op2;
5847     if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5848       // these moves are exactly equal and can be optimized
5849       return false;
5850     }
5851 
5852   } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
5853     assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
5854     assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
5855     LIR_Op1* fxch1 = (LIR_Op1*)op1;
5856     LIR_Op1* fxch2 = (LIR_Op1*)op2;
5857     if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
5858       // equal FPU stack operations can be optimized
5859       return false;
5860     }
5861 
5862   } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
5863     // equal FPU stack operations can be optimized
5864     return false;
5865   }
5866 
5867   // no optimization possible
5868   return true;
5869 }
5870 
5871 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
5872   TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
5873 
5874   if (block->is_predecessor(block)) {
5875     // currently we can't handle this correctly.
5876     return;
5877   }
5878 
5879   init_instructions();
5880   int num_preds = block->number_of_preds();
5881   assert(num_preds > 1, "do not call otherwise");
5882   assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5883 
5884   // setup a list with the lir-instructions of all predecessors
5885   int i;
5886   for (i = 0; i < num_preds; i++) {
5887     BlockBegin* pred = block->pred_at(i);
5888     LIR_OpList* pred_instructions = pred->lir()->instructions_list();
5889 
5890     if (pred->number_of_sux() != 1) {
5891       // this can happen with switch-statements where multiple edges are between
5892       // the same blocks.
5893       return;
5894     }
5895 
5896     assert(pred->number_of_sux() == 1, "can handle only one successor");
5897     assert(pred->sux_at(0) == block, "invalid control flow");
5898     assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5899     assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5900     assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5901 
5902     if (pred_instructions->last()->info() != NULL) {
5903       // can not optimize instructions when debug info is needed
5904       return;
5905     }
5906 
5907     // ignore the unconditional branch at the end of the block
5908     append_instructions(pred_instructions, pred_instructions->length() - 2);
5909   }
5910 
5911 
5912   // process lir-instructions while all predecessors end with the same instruction
5913   while (true) {
5914     LIR_Op* op = instruction_at(0);
5915     for (i = 1; i < num_preds; i++) {
5916       if (operations_different(op, instruction_at(i))) {
5917         // these instructions are different and cannot be optimized ->
5918         // no further optimization possible
5919         return;
5920       }
5921     }
5922 
5923     TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
5924 
5925     // insert the instruction at the beginning of the current block
5926     block->lir()->insert_before(1, op);
5927 
5928     // delete the instruction at the end of all predecessors
5929     for (i = 0; i < num_preds; i++) {
5930       remove_cur_instruction(i, true);
5931     }
5932   }
5933 }
5934 
5935 
5936 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
5937   TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
5938 
5939   init_instructions();
5940   int num_sux = block->number_of_sux();
5941 
5942   LIR_OpList* cur_instructions = block->lir()->instructions_list();
5943 
5944   assert(num_sux == 2, "method should not be called otherwise");
5945   assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5946   assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5947   assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5948 
5949   if (cur_instructions->last()->info() != NULL) {
5950     // can no optimize instructions when debug info is needed
5951     return;
5952   }
5953 
5954   LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
5955   if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
5956     // not a valid case for optimization
5957     // currently, only blocks that end with two branches (conditional branch followed
5958     // by unconditional branch) are optimized
5959     return;
5960   }
5961 
5962   // now it is guaranteed that the block ends with two branch instructions.
5963   // the instructions are inserted at the end of the block before these two branches
5964   int insert_idx = cur_instructions->length() - 2;
5965 
5966   int i;
5967 #ifdef ASSERT
5968   for (i = insert_idx - 1; i >= 0; i--) {
5969     LIR_Op* op = cur_instructions->at(i);
5970     if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
5971       assert(false, "block with two successors can have only two branch instructions");
5972     }
5973   }
5974 #endif
5975 
5976   // setup a list with the lir-instructions of all successors
5977   for (i = 0; i < num_sux; i++) {
5978     BlockBegin* sux = block->sux_at(i);
5979     LIR_OpList* sux_instructions = sux->lir()->instructions_list();
5980 
5981     assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
5982 
5983     if (sux->number_of_preds() != 1) {
5984       // this can happen with switch-statements where multiple edges are between
5985       // the same blocks.
5986       return;
5987     }
5988     assert(sux->pred_at(0) == block, "invalid control flow");
5989     assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5990 
5991     // ignore the label at the beginning of the block
5992     append_instructions(sux_instructions, 1);
5993   }
5994 
5995   // process lir-instructions while all successors begin with the same instruction
5996   while (true) {
5997     LIR_Op* op = instruction_at(0);
5998     for (i = 1; i < num_sux; i++) {
5999       if (operations_different(op, instruction_at(i))) {
6000         // these instructions are different and cannot be optimized ->
6001         // no further optimization possible
6002         return;
6003       }
6004     }
6005 
6006     TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6007 
6008     // insert instruction at end of current block
6009     block->lir()->insert_before(insert_idx, op);
6010     insert_idx++;
6011 
6012     // delete the instructions at the beginning of all successors
6013     for (i = 0; i < num_sux; i++) {
6014       remove_cur_instruction(i, false);
6015     }
6016   }
6017 }
6018 
6019 
6020 // Implementation of ControlFlowOptimizer
6021 
6022 ControlFlowOptimizer::ControlFlowOptimizer() :
6023   _original_preds(4)
6024 {
6025 }
6026 
6027 void ControlFlowOptimizer::optimize(BlockList* code) {
6028   ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6029 
6030   // push the OSR entry block to the end so that we're not jumping over it.
6031   BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6032   if (osr_entry) {
6033     int index = osr_entry->linear_scan_number();
6034     assert(code->at(index) == osr_entry, "wrong index");
6035     code->remove_at(index);
6036     code->append(osr_entry);
6037   }
6038 
6039   optimizer.reorder_short_loops(code);
6040   optimizer.delete_empty_blocks(code);
6041   optimizer.delete_unnecessary_jumps(code);
6042   optimizer.delete_jumps_to_return(code);
6043 }
6044 
6045 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6046   int i = header_idx + 1;
6047   int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6048   while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6049     i++;
6050   }
6051 
6052   if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6053     int end_idx = i - 1;
6054     BlockBegin* end_block = code->at(end_idx);
6055 
6056     if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6057       // short loop from header_idx to end_idx found -> reorder blocks such that
6058       // the header_block is the last block instead of the first block of the loop
6059       TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6060                                          end_idx - header_idx + 1,
6061                                          header_block->block_id(), end_block->block_id()));
6062 
6063       for (int j = header_idx; j < end_idx; j++) {
6064         code->at_put(j, code->at(j + 1));
6065       }
6066       code->at_put(end_idx, header_block);
6067 
6068       // correct the flags so that any loop alignment occurs in the right place.
6069       assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6070       code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6071       code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6072     }
6073   }
6074 }
6075 
6076 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6077   for (int i = code->length() - 1; i >= 0; i--) {
6078     BlockBegin* block = code->at(i);
6079 
6080     if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6081       reorder_short_loop(code, block, i);
6082     }
6083   }
6084 
6085   DEBUG_ONLY(verify(code));
6086 }
6087 
6088 // only blocks with exactly one successor can be deleted. Such blocks
6089 // must always end with an unconditional branch to this successor
6090 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6091   if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6092     return false;
6093   }
6094 
6095   LIR_OpList* instructions = block->lir()->instructions_list();
6096 
6097   assert(instructions->length() >= 2, "block must have label and branch");
6098   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6099   assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6100   assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6101   assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6102 
6103   // block must have exactly one successor
6104 
6105   if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6106     return true;
6107   }
6108   return false;
6109 }
6110 
6111 // substitute branch targets in all branch-instructions of this blocks
6112 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6113   TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6114 
6115   LIR_OpList* instructions = block->lir()->instructions_list();
6116 
6117   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6118   for (int i = instructions->length() - 1; i >= 1; i--) {
6119     LIR_Op* op = instructions->at(i);
6120 
6121     if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6122       assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6123       LIR_OpBranch* branch = (LIR_OpBranch*)op;
6124 
6125       if (branch->block() == target_from) {
6126         branch->change_block(target_to);
6127       }
6128       if (branch->ublock() == target_from) {
6129         branch->change_ublock(target_to);
6130       }
6131     }
6132   }
6133 }
6134 
6135 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6136   int old_pos = 0;
6137   int new_pos = 0;
6138   int num_blocks = code->length();
6139 
6140   while (old_pos < num_blocks) {
6141     BlockBegin* block = code->at(old_pos);
6142 
6143     if (can_delete_block(block)) {
6144       BlockBegin* new_target = block->sux_at(0);
6145 
6146       // propagate backward branch target flag for correct code alignment
6147       if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6148         new_target->set(BlockBegin::backward_branch_target_flag);
6149       }
6150 
6151       // collect a list with all predecessors that contains each predecessor only once
6152       // the predecessors of cur are changed during the substitution, so a copy of the
6153       // predecessor list is necessary
6154       int j;
6155       _original_preds.clear();
6156       for (j = block->number_of_preds() - 1; j >= 0; j--) {
6157         BlockBegin* pred = block->pred_at(j);
6158         if (_original_preds.index_of(pred) == -1) {
6159           _original_preds.append(pred);
6160         }
6161       }
6162 
6163       for (j = _original_preds.length() - 1; j >= 0; j--) {
6164         BlockBegin* pred = _original_preds.at(j);
6165         substitute_branch_target(pred, block, new_target);
6166         pred->substitute_sux(block, new_target);
6167       }
6168     } else {
6169       // adjust position of this block in the block list if blocks before
6170       // have been deleted
6171       if (new_pos != old_pos) {
6172         code->at_put(new_pos, code->at(old_pos));
6173       }
6174       new_pos++;
6175     }
6176     old_pos++;
6177   }
6178   code->truncate(new_pos);
6179 
6180   DEBUG_ONLY(verify(code));
6181 }
6182 
6183 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6184   // skip the last block because there a branch is always necessary
6185   for (int i = code->length() - 2; i >= 0; i--) {
6186     BlockBegin* block = code->at(i);
6187     LIR_OpList* instructions = block->lir()->instructions_list();
6188 
6189     LIR_Op* last_op = instructions->last();
6190     if (last_op->code() == lir_branch) {
6191       assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6192       LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6193 
6194       assert(last_branch->block() != NULL, "last branch must always have a block as target");
6195       assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6196 
6197       if (last_branch->info() == NULL) {
6198         if (last_branch->block() == code->at(i + 1)) {
6199 
6200           TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6201 
6202           // delete last branch instruction
6203           instructions->truncate(instructions->length() - 1);
6204 
6205         } else {
6206           LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6207           if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6208             assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6209             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6210 
6211             if (prev_branch->stub() == NULL) {
6212 
6213               LIR_Op2* prev_cmp = NULL;
6214 
6215               for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6216                 prev_op = instructions->at(j);
6217                 if (prev_op->code() == lir_cmp) {
6218                   assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6219                   prev_cmp = (LIR_Op2*)prev_op;
6220                   assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6221                 }
6222               }
6223               assert(prev_cmp != NULL, "should have found comp instruction for branch");
6224               if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6225 
6226                 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6227 
6228                 // eliminate a conditional branch to the immediate successor
6229                 prev_branch->change_block(last_branch->block());
6230                 prev_branch->negate_cond();
6231                 prev_cmp->set_condition(prev_branch->cond());
6232                 instructions->truncate(instructions->length() - 1);
6233               }
6234             }
6235           }
6236         }
6237       }
6238     }
6239   }
6240 
6241   DEBUG_ONLY(verify(code));
6242 }
6243 
6244 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6245 #ifdef ASSERT
6246   BitMap return_converted(BlockBegin::number_of_blocks());
6247   return_converted.clear();
6248 #endif
6249 
6250   for (int i = code->length() - 1; i >= 0; i--) {
6251     BlockBegin* block = code->at(i);
6252     LIR_OpList* cur_instructions = block->lir()->instructions_list();
6253     LIR_Op*     cur_last_op = cur_instructions->last();
6254 
6255     assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6256     if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6257       // the block contains only a label and a return
6258       // if a predecessor ends with an unconditional jump to this block, then the jump
6259       // can be replaced with a return instruction
6260       //
6261       // Note: the original block with only a return statement cannot be deleted completely
6262       //       because the predecessors might have other (conditional) jumps to this block
6263       //       -> this may lead to unnecesary return instructions in the final code
6264 
6265       assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6266       assert(block->number_of_sux() == 0 ||
6267              (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6268              "blocks that end with return must not have successors");
6269 
6270       assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6271       LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6272 
6273       for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6274         BlockBegin* pred = block->pred_at(j);
6275         LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6276         LIR_Op*     pred_last_op = pred_instructions->last();
6277 
6278         if (pred_last_op->code() == lir_branch) {
6279           assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6280           LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6281 
6282           if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6283             // replace the jump to a return with a direct return
6284             // Note: currently the edge between the blocks is not deleted
6285             pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
6286 #ifdef ASSERT
6287             return_converted.set_bit(pred->block_id());
6288 #endif
6289           }
6290         }
6291       }
6292     }
6293   }
6294 }
6295 
6296 
6297 #ifdef ASSERT
6298 void ControlFlowOptimizer::verify(BlockList* code) {
6299   for (int i = 0; i < code->length(); i++) {
6300     BlockBegin* block = code->at(i);
6301     LIR_OpList* instructions = block->lir()->instructions_list();
6302 
6303     int j;
6304     for (j = 0; j < instructions->length(); j++) {
6305       LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6306 
6307       if (op_branch != NULL) {
6308         assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid");
6309         assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid");
6310       }
6311     }
6312 
6313     for (j = 0; j < block->number_of_sux() - 1; j++) {
6314       BlockBegin* sux = block->sux_at(j);
6315       assert(code->index_of(sux) != -1, "successor not valid");
6316     }
6317 
6318     for (j = 0; j < block->number_of_preds() - 1; j++) {
6319       BlockBegin* pred = block->pred_at(j);
6320       assert(code->index_of(pred) != -1, "successor not valid");
6321     }
6322   }
6323 }
6324 #endif
6325 
6326 
6327 #ifndef PRODUCT
6328 
6329 // Implementation of LinearStatistic
6330 
6331 const char* LinearScanStatistic::counter_name(int counter_idx) {
6332   switch (counter_idx) {
6333     case counter_method:          return "compiled methods";
6334     case counter_fpu_method:      return "methods using fpu";
6335     case counter_loop_method:     return "methods with loops";
6336     case counter_exception_method:return "methods with xhandler";
6337 
6338     case counter_loop:            return "loops";
6339     case counter_block:           return "blocks";
6340     case counter_loop_block:      return "blocks inside loop";
6341     case counter_exception_block: return "exception handler entries";
6342     case counter_interval:        return "intervals";
6343     case counter_fixed_interval:  return "fixed intervals";
6344     case counter_range:           return "ranges";
6345     case counter_fixed_range:     return "fixed ranges";
6346     case counter_use_pos:         return "use positions";
6347     case counter_fixed_use_pos:   return "fixed use positions";
6348     case counter_spill_slots:     return "spill slots";
6349 
6350     // counter for classes of lir instructions
6351     case counter_instruction:     return "total instructions";
6352     case counter_label:           return "labels";
6353     case counter_entry:           return "method entries";
6354     case counter_return:          return "method returns";
6355     case counter_call:            return "method calls";
6356     case counter_move:            return "moves";
6357     case counter_cmp:             return "compare";
6358     case counter_cond_branch:     return "conditional branches";
6359     case counter_uncond_branch:   return "unconditional branches";
6360     case counter_stub_branch:     return "branches to stub";
6361     case counter_alu:             return "artithmetic + logic";
6362     case counter_alloc:           return "allocations";
6363     case counter_sync:            return "synchronisation";
6364     case counter_throw:           return "throw";
6365     case counter_unwind:          return "unwind";
6366     case counter_typecheck:       return "type+null-checks";
6367     case counter_fpu_stack:       return "fpu-stack";
6368     case counter_misc_inst:       return "other instructions";
6369     case counter_other_inst:      return "misc. instructions";
6370 
6371     // counter for different types of moves
6372     case counter_move_total:      return "total moves";
6373     case counter_move_reg_reg:    return "register->register";
6374     case counter_move_reg_stack:  return "register->stack";
6375     case counter_move_stack_reg:  return "stack->register";
6376     case counter_move_stack_stack:return "stack->stack";
6377     case counter_move_reg_mem:    return "register->memory";
6378     case counter_move_mem_reg:    return "memory->register";
6379     case counter_move_const_any:  return "constant->any";
6380 
6381     case blank_line_1:            return "";
6382     case blank_line_2:            return "";
6383 
6384     default: ShouldNotReachHere(); return "";
6385   }
6386 }
6387 
6388 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6389   if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6390     return counter_method;
6391   } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6392     return counter_block;
6393   } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6394     return counter_instruction;
6395   } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6396     return counter_move_total;
6397   }
6398   return invalid_counter;
6399 }
6400 
6401 LinearScanStatistic::LinearScanStatistic() {
6402   for (int i = 0; i < number_of_counters; i++) {
6403     _counters_sum[i] = 0;
6404     _counters_max[i] = -1;
6405   }
6406 
6407 }
6408 
6409 // add the method-local numbers to the total sum
6410 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6411   for (int i = 0; i < number_of_counters; i++) {
6412     _counters_sum[i] += method_statistic._counters_sum[i];
6413     _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6414   }
6415 }
6416 
6417 void LinearScanStatistic::print(const char* title) {
6418   if (CountLinearScan || TraceLinearScanLevel > 0) {
6419     tty->cr();
6420     tty->print_cr("***** LinearScan statistic - %s *****", title);
6421 
6422     for (int i = 0; i < number_of_counters; i++) {
6423       if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6424         tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6425 
6426         if (base_counter(i) != invalid_counter) {
6427           tty->print("  (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]);
6428         } else {
6429           tty->print("           ");
6430         }
6431 
6432         if (_counters_max[i] >= 0) {
6433           tty->print("%8d", _counters_max[i]);
6434         }
6435       }
6436       tty->cr();
6437     }
6438   }
6439 }
6440 
6441 void LinearScanStatistic::collect(LinearScan* allocator) {
6442   inc_counter(counter_method);
6443   if (allocator->has_fpu_registers()) {
6444     inc_counter(counter_fpu_method);
6445   }
6446   if (allocator->num_loops() > 0) {
6447     inc_counter(counter_loop_method);
6448   }
6449   inc_counter(counter_loop, allocator->num_loops());
6450   inc_counter(counter_spill_slots, allocator->max_spills());
6451 
6452   int i;
6453   for (i = 0; i < allocator->interval_count(); i++) {
6454     Interval* cur = allocator->interval_at(i);
6455 
6456     if (cur != NULL) {
6457       inc_counter(counter_interval);
6458       inc_counter(counter_use_pos, cur->num_use_positions());
6459       if (LinearScan::is_precolored_interval(cur)) {
6460         inc_counter(counter_fixed_interval);
6461         inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6462       }
6463 
6464       Range* range = cur->first();
6465       while (range != Range::end()) {
6466         inc_counter(counter_range);
6467         if (LinearScan::is_precolored_interval(cur)) {
6468           inc_counter(counter_fixed_range);
6469         }
6470         range = range->next();
6471       }
6472     }
6473   }
6474 
6475   bool has_xhandlers = false;
6476   // Note: only count blocks that are in code-emit order
6477   for (i = 0; i < allocator->ir()->code()->length(); i++) {
6478     BlockBegin* cur = allocator->ir()->code()->at(i);
6479 
6480     inc_counter(counter_block);
6481     if (cur->loop_depth() > 0) {
6482       inc_counter(counter_loop_block);
6483     }
6484     if (cur->is_set(BlockBegin::exception_entry_flag)) {
6485       inc_counter(counter_exception_block);
6486       has_xhandlers = true;
6487     }
6488 
6489     LIR_OpList* instructions = cur->lir()->instructions_list();
6490     for (int j = 0; j < instructions->length(); j++) {
6491       LIR_Op* op = instructions->at(j);
6492 
6493       inc_counter(counter_instruction);
6494 
6495       switch (op->code()) {
6496         case lir_label:           inc_counter(counter_label); break;
6497         case lir_std_entry:
6498         case lir_osr_entry:       inc_counter(counter_entry); break;
6499         case lir_return:          inc_counter(counter_return); break;
6500 
6501         case lir_rtcall:
6502         case lir_static_call:
6503         case lir_optvirtual_call:
6504         case lir_virtual_call:    inc_counter(counter_call); break;
6505 
6506         case lir_move: {
6507           inc_counter(counter_move);
6508           inc_counter(counter_move_total);
6509 
6510           LIR_Opr in = op->as_Op1()->in_opr();
6511           LIR_Opr res = op->as_Op1()->result_opr();
6512           if (in->is_register()) {
6513             if (res->is_register()) {
6514               inc_counter(counter_move_reg_reg);
6515             } else if (res->is_stack()) {
6516               inc_counter(counter_move_reg_stack);
6517             } else if (res->is_address()) {
6518               inc_counter(counter_move_reg_mem);
6519             } else {
6520               ShouldNotReachHere();
6521             }
6522           } else if (in->is_stack()) {
6523             if (res->is_register()) {
6524               inc_counter(counter_move_stack_reg);
6525             } else {
6526               inc_counter(counter_move_stack_stack);
6527             }
6528           } else if (in->is_address()) {
6529             assert(res->is_register(), "must be");
6530             inc_counter(counter_move_mem_reg);
6531           } else if (in->is_constant()) {
6532             inc_counter(counter_move_const_any);
6533           } else {
6534             ShouldNotReachHere();
6535           }
6536           break;
6537         }
6538 
6539         case lir_cmp:             inc_counter(counter_cmp); break;
6540 
6541         case lir_branch:
6542         case lir_cond_float_branch: {
6543           LIR_OpBranch* branch = op->as_OpBranch();
6544           if (branch->block() == NULL) {
6545             inc_counter(counter_stub_branch);
6546           } else if (branch->cond() == lir_cond_always) {
6547             inc_counter(counter_uncond_branch);
6548           } else {
6549             inc_counter(counter_cond_branch);
6550           }
6551           break;
6552         }
6553 
6554         case lir_neg:
6555         case lir_add:
6556         case lir_sub:
6557         case lir_mul:
6558         case lir_mul_strictfp:
6559         case lir_div:
6560         case lir_div_strictfp:
6561         case lir_rem:
6562         case lir_sqrt:
6563         case lir_sin:
6564         case lir_cos:
6565         case lir_abs:
6566         case lir_log10:
6567         case lir_log:
6568         case lir_pow:
6569         case lir_exp:
6570         case lir_logic_and:
6571         case lir_logic_or:
6572         case lir_logic_xor:
6573         case lir_shl:
6574         case lir_shr:
6575         case lir_ushr:            inc_counter(counter_alu); break;
6576 
6577         case lir_alloc_object:
6578         case lir_alloc_array:     inc_counter(counter_alloc); break;
6579 
6580         case lir_monaddr:
6581         case lir_lock:
6582         case lir_unlock:          inc_counter(counter_sync); break;
6583 
6584         case lir_throw:           inc_counter(counter_throw); break;
6585 
6586         case lir_unwind:          inc_counter(counter_unwind); break;
6587 
6588         case lir_null_check:
6589         case lir_leal:
6590         case lir_instanceof:
6591         case lir_checkcast:
6592         case lir_store_check:     inc_counter(counter_typecheck); break;
6593 
6594         case lir_fpop_raw:
6595         case lir_fxch:
6596         case lir_fld:             inc_counter(counter_fpu_stack); break;
6597 
6598         case lir_nop:
6599         case lir_push:
6600         case lir_pop:
6601         case lir_convert:
6602         case lir_roundfp:
6603         case lir_cmove:           inc_counter(counter_misc_inst); break;
6604 
6605         default:                  inc_counter(counter_other_inst); break;
6606       }
6607     }
6608   }
6609 
6610   if (has_xhandlers) {
6611     inc_counter(counter_exception_method);
6612   }
6613 }
6614 
6615 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6616   if (CountLinearScan || TraceLinearScanLevel > 0) {
6617 
6618     LinearScanStatistic local_statistic = LinearScanStatistic();
6619 
6620     local_statistic.collect(allocator);
6621     global_statistic.sum_up(local_statistic);
6622 
6623     if (TraceLinearScanLevel > 2) {
6624       local_statistic.print("current local statistic");
6625     }
6626   }
6627 }
6628 
6629 
6630 // Implementation of LinearTimers
6631 
6632 LinearScanTimers::LinearScanTimers() {
6633   for (int i = 0; i < number_of_timers; i++) {
6634     timer(i)->reset();
6635   }
6636 }
6637 
6638 const char* LinearScanTimers::timer_name(int idx) {
6639   switch (idx) {
6640     case timer_do_nothing:               return "Nothing (Time Check)";
6641     case timer_number_instructions:      return "Number Instructions";
6642     case timer_compute_local_live_sets:  return "Local Live Sets";
6643     case timer_compute_global_live_sets: return "Global Live Sets";
6644     case timer_build_intervals:          return "Build Intervals";
6645     case timer_sort_intervals_before:    return "Sort Intervals Before";
6646     case timer_allocate_registers:       return "Allocate Registers";
6647     case timer_resolve_data_flow:        return "Resolve Data Flow";
6648     case timer_sort_intervals_after:     return "Sort Intervals After";
6649     case timer_eliminate_spill_moves:    return "Spill optimization";
6650     case timer_assign_reg_num:           return "Assign Reg Num";
6651     case timer_allocate_fpu_stack:       return "Allocate FPU Stack";
6652     case timer_optimize_lir:             return "Optimize LIR";
6653     default: ShouldNotReachHere();       return "";
6654   }
6655 }
6656 
6657 void LinearScanTimers::begin_method() {
6658   if (TimeEachLinearScan) {
6659     // reset all timers to measure only current method
6660     for (int i = 0; i < number_of_timers; i++) {
6661       timer(i)->reset();
6662     }
6663   }
6664 }
6665 
6666 void LinearScanTimers::end_method(LinearScan* allocator) {
6667   if (TimeEachLinearScan) {
6668 
6669     double c = timer(timer_do_nothing)->seconds();
6670     double total = 0;
6671     for (int i = 1; i < number_of_timers; i++) {
6672       total += timer(i)->seconds() - c;
6673     }
6674 
6675     if (total >= 0.0005) {
6676       // print all information in one line for automatic processing
6677       tty->print("@"); allocator->compilation()->method()->print_name();
6678 
6679       tty->print("@ %d ", allocator->compilation()->method()->code_size());
6680       tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6681       tty->print("@ %d ", allocator->block_count());
6682       tty->print("@ %d ", allocator->num_virtual_regs());
6683       tty->print("@ %d ", allocator->interval_count());
6684       tty->print("@ %d ", allocator->_num_calls);
6685       tty->print("@ %d ", allocator->num_loops());
6686 
6687       tty->print("@ %6.6f ", total);
6688       for (int i = 1; i < number_of_timers; i++) {
6689         tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6690       }
6691       tty->cr();
6692     }
6693   }
6694 }
6695 
6696 void LinearScanTimers::print(double total_time) {
6697   if (TimeLinearScan) {
6698     // correction value: sum of dummy-timer that only measures the time that
6699     // is necesary to start and stop itself
6700     double c = timer(timer_do_nothing)->seconds();
6701 
6702     for (int i = 0; i < number_of_timers; i++) {
6703       double t = timer(i)->seconds();
6704       tty->print_cr("    %25s: %6.3f s (%4.1f%%)  corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6705     }
6706   }
6707 }
6708 
6709 #endif // #ifndef PRODUCT