1 //
2 // Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer/long registers
173 reg_class all_reg(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all int registers
191 reg_class all_int_reg(RAX
192 RDX,
193 RBP,
194 RDI,
195 RSI,
196 RCX,
197 RBX,
198 R8,
199 R9,
200 R10,
201 R11,
202 R12,
203 R13,
204 R14);
205
206 // Class for all pointer registers
207 reg_class any_reg %{
208 return _ANY_REG_mask;
209 %}
210
211 // Class for all pointer registers (excluding RSP)
212 reg_class ptr_reg %{
213 return _PTR_REG_mask;
214 %}
215
216 // Class for all pointer registers (excluding RSP and RBP)
217 reg_class ptr_reg_no_rbp %{
218 return _PTR_REG_NO_RBP_mask;
219 %}
220
221 // Class for all pointer registers (excluding RAX and RSP)
222 reg_class ptr_no_rax_reg %{
223 return _PTR_NO_RAX_REG_mask;
224 %}
225
226 // Class for all pointer registers (excluding RAX, RBX, and RSP)
227 reg_class ptr_no_rax_rbx_reg %{
228 return _PTR_NO_RAX_RBX_REG_mask;
229 %}
230
231 // Class for all long registers (excluding RSP)
232 reg_class long_reg %{
233 return _LONG_REG_mask;
234 %}
235
236 // Class for all long registers (excluding RAX, RDX and RSP)
237 reg_class long_no_rax_rdx_reg %{
238 return _LONG_NO_RAX_RDX_REG_mask;
239 %}
240
241 // Class for all long registers (excluding RCX and RSP)
242 reg_class long_no_rcx_reg %{
243 return _LONG_NO_RCX_REG_mask;
244 %}
245
246 // Class for all int registers (excluding RSP)
247 reg_class int_reg %{
248 return _INT_REG_mask;
249 %}
250
251 // Class for all int registers (excluding RAX, RDX, and RSP)
252 reg_class int_no_rax_rdx_reg %{
253 return _INT_NO_RAX_RDX_REG_mask;
254 %}
255
256 // Class for all int registers (excluding RCX and RSP)
257 reg_class int_no_rcx_reg %{
258 return _INT_NO_RCX_REG_mask;
259 %}
260
261 // Singleton class for RAX pointer register
262 reg_class ptr_rax_reg(RAX, RAX_H);
263
264 // Singleton class for RBX pointer register
265 reg_class ptr_rbx_reg(RBX, RBX_H);
266
267 // Singleton class for RSI pointer register
268 reg_class ptr_rsi_reg(RSI, RSI_H);
269
270 // Singleton class for RDI pointer register
271 reg_class ptr_rdi_reg(RDI, RDI_H);
272
273 // Singleton class for stack pointer
274 reg_class ptr_rsp_reg(RSP, RSP_H);
275
276 // Singleton class for TLS pointer
277 reg_class ptr_r15_reg(R15, R15_H);
278
279 // Singleton class for RAX long register
280 reg_class long_rax_reg(RAX, RAX_H);
281
282 // Singleton class for RCX long register
283 reg_class long_rcx_reg(RCX, RCX_H);
284
285 // Singleton class for RDX long register
286 reg_class long_rdx_reg(RDX, RDX_H);
287
288 // Singleton class for RAX int register
289 reg_class int_rax_reg(RAX);
290
291 // Singleton class for RBX int register
292 reg_class int_rbx_reg(RBX);
293
294 // Singleton class for RCX int register
295 reg_class int_rcx_reg(RCX);
296
297 // Singleton class for RCX int register
298 reg_class int_rdx_reg(RDX);
299
300 // Singleton class for RCX int register
301 reg_class int_rdi_reg(RDI);
302
303 // Singleton class for instruction pointer
304 // reg_class ip_reg(RIP);
305
306 %}
307
308 //----------SOURCE BLOCK-------------------------------------------------------
309 // This is a block of C++ code which provides values, functions, and
310 // definitions necessary in the rest of the architecture description
311 source_hpp %{
312
313 extern RegMask _ANY_REG_mask;
314 extern RegMask _PTR_REG_mask;
315 extern RegMask _PTR_REG_NO_RBP_mask;
316 extern RegMask _PTR_NO_RAX_REG_mask;
317 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
318 extern RegMask _LONG_REG_mask;
319 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
320 extern RegMask _LONG_NO_RCX_REG_mask;
321 extern RegMask _INT_REG_mask;
322 extern RegMask _INT_NO_RAX_RDX_REG_mask;
323 extern RegMask _INT_NO_RCX_REG_mask;
324
325 extern RegMask _STACK_OR_PTR_REG_mask;
326 extern RegMask _STACK_OR_LONG_REG_mask;
327 extern RegMask _STACK_OR_INT_REG_mask;
328
329 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
330 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
331 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
332
333 %}
334
335 source %{
336 #define RELOC_IMM64 Assembler::imm_operand
337 #define RELOC_DISP32 Assembler::disp32_operand
338
339 #define __ _masm.
340
341 RegMask _ANY_REG_mask;
342 RegMask _PTR_REG_mask;
343 RegMask _PTR_REG_NO_RBP_mask;
344 RegMask _PTR_NO_RAX_REG_mask;
345 RegMask _PTR_NO_RAX_RBX_REG_mask;
346 RegMask _LONG_REG_mask;
347 RegMask _LONG_NO_RAX_RDX_REG_mask;
348 RegMask _LONG_NO_RCX_REG_mask;
349 RegMask _INT_REG_mask;
350 RegMask _INT_NO_RAX_RDX_REG_mask;
351 RegMask _INT_NO_RCX_REG_mask;
352 RegMask _STACK_OR_PTR_REG_mask;
353 RegMask _STACK_OR_LONG_REG_mask;
354 RegMask _STACK_OR_INT_REG_mask;
355
356 static bool need_r12_heapbase() {
357 return UseCompressedOops || UseCompressedClassPointers;
358 }
359
360 void reg_mask_init() {
361 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
362 // We derive a number of subsets from it.
363 _ANY_REG_mask = _ALL_REG_mask;
364
365 if (PreserveFramePointer) {
366 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
367 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
368 }
369 if (need_r12_heapbase()) {
370 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
371 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
372 }
373
374 _PTR_REG_mask = _ANY_REG_mask;
375 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
376 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
377 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
378 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
379
380 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
381 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
382
383 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
384 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
385 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
386
387 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
388 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
389 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
390
391 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
392 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
393 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
394
395 _LONG_REG_mask = _PTR_REG_mask;
396 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
397 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
398
399 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
400 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
401 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
402 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
403 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
404
405 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
406 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
407 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
408
409 _INT_REG_mask = _ALL_INT_REG_mask;
410 if (PreserveFramePointer) {
411 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
412 }
413 if (need_r12_heapbase()) {
414 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
415 }
416
417 _STACK_OR_INT_REG_mask = _INT_REG_mask;
418 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
419
420 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
421 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
422 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
423
424 _INT_NO_RCX_REG_mask = _INT_REG_mask;
425 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
426 }
427
428 static bool generate_vzeroupper(Compile* C) {
429 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
430 }
431
432 static int clear_avx_size() {
433 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
434 }
435
436 // !!!!! Special hack to get all types of calls to specify the byte offset
437 // from the start of the call to the point where the return address
438 // will point.
439 int MachCallStaticJavaNode::ret_addr_offset()
440 {
441 int offset = 5; // 5 bytes from start of call to where return address points
442 offset += clear_avx_size();
443 return offset;
444 }
445
446 int MachCallDynamicJavaNode::ret_addr_offset()
447 {
448 int offset = 15; // 15 bytes from start of call to where return address points
449 offset += clear_avx_size();
450 return offset;
451 }
452
453 int MachCallRuntimeNode::ret_addr_offset() {
454 int offset = 13; // movq r10,#addr; callq (r10)
455 offset += clear_avx_size();
456 return offset;
457 }
458
459 // Indicate if the safepoint node needs the polling page as an input,
460 // it does if the polling page is more than disp32 away.
461 bool SafePointNode::needs_polling_address_input()
462 {
463 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
464 }
465
466 //
467 // Compute padding required for nodes which need alignment
468 //
469
470 // The address of the call instruction needs to be 4-byte aligned to
471 // ensure that it does not span a cache line so that it can be patched.
472 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
473 {
474 current_offset += clear_avx_size(); // skip vzeroupper
475 current_offset += 1; // skip call opcode byte
476 return align_up(current_offset, alignment_required()) - current_offset;
477 }
478
479 // The address of the call instruction needs to be 4-byte aligned to
480 // ensure that it does not span a cache line so that it can be patched.
481 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
482 {
483 current_offset += clear_avx_size(); // skip vzeroupper
484 current_offset += 11; // skip movq instruction + call opcode byte
485 return align_up(current_offset, alignment_required()) - current_offset;
486 }
487
488 // EMIT_RM()
489 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
490 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
491 cbuf.insts()->emit_int8(c);
492 }
493
494 // EMIT_CC()
495 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
496 unsigned char c = (unsigned char) (f1 | f2);
497 cbuf.insts()->emit_int8(c);
498 }
499
500 // EMIT_OPCODE()
501 void emit_opcode(CodeBuffer &cbuf, int code) {
502 cbuf.insts()->emit_int8((unsigned char) code);
503 }
504
505 // EMIT_OPCODE() w/ relocation information
506 void emit_opcode(CodeBuffer &cbuf,
507 int code, relocInfo::relocType reloc, int offset, int format)
508 {
509 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
510 emit_opcode(cbuf, code);
511 }
512
513 // EMIT_D8()
514 void emit_d8(CodeBuffer &cbuf, int d8) {
515 cbuf.insts()->emit_int8((unsigned char) d8);
516 }
517
518 // EMIT_D16()
519 void emit_d16(CodeBuffer &cbuf, int d16) {
520 cbuf.insts()->emit_int16(d16);
521 }
522
523 // EMIT_D32()
524 void emit_d32(CodeBuffer &cbuf, int d32) {
525 cbuf.insts()->emit_int32(d32);
526 }
527
528 // EMIT_D64()
529 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
530 cbuf.insts()->emit_int64(d64);
531 }
532
533 // emit 32 bit value and construct relocation entry from relocInfo::relocType
534 void emit_d32_reloc(CodeBuffer& cbuf,
535 int d32,
536 relocInfo::relocType reloc,
537 int format)
538 {
539 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
540 cbuf.relocate(cbuf.insts_mark(), reloc, format);
541 cbuf.insts()->emit_int32(d32);
542 }
543
544 // emit 32 bit value and construct relocation entry from RelocationHolder
545 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
546 #ifdef ASSERT
547 if (rspec.reloc()->type() == relocInfo::oop_type &&
548 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
549 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
550 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code");
551 }
552 #endif
553 cbuf.relocate(cbuf.insts_mark(), rspec, format);
554 cbuf.insts()->emit_int32(d32);
555 }
556
557 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
558 address next_ip = cbuf.insts_end() + 4;
559 emit_d32_reloc(cbuf, (int) (addr - next_ip),
560 external_word_Relocation::spec(addr),
561 RELOC_DISP32);
562 }
563
564
565 // emit 64 bit value and construct relocation entry from relocInfo::relocType
566 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
567 cbuf.relocate(cbuf.insts_mark(), reloc, format);
568 cbuf.insts()->emit_int64(d64);
569 }
570
571 // emit 64 bit value and construct relocation entry from RelocationHolder
572 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
573 #ifdef ASSERT
574 if (rspec.reloc()->type() == relocInfo::oop_type &&
575 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
576 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
577 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code");
578 }
579 #endif
580 cbuf.relocate(cbuf.insts_mark(), rspec, format);
581 cbuf.insts()->emit_int64(d64);
582 }
583
584 // Access stack slot for load or store
585 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
586 {
587 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
588 if (-0x80 <= disp && disp < 0x80) {
589 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
590 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
591 emit_d8(cbuf, disp); // Displacement // R/M byte
592 } else {
593 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
594 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
595 emit_d32(cbuf, disp); // Displacement // R/M byte
596 }
597 }
598
599 // rRegI ereg, memory mem) %{ // emit_reg_mem
600 void encode_RegMem(CodeBuffer &cbuf,
601 int reg,
602 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
603 {
604 assert(disp_reloc == relocInfo::none, "cannot have disp");
605 int regenc = reg & 7;
606 int baseenc = base & 7;
607 int indexenc = index & 7;
608
609 // There is no index & no scale, use form without SIB byte
610 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
611 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
612 if (disp == 0 && base != RBP_enc && base != R13_enc) {
613 emit_rm(cbuf, 0x0, regenc, baseenc); // *
614 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
615 // If 8-bit displacement, mode 0x1
616 emit_rm(cbuf, 0x1, regenc, baseenc); // *
617 emit_d8(cbuf, disp);
618 } else {
619 // If 32-bit displacement
620 if (base == -1) { // Special flag for absolute address
621 emit_rm(cbuf, 0x0, regenc, 0x5); // *
622 if (disp_reloc != relocInfo::none) {
623 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
624 } else {
625 emit_d32(cbuf, disp);
626 }
627 } else {
628 // Normal base + offset
629 emit_rm(cbuf, 0x2, regenc, baseenc); // *
630 if (disp_reloc != relocInfo::none) {
631 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
632 } else {
633 emit_d32(cbuf, disp);
634 }
635 }
636 }
637 } else {
638 // Else, encode with the SIB byte
639 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
640 if (disp == 0 && base != RBP_enc && base != R13_enc) {
641 // If no displacement
642 emit_rm(cbuf, 0x0, regenc, 0x4); // *
643 emit_rm(cbuf, scale, indexenc, baseenc);
644 } else {
645 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
646 // If 8-bit displacement, mode 0x1
647 emit_rm(cbuf, 0x1, regenc, 0x4); // *
648 emit_rm(cbuf, scale, indexenc, baseenc);
649 emit_d8(cbuf, disp);
650 } else {
651 // If 32-bit displacement
652 if (base == 0x04 ) {
653 emit_rm(cbuf, 0x2, regenc, 0x4);
654 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
655 } else {
656 emit_rm(cbuf, 0x2, regenc, 0x4);
657 emit_rm(cbuf, scale, indexenc, baseenc); // *
658 }
659 if (disp_reloc != relocInfo::none) {
660 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
661 } else {
662 emit_d32(cbuf, disp);
663 }
664 }
665 }
666 }
667 }
668
669 // This could be in MacroAssembler but it's fairly C2 specific
670 void emit_cmpfp_fixup(MacroAssembler& _masm) {
671 Label exit;
672 __ jccb(Assembler::noParity, exit);
673 __ pushf();
674 //
675 // comiss/ucomiss instructions set ZF,PF,CF flags and
676 // zero OF,AF,SF for NaN values.
677 // Fixup flags by zeroing ZF,PF so that compare of NaN
678 // values returns 'less than' result (CF is set).
679 // Leave the rest of flags unchanged.
680 //
681 // 7 6 5 4 3 2 1 0
682 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
683 // 0 0 1 0 1 0 1 1 (0x2B)
684 //
685 __ andq(Address(rsp, 0), 0xffffff2b);
686 __ popf();
687 __ bind(exit);
688 }
689
690 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
691 Label done;
692 __ movl(dst, -1);
693 __ jcc(Assembler::parity, done);
694 __ jcc(Assembler::below, done);
695 __ setb(Assembler::notEqual, dst);
696 __ movzbl(dst, dst);
697 __ bind(done);
698 }
699
700 // Math.min() # Math.max()
701 // --------------------------
702 // ucomis[s/d] #
703 // ja -> b # a
704 // jp -> NaN # NaN
705 // jb -> a # b
706 // je #
707 // |-jz -> a | b # a & b
708 // | -> a #
709 void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
710 XMMRegister a, XMMRegister b,
711 XMMRegister xmmt, Register rt,
712 bool min, bool single) {
713
714 Label nan, zero, below, above, done;
715
716 if (single)
717 __ ucomiss(a, b);
718 else
719 __ ucomisd(a, b);
720
721 if (dst->encoding() != (min ? b : a)->encoding())
722 __ jccb(Assembler::above, above); // CF=0 & ZF=0
723 else
724 __ jccb(Assembler::above, done);
725
726 __ jccb(Assembler::parity, nan); // PF=1
727 __ jccb(Assembler::below, below); // CF=1
728
729 // equal
730 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
731 if (single) {
732 __ ucomiss(a, xmmt);
733 __ jccb(Assembler::equal, zero);
734
735 __ movflt(dst, a);
736 __ jmp(done);
737 }
738 else {
739 __ ucomisd(a, xmmt);
740 __ jccb(Assembler::equal, zero);
741
742 __ movdbl(dst, a);
743 __ jmp(done);
744 }
745
746 __ bind(zero);
747 if (min)
748 __ vpor(dst, a, b, Assembler::AVX_128bit);
749 else
750 __ vpand(dst, a, b, Assembler::AVX_128bit);
751
752 __ jmp(done);
753
754 __ bind(above);
755 if (single)
756 __ movflt(dst, min ? b : a);
757 else
758 __ movdbl(dst, min ? b : a);
759
760 __ jmp(done);
761
762 __ bind(nan);
763 if (single) {
764 __ movl(rt, 0x7fc00000); // Float.NaN
765 __ movdl(dst, rt);
766 }
767 else {
768 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
769 __ movdq(dst, rt);
770 }
771 __ jmp(done);
772
773 __ bind(below);
774 if (single)
775 __ movflt(dst, min ? a : b);
776 else
777 __ movdbl(dst, min ? a : b);
778
779 __ bind(done);
780 }
781
782 //=============================================================================
783 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
784
785 int Compile::ConstantTable::calculate_table_base_offset() const {
786 return 0; // absolute addressing, no offset
787 }
788
789 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
790 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
791 ShouldNotReachHere();
792 }
793
794 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
795 // Empty encoding
796 }
797
798 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
799 return 0;
800 }
801
802 #ifndef PRODUCT
803 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
804 st->print("# MachConstantBaseNode (empty encoding)");
805 }
806 #endif
807
808
809 //=============================================================================
810 #ifndef PRODUCT
811 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
812 Compile* C = ra_->C;
813
814 int framesize = C->frame_size_in_bytes();
815 int bangsize = C->bang_size_in_bytes();
816 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
817 // Remove wordSize for return addr which is already pushed.
818 framesize -= wordSize;
819
820 if (C->need_stack_bang(bangsize)) {
821 framesize -= wordSize;
822 st->print("# stack bang (%d bytes)", bangsize);
823 st->print("\n\t");
824 st->print("pushq rbp\t# Save rbp");
825 if (PreserveFramePointer) {
826 st->print("\n\t");
827 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
828 }
829 if (framesize) {
830 st->print("\n\t");
831 st->print("subq rsp, #%d\t# Create frame",framesize);
832 }
833 } else {
834 st->print("subq rsp, #%d\t# Create frame",framesize);
835 st->print("\n\t");
836 framesize -= wordSize;
837 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
838 if (PreserveFramePointer) {
839 st->print("\n\t");
840 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
841 if (framesize > 0) {
842 st->print("\n\t");
843 st->print("addq rbp, #%d", framesize);
844 }
845 }
846 }
847
848 if (VerifyStackAtCalls) {
849 st->print("\n\t");
850 framesize -= wordSize;
851 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
852 #ifdef ASSERT
853 st->print("\n\t");
854 st->print("# stack alignment check");
855 #endif
856 }
857 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
858 st->print("\n\t");
859 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
860 st->print("\n\t");
861 st->print("je fast_entry\t");
862 st->print("\n\t");
863 st->print("call #nmethod_entry_barrier_stub\t");
864 st->print("\n\tfast_entry:");
865 }
866 st->cr();
867 }
868 #endif
869
870 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
871 Compile* C = ra_->C;
872 MacroAssembler _masm(&cbuf);
873
874 int framesize = C->frame_size_in_bytes();
875 int bangsize = C->bang_size_in_bytes();
876
877 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
878
879 C->set_frame_complete(cbuf.insts_size());
880
881 if (C->has_mach_constant_base_node()) {
882 // NOTE: We set the table base offset here because users might be
883 // emitted before MachConstantBaseNode.
884 Compile::ConstantTable& constant_table = C->constant_table();
885 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
886 }
887 }
888
889 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
890 {
891 return MachNode::size(ra_); // too many variables; just compute it
892 // the hard way
893 }
894
895 int MachPrologNode::reloc() const
896 {
897 return 0; // a large enough number
898 }
899
900 //=============================================================================
901 #ifndef PRODUCT
902 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
903 {
904 Compile* C = ra_->C;
905 if (generate_vzeroupper(C)) {
906 st->print("vzeroupper");
907 st->cr(); st->print("\t");
908 }
909
910 int framesize = C->frame_size_in_bytes();
911 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
912 // Remove word for return adr already pushed
913 // and RBP
914 framesize -= 2*wordSize;
915
916 if (framesize) {
917 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
918 st->print("\t");
919 }
920
921 st->print_cr("popq rbp");
922 if (do_polling() && C->is_method_compilation()) {
923 st->print("\t");
924 if (SafepointMechanism::uses_thread_local_poll()) {
925 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
926 "testl rax, [rscratch1]\t"
927 "# Safepoint: poll for GC");
928 } else if (Assembler::is_polling_page_far()) {
929 st->print_cr("movq rscratch1, #polling_page_address\n\t"
930 "testl rax, [rscratch1]\t"
931 "# Safepoint: poll for GC");
932 } else {
933 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
934 "# Safepoint: poll for GC");
935 }
936 }
937 }
938 #endif
939
940 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
941 {
942 Compile* C = ra_->C;
943 MacroAssembler _masm(&cbuf);
944
945 if (generate_vzeroupper(C)) {
946 // Clear upper bits of YMM registers when current compiled code uses
947 // wide vectors to avoid AVX <-> SSE transition penalty during call.
948 __ vzeroupper();
949 }
950
951 int framesize = C->frame_size_in_bytes();
952 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
953 // Remove word for return adr already pushed
954 // and RBP
955 framesize -= 2*wordSize;
956
957 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
958
959 if (framesize) {
960 emit_opcode(cbuf, Assembler::REX_W);
961 if (framesize < 0x80) {
962 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
963 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
964 emit_d8(cbuf, framesize);
965 } else {
966 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
967 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
968 emit_d32(cbuf, framesize);
969 }
970 }
971
972 // popq rbp
973 emit_opcode(cbuf, 0x58 | RBP_enc);
974
975 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
976 __ reserved_stack_check();
977 }
978
979 if (do_polling() && C->is_method_compilation()) {
980 MacroAssembler _masm(&cbuf);
981 if (SafepointMechanism::uses_thread_local_poll()) {
982 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
983 __ relocate(relocInfo::poll_return_type);
984 __ testl(rax, Address(rscratch1, 0));
985 } else {
986 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
987 if (Assembler::is_polling_page_far()) {
988 __ lea(rscratch1, polling_page);
989 __ relocate(relocInfo::poll_return_type);
990 __ testl(rax, Address(rscratch1, 0));
991 } else {
992 __ testl(rax, polling_page);
993 }
994 }
995 }
996 }
997
998 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
999 {
1000 return MachNode::size(ra_); // too many variables; just compute it
1001 // the hard way
1002 }
1003
1004 int MachEpilogNode::reloc() const
1005 {
1006 return 2; // a large enough number
1007 }
1008
1009 const Pipeline* MachEpilogNode::pipeline() const
1010 {
1011 return MachNode::pipeline_class();
1012 }
1013
1014 int MachEpilogNode::safepoint_offset() const
1015 {
1016 return 0;
1017 }
1018
1019 //=============================================================================
1020
1021 enum RC {
1022 rc_bad,
1023 rc_int,
1024 rc_float,
1025 rc_stack
1026 };
1027
1028 static enum RC rc_class(OptoReg::Name reg)
1029 {
1030 if( !OptoReg::is_valid(reg) ) return rc_bad;
1031
1032 if (OptoReg::is_stack(reg)) return rc_stack;
1033
1034 VMReg r = OptoReg::as_VMReg(reg);
1035
1036 if (r->is_Register()) return rc_int;
1037
1038 assert(r->is_XMMRegister(), "must be");
1039 return rc_float;
1040 }
1041
1042 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1043 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1044 int src_hi, int dst_hi, uint ireg, outputStream* st);
1045
1046 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1047 int stack_offset, int reg, uint ireg, outputStream* st);
1048
1049 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1050 int dst_offset, uint ireg, outputStream* st) {
1051 if (cbuf) {
1052 MacroAssembler _masm(cbuf);
1053 switch (ireg) {
1054 case Op_VecS:
1055 __ movq(Address(rsp, -8), rax);
1056 __ movl(rax, Address(rsp, src_offset));
1057 __ movl(Address(rsp, dst_offset), rax);
1058 __ movq(rax, Address(rsp, -8));
1059 break;
1060 case Op_VecD:
1061 __ pushq(Address(rsp, src_offset));
1062 __ popq (Address(rsp, dst_offset));
1063 break;
1064 case Op_VecX:
1065 __ pushq(Address(rsp, src_offset));
1066 __ popq (Address(rsp, dst_offset));
1067 __ pushq(Address(rsp, src_offset+8));
1068 __ popq (Address(rsp, dst_offset+8));
1069 break;
1070 case Op_VecY:
1071 __ vmovdqu(Address(rsp, -32), xmm0);
1072 __ vmovdqu(xmm0, Address(rsp, src_offset));
1073 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1074 __ vmovdqu(xmm0, Address(rsp, -32));
1075 break;
1076 case Op_VecZ:
1077 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1078 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1079 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1080 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1081 break;
1082 default:
1083 ShouldNotReachHere();
1084 }
1085 #ifndef PRODUCT
1086 } else {
1087 switch (ireg) {
1088 case Op_VecS:
1089 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1090 "movl rax, [rsp + #%d]\n\t"
1091 "movl [rsp + #%d], rax\n\t"
1092 "movq rax, [rsp - #8]",
1093 src_offset, dst_offset);
1094 break;
1095 case Op_VecD:
1096 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1097 "popq [rsp + #%d]",
1098 src_offset, dst_offset);
1099 break;
1100 case Op_VecX:
1101 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1102 "popq [rsp + #%d]\n\t"
1103 "pushq [rsp + #%d]\n\t"
1104 "popq [rsp + #%d]",
1105 src_offset, dst_offset, src_offset+8, dst_offset+8);
1106 break;
1107 case Op_VecY:
1108 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1109 "vmovdqu xmm0, [rsp + #%d]\n\t"
1110 "vmovdqu [rsp + #%d], xmm0\n\t"
1111 "vmovdqu xmm0, [rsp - #32]",
1112 src_offset, dst_offset);
1113 break;
1114 case Op_VecZ:
1115 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1116 "vmovdqu xmm0, [rsp + #%d]\n\t"
1117 "vmovdqu [rsp + #%d], xmm0\n\t"
1118 "vmovdqu xmm0, [rsp - #64]",
1119 src_offset, dst_offset);
1120 break;
1121 default:
1122 ShouldNotReachHere();
1123 }
1124 #endif
1125 }
1126 }
1127
1128 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1129 PhaseRegAlloc* ra_,
1130 bool do_size,
1131 outputStream* st) const {
1132 assert(cbuf != NULL || st != NULL, "sanity");
1133 // Get registers to move
1134 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1135 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1136 OptoReg::Name dst_second = ra_->get_reg_second(this);
1137 OptoReg::Name dst_first = ra_->get_reg_first(this);
1138
1139 enum RC src_second_rc = rc_class(src_second);
1140 enum RC src_first_rc = rc_class(src_first);
1141 enum RC dst_second_rc = rc_class(dst_second);
1142 enum RC dst_first_rc = rc_class(dst_first);
1143
1144 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1145 "must move at least 1 register" );
1146
1147 if (src_first == dst_first && src_second == dst_second) {
1148 // Self copy, no move
1149 return 0;
1150 }
1151 if (bottom_type()->isa_vect() != NULL) {
1152 uint ireg = ideal_reg();
1153 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1154 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1155 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1156 // mem -> mem
1157 int src_offset = ra_->reg2offset(src_first);
1158 int dst_offset = ra_->reg2offset(dst_first);
1159 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1160 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1161 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1162 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1163 int stack_offset = ra_->reg2offset(dst_first);
1164 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1165 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1166 int stack_offset = ra_->reg2offset(src_first);
1167 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1168 } else {
1169 ShouldNotReachHere();
1170 }
1171 return 0;
1172 }
1173 if (src_first_rc == rc_stack) {
1174 // mem ->
1175 if (dst_first_rc == rc_stack) {
1176 // mem -> mem
1177 assert(src_second != dst_first, "overlap");
1178 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1179 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1180 // 64-bit
1181 int src_offset = ra_->reg2offset(src_first);
1182 int dst_offset = ra_->reg2offset(dst_first);
1183 if (cbuf) {
1184 MacroAssembler _masm(cbuf);
1185 __ pushq(Address(rsp, src_offset));
1186 __ popq (Address(rsp, dst_offset));
1187 #ifndef PRODUCT
1188 } else {
1189 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1190 "popq [rsp + #%d]",
1191 src_offset, dst_offset);
1192 #endif
1193 }
1194 } else {
1195 // 32-bit
1196 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1197 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1198 // No pushl/popl, so:
1199 int src_offset = ra_->reg2offset(src_first);
1200 int dst_offset = ra_->reg2offset(dst_first);
1201 if (cbuf) {
1202 MacroAssembler _masm(cbuf);
1203 __ movq(Address(rsp, -8), rax);
1204 __ movl(rax, Address(rsp, src_offset));
1205 __ movl(Address(rsp, dst_offset), rax);
1206 __ movq(rax, Address(rsp, -8));
1207 #ifndef PRODUCT
1208 } else {
1209 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1210 "movl rax, [rsp + #%d]\n\t"
1211 "movl [rsp + #%d], rax\n\t"
1212 "movq rax, [rsp - #8]",
1213 src_offset, dst_offset);
1214 #endif
1215 }
1216 }
1217 return 0;
1218 } else if (dst_first_rc == rc_int) {
1219 // mem -> gpr
1220 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1221 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1222 // 64-bit
1223 int offset = ra_->reg2offset(src_first);
1224 if (cbuf) {
1225 MacroAssembler _masm(cbuf);
1226 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1227 #ifndef PRODUCT
1228 } else {
1229 st->print("movq %s, [rsp + #%d]\t# spill",
1230 Matcher::regName[dst_first],
1231 offset);
1232 #endif
1233 }
1234 } else {
1235 // 32-bit
1236 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1237 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1238 int offset = ra_->reg2offset(src_first);
1239 if (cbuf) {
1240 MacroAssembler _masm(cbuf);
1241 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1242 #ifndef PRODUCT
1243 } else {
1244 st->print("movl %s, [rsp + #%d]\t# spill",
1245 Matcher::regName[dst_first],
1246 offset);
1247 #endif
1248 }
1249 }
1250 return 0;
1251 } else if (dst_first_rc == rc_float) {
1252 // mem-> xmm
1253 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1254 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1255 // 64-bit
1256 int offset = ra_->reg2offset(src_first);
1257 if (cbuf) {
1258 MacroAssembler _masm(cbuf);
1259 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1260 #ifndef PRODUCT
1261 } else {
1262 st->print("%s %s, [rsp + #%d]\t# spill",
1263 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1264 Matcher::regName[dst_first],
1265 offset);
1266 #endif
1267 }
1268 } else {
1269 // 32-bit
1270 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1271 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1272 int offset = ra_->reg2offset(src_first);
1273 if (cbuf) {
1274 MacroAssembler _masm(cbuf);
1275 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1276 #ifndef PRODUCT
1277 } else {
1278 st->print("movss %s, [rsp + #%d]\t# spill",
1279 Matcher::regName[dst_first],
1280 offset);
1281 #endif
1282 }
1283 }
1284 return 0;
1285 }
1286 } else if (src_first_rc == rc_int) {
1287 // gpr ->
1288 if (dst_first_rc == rc_stack) {
1289 // gpr -> mem
1290 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1291 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1292 // 64-bit
1293 int offset = ra_->reg2offset(dst_first);
1294 if (cbuf) {
1295 MacroAssembler _masm(cbuf);
1296 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1297 #ifndef PRODUCT
1298 } else {
1299 st->print("movq [rsp + #%d], %s\t# spill",
1300 offset,
1301 Matcher::regName[src_first]);
1302 #endif
1303 }
1304 } else {
1305 // 32-bit
1306 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1307 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1308 int offset = ra_->reg2offset(dst_first);
1309 if (cbuf) {
1310 MacroAssembler _masm(cbuf);
1311 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1312 #ifndef PRODUCT
1313 } else {
1314 st->print("movl [rsp + #%d], %s\t# spill",
1315 offset,
1316 Matcher::regName[src_first]);
1317 #endif
1318 }
1319 }
1320 return 0;
1321 } else if (dst_first_rc == rc_int) {
1322 // gpr -> gpr
1323 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1324 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1325 // 64-bit
1326 if (cbuf) {
1327 MacroAssembler _masm(cbuf);
1328 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1329 as_Register(Matcher::_regEncode[src_first]));
1330 #ifndef PRODUCT
1331 } else {
1332 st->print("movq %s, %s\t# spill",
1333 Matcher::regName[dst_first],
1334 Matcher::regName[src_first]);
1335 #endif
1336 }
1337 return 0;
1338 } else {
1339 // 32-bit
1340 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1341 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1342 if (cbuf) {
1343 MacroAssembler _masm(cbuf);
1344 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1345 as_Register(Matcher::_regEncode[src_first]));
1346 #ifndef PRODUCT
1347 } else {
1348 st->print("movl %s, %s\t# spill",
1349 Matcher::regName[dst_first],
1350 Matcher::regName[src_first]);
1351 #endif
1352 }
1353 return 0;
1354 }
1355 } else if (dst_first_rc == rc_float) {
1356 // gpr -> xmm
1357 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1358 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1359 // 64-bit
1360 if (cbuf) {
1361 MacroAssembler _masm(cbuf);
1362 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1363 #ifndef PRODUCT
1364 } else {
1365 st->print("movdq %s, %s\t# spill",
1366 Matcher::regName[dst_first],
1367 Matcher::regName[src_first]);
1368 #endif
1369 }
1370 } else {
1371 // 32-bit
1372 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1373 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1374 if (cbuf) {
1375 MacroAssembler _masm(cbuf);
1376 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1377 #ifndef PRODUCT
1378 } else {
1379 st->print("movdl %s, %s\t# spill",
1380 Matcher::regName[dst_first],
1381 Matcher::regName[src_first]);
1382 #endif
1383 }
1384 }
1385 return 0;
1386 }
1387 } else if (src_first_rc == rc_float) {
1388 // xmm ->
1389 if (dst_first_rc == rc_stack) {
1390 // xmm -> mem
1391 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1392 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1393 // 64-bit
1394 int offset = ra_->reg2offset(dst_first);
1395 if (cbuf) {
1396 MacroAssembler _masm(cbuf);
1397 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1398 #ifndef PRODUCT
1399 } else {
1400 st->print("movsd [rsp + #%d], %s\t# spill",
1401 offset,
1402 Matcher::regName[src_first]);
1403 #endif
1404 }
1405 } else {
1406 // 32-bit
1407 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1408 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1409 int offset = ra_->reg2offset(dst_first);
1410 if (cbuf) {
1411 MacroAssembler _masm(cbuf);
1412 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1413 #ifndef PRODUCT
1414 } else {
1415 st->print("movss [rsp + #%d], %s\t# spill",
1416 offset,
1417 Matcher::regName[src_first]);
1418 #endif
1419 }
1420 }
1421 return 0;
1422 } else if (dst_first_rc == rc_int) {
1423 // xmm -> gpr
1424 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1425 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1426 // 64-bit
1427 if (cbuf) {
1428 MacroAssembler _masm(cbuf);
1429 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1430 #ifndef PRODUCT
1431 } else {
1432 st->print("movdq %s, %s\t# spill",
1433 Matcher::regName[dst_first],
1434 Matcher::regName[src_first]);
1435 #endif
1436 }
1437 } else {
1438 // 32-bit
1439 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1440 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1441 if (cbuf) {
1442 MacroAssembler _masm(cbuf);
1443 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1444 #ifndef PRODUCT
1445 } else {
1446 st->print("movdl %s, %s\t# spill",
1447 Matcher::regName[dst_first],
1448 Matcher::regName[src_first]);
1449 #endif
1450 }
1451 }
1452 return 0;
1453 } else if (dst_first_rc == rc_float) {
1454 // xmm -> xmm
1455 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1456 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1457 // 64-bit
1458 if (cbuf) {
1459 MacroAssembler _masm(cbuf);
1460 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1461 #ifndef PRODUCT
1462 } else {
1463 st->print("%s %s, %s\t# spill",
1464 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1465 Matcher::regName[dst_first],
1466 Matcher::regName[src_first]);
1467 #endif
1468 }
1469 } else {
1470 // 32-bit
1471 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1472 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1473 if (cbuf) {
1474 MacroAssembler _masm(cbuf);
1475 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1476 #ifndef PRODUCT
1477 } else {
1478 st->print("%s %s, %s\t# spill",
1479 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1480 Matcher::regName[dst_first],
1481 Matcher::regName[src_first]);
1482 #endif
1483 }
1484 }
1485 return 0;
1486 }
1487 }
1488
1489 assert(0," foo ");
1490 Unimplemented();
1491 return 0;
1492 }
1493
1494 #ifndef PRODUCT
1495 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1496 implementation(NULL, ra_, false, st);
1497 }
1498 #endif
1499
1500 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1501 implementation(&cbuf, ra_, false, NULL);
1502 }
1503
1504 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1505 return MachNode::size(ra_);
1506 }
1507
1508 //=============================================================================
1509 #ifndef PRODUCT
1510 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1511 {
1512 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1513 int reg = ra_->get_reg_first(this);
1514 st->print("leaq %s, [rsp + #%d]\t# box lock",
1515 Matcher::regName[reg], offset);
1516 }
1517 #endif
1518
1519 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1520 {
1521 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1522 int reg = ra_->get_encode(this);
1523 if (offset >= 0x80) {
1524 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1525 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1526 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1527 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1528 emit_d32(cbuf, offset);
1529 } else {
1530 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1531 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1532 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1533 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1534 emit_d8(cbuf, offset);
1535 }
1536 }
1537
1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1539 {
1540 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1541 return (offset < 0x80) ? 5 : 8; // REX
1542 }
1543
1544 //=============================================================================
1545 #ifndef PRODUCT
1546 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1547 {
1548 if (UseCompressedClassPointers) {
1549 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1550 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1551 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1552 } else {
1553 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1554 "# Inline cache check");
1555 }
1556 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1557 st->print_cr("\tnop\t# nops to align entry point");
1558 }
1559 #endif
1560
1561 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1562 {
1563 MacroAssembler masm(&cbuf);
1564 uint insts_size = cbuf.insts_size();
1565 if (UseCompressedClassPointers) {
1566 masm.load_klass(rscratch1, j_rarg0);
1567 masm.cmpptr(rax, rscratch1);
1568 } else {
1569 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1570 }
1571
1572 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1573
1574 /* WARNING these NOPs are critical so that verified entry point is properly
1575 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1576 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1577 if (OptoBreakpoint) {
1578 // Leave space for int3
1579 nops_cnt -= 1;
1580 }
1581 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1582 if (nops_cnt > 0)
1583 masm.nop(nops_cnt);
1584 }
1585
1586 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1587 {
1588 return MachNode::size(ra_); // too many variables; just compute it
1589 // the hard way
1590 }
1591
1592
1593 //=============================================================================
1594
1595 int Matcher::regnum_to_fpu_offset(int regnum)
1596 {
1597 return regnum - 32; // The FP registers are in the second chunk
1598 }
1599
1600 // This is UltraSparc specific, true just means we have fast l2f conversion
1601 const bool Matcher::convL2FSupported(void) {
1602 return true;
1603 }
1604
1605 // Is this branch offset short enough that a short branch can be used?
1606 //
1607 // NOTE: If the platform does not provide any short branch variants, then
1608 // this method should return false for offset 0.
1609 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1610 // The passed offset is relative to address of the branch.
1611 // On 86 a branch displacement is calculated relative to address
1612 // of a next instruction.
1613 offset -= br_size;
1614
1615 // the short version of jmpConUCF2 contains multiple branches,
1616 // making the reach slightly less
1617 if (rule == jmpConUCF2_rule)
1618 return (-126 <= offset && offset <= 125);
1619 return (-128 <= offset && offset <= 127);
1620 }
1621
1622 const bool Matcher::isSimpleConstant64(jlong value) {
1623 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1624 //return value == (int) value; // Cf. storeImmL and immL32.
1625
1626 // Probably always true, even if a temp register is required.
1627 return true;
1628 }
1629
1630 // The ecx parameter to rep stosq for the ClearArray node is in words.
1631 const bool Matcher::init_array_count_is_in_bytes = false;
1632
1633 // No additional cost for CMOVL.
1634 const int Matcher::long_cmove_cost() { return 0; }
1635
1636 // No CMOVF/CMOVD with SSE2
1637 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1638
1639 // Does the CPU require late expand (see block.cpp for description of late expand)?
1640 const bool Matcher::require_postalloc_expand = false;
1641
1642 // Do we need to mask the count passed to shift instructions or does
1643 // the cpu only look at the lower 5/6 bits anyway?
1644 const bool Matcher::need_masked_shift_count = false;
1645
1646 bool Matcher::narrow_oop_use_complex_address() {
1647 assert(UseCompressedOops, "only for compressed oops code");
1648 return (LogMinObjAlignmentInBytes <= 3);
1649 }
1650
1651 bool Matcher::narrow_klass_use_complex_address() {
1652 assert(UseCompressedClassPointers, "only for compressed klass code");
1653 return (LogKlassAlignmentInBytes <= 3);
1654 }
1655
1656 bool Matcher::const_oop_prefer_decode() {
1657 // Prefer ConN+DecodeN over ConP.
1658 return true;
1659 }
1660
1661 bool Matcher::const_klass_prefer_decode() {
1662 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1663 // or condisider the following:
1664 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1665 //return Universe::narrow_klass_base() == NULL;
1666 return true;
1667 }
1668
1669 // Is it better to copy float constants, or load them directly from
1670 // memory? Intel can load a float constant from a direct address,
1671 // requiring no extra registers. Most RISCs will have to materialize
1672 // an address into a register first, so they would do better to copy
1673 // the constant from stack.
1674 const bool Matcher::rematerialize_float_constants = true; // XXX
1675
1676 // If CPU can load and store mis-aligned doubles directly then no
1677 // fixup is needed. Else we split the double into 2 integer pieces
1678 // and move it piece-by-piece. Only happens when passing doubles into
1679 // C code as the Java calling convention forces doubles to be aligned.
1680 const bool Matcher::misaligned_doubles_ok = true;
1681
1682 // No-op on amd64
1683 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1684
1685 // Advertise here if the CPU requires explicit rounding operations to
1686 // implement the UseStrictFP mode.
1687 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1688
1689 // Are floats conerted to double when stored to stack during deoptimization?
1690 // On x64 it is stored without convertion so we can use normal access.
1691 bool Matcher::float_in_double() { return false; }
1692
1693 // Do ints take an entire long register or just half?
1694 const bool Matcher::int_in_long = true;
1695
1696 // Return whether or not this register is ever used as an argument.
1697 // This function is used on startup to build the trampoline stubs in
1698 // generateOptoStub. Registers not mentioned will be killed by the VM
1699 // call in the trampoline, and arguments in those registers not be
1700 // available to the callee.
1701 bool Matcher::can_be_java_arg(int reg)
1702 {
1703 return
1704 reg == RDI_num || reg == RDI_H_num ||
1705 reg == RSI_num || reg == RSI_H_num ||
1706 reg == RDX_num || reg == RDX_H_num ||
1707 reg == RCX_num || reg == RCX_H_num ||
1708 reg == R8_num || reg == R8_H_num ||
1709 reg == R9_num || reg == R9_H_num ||
1710 reg == R12_num || reg == R12_H_num ||
1711 reg == XMM0_num || reg == XMM0b_num ||
1712 reg == XMM1_num || reg == XMM1b_num ||
1713 reg == XMM2_num || reg == XMM2b_num ||
1714 reg == XMM3_num || reg == XMM3b_num ||
1715 reg == XMM4_num || reg == XMM4b_num ||
1716 reg == XMM5_num || reg == XMM5b_num ||
1717 reg == XMM6_num || reg == XMM6b_num ||
1718 reg == XMM7_num || reg == XMM7b_num;
1719 }
1720
1721 bool Matcher::is_spillable_arg(int reg)
1722 {
1723 return can_be_java_arg(reg);
1724 }
1725
1726 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1727 // In 64 bit mode a code which use multiply when
1728 // devisor is constant is faster than hardware
1729 // DIV instruction (it uses MulHiL).
1730 return false;
1731 }
1732
1733 // Register for DIVI projection of divmodI
1734 RegMask Matcher::divI_proj_mask() {
1735 return INT_RAX_REG_mask();
1736 }
1737
1738 // Register for MODI projection of divmodI
1739 RegMask Matcher::modI_proj_mask() {
1740 return INT_RDX_REG_mask();
1741 }
1742
1743 // Register for DIVL projection of divmodL
1744 RegMask Matcher::divL_proj_mask() {
1745 return LONG_RAX_REG_mask();
1746 }
1747
1748 // Register for MODL projection of divmodL
1749 RegMask Matcher::modL_proj_mask() {
1750 return LONG_RDX_REG_mask();
1751 }
1752
1753 // Register for saving SP into on method handle invokes. Not used on x86_64.
1754 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1755 return NO_REG_mask();
1756 }
1757
1758 %}
1759
1760 //----------ENCODING BLOCK-----------------------------------------------------
1761 // This block specifies the encoding classes used by the compiler to
1762 // output byte streams. Encoding classes are parameterized macros
1763 // used by Machine Instruction Nodes in order to generate the bit
1764 // encoding of the instruction. Operands specify their base encoding
1765 // interface with the interface keyword. There are currently
1766 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1767 // COND_INTER. REG_INTER causes an operand to generate a function
1768 // which returns its register number when queried. CONST_INTER causes
1769 // an operand to generate a function which returns the value of the
1770 // constant when queried. MEMORY_INTER causes an operand to generate
1771 // four functions which return the Base Register, the Index Register,
1772 // the Scale Value, and the Offset Value of the operand when queried.
1773 // COND_INTER causes an operand to generate six functions which return
1774 // the encoding code (ie - encoding bits for the instruction)
1775 // associated with each basic boolean condition for a conditional
1776 // instruction.
1777 //
1778 // Instructions specify two basic values for encoding. Again, a
1779 // function is available to check if the constant displacement is an
1780 // oop. They use the ins_encode keyword to specify their encoding
1781 // classes (which must be a sequence of enc_class names, and their
1782 // parameters, specified in the encoding block), and they use the
1783 // opcode keyword to specify, in order, their primary, secondary, and
1784 // tertiary opcode. Only the opcode sections which a particular
1785 // instruction needs for encoding need to be specified.
1786 encode %{
1787 // Build emit functions for each basic byte or larger field in the
1788 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1789 // from C++ code in the enc_class source block. Emit functions will
1790 // live in the main source block for now. In future, we can
1791 // generalize this by adding a syntax that specifies the sizes of
1792 // fields in an order, so that the adlc can build the emit functions
1793 // automagically
1794
1795 // Emit primary opcode
1796 enc_class OpcP
1797 %{
1798 emit_opcode(cbuf, $primary);
1799 %}
1800
1801 // Emit secondary opcode
1802 enc_class OpcS
1803 %{
1804 emit_opcode(cbuf, $secondary);
1805 %}
1806
1807 // Emit tertiary opcode
1808 enc_class OpcT
1809 %{
1810 emit_opcode(cbuf, $tertiary);
1811 %}
1812
1813 // Emit opcode directly
1814 enc_class Opcode(immI d8)
1815 %{
1816 emit_opcode(cbuf, $d8$$constant);
1817 %}
1818
1819 // Emit size prefix
1820 enc_class SizePrefix
1821 %{
1822 emit_opcode(cbuf, 0x66);
1823 %}
1824
1825 enc_class reg(rRegI reg)
1826 %{
1827 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1828 %}
1829
1830 enc_class reg_reg(rRegI dst, rRegI src)
1831 %{
1832 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1833 %}
1834
1835 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1836 %{
1837 emit_opcode(cbuf, $opcode$$constant);
1838 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1839 %}
1840
1841 enc_class cdql_enc(no_rax_rdx_RegI div)
1842 %{
1843 // Full implementation of Java idiv and irem; checks for
1844 // special case as described in JVM spec., p.243 & p.271.
1845 //
1846 // normal case special case
1847 //
1848 // input : rax: dividend min_int
1849 // reg: divisor -1
1850 //
1851 // output: rax: quotient (= rax idiv reg) min_int
1852 // rdx: remainder (= rax irem reg) 0
1853 //
1854 // Code sequnce:
1855 //
1856 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1857 // 5: 75 07/08 jne e <normal>
1858 // 7: 33 d2 xor %edx,%edx
1859 // [div >= 8 -> offset + 1]
1860 // [REX_B]
1861 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1862 // c: 74 03/04 je 11 <done>
1863 // 000000000000000e <normal>:
1864 // e: 99 cltd
1865 // [div >= 8 -> offset + 1]
1866 // [REX_B]
1867 // f: f7 f9 idiv $div
1868 // 0000000000000011 <done>:
1869
1870 // cmp $0x80000000,%eax
1871 emit_opcode(cbuf, 0x3d);
1872 emit_d8(cbuf, 0x00);
1873 emit_d8(cbuf, 0x00);
1874 emit_d8(cbuf, 0x00);
1875 emit_d8(cbuf, 0x80);
1876
1877 // jne e <normal>
1878 emit_opcode(cbuf, 0x75);
1879 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1880
1881 // xor %edx,%edx
1882 emit_opcode(cbuf, 0x33);
1883 emit_d8(cbuf, 0xD2);
1884
1885 // cmp $0xffffffffffffffff,%ecx
1886 if ($div$$reg >= 8) {
1887 emit_opcode(cbuf, Assembler::REX_B);
1888 }
1889 emit_opcode(cbuf, 0x83);
1890 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1891 emit_d8(cbuf, 0xFF);
1892
1893 // je 11 <done>
1894 emit_opcode(cbuf, 0x74);
1895 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1896
1897 // <normal>
1898 // cltd
1899 emit_opcode(cbuf, 0x99);
1900
1901 // idivl (note: must be emitted by the user of this rule)
1902 // <done>
1903 %}
1904
1905 enc_class cdqq_enc(no_rax_rdx_RegL div)
1906 %{
1907 // Full implementation of Java ldiv and lrem; checks for
1908 // special case as described in JVM spec., p.243 & p.271.
1909 //
1910 // normal case special case
1911 //
1912 // input : rax: dividend min_long
1913 // reg: divisor -1
1914 //
1915 // output: rax: quotient (= rax idiv reg) min_long
1916 // rdx: remainder (= rax irem reg) 0
1917 //
1918 // Code sequnce:
1919 //
1920 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1921 // 7: 00 00 80
1922 // a: 48 39 d0 cmp %rdx,%rax
1923 // d: 75 08 jne 17 <normal>
1924 // f: 33 d2 xor %edx,%edx
1925 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1926 // 15: 74 05 je 1c <done>
1927 // 0000000000000017 <normal>:
1928 // 17: 48 99 cqto
1929 // 19: 48 f7 f9 idiv $div
1930 // 000000000000001c <done>:
1931
1932 // mov $0x8000000000000000,%rdx
1933 emit_opcode(cbuf, Assembler::REX_W);
1934 emit_opcode(cbuf, 0xBA);
1935 emit_d8(cbuf, 0x00);
1936 emit_d8(cbuf, 0x00);
1937 emit_d8(cbuf, 0x00);
1938 emit_d8(cbuf, 0x00);
1939 emit_d8(cbuf, 0x00);
1940 emit_d8(cbuf, 0x00);
1941 emit_d8(cbuf, 0x00);
1942 emit_d8(cbuf, 0x80);
1943
1944 // cmp %rdx,%rax
1945 emit_opcode(cbuf, Assembler::REX_W);
1946 emit_opcode(cbuf, 0x39);
1947 emit_d8(cbuf, 0xD0);
1948
1949 // jne 17 <normal>
1950 emit_opcode(cbuf, 0x75);
1951 emit_d8(cbuf, 0x08);
1952
1953 // xor %edx,%edx
1954 emit_opcode(cbuf, 0x33);
1955 emit_d8(cbuf, 0xD2);
1956
1957 // cmp $0xffffffffffffffff,$div
1958 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1959 emit_opcode(cbuf, 0x83);
1960 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1961 emit_d8(cbuf, 0xFF);
1962
1963 // je 1e <done>
1964 emit_opcode(cbuf, 0x74);
1965 emit_d8(cbuf, 0x05);
1966
1967 // <normal>
1968 // cqto
1969 emit_opcode(cbuf, Assembler::REX_W);
1970 emit_opcode(cbuf, 0x99);
1971
1972 // idivq (note: must be emitted by the user of this rule)
1973 // <done>
1974 %}
1975
1976 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1977 enc_class OpcSE(immI imm)
1978 %{
1979 // Emit primary opcode and set sign-extend bit
1980 // Check for 8-bit immediate, and set sign extend bit in opcode
1981 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1982 emit_opcode(cbuf, $primary | 0x02);
1983 } else {
1984 // 32-bit immediate
1985 emit_opcode(cbuf, $primary);
1986 }
1987 %}
1988
1989 enc_class OpcSErm(rRegI dst, immI imm)
1990 %{
1991 // OpcSEr/m
1992 int dstenc = $dst$$reg;
1993 if (dstenc >= 8) {
1994 emit_opcode(cbuf, Assembler::REX_B);
1995 dstenc -= 8;
1996 }
1997 // Emit primary opcode and set sign-extend bit
1998 // Check for 8-bit immediate, and set sign extend bit in opcode
1999 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2000 emit_opcode(cbuf, $primary | 0x02);
2001 } else {
2002 // 32-bit immediate
2003 emit_opcode(cbuf, $primary);
2004 }
2005 // Emit r/m byte with secondary opcode, after primary opcode.
2006 emit_rm(cbuf, 0x3, $secondary, dstenc);
2007 %}
2008
2009 enc_class OpcSErm_wide(rRegL dst, immI imm)
2010 %{
2011 // OpcSEr/m
2012 int dstenc = $dst$$reg;
2013 if (dstenc < 8) {
2014 emit_opcode(cbuf, Assembler::REX_W);
2015 } else {
2016 emit_opcode(cbuf, Assembler::REX_WB);
2017 dstenc -= 8;
2018 }
2019 // Emit primary opcode and set sign-extend bit
2020 // Check for 8-bit immediate, and set sign extend bit in opcode
2021 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2022 emit_opcode(cbuf, $primary | 0x02);
2023 } else {
2024 // 32-bit immediate
2025 emit_opcode(cbuf, $primary);
2026 }
2027 // Emit r/m byte with secondary opcode, after primary opcode.
2028 emit_rm(cbuf, 0x3, $secondary, dstenc);
2029 %}
2030
2031 enc_class Con8or32(immI imm)
2032 %{
2033 // Check for 8-bit immediate, and set sign extend bit in opcode
2034 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2035 $$$emit8$imm$$constant;
2036 } else {
2037 // 32-bit immediate
2038 $$$emit32$imm$$constant;
2039 }
2040 %}
2041
2042 enc_class opc2_reg(rRegI dst)
2043 %{
2044 // BSWAP
2045 emit_cc(cbuf, $secondary, $dst$$reg);
2046 %}
2047
2048 enc_class opc3_reg(rRegI dst)
2049 %{
2050 // BSWAP
2051 emit_cc(cbuf, $tertiary, $dst$$reg);
2052 %}
2053
2054 enc_class reg_opc(rRegI div)
2055 %{
2056 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2057 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2058 %}
2059
2060 enc_class enc_cmov(cmpOp cop)
2061 %{
2062 // CMOV
2063 $$$emit8$primary;
2064 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2065 %}
2066
2067 enc_class enc_PartialSubtypeCheck()
2068 %{
2069 Register Rrdi = as_Register(RDI_enc); // result register
2070 Register Rrax = as_Register(RAX_enc); // super class
2071 Register Rrcx = as_Register(RCX_enc); // killed
2072 Register Rrsi = as_Register(RSI_enc); // sub class
2073 Label miss;
2074 const bool set_cond_codes = true;
2075
2076 MacroAssembler _masm(&cbuf);
2077 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2078 NULL, &miss,
2079 /*set_cond_codes:*/ true);
2080 if ($primary) {
2081 __ xorptr(Rrdi, Rrdi);
2082 }
2083 __ bind(miss);
2084 %}
2085
2086 enc_class clear_avx %{
2087 debug_only(int off0 = cbuf.insts_size());
2088 if (generate_vzeroupper(Compile::current())) {
2089 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2090 // Clear upper bits of YMM registers when current compiled code uses
2091 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2092 MacroAssembler _masm(&cbuf);
2093 __ vzeroupper();
2094 }
2095 debug_only(int off1 = cbuf.insts_size());
2096 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2097 %}
2098
2099 enc_class Java_To_Runtime(method meth) %{
2100 // No relocation needed
2101 MacroAssembler _masm(&cbuf);
2102 __ mov64(r10, (int64_t) $meth$$method);
2103 __ call(r10);
2104 %}
2105
2106 enc_class Java_To_Interpreter(method meth)
2107 %{
2108 // CALL Java_To_Interpreter
2109 // This is the instruction starting address for relocation info.
2110 cbuf.set_insts_mark();
2111 $$$emit8$primary;
2112 // CALL directly to the runtime
2113 emit_d32_reloc(cbuf,
2114 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2115 runtime_call_Relocation::spec(),
2116 RELOC_DISP32);
2117 %}
2118
2119 enc_class Java_Static_Call(method meth)
2120 %{
2121 // JAVA STATIC CALL
2122 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2123 // determine who we intended to call.
2124 cbuf.set_insts_mark();
2125 $$$emit8$primary;
2126
2127 if (!_method) {
2128 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2129 runtime_call_Relocation::spec(),
2130 RELOC_DISP32);
2131 } else {
2132 int method_index = resolved_method_index(cbuf);
2133 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2134 : static_call_Relocation::spec(method_index);
2135 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2136 rspec, RELOC_DISP32);
2137 // Emit stubs for static call.
2138 address mark = cbuf.insts_mark();
2139 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2140 if (stub == NULL) {
2141 ciEnv::current()->record_failure("CodeCache is full");
2142 return;
2143 }
2144 #if INCLUDE_AOT
2145 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2146 #endif
2147 }
2148 %}
2149
2150 enc_class Java_Dynamic_Call(method meth) %{
2151 MacroAssembler _masm(&cbuf);
2152 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2153 %}
2154
2155 enc_class Java_Compiled_Call(method meth)
2156 %{
2157 // JAVA COMPILED CALL
2158 int disp = in_bytes(Method:: from_compiled_offset());
2159
2160 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2161 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2162
2163 // callq *disp(%rax)
2164 cbuf.set_insts_mark();
2165 $$$emit8$primary;
2166 if (disp < 0x80) {
2167 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2168 emit_d8(cbuf, disp); // Displacement
2169 } else {
2170 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2171 emit_d32(cbuf, disp); // Displacement
2172 }
2173 %}
2174
2175 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2176 %{
2177 // SAL, SAR, SHR
2178 int dstenc = $dst$$reg;
2179 if (dstenc >= 8) {
2180 emit_opcode(cbuf, Assembler::REX_B);
2181 dstenc -= 8;
2182 }
2183 $$$emit8$primary;
2184 emit_rm(cbuf, 0x3, $secondary, dstenc);
2185 $$$emit8$shift$$constant;
2186 %}
2187
2188 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2189 %{
2190 // SAL, SAR, SHR
2191 int dstenc = $dst$$reg;
2192 if (dstenc < 8) {
2193 emit_opcode(cbuf, Assembler::REX_W);
2194 } else {
2195 emit_opcode(cbuf, Assembler::REX_WB);
2196 dstenc -= 8;
2197 }
2198 $$$emit8$primary;
2199 emit_rm(cbuf, 0x3, $secondary, dstenc);
2200 $$$emit8$shift$$constant;
2201 %}
2202
2203 enc_class load_immI(rRegI dst, immI src)
2204 %{
2205 int dstenc = $dst$$reg;
2206 if (dstenc >= 8) {
2207 emit_opcode(cbuf, Assembler::REX_B);
2208 dstenc -= 8;
2209 }
2210 emit_opcode(cbuf, 0xB8 | dstenc);
2211 $$$emit32$src$$constant;
2212 %}
2213
2214 enc_class load_immL(rRegL dst, immL src)
2215 %{
2216 int dstenc = $dst$$reg;
2217 if (dstenc < 8) {
2218 emit_opcode(cbuf, Assembler::REX_W);
2219 } else {
2220 emit_opcode(cbuf, Assembler::REX_WB);
2221 dstenc -= 8;
2222 }
2223 emit_opcode(cbuf, 0xB8 | dstenc);
2224 emit_d64(cbuf, $src$$constant);
2225 %}
2226
2227 enc_class load_immUL32(rRegL dst, immUL32 src)
2228 %{
2229 // same as load_immI, but this time we care about zeroes in the high word
2230 int dstenc = $dst$$reg;
2231 if (dstenc >= 8) {
2232 emit_opcode(cbuf, Assembler::REX_B);
2233 dstenc -= 8;
2234 }
2235 emit_opcode(cbuf, 0xB8 | dstenc);
2236 $$$emit32$src$$constant;
2237 %}
2238
2239 enc_class load_immL32(rRegL dst, immL32 src)
2240 %{
2241 int dstenc = $dst$$reg;
2242 if (dstenc < 8) {
2243 emit_opcode(cbuf, Assembler::REX_W);
2244 } else {
2245 emit_opcode(cbuf, Assembler::REX_WB);
2246 dstenc -= 8;
2247 }
2248 emit_opcode(cbuf, 0xC7);
2249 emit_rm(cbuf, 0x03, 0x00, dstenc);
2250 $$$emit32$src$$constant;
2251 %}
2252
2253 enc_class load_immP31(rRegP dst, immP32 src)
2254 %{
2255 // same as load_immI, but this time we care about zeroes in the high word
2256 int dstenc = $dst$$reg;
2257 if (dstenc >= 8) {
2258 emit_opcode(cbuf, Assembler::REX_B);
2259 dstenc -= 8;
2260 }
2261 emit_opcode(cbuf, 0xB8 | dstenc);
2262 $$$emit32$src$$constant;
2263 %}
2264
2265 enc_class load_immP(rRegP dst, immP src)
2266 %{
2267 int dstenc = $dst$$reg;
2268 if (dstenc < 8) {
2269 emit_opcode(cbuf, Assembler::REX_W);
2270 } else {
2271 emit_opcode(cbuf, Assembler::REX_WB);
2272 dstenc -= 8;
2273 }
2274 emit_opcode(cbuf, 0xB8 | dstenc);
2275 // This next line should be generated from ADLC
2276 if ($src->constant_reloc() != relocInfo::none) {
2277 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2278 } else {
2279 emit_d64(cbuf, $src$$constant);
2280 }
2281 %}
2282
2283 enc_class Con32(immI src)
2284 %{
2285 // Output immediate
2286 $$$emit32$src$$constant;
2287 %}
2288
2289 enc_class Con32F_as_bits(immF src)
2290 %{
2291 // Output Float immediate bits
2292 jfloat jf = $src$$constant;
2293 jint jf_as_bits = jint_cast(jf);
2294 emit_d32(cbuf, jf_as_bits);
2295 %}
2296
2297 enc_class Con16(immI src)
2298 %{
2299 // Output immediate
2300 $$$emit16$src$$constant;
2301 %}
2302
2303 // How is this different from Con32??? XXX
2304 enc_class Con_d32(immI src)
2305 %{
2306 emit_d32(cbuf,$src$$constant);
2307 %}
2308
2309 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2310 // Output immediate memory reference
2311 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2312 emit_d32(cbuf, 0x00);
2313 %}
2314
2315 enc_class lock_prefix()
2316 %{
2317 emit_opcode(cbuf, 0xF0); // lock
2318 %}
2319
2320 enc_class REX_mem(memory mem)
2321 %{
2322 if ($mem$$base >= 8) {
2323 if ($mem$$index < 8) {
2324 emit_opcode(cbuf, Assembler::REX_B);
2325 } else {
2326 emit_opcode(cbuf, Assembler::REX_XB);
2327 }
2328 } else {
2329 if ($mem$$index >= 8) {
2330 emit_opcode(cbuf, Assembler::REX_X);
2331 }
2332 }
2333 %}
2334
2335 enc_class REX_mem_wide(memory mem)
2336 %{
2337 if ($mem$$base >= 8) {
2338 if ($mem$$index < 8) {
2339 emit_opcode(cbuf, Assembler::REX_WB);
2340 } else {
2341 emit_opcode(cbuf, Assembler::REX_WXB);
2342 }
2343 } else {
2344 if ($mem$$index < 8) {
2345 emit_opcode(cbuf, Assembler::REX_W);
2346 } else {
2347 emit_opcode(cbuf, Assembler::REX_WX);
2348 }
2349 }
2350 %}
2351
2352 // for byte regs
2353 enc_class REX_breg(rRegI reg)
2354 %{
2355 if ($reg$$reg >= 4) {
2356 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2357 }
2358 %}
2359
2360 // for byte regs
2361 enc_class REX_reg_breg(rRegI dst, rRegI src)
2362 %{
2363 if ($dst$$reg < 8) {
2364 if ($src$$reg >= 4) {
2365 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2366 }
2367 } else {
2368 if ($src$$reg < 8) {
2369 emit_opcode(cbuf, Assembler::REX_R);
2370 } else {
2371 emit_opcode(cbuf, Assembler::REX_RB);
2372 }
2373 }
2374 %}
2375
2376 // for byte regs
2377 enc_class REX_breg_mem(rRegI reg, memory mem)
2378 %{
2379 if ($reg$$reg < 8) {
2380 if ($mem$$base < 8) {
2381 if ($mem$$index >= 8) {
2382 emit_opcode(cbuf, Assembler::REX_X);
2383 } else if ($reg$$reg >= 4) {
2384 emit_opcode(cbuf, Assembler::REX);
2385 }
2386 } else {
2387 if ($mem$$index < 8) {
2388 emit_opcode(cbuf, Assembler::REX_B);
2389 } else {
2390 emit_opcode(cbuf, Assembler::REX_XB);
2391 }
2392 }
2393 } else {
2394 if ($mem$$base < 8) {
2395 if ($mem$$index < 8) {
2396 emit_opcode(cbuf, Assembler::REX_R);
2397 } else {
2398 emit_opcode(cbuf, Assembler::REX_RX);
2399 }
2400 } else {
2401 if ($mem$$index < 8) {
2402 emit_opcode(cbuf, Assembler::REX_RB);
2403 } else {
2404 emit_opcode(cbuf, Assembler::REX_RXB);
2405 }
2406 }
2407 }
2408 %}
2409
2410 enc_class REX_reg(rRegI reg)
2411 %{
2412 if ($reg$$reg >= 8) {
2413 emit_opcode(cbuf, Assembler::REX_B);
2414 }
2415 %}
2416
2417 enc_class REX_reg_wide(rRegI reg)
2418 %{
2419 if ($reg$$reg < 8) {
2420 emit_opcode(cbuf, Assembler::REX_W);
2421 } else {
2422 emit_opcode(cbuf, Assembler::REX_WB);
2423 }
2424 %}
2425
2426 enc_class REX_reg_reg(rRegI dst, rRegI src)
2427 %{
2428 if ($dst$$reg < 8) {
2429 if ($src$$reg >= 8) {
2430 emit_opcode(cbuf, Assembler::REX_B);
2431 }
2432 } else {
2433 if ($src$$reg < 8) {
2434 emit_opcode(cbuf, Assembler::REX_R);
2435 } else {
2436 emit_opcode(cbuf, Assembler::REX_RB);
2437 }
2438 }
2439 %}
2440
2441 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2442 %{
2443 if ($dst$$reg < 8) {
2444 if ($src$$reg < 8) {
2445 emit_opcode(cbuf, Assembler::REX_W);
2446 } else {
2447 emit_opcode(cbuf, Assembler::REX_WB);
2448 }
2449 } else {
2450 if ($src$$reg < 8) {
2451 emit_opcode(cbuf, Assembler::REX_WR);
2452 } else {
2453 emit_opcode(cbuf, Assembler::REX_WRB);
2454 }
2455 }
2456 %}
2457
2458 enc_class REX_reg_mem(rRegI reg, memory mem)
2459 %{
2460 if ($reg$$reg < 8) {
2461 if ($mem$$base < 8) {
2462 if ($mem$$index >= 8) {
2463 emit_opcode(cbuf, Assembler::REX_X);
2464 }
2465 } else {
2466 if ($mem$$index < 8) {
2467 emit_opcode(cbuf, Assembler::REX_B);
2468 } else {
2469 emit_opcode(cbuf, Assembler::REX_XB);
2470 }
2471 }
2472 } else {
2473 if ($mem$$base < 8) {
2474 if ($mem$$index < 8) {
2475 emit_opcode(cbuf, Assembler::REX_R);
2476 } else {
2477 emit_opcode(cbuf, Assembler::REX_RX);
2478 }
2479 } else {
2480 if ($mem$$index < 8) {
2481 emit_opcode(cbuf, Assembler::REX_RB);
2482 } else {
2483 emit_opcode(cbuf, Assembler::REX_RXB);
2484 }
2485 }
2486 }
2487 %}
2488
2489 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2490 %{
2491 if ($reg$$reg < 8) {
2492 if ($mem$$base < 8) {
2493 if ($mem$$index < 8) {
2494 emit_opcode(cbuf, Assembler::REX_W);
2495 } else {
2496 emit_opcode(cbuf, Assembler::REX_WX);
2497 }
2498 } else {
2499 if ($mem$$index < 8) {
2500 emit_opcode(cbuf, Assembler::REX_WB);
2501 } else {
2502 emit_opcode(cbuf, Assembler::REX_WXB);
2503 }
2504 }
2505 } else {
2506 if ($mem$$base < 8) {
2507 if ($mem$$index < 8) {
2508 emit_opcode(cbuf, Assembler::REX_WR);
2509 } else {
2510 emit_opcode(cbuf, Assembler::REX_WRX);
2511 }
2512 } else {
2513 if ($mem$$index < 8) {
2514 emit_opcode(cbuf, Assembler::REX_WRB);
2515 } else {
2516 emit_opcode(cbuf, Assembler::REX_WRXB);
2517 }
2518 }
2519 }
2520 %}
2521
2522 enc_class reg_mem(rRegI ereg, memory mem)
2523 %{
2524 // High registers handle in encode_RegMem
2525 int reg = $ereg$$reg;
2526 int base = $mem$$base;
2527 int index = $mem$$index;
2528 int scale = $mem$$scale;
2529 int disp = $mem$$disp;
2530 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2531
2532 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2533 %}
2534
2535 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2536 %{
2537 int rm_byte_opcode = $rm_opcode$$constant;
2538
2539 // High registers handle in encode_RegMem
2540 int base = $mem$$base;
2541 int index = $mem$$index;
2542 int scale = $mem$$scale;
2543 int displace = $mem$$disp;
2544
2545 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2546 // working with static
2547 // globals
2548 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2549 disp_reloc);
2550 %}
2551
2552 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2553 %{
2554 int reg_encoding = $dst$$reg;
2555 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2556 int index = 0x04; // 0x04 indicates no index
2557 int scale = 0x00; // 0x00 indicates no scale
2558 int displace = $src1$$constant; // 0x00 indicates no displacement
2559 relocInfo::relocType disp_reloc = relocInfo::none;
2560 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2561 disp_reloc);
2562 %}
2563
2564 enc_class neg_reg(rRegI dst)
2565 %{
2566 int dstenc = $dst$$reg;
2567 if (dstenc >= 8) {
2568 emit_opcode(cbuf, Assembler::REX_B);
2569 dstenc -= 8;
2570 }
2571 // NEG $dst
2572 emit_opcode(cbuf, 0xF7);
2573 emit_rm(cbuf, 0x3, 0x03, dstenc);
2574 %}
2575
2576 enc_class neg_reg_wide(rRegI dst)
2577 %{
2578 int dstenc = $dst$$reg;
2579 if (dstenc < 8) {
2580 emit_opcode(cbuf, Assembler::REX_W);
2581 } else {
2582 emit_opcode(cbuf, Assembler::REX_WB);
2583 dstenc -= 8;
2584 }
2585 // NEG $dst
2586 emit_opcode(cbuf, 0xF7);
2587 emit_rm(cbuf, 0x3, 0x03, dstenc);
2588 %}
2589
2590 enc_class setLT_reg(rRegI dst)
2591 %{
2592 int dstenc = $dst$$reg;
2593 if (dstenc >= 8) {
2594 emit_opcode(cbuf, Assembler::REX_B);
2595 dstenc -= 8;
2596 } else if (dstenc >= 4) {
2597 emit_opcode(cbuf, Assembler::REX);
2598 }
2599 // SETLT $dst
2600 emit_opcode(cbuf, 0x0F);
2601 emit_opcode(cbuf, 0x9C);
2602 emit_rm(cbuf, 0x3, 0x0, dstenc);
2603 %}
2604
2605 enc_class setNZ_reg(rRegI dst)
2606 %{
2607 int dstenc = $dst$$reg;
2608 if (dstenc >= 8) {
2609 emit_opcode(cbuf, Assembler::REX_B);
2610 dstenc -= 8;
2611 } else if (dstenc >= 4) {
2612 emit_opcode(cbuf, Assembler::REX);
2613 }
2614 // SETNZ $dst
2615 emit_opcode(cbuf, 0x0F);
2616 emit_opcode(cbuf, 0x95);
2617 emit_rm(cbuf, 0x3, 0x0, dstenc);
2618 %}
2619
2620
2621 // Compare the lonogs and set -1, 0, or 1 into dst
2622 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2623 %{
2624 int src1enc = $src1$$reg;
2625 int src2enc = $src2$$reg;
2626 int dstenc = $dst$$reg;
2627
2628 // cmpq $src1, $src2
2629 if (src1enc < 8) {
2630 if (src2enc < 8) {
2631 emit_opcode(cbuf, Assembler::REX_W);
2632 } else {
2633 emit_opcode(cbuf, Assembler::REX_WB);
2634 }
2635 } else {
2636 if (src2enc < 8) {
2637 emit_opcode(cbuf, Assembler::REX_WR);
2638 } else {
2639 emit_opcode(cbuf, Assembler::REX_WRB);
2640 }
2641 }
2642 emit_opcode(cbuf, 0x3B);
2643 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2644
2645 // movl $dst, -1
2646 if (dstenc >= 8) {
2647 emit_opcode(cbuf, Assembler::REX_B);
2648 }
2649 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2650 emit_d32(cbuf, -1);
2651
2652 // jl,s done
2653 emit_opcode(cbuf, 0x7C);
2654 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2655
2656 // setne $dst
2657 if (dstenc >= 4) {
2658 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2659 }
2660 emit_opcode(cbuf, 0x0F);
2661 emit_opcode(cbuf, 0x95);
2662 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2663
2664 // movzbl $dst, $dst
2665 if (dstenc >= 4) {
2666 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2667 }
2668 emit_opcode(cbuf, 0x0F);
2669 emit_opcode(cbuf, 0xB6);
2670 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2671 %}
2672
2673 enc_class Push_ResultXD(regD dst) %{
2674 MacroAssembler _masm(&cbuf);
2675 __ fstp_d(Address(rsp, 0));
2676 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2677 __ addptr(rsp, 8);
2678 %}
2679
2680 enc_class Push_SrcXD(regD src) %{
2681 MacroAssembler _masm(&cbuf);
2682 __ subptr(rsp, 8);
2683 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2684 __ fld_d(Address(rsp, 0));
2685 %}
2686
2687
2688 enc_class enc_rethrow()
2689 %{
2690 cbuf.set_insts_mark();
2691 emit_opcode(cbuf, 0xE9); // jmp entry
2692 emit_d32_reloc(cbuf,
2693 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2694 runtime_call_Relocation::spec(),
2695 RELOC_DISP32);
2696 %}
2697
2698 %}
2699
2700
2701
2702 //----------FRAME--------------------------------------------------------------
2703 // Definition of frame structure and management information.
2704 //
2705 // S T A C K L A Y O U T Allocators stack-slot number
2706 // | (to get allocators register number
2707 // G Owned by | | v add OptoReg::stack0())
2708 // r CALLER | |
2709 // o | +--------+ pad to even-align allocators stack-slot
2710 // w V | pad0 | numbers; owned by CALLER
2711 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2712 // h ^ | in | 5
2713 // | | args | 4 Holes in incoming args owned by SELF
2714 // | | | | 3
2715 // | | +--------+
2716 // V | | old out| Empty on Intel, window on Sparc
2717 // | old |preserve| Must be even aligned.
2718 // | SP-+--------+----> Matcher::_old_SP, even aligned
2719 // | | in | 3 area for Intel ret address
2720 // Owned by |preserve| Empty on Sparc.
2721 // SELF +--------+
2722 // | | pad2 | 2 pad to align old SP
2723 // | +--------+ 1
2724 // | | locks | 0
2725 // | +--------+----> OptoReg::stack0(), even aligned
2726 // | | pad1 | 11 pad to align new SP
2727 // | +--------+
2728 // | | | 10
2729 // | | spills | 9 spills
2730 // V | | 8 (pad0 slot for callee)
2731 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2732 // ^ | out | 7
2733 // | | args | 6 Holes in outgoing args owned by CALLEE
2734 // Owned by +--------+
2735 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2736 // | new |preserve| Must be even-aligned.
2737 // | SP-+--------+----> Matcher::_new_SP, even aligned
2738 // | | |
2739 //
2740 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2741 // known from SELF's arguments and the Java calling convention.
2742 // Region 6-7 is determined per call site.
2743 // Note 2: If the calling convention leaves holes in the incoming argument
2744 // area, those holes are owned by SELF. Holes in the outgoing area
2745 // are owned by the CALLEE. Holes should not be nessecary in the
2746 // incoming area, as the Java calling convention is completely under
2747 // the control of the AD file. Doubles can be sorted and packed to
2748 // avoid holes. Holes in the outgoing arguments may be nessecary for
2749 // varargs C calling conventions.
2750 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2751 // even aligned with pad0 as needed.
2752 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2753 // region 6-11 is even aligned; it may be padded out more so that
2754 // the region from SP to FP meets the minimum stack alignment.
2755 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2756 // alignment. Region 11, pad1, may be dynamically extended so that
2757 // SP meets the minimum alignment.
2758
2759 frame
2760 %{
2761 // What direction does stack grow in (assumed to be same for C & Java)
2762 stack_direction(TOWARDS_LOW);
2763
2764 // These three registers define part of the calling convention
2765 // between compiled code and the interpreter.
2766 inline_cache_reg(RAX); // Inline Cache Register
2767 interpreter_method_oop_reg(RBX); // Method Oop Register when
2768 // calling interpreter
2769
2770 // Optional: name the operand used by cisc-spilling to access
2771 // [stack_pointer + offset]
2772 cisc_spilling_operand_name(indOffset32);
2773
2774 // Number of stack slots consumed by locking an object
2775 sync_stack_slots(2);
2776
2777 // Compiled code's Frame Pointer
2778 frame_pointer(RSP);
2779
2780 // Interpreter stores its frame pointer in a register which is
2781 // stored to the stack by I2CAdaptors.
2782 // I2CAdaptors convert from interpreted java to compiled java.
2783 interpreter_frame_pointer(RBP);
2784
2785 // Stack alignment requirement
2786 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2787
2788 // Number of stack slots between incoming argument block and the start of
2789 // a new frame. The PROLOG must add this many slots to the stack. The
2790 // EPILOG must remove this many slots. amd64 needs two slots for
2791 // return address.
2792 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2793
2794 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2795 // for calls to C. Supports the var-args backing area for register parms.
2796 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2797
2798 // The after-PROLOG location of the return address. Location of
2799 // return address specifies a type (REG or STACK) and a number
2800 // representing the register number (i.e. - use a register name) or
2801 // stack slot.
2802 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2803 // Otherwise, it is above the locks and verification slot and alignment word
2804 return_addr(STACK - 2 +
2805 align_up((Compile::current()->in_preserve_stack_slots() +
2806 Compile::current()->fixed_slots()),
2807 stack_alignment_in_slots()));
2808
2809 // Body of function which returns an integer array locating
2810 // arguments either in registers or in stack slots. Passed an array
2811 // of ideal registers called "sig" and a "length" count. Stack-slot
2812 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2813 // arguments for a CALLEE. Incoming stack arguments are
2814 // automatically biased by the preserve_stack_slots field above.
2815
2816 calling_convention
2817 %{
2818 // No difference between ingoing/outgoing just pass false
2819 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2820 %}
2821
2822 c_calling_convention
2823 %{
2824 // This is obviously always outgoing
2825 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2826 %}
2827
2828 // Location of compiled Java return values. Same as C for now.
2829 return_value
2830 %{
2831 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2832 "only return normal values");
2833
2834 static const int lo[Op_RegL + 1] = {
2835 0,
2836 0,
2837 RAX_num, // Op_RegN
2838 RAX_num, // Op_RegI
2839 RAX_num, // Op_RegP
2840 XMM0_num, // Op_RegF
2841 XMM0_num, // Op_RegD
2842 RAX_num // Op_RegL
2843 };
2844 static const int hi[Op_RegL + 1] = {
2845 0,
2846 0,
2847 OptoReg::Bad, // Op_RegN
2848 OptoReg::Bad, // Op_RegI
2849 RAX_H_num, // Op_RegP
2850 OptoReg::Bad, // Op_RegF
2851 XMM0b_num, // Op_RegD
2852 RAX_H_num // Op_RegL
2853 };
2854 // Excluded flags and vector registers.
2855 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2856 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2857 %}
2858 %}
2859
2860 //----------ATTRIBUTES---------------------------------------------------------
2861 //----------Operand Attributes-------------------------------------------------
2862 op_attrib op_cost(0); // Required cost attribute
2863
2864 //----------Instruction Attributes---------------------------------------------
2865 ins_attrib ins_cost(100); // Required cost attribute
2866 ins_attrib ins_size(8); // Required size attribute (in bits)
2867 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2868 // a non-matching short branch variant
2869 // of some long branch?
2870 ins_attrib ins_alignment(1); // Required alignment attribute (must
2871 // be a power of 2) specifies the
2872 // alignment that some part of the
2873 // instruction (not necessarily the
2874 // start) requires. If > 1, a
2875 // compute_padding() function must be
2876 // provided for the instruction
2877
2878 //----------OPERANDS-----------------------------------------------------------
2879 // Operand definitions must precede instruction definitions for correct parsing
2880 // in the ADLC because operands constitute user defined types which are used in
2881 // instruction definitions.
2882
2883 //----------Simple Operands----------------------------------------------------
2884 // Immediate Operands
2885 // Integer Immediate
2886 operand immI()
2887 %{
2888 match(ConI);
2889
2890 op_cost(10);
2891 format %{ %}
2892 interface(CONST_INTER);
2893 %}
2894
2895 // Constant for test vs zero
2896 operand immI0()
2897 %{
2898 predicate(n->get_int() == 0);
2899 match(ConI);
2900
2901 op_cost(0);
2902 format %{ %}
2903 interface(CONST_INTER);
2904 %}
2905
2906 // Constant for increment
2907 operand immI1()
2908 %{
2909 predicate(n->get_int() == 1);
2910 match(ConI);
2911
2912 op_cost(0);
2913 format %{ %}
2914 interface(CONST_INTER);
2915 %}
2916
2917 // Constant for decrement
2918 operand immI_M1()
2919 %{
2920 predicate(n->get_int() == -1);
2921 match(ConI);
2922
2923 op_cost(0);
2924 format %{ %}
2925 interface(CONST_INTER);
2926 %}
2927
2928 // Valid scale values for addressing modes
2929 operand immI2()
2930 %{
2931 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2932 match(ConI);
2933
2934 format %{ %}
2935 interface(CONST_INTER);
2936 %}
2937
2938 operand immI8()
2939 %{
2940 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2941 match(ConI);
2942
2943 op_cost(5);
2944 format %{ %}
2945 interface(CONST_INTER);
2946 %}
2947
2948 operand immU8()
2949 %{
2950 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2951 match(ConI);
2952
2953 op_cost(5);
2954 format %{ %}
2955 interface(CONST_INTER);
2956 %}
2957
2958 operand immI16()
2959 %{
2960 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2961 match(ConI);
2962
2963 op_cost(10);
2964 format %{ %}
2965 interface(CONST_INTER);
2966 %}
2967
2968 // Int Immediate non-negative
2969 operand immU31()
2970 %{
2971 predicate(n->get_int() >= 0);
2972 match(ConI);
2973
2974 op_cost(0);
2975 format %{ %}
2976 interface(CONST_INTER);
2977 %}
2978
2979 // Constant for long shifts
2980 operand immI_32()
2981 %{
2982 predicate( n->get_int() == 32 );
2983 match(ConI);
2984
2985 op_cost(0);
2986 format %{ %}
2987 interface(CONST_INTER);
2988 %}
2989
2990 // Constant for long shifts
2991 operand immI_64()
2992 %{
2993 predicate( n->get_int() == 64 );
2994 match(ConI);
2995
2996 op_cost(0);
2997 format %{ %}
2998 interface(CONST_INTER);
2999 %}
3000
3001 // Pointer Immediate
3002 operand immP()
3003 %{
3004 match(ConP);
3005
3006 op_cost(10);
3007 format %{ %}
3008 interface(CONST_INTER);
3009 %}
3010
3011 // NULL Pointer Immediate
3012 operand immP0()
3013 %{
3014 predicate(n->get_ptr() == 0);
3015 match(ConP);
3016
3017 op_cost(5);
3018 format %{ %}
3019 interface(CONST_INTER);
3020 %}
3021
3022 // Pointer Immediate
3023 operand immN() %{
3024 match(ConN);
3025
3026 op_cost(10);
3027 format %{ %}
3028 interface(CONST_INTER);
3029 %}
3030
3031 operand immNKlass() %{
3032 match(ConNKlass);
3033
3034 op_cost(10);
3035 format %{ %}
3036 interface(CONST_INTER);
3037 %}
3038
3039 // NULL Pointer Immediate
3040 operand immN0() %{
3041 predicate(n->get_narrowcon() == 0);
3042 match(ConN);
3043
3044 op_cost(5);
3045 format %{ %}
3046 interface(CONST_INTER);
3047 %}
3048
3049 operand immP31()
3050 %{
3051 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3052 && (n->get_ptr() >> 31) == 0);
3053 match(ConP);
3054
3055 op_cost(5);
3056 format %{ %}
3057 interface(CONST_INTER);
3058 %}
3059
3060
3061 // Long Immediate
3062 operand immL()
3063 %{
3064 match(ConL);
3065
3066 op_cost(20);
3067 format %{ %}
3068 interface(CONST_INTER);
3069 %}
3070
3071 // Long Immediate 8-bit
3072 operand immL8()
3073 %{
3074 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3075 match(ConL);
3076
3077 op_cost(5);
3078 format %{ %}
3079 interface(CONST_INTER);
3080 %}
3081
3082 // Long Immediate 32-bit unsigned
3083 operand immUL32()
3084 %{
3085 predicate(n->get_long() == (unsigned int) (n->get_long()));
3086 match(ConL);
3087
3088 op_cost(10);
3089 format %{ %}
3090 interface(CONST_INTER);
3091 %}
3092
3093 // Long Immediate 32-bit signed
3094 operand immL32()
3095 %{
3096 predicate(n->get_long() == (int) (n->get_long()));
3097 match(ConL);
3098
3099 op_cost(15);
3100 format %{ %}
3101 interface(CONST_INTER);
3102 %}
3103
3104 // Long Immediate zero
3105 operand immL0()
3106 %{
3107 predicate(n->get_long() == 0L);
3108 match(ConL);
3109
3110 op_cost(10);
3111 format %{ %}
3112 interface(CONST_INTER);
3113 %}
3114
3115 // Constant for increment
3116 operand immL1()
3117 %{
3118 predicate(n->get_long() == 1);
3119 match(ConL);
3120
3121 format %{ %}
3122 interface(CONST_INTER);
3123 %}
3124
3125 // Constant for decrement
3126 operand immL_M1()
3127 %{
3128 predicate(n->get_long() == -1);
3129 match(ConL);
3130
3131 format %{ %}
3132 interface(CONST_INTER);
3133 %}
3134
3135 // Long Immediate: the value 10
3136 operand immL10()
3137 %{
3138 predicate(n->get_long() == 10);
3139 match(ConL);
3140
3141 format %{ %}
3142 interface(CONST_INTER);
3143 %}
3144
3145 // Long immediate from 0 to 127.
3146 // Used for a shorter form of long mul by 10.
3147 operand immL_127()
3148 %{
3149 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3150 match(ConL);
3151
3152 op_cost(10);
3153 format %{ %}
3154 interface(CONST_INTER);
3155 %}
3156
3157 // Long Immediate: low 32-bit mask
3158 operand immL_32bits()
3159 %{
3160 predicate(n->get_long() == 0xFFFFFFFFL);
3161 match(ConL);
3162 op_cost(20);
3163
3164 format %{ %}
3165 interface(CONST_INTER);
3166 %}
3167
3168 // Float Immediate zero
3169 operand immF0()
3170 %{
3171 predicate(jint_cast(n->getf()) == 0);
3172 match(ConF);
3173
3174 op_cost(5);
3175 format %{ %}
3176 interface(CONST_INTER);
3177 %}
3178
3179 // Float Immediate
3180 operand immF()
3181 %{
3182 match(ConF);
3183
3184 op_cost(15);
3185 format %{ %}
3186 interface(CONST_INTER);
3187 %}
3188
3189 // Double Immediate zero
3190 operand immD0()
3191 %{
3192 predicate(jlong_cast(n->getd()) == 0);
3193 match(ConD);
3194
3195 op_cost(5);
3196 format %{ %}
3197 interface(CONST_INTER);
3198 %}
3199
3200 // Double Immediate
3201 operand immD()
3202 %{
3203 match(ConD);
3204
3205 op_cost(15);
3206 format %{ %}
3207 interface(CONST_INTER);
3208 %}
3209
3210 // Immediates for special shifts (sign extend)
3211
3212 // Constants for increment
3213 operand immI_16()
3214 %{
3215 predicate(n->get_int() == 16);
3216 match(ConI);
3217
3218 format %{ %}
3219 interface(CONST_INTER);
3220 %}
3221
3222 operand immI_24()
3223 %{
3224 predicate(n->get_int() == 24);
3225 match(ConI);
3226
3227 format %{ %}
3228 interface(CONST_INTER);
3229 %}
3230
3231 // Constant for byte-wide masking
3232 operand immI_255()
3233 %{
3234 predicate(n->get_int() == 255);
3235 match(ConI);
3236
3237 format %{ %}
3238 interface(CONST_INTER);
3239 %}
3240
3241 // Constant for short-wide masking
3242 operand immI_65535()
3243 %{
3244 predicate(n->get_int() == 65535);
3245 match(ConI);
3246
3247 format %{ %}
3248 interface(CONST_INTER);
3249 %}
3250
3251 // Constant for byte-wide masking
3252 operand immL_255()
3253 %{
3254 predicate(n->get_long() == 255);
3255 match(ConL);
3256
3257 format %{ %}
3258 interface(CONST_INTER);
3259 %}
3260
3261 // Constant for short-wide masking
3262 operand immL_65535()
3263 %{
3264 predicate(n->get_long() == 65535);
3265 match(ConL);
3266
3267 format %{ %}
3268 interface(CONST_INTER);
3269 %}
3270
3271 // Register Operands
3272 // Integer Register
3273 operand rRegI()
3274 %{
3275 constraint(ALLOC_IN_RC(int_reg));
3276 match(RegI);
3277
3278 match(rax_RegI);
3279 match(rbx_RegI);
3280 match(rcx_RegI);
3281 match(rdx_RegI);
3282 match(rdi_RegI);
3283
3284 format %{ %}
3285 interface(REG_INTER);
3286 %}
3287
3288 // Special Registers
3289 operand rax_RegI()
3290 %{
3291 constraint(ALLOC_IN_RC(int_rax_reg));
3292 match(RegI);
3293 match(rRegI);
3294
3295 format %{ "RAX" %}
3296 interface(REG_INTER);
3297 %}
3298
3299 // Special Registers
3300 operand rbx_RegI()
3301 %{
3302 constraint(ALLOC_IN_RC(int_rbx_reg));
3303 match(RegI);
3304 match(rRegI);
3305
3306 format %{ "RBX" %}
3307 interface(REG_INTER);
3308 %}
3309
3310 operand rcx_RegI()
3311 %{
3312 constraint(ALLOC_IN_RC(int_rcx_reg));
3313 match(RegI);
3314 match(rRegI);
3315
3316 format %{ "RCX" %}
3317 interface(REG_INTER);
3318 %}
3319
3320 operand rdx_RegI()
3321 %{
3322 constraint(ALLOC_IN_RC(int_rdx_reg));
3323 match(RegI);
3324 match(rRegI);
3325
3326 format %{ "RDX" %}
3327 interface(REG_INTER);
3328 %}
3329
3330 operand rdi_RegI()
3331 %{
3332 constraint(ALLOC_IN_RC(int_rdi_reg));
3333 match(RegI);
3334 match(rRegI);
3335
3336 format %{ "RDI" %}
3337 interface(REG_INTER);
3338 %}
3339
3340 operand no_rcx_RegI()
3341 %{
3342 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3343 match(RegI);
3344 match(rax_RegI);
3345 match(rbx_RegI);
3346 match(rdx_RegI);
3347 match(rdi_RegI);
3348
3349 format %{ %}
3350 interface(REG_INTER);
3351 %}
3352
3353 operand no_rax_rdx_RegI()
3354 %{
3355 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3356 match(RegI);
3357 match(rbx_RegI);
3358 match(rcx_RegI);
3359 match(rdi_RegI);
3360
3361 format %{ %}
3362 interface(REG_INTER);
3363 %}
3364
3365 // Pointer Register
3366 operand any_RegP()
3367 %{
3368 constraint(ALLOC_IN_RC(any_reg));
3369 match(RegP);
3370 match(rax_RegP);
3371 match(rbx_RegP);
3372 match(rdi_RegP);
3373 match(rsi_RegP);
3374 match(rbp_RegP);
3375 match(r15_RegP);
3376 match(rRegP);
3377
3378 format %{ %}
3379 interface(REG_INTER);
3380 %}
3381
3382 operand rRegP()
3383 %{
3384 constraint(ALLOC_IN_RC(ptr_reg));
3385 match(RegP);
3386 match(rax_RegP);
3387 match(rbx_RegP);
3388 match(rdi_RegP);
3389 match(rsi_RegP);
3390 match(rbp_RegP); // See Q&A below about
3391 match(r15_RegP); // r15_RegP and rbp_RegP.
3392
3393 format %{ %}
3394 interface(REG_INTER);
3395 %}
3396
3397 operand rRegN() %{
3398 constraint(ALLOC_IN_RC(int_reg));
3399 match(RegN);
3400
3401 format %{ %}
3402 interface(REG_INTER);
3403 %}
3404
3405 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3406 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3407 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3408 // The output of an instruction is controlled by the allocator, which respects
3409 // register class masks, not match rules. Unless an instruction mentions
3410 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3411 // by the allocator as an input.
3412 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3413 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3414 // result, RBP is not included in the output of the instruction either.
3415
3416 operand no_rax_RegP()
3417 %{
3418 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3419 match(RegP);
3420 match(rbx_RegP);
3421 match(rsi_RegP);
3422 match(rdi_RegP);
3423
3424 format %{ %}
3425 interface(REG_INTER);
3426 %}
3427
3428 // This operand is not allowed to use RBP even if
3429 // RBP is not used to hold the frame pointer.
3430 operand no_rbp_RegP()
3431 %{
3432 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3433 match(RegP);
3434 match(rbx_RegP);
3435 match(rsi_RegP);
3436 match(rdi_RegP);
3437
3438 format %{ %}
3439 interface(REG_INTER);
3440 %}
3441
3442 operand no_rax_rbx_RegP()
3443 %{
3444 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3445 match(RegP);
3446 match(rsi_RegP);
3447 match(rdi_RegP);
3448
3449 format %{ %}
3450 interface(REG_INTER);
3451 %}
3452
3453 // Special Registers
3454 // Return a pointer value
3455 operand rax_RegP()
3456 %{
3457 constraint(ALLOC_IN_RC(ptr_rax_reg));
3458 match(RegP);
3459 match(rRegP);
3460
3461 format %{ %}
3462 interface(REG_INTER);
3463 %}
3464
3465 // Special Registers
3466 // Return a compressed pointer value
3467 operand rax_RegN()
3468 %{
3469 constraint(ALLOC_IN_RC(int_rax_reg));
3470 match(RegN);
3471 match(rRegN);
3472
3473 format %{ %}
3474 interface(REG_INTER);
3475 %}
3476
3477 // Used in AtomicAdd
3478 operand rbx_RegP()
3479 %{
3480 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3481 match(RegP);
3482 match(rRegP);
3483
3484 format %{ %}
3485 interface(REG_INTER);
3486 %}
3487
3488 operand rsi_RegP()
3489 %{
3490 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3491 match(RegP);
3492 match(rRegP);
3493
3494 format %{ %}
3495 interface(REG_INTER);
3496 %}
3497
3498 // Used in rep stosq
3499 operand rdi_RegP()
3500 %{
3501 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3502 match(RegP);
3503 match(rRegP);
3504
3505 format %{ %}
3506 interface(REG_INTER);
3507 %}
3508
3509 operand r15_RegP()
3510 %{
3511 constraint(ALLOC_IN_RC(ptr_r15_reg));
3512 match(RegP);
3513 match(rRegP);
3514
3515 format %{ %}
3516 interface(REG_INTER);
3517 %}
3518
3519 operand rRegL()
3520 %{
3521 constraint(ALLOC_IN_RC(long_reg));
3522 match(RegL);
3523 match(rax_RegL);
3524 match(rdx_RegL);
3525
3526 format %{ %}
3527 interface(REG_INTER);
3528 %}
3529
3530 // Special Registers
3531 operand no_rax_rdx_RegL()
3532 %{
3533 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3534 match(RegL);
3535 match(rRegL);
3536
3537 format %{ %}
3538 interface(REG_INTER);
3539 %}
3540
3541 operand no_rax_RegL()
3542 %{
3543 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3544 match(RegL);
3545 match(rRegL);
3546 match(rdx_RegL);
3547
3548 format %{ %}
3549 interface(REG_INTER);
3550 %}
3551
3552 operand no_rcx_RegL()
3553 %{
3554 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3555 match(RegL);
3556 match(rRegL);
3557
3558 format %{ %}
3559 interface(REG_INTER);
3560 %}
3561
3562 operand rax_RegL()
3563 %{
3564 constraint(ALLOC_IN_RC(long_rax_reg));
3565 match(RegL);
3566 match(rRegL);
3567
3568 format %{ "RAX" %}
3569 interface(REG_INTER);
3570 %}
3571
3572 operand rcx_RegL()
3573 %{
3574 constraint(ALLOC_IN_RC(long_rcx_reg));
3575 match(RegL);
3576 match(rRegL);
3577
3578 format %{ %}
3579 interface(REG_INTER);
3580 %}
3581
3582 operand rdx_RegL()
3583 %{
3584 constraint(ALLOC_IN_RC(long_rdx_reg));
3585 match(RegL);
3586 match(rRegL);
3587
3588 format %{ %}
3589 interface(REG_INTER);
3590 %}
3591
3592 // Flags register, used as output of compare instructions
3593 operand rFlagsReg()
3594 %{
3595 constraint(ALLOC_IN_RC(int_flags));
3596 match(RegFlags);
3597
3598 format %{ "RFLAGS" %}
3599 interface(REG_INTER);
3600 %}
3601
3602 // Flags register, used as output of FLOATING POINT compare instructions
3603 operand rFlagsRegU()
3604 %{
3605 constraint(ALLOC_IN_RC(int_flags));
3606 match(RegFlags);
3607
3608 format %{ "RFLAGS_U" %}
3609 interface(REG_INTER);
3610 %}
3611
3612 operand rFlagsRegUCF() %{
3613 constraint(ALLOC_IN_RC(int_flags));
3614 match(RegFlags);
3615 predicate(false);
3616
3617 format %{ "RFLAGS_U_CF" %}
3618 interface(REG_INTER);
3619 %}
3620
3621 // Float register operands
3622 operand regF() %{
3623 constraint(ALLOC_IN_RC(float_reg));
3624 match(RegF);
3625
3626 format %{ %}
3627 interface(REG_INTER);
3628 %}
3629
3630 // Float register operands
3631 operand legRegF() %{
3632 constraint(ALLOC_IN_RC(float_reg_legacy));
3633 match(RegF);
3634
3635 format %{ %}
3636 interface(REG_INTER);
3637 %}
3638
3639 // Float register operands
3640 operand vlRegF() %{
3641 constraint(ALLOC_IN_RC(float_reg_vl));
3642 match(RegF);
3643
3644 format %{ %}
3645 interface(REG_INTER);
3646 %}
3647
3648 // Double register operands
3649 operand regD() %{
3650 constraint(ALLOC_IN_RC(double_reg));
3651 match(RegD);
3652
3653 format %{ %}
3654 interface(REG_INTER);
3655 %}
3656
3657 // Double register operands
3658 operand legRegD() %{
3659 constraint(ALLOC_IN_RC(double_reg_legacy));
3660 match(RegD);
3661
3662 format %{ %}
3663 interface(REG_INTER);
3664 %}
3665
3666 // Double register operands
3667 operand vlRegD() %{
3668 constraint(ALLOC_IN_RC(double_reg_vl));
3669 match(RegD);
3670
3671 format %{ %}
3672 interface(REG_INTER);
3673 %}
3674
3675 // Vectors
3676 operand vecS() %{
3677 constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
3678 match(VecS);
3679
3680 format %{ %}
3681 interface(REG_INTER);
3682 %}
3683
3684 // Vectors
3685 operand legVecS() %{
3686 constraint(ALLOC_IN_RC(vectors_reg_legacy));
3687 match(VecS);
3688
3689 format %{ %}
3690 interface(REG_INTER);
3691 %}
3692
3693 operand vecD() %{
3694 constraint(ALLOC_IN_RC(vectord_reg_vlbwdq));
3695 match(VecD);
3696
3697 format %{ %}
3698 interface(REG_INTER);
3699 %}
3700
3701 operand legVecD() %{
3702 constraint(ALLOC_IN_RC(vectord_reg_legacy));
3703 match(VecD);
3704
3705 format %{ %}
3706 interface(REG_INTER);
3707 %}
3708
3709 operand vecX() %{
3710 constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq));
3711 match(VecX);
3712
3713 format %{ %}
3714 interface(REG_INTER);
3715 %}
3716
3717 operand legVecX() %{
3718 constraint(ALLOC_IN_RC(vectorx_reg_legacy));
3719 match(VecX);
3720
3721 format %{ %}
3722 interface(REG_INTER);
3723 %}
3724
3725 operand vecY() %{
3726 constraint(ALLOC_IN_RC(vectory_reg_vlbwdq));
3727 match(VecY);
3728
3729 format %{ %}
3730 interface(REG_INTER);
3731 %}
3732
3733 operand legVecY() %{
3734 constraint(ALLOC_IN_RC(vectory_reg_legacy));
3735 match(VecY);
3736
3737 format %{ %}
3738 interface(REG_INTER);
3739 %}
3740
3741 //----------Memory Operands----------------------------------------------------
3742 // Direct Memory Operand
3743 // operand direct(immP addr)
3744 // %{
3745 // match(addr);
3746
3747 // format %{ "[$addr]" %}
3748 // interface(MEMORY_INTER) %{
3749 // base(0xFFFFFFFF);
3750 // index(0x4);
3751 // scale(0x0);
3752 // disp($addr);
3753 // %}
3754 // %}
3755
3756 // Indirect Memory Operand
3757 operand indirect(any_RegP reg)
3758 %{
3759 constraint(ALLOC_IN_RC(ptr_reg));
3760 match(reg);
3761
3762 format %{ "[$reg]" %}
3763 interface(MEMORY_INTER) %{
3764 base($reg);
3765 index(0x4);
3766 scale(0x0);
3767 disp(0x0);
3768 %}
3769 %}
3770
3771 // Indirect Memory Plus Short Offset Operand
3772 operand indOffset8(any_RegP reg, immL8 off)
3773 %{
3774 constraint(ALLOC_IN_RC(ptr_reg));
3775 match(AddP reg off);
3776
3777 format %{ "[$reg + $off (8-bit)]" %}
3778 interface(MEMORY_INTER) %{
3779 base($reg);
3780 index(0x4);
3781 scale(0x0);
3782 disp($off);
3783 %}
3784 %}
3785
3786 // Indirect Memory Plus Long Offset Operand
3787 operand indOffset32(any_RegP reg, immL32 off)
3788 %{
3789 constraint(ALLOC_IN_RC(ptr_reg));
3790 match(AddP reg off);
3791
3792 format %{ "[$reg + $off (32-bit)]" %}
3793 interface(MEMORY_INTER) %{
3794 base($reg);
3795 index(0x4);
3796 scale(0x0);
3797 disp($off);
3798 %}
3799 %}
3800
3801 // Indirect Memory Plus Index Register Plus Offset Operand
3802 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3803 %{
3804 constraint(ALLOC_IN_RC(ptr_reg));
3805 match(AddP (AddP reg lreg) off);
3806
3807 op_cost(10);
3808 format %{"[$reg + $off + $lreg]" %}
3809 interface(MEMORY_INTER) %{
3810 base($reg);
3811 index($lreg);
3812 scale(0x0);
3813 disp($off);
3814 %}
3815 %}
3816
3817 // Indirect Memory Plus Index Register Plus Offset Operand
3818 operand indIndex(any_RegP reg, rRegL lreg)
3819 %{
3820 constraint(ALLOC_IN_RC(ptr_reg));
3821 match(AddP reg lreg);
3822
3823 op_cost(10);
3824 format %{"[$reg + $lreg]" %}
3825 interface(MEMORY_INTER) %{
3826 base($reg);
3827 index($lreg);
3828 scale(0x0);
3829 disp(0x0);
3830 %}
3831 %}
3832
3833 // Indirect Memory Times Scale Plus Index Register
3834 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3835 %{
3836 constraint(ALLOC_IN_RC(ptr_reg));
3837 match(AddP reg (LShiftL lreg scale));
3838
3839 op_cost(10);
3840 format %{"[$reg + $lreg << $scale]" %}
3841 interface(MEMORY_INTER) %{
3842 base($reg);
3843 index($lreg);
3844 scale($scale);
3845 disp(0x0);
3846 %}
3847 %}
3848
3849 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3850 %{
3851 constraint(ALLOC_IN_RC(ptr_reg));
3852 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3853 match(AddP reg (LShiftL (ConvI2L idx) scale));
3854
3855 op_cost(10);
3856 format %{"[$reg + pos $idx << $scale]" %}
3857 interface(MEMORY_INTER) %{
3858 base($reg);
3859 index($idx);
3860 scale($scale);
3861 disp(0x0);
3862 %}
3863 %}
3864
3865 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3866 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3867 %{
3868 constraint(ALLOC_IN_RC(ptr_reg));
3869 match(AddP (AddP reg (LShiftL lreg scale)) off);
3870
3871 op_cost(10);
3872 format %{"[$reg + $off + $lreg << $scale]" %}
3873 interface(MEMORY_INTER) %{
3874 base($reg);
3875 index($lreg);
3876 scale($scale);
3877 disp($off);
3878 %}
3879 %}
3880
3881 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3882 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3883 %{
3884 constraint(ALLOC_IN_RC(ptr_reg));
3885 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3886 match(AddP (AddP reg (ConvI2L idx)) off);
3887
3888 op_cost(10);
3889 format %{"[$reg + $off + $idx]" %}
3890 interface(MEMORY_INTER) %{
3891 base($reg);
3892 index($idx);
3893 scale(0x0);
3894 disp($off);
3895 %}
3896 %}
3897
3898 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3899 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3900 %{
3901 constraint(ALLOC_IN_RC(ptr_reg));
3902 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3903 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3904
3905 op_cost(10);
3906 format %{"[$reg + $off + $idx << $scale]" %}
3907 interface(MEMORY_INTER) %{
3908 base($reg);
3909 index($idx);
3910 scale($scale);
3911 disp($off);
3912 %}
3913 %}
3914
3915 // Indirect Narrow Oop Plus Offset Operand
3916 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3917 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3918 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3919 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3920 constraint(ALLOC_IN_RC(ptr_reg));
3921 match(AddP (DecodeN reg) off);
3922
3923 op_cost(10);
3924 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3925 interface(MEMORY_INTER) %{
3926 base(0xc); // R12
3927 index($reg);
3928 scale(0x3);
3929 disp($off);
3930 %}
3931 %}
3932
3933 // Indirect Memory Operand
3934 operand indirectNarrow(rRegN reg)
3935 %{
3936 predicate(Universe::narrow_oop_shift() == 0);
3937 constraint(ALLOC_IN_RC(ptr_reg));
3938 match(DecodeN reg);
3939
3940 format %{ "[$reg]" %}
3941 interface(MEMORY_INTER) %{
3942 base($reg);
3943 index(0x4);
3944 scale(0x0);
3945 disp(0x0);
3946 %}
3947 %}
3948
3949 // Indirect Memory Plus Short Offset Operand
3950 operand indOffset8Narrow(rRegN reg, immL8 off)
3951 %{
3952 predicate(Universe::narrow_oop_shift() == 0);
3953 constraint(ALLOC_IN_RC(ptr_reg));
3954 match(AddP (DecodeN reg) off);
3955
3956 format %{ "[$reg + $off (8-bit)]" %}
3957 interface(MEMORY_INTER) %{
3958 base($reg);
3959 index(0x4);
3960 scale(0x0);
3961 disp($off);
3962 %}
3963 %}
3964
3965 // Indirect Memory Plus Long Offset Operand
3966 operand indOffset32Narrow(rRegN reg, immL32 off)
3967 %{
3968 predicate(Universe::narrow_oop_shift() == 0);
3969 constraint(ALLOC_IN_RC(ptr_reg));
3970 match(AddP (DecodeN reg) off);
3971
3972 format %{ "[$reg + $off (32-bit)]" %}
3973 interface(MEMORY_INTER) %{
3974 base($reg);
3975 index(0x4);
3976 scale(0x0);
3977 disp($off);
3978 %}
3979 %}
3980
3981 // Indirect Memory Plus Index Register Plus Offset Operand
3982 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3983 %{
3984 predicate(Universe::narrow_oop_shift() == 0);
3985 constraint(ALLOC_IN_RC(ptr_reg));
3986 match(AddP (AddP (DecodeN reg) lreg) off);
3987
3988 op_cost(10);
3989 format %{"[$reg + $off + $lreg]" %}
3990 interface(MEMORY_INTER) %{
3991 base($reg);
3992 index($lreg);
3993 scale(0x0);
3994 disp($off);
3995 %}
3996 %}
3997
3998 // Indirect Memory Plus Index Register Plus Offset Operand
3999 operand indIndexNarrow(rRegN reg, rRegL lreg)
4000 %{
4001 predicate(Universe::narrow_oop_shift() == 0);
4002 constraint(ALLOC_IN_RC(ptr_reg));
4003 match(AddP (DecodeN reg) lreg);
4004
4005 op_cost(10);
4006 format %{"[$reg + $lreg]" %}
4007 interface(MEMORY_INTER) %{
4008 base($reg);
4009 index($lreg);
4010 scale(0x0);
4011 disp(0x0);
4012 %}
4013 %}
4014
4015 // Indirect Memory Times Scale Plus Index Register
4016 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4017 %{
4018 predicate(Universe::narrow_oop_shift() == 0);
4019 constraint(ALLOC_IN_RC(ptr_reg));
4020 match(AddP (DecodeN reg) (LShiftL lreg scale));
4021
4022 op_cost(10);
4023 format %{"[$reg + $lreg << $scale]" %}
4024 interface(MEMORY_INTER) %{
4025 base($reg);
4026 index($lreg);
4027 scale($scale);
4028 disp(0x0);
4029 %}
4030 %}
4031
4032 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4033 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4034 %{
4035 predicate(Universe::narrow_oop_shift() == 0);
4036 constraint(ALLOC_IN_RC(ptr_reg));
4037 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4038
4039 op_cost(10);
4040 format %{"[$reg + $off + $lreg << $scale]" %}
4041 interface(MEMORY_INTER) %{
4042 base($reg);
4043 index($lreg);
4044 scale($scale);
4045 disp($off);
4046 %}
4047 %}
4048
4049 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4050 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4051 %{
4052 constraint(ALLOC_IN_RC(ptr_reg));
4053 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4054 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4055
4056 op_cost(10);
4057 format %{"[$reg + $off + $idx]" %}
4058 interface(MEMORY_INTER) %{
4059 base($reg);
4060 index($idx);
4061 scale(0x0);
4062 disp($off);
4063 %}
4064 %}
4065
4066 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4067 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4068 %{
4069 constraint(ALLOC_IN_RC(ptr_reg));
4070 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4071 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4072
4073 op_cost(10);
4074 format %{"[$reg + $off + $idx << $scale]" %}
4075 interface(MEMORY_INTER) %{
4076 base($reg);
4077 index($idx);
4078 scale($scale);
4079 disp($off);
4080 %}
4081 %}
4082
4083 //----------Special Memory Operands--------------------------------------------
4084 // Stack Slot Operand - This operand is used for loading and storing temporary
4085 // values on the stack where a match requires a value to
4086 // flow through memory.
4087 operand stackSlotP(sRegP reg)
4088 %{
4089 constraint(ALLOC_IN_RC(stack_slots));
4090 // No match rule because this operand is only generated in matching
4091
4092 format %{ "[$reg]" %}
4093 interface(MEMORY_INTER) %{
4094 base(0x4); // RSP
4095 index(0x4); // No Index
4096 scale(0x0); // No Scale
4097 disp($reg); // Stack Offset
4098 %}
4099 %}
4100
4101 operand stackSlotI(sRegI reg)
4102 %{
4103 constraint(ALLOC_IN_RC(stack_slots));
4104 // No match rule because this operand is only generated in matching
4105
4106 format %{ "[$reg]" %}
4107 interface(MEMORY_INTER) %{
4108 base(0x4); // RSP
4109 index(0x4); // No Index
4110 scale(0x0); // No Scale
4111 disp($reg); // Stack Offset
4112 %}
4113 %}
4114
4115 operand stackSlotF(sRegF reg)
4116 %{
4117 constraint(ALLOC_IN_RC(stack_slots));
4118 // No match rule because this operand is only generated in matching
4119
4120 format %{ "[$reg]" %}
4121 interface(MEMORY_INTER) %{
4122 base(0x4); // RSP
4123 index(0x4); // No Index
4124 scale(0x0); // No Scale
4125 disp($reg); // Stack Offset
4126 %}
4127 %}
4128
4129 operand stackSlotD(sRegD reg)
4130 %{
4131 constraint(ALLOC_IN_RC(stack_slots));
4132 // No match rule because this operand is only generated in matching
4133
4134 format %{ "[$reg]" %}
4135 interface(MEMORY_INTER) %{
4136 base(0x4); // RSP
4137 index(0x4); // No Index
4138 scale(0x0); // No Scale
4139 disp($reg); // Stack Offset
4140 %}
4141 %}
4142 operand stackSlotL(sRegL reg)
4143 %{
4144 constraint(ALLOC_IN_RC(stack_slots));
4145 // No match rule because this operand is only generated in matching
4146
4147 format %{ "[$reg]" %}
4148 interface(MEMORY_INTER) %{
4149 base(0x4); // RSP
4150 index(0x4); // No Index
4151 scale(0x0); // No Scale
4152 disp($reg); // Stack Offset
4153 %}
4154 %}
4155
4156 //----------Conditional Branch Operands----------------------------------------
4157 // Comparison Op - This is the operation of the comparison, and is limited to
4158 // the following set of codes:
4159 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4160 //
4161 // Other attributes of the comparison, such as unsignedness, are specified
4162 // by the comparison instruction that sets a condition code flags register.
4163 // That result is represented by a flags operand whose subtype is appropriate
4164 // to the unsignedness (etc.) of the comparison.
4165 //
4166 // Later, the instruction which matches both the Comparison Op (a Bool) and
4167 // the flags (produced by the Cmp) specifies the coding of the comparison op
4168 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4169
4170 // Comparision Code
4171 operand cmpOp()
4172 %{
4173 match(Bool);
4174
4175 format %{ "" %}
4176 interface(COND_INTER) %{
4177 equal(0x4, "e");
4178 not_equal(0x5, "ne");
4179 less(0xC, "l");
4180 greater_equal(0xD, "ge");
4181 less_equal(0xE, "le");
4182 greater(0xF, "g");
4183 overflow(0x0, "o");
4184 no_overflow(0x1, "no");
4185 %}
4186 %}
4187
4188 // Comparison Code, unsigned compare. Used by FP also, with
4189 // C2 (unordered) turned into GT or LT already. The other bits
4190 // C0 and C3 are turned into Carry & Zero flags.
4191 operand cmpOpU()
4192 %{
4193 match(Bool);
4194
4195 format %{ "" %}
4196 interface(COND_INTER) %{
4197 equal(0x4, "e");
4198 not_equal(0x5, "ne");
4199 less(0x2, "b");
4200 greater_equal(0x3, "nb");
4201 less_equal(0x6, "be");
4202 greater(0x7, "nbe");
4203 overflow(0x0, "o");
4204 no_overflow(0x1, "no");
4205 %}
4206 %}
4207
4208
4209 // Floating comparisons that don't require any fixup for the unordered case
4210 operand cmpOpUCF() %{
4211 match(Bool);
4212 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4213 n->as_Bool()->_test._test == BoolTest::ge ||
4214 n->as_Bool()->_test._test == BoolTest::le ||
4215 n->as_Bool()->_test._test == BoolTest::gt);
4216 format %{ "" %}
4217 interface(COND_INTER) %{
4218 equal(0x4, "e");
4219 not_equal(0x5, "ne");
4220 less(0x2, "b");
4221 greater_equal(0x3, "nb");
4222 less_equal(0x6, "be");
4223 greater(0x7, "nbe");
4224 overflow(0x0, "o");
4225 no_overflow(0x1, "no");
4226 %}
4227 %}
4228
4229
4230 // Floating comparisons that can be fixed up with extra conditional jumps
4231 operand cmpOpUCF2() %{
4232 match(Bool);
4233 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4234 n->as_Bool()->_test._test == BoolTest::eq);
4235 format %{ "" %}
4236 interface(COND_INTER) %{
4237 equal(0x4, "e");
4238 not_equal(0x5, "ne");
4239 less(0x2, "b");
4240 greater_equal(0x3, "nb");
4241 less_equal(0x6, "be");
4242 greater(0x7, "nbe");
4243 overflow(0x0, "o");
4244 no_overflow(0x1, "no");
4245 %}
4246 %}
4247
4248 // Operands for bound floating pointer register arguments
4249 operand rxmm0() %{
4250 constraint(ALLOC_IN_RC(xmm0_reg));
4251 match(VecX);
4252 format%{%}
4253 interface(REG_INTER);
4254 %}
4255 operand rxmm1() %{
4256 constraint(ALLOC_IN_RC(xmm1_reg));
4257 match(VecX);
4258 format%{%}
4259 interface(REG_INTER);
4260 %}
4261 operand rxmm2() %{
4262 constraint(ALLOC_IN_RC(xmm2_reg));
4263 match(VecX);
4264 format%{%}
4265 interface(REG_INTER);
4266 %}
4267 operand rxmm3() %{
4268 constraint(ALLOC_IN_RC(xmm3_reg));
4269 match(VecX);
4270 format%{%}
4271 interface(REG_INTER);
4272 %}
4273 operand rxmm4() %{
4274 constraint(ALLOC_IN_RC(xmm4_reg));
4275 match(VecX);
4276 format%{%}
4277 interface(REG_INTER);
4278 %}
4279 operand rxmm5() %{
4280 constraint(ALLOC_IN_RC(xmm5_reg));
4281 match(VecX);
4282 format%{%}
4283 interface(REG_INTER);
4284 %}
4285 operand rxmm6() %{
4286 constraint(ALLOC_IN_RC(xmm6_reg));
4287 match(VecX);
4288 format%{%}
4289 interface(REG_INTER);
4290 %}
4291 operand rxmm7() %{
4292 constraint(ALLOC_IN_RC(xmm7_reg));
4293 match(VecX);
4294 format%{%}
4295 interface(REG_INTER);
4296 %}
4297 operand rxmm8() %{
4298 constraint(ALLOC_IN_RC(xmm8_reg));
4299 match(VecX);
4300 format%{%}
4301 interface(REG_INTER);
4302 %}
4303 operand rxmm9() %{
4304 constraint(ALLOC_IN_RC(xmm9_reg));
4305 match(VecX);
4306 format%{%}
4307 interface(REG_INTER);
4308 %}
4309 operand rxmm10() %{
4310 constraint(ALLOC_IN_RC(xmm10_reg));
4311 match(VecX);
4312 format%{%}
4313 interface(REG_INTER);
4314 %}
4315 operand rxmm11() %{
4316 constraint(ALLOC_IN_RC(xmm11_reg));
4317 match(VecX);
4318 format%{%}
4319 interface(REG_INTER);
4320 %}
4321 operand rxmm12() %{
4322 constraint(ALLOC_IN_RC(xmm12_reg));
4323 match(VecX);
4324 format%{%}
4325 interface(REG_INTER);
4326 %}
4327 operand rxmm13() %{
4328 constraint(ALLOC_IN_RC(xmm13_reg));
4329 match(VecX);
4330 format%{%}
4331 interface(REG_INTER);
4332 %}
4333 operand rxmm14() %{
4334 constraint(ALLOC_IN_RC(xmm14_reg));
4335 match(VecX);
4336 format%{%}
4337 interface(REG_INTER);
4338 %}
4339 operand rxmm15() %{
4340 constraint(ALLOC_IN_RC(xmm15_reg));
4341 match(VecX);
4342 format%{%}
4343 interface(REG_INTER);
4344 %}
4345 operand rxmm16() %{
4346 constraint(ALLOC_IN_RC(xmm16_reg));
4347 match(VecX);
4348 format%{%}
4349 interface(REG_INTER);
4350 %}
4351 operand rxmm17() %{
4352 constraint(ALLOC_IN_RC(xmm17_reg));
4353 match(VecX);
4354 format%{%}
4355 interface(REG_INTER);
4356 %}
4357 operand rxmm18() %{
4358 constraint(ALLOC_IN_RC(xmm18_reg));
4359 match(VecX);
4360 format%{%}
4361 interface(REG_INTER);
4362 %}
4363 operand rxmm19() %{
4364 constraint(ALLOC_IN_RC(xmm19_reg));
4365 match(VecX);
4366 format%{%}
4367 interface(REG_INTER);
4368 %}
4369 operand rxmm20() %{
4370 constraint(ALLOC_IN_RC(xmm20_reg));
4371 match(VecX);
4372 format%{%}
4373 interface(REG_INTER);
4374 %}
4375 operand rxmm21() %{
4376 constraint(ALLOC_IN_RC(xmm21_reg));
4377 match(VecX);
4378 format%{%}
4379 interface(REG_INTER);
4380 %}
4381 operand rxmm22() %{
4382 constraint(ALLOC_IN_RC(xmm22_reg));
4383 match(VecX);
4384 format%{%}
4385 interface(REG_INTER);
4386 %}
4387 operand rxmm23() %{
4388 constraint(ALLOC_IN_RC(xmm23_reg));
4389 match(VecX);
4390 format%{%}
4391 interface(REG_INTER);
4392 %}
4393 operand rxmm24() %{
4394 constraint(ALLOC_IN_RC(xmm24_reg));
4395 match(VecX);
4396 format%{%}
4397 interface(REG_INTER);
4398 %}
4399 operand rxmm25() %{
4400 constraint(ALLOC_IN_RC(xmm25_reg));
4401 match(VecX);
4402 format%{%}
4403 interface(REG_INTER);
4404 %}
4405 operand rxmm26() %{
4406 constraint(ALLOC_IN_RC(xmm26_reg));
4407 match(VecX);
4408 format%{%}
4409 interface(REG_INTER);
4410 %}
4411 operand rxmm27() %{
4412 constraint(ALLOC_IN_RC(xmm27_reg));
4413 match(VecX);
4414 format%{%}
4415 interface(REG_INTER);
4416 %}
4417 operand rxmm28() %{
4418 constraint(ALLOC_IN_RC(xmm28_reg));
4419 match(VecX);
4420 format%{%}
4421 interface(REG_INTER);
4422 %}
4423 operand rxmm29() %{
4424 constraint(ALLOC_IN_RC(xmm29_reg));
4425 match(VecX);
4426 format%{%}
4427 interface(REG_INTER);
4428 %}
4429 operand rxmm30() %{
4430 constraint(ALLOC_IN_RC(xmm30_reg));
4431 match(VecX);
4432 format%{%}
4433 interface(REG_INTER);
4434 %}
4435 operand rxmm31() %{
4436 constraint(ALLOC_IN_RC(xmm31_reg));
4437 match(VecX);
4438 format%{%}
4439 interface(REG_INTER);
4440 %}
4441
4442 //----------OPERAND CLASSES----------------------------------------------------
4443 // Operand Classes are groups of operands that are used as to simplify
4444 // instruction definitions by not requiring the AD writer to specify separate
4445 // instructions for every form of operand when the instruction accepts
4446 // multiple operand types with the same basic encoding and format. The classic
4447 // case of this is memory operands.
4448
4449 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4450 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4451 indCompressedOopOffset,
4452 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4453 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4454 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4455
4456 //----------PIPELINE-----------------------------------------------------------
4457 // Rules which define the behavior of the target architectures pipeline.
4458 pipeline %{
4459
4460 //----------ATTRIBUTES---------------------------------------------------------
4461 attributes %{
4462 variable_size_instructions; // Fixed size instructions
4463 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4464 instruction_unit_size = 1; // An instruction is 1 bytes long
4465 instruction_fetch_unit_size = 16; // The processor fetches one line
4466 instruction_fetch_units = 1; // of 16 bytes
4467
4468 // List of nop instructions
4469 nops( MachNop );
4470 %}
4471
4472 //----------RESOURCES----------------------------------------------------------
4473 // Resources are the functional units available to the machine
4474
4475 // Generic P2/P3 pipeline
4476 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4477 // 3 instructions decoded per cycle.
4478 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4479 // 3 ALU op, only ALU0 handles mul instructions.
4480 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4481 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4482 BR, FPU,
4483 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4484
4485 //----------PIPELINE DESCRIPTION-----------------------------------------------
4486 // Pipeline Description specifies the stages in the machine's pipeline
4487
4488 // Generic P2/P3 pipeline
4489 pipe_desc(S0, S1, S2, S3, S4, S5);
4490
4491 //----------PIPELINE CLASSES---------------------------------------------------
4492 // Pipeline Classes describe the stages in which input and output are
4493 // referenced by the hardware pipeline.
4494
4495 // Naming convention: ialu or fpu
4496 // Then: _reg
4497 // Then: _reg if there is a 2nd register
4498 // Then: _long if it's a pair of instructions implementing a long
4499 // Then: _fat if it requires the big decoder
4500 // Or: _mem if it requires the big decoder and a memory unit.
4501
4502 // Integer ALU reg operation
4503 pipe_class ialu_reg(rRegI dst)
4504 %{
4505 single_instruction;
4506 dst : S4(write);
4507 dst : S3(read);
4508 DECODE : S0; // any decoder
4509 ALU : S3; // any alu
4510 %}
4511
4512 // Long ALU reg operation
4513 pipe_class ialu_reg_long(rRegL dst)
4514 %{
4515 instruction_count(2);
4516 dst : S4(write);
4517 dst : S3(read);
4518 DECODE : S0(2); // any 2 decoders
4519 ALU : S3(2); // both alus
4520 %}
4521
4522 // Integer ALU reg operation using big decoder
4523 pipe_class ialu_reg_fat(rRegI dst)
4524 %{
4525 single_instruction;
4526 dst : S4(write);
4527 dst : S3(read);
4528 D0 : S0; // big decoder only
4529 ALU : S3; // any alu
4530 %}
4531
4532 // Long ALU reg operation using big decoder
4533 pipe_class ialu_reg_long_fat(rRegL dst)
4534 %{
4535 instruction_count(2);
4536 dst : S4(write);
4537 dst : S3(read);
4538 D0 : S0(2); // big decoder only; twice
4539 ALU : S3(2); // any 2 alus
4540 %}
4541
4542 // Integer ALU reg-reg operation
4543 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4544 %{
4545 single_instruction;
4546 dst : S4(write);
4547 src : S3(read);
4548 DECODE : S0; // any decoder
4549 ALU : S3; // any alu
4550 %}
4551
4552 // Long ALU reg-reg operation
4553 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4554 %{
4555 instruction_count(2);
4556 dst : S4(write);
4557 src : S3(read);
4558 DECODE : S0(2); // any 2 decoders
4559 ALU : S3(2); // both alus
4560 %}
4561
4562 // Integer ALU reg-reg operation
4563 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4564 %{
4565 single_instruction;
4566 dst : S4(write);
4567 src : S3(read);
4568 D0 : S0; // big decoder only
4569 ALU : S3; // any alu
4570 %}
4571
4572 // Long ALU reg-reg operation
4573 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4574 %{
4575 instruction_count(2);
4576 dst : S4(write);
4577 src : S3(read);
4578 D0 : S0(2); // big decoder only; twice
4579 ALU : S3(2); // both alus
4580 %}
4581
4582 // Integer ALU reg-mem operation
4583 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4584 %{
4585 single_instruction;
4586 dst : S5(write);
4587 mem : S3(read);
4588 D0 : S0; // big decoder only
4589 ALU : S4; // any alu
4590 MEM : S3; // any mem
4591 %}
4592
4593 // Integer mem operation (prefetch)
4594 pipe_class ialu_mem(memory mem)
4595 %{
4596 single_instruction;
4597 mem : S3(read);
4598 D0 : S0; // big decoder only
4599 MEM : S3; // any mem
4600 %}
4601
4602 // Integer Store to Memory
4603 pipe_class ialu_mem_reg(memory mem, rRegI src)
4604 %{
4605 single_instruction;
4606 mem : S3(read);
4607 src : S5(read);
4608 D0 : S0; // big decoder only
4609 ALU : S4; // any alu
4610 MEM : S3;
4611 %}
4612
4613 // // Long Store to Memory
4614 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4615 // %{
4616 // instruction_count(2);
4617 // mem : S3(read);
4618 // src : S5(read);
4619 // D0 : S0(2); // big decoder only; twice
4620 // ALU : S4(2); // any 2 alus
4621 // MEM : S3(2); // Both mems
4622 // %}
4623
4624 // Integer Store to Memory
4625 pipe_class ialu_mem_imm(memory mem)
4626 %{
4627 single_instruction;
4628 mem : S3(read);
4629 D0 : S0; // big decoder only
4630 ALU : S4; // any alu
4631 MEM : S3;
4632 %}
4633
4634 // Integer ALU0 reg-reg operation
4635 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4636 %{
4637 single_instruction;
4638 dst : S4(write);
4639 src : S3(read);
4640 D0 : S0; // Big decoder only
4641 ALU0 : S3; // only alu0
4642 %}
4643
4644 // Integer ALU0 reg-mem operation
4645 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4646 %{
4647 single_instruction;
4648 dst : S5(write);
4649 mem : S3(read);
4650 D0 : S0; // big decoder only
4651 ALU0 : S4; // ALU0 only
4652 MEM : S3; // any mem
4653 %}
4654
4655 // Integer ALU reg-reg operation
4656 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4657 %{
4658 single_instruction;
4659 cr : S4(write);
4660 src1 : S3(read);
4661 src2 : S3(read);
4662 DECODE : S0; // any decoder
4663 ALU : S3; // any alu
4664 %}
4665
4666 // Integer ALU reg-imm operation
4667 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4668 %{
4669 single_instruction;
4670 cr : S4(write);
4671 src1 : S3(read);
4672 DECODE : S0; // any decoder
4673 ALU : S3; // any alu
4674 %}
4675
4676 // Integer ALU reg-mem operation
4677 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4678 %{
4679 single_instruction;
4680 cr : S4(write);
4681 src1 : S3(read);
4682 src2 : S3(read);
4683 D0 : S0; // big decoder only
4684 ALU : S4; // any alu
4685 MEM : S3;
4686 %}
4687
4688 // Conditional move reg-reg
4689 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4690 %{
4691 instruction_count(4);
4692 y : S4(read);
4693 q : S3(read);
4694 p : S3(read);
4695 DECODE : S0(4); // any decoder
4696 %}
4697
4698 // Conditional move reg-reg
4699 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4700 %{
4701 single_instruction;
4702 dst : S4(write);
4703 src : S3(read);
4704 cr : S3(read);
4705 DECODE : S0; // any decoder
4706 %}
4707
4708 // Conditional move reg-mem
4709 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4710 %{
4711 single_instruction;
4712 dst : S4(write);
4713 src : S3(read);
4714 cr : S3(read);
4715 DECODE : S0; // any decoder
4716 MEM : S3;
4717 %}
4718
4719 // Conditional move reg-reg long
4720 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4721 %{
4722 single_instruction;
4723 dst : S4(write);
4724 src : S3(read);
4725 cr : S3(read);
4726 DECODE : S0(2); // any 2 decoders
4727 %}
4728
4729 // XXX
4730 // // Conditional move double reg-reg
4731 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4732 // %{
4733 // single_instruction;
4734 // dst : S4(write);
4735 // src : S3(read);
4736 // cr : S3(read);
4737 // DECODE : S0; // any decoder
4738 // %}
4739
4740 // Float reg-reg operation
4741 pipe_class fpu_reg(regD dst)
4742 %{
4743 instruction_count(2);
4744 dst : S3(read);
4745 DECODE : S0(2); // any 2 decoders
4746 FPU : S3;
4747 %}
4748
4749 // Float reg-reg operation
4750 pipe_class fpu_reg_reg(regD dst, regD src)
4751 %{
4752 instruction_count(2);
4753 dst : S4(write);
4754 src : S3(read);
4755 DECODE : S0(2); // any 2 decoders
4756 FPU : S3;
4757 %}
4758
4759 // Float reg-reg operation
4760 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4761 %{
4762 instruction_count(3);
4763 dst : S4(write);
4764 src1 : S3(read);
4765 src2 : S3(read);
4766 DECODE : S0(3); // any 3 decoders
4767 FPU : S3(2);
4768 %}
4769
4770 // Float reg-reg operation
4771 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4772 %{
4773 instruction_count(4);
4774 dst : S4(write);
4775 src1 : S3(read);
4776 src2 : S3(read);
4777 src3 : S3(read);
4778 DECODE : S0(4); // any 3 decoders
4779 FPU : S3(2);
4780 %}
4781
4782 // Float reg-reg operation
4783 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4784 %{
4785 instruction_count(4);
4786 dst : S4(write);
4787 src1 : S3(read);
4788 src2 : S3(read);
4789 src3 : S3(read);
4790 DECODE : S1(3); // any 3 decoders
4791 D0 : S0; // Big decoder only
4792 FPU : S3(2);
4793 MEM : S3;
4794 %}
4795
4796 // Float reg-mem operation
4797 pipe_class fpu_reg_mem(regD dst, memory mem)
4798 %{
4799 instruction_count(2);
4800 dst : S5(write);
4801 mem : S3(read);
4802 D0 : S0; // big decoder only
4803 DECODE : S1; // any decoder for FPU POP
4804 FPU : S4;
4805 MEM : S3; // any mem
4806 %}
4807
4808 // Float reg-mem operation
4809 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4810 %{
4811 instruction_count(3);
4812 dst : S5(write);
4813 src1 : S3(read);
4814 mem : S3(read);
4815 D0 : S0; // big decoder only
4816 DECODE : S1(2); // any decoder for FPU POP
4817 FPU : S4;
4818 MEM : S3; // any mem
4819 %}
4820
4821 // Float mem-reg operation
4822 pipe_class fpu_mem_reg(memory mem, regD src)
4823 %{
4824 instruction_count(2);
4825 src : S5(read);
4826 mem : S3(read);
4827 DECODE : S0; // any decoder for FPU PUSH
4828 D0 : S1; // big decoder only
4829 FPU : S4;
4830 MEM : S3; // any mem
4831 %}
4832
4833 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4834 %{
4835 instruction_count(3);
4836 src1 : S3(read);
4837 src2 : S3(read);
4838 mem : S3(read);
4839 DECODE : S0(2); // any decoder for FPU PUSH
4840 D0 : S1; // big decoder only
4841 FPU : S4;
4842 MEM : S3; // any mem
4843 %}
4844
4845 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4846 %{
4847 instruction_count(3);
4848 src1 : S3(read);
4849 src2 : S3(read);
4850 mem : S4(read);
4851 DECODE : S0; // any decoder for FPU PUSH
4852 D0 : S0(2); // big decoder only
4853 FPU : S4;
4854 MEM : S3(2); // any mem
4855 %}
4856
4857 pipe_class fpu_mem_mem(memory dst, memory src1)
4858 %{
4859 instruction_count(2);
4860 src1 : S3(read);
4861 dst : S4(read);
4862 D0 : S0(2); // big decoder only
4863 MEM : S3(2); // any mem
4864 %}
4865
4866 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4867 %{
4868 instruction_count(3);
4869 src1 : S3(read);
4870 src2 : S3(read);
4871 dst : S4(read);
4872 D0 : S0(3); // big decoder only
4873 FPU : S4;
4874 MEM : S3(3); // any mem
4875 %}
4876
4877 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4878 %{
4879 instruction_count(3);
4880 src1 : S4(read);
4881 mem : S4(read);
4882 DECODE : S0; // any decoder for FPU PUSH
4883 D0 : S0(2); // big decoder only
4884 FPU : S4;
4885 MEM : S3(2); // any mem
4886 %}
4887
4888 // Float load constant
4889 pipe_class fpu_reg_con(regD dst)
4890 %{
4891 instruction_count(2);
4892 dst : S5(write);
4893 D0 : S0; // big decoder only for the load
4894 DECODE : S1; // any decoder for FPU POP
4895 FPU : S4;
4896 MEM : S3; // any mem
4897 %}
4898
4899 // Float load constant
4900 pipe_class fpu_reg_reg_con(regD dst, regD src)
4901 %{
4902 instruction_count(3);
4903 dst : S5(write);
4904 src : S3(read);
4905 D0 : S0; // big decoder only for the load
4906 DECODE : S1(2); // any decoder for FPU POP
4907 FPU : S4;
4908 MEM : S3; // any mem
4909 %}
4910
4911 // UnConditional branch
4912 pipe_class pipe_jmp(label labl)
4913 %{
4914 single_instruction;
4915 BR : S3;
4916 %}
4917
4918 // Conditional branch
4919 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4920 %{
4921 single_instruction;
4922 cr : S1(read);
4923 BR : S3;
4924 %}
4925
4926 // Allocation idiom
4927 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4928 %{
4929 instruction_count(1); force_serialization;
4930 fixed_latency(6);
4931 heap_ptr : S3(read);
4932 DECODE : S0(3);
4933 D0 : S2;
4934 MEM : S3;
4935 ALU : S3(2);
4936 dst : S5(write);
4937 BR : S5;
4938 %}
4939
4940 // Generic big/slow expanded idiom
4941 pipe_class pipe_slow()
4942 %{
4943 instruction_count(10); multiple_bundles; force_serialization;
4944 fixed_latency(100);
4945 D0 : S0(2);
4946 MEM : S3(2);
4947 %}
4948
4949 // The real do-nothing guy
4950 pipe_class empty()
4951 %{
4952 instruction_count(0);
4953 %}
4954
4955 // Define the class for the Nop node
4956 define
4957 %{
4958 MachNop = empty;
4959 %}
4960
4961 %}
4962
4963 //----------INSTRUCTIONS-------------------------------------------------------
4964 //
4965 // match -- States which machine-independent subtree may be replaced
4966 // by this instruction.
4967 // ins_cost -- The estimated cost of this instruction is used by instruction
4968 // selection to identify a minimum cost tree of machine
4969 // instructions that matches a tree of machine-independent
4970 // instructions.
4971 // format -- A string providing the disassembly for this instruction.
4972 // The value of an instruction's operand may be inserted
4973 // by referring to it with a '$' prefix.
4974 // opcode -- Three instruction opcodes may be provided. These are referred
4975 // to within an encode class as $primary, $secondary, and $tertiary
4976 // rrspectively. The primary opcode is commonly used to
4977 // indicate the type of machine instruction, while secondary
4978 // and tertiary are often used for prefix options or addressing
4979 // modes.
4980 // ins_encode -- A list of encode classes with parameters. The encode class
4981 // name must have been defined in an 'enc_class' specification
4982 // in the encode section of the architecture description.
4983
4984
4985 //----------Load/Store/Move Instructions---------------------------------------
4986 //----------Load Instructions--------------------------------------------------
4987
4988 // Load Byte (8 bit signed)
4989 instruct loadB(rRegI dst, memory mem)
4990 %{
4991 match(Set dst (LoadB mem));
4992
4993 ins_cost(125);
4994 format %{ "movsbl $dst, $mem\t# byte" %}
4995
4996 ins_encode %{
4997 __ movsbl($dst$$Register, $mem$$Address);
4998 %}
4999
5000 ins_pipe(ialu_reg_mem);
5001 %}
5002
5003 // Load Byte (8 bit signed) into Long Register
5004 instruct loadB2L(rRegL dst, memory mem)
5005 %{
5006 match(Set dst (ConvI2L (LoadB mem)));
5007
5008 ins_cost(125);
5009 format %{ "movsbq $dst, $mem\t# byte -> long" %}
5010
5011 ins_encode %{
5012 __ movsbq($dst$$Register, $mem$$Address);
5013 %}
5014
5015 ins_pipe(ialu_reg_mem);
5016 %}
5017
5018 // Load Unsigned Byte (8 bit UNsigned)
5019 instruct loadUB(rRegI dst, memory mem)
5020 %{
5021 match(Set dst (LoadUB mem));
5022
5023 ins_cost(125);
5024 format %{ "movzbl $dst, $mem\t# ubyte" %}
5025
5026 ins_encode %{
5027 __ movzbl($dst$$Register, $mem$$Address);
5028 %}
5029
5030 ins_pipe(ialu_reg_mem);
5031 %}
5032
5033 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5034 instruct loadUB2L(rRegL dst, memory mem)
5035 %{
5036 match(Set dst (ConvI2L (LoadUB mem)));
5037
5038 ins_cost(125);
5039 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
5040
5041 ins_encode %{
5042 __ movzbq($dst$$Register, $mem$$Address);
5043 %}
5044
5045 ins_pipe(ialu_reg_mem);
5046 %}
5047
5048 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5049 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5050 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5051 effect(KILL cr);
5052
5053 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
5054 "andl $dst, right_n_bits($mask, 8)" %}
5055 ins_encode %{
5056 Register Rdst = $dst$$Register;
5057 __ movzbq(Rdst, $mem$$Address);
5058 __ andl(Rdst, $mask$$constant & right_n_bits(8));
5059 %}
5060 ins_pipe(ialu_reg_mem);
5061 %}
5062
5063 // Load Short (16 bit signed)
5064 instruct loadS(rRegI dst, memory mem)
5065 %{
5066 match(Set dst (LoadS mem));
5067
5068 ins_cost(125);
5069 format %{ "movswl $dst, $mem\t# short" %}
5070
5071 ins_encode %{
5072 __ movswl($dst$$Register, $mem$$Address);
5073 %}
5074
5075 ins_pipe(ialu_reg_mem);
5076 %}
5077
5078 // Load Short (16 bit signed) to Byte (8 bit signed)
5079 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5080 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5081
5082 ins_cost(125);
5083 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5084 ins_encode %{
5085 __ movsbl($dst$$Register, $mem$$Address);
5086 %}
5087 ins_pipe(ialu_reg_mem);
5088 %}
5089
5090 // Load Short (16 bit signed) into Long Register
5091 instruct loadS2L(rRegL dst, memory mem)
5092 %{
5093 match(Set dst (ConvI2L (LoadS mem)));
5094
5095 ins_cost(125);
5096 format %{ "movswq $dst, $mem\t# short -> long" %}
5097
5098 ins_encode %{
5099 __ movswq($dst$$Register, $mem$$Address);
5100 %}
5101
5102 ins_pipe(ialu_reg_mem);
5103 %}
5104
5105 // Load Unsigned Short/Char (16 bit UNsigned)
5106 instruct loadUS(rRegI dst, memory mem)
5107 %{
5108 match(Set dst (LoadUS mem));
5109
5110 ins_cost(125);
5111 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5112
5113 ins_encode %{
5114 __ movzwl($dst$$Register, $mem$$Address);
5115 %}
5116
5117 ins_pipe(ialu_reg_mem);
5118 %}
5119
5120 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5121 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5122 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5123
5124 ins_cost(125);
5125 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5126 ins_encode %{
5127 __ movsbl($dst$$Register, $mem$$Address);
5128 %}
5129 ins_pipe(ialu_reg_mem);
5130 %}
5131
5132 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5133 instruct loadUS2L(rRegL dst, memory mem)
5134 %{
5135 match(Set dst (ConvI2L (LoadUS mem)));
5136
5137 ins_cost(125);
5138 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5139
5140 ins_encode %{
5141 __ movzwq($dst$$Register, $mem$$Address);
5142 %}
5143
5144 ins_pipe(ialu_reg_mem);
5145 %}
5146
5147 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5148 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5149 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5150
5151 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5152 ins_encode %{
5153 __ movzbq($dst$$Register, $mem$$Address);
5154 %}
5155 ins_pipe(ialu_reg_mem);
5156 %}
5157
5158 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
5159 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5160 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5161 effect(KILL cr);
5162
5163 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
5164 "andl $dst, right_n_bits($mask, 16)" %}
5165 ins_encode %{
5166 Register Rdst = $dst$$Register;
5167 __ movzwq(Rdst, $mem$$Address);
5168 __ andl(Rdst, $mask$$constant & right_n_bits(16));
5169 %}
5170 ins_pipe(ialu_reg_mem);
5171 %}
5172
5173 // Load Integer
5174 instruct loadI(rRegI dst, memory mem)
5175 %{
5176 match(Set dst (LoadI mem));
5177
5178 ins_cost(125);
5179 format %{ "movl $dst, $mem\t# int" %}
5180
5181 ins_encode %{
5182 __ movl($dst$$Register, $mem$$Address);
5183 %}
5184
5185 ins_pipe(ialu_reg_mem);
5186 %}
5187
5188 // Load Integer (32 bit signed) to Byte (8 bit signed)
5189 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5190 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5191
5192 ins_cost(125);
5193 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5194 ins_encode %{
5195 __ movsbl($dst$$Register, $mem$$Address);
5196 %}
5197 ins_pipe(ialu_reg_mem);
5198 %}
5199
5200 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5201 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5202 match(Set dst (AndI (LoadI mem) mask));
5203
5204 ins_cost(125);
5205 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5206 ins_encode %{
5207 __ movzbl($dst$$Register, $mem$$Address);
5208 %}
5209 ins_pipe(ialu_reg_mem);
5210 %}
5211
5212 // Load Integer (32 bit signed) to Short (16 bit signed)
5213 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5214 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5215
5216 ins_cost(125);
5217 format %{ "movswl $dst, $mem\t# int -> short" %}
5218 ins_encode %{
5219 __ movswl($dst$$Register, $mem$$Address);
5220 %}
5221 ins_pipe(ialu_reg_mem);
5222 %}
5223
5224 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5225 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5226 match(Set dst (AndI (LoadI mem) mask));
5227
5228 ins_cost(125);
5229 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5230 ins_encode %{
5231 __ movzwl($dst$$Register, $mem$$Address);
5232 %}
5233 ins_pipe(ialu_reg_mem);
5234 %}
5235
5236 // Load Integer into Long Register
5237 instruct loadI2L(rRegL dst, memory mem)
5238 %{
5239 match(Set dst (ConvI2L (LoadI mem)));
5240
5241 ins_cost(125);
5242 format %{ "movslq $dst, $mem\t# int -> long" %}
5243
5244 ins_encode %{
5245 __ movslq($dst$$Register, $mem$$Address);
5246 %}
5247
5248 ins_pipe(ialu_reg_mem);
5249 %}
5250
5251 // Load Integer with mask 0xFF into Long Register
5252 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5253 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5254
5255 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5256 ins_encode %{
5257 __ movzbq($dst$$Register, $mem$$Address);
5258 %}
5259 ins_pipe(ialu_reg_mem);
5260 %}
5261
5262 // Load Integer with mask 0xFFFF into Long Register
5263 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5264 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5265
5266 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5267 ins_encode %{
5268 __ movzwq($dst$$Register, $mem$$Address);
5269 %}
5270 ins_pipe(ialu_reg_mem);
5271 %}
5272
5273 // Load Integer with a 31-bit mask into Long Register
5274 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5275 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5276 effect(KILL cr);
5277
5278 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5279 "andl $dst, $mask" %}
5280 ins_encode %{
5281 Register Rdst = $dst$$Register;
5282 __ movl(Rdst, $mem$$Address);
5283 __ andl(Rdst, $mask$$constant);
5284 %}
5285 ins_pipe(ialu_reg_mem);
5286 %}
5287
5288 // Load Unsigned Integer into Long Register
5289 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5290 %{
5291 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5292
5293 ins_cost(125);
5294 format %{ "movl $dst, $mem\t# uint -> long" %}
5295
5296 ins_encode %{
5297 __ movl($dst$$Register, $mem$$Address);
5298 %}
5299
5300 ins_pipe(ialu_reg_mem);
5301 %}
5302
5303 // Load Long
5304 instruct loadL(rRegL dst, memory mem)
5305 %{
5306 match(Set dst (LoadL mem));
5307
5308 ins_cost(125);
5309 format %{ "movq $dst, $mem\t# long" %}
5310
5311 ins_encode %{
5312 __ movq($dst$$Register, $mem$$Address);
5313 %}
5314
5315 ins_pipe(ialu_reg_mem); // XXX
5316 %}
5317
5318 // Load Range
5319 instruct loadRange(rRegI dst, memory mem)
5320 %{
5321 match(Set dst (LoadRange mem));
5322
5323 ins_cost(125); // XXX
5324 format %{ "movl $dst, $mem\t# range" %}
5325 opcode(0x8B);
5326 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5327 ins_pipe(ialu_reg_mem);
5328 %}
5329
5330 // Load Pointer
5331 instruct loadP(rRegP dst, memory mem)
5332 %{
5333 match(Set dst (LoadP mem));
5334
5335 ins_cost(125); // XXX
5336 format %{ "movq $dst, $mem\t# ptr" %}
5337 opcode(0x8B);
5338 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5339 ins_pipe(ialu_reg_mem); // XXX
5340 %}
5341
5342 // Load Compressed Pointer
5343 instruct loadN(rRegN dst, memory mem)
5344 %{
5345 match(Set dst (LoadN mem));
5346
5347 ins_cost(125); // XXX
5348 format %{ "movl $dst, $mem\t# compressed ptr" %}
5349 ins_encode %{
5350 __ movl($dst$$Register, $mem$$Address);
5351 %}
5352 ins_pipe(ialu_reg_mem); // XXX
5353 %}
5354
5355
5356 // Load Klass Pointer
5357 instruct loadKlass(rRegP dst, memory mem)
5358 %{
5359 match(Set dst (LoadKlass mem));
5360
5361 ins_cost(125); // XXX
5362 format %{ "movq $dst, $mem\t# class" %}
5363 opcode(0x8B);
5364 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5365 ins_pipe(ialu_reg_mem); // XXX
5366 %}
5367
5368 // Load narrow Klass Pointer
5369 instruct loadNKlass(rRegN dst, memory mem)
5370 %{
5371 match(Set dst (LoadNKlass mem));
5372
5373 ins_cost(125); // XXX
5374 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5375 ins_encode %{
5376 __ movl($dst$$Register, $mem$$Address);
5377 %}
5378 ins_pipe(ialu_reg_mem); // XXX
5379 %}
5380
5381 // Load Float
5382 instruct loadF(regF dst, memory mem)
5383 %{
5384 match(Set dst (LoadF mem));
5385
5386 ins_cost(145); // XXX
5387 format %{ "movss $dst, $mem\t# float" %}
5388 ins_encode %{
5389 __ movflt($dst$$XMMRegister, $mem$$Address);
5390 %}
5391 ins_pipe(pipe_slow); // XXX
5392 %}
5393
5394 // Load Float
5395 instruct MoveF2VL(vlRegF dst, regF src) %{
5396 match(Set dst src);
5397 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5398 ins_encode %{
5399 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5400 %}
5401 ins_pipe( fpu_reg_reg );
5402 %}
5403
5404 // Load Float
5405 instruct MoveF2LEG(legRegF dst, regF src) %{
5406 match(Set dst src);
5407 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5408 ins_encode %{
5409 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5410 %}
5411 ins_pipe( fpu_reg_reg );
5412 %}
5413
5414 // Load Float
5415 instruct MoveVL2F(regF dst, vlRegF src) %{
5416 match(Set dst src);
5417 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5418 ins_encode %{
5419 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5420 %}
5421 ins_pipe( fpu_reg_reg );
5422 %}
5423
5424 // Load Float
5425 instruct MoveLEG2F(regF dst, legRegF src) %{
5426 match(Set dst src);
5427 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5428 ins_encode %{
5429 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5430 %}
5431 ins_pipe( fpu_reg_reg );
5432 %}
5433
5434 // Load Double
5435 instruct loadD_partial(regD dst, memory mem)
5436 %{
5437 predicate(!UseXmmLoadAndClearUpper);
5438 match(Set dst (LoadD mem));
5439
5440 ins_cost(145); // XXX
5441 format %{ "movlpd $dst, $mem\t# double" %}
5442 ins_encode %{
5443 __ movdbl($dst$$XMMRegister, $mem$$Address);
5444 %}
5445 ins_pipe(pipe_slow); // XXX
5446 %}
5447
5448 instruct loadD(regD dst, memory mem)
5449 %{
5450 predicate(UseXmmLoadAndClearUpper);
5451 match(Set dst (LoadD mem));
5452
5453 ins_cost(145); // XXX
5454 format %{ "movsd $dst, $mem\t# double" %}
5455 ins_encode %{
5456 __ movdbl($dst$$XMMRegister, $mem$$Address);
5457 %}
5458 ins_pipe(pipe_slow); // XXX
5459 %}
5460
5461 // Load Double
5462 instruct MoveD2VL(vlRegD dst, regD src) %{
5463 match(Set dst src);
5464 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5465 ins_encode %{
5466 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5467 %}
5468 ins_pipe( fpu_reg_reg );
5469 %}
5470
5471 // Load Double
5472 instruct MoveD2LEG(legRegD dst, regD src) %{
5473 match(Set dst src);
5474 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5475 ins_encode %{
5476 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5477 %}
5478 ins_pipe( fpu_reg_reg );
5479 %}
5480
5481 // Load Double
5482 instruct MoveVL2D(regD dst, vlRegD src) %{
5483 match(Set dst src);
5484 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5485 ins_encode %{
5486 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5487 %}
5488 ins_pipe( fpu_reg_reg );
5489 %}
5490
5491 // Load Double
5492 instruct MoveLEG2D(regD dst, legRegD src) %{
5493 match(Set dst src);
5494 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5495 ins_encode %{
5496 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5497 %}
5498 ins_pipe( fpu_reg_reg );
5499 %}
5500
5501 // Following pseudo code describes the algorithm for max[FD]:
5502 // Min algorithm is on similar lines
5503 // btmp = (b < +0.0) ? a : b
5504 // atmp = (b < +0.0) ? b : a
5505 // Tmp = Max_Float(atmp , btmp)
5506 // Res = (atmp == NaN) ? atmp : Tmp
5507
5508 // max = java.lang.Math.max(float a, float b)
5509 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5510 predicate(UseAVX > 0 && !n->is_reduction());
5511 match(Set dst (MaxF a b));
5512 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5513 format %{
5514 "blendvps $btmp,$b,$a,$b \n\t"
5515 "blendvps $atmp,$a,$b,$b \n\t"
5516 "vmaxss $tmp,$atmp,$btmp \n\t"
5517 "cmpps.unordered $btmp,$atmp,$atmp \n\t"
5518 "blendvps $dst,$tmp,$atmp,$btmp \n\t"
5519 %}
5520 ins_encode %{
5521 int vector_len = Assembler::AVX_128bit;
5522 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5523 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5524 __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5525 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5526 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5527 %}
5528 ins_pipe( pipe_slow );
5529 %}
5530
5531 instruct maxF_reduction_reg(regF dst, regF a, regF b, regF xmmt, rRegI tmp, rFlagsReg cr) %{
5532 predicate(UseAVX > 0 && n->is_reduction());
5533 match(Set dst (MaxF a b));
5534 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5535
5536 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
5537 ins_encode %{
5538 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5539 false /*min*/, true /*single*/);
5540 %}
5541 ins_pipe( pipe_slow );
5542 %}
5543
5544 // max = java.lang.Math.max(double a, double b)
5545 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5546 predicate(UseAVX > 0 && !n->is_reduction());
5547 match(Set dst (MaxD a b));
5548 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
5549 format %{
5550 "blendvpd $btmp,$b,$a,$b \n\t"
5551 "blendvpd $atmp,$a,$b,$b \n\t"
5552 "vmaxsd $tmp,$atmp,$btmp \n\t"
5553 "cmppd.unordered $btmp,$atmp,$atmp \n\t"
5554 "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
5555 %}
5556 ins_encode %{
5557 int vector_len = Assembler::AVX_128bit;
5558 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5559 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5560 __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5561 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5562 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5563 %}
5564 ins_pipe( pipe_slow );
5565 %}
5566
5567 instruct maxD_reduction_reg(regD dst, regD a, regD b, regD xmmt, rRegL tmp, rFlagsReg cr) %{
5568 predicate(UseAVX > 0 && n->is_reduction());
5569 match(Set dst (MaxD a b));
5570 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5571
5572 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
5573 ins_encode %{
5574 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5575 false /*min*/, false /*single*/);
5576 %}
5577 ins_pipe( pipe_slow );
5578 %}
5579
5580 // min = java.lang.Math.min(float a, float b)
5581 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5582 predicate(UseAVX > 0 && !n->is_reduction());
5583 match(Set dst (MinF a b));
5584 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5585 format %{
5586 "blendvps $atmp,$a,$b,$a \n\t"
5587 "blendvps $btmp,$b,$a,$a \n\t"
5588 "vminss $tmp,$atmp,$btmp \n\t"
5589 "cmpps.unordered $btmp,$atmp,$atmp \n\t"
5590 "blendvps $dst,$tmp,$atmp,$btmp \n\t"
5591 %}
5592 ins_encode %{
5593 int vector_len = Assembler::AVX_128bit;
5594 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5595 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5596 __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5597 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5598 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5599 %}
5600 ins_pipe( pipe_slow );
5601 %}
5602
5603 instruct minF_reduction_reg(regF dst, regF a, regF b, regF xmmt, rRegI tmp, rFlagsReg cr) %{
5604 predicate(UseAVX > 0 && n->is_reduction());
5605 match(Set dst (MinF a b));
5606 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5607
5608 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
5609 ins_encode %{
5610 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5611 true /*min*/, true /*single*/);
5612 %}
5613 ins_pipe( pipe_slow );
5614 %}
5615
5616 // min = java.lang.Math.min(double a, double b)
5617 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5618 predicate(UseAVX > 0 && !n->is_reduction());
5619 match(Set dst (MinD a b));
5620 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5621 format %{
5622 "blendvpd $atmp,$a,$b,$a \n\t"
5623 "blendvpd $btmp,$b,$a,$a \n\t"
5624 "vminsd $tmp,$atmp,$btmp \n\t"
5625 "cmppd.unordered $btmp,$atmp,$atmp \n\t"
5626 "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
5627 %}
5628 ins_encode %{
5629 int vector_len = Assembler::AVX_128bit;
5630 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5631 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5632 __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5633 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5634 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5635 %}
5636 ins_pipe( pipe_slow );
5637 %}
5638
5639 instruct minD_reduction_reg(regD dst, regD a, regD b, regD xmmt, rRegL tmp, rFlagsReg cr) %{
5640 predicate(UseAVX > 0 && n->is_reduction());
5641 match(Set dst (MinD a b));
5642 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5643
5644 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
5645 ins_encode %{
5646 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5647 true /*min*/, false /*single*/);
5648 %}
5649 ins_pipe( pipe_slow );
5650 %}
5651
5652 // Load Effective Address
5653 instruct leaP8(rRegP dst, indOffset8 mem)
5654 %{
5655 match(Set dst mem);
5656
5657 ins_cost(110); // XXX
5658 format %{ "leaq $dst, $mem\t# ptr 8" %}
5659 opcode(0x8D);
5660 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5661 ins_pipe(ialu_reg_reg_fat);
5662 %}
5663
5664 instruct leaP32(rRegP dst, indOffset32 mem)
5665 %{
5666 match(Set dst mem);
5667
5668 ins_cost(110);
5669 format %{ "leaq $dst, $mem\t# ptr 32" %}
5670 opcode(0x8D);
5671 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5672 ins_pipe(ialu_reg_reg_fat);
5673 %}
5674
5675 // instruct leaPIdx(rRegP dst, indIndex mem)
5676 // %{
5677 // match(Set dst mem);
5678
5679 // ins_cost(110);
5680 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5681 // opcode(0x8D);
5682 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5683 // ins_pipe(ialu_reg_reg_fat);
5684 // %}
5685
5686 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5687 %{
5688 match(Set dst mem);
5689
5690 ins_cost(110);
5691 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5692 opcode(0x8D);
5693 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5694 ins_pipe(ialu_reg_reg_fat);
5695 %}
5696
5697 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5698 %{
5699 match(Set dst mem);
5700
5701 ins_cost(110);
5702 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5703 opcode(0x8D);
5704 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5705 ins_pipe(ialu_reg_reg_fat);
5706 %}
5707
5708 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5709 %{
5710 match(Set dst mem);
5711
5712 ins_cost(110);
5713 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5714 opcode(0x8D);
5715 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5716 ins_pipe(ialu_reg_reg_fat);
5717 %}
5718
5719 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5720 %{
5721 match(Set dst mem);
5722
5723 ins_cost(110);
5724 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5725 opcode(0x8D);
5726 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5727 ins_pipe(ialu_reg_reg_fat);
5728 %}
5729
5730 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5731 %{
5732 match(Set dst mem);
5733
5734 ins_cost(110);
5735 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5736 opcode(0x8D);
5737 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5738 ins_pipe(ialu_reg_reg_fat);
5739 %}
5740
5741 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5742 %{
5743 match(Set dst mem);
5744
5745 ins_cost(110);
5746 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5747 opcode(0x8D);
5748 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5749 ins_pipe(ialu_reg_reg_fat);
5750 %}
5751
5752 // Load Effective Address which uses Narrow (32-bits) oop
5753 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5754 %{
5755 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5756 match(Set dst mem);
5757
5758 ins_cost(110);
5759 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5760 opcode(0x8D);
5761 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5762 ins_pipe(ialu_reg_reg_fat);
5763 %}
5764
5765 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5766 %{
5767 predicate(Universe::narrow_oop_shift() == 0);
5768 match(Set dst mem);
5769
5770 ins_cost(110); // XXX
5771 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5772 opcode(0x8D);
5773 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5774 ins_pipe(ialu_reg_reg_fat);
5775 %}
5776
5777 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5778 %{
5779 predicate(Universe::narrow_oop_shift() == 0);
5780 match(Set dst mem);
5781
5782 ins_cost(110);
5783 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5784 opcode(0x8D);
5785 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5786 ins_pipe(ialu_reg_reg_fat);
5787 %}
5788
5789 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5790 %{
5791 predicate(Universe::narrow_oop_shift() == 0);
5792 match(Set dst mem);
5793
5794 ins_cost(110);
5795 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5796 opcode(0x8D);
5797 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5798 ins_pipe(ialu_reg_reg_fat);
5799 %}
5800
5801 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5802 %{
5803 predicate(Universe::narrow_oop_shift() == 0);
5804 match(Set dst mem);
5805
5806 ins_cost(110);
5807 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5808 opcode(0x8D);
5809 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5810 ins_pipe(ialu_reg_reg_fat);
5811 %}
5812
5813 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5814 %{
5815 predicate(Universe::narrow_oop_shift() == 0);
5816 match(Set dst mem);
5817
5818 ins_cost(110);
5819 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5820 opcode(0x8D);
5821 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5822 ins_pipe(ialu_reg_reg_fat);
5823 %}
5824
5825 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5826 %{
5827 predicate(Universe::narrow_oop_shift() == 0);
5828 match(Set dst mem);
5829
5830 ins_cost(110);
5831 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5832 opcode(0x8D);
5833 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5834 ins_pipe(ialu_reg_reg_fat);
5835 %}
5836
5837 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5838 %{
5839 predicate(Universe::narrow_oop_shift() == 0);
5840 match(Set dst mem);
5841
5842 ins_cost(110);
5843 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5844 opcode(0x8D);
5845 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5846 ins_pipe(ialu_reg_reg_fat);
5847 %}
5848
5849 instruct loadConI(rRegI dst, immI src)
5850 %{
5851 match(Set dst src);
5852
5853 format %{ "movl $dst, $src\t# int" %}
5854 ins_encode(load_immI(dst, src));
5855 ins_pipe(ialu_reg_fat); // XXX
5856 %}
5857
5858 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5859 %{
5860 match(Set dst src);
5861 effect(KILL cr);
5862
5863 ins_cost(50);
5864 format %{ "xorl $dst, $dst\t# int" %}
5865 opcode(0x33); /* + rd */
5866 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5867 ins_pipe(ialu_reg);
5868 %}
5869
5870 instruct loadConL(rRegL dst, immL src)
5871 %{
5872 match(Set dst src);
5873
5874 ins_cost(150);
5875 format %{ "movq $dst, $src\t# long" %}
5876 ins_encode(load_immL(dst, src));
5877 ins_pipe(ialu_reg);
5878 %}
5879
5880 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5881 %{
5882 match(Set dst src);
5883 effect(KILL cr);
5884
5885 ins_cost(50);
5886 format %{ "xorl $dst, $dst\t# long" %}
5887 opcode(0x33); /* + rd */
5888 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5889 ins_pipe(ialu_reg); // XXX
5890 %}
5891
5892 instruct loadConUL32(rRegL dst, immUL32 src)
5893 %{
5894 match(Set dst src);
5895
5896 ins_cost(60);
5897 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5898 ins_encode(load_immUL32(dst, src));
5899 ins_pipe(ialu_reg);
5900 %}
5901
5902 instruct loadConL32(rRegL dst, immL32 src)
5903 %{
5904 match(Set dst src);
5905
5906 ins_cost(70);
5907 format %{ "movq $dst, $src\t# long (32-bit)" %}
5908 ins_encode(load_immL32(dst, src));
5909 ins_pipe(ialu_reg);
5910 %}
5911
5912 instruct loadConP(rRegP dst, immP con) %{
5913 match(Set dst con);
5914
5915 format %{ "movq $dst, $con\t# ptr" %}
5916 ins_encode(load_immP(dst, con));
5917 ins_pipe(ialu_reg_fat); // XXX
5918 %}
5919
5920 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5921 %{
5922 match(Set dst src);
5923 effect(KILL cr);
5924
5925 ins_cost(50);
5926 format %{ "xorl $dst, $dst\t# ptr" %}
5927 opcode(0x33); /* + rd */
5928 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5929 ins_pipe(ialu_reg);
5930 %}
5931
5932 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5933 %{
5934 match(Set dst src);
5935 effect(KILL cr);
5936
5937 ins_cost(60);
5938 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5939 ins_encode(load_immP31(dst, src));
5940 ins_pipe(ialu_reg);
5941 %}
5942
5943 instruct loadConF(regF dst, immF con) %{
5944 match(Set dst con);
5945 ins_cost(125);
5946 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5947 ins_encode %{
5948 __ movflt($dst$$XMMRegister, $constantaddress($con));
5949 %}
5950 ins_pipe(pipe_slow);
5951 %}
5952
5953 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5954 match(Set dst src);
5955 effect(KILL cr);
5956 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5957 ins_encode %{
5958 __ xorq($dst$$Register, $dst$$Register);
5959 %}
5960 ins_pipe(ialu_reg);
5961 %}
5962
5963 instruct loadConN(rRegN dst, immN src) %{
5964 match(Set dst src);
5965
5966 ins_cost(125);
5967 format %{ "movl $dst, $src\t# compressed ptr" %}
5968 ins_encode %{
5969 address con = (address)$src$$constant;
5970 if (con == NULL) {
5971 ShouldNotReachHere();
5972 } else {
5973 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5974 }
5975 %}
5976 ins_pipe(ialu_reg_fat); // XXX
5977 %}
5978
5979 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5980 match(Set dst src);
5981
5982 ins_cost(125);
5983 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5984 ins_encode %{
5985 address con = (address)$src$$constant;
5986 if (con == NULL) {
5987 ShouldNotReachHere();
5988 } else {
5989 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5990 }
5991 %}
5992 ins_pipe(ialu_reg_fat); // XXX
5993 %}
5994
5995 instruct loadConF0(regF dst, immF0 src)
5996 %{
5997 match(Set dst src);
5998 ins_cost(100);
5999
6000 format %{ "xorps $dst, $dst\t# float 0.0" %}
6001 ins_encode %{
6002 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6003 %}
6004 ins_pipe(pipe_slow);
6005 %}
6006
6007 // Use the same format since predicate() can not be used here.
6008 instruct loadConD(regD dst, immD con) %{
6009 match(Set dst con);
6010 ins_cost(125);
6011 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
6012 ins_encode %{
6013 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6014 %}
6015 ins_pipe(pipe_slow);
6016 %}
6017
6018 instruct loadConD0(regD dst, immD0 src)
6019 %{
6020 match(Set dst src);
6021 ins_cost(100);
6022
6023 format %{ "xorpd $dst, $dst\t# double 0.0" %}
6024 ins_encode %{
6025 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6026 %}
6027 ins_pipe(pipe_slow);
6028 %}
6029
6030 instruct loadSSI(rRegI dst, stackSlotI src)
6031 %{
6032 match(Set dst src);
6033
6034 ins_cost(125);
6035 format %{ "movl $dst, $src\t# int stk" %}
6036 opcode(0x8B);
6037 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6038 ins_pipe(ialu_reg_mem);
6039 %}
6040
6041 instruct loadSSL(rRegL dst, stackSlotL src)
6042 %{
6043 match(Set dst src);
6044
6045 ins_cost(125);
6046 format %{ "movq $dst, $src\t# long stk" %}
6047 opcode(0x8B);
6048 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6049 ins_pipe(ialu_reg_mem);
6050 %}
6051
6052 instruct loadSSP(rRegP dst, stackSlotP src)
6053 %{
6054 match(Set dst src);
6055
6056 ins_cost(125);
6057 format %{ "movq $dst, $src\t# ptr stk" %}
6058 opcode(0x8B);
6059 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6060 ins_pipe(ialu_reg_mem);
6061 %}
6062
6063 instruct loadSSF(regF dst, stackSlotF src)
6064 %{
6065 match(Set dst src);
6066
6067 ins_cost(125);
6068 format %{ "movss $dst, $src\t# float stk" %}
6069 ins_encode %{
6070 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
6071 %}
6072 ins_pipe(pipe_slow); // XXX
6073 %}
6074
6075 // Use the same format since predicate() can not be used here.
6076 instruct loadSSD(regD dst, stackSlotD src)
6077 %{
6078 match(Set dst src);
6079
6080 ins_cost(125);
6081 format %{ "movsd $dst, $src\t# double stk" %}
6082 ins_encode %{
6083 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
6084 %}
6085 ins_pipe(pipe_slow); // XXX
6086 %}
6087
6088 // Prefetch instructions for allocation.
6089 // Must be safe to execute with invalid address (cannot fault).
6090
6091 instruct prefetchAlloc( memory mem ) %{
6092 predicate(AllocatePrefetchInstr==3);
6093 match(PrefetchAllocation mem);
6094 ins_cost(125);
6095
6096 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
6097 ins_encode %{
6098 __ prefetchw($mem$$Address);
6099 %}
6100 ins_pipe(ialu_mem);
6101 %}
6102
6103 instruct prefetchAllocNTA( memory mem ) %{
6104 predicate(AllocatePrefetchInstr==0);
6105 match(PrefetchAllocation mem);
6106 ins_cost(125);
6107
6108 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
6109 ins_encode %{
6110 __ prefetchnta($mem$$Address);
6111 %}
6112 ins_pipe(ialu_mem);
6113 %}
6114
6115 instruct prefetchAllocT0( memory mem ) %{
6116 predicate(AllocatePrefetchInstr==1);
6117 match(PrefetchAllocation mem);
6118 ins_cost(125);
6119
6120 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
6121 ins_encode %{
6122 __ prefetcht0($mem$$Address);
6123 %}
6124 ins_pipe(ialu_mem);
6125 %}
6126
6127 instruct prefetchAllocT2( memory mem ) %{
6128 predicate(AllocatePrefetchInstr==2);
6129 match(PrefetchAllocation mem);
6130 ins_cost(125);
6131
6132 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
6133 ins_encode %{
6134 __ prefetcht2($mem$$Address);
6135 %}
6136 ins_pipe(ialu_mem);
6137 %}
6138
6139 //----------Store Instructions-------------------------------------------------
6140
6141 // Store Byte
6142 instruct storeB(memory mem, rRegI src)
6143 %{
6144 match(Set mem (StoreB mem src));
6145
6146 ins_cost(125); // XXX
6147 format %{ "movb $mem, $src\t# byte" %}
6148 opcode(0x88);
6149 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6150 ins_pipe(ialu_mem_reg);
6151 %}
6152
6153 // Store Char/Short
6154 instruct storeC(memory mem, rRegI src)
6155 %{
6156 match(Set mem (StoreC mem src));
6157
6158 ins_cost(125); // XXX
6159 format %{ "movw $mem, $src\t# char/short" %}
6160 opcode(0x89);
6161 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6162 ins_pipe(ialu_mem_reg);
6163 %}
6164
6165 // Store Integer
6166 instruct storeI(memory mem, rRegI src)
6167 %{
6168 match(Set mem (StoreI mem src));
6169
6170 ins_cost(125); // XXX
6171 format %{ "movl $mem, $src\t# int" %}
6172 opcode(0x89);
6173 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6174 ins_pipe(ialu_mem_reg);
6175 %}
6176
6177 // Store Long
6178 instruct storeL(memory mem, rRegL src)
6179 %{
6180 match(Set mem (StoreL mem src));
6181
6182 ins_cost(125); // XXX
6183 format %{ "movq $mem, $src\t# long" %}
6184 opcode(0x89);
6185 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6186 ins_pipe(ialu_mem_reg); // XXX
6187 %}
6188
6189 // Store Pointer
6190 instruct storeP(memory mem, any_RegP src)
6191 %{
6192 match(Set mem (StoreP mem src));
6193
6194 ins_cost(125); // XXX
6195 format %{ "movq $mem, $src\t# ptr" %}
6196 opcode(0x89);
6197 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6198 ins_pipe(ialu_mem_reg);
6199 %}
6200
6201 instruct storeImmP0(memory mem, immP0 zero)
6202 %{
6203 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6204 match(Set mem (StoreP mem zero));
6205
6206 ins_cost(125); // XXX
6207 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6208 ins_encode %{
6209 __ movq($mem$$Address, r12);
6210 %}
6211 ins_pipe(ialu_mem_reg);
6212 %}
6213
6214 // Store NULL Pointer, mark word, or other simple pointer constant.
6215 instruct storeImmP(memory mem, immP31 src)
6216 %{
6217 match(Set mem (StoreP mem src));
6218
6219 ins_cost(150); // XXX
6220 format %{ "movq $mem, $src\t# ptr" %}
6221 opcode(0xC7); /* C7 /0 */
6222 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6223 ins_pipe(ialu_mem_imm);
6224 %}
6225
6226 // Store Compressed Pointer
6227 instruct storeN(memory mem, rRegN src)
6228 %{
6229 match(Set mem (StoreN mem src));
6230
6231 ins_cost(125); // XXX
6232 format %{ "movl $mem, $src\t# compressed ptr" %}
6233 ins_encode %{
6234 __ movl($mem$$Address, $src$$Register);
6235 %}
6236 ins_pipe(ialu_mem_reg);
6237 %}
6238
6239 instruct storeNKlass(memory mem, rRegN src)
6240 %{
6241 match(Set mem (StoreNKlass mem src));
6242
6243 ins_cost(125); // XXX
6244 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6245 ins_encode %{
6246 __ movl($mem$$Address, $src$$Register);
6247 %}
6248 ins_pipe(ialu_mem_reg);
6249 %}
6250
6251 instruct storeImmN0(memory mem, immN0 zero)
6252 %{
6253 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6254 match(Set mem (StoreN mem zero));
6255
6256 ins_cost(125); // XXX
6257 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6258 ins_encode %{
6259 __ movl($mem$$Address, r12);
6260 %}
6261 ins_pipe(ialu_mem_reg);
6262 %}
6263
6264 instruct storeImmN(memory mem, immN src)
6265 %{
6266 match(Set mem (StoreN mem src));
6267
6268 ins_cost(150); // XXX
6269 format %{ "movl $mem, $src\t# compressed ptr" %}
6270 ins_encode %{
6271 address con = (address)$src$$constant;
6272 if (con == NULL) {
6273 __ movl($mem$$Address, (int32_t)0);
6274 } else {
6275 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6276 }
6277 %}
6278 ins_pipe(ialu_mem_imm);
6279 %}
6280
6281 instruct storeImmNKlass(memory mem, immNKlass src)
6282 %{
6283 match(Set mem (StoreNKlass mem src));
6284
6285 ins_cost(150); // XXX
6286 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6287 ins_encode %{
6288 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6289 %}
6290 ins_pipe(ialu_mem_imm);
6291 %}
6292
6293 // Store Integer Immediate
6294 instruct storeImmI0(memory mem, immI0 zero)
6295 %{
6296 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6297 match(Set mem (StoreI mem zero));
6298
6299 ins_cost(125); // XXX
6300 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6301 ins_encode %{
6302 __ movl($mem$$Address, r12);
6303 %}
6304 ins_pipe(ialu_mem_reg);
6305 %}
6306
6307 instruct storeImmI(memory mem, immI src)
6308 %{
6309 match(Set mem (StoreI mem src));
6310
6311 ins_cost(150);
6312 format %{ "movl $mem, $src\t# int" %}
6313 opcode(0xC7); /* C7 /0 */
6314 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6315 ins_pipe(ialu_mem_imm);
6316 %}
6317
6318 // Store Long Immediate
6319 instruct storeImmL0(memory mem, immL0 zero)
6320 %{
6321 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6322 match(Set mem (StoreL mem zero));
6323
6324 ins_cost(125); // XXX
6325 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6326 ins_encode %{
6327 __ movq($mem$$Address, r12);
6328 %}
6329 ins_pipe(ialu_mem_reg);
6330 %}
6331
6332 instruct storeImmL(memory mem, immL32 src)
6333 %{
6334 match(Set mem (StoreL mem src));
6335
6336 ins_cost(150);
6337 format %{ "movq $mem, $src\t# long" %}
6338 opcode(0xC7); /* C7 /0 */
6339 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6340 ins_pipe(ialu_mem_imm);
6341 %}
6342
6343 // Store Short/Char Immediate
6344 instruct storeImmC0(memory mem, immI0 zero)
6345 %{
6346 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6347 match(Set mem (StoreC mem zero));
6348
6349 ins_cost(125); // XXX
6350 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6351 ins_encode %{
6352 __ movw($mem$$Address, r12);
6353 %}
6354 ins_pipe(ialu_mem_reg);
6355 %}
6356
6357 instruct storeImmI16(memory mem, immI16 src)
6358 %{
6359 predicate(UseStoreImmI16);
6360 match(Set mem (StoreC mem src));
6361
6362 ins_cost(150);
6363 format %{ "movw $mem, $src\t# short/char" %}
6364 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6365 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6366 ins_pipe(ialu_mem_imm);
6367 %}
6368
6369 // Store Byte Immediate
6370 instruct storeImmB0(memory mem, immI0 zero)
6371 %{
6372 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6373 match(Set mem (StoreB mem zero));
6374
6375 ins_cost(125); // XXX
6376 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6377 ins_encode %{
6378 __ movb($mem$$Address, r12);
6379 %}
6380 ins_pipe(ialu_mem_reg);
6381 %}
6382
6383 instruct storeImmB(memory mem, immI8 src)
6384 %{
6385 match(Set mem (StoreB mem src));
6386
6387 ins_cost(150); // XXX
6388 format %{ "movb $mem, $src\t# byte" %}
6389 opcode(0xC6); /* C6 /0 */
6390 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6391 ins_pipe(ialu_mem_imm);
6392 %}
6393
6394 // Store CMS card-mark Immediate
6395 instruct storeImmCM0_reg(memory mem, immI0 zero)
6396 %{
6397 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6398 match(Set mem (StoreCM mem zero));
6399
6400 ins_cost(125); // XXX
6401 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6402 ins_encode %{
6403 __ movb($mem$$Address, r12);
6404 %}
6405 ins_pipe(ialu_mem_reg);
6406 %}
6407
6408 instruct storeImmCM0(memory mem, immI0 src)
6409 %{
6410 match(Set mem (StoreCM mem src));
6411
6412 ins_cost(150); // XXX
6413 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6414 opcode(0xC6); /* C6 /0 */
6415 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6416 ins_pipe(ialu_mem_imm);
6417 %}
6418
6419 // Store Float
6420 instruct storeF(memory mem, regF src)
6421 %{
6422 match(Set mem (StoreF mem src));
6423
6424 ins_cost(95); // XXX
6425 format %{ "movss $mem, $src\t# float" %}
6426 ins_encode %{
6427 __ movflt($mem$$Address, $src$$XMMRegister);
6428 %}
6429 ins_pipe(pipe_slow); // XXX
6430 %}
6431
6432 // Store immediate Float value (it is faster than store from XMM register)
6433 instruct storeF0(memory mem, immF0 zero)
6434 %{
6435 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6436 match(Set mem (StoreF mem zero));
6437
6438 ins_cost(25); // XXX
6439 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6440 ins_encode %{
6441 __ movl($mem$$Address, r12);
6442 %}
6443 ins_pipe(ialu_mem_reg);
6444 %}
6445
6446 instruct storeF_imm(memory mem, immF src)
6447 %{
6448 match(Set mem (StoreF mem src));
6449
6450 ins_cost(50);
6451 format %{ "movl $mem, $src\t# float" %}
6452 opcode(0xC7); /* C7 /0 */
6453 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6454 ins_pipe(ialu_mem_imm);
6455 %}
6456
6457 // Store Double
6458 instruct storeD(memory mem, regD src)
6459 %{
6460 match(Set mem (StoreD mem src));
6461
6462 ins_cost(95); // XXX
6463 format %{ "movsd $mem, $src\t# double" %}
6464 ins_encode %{
6465 __ movdbl($mem$$Address, $src$$XMMRegister);
6466 %}
6467 ins_pipe(pipe_slow); // XXX
6468 %}
6469
6470 // Store immediate double 0.0 (it is faster than store from XMM register)
6471 instruct storeD0_imm(memory mem, immD0 src)
6472 %{
6473 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6474 match(Set mem (StoreD mem src));
6475
6476 ins_cost(50);
6477 format %{ "movq $mem, $src\t# double 0." %}
6478 opcode(0xC7); /* C7 /0 */
6479 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6480 ins_pipe(ialu_mem_imm);
6481 %}
6482
6483 instruct storeD0(memory mem, immD0 zero)
6484 %{
6485 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6486 match(Set mem (StoreD mem zero));
6487
6488 ins_cost(25); // XXX
6489 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6490 ins_encode %{
6491 __ movq($mem$$Address, r12);
6492 %}
6493 ins_pipe(ialu_mem_reg);
6494 %}
6495
6496 instruct storeSSI(stackSlotI dst, rRegI src)
6497 %{
6498 match(Set dst src);
6499
6500 ins_cost(100);
6501 format %{ "movl $dst, $src\t# int stk" %}
6502 opcode(0x89);
6503 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6504 ins_pipe( ialu_mem_reg );
6505 %}
6506
6507 instruct storeSSL(stackSlotL dst, rRegL src)
6508 %{
6509 match(Set dst src);
6510
6511 ins_cost(100);
6512 format %{ "movq $dst, $src\t# long stk" %}
6513 opcode(0x89);
6514 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6515 ins_pipe(ialu_mem_reg);
6516 %}
6517
6518 instruct storeSSP(stackSlotP dst, rRegP src)
6519 %{
6520 match(Set dst src);
6521
6522 ins_cost(100);
6523 format %{ "movq $dst, $src\t# ptr stk" %}
6524 opcode(0x89);
6525 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6526 ins_pipe(ialu_mem_reg);
6527 %}
6528
6529 instruct storeSSF(stackSlotF dst, regF src)
6530 %{
6531 match(Set dst src);
6532
6533 ins_cost(95); // XXX
6534 format %{ "movss $dst, $src\t# float stk" %}
6535 ins_encode %{
6536 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6537 %}
6538 ins_pipe(pipe_slow); // XXX
6539 %}
6540
6541 instruct storeSSD(stackSlotD dst, regD src)
6542 %{
6543 match(Set dst src);
6544
6545 ins_cost(95); // XXX
6546 format %{ "movsd $dst, $src\t# double stk" %}
6547 ins_encode %{
6548 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6549 %}
6550 ins_pipe(pipe_slow); // XXX
6551 %}
6552
6553 //----------BSWAP Instructions-------------------------------------------------
6554 instruct bytes_reverse_int(rRegI dst) %{
6555 match(Set dst (ReverseBytesI dst));
6556
6557 format %{ "bswapl $dst" %}
6558 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6559 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6560 ins_pipe( ialu_reg );
6561 %}
6562
6563 instruct bytes_reverse_long(rRegL dst) %{
6564 match(Set dst (ReverseBytesL dst));
6565
6566 format %{ "bswapq $dst" %}
6567 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6568 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6569 ins_pipe( ialu_reg);
6570 %}
6571
6572 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6573 match(Set dst (ReverseBytesUS dst));
6574 effect(KILL cr);
6575
6576 format %{ "bswapl $dst\n\t"
6577 "shrl $dst,16\n\t" %}
6578 ins_encode %{
6579 __ bswapl($dst$$Register);
6580 __ shrl($dst$$Register, 16);
6581 %}
6582 ins_pipe( ialu_reg );
6583 %}
6584
6585 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6586 match(Set dst (ReverseBytesS dst));
6587 effect(KILL cr);
6588
6589 format %{ "bswapl $dst\n\t"
6590 "sar $dst,16\n\t" %}
6591 ins_encode %{
6592 __ bswapl($dst$$Register);
6593 __ sarl($dst$$Register, 16);
6594 %}
6595 ins_pipe( ialu_reg );
6596 %}
6597
6598 //---------- Zeros Count Instructions ------------------------------------------
6599
6600 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6601 predicate(UseCountLeadingZerosInstruction);
6602 match(Set dst (CountLeadingZerosI src));
6603 effect(KILL cr);
6604
6605 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6606 ins_encode %{
6607 __ lzcntl($dst$$Register, $src$$Register);
6608 %}
6609 ins_pipe(ialu_reg);
6610 %}
6611
6612 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6613 predicate(!UseCountLeadingZerosInstruction);
6614 match(Set dst (CountLeadingZerosI src));
6615 effect(KILL cr);
6616
6617 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6618 "jnz skip\n\t"
6619 "movl $dst, -1\n"
6620 "skip:\n\t"
6621 "negl $dst\n\t"
6622 "addl $dst, 31" %}
6623 ins_encode %{
6624 Register Rdst = $dst$$Register;
6625 Register Rsrc = $src$$Register;
6626 Label skip;
6627 __ bsrl(Rdst, Rsrc);
6628 __ jccb(Assembler::notZero, skip);
6629 __ movl(Rdst, -1);
6630 __ bind(skip);
6631 __ negl(Rdst);
6632 __ addl(Rdst, BitsPerInt - 1);
6633 %}
6634 ins_pipe(ialu_reg);
6635 %}
6636
6637 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6638 predicate(UseCountLeadingZerosInstruction);
6639 match(Set dst (CountLeadingZerosL src));
6640 effect(KILL cr);
6641
6642 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6643 ins_encode %{
6644 __ lzcntq($dst$$Register, $src$$Register);
6645 %}
6646 ins_pipe(ialu_reg);
6647 %}
6648
6649 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6650 predicate(!UseCountLeadingZerosInstruction);
6651 match(Set dst (CountLeadingZerosL src));
6652 effect(KILL cr);
6653
6654 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6655 "jnz skip\n\t"
6656 "movl $dst, -1\n"
6657 "skip:\n\t"
6658 "negl $dst\n\t"
6659 "addl $dst, 63" %}
6660 ins_encode %{
6661 Register Rdst = $dst$$Register;
6662 Register Rsrc = $src$$Register;
6663 Label skip;
6664 __ bsrq(Rdst, Rsrc);
6665 __ jccb(Assembler::notZero, skip);
6666 __ movl(Rdst, -1);
6667 __ bind(skip);
6668 __ negl(Rdst);
6669 __ addl(Rdst, BitsPerLong - 1);
6670 %}
6671 ins_pipe(ialu_reg);
6672 %}
6673
6674 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6675 predicate(UseCountTrailingZerosInstruction);
6676 match(Set dst (CountTrailingZerosI src));
6677 effect(KILL cr);
6678
6679 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6680 ins_encode %{
6681 __ tzcntl($dst$$Register, $src$$Register);
6682 %}
6683 ins_pipe(ialu_reg);
6684 %}
6685
6686 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6687 predicate(!UseCountTrailingZerosInstruction);
6688 match(Set dst (CountTrailingZerosI src));
6689 effect(KILL cr);
6690
6691 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6692 "jnz done\n\t"
6693 "movl $dst, 32\n"
6694 "done:" %}
6695 ins_encode %{
6696 Register Rdst = $dst$$Register;
6697 Label done;
6698 __ bsfl(Rdst, $src$$Register);
6699 __ jccb(Assembler::notZero, done);
6700 __ movl(Rdst, BitsPerInt);
6701 __ bind(done);
6702 %}
6703 ins_pipe(ialu_reg);
6704 %}
6705
6706 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6707 predicate(UseCountTrailingZerosInstruction);
6708 match(Set dst (CountTrailingZerosL src));
6709 effect(KILL cr);
6710
6711 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6712 ins_encode %{
6713 __ tzcntq($dst$$Register, $src$$Register);
6714 %}
6715 ins_pipe(ialu_reg);
6716 %}
6717
6718 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6719 predicate(!UseCountTrailingZerosInstruction);
6720 match(Set dst (CountTrailingZerosL src));
6721 effect(KILL cr);
6722
6723 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6724 "jnz done\n\t"
6725 "movl $dst, 64\n"
6726 "done:" %}
6727 ins_encode %{
6728 Register Rdst = $dst$$Register;
6729 Label done;
6730 __ bsfq(Rdst, $src$$Register);
6731 __ jccb(Assembler::notZero, done);
6732 __ movl(Rdst, BitsPerLong);
6733 __ bind(done);
6734 %}
6735 ins_pipe(ialu_reg);
6736 %}
6737
6738
6739 //---------- Population Count Instructions -------------------------------------
6740
6741 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6742 predicate(UsePopCountInstruction);
6743 match(Set dst (PopCountI src));
6744 effect(KILL cr);
6745
6746 format %{ "popcnt $dst, $src" %}
6747 ins_encode %{
6748 __ popcntl($dst$$Register, $src$$Register);
6749 %}
6750 ins_pipe(ialu_reg);
6751 %}
6752
6753 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6754 predicate(UsePopCountInstruction);
6755 match(Set dst (PopCountI (LoadI mem)));
6756 effect(KILL cr);
6757
6758 format %{ "popcnt $dst, $mem" %}
6759 ins_encode %{
6760 __ popcntl($dst$$Register, $mem$$Address);
6761 %}
6762 ins_pipe(ialu_reg);
6763 %}
6764
6765 // Note: Long.bitCount(long) returns an int.
6766 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6767 predicate(UsePopCountInstruction);
6768 match(Set dst (PopCountL src));
6769 effect(KILL cr);
6770
6771 format %{ "popcnt $dst, $src" %}
6772 ins_encode %{
6773 __ popcntq($dst$$Register, $src$$Register);
6774 %}
6775 ins_pipe(ialu_reg);
6776 %}
6777
6778 // Note: Long.bitCount(long) returns an int.
6779 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6780 predicate(UsePopCountInstruction);
6781 match(Set dst (PopCountL (LoadL mem)));
6782 effect(KILL cr);
6783
6784 format %{ "popcnt $dst, $mem" %}
6785 ins_encode %{
6786 __ popcntq($dst$$Register, $mem$$Address);
6787 %}
6788 ins_pipe(ialu_reg);
6789 %}
6790
6791
6792 //----------MemBar Instructions-----------------------------------------------
6793 // Memory barrier flavors
6794
6795 instruct membar_acquire()
6796 %{
6797 match(MemBarAcquire);
6798 match(LoadFence);
6799 ins_cost(0);
6800
6801 size(0);
6802 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6803 ins_encode();
6804 ins_pipe(empty);
6805 %}
6806
6807 instruct membar_acquire_lock()
6808 %{
6809 match(MemBarAcquireLock);
6810 ins_cost(0);
6811
6812 size(0);
6813 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6814 ins_encode();
6815 ins_pipe(empty);
6816 %}
6817
6818 instruct membar_release()
6819 %{
6820 match(MemBarRelease);
6821 match(StoreFence);
6822 ins_cost(0);
6823
6824 size(0);
6825 format %{ "MEMBAR-release ! (empty encoding)" %}
6826 ins_encode();
6827 ins_pipe(empty);
6828 %}
6829
6830 instruct membar_release_lock()
6831 %{
6832 match(MemBarReleaseLock);
6833 ins_cost(0);
6834
6835 size(0);
6836 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6837 ins_encode();
6838 ins_pipe(empty);
6839 %}
6840
6841 instruct membar_volatile(rFlagsReg cr) %{
6842 match(MemBarVolatile);
6843 effect(KILL cr);
6844 ins_cost(400);
6845
6846 format %{
6847 $$template
6848 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6849 %}
6850 ins_encode %{
6851 __ membar(Assembler::StoreLoad);
6852 %}
6853 ins_pipe(pipe_slow);
6854 %}
6855
6856 instruct unnecessary_membar_volatile()
6857 %{
6858 match(MemBarVolatile);
6859 predicate(Matcher::post_store_load_barrier(n));
6860 ins_cost(0);
6861
6862 size(0);
6863 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6864 ins_encode();
6865 ins_pipe(empty);
6866 %}
6867
6868 instruct membar_storestore() %{
6869 match(MemBarStoreStore);
6870 ins_cost(0);
6871
6872 size(0);
6873 format %{ "MEMBAR-storestore (empty encoding)" %}
6874 ins_encode( );
6875 ins_pipe(empty);
6876 %}
6877
6878 //----------Move Instructions--------------------------------------------------
6879
6880 instruct castX2P(rRegP dst, rRegL src)
6881 %{
6882 match(Set dst (CastX2P src));
6883
6884 format %{ "movq $dst, $src\t# long->ptr" %}
6885 ins_encode %{
6886 if ($dst$$reg != $src$$reg) {
6887 __ movptr($dst$$Register, $src$$Register);
6888 }
6889 %}
6890 ins_pipe(ialu_reg_reg); // XXX
6891 %}
6892
6893 instruct castP2X(rRegL dst, rRegP src)
6894 %{
6895 match(Set dst (CastP2X src));
6896
6897 format %{ "movq $dst, $src\t# ptr -> long" %}
6898 ins_encode %{
6899 if ($dst$$reg != $src$$reg) {
6900 __ movptr($dst$$Register, $src$$Register);
6901 }
6902 %}
6903 ins_pipe(ialu_reg_reg); // XXX
6904 %}
6905
6906 // Convert oop into int for vectors alignment masking
6907 instruct convP2I(rRegI dst, rRegP src)
6908 %{
6909 match(Set dst (ConvL2I (CastP2X src)));
6910
6911 format %{ "movl $dst, $src\t# ptr -> int" %}
6912 ins_encode %{
6913 __ movl($dst$$Register, $src$$Register);
6914 %}
6915 ins_pipe(ialu_reg_reg); // XXX
6916 %}
6917
6918 // Convert compressed oop into int for vectors alignment masking
6919 // in case of 32bit oops (heap < 4Gb).
6920 instruct convN2I(rRegI dst, rRegN src)
6921 %{
6922 predicate(Universe::narrow_oop_shift() == 0);
6923 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6924
6925 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6926 ins_encode %{
6927 __ movl($dst$$Register, $src$$Register);
6928 %}
6929 ins_pipe(ialu_reg_reg); // XXX
6930 %}
6931
6932 // Convert oop pointer into compressed form
6933 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6934 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6935 match(Set dst (EncodeP src));
6936 effect(KILL cr);
6937 format %{ "encode_heap_oop $dst,$src" %}
6938 ins_encode %{
6939 Register s = $src$$Register;
6940 Register d = $dst$$Register;
6941 if (s != d) {
6942 __ movq(d, s);
6943 }
6944 __ encode_heap_oop(d);
6945 %}
6946 ins_pipe(ialu_reg_long);
6947 %}
6948
6949 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6950 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6951 match(Set dst (EncodeP src));
6952 effect(KILL cr);
6953 format %{ "encode_heap_oop_not_null $dst,$src" %}
6954 ins_encode %{
6955 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6956 %}
6957 ins_pipe(ialu_reg_long);
6958 %}
6959
6960 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6961 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6962 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6963 match(Set dst (DecodeN src));
6964 effect(KILL cr);
6965 format %{ "decode_heap_oop $dst,$src" %}
6966 ins_encode %{
6967 Register s = $src$$Register;
6968 Register d = $dst$$Register;
6969 if (s != d) {
6970 __ movq(d, s);
6971 }
6972 __ decode_heap_oop(d);
6973 %}
6974 ins_pipe(ialu_reg_long);
6975 %}
6976
6977 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6978 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6979 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6980 match(Set dst (DecodeN src));
6981 effect(KILL cr);
6982 format %{ "decode_heap_oop_not_null $dst,$src" %}
6983 ins_encode %{
6984 Register s = $src$$Register;
6985 Register d = $dst$$Register;
6986 if (s != d) {
6987 __ decode_heap_oop_not_null(d, s);
6988 } else {
6989 __ decode_heap_oop_not_null(d);
6990 }
6991 %}
6992 ins_pipe(ialu_reg_long);
6993 %}
6994
6995 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6996 match(Set dst (EncodePKlass src));
6997 effect(KILL cr);
6998 format %{ "encode_klass_not_null $dst,$src" %}
6999 ins_encode %{
7000 __ encode_klass_not_null($dst$$Register, $src$$Register);
7001 %}
7002 ins_pipe(ialu_reg_long);
7003 %}
7004
7005 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
7006 match(Set dst (DecodeNKlass src));
7007 effect(KILL cr);
7008 format %{ "decode_klass_not_null $dst,$src" %}
7009 ins_encode %{
7010 Register s = $src$$Register;
7011 Register d = $dst$$Register;
7012 if (s != d) {
7013 __ decode_klass_not_null(d, s);
7014 } else {
7015 __ decode_klass_not_null(d);
7016 }
7017 %}
7018 ins_pipe(ialu_reg_long);
7019 %}
7020
7021
7022 //----------Conditional Move---------------------------------------------------
7023 // Jump
7024 // dummy instruction for generating temp registers
7025 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
7026 match(Jump (LShiftL switch_val shift));
7027 ins_cost(350);
7028 predicate(false);
7029 effect(TEMP dest);
7030
7031 format %{ "leaq $dest, [$constantaddress]\n\t"
7032 "jmp [$dest + $switch_val << $shift]\n\t" %}
7033 ins_encode %{
7034 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7035 // to do that and the compiler is using that register as one it can allocate.
7036 // So we build it all by hand.
7037 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
7038 // ArrayAddress dispatch(table, index);
7039 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
7040 __ lea($dest$$Register, $constantaddress);
7041 __ jmp(dispatch);
7042 %}
7043 ins_pipe(pipe_jmp);
7044 %}
7045
7046 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
7047 match(Jump (AddL (LShiftL switch_val shift) offset));
7048 ins_cost(350);
7049 effect(TEMP dest);
7050
7051 format %{ "leaq $dest, [$constantaddress]\n\t"
7052 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
7053 ins_encode %{
7054 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7055 // to do that and the compiler is using that register as one it can allocate.
7056 // So we build it all by hand.
7057 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
7058 // ArrayAddress dispatch(table, index);
7059 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
7060 __ lea($dest$$Register, $constantaddress);
7061 __ jmp(dispatch);
7062 %}
7063 ins_pipe(pipe_jmp);
7064 %}
7065
7066 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
7067 match(Jump switch_val);
7068 ins_cost(350);
7069 effect(TEMP dest);
7070
7071 format %{ "leaq $dest, [$constantaddress]\n\t"
7072 "jmp [$dest + $switch_val]\n\t" %}
7073 ins_encode %{
7074 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7075 // to do that and the compiler is using that register as one it can allocate.
7076 // So we build it all by hand.
7077 // Address index(noreg, switch_reg, Address::times_1);
7078 // ArrayAddress dispatch(table, index);
7079 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
7080 __ lea($dest$$Register, $constantaddress);
7081 __ jmp(dispatch);
7082 %}
7083 ins_pipe(pipe_jmp);
7084 %}
7085
7086 // Conditional move
7087 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
7088 %{
7089 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7090
7091 ins_cost(200); // XXX
7092 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7093 opcode(0x0F, 0x40);
7094 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7095 ins_pipe(pipe_cmov_reg);
7096 %}
7097
7098 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
7099 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7100
7101 ins_cost(200); // XXX
7102 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7103 opcode(0x0F, 0x40);
7104 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7105 ins_pipe(pipe_cmov_reg);
7106 %}
7107
7108 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
7109 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7110 ins_cost(200);
7111 expand %{
7112 cmovI_regU(cop, cr, dst, src);
7113 %}
7114 %}
7115
7116 // Conditional move
7117 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7118 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7119
7120 ins_cost(250); // XXX
7121 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7122 opcode(0x0F, 0x40);
7123 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7124 ins_pipe(pipe_cmov_mem);
7125 %}
7126
7127 // Conditional move
7128 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7129 %{
7130 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7131
7132 ins_cost(250); // XXX
7133 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7134 opcode(0x0F, 0x40);
7135 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7136 ins_pipe(pipe_cmov_mem);
7137 %}
7138
7139 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7140 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7141 ins_cost(250);
7142 expand %{
7143 cmovI_memU(cop, cr, dst, src);
7144 %}
7145 %}
7146
7147 // Conditional move
7148 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7149 %{
7150 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7151
7152 ins_cost(200); // XXX
7153 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7154 opcode(0x0F, 0x40);
7155 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7156 ins_pipe(pipe_cmov_reg);
7157 %}
7158
7159 // Conditional move
7160 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7161 %{
7162 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7163
7164 ins_cost(200); // XXX
7165 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7166 opcode(0x0F, 0x40);
7167 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7168 ins_pipe(pipe_cmov_reg);
7169 %}
7170
7171 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7172 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7173 ins_cost(200);
7174 expand %{
7175 cmovN_regU(cop, cr, dst, src);
7176 %}
7177 %}
7178
7179 // Conditional move
7180 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7181 %{
7182 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7183
7184 ins_cost(200); // XXX
7185 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7186 opcode(0x0F, 0x40);
7187 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7188 ins_pipe(pipe_cmov_reg); // XXX
7189 %}
7190
7191 // Conditional move
7192 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7193 %{
7194 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7195
7196 ins_cost(200); // XXX
7197 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7198 opcode(0x0F, 0x40);
7199 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7200 ins_pipe(pipe_cmov_reg); // XXX
7201 %}
7202
7203 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7204 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7205 ins_cost(200);
7206 expand %{
7207 cmovP_regU(cop, cr, dst, src);
7208 %}
7209 %}
7210
7211 // DISABLED: Requires the ADLC to emit a bottom_type call that
7212 // correctly meets the two pointer arguments; one is an incoming
7213 // register but the other is a memory operand. ALSO appears to
7214 // be buggy with implicit null checks.
7215 //
7216 //// Conditional move
7217 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7218 //%{
7219 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7220 // ins_cost(250);
7221 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7222 // opcode(0x0F,0x40);
7223 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7224 // ins_pipe( pipe_cmov_mem );
7225 //%}
7226 //
7227 //// Conditional move
7228 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7229 //%{
7230 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7231 // ins_cost(250);
7232 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7233 // opcode(0x0F,0x40);
7234 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7235 // ins_pipe( pipe_cmov_mem );
7236 //%}
7237
7238 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7239 %{
7240 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7241
7242 ins_cost(200); // XXX
7243 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7244 opcode(0x0F, 0x40);
7245 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7246 ins_pipe(pipe_cmov_reg); // XXX
7247 %}
7248
7249 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7250 %{
7251 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7252
7253 ins_cost(200); // XXX
7254 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7255 opcode(0x0F, 0x40);
7256 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7257 ins_pipe(pipe_cmov_mem); // XXX
7258 %}
7259
7260 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7261 %{
7262 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7263
7264 ins_cost(200); // XXX
7265 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7266 opcode(0x0F, 0x40);
7267 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7268 ins_pipe(pipe_cmov_reg); // XXX
7269 %}
7270
7271 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7272 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7273 ins_cost(200);
7274 expand %{
7275 cmovL_regU(cop, cr, dst, src);
7276 %}
7277 %}
7278
7279 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7280 %{
7281 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7282
7283 ins_cost(200); // XXX
7284 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7285 opcode(0x0F, 0x40);
7286 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7287 ins_pipe(pipe_cmov_mem); // XXX
7288 %}
7289
7290 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7291 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7292 ins_cost(200);
7293 expand %{
7294 cmovL_memU(cop, cr, dst, src);
7295 %}
7296 %}
7297
7298 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7299 %{
7300 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7301
7302 ins_cost(200); // XXX
7303 format %{ "jn$cop skip\t# signed cmove float\n\t"
7304 "movss $dst, $src\n"
7305 "skip:" %}
7306 ins_encode %{
7307 Label Lskip;
7308 // Invert sense of branch from sense of CMOV
7309 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7310 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7311 __ bind(Lskip);
7312 %}
7313 ins_pipe(pipe_slow);
7314 %}
7315
7316 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7317 // %{
7318 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7319
7320 // ins_cost(200); // XXX
7321 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7322 // "movss $dst, $src\n"
7323 // "skip:" %}
7324 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7325 // ins_pipe(pipe_slow);
7326 // %}
7327
7328 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7329 %{
7330 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7331
7332 ins_cost(200); // XXX
7333 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7334 "movss $dst, $src\n"
7335 "skip:" %}
7336 ins_encode %{
7337 Label Lskip;
7338 // Invert sense of branch from sense of CMOV
7339 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7340 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7341 __ bind(Lskip);
7342 %}
7343 ins_pipe(pipe_slow);
7344 %}
7345
7346 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7347 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7348 ins_cost(200);
7349 expand %{
7350 cmovF_regU(cop, cr, dst, src);
7351 %}
7352 %}
7353
7354 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7355 %{
7356 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7357
7358 ins_cost(200); // XXX
7359 format %{ "jn$cop skip\t# signed cmove double\n\t"
7360 "movsd $dst, $src\n"
7361 "skip:" %}
7362 ins_encode %{
7363 Label Lskip;
7364 // Invert sense of branch from sense of CMOV
7365 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7366 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7367 __ bind(Lskip);
7368 %}
7369 ins_pipe(pipe_slow);
7370 %}
7371
7372 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7373 %{
7374 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7375
7376 ins_cost(200); // XXX
7377 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7378 "movsd $dst, $src\n"
7379 "skip:" %}
7380 ins_encode %{
7381 Label Lskip;
7382 // Invert sense of branch from sense of CMOV
7383 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7384 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7385 __ bind(Lskip);
7386 %}
7387 ins_pipe(pipe_slow);
7388 %}
7389
7390 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7391 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7392 ins_cost(200);
7393 expand %{
7394 cmovD_regU(cop, cr, dst, src);
7395 %}
7396 %}
7397
7398 //----------Arithmetic Instructions--------------------------------------------
7399 //----------Addition Instructions----------------------------------------------
7400
7401 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7402 %{
7403 match(Set dst (AddI dst src));
7404 effect(KILL cr);
7405
7406 format %{ "addl $dst, $src\t# int" %}
7407 opcode(0x03);
7408 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7409 ins_pipe(ialu_reg_reg);
7410 %}
7411
7412 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7413 %{
7414 match(Set dst (AddI dst src));
7415 effect(KILL cr);
7416
7417 format %{ "addl $dst, $src\t# int" %}
7418 opcode(0x81, 0x00); /* /0 id */
7419 ins_encode(OpcSErm(dst, src), Con8or32(src));
7420 ins_pipe( ialu_reg );
7421 %}
7422
7423 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7424 %{
7425 match(Set dst (AddI dst (LoadI src)));
7426 effect(KILL cr);
7427
7428 ins_cost(125); // XXX
7429 format %{ "addl $dst, $src\t# int" %}
7430 opcode(0x03);
7431 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7432 ins_pipe(ialu_reg_mem);
7433 %}
7434
7435 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7436 %{
7437 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7438 effect(KILL cr);
7439
7440 ins_cost(150); // XXX
7441 format %{ "addl $dst, $src\t# int" %}
7442 opcode(0x01); /* Opcode 01 /r */
7443 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7444 ins_pipe(ialu_mem_reg);
7445 %}
7446
7447 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7448 %{
7449 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7450 effect(KILL cr);
7451
7452 ins_cost(125); // XXX
7453 format %{ "addl $dst, $src\t# int" %}
7454 opcode(0x81); /* Opcode 81 /0 id */
7455 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7456 ins_pipe(ialu_mem_imm);
7457 %}
7458
7459 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7460 %{
7461 predicate(UseIncDec);
7462 match(Set dst (AddI dst src));
7463 effect(KILL cr);
7464
7465 format %{ "incl $dst\t# int" %}
7466 opcode(0xFF, 0x00); // FF /0
7467 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7468 ins_pipe(ialu_reg);
7469 %}
7470
7471 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7472 %{
7473 predicate(UseIncDec);
7474 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7475 effect(KILL cr);
7476
7477 ins_cost(125); // XXX
7478 format %{ "incl $dst\t# int" %}
7479 opcode(0xFF); /* Opcode FF /0 */
7480 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7481 ins_pipe(ialu_mem_imm);
7482 %}
7483
7484 // XXX why does that use AddI
7485 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7486 %{
7487 predicate(UseIncDec);
7488 match(Set dst (AddI dst src));
7489 effect(KILL cr);
7490
7491 format %{ "decl $dst\t# int" %}
7492 opcode(0xFF, 0x01); // FF /1
7493 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7494 ins_pipe(ialu_reg);
7495 %}
7496
7497 // XXX why does that use AddI
7498 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7499 %{
7500 predicate(UseIncDec);
7501 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7502 effect(KILL cr);
7503
7504 ins_cost(125); // XXX
7505 format %{ "decl $dst\t# int" %}
7506 opcode(0xFF); /* Opcode FF /1 */
7507 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7508 ins_pipe(ialu_mem_imm);
7509 %}
7510
7511 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7512 %{
7513 match(Set dst (AddI src0 src1));
7514
7515 ins_cost(110);
7516 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7517 opcode(0x8D); /* 0x8D /r */
7518 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7519 ins_pipe(ialu_reg_reg);
7520 %}
7521
7522 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7523 %{
7524 match(Set dst (AddL dst src));
7525 effect(KILL cr);
7526
7527 format %{ "addq $dst, $src\t# long" %}
7528 opcode(0x03);
7529 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7530 ins_pipe(ialu_reg_reg);
7531 %}
7532
7533 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7534 %{
7535 match(Set dst (AddL dst src));
7536 effect(KILL cr);
7537
7538 format %{ "addq $dst, $src\t# long" %}
7539 opcode(0x81, 0x00); /* /0 id */
7540 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7541 ins_pipe( ialu_reg );
7542 %}
7543
7544 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7545 %{
7546 match(Set dst (AddL dst (LoadL src)));
7547 effect(KILL cr);
7548
7549 ins_cost(125); // XXX
7550 format %{ "addq $dst, $src\t# long" %}
7551 opcode(0x03);
7552 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7553 ins_pipe(ialu_reg_mem);
7554 %}
7555
7556 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7557 %{
7558 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7559 effect(KILL cr);
7560
7561 ins_cost(150); // XXX
7562 format %{ "addq $dst, $src\t# long" %}
7563 opcode(0x01); /* Opcode 01 /r */
7564 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7565 ins_pipe(ialu_mem_reg);
7566 %}
7567
7568 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7569 %{
7570 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7571 effect(KILL cr);
7572
7573 ins_cost(125); // XXX
7574 format %{ "addq $dst, $src\t# long" %}
7575 opcode(0x81); /* Opcode 81 /0 id */
7576 ins_encode(REX_mem_wide(dst),
7577 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7578 ins_pipe(ialu_mem_imm);
7579 %}
7580
7581 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7582 %{
7583 predicate(UseIncDec);
7584 match(Set dst (AddL dst src));
7585 effect(KILL cr);
7586
7587 format %{ "incq $dst\t# long" %}
7588 opcode(0xFF, 0x00); // FF /0
7589 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7590 ins_pipe(ialu_reg);
7591 %}
7592
7593 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7594 %{
7595 predicate(UseIncDec);
7596 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7597 effect(KILL cr);
7598
7599 ins_cost(125); // XXX
7600 format %{ "incq $dst\t# long" %}
7601 opcode(0xFF); /* Opcode FF /0 */
7602 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7603 ins_pipe(ialu_mem_imm);
7604 %}
7605
7606 // XXX why does that use AddL
7607 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7608 %{
7609 predicate(UseIncDec);
7610 match(Set dst (AddL dst src));
7611 effect(KILL cr);
7612
7613 format %{ "decq $dst\t# long" %}
7614 opcode(0xFF, 0x01); // FF /1
7615 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7616 ins_pipe(ialu_reg);
7617 %}
7618
7619 // XXX why does that use AddL
7620 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7621 %{
7622 predicate(UseIncDec);
7623 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7624 effect(KILL cr);
7625
7626 ins_cost(125); // XXX
7627 format %{ "decq $dst\t# long" %}
7628 opcode(0xFF); /* Opcode FF /1 */
7629 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7630 ins_pipe(ialu_mem_imm);
7631 %}
7632
7633 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7634 %{
7635 match(Set dst (AddL src0 src1));
7636
7637 ins_cost(110);
7638 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7639 opcode(0x8D); /* 0x8D /r */
7640 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7641 ins_pipe(ialu_reg_reg);
7642 %}
7643
7644 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7645 %{
7646 match(Set dst (AddP dst src));
7647 effect(KILL cr);
7648
7649 format %{ "addq $dst, $src\t# ptr" %}
7650 opcode(0x03);
7651 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7652 ins_pipe(ialu_reg_reg);
7653 %}
7654
7655 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7656 %{
7657 match(Set dst (AddP dst src));
7658 effect(KILL cr);
7659
7660 format %{ "addq $dst, $src\t# ptr" %}
7661 opcode(0x81, 0x00); /* /0 id */
7662 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7663 ins_pipe( ialu_reg );
7664 %}
7665
7666 // XXX addP mem ops ????
7667
7668 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7669 %{
7670 match(Set dst (AddP src0 src1));
7671
7672 ins_cost(110);
7673 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7674 opcode(0x8D); /* 0x8D /r */
7675 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7676 ins_pipe(ialu_reg_reg);
7677 %}
7678
7679 instruct checkCastPP(rRegP dst)
7680 %{
7681 match(Set dst (CheckCastPP dst));
7682
7683 size(0);
7684 format %{ "# checkcastPP of $dst" %}
7685 ins_encode(/* empty encoding */);
7686 ins_pipe(empty);
7687 %}
7688
7689 instruct castPP(rRegP dst)
7690 %{
7691 match(Set dst (CastPP dst));
7692
7693 size(0);
7694 format %{ "# castPP of $dst" %}
7695 ins_encode(/* empty encoding */);
7696 ins_pipe(empty);
7697 %}
7698
7699 instruct castII(rRegI dst)
7700 %{
7701 match(Set dst (CastII dst));
7702
7703 size(0);
7704 format %{ "# castII of $dst" %}
7705 ins_encode(/* empty encoding */);
7706 ins_cost(0);
7707 ins_pipe(empty);
7708 %}
7709
7710 // LoadP-locked same as a regular LoadP when used with compare-swap
7711 instruct loadPLocked(rRegP dst, memory mem)
7712 %{
7713 match(Set dst (LoadPLocked mem));
7714
7715 ins_cost(125); // XXX
7716 format %{ "movq $dst, $mem\t# ptr locked" %}
7717 opcode(0x8B);
7718 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7719 ins_pipe(ialu_reg_mem); // XXX
7720 %}
7721
7722 // Conditional-store of the updated heap-top.
7723 // Used during allocation of the shared heap.
7724 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7725
7726 instruct storePConditional(memory heap_top_ptr,
7727 rax_RegP oldval, rRegP newval,
7728 rFlagsReg cr)
7729 %{
7730 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7731
7732 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7733 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7734 opcode(0x0F, 0xB1);
7735 ins_encode(lock_prefix,
7736 REX_reg_mem_wide(newval, heap_top_ptr),
7737 OpcP, OpcS,
7738 reg_mem(newval, heap_top_ptr));
7739 ins_pipe(pipe_cmpxchg);
7740 %}
7741
7742 // Conditional-store of an int value.
7743 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7744 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7745 %{
7746 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7747 effect(KILL oldval);
7748
7749 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7750 opcode(0x0F, 0xB1);
7751 ins_encode(lock_prefix,
7752 REX_reg_mem(newval, mem),
7753 OpcP, OpcS,
7754 reg_mem(newval, mem));
7755 ins_pipe(pipe_cmpxchg);
7756 %}
7757
7758 // Conditional-store of a long value.
7759 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7760 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7761 %{
7762 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7763 effect(KILL oldval);
7764
7765 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7766 opcode(0x0F, 0xB1);
7767 ins_encode(lock_prefix,
7768 REX_reg_mem_wide(newval, mem),
7769 OpcP, OpcS,
7770 reg_mem(newval, mem));
7771 ins_pipe(pipe_cmpxchg);
7772 %}
7773
7774
7775 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7776 instruct compareAndSwapP(rRegI res,
7777 memory mem_ptr,
7778 rax_RegP oldval, rRegP newval,
7779 rFlagsReg cr)
7780 %{
7781 predicate(VM_Version::supports_cx8());
7782 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7783 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7784 effect(KILL cr, KILL oldval);
7785
7786 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7787 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7788 "sete $res\n\t"
7789 "movzbl $res, $res" %}
7790 opcode(0x0F, 0xB1);
7791 ins_encode(lock_prefix,
7792 REX_reg_mem_wide(newval, mem_ptr),
7793 OpcP, OpcS,
7794 reg_mem(newval, mem_ptr),
7795 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7796 REX_reg_breg(res, res), // movzbl
7797 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7798 ins_pipe( pipe_cmpxchg );
7799 %}
7800
7801 instruct compareAndSwapL(rRegI res,
7802 memory mem_ptr,
7803 rax_RegL oldval, rRegL newval,
7804 rFlagsReg cr)
7805 %{
7806 predicate(VM_Version::supports_cx8());
7807 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7808 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7809 effect(KILL cr, KILL oldval);
7810
7811 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7812 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7813 "sete $res\n\t"
7814 "movzbl $res, $res" %}
7815 opcode(0x0F, 0xB1);
7816 ins_encode(lock_prefix,
7817 REX_reg_mem_wide(newval, mem_ptr),
7818 OpcP, OpcS,
7819 reg_mem(newval, mem_ptr),
7820 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7821 REX_reg_breg(res, res), // movzbl
7822 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7823 ins_pipe( pipe_cmpxchg );
7824 %}
7825
7826 instruct compareAndSwapI(rRegI res,
7827 memory mem_ptr,
7828 rax_RegI oldval, rRegI newval,
7829 rFlagsReg cr)
7830 %{
7831 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7832 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7833 effect(KILL cr, KILL oldval);
7834
7835 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7836 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7837 "sete $res\n\t"
7838 "movzbl $res, $res" %}
7839 opcode(0x0F, 0xB1);
7840 ins_encode(lock_prefix,
7841 REX_reg_mem(newval, mem_ptr),
7842 OpcP, OpcS,
7843 reg_mem(newval, mem_ptr),
7844 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7845 REX_reg_breg(res, res), // movzbl
7846 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7847 ins_pipe( pipe_cmpxchg );
7848 %}
7849
7850 instruct compareAndSwapB(rRegI res,
7851 memory mem_ptr,
7852 rax_RegI oldval, rRegI newval,
7853 rFlagsReg cr)
7854 %{
7855 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7856 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7857 effect(KILL cr, KILL oldval);
7858
7859 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7860 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7861 "sete $res\n\t"
7862 "movzbl $res, $res" %}
7863 opcode(0x0F, 0xB0);
7864 ins_encode(lock_prefix,
7865 REX_breg_mem(newval, mem_ptr),
7866 OpcP, OpcS,
7867 reg_mem(newval, mem_ptr),
7868 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7869 REX_reg_breg(res, res), // movzbl
7870 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7871 ins_pipe( pipe_cmpxchg );
7872 %}
7873
7874 instruct compareAndSwapS(rRegI res,
7875 memory mem_ptr,
7876 rax_RegI oldval, rRegI newval,
7877 rFlagsReg cr)
7878 %{
7879 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7880 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7881 effect(KILL cr, KILL oldval);
7882
7883 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7884 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7885 "sete $res\n\t"
7886 "movzbl $res, $res" %}
7887 opcode(0x0F, 0xB1);
7888 ins_encode(lock_prefix,
7889 SizePrefix,
7890 REX_reg_mem(newval, mem_ptr),
7891 OpcP, OpcS,
7892 reg_mem(newval, mem_ptr),
7893 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7894 REX_reg_breg(res, res), // movzbl
7895 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7896 ins_pipe( pipe_cmpxchg );
7897 %}
7898
7899 instruct compareAndSwapN(rRegI res,
7900 memory mem_ptr,
7901 rax_RegN oldval, rRegN newval,
7902 rFlagsReg cr) %{
7903 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7904 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7905 effect(KILL cr, KILL oldval);
7906
7907 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7908 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7909 "sete $res\n\t"
7910 "movzbl $res, $res" %}
7911 opcode(0x0F, 0xB1);
7912 ins_encode(lock_prefix,
7913 REX_reg_mem(newval, mem_ptr),
7914 OpcP, OpcS,
7915 reg_mem(newval, mem_ptr),
7916 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7917 REX_reg_breg(res, res), // movzbl
7918 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7919 ins_pipe( pipe_cmpxchg );
7920 %}
7921
7922 instruct compareAndExchangeB(
7923 memory mem_ptr,
7924 rax_RegI oldval, rRegI newval,
7925 rFlagsReg cr)
7926 %{
7927 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7928 effect(KILL cr);
7929
7930 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7931 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7932 opcode(0x0F, 0xB0);
7933 ins_encode(lock_prefix,
7934 REX_breg_mem(newval, mem_ptr),
7935 OpcP, OpcS,
7936 reg_mem(newval, mem_ptr) // lock cmpxchg
7937 );
7938 ins_pipe( pipe_cmpxchg );
7939 %}
7940
7941 instruct compareAndExchangeS(
7942 memory mem_ptr,
7943 rax_RegI oldval, rRegI newval,
7944 rFlagsReg cr)
7945 %{
7946 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7947 effect(KILL cr);
7948
7949 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7950 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7951 opcode(0x0F, 0xB1);
7952 ins_encode(lock_prefix,
7953 SizePrefix,
7954 REX_reg_mem(newval, mem_ptr),
7955 OpcP, OpcS,
7956 reg_mem(newval, mem_ptr) // lock cmpxchg
7957 );
7958 ins_pipe( pipe_cmpxchg );
7959 %}
7960
7961 instruct compareAndExchangeI(
7962 memory mem_ptr,
7963 rax_RegI oldval, rRegI newval,
7964 rFlagsReg cr)
7965 %{
7966 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7967 effect(KILL cr);
7968
7969 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7970 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7971 opcode(0x0F, 0xB1);
7972 ins_encode(lock_prefix,
7973 REX_reg_mem(newval, mem_ptr),
7974 OpcP, OpcS,
7975 reg_mem(newval, mem_ptr) // lock cmpxchg
7976 );
7977 ins_pipe( pipe_cmpxchg );
7978 %}
7979
7980 instruct compareAndExchangeL(
7981 memory mem_ptr,
7982 rax_RegL oldval, rRegL newval,
7983 rFlagsReg cr)
7984 %{
7985 predicate(VM_Version::supports_cx8());
7986 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7987 effect(KILL cr);
7988
7989 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7990 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7991 opcode(0x0F, 0xB1);
7992 ins_encode(lock_prefix,
7993 REX_reg_mem_wide(newval, mem_ptr),
7994 OpcP, OpcS,
7995 reg_mem(newval, mem_ptr) // lock cmpxchg
7996 );
7997 ins_pipe( pipe_cmpxchg );
7998 %}
7999
8000 instruct compareAndExchangeN(
8001 memory mem_ptr,
8002 rax_RegN oldval, rRegN newval,
8003 rFlagsReg cr) %{
8004 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
8005 effect(KILL cr);
8006
8007 format %{ "cmpxchgl $mem_ptr,$newval\t# "
8008 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
8009 opcode(0x0F, 0xB1);
8010 ins_encode(lock_prefix,
8011 REX_reg_mem(newval, mem_ptr),
8012 OpcP, OpcS,
8013 reg_mem(newval, mem_ptr) // lock cmpxchg
8014 );
8015 ins_pipe( pipe_cmpxchg );
8016 %}
8017
8018 instruct compareAndExchangeP(
8019 memory mem_ptr,
8020 rax_RegP oldval, rRegP newval,
8021 rFlagsReg cr)
8022 %{
8023 predicate(VM_Version::supports_cx8());
8024 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
8025 effect(KILL cr);
8026
8027 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8028 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
8029 opcode(0x0F, 0xB1);
8030 ins_encode(lock_prefix,
8031 REX_reg_mem_wide(newval, mem_ptr),
8032 OpcP, OpcS,
8033 reg_mem(newval, mem_ptr) // lock cmpxchg
8034 );
8035 ins_pipe( pipe_cmpxchg );
8036 %}
8037
8038 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8039 predicate(n->as_LoadStore()->result_not_used());
8040 match(Set dummy (GetAndAddB mem add));
8041 effect(KILL cr);
8042 format %{ "ADDB [$mem],$add" %}
8043 ins_encode %{
8044 __ lock();
8045 __ addb($mem$$Address, $add$$constant);
8046 %}
8047 ins_pipe( pipe_cmpxchg );
8048 %}
8049
8050 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
8051 match(Set newval (GetAndAddB mem newval));
8052 effect(KILL cr);
8053 format %{ "XADDB [$mem],$newval" %}
8054 ins_encode %{
8055 __ lock();
8056 __ xaddb($mem$$Address, $newval$$Register);
8057 %}
8058 ins_pipe( pipe_cmpxchg );
8059 %}
8060
8061 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8062 predicate(n->as_LoadStore()->result_not_used());
8063 match(Set dummy (GetAndAddS mem add));
8064 effect(KILL cr);
8065 format %{ "ADDW [$mem],$add" %}
8066 ins_encode %{
8067 __ lock();
8068 __ addw($mem$$Address, $add$$constant);
8069 %}
8070 ins_pipe( pipe_cmpxchg );
8071 %}
8072
8073 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
8074 match(Set newval (GetAndAddS mem newval));
8075 effect(KILL cr);
8076 format %{ "XADDW [$mem],$newval" %}
8077 ins_encode %{
8078 __ lock();
8079 __ xaddw($mem$$Address, $newval$$Register);
8080 %}
8081 ins_pipe( pipe_cmpxchg );
8082 %}
8083
8084 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8085 predicate(n->as_LoadStore()->result_not_used());
8086 match(Set dummy (GetAndAddI mem add));
8087 effect(KILL cr);
8088 format %{ "ADDL [$mem],$add" %}
8089 ins_encode %{
8090 __ lock();
8091 __ addl($mem$$Address, $add$$constant);
8092 %}
8093 ins_pipe( pipe_cmpxchg );
8094 %}
8095
8096 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
8097 match(Set newval (GetAndAddI mem newval));
8098 effect(KILL cr);
8099 format %{ "XADDL [$mem],$newval" %}
8100 ins_encode %{
8101 __ lock();
8102 __ xaddl($mem$$Address, $newval$$Register);
8103 %}
8104 ins_pipe( pipe_cmpxchg );
8105 %}
8106
8107 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8108 predicate(n->as_LoadStore()->result_not_used());
8109 match(Set dummy (GetAndAddL mem add));
8110 effect(KILL cr);
8111 format %{ "ADDQ [$mem],$add" %}
8112 ins_encode %{
8113 __ lock();
8114 __ addq($mem$$Address, $add$$constant);
8115 %}
8116 ins_pipe( pipe_cmpxchg );
8117 %}
8118
8119 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
8120 match(Set newval (GetAndAddL mem newval));
8121 effect(KILL cr);
8122 format %{ "XADDQ [$mem],$newval" %}
8123 ins_encode %{
8124 __ lock();
8125 __ xaddq($mem$$Address, $newval$$Register);
8126 %}
8127 ins_pipe( pipe_cmpxchg );
8128 %}
8129
8130 instruct xchgB( memory mem, rRegI newval) %{
8131 match(Set newval (GetAndSetB mem newval));
8132 format %{ "XCHGB $newval,[$mem]" %}
8133 ins_encode %{
8134 __ xchgb($newval$$Register, $mem$$Address);
8135 %}
8136 ins_pipe( pipe_cmpxchg );
8137 %}
8138
8139 instruct xchgS( memory mem, rRegI newval) %{
8140 match(Set newval (GetAndSetS mem newval));
8141 format %{ "XCHGW $newval,[$mem]" %}
8142 ins_encode %{
8143 __ xchgw($newval$$Register, $mem$$Address);
8144 %}
8145 ins_pipe( pipe_cmpxchg );
8146 %}
8147
8148 instruct xchgI( memory mem, rRegI newval) %{
8149 match(Set newval (GetAndSetI mem newval));
8150 format %{ "XCHGL $newval,[$mem]" %}
8151 ins_encode %{
8152 __ xchgl($newval$$Register, $mem$$Address);
8153 %}
8154 ins_pipe( pipe_cmpxchg );
8155 %}
8156
8157 instruct xchgL( memory mem, rRegL newval) %{
8158 match(Set newval (GetAndSetL mem newval));
8159 format %{ "XCHGL $newval,[$mem]" %}
8160 ins_encode %{
8161 __ xchgq($newval$$Register, $mem$$Address);
8162 %}
8163 ins_pipe( pipe_cmpxchg );
8164 %}
8165
8166 instruct xchgP( memory mem, rRegP newval) %{
8167 match(Set newval (GetAndSetP mem newval));
8168 format %{ "XCHGQ $newval,[$mem]" %}
8169 ins_encode %{
8170 __ xchgq($newval$$Register, $mem$$Address);
8171 %}
8172 ins_pipe( pipe_cmpxchg );
8173 %}
8174
8175 instruct xchgN( memory mem, rRegN newval) %{
8176 match(Set newval (GetAndSetN mem newval));
8177 format %{ "XCHGL $newval,$mem]" %}
8178 ins_encode %{
8179 __ xchgl($newval$$Register, $mem$$Address);
8180 %}
8181 ins_pipe( pipe_cmpxchg );
8182 %}
8183
8184 //----------Abs Instructions-------------------------------------------
8185
8186 // Integer Absolute Instructions
8187 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr)
8188 %{
8189 match(Set dst (AbsI src));
8190 effect(TEMP dst, TEMP tmp, KILL cr);
8191 format %{ "movl $tmp, $src\n\t"
8192 "sarl $tmp, 31\n\t"
8193 "movl $dst, $src\n\t"
8194 "xorl $dst, $tmp\n\t"
8195 "subl $dst, $tmp\n"
8196 %}
8197 ins_encode %{
8198 __ movl($tmp$$Register, $src$$Register);
8199 __ sarl($tmp$$Register, 31);
8200 __ movl($dst$$Register, $src$$Register);
8201 __ xorl($dst$$Register, $tmp$$Register);
8202 __ subl($dst$$Register, $tmp$$Register);
8203 %}
8204
8205 ins_pipe(ialu_reg_reg);
8206 %}
8207
8208 // Long Absolute Instructions
8209 instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr)
8210 %{
8211 match(Set dst (AbsL src));
8212 effect(TEMP dst, TEMP tmp, KILL cr);
8213 format %{ "movq $tmp, $src\n\t"
8214 "sarq $tmp, 63\n\t"
8215 "movq $dst, $src\n\t"
8216 "xorq $dst, $tmp\n\t"
8217 "subq $dst, $tmp\n"
8218 %}
8219 ins_encode %{
8220 __ movq($tmp$$Register, $src$$Register);
8221 __ sarq($tmp$$Register, 63);
8222 __ movq($dst$$Register, $src$$Register);
8223 __ xorq($dst$$Register, $tmp$$Register);
8224 __ subq($dst$$Register, $tmp$$Register);
8225 %}
8226
8227 ins_pipe(ialu_reg_reg);
8228 %}
8229
8230 //----------Subtraction Instructions-------------------------------------------
8231
8232 // Integer Subtraction Instructions
8233 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8234 %{
8235 match(Set dst (SubI dst src));
8236 effect(KILL cr);
8237
8238 format %{ "subl $dst, $src\t# int" %}
8239 opcode(0x2B);
8240 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8241 ins_pipe(ialu_reg_reg);
8242 %}
8243
8244 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8245 %{
8246 match(Set dst (SubI dst src));
8247 effect(KILL cr);
8248
8249 format %{ "subl $dst, $src\t# int" %}
8250 opcode(0x81, 0x05); /* Opcode 81 /5 */
8251 ins_encode(OpcSErm(dst, src), Con8or32(src));
8252 ins_pipe(ialu_reg);
8253 %}
8254
8255 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8256 %{
8257 match(Set dst (SubI dst (LoadI src)));
8258 effect(KILL cr);
8259
8260 ins_cost(125);
8261 format %{ "subl $dst, $src\t# int" %}
8262 opcode(0x2B);
8263 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8264 ins_pipe(ialu_reg_mem);
8265 %}
8266
8267 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8268 %{
8269 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8270 effect(KILL cr);
8271
8272 ins_cost(150);
8273 format %{ "subl $dst, $src\t# int" %}
8274 opcode(0x29); /* Opcode 29 /r */
8275 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8276 ins_pipe(ialu_mem_reg);
8277 %}
8278
8279 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8280 %{
8281 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8282 effect(KILL cr);
8283
8284 ins_cost(125); // XXX
8285 format %{ "subl $dst, $src\t# int" %}
8286 opcode(0x81); /* Opcode 81 /5 id */
8287 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8288 ins_pipe(ialu_mem_imm);
8289 %}
8290
8291 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8292 %{
8293 match(Set dst (SubL dst src));
8294 effect(KILL cr);
8295
8296 format %{ "subq $dst, $src\t# long" %}
8297 opcode(0x2B);
8298 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8299 ins_pipe(ialu_reg_reg);
8300 %}
8301
8302 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8303 %{
8304 match(Set dst (SubL dst src));
8305 effect(KILL cr);
8306
8307 format %{ "subq $dst, $src\t# long" %}
8308 opcode(0x81, 0x05); /* Opcode 81 /5 */
8309 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8310 ins_pipe(ialu_reg);
8311 %}
8312
8313 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8314 %{
8315 match(Set dst (SubL dst (LoadL src)));
8316 effect(KILL cr);
8317
8318 ins_cost(125);
8319 format %{ "subq $dst, $src\t# long" %}
8320 opcode(0x2B);
8321 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8322 ins_pipe(ialu_reg_mem);
8323 %}
8324
8325 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8326 %{
8327 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8328 effect(KILL cr);
8329
8330 ins_cost(150);
8331 format %{ "subq $dst, $src\t# long" %}
8332 opcode(0x29); /* Opcode 29 /r */
8333 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8334 ins_pipe(ialu_mem_reg);
8335 %}
8336
8337 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8338 %{
8339 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8340 effect(KILL cr);
8341
8342 ins_cost(125); // XXX
8343 format %{ "subq $dst, $src\t# long" %}
8344 opcode(0x81); /* Opcode 81 /5 id */
8345 ins_encode(REX_mem_wide(dst),
8346 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8347 ins_pipe(ialu_mem_imm);
8348 %}
8349
8350 // Subtract from a pointer
8351 // XXX hmpf???
8352 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8353 %{
8354 match(Set dst (AddP dst (SubI zero src)));
8355 effect(KILL cr);
8356
8357 format %{ "subq $dst, $src\t# ptr - int" %}
8358 opcode(0x2B);
8359 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8360 ins_pipe(ialu_reg_reg);
8361 %}
8362
8363 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8364 %{
8365 match(Set dst (SubI zero dst));
8366 effect(KILL cr);
8367
8368 format %{ "negl $dst\t# int" %}
8369 opcode(0xF7, 0x03); // Opcode F7 /3
8370 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8371 ins_pipe(ialu_reg);
8372 %}
8373
8374 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8375 %{
8376 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8377 effect(KILL cr);
8378
8379 format %{ "negl $dst\t# int" %}
8380 opcode(0xF7, 0x03); // Opcode F7 /3
8381 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8382 ins_pipe(ialu_reg);
8383 %}
8384
8385 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8386 %{
8387 match(Set dst (SubL zero dst));
8388 effect(KILL cr);
8389
8390 format %{ "negq $dst\t# long" %}
8391 opcode(0xF7, 0x03); // Opcode F7 /3
8392 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8393 ins_pipe(ialu_reg);
8394 %}
8395
8396 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8397 %{
8398 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8399 effect(KILL cr);
8400
8401 format %{ "negq $dst\t# long" %}
8402 opcode(0xF7, 0x03); // Opcode F7 /3
8403 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8404 ins_pipe(ialu_reg);
8405 %}
8406
8407 //----------Multiplication/Division Instructions-------------------------------
8408 // Integer Multiplication Instructions
8409 // Multiply Register
8410
8411 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8412 %{
8413 match(Set dst (MulI dst src));
8414 effect(KILL cr);
8415
8416 ins_cost(300);
8417 format %{ "imull $dst, $src\t# int" %}
8418 opcode(0x0F, 0xAF);
8419 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8420 ins_pipe(ialu_reg_reg_alu0);
8421 %}
8422
8423 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8424 %{
8425 match(Set dst (MulI src imm));
8426 effect(KILL cr);
8427
8428 ins_cost(300);
8429 format %{ "imull $dst, $src, $imm\t# int" %}
8430 opcode(0x69); /* 69 /r id */
8431 ins_encode(REX_reg_reg(dst, src),
8432 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8433 ins_pipe(ialu_reg_reg_alu0);
8434 %}
8435
8436 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8437 %{
8438 match(Set dst (MulI dst (LoadI src)));
8439 effect(KILL cr);
8440
8441 ins_cost(350);
8442 format %{ "imull $dst, $src\t# int" %}
8443 opcode(0x0F, 0xAF);
8444 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8445 ins_pipe(ialu_reg_mem_alu0);
8446 %}
8447
8448 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8449 %{
8450 match(Set dst (MulI (LoadI src) imm));
8451 effect(KILL cr);
8452
8453 ins_cost(300);
8454 format %{ "imull $dst, $src, $imm\t# int" %}
8455 opcode(0x69); /* 69 /r id */
8456 ins_encode(REX_reg_mem(dst, src),
8457 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8458 ins_pipe(ialu_reg_mem_alu0);
8459 %}
8460
8461 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8462 %{
8463 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8464 effect(KILL cr, KILL src2);
8465
8466 expand %{ mulI_rReg(dst, src1, cr);
8467 mulI_rReg(src2, src3, cr);
8468 addI_rReg(dst, src2, cr); %}
8469 %}
8470
8471 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8472 %{
8473 match(Set dst (MulL dst src));
8474 effect(KILL cr);
8475
8476 ins_cost(300);
8477 format %{ "imulq $dst, $src\t# long" %}
8478 opcode(0x0F, 0xAF);
8479 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8480 ins_pipe(ialu_reg_reg_alu0);
8481 %}
8482
8483 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8484 %{
8485 match(Set dst (MulL src imm));
8486 effect(KILL cr);
8487
8488 ins_cost(300);
8489 format %{ "imulq $dst, $src, $imm\t# long" %}
8490 opcode(0x69); /* 69 /r id */
8491 ins_encode(REX_reg_reg_wide(dst, src),
8492 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8493 ins_pipe(ialu_reg_reg_alu0);
8494 %}
8495
8496 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8497 %{
8498 match(Set dst (MulL dst (LoadL src)));
8499 effect(KILL cr);
8500
8501 ins_cost(350);
8502 format %{ "imulq $dst, $src\t# long" %}
8503 opcode(0x0F, 0xAF);
8504 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8505 ins_pipe(ialu_reg_mem_alu0);
8506 %}
8507
8508 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8509 %{
8510 match(Set dst (MulL (LoadL src) imm));
8511 effect(KILL cr);
8512
8513 ins_cost(300);
8514 format %{ "imulq $dst, $src, $imm\t# long" %}
8515 opcode(0x69); /* 69 /r id */
8516 ins_encode(REX_reg_mem_wide(dst, src),
8517 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8518 ins_pipe(ialu_reg_mem_alu0);
8519 %}
8520
8521 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8522 %{
8523 match(Set dst (MulHiL src rax));
8524 effect(USE_KILL rax, KILL cr);
8525
8526 ins_cost(300);
8527 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8528 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8529 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8530 ins_pipe(ialu_reg_reg_alu0);
8531 %}
8532
8533 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8534 rFlagsReg cr)
8535 %{
8536 match(Set rax (DivI rax div));
8537 effect(KILL rdx, KILL cr);
8538
8539 ins_cost(30*100+10*100); // XXX
8540 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8541 "jne,s normal\n\t"
8542 "xorl rdx, rdx\n\t"
8543 "cmpl $div, -1\n\t"
8544 "je,s done\n"
8545 "normal: cdql\n\t"
8546 "idivl $div\n"
8547 "done:" %}
8548 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8549 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8550 ins_pipe(ialu_reg_reg_alu0);
8551 %}
8552
8553 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8554 rFlagsReg cr)
8555 %{
8556 match(Set rax (DivL rax div));
8557 effect(KILL rdx, KILL cr);
8558
8559 ins_cost(30*100+10*100); // XXX
8560 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8561 "cmpq rax, rdx\n\t"
8562 "jne,s normal\n\t"
8563 "xorl rdx, rdx\n\t"
8564 "cmpq $div, -1\n\t"
8565 "je,s done\n"
8566 "normal: cdqq\n\t"
8567 "idivq $div\n"
8568 "done:" %}
8569 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8570 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8571 ins_pipe(ialu_reg_reg_alu0);
8572 %}
8573
8574 // Integer DIVMOD with Register, both quotient and mod results
8575 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8576 rFlagsReg cr)
8577 %{
8578 match(DivModI rax div);
8579 effect(KILL cr);
8580
8581 ins_cost(30*100+10*100); // XXX
8582 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8583 "jne,s normal\n\t"
8584 "xorl rdx, rdx\n\t"
8585 "cmpl $div, -1\n\t"
8586 "je,s done\n"
8587 "normal: cdql\n\t"
8588 "idivl $div\n"
8589 "done:" %}
8590 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8591 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8592 ins_pipe(pipe_slow);
8593 %}
8594
8595 // Long DIVMOD with Register, both quotient and mod results
8596 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8597 rFlagsReg cr)
8598 %{
8599 match(DivModL rax div);
8600 effect(KILL cr);
8601
8602 ins_cost(30*100+10*100); // XXX
8603 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8604 "cmpq rax, rdx\n\t"
8605 "jne,s normal\n\t"
8606 "xorl rdx, rdx\n\t"
8607 "cmpq $div, -1\n\t"
8608 "je,s done\n"
8609 "normal: cdqq\n\t"
8610 "idivq $div\n"
8611 "done:" %}
8612 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8613 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8614 ins_pipe(pipe_slow);
8615 %}
8616
8617 //----------- DivL-By-Constant-Expansions--------------------------------------
8618 // DivI cases are handled by the compiler
8619
8620 // Magic constant, reciprocal of 10
8621 instruct loadConL_0x6666666666666667(rRegL dst)
8622 %{
8623 effect(DEF dst);
8624
8625 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8626 ins_encode(load_immL(dst, 0x6666666666666667));
8627 ins_pipe(ialu_reg);
8628 %}
8629
8630 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8631 %{
8632 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8633
8634 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8635 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8636 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8637 ins_pipe(ialu_reg_reg_alu0);
8638 %}
8639
8640 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8641 %{
8642 effect(USE_DEF dst, KILL cr);
8643
8644 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8645 opcode(0xC1, 0x7); /* C1 /7 ib */
8646 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8647 ins_pipe(ialu_reg);
8648 %}
8649
8650 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8651 %{
8652 effect(USE_DEF dst, KILL cr);
8653
8654 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8655 opcode(0xC1, 0x7); /* C1 /7 ib */
8656 ins_encode(reg_opc_imm_wide(dst, 0x2));
8657 ins_pipe(ialu_reg);
8658 %}
8659
8660 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8661 %{
8662 match(Set dst (DivL src div));
8663
8664 ins_cost((5+8)*100);
8665 expand %{
8666 rax_RegL rax; // Killed temp
8667 rFlagsReg cr; // Killed
8668 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8669 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8670 sarL_rReg_63(src, cr); // sarq src, 63
8671 sarL_rReg_2(dst, cr); // sarq rdx, 2
8672 subL_rReg(dst, src, cr); // subl rdx, src
8673 %}
8674 %}
8675
8676 //-----------------------------------------------------------------------------
8677
8678 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8679 rFlagsReg cr)
8680 %{
8681 match(Set rdx (ModI rax div));
8682 effect(KILL rax, KILL cr);
8683
8684 ins_cost(300); // XXX
8685 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8686 "jne,s normal\n\t"
8687 "xorl rdx, rdx\n\t"
8688 "cmpl $div, -1\n\t"
8689 "je,s done\n"
8690 "normal: cdql\n\t"
8691 "idivl $div\n"
8692 "done:" %}
8693 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8694 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8695 ins_pipe(ialu_reg_reg_alu0);
8696 %}
8697
8698 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8699 rFlagsReg cr)
8700 %{
8701 match(Set rdx (ModL rax div));
8702 effect(KILL rax, KILL cr);
8703
8704 ins_cost(300); // XXX
8705 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8706 "cmpq rax, rdx\n\t"
8707 "jne,s normal\n\t"
8708 "xorl rdx, rdx\n\t"
8709 "cmpq $div, -1\n\t"
8710 "je,s done\n"
8711 "normal: cdqq\n\t"
8712 "idivq $div\n"
8713 "done:" %}
8714 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8715 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8716 ins_pipe(ialu_reg_reg_alu0);
8717 %}
8718
8719 // Integer Shift Instructions
8720 // Shift Left by one
8721 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8722 %{
8723 match(Set dst (LShiftI dst shift));
8724 effect(KILL cr);
8725
8726 format %{ "sall $dst, $shift" %}
8727 opcode(0xD1, 0x4); /* D1 /4 */
8728 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8729 ins_pipe(ialu_reg);
8730 %}
8731
8732 // Shift Left by one
8733 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8734 %{
8735 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8736 effect(KILL cr);
8737
8738 format %{ "sall $dst, $shift\t" %}
8739 opcode(0xD1, 0x4); /* D1 /4 */
8740 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8741 ins_pipe(ialu_mem_imm);
8742 %}
8743
8744 // Shift Left by 8-bit immediate
8745 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8746 %{
8747 match(Set dst (LShiftI dst shift));
8748 effect(KILL cr);
8749
8750 format %{ "sall $dst, $shift" %}
8751 opcode(0xC1, 0x4); /* C1 /4 ib */
8752 ins_encode(reg_opc_imm(dst, shift));
8753 ins_pipe(ialu_reg);
8754 %}
8755
8756 // Shift Left by 8-bit immediate
8757 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8758 %{
8759 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8760 effect(KILL cr);
8761
8762 format %{ "sall $dst, $shift" %}
8763 opcode(0xC1, 0x4); /* C1 /4 ib */
8764 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8765 ins_pipe(ialu_mem_imm);
8766 %}
8767
8768 // Shift Left by variable
8769 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8770 %{
8771 match(Set dst (LShiftI dst shift));
8772 effect(KILL cr);
8773
8774 format %{ "sall $dst, $shift" %}
8775 opcode(0xD3, 0x4); /* D3 /4 */
8776 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8777 ins_pipe(ialu_reg_reg);
8778 %}
8779
8780 // Shift Left by variable
8781 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8782 %{
8783 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8784 effect(KILL cr);
8785
8786 format %{ "sall $dst, $shift" %}
8787 opcode(0xD3, 0x4); /* D3 /4 */
8788 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8789 ins_pipe(ialu_mem_reg);
8790 %}
8791
8792 // Arithmetic shift right by one
8793 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8794 %{
8795 match(Set dst (RShiftI dst shift));
8796 effect(KILL cr);
8797
8798 format %{ "sarl $dst, $shift" %}
8799 opcode(0xD1, 0x7); /* D1 /7 */
8800 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8801 ins_pipe(ialu_reg);
8802 %}
8803
8804 // Arithmetic shift right by one
8805 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8806 %{
8807 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8808 effect(KILL cr);
8809
8810 format %{ "sarl $dst, $shift" %}
8811 opcode(0xD1, 0x7); /* D1 /7 */
8812 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8813 ins_pipe(ialu_mem_imm);
8814 %}
8815
8816 // Arithmetic Shift Right by 8-bit immediate
8817 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8818 %{
8819 match(Set dst (RShiftI dst shift));
8820 effect(KILL cr);
8821
8822 format %{ "sarl $dst, $shift" %}
8823 opcode(0xC1, 0x7); /* C1 /7 ib */
8824 ins_encode(reg_opc_imm(dst, shift));
8825 ins_pipe(ialu_mem_imm);
8826 %}
8827
8828 // Arithmetic Shift Right by 8-bit immediate
8829 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8830 %{
8831 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8832 effect(KILL cr);
8833
8834 format %{ "sarl $dst, $shift" %}
8835 opcode(0xC1, 0x7); /* C1 /7 ib */
8836 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8837 ins_pipe(ialu_mem_imm);
8838 %}
8839
8840 // Arithmetic Shift Right by variable
8841 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8842 %{
8843 match(Set dst (RShiftI dst shift));
8844 effect(KILL cr);
8845
8846 format %{ "sarl $dst, $shift" %}
8847 opcode(0xD3, 0x7); /* D3 /7 */
8848 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8849 ins_pipe(ialu_reg_reg);
8850 %}
8851
8852 // Arithmetic Shift Right by variable
8853 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8854 %{
8855 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8856 effect(KILL cr);
8857
8858 format %{ "sarl $dst, $shift" %}
8859 opcode(0xD3, 0x7); /* D3 /7 */
8860 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8861 ins_pipe(ialu_mem_reg);
8862 %}
8863
8864 // Logical shift right by one
8865 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8866 %{
8867 match(Set dst (URShiftI dst shift));
8868 effect(KILL cr);
8869
8870 format %{ "shrl $dst, $shift" %}
8871 opcode(0xD1, 0x5); /* D1 /5 */
8872 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8873 ins_pipe(ialu_reg);
8874 %}
8875
8876 // Logical shift right by one
8877 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8878 %{
8879 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8880 effect(KILL cr);
8881
8882 format %{ "shrl $dst, $shift" %}
8883 opcode(0xD1, 0x5); /* D1 /5 */
8884 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8885 ins_pipe(ialu_mem_imm);
8886 %}
8887
8888 // Logical Shift Right by 8-bit immediate
8889 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8890 %{
8891 match(Set dst (URShiftI dst shift));
8892 effect(KILL cr);
8893
8894 format %{ "shrl $dst, $shift" %}
8895 opcode(0xC1, 0x5); /* C1 /5 ib */
8896 ins_encode(reg_opc_imm(dst, shift));
8897 ins_pipe(ialu_reg);
8898 %}
8899
8900 // Logical Shift Right by 8-bit immediate
8901 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8902 %{
8903 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8904 effect(KILL cr);
8905
8906 format %{ "shrl $dst, $shift" %}
8907 opcode(0xC1, 0x5); /* C1 /5 ib */
8908 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8909 ins_pipe(ialu_mem_imm);
8910 %}
8911
8912 // Logical Shift Right by variable
8913 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8914 %{
8915 match(Set dst (URShiftI dst shift));
8916 effect(KILL cr);
8917
8918 format %{ "shrl $dst, $shift" %}
8919 opcode(0xD3, 0x5); /* D3 /5 */
8920 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8921 ins_pipe(ialu_reg_reg);
8922 %}
8923
8924 // Logical Shift Right by variable
8925 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8926 %{
8927 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8928 effect(KILL cr);
8929
8930 format %{ "shrl $dst, $shift" %}
8931 opcode(0xD3, 0x5); /* D3 /5 */
8932 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8933 ins_pipe(ialu_mem_reg);
8934 %}
8935
8936 // Long Shift Instructions
8937 // Shift Left by one
8938 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8939 %{
8940 match(Set dst (LShiftL dst shift));
8941 effect(KILL cr);
8942
8943 format %{ "salq $dst, $shift" %}
8944 opcode(0xD1, 0x4); /* D1 /4 */
8945 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8946 ins_pipe(ialu_reg);
8947 %}
8948
8949 // Shift Left by one
8950 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8951 %{
8952 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8953 effect(KILL cr);
8954
8955 format %{ "salq $dst, $shift" %}
8956 opcode(0xD1, 0x4); /* D1 /4 */
8957 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8958 ins_pipe(ialu_mem_imm);
8959 %}
8960
8961 // Shift Left by 8-bit immediate
8962 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8963 %{
8964 match(Set dst (LShiftL dst shift));
8965 effect(KILL cr);
8966
8967 format %{ "salq $dst, $shift" %}
8968 opcode(0xC1, 0x4); /* C1 /4 ib */
8969 ins_encode(reg_opc_imm_wide(dst, shift));
8970 ins_pipe(ialu_reg);
8971 %}
8972
8973 // Shift Left by 8-bit immediate
8974 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8975 %{
8976 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8977 effect(KILL cr);
8978
8979 format %{ "salq $dst, $shift" %}
8980 opcode(0xC1, 0x4); /* C1 /4 ib */
8981 ins_encode(REX_mem_wide(dst), OpcP,
8982 RM_opc_mem(secondary, dst), Con8or32(shift));
8983 ins_pipe(ialu_mem_imm);
8984 %}
8985
8986 // Shift Left by variable
8987 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8988 %{
8989 match(Set dst (LShiftL dst shift));
8990 effect(KILL cr);
8991
8992 format %{ "salq $dst, $shift" %}
8993 opcode(0xD3, 0x4); /* D3 /4 */
8994 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8995 ins_pipe(ialu_reg_reg);
8996 %}
8997
8998 // Shift Left by variable
8999 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9000 %{
9001 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9002 effect(KILL cr);
9003
9004 format %{ "salq $dst, $shift" %}
9005 opcode(0xD3, 0x4); /* D3 /4 */
9006 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9007 ins_pipe(ialu_mem_reg);
9008 %}
9009
9010 // Arithmetic shift right by one
9011 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9012 %{
9013 match(Set dst (RShiftL dst shift));
9014 effect(KILL cr);
9015
9016 format %{ "sarq $dst, $shift" %}
9017 opcode(0xD1, 0x7); /* D1 /7 */
9018 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9019 ins_pipe(ialu_reg);
9020 %}
9021
9022 // Arithmetic shift right by one
9023 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9024 %{
9025 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9026 effect(KILL cr);
9027
9028 format %{ "sarq $dst, $shift" %}
9029 opcode(0xD1, 0x7); /* D1 /7 */
9030 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9031 ins_pipe(ialu_mem_imm);
9032 %}
9033
9034 // Arithmetic Shift Right by 8-bit immediate
9035 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9036 %{
9037 match(Set dst (RShiftL dst shift));
9038 effect(KILL cr);
9039
9040 format %{ "sarq $dst, $shift" %}
9041 opcode(0xC1, 0x7); /* C1 /7 ib */
9042 ins_encode(reg_opc_imm_wide(dst, shift));
9043 ins_pipe(ialu_mem_imm);
9044 %}
9045
9046 // Arithmetic Shift Right by 8-bit immediate
9047 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9048 %{
9049 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9050 effect(KILL cr);
9051
9052 format %{ "sarq $dst, $shift" %}
9053 opcode(0xC1, 0x7); /* C1 /7 ib */
9054 ins_encode(REX_mem_wide(dst), OpcP,
9055 RM_opc_mem(secondary, dst), Con8or32(shift));
9056 ins_pipe(ialu_mem_imm);
9057 %}
9058
9059 // Arithmetic Shift Right by variable
9060 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9061 %{
9062 match(Set dst (RShiftL dst shift));
9063 effect(KILL cr);
9064
9065 format %{ "sarq $dst, $shift" %}
9066 opcode(0xD3, 0x7); /* D3 /7 */
9067 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9068 ins_pipe(ialu_reg_reg);
9069 %}
9070
9071 // Arithmetic Shift Right by variable
9072 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9073 %{
9074 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9075 effect(KILL cr);
9076
9077 format %{ "sarq $dst, $shift" %}
9078 opcode(0xD3, 0x7); /* D3 /7 */
9079 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9080 ins_pipe(ialu_mem_reg);
9081 %}
9082
9083 // Logical shift right by one
9084 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9085 %{
9086 match(Set dst (URShiftL dst shift));
9087 effect(KILL cr);
9088
9089 format %{ "shrq $dst, $shift" %}
9090 opcode(0xD1, 0x5); /* D1 /5 */
9091 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
9092 ins_pipe(ialu_reg);
9093 %}
9094
9095 // Logical shift right by one
9096 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9097 %{
9098 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9099 effect(KILL cr);
9100
9101 format %{ "shrq $dst, $shift" %}
9102 opcode(0xD1, 0x5); /* D1 /5 */
9103 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9104 ins_pipe(ialu_mem_imm);
9105 %}
9106
9107 // Logical Shift Right by 8-bit immediate
9108 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9109 %{
9110 match(Set dst (URShiftL dst shift));
9111 effect(KILL cr);
9112
9113 format %{ "shrq $dst, $shift" %}
9114 opcode(0xC1, 0x5); /* C1 /5 ib */
9115 ins_encode(reg_opc_imm_wide(dst, shift));
9116 ins_pipe(ialu_reg);
9117 %}
9118
9119
9120 // Logical Shift Right by 8-bit immediate
9121 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9122 %{
9123 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9124 effect(KILL cr);
9125
9126 format %{ "shrq $dst, $shift" %}
9127 opcode(0xC1, 0x5); /* C1 /5 ib */
9128 ins_encode(REX_mem_wide(dst), OpcP,
9129 RM_opc_mem(secondary, dst), Con8or32(shift));
9130 ins_pipe(ialu_mem_imm);
9131 %}
9132
9133 // Logical Shift Right by variable
9134 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9135 %{
9136 match(Set dst (URShiftL dst shift));
9137 effect(KILL cr);
9138
9139 format %{ "shrq $dst, $shift" %}
9140 opcode(0xD3, 0x5); /* D3 /5 */
9141 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9142 ins_pipe(ialu_reg_reg);
9143 %}
9144
9145 // Logical Shift Right by variable
9146 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9147 %{
9148 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9149 effect(KILL cr);
9150
9151 format %{ "shrq $dst, $shift" %}
9152 opcode(0xD3, 0x5); /* D3 /5 */
9153 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9154 ins_pipe(ialu_mem_reg);
9155 %}
9156
9157 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9158 // This idiom is used by the compiler for the i2b bytecode.
9159 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9160 %{
9161 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9162
9163 format %{ "movsbl $dst, $src\t# i2b" %}
9164 opcode(0x0F, 0xBE);
9165 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9166 ins_pipe(ialu_reg_reg);
9167 %}
9168
9169 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9170 // This idiom is used by the compiler the i2s bytecode.
9171 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9172 %{
9173 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9174
9175 format %{ "movswl $dst, $src\t# i2s" %}
9176 opcode(0x0F, 0xBF);
9177 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9178 ins_pipe(ialu_reg_reg);
9179 %}
9180
9181 // ROL/ROR instructions
9182
9183 // ROL expand
9184 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9185 effect(KILL cr, USE_DEF dst);
9186
9187 format %{ "roll $dst" %}
9188 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9189 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9190 ins_pipe(ialu_reg);
9191 %}
9192
9193 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9194 effect(USE_DEF dst, USE shift, KILL cr);
9195
9196 format %{ "roll $dst, $shift" %}
9197 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9198 ins_encode( reg_opc_imm(dst, shift) );
9199 ins_pipe(ialu_reg);
9200 %}
9201
9202 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9203 %{
9204 effect(USE_DEF dst, USE shift, KILL cr);
9205
9206 format %{ "roll $dst, $shift" %}
9207 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9208 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9209 ins_pipe(ialu_reg_reg);
9210 %}
9211 // end of ROL expand
9212
9213 // Rotate Left by one
9214 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9215 %{
9216 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9217
9218 expand %{
9219 rolI_rReg_imm1(dst, cr);
9220 %}
9221 %}
9222
9223 // Rotate Left by 8-bit immediate
9224 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9225 %{
9226 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9227 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9228
9229 expand %{
9230 rolI_rReg_imm8(dst, lshift, cr);
9231 %}
9232 %}
9233
9234 // Rotate Left by variable
9235 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9236 %{
9237 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9238
9239 expand %{
9240 rolI_rReg_CL(dst, shift, cr);
9241 %}
9242 %}
9243
9244 // Rotate Left by variable
9245 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9246 %{
9247 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9248
9249 expand %{
9250 rolI_rReg_CL(dst, shift, cr);
9251 %}
9252 %}
9253
9254 // ROR expand
9255 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9256 %{
9257 effect(USE_DEF dst, KILL cr);
9258
9259 format %{ "rorl $dst" %}
9260 opcode(0xD1, 0x1); /* D1 /1 */
9261 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9262 ins_pipe(ialu_reg);
9263 %}
9264
9265 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9266 %{
9267 effect(USE_DEF dst, USE shift, KILL cr);
9268
9269 format %{ "rorl $dst, $shift" %}
9270 opcode(0xC1, 0x1); /* C1 /1 ib */
9271 ins_encode(reg_opc_imm(dst, shift));
9272 ins_pipe(ialu_reg);
9273 %}
9274
9275 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9276 %{
9277 effect(USE_DEF dst, USE shift, KILL cr);
9278
9279 format %{ "rorl $dst, $shift" %}
9280 opcode(0xD3, 0x1); /* D3 /1 */
9281 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9282 ins_pipe(ialu_reg_reg);
9283 %}
9284 // end of ROR expand
9285
9286 // Rotate Right by one
9287 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9288 %{
9289 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9290
9291 expand %{
9292 rorI_rReg_imm1(dst, cr);
9293 %}
9294 %}
9295
9296 // Rotate Right by 8-bit immediate
9297 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9298 %{
9299 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9300 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9301
9302 expand %{
9303 rorI_rReg_imm8(dst, rshift, cr);
9304 %}
9305 %}
9306
9307 // Rotate Right by variable
9308 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9309 %{
9310 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9311
9312 expand %{
9313 rorI_rReg_CL(dst, shift, cr);
9314 %}
9315 %}
9316
9317 // Rotate Right by variable
9318 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9319 %{
9320 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9321
9322 expand %{
9323 rorI_rReg_CL(dst, shift, cr);
9324 %}
9325 %}
9326
9327 // for long rotate
9328 // ROL expand
9329 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9330 effect(USE_DEF dst, KILL cr);
9331
9332 format %{ "rolq $dst" %}
9333 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9334 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9335 ins_pipe(ialu_reg);
9336 %}
9337
9338 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9339 effect(USE_DEF dst, USE shift, KILL cr);
9340
9341 format %{ "rolq $dst, $shift" %}
9342 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9343 ins_encode( reg_opc_imm_wide(dst, shift) );
9344 ins_pipe(ialu_reg);
9345 %}
9346
9347 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9348 %{
9349 effect(USE_DEF dst, USE shift, KILL cr);
9350
9351 format %{ "rolq $dst, $shift" %}
9352 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9353 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9354 ins_pipe(ialu_reg_reg);
9355 %}
9356 // end of ROL expand
9357
9358 // Rotate Left by one
9359 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9360 %{
9361 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9362
9363 expand %{
9364 rolL_rReg_imm1(dst, cr);
9365 %}
9366 %}
9367
9368 // Rotate Left by 8-bit immediate
9369 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9370 %{
9371 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9372 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9373
9374 expand %{
9375 rolL_rReg_imm8(dst, lshift, cr);
9376 %}
9377 %}
9378
9379 // Rotate Left by variable
9380 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9381 %{
9382 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9383
9384 expand %{
9385 rolL_rReg_CL(dst, shift, cr);
9386 %}
9387 %}
9388
9389 // Rotate Left by variable
9390 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9391 %{
9392 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9393
9394 expand %{
9395 rolL_rReg_CL(dst, shift, cr);
9396 %}
9397 %}
9398
9399 // ROR expand
9400 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9401 %{
9402 effect(USE_DEF dst, KILL cr);
9403
9404 format %{ "rorq $dst" %}
9405 opcode(0xD1, 0x1); /* D1 /1 */
9406 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9407 ins_pipe(ialu_reg);
9408 %}
9409
9410 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9411 %{
9412 effect(USE_DEF dst, USE shift, KILL cr);
9413
9414 format %{ "rorq $dst, $shift" %}
9415 opcode(0xC1, 0x1); /* C1 /1 ib */
9416 ins_encode(reg_opc_imm_wide(dst, shift));
9417 ins_pipe(ialu_reg);
9418 %}
9419
9420 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9421 %{
9422 effect(USE_DEF dst, USE shift, KILL cr);
9423
9424 format %{ "rorq $dst, $shift" %}
9425 opcode(0xD3, 0x1); /* D3 /1 */
9426 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9427 ins_pipe(ialu_reg_reg);
9428 %}
9429 // end of ROR expand
9430
9431 // Rotate Right by one
9432 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9433 %{
9434 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9435
9436 expand %{
9437 rorL_rReg_imm1(dst, cr);
9438 %}
9439 %}
9440
9441 // Rotate Right by 8-bit immediate
9442 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9443 %{
9444 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9445 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9446
9447 expand %{
9448 rorL_rReg_imm8(dst, rshift, cr);
9449 %}
9450 %}
9451
9452 // Rotate Right by variable
9453 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9454 %{
9455 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9456
9457 expand %{
9458 rorL_rReg_CL(dst, shift, cr);
9459 %}
9460 %}
9461
9462 // Rotate Right by variable
9463 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9464 %{
9465 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9466
9467 expand %{
9468 rorL_rReg_CL(dst, shift, cr);
9469 %}
9470 %}
9471
9472 // Logical Instructions
9473
9474 // Integer Logical Instructions
9475
9476 // And Instructions
9477 // And Register with Register
9478 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9479 %{
9480 match(Set dst (AndI dst src));
9481 effect(KILL cr);
9482
9483 format %{ "andl $dst, $src\t# int" %}
9484 opcode(0x23);
9485 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9486 ins_pipe(ialu_reg_reg);
9487 %}
9488
9489 // And Register with Immediate 255
9490 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9491 %{
9492 match(Set dst (AndI dst src));
9493
9494 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9495 opcode(0x0F, 0xB6);
9496 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9497 ins_pipe(ialu_reg);
9498 %}
9499
9500 // And Register with Immediate 255 and promote to long
9501 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9502 %{
9503 match(Set dst (ConvI2L (AndI src mask)));
9504
9505 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9506 opcode(0x0F, 0xB6);
9507 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9508 ins_pipe(ialu_reg);
9509 %}
9510
9511 // And Register with Immediate 65535
9512 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9513 %{
9514 match(Set dst (AndI dst src));
9515
9516 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9517 opcode(0x0F, 0xB7);
9518 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9519 ins_pipe(ialu_reg);
9520 %}
9521
9522 // And Register with Immediate 65535 and promote to long
9523 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9524 %{
9525 match(Set dst (ConvI2L (AndI src mask)));
9526
9527 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9528 opcode(0x0F, 0xB7);
9529 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9530 ins_pipe(ialu_reg);
9531 %}
9532
9533 // And Register with Immediate
9534 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9535 %{
9536 match(Set dst (AndI dst src));
9537 effect(KILL cr);
9538
9539 format %{ "andl $dst, $src\t# int" %}
9540 opcode(0x81, 0x04); /* Opcode 81 /4 */
9541 ins_encode(OpcSErm(dst, src), Con8or32(src));
9542 ins_pipe(ialu_reg);
9543 %}
9544
9545 // And Register with Memory
9546 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9547 %{
9548 match(Set dst (AndI dst (LoadI src)));
9549 effect(KILL cr);
9550
9551 ins_cost(125);
9552 format %{ "andl $dst, $src\t# int" %}
9553 opcode(0x23);
9554 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9555 ins_pipe(ialu_reg_mem);
9556 %}
9557
9558 // And Memory with Register
9559 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9560 %{
9561 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9562 effect(KILL cr);
9563
9564 ins_cost(150);
9565 format %{ "andb $dst, $src\t# byte" %}
9566 opcode(0x20);
9567 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9568 ins_pipe(ialu_mem_reg);
9569 %}
9570
9571 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9572 %{
9573 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9574 effect(KILL cr);
9575
9576 ins_cost(150);
9577 format %{ "andl $dst, $src\t# int" %}
9578 opcode(0x21); /* Opcode 21 /r */
9579 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9580 ins_pipe(ialu_mem_reg);
9581 %}
9582
9583 // And Memory with Immediate
9584 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9585 %{
9586 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9587 effect(KILL cr);
9588
9589 ins_cost(125);
9590 format %{ "andl $dst, $src\t# int" %}
9591 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9592 ins_encode(REX_mem(dst), OpcSE(src),
9593 RM_opc_mem(secondary, dst), Con8or32(src));
9594 ins_pipe(ialu_mem_imm);
9595 %}
9596
9597 // BMI1 instructions
9598 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9599 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9600 predicate(UseBMI1Instructions);
9601 effect(KILL cr);
9602
9603 ins_cost(125);
9604 format %{ "andnl $dst, $src1, $src2" %}
9605
9606 ins_encode %{
9607 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9608 %}
9609 ins_pipe(ialu_reg_mem);
9610 %}
9611
9612 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9613 match(Set dst (AndI (XorI src1 minus_1) src2));
9614 predicate(UseBMI1Instructions);
9615 effect(KILL cr);
9616
9617 format %{ "andnl $dst, $src1, $src2" %}
9618
9619 ins_encode %{
9620 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9621 %}
9622 ins_pipe(ialu_reg);
9623 %}
9624
9625 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9626 match(Set dst (AndI (SubI imm_zero src) src));
9627 predicate(UseBMI1Instructions);
9628 effect(KILL cr);
9629
9630 format %{ "blsil $dst, $src" %}
9631
9632 ins_encode %{
9633 __ blsil($dst$$Register, $src$$Register);
9634 %}
9635 ins_pipe(ialu_reg);
9636 %}
9637
9638 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9639 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9640 predicate(UseBMI1Instructions);
9641 effect(KILL cr);
9642
9643 ins_cost(125);
9644 format %{ "blsil $dst, $src" %}
9645
9646 ins_encode %{
9647 __ blsil($dst$$Register, $src$$Address);
9648 %}
9649 ins_pipe(ialu_reg_mem);
9650 %}
9651
9652 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9653 %{
9654 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9655 predicate(UseBMI1Instructions);
9656 effect(KILL cr);
9657
9658 ins_cost(125);
9659 format %{ "blsmskl $dst, $src" %}
9660
9661 ins_encode %{
9662 __ blsmskl($dst$$Register, $src$$Address);
9663 %}
9664 ins_pipe(ialu_reg_mem);
9665 %}
9666
9667 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9668 %{
9669 match(Set dst (XorI (AddI src minus_1) src));
9670 predicate(UseBMI1Instructions);
9671 effect(KILL cr);
9672
9673 format %{ "blsmskl $dst, $src" %}
9674
9675 ins_encode %{
9676 __ blsmskl($dst$$Register, $src$$Register);
9677 %}
9678
9679 ins_pipe(ialu_reg);
9680 %}
9681
9682 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9683 %{
9684 match(Set dst (AndI (AddI src minus_1) src) );
9685 predicate(UseBMI1Instructions);
9686 effect(KILL cr);
9687
9688 format %{ "blsrl $dst, $src" %}
9689
9690 ins_encode %{
9691 __ blsrl($dst$$Register, $src$$Register);
9692 %}
9693
9694 ins_pipe(ialu_reg_mem);
9695 %}
9696
9697 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9698 %{
9699 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9700 predicate(UseBMI1Instructions);
9701 effect(KILL cr);
9702
9703 ins_cost(125);
9704 format %{ "blsrl $dst, $src" %}
9705
9706 ins_encode %{
9707 __ blsrl($dst$$Register, $src$$Address);
9708 %}
9709
9710 ins_pipe(ialu_reg);
9711 %}
9712
9713 // Or Instructions
9714 // Or Register with Register
9715 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9716 %{
9717 match(Set dst (OrI dst src));
9718 effect(KILL cr);
9719
9720 format %{ "orl $dst, $src\t# int" %}
9721 opcode(0x0B);
9722 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9723 ins_pipe(ialu_reg_reg);
9724 %}
9725
9726 // Or Register with Immediate
9727 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9728 %{
9729 match(Set dst (OrI dst src));
9730 effect(KILL cr);
9731
9732 format %{ "orl $dst, $src\t# int" %}
9733 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9734 ins_encode(OpcSErm(dst, src), Con8or32(src));
9735 ins_pipe(ialu_reg);
9736 %}
9737
9738 // Or Register with Memory
9739 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9740 %{
9741 match(Set dst (OrI dst (LoadI src)));
9742 effect(KILL cr);
9743
9744 ins_cost(125);
9745 format %{ "orl $dst, $src\t# int" %}
9746 opcode(0x0B);
9747 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9748 ins_pipe(ialu_reg_mem);
9749 %}
9750
9751 // Or Memory with Register
9752 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9753 %{
9754 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9755 effect(KILL cr);
9756
9757 ins_cost(150);
9758 format %{ "orb $dst, $src\t# byte" %}
9759 opcode(0x08);
9760 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9761 ins_pipe(ialu_mem_reg);
9762 %}
9763
9764 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9765 %{
9766 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9767 effect(KILL cr);
9768
9769 ins_cost(150);
9770 format %{ "orl $dst, $src\t# int" %}
9771 opcode(0x09); /* Opcode 09 /r */
9772 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9773 ins_pipe(ialu_mem_reg);
9774 %}
9775
9776 // Or Memory with Immediate
9777 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9778 %{
9779 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9780 effect(KILL cr);
9781
9782 ins_cost(125);
9783 format %{ "orl $dst, $src\t# int" %}
9784 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9785 ins_encode(REX_mem(dst), OpcSE(src),
9786 RM_opc_mem(secondary, dst), Con8or32(src));
9787 ins_pipe(ialu_mem_imm);
9788 %}
9789
9790 // Xor Instructions
9791 // Xor Register with Register
9792 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9793 %{
9794 match(Set dst (XorI dst src));
9795 effect(KILL cr);
9796
9797 format %{ "xorl $dst, $src\t# int" %}
9798 opcode(0x33);
9799 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9800 ins_pipe(ialu_reg_reg);
9801 %}
9802
9803 // Xor Register with Immediate -1
9804 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9805 match(Set dst (XorI dst imm));
9806
9807 format %{ "not $dst" %}
9808 ins_encode %{
9809 __ notl($dst$$Register);
9810 %}
9811 ins_pipe(ialu_reg);
9812 %}
9813
9814 // Xor Register with Immediate
9815 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9816 %{
9817 match(Set dst (XorI dst src));
9818 effect(KILL cr);
9819
9820 format %{ "xorl $dst, $src\t# int" %}
9821 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9822 ins_encode(OpcSErm(dst, src), Con8or32(src));
9823 ins_pipe(ialu_reg);
9824 %}
9825
9826 // Xor Register with Memory
9827 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9828 %{
9829 match(Set dst (XorI dst (LoadI src)));
9830 effect(KILL cr);
9831
9832 ins_cost(125);
9833 format %{ "xorl $dst, $src\t# int" %}
9834 opcode(0x33);
9835 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9836 ins_pipe(ialu_reg_mem);
9837 %}
9838
9839 // Xor Memory with Register
9840 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9841 %{
9842 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9843 effect(KILL cr);
9844
9845 ins_cost(150);
9846 format %{ "xorb $dst, $src\t# byte" %}
9847 opcode(0x30);
9848 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9849 ins_pipe(ialu_mem_reg);
9850 %}
9851
9852 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9853 %{
9854 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9855 effect(KILL cr);
9856
9857 ins_cost(150);
9858 format %{ "xorl $dst, $src\t# int" %}
9859 opcode(0x31); /* Opcode 31 /r */
9860 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9861 ins_pipe(ialu_mem_reg);
9862 %}
9863
9864 // Xor Memory with Immediate
9865 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9866 %{
9867 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9868 effect(KILL cr);
9869
9870 ins_cost(125);
9871 format %{ "xorl $dst, $src\t# int" %}
9872 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9873 ins_encode(REX_mem(dst), OpcSE(src),
9874 RM_opc_mem(secondary, dst), Con8or32(src));
9875 ins_pipe(ialu_mem_imm);
9876 %}
9877
9878
9879 // Long Logical Instructions
9880
9881 // And Instructions
9882 // And Register with Register
9883 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9884 %{
9885 match(Set dst (AndL dst src));
9886 effect(KILL cr);
9887
9888 format %{ "andq $dst, $src\t# long" %}
9889 opcode(0x23);
9890 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9891 ins_pipe(ialu_reg_reg);
9892 %}
9893
9894 // And Register with Immediate 255
9895 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9896 %{
9897 match(Set dst (AndL dst src));
9898
9899 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9900 opcode(0x0F, 0xB6);
9901 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9902 ins_pipe(ialu_reg);
9903 %}
9904
9905 // And Register with Immediate 65535
9906 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9907 %{
9908 match(Set dst (AndL dst src));
9909
9910 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9911 opcode(0x0F, 0xB7);
9912 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9913 ins_pipe(ialu_reg);
9914 %}
9915
9916 // And Register with Immediate
9917 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9918 %{
9919 match(Set dst (AndL dst src));
9920 effect(KILL cr);
9921
9922 format %{ "andq $dst, $src\t# long" %}
9923 opcode(0x81, 0x04); /* Opcode 81 /4 */
9924 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9925 ins_pipe(ialu_reg);
9926 %}
9927
9928 // And Register with Memory
9929 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9930 %{
9931 match(Set dst (AndL dst (LoadL src)));
9932 effect(KILL cr);
9933
9934 ins_cost(125);
9935 format %{ "andq $dst, $src\t# long" %}
9936 opcode(0x23);
9937 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9938 ins_pipe(ialu_reg_mem);
9939 %}
9940
9941 // And Memory with Register
9942 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9943 %{
9944 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9945 effect(KILL cr);
9946
9947 ins_cost(150);
9948 format %{ "andq $dst, $src\t# long" %}
9949 opcode(0x21); /* Opcode 21 /r */
9950 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9951 ins_pipe(ialu_mem_reg);
9952 %}
9953
9954 // And Memory with Immediate
9955 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9956 %{
9957 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9958 effect(KILL cr);
9959
9960 ins_cost(125);
9961 format %{ "andq $dst, $src\t# long" %}
9962 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9963 ins_encode(REX_mem_wide(dst), OpcSE(src),
9964 RM_opc_mem(secondary, dst), Con8or32(src));
9965 ins_pipe(ialu_mem_imm);
9966 %}
9967
9968 // BMI1 instructions
9969 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9970 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9971 predicate(UseBMI1Instructions);
9972 effect(KILL cr);
9973
9974 ins_cost(125);
9975 format %{ "andnq $dst, $src1, $src2" %}
9976
9977 ins_encode %{
9978 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9979 %}
9980 ins_pipe(ialu_reg_mem);
9981 %}
9982
9983 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9984 match(Set dst (AndL (XorL src1 minus_1) src2));
9985 predicate(UseBMI1Instructions);
9986 effect(KILL cr);
9987
9988 format %{ "andnq $dst, $src1, $src2" %}
9989
9990 ins_encode %{
9991 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9992 %}
9993 ins_pipe(ialu_reg_mem);
9994 %}
9995
9996 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9997 match(Set dst (AndL (SubL imm_zero src) src));
9998 predicate(UseBMI1Instructions);
9999 effect(KILL cr);
10000
10001 format %{ "blsiq $dst, $src" %}
10002
10003 ins_encode %{
10004 __ blsiq($dst$$Register, $src$$Register);
10005 %}
10006 ins_pipe(ialu_reg);
10007 %}
10008
10009 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
10010 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
10011 predicate(UseBMI1Instructions);
10012 effect(KILL cr);
10013
10014 ins_cost(125);
10015 format %{ "blsiq $dst, $src" %}
10016
10017 ins_encode %{
10018 __ blsiq($dst$$Register, $src$$Address);
10019 %}
10020 ins_pipe(ialu_reg_mem);
10021 %}
10022
10023 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
10024 %{
10025 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
10026 predicate(UseBMI1Instructions);
10027 effect(KILL cr);
10028
10029 ins_cost(125);
10030 format %{ "blsmskq $dst, $src" %}
10031
10032 ins_encode %{
10033 __ blsmskq($dst$$Register, $src$$Address);
10034 %}
10035 ins_pipe(ialu_reg_mem);
10036 %}
10037
10038 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
10039 %{
10040 match(Set dst (XorL (AddL src minus_1) src));
10041 predicate(UseBMI1Instructions);
10042 effect(KILL cr);
10043
10044 format %{ "blsmskq $dst, $src" %}
10045
10046 ins_encode %{
10047 __ blsmskq($dst$$Register, $src$$Register);
10048 %}
10049
10050 ins_pipe(ialu_reg);
10051 %}
10052
10053 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
10054 %{
10055 match(Set dst (AndL (AddL src minus_1) src) );
10056 predicate(UseBMI1Instructions);
10057 effect(KILL cr);
10058
10059 format %{ "blsrq $dst, $src" %}
10060
10061 ins_encode %{
10062 __ blsrq($dst$$Register, $src$$Register);
10063 %}
10064
10065 ins_pipe(ialu_reg);
10066 %}
10067
10068 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
10069 %{
10070 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
10071 predicate(UseBMI1Instructions);
10072 effect(KILL cr);
10073
10074 ins_cost(125);
10075 format %{ "blsrq $dst, $src" %}
10076
10077 ins_encode %{
10078 __ blsrq($dst$$Register, $src$$Address);
10079 %}
10080
10081 ins_pipe(ialu_reg);
10082 %}
10083
10084 // Or Instructions
10085 // Or Register with Register
10086 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10087 %{
10088 match(Set dst (OrL dst src));
10089 effect(KILL cr);
10090
10091 format %{ "orq $dst, $src\t# long" %}
10092 opcode(0x0B);
10093 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10094 ins_pipe(ialu_reg_reg);
10095 %}
10096
10097 // Use any_RegP to match R15 (TLS register) without spilling.
10098 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
10099 match(Set dst (OrL dst (CastP2X src)));
10100 effect(KILL cr);
10101
10102 format %{ "orq $dst, $src\t# long" %}
10103 opcode(0x0B);
10104 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10105 ins_pipe(ialu_reg_reg);
10106 %}
10107
10108
10109 // Or Register with Immediate
10110 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10111 %{
10112 match(Set dst (OrL dst src));
10113 effect(KILL cr);
10114
10115 format %{ "orq $dst, $src\t# long" %}
10116 opcode(0x81, 0x01); /* Opcode 81 /1 id */
10117 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10118 ins_pipe(ialu_reg);
10119 %}
10120
10121 // Or Register with Memory
10122 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10123 %{
10124 match(Set dst (OrL dst (LoadL src)));
10125 effect(KILL cr);
10126
10127 ins_cost(125);
10128 format %{ "orq $dst, $src\t# long" %}
10129 opcode(0x0B);
10130 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10131 ins_pipe(ialu_reg_mem);
10132 %}
10133
10134 // Or Memory with Register
10135 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10136 %{
10137 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10138 effect(KILL cr);
10139
10140 ins_cost(150);
10141 format %{ "orq $dst, $src\t# long" %}
10142 opcode(0x09); /* Opcode 09 /r */
10143 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10144 ins_pipe(ialu_mem_reg);
10145 %}
10146
10147 // Or Memory with Immediate
10148 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10149 %{
10150 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10151 effect(KILL cr);
10152
10153 ins_cost(125);
10154 format %{ "orq $dst, $src\t# long" %}
10155 opcode(0x81, 0x1); /* Opcode 81 /1 id */
10156 ins_encode(REX_mem_wide(dst), OpcSE(src),
10157 RM_opc_mem(secondary, dst), Con8or32(src));
10158 ins_pipe(ialu_mem_imm);
10159 %}
10160
10161 // Xor Instructions
10162 // Xor Register with Register
10163 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10164 %{
10165 match(Set dst (XorL dst src));
10166 effect(KILL cr);
10167
10168 format %{ "xorq $dst, $src\t# long" %}
10169 opcode(0x33);
10170 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10171 ins_pipe(ialu_reg_reg);
10172 %}
10173
10174 // Xor Register with Immediate -1
10175 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10176 match(Set dst (XorL dst imm));
10177
10178 format %{ "notq $dst" %}
10179 ins_encode %{
10180 __ notq($dst$$Register);
10181 %}
10182 ins_pipe(ialu_reg);
10183 %}
10184
10185 // Xor Register with Immediate
10186 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10187 %{
10188 match(Set dst (XorL dst src));
10189 effect(KILL cr);
10190
10191 format %{ "xorq $dst, $src\t# long" %}
10192 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10193 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10194 ins_pipe(ialu_reg);
10195 %}
10196
10197 // Xor Register with Memory
10198 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10199 %{
10200 match(Set dst (XorL dst (LoadL src)));
10201 effect(KILL cr);
10202
10203 ins_cost(125);
10204 format %{ "xorq $dst, $src\t# long" %}
10205 opcode(0x33);
10206 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10207 ins_pipe(ialu_reg_mem);
10208 %}
10209
10210 // Xor Memory with Register
10211 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10212 %{
10213 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10214 effect(KILL cr);
10215
10216 ins_cost(150);
10217 format %{ "xorq $dst, $src\t# long" %}
10218 opcode(0x31); /* Opcode 31 /r */
10219 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10220 ins_pipe(ialu_mem_reg);
10221 %}
10222
10223 // Xor Memory with Immediate
10224 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10225 %{
10226 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10227 effect(KILL cr);
10228
10229 ins_cost(125);
10230 format %{ "xorq $dst, $src\t# long" %}
10231 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10232 ins_encode(REX_mem_wide(dst), OpcSE(src),
10233 RM_opc_mem(secondary, dst), Con8or32(src));
10234 ins_pipe(ialu_mem_imm);
10235 %}
10236
10237 // Convert Int to Boolean
10238 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10239 %{
10240 match(Set dst (Conv2B src));
10241 effect(KILL cr);
10242
10243 format %{ "testl $src, $src\t# ci2b\n\t"
10244 "setnz $dst\n\t"
10245 "movzbl $dst, $dst" %}
10246 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10247 setNZ_reg(dst),
10248 REX_reg_breg(dst, dst), // movzbl
10249 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10250 ins_pipe(pipe_slow); // XXX
10251 %}
10252
10253 // Convert Pointer to Boolean
10254 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10255 %{
10256 match(Set dst (Conv2B src));
10257 effect(KILL cr);
10258
10259 format %{ "testq $src, $src\t# cp2b\n\t"
10260 "setnz $dst\n\t"
10261 "movzbl $dst, $dst" %}
10262 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10263 setNZ_reg(dst),
10264 REX_reg_breg(dst, dst), // movzbl
10265 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10266 ins_pipe(pipe_slow); // XXX
10267 %}
10268
10269 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10270 %{
10271 match(Set dst (CmpLTMask p q));
10272 effect(KILL cr);
10273
10274 ins_cost(400);
10275 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10276 "setlt $dst\n\t"
10277 "movzbl $dst, $dst\n\t"
10278 "negl $dst" %}
10279 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10280 setLT_reg(dst),
10281 REX_reg_breg(dst, dst), // movzbl
10282 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10283 neg_reg(dst));
10284 ins_pipe(pipe_slow);
10285 %}
10286
10287 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10288 %{
10289 match(Set dst (CmpLTMask dst zero));
10290 effect(KILL cr);
10291
10292 ins_cost(100);
10293 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10294 ins_encode %{
10295 __ sarl($dst$$Register, 31);
10296 %}
10297 ins_pipe(ialu_reg);
10298 %}
10299
10300 /* Better to save a register than avoid a branch */
10301 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10302 %{
10303 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10304 effect(KILL cr);
10305 ins_cost(300);
10306 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10307 "jge done\n\t"
10308 "addl $p,$y\n"
10309 "done: " %}
10310 ins_encode %{
10311 Register Rp = $p$$Register;
10312 Register Rq = $q$$Register;
10313 Register Ry = $y$$Register;
10314 Label done;
10315 __ subl(Rp, Rq);
10316 __ jccb(Assembler::greaterEqual, done);
10317 __ addl(Rp, Ry);
10318 __ bind(done);
10319 %}
10320 ins_pipe(pipe_cmplt);
10321 %}
10322
10323 /* Better to save a register than avoid a branch */
10324 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10325 %{
10326 match(Set y (AndI (CmpLTMask p q) y));
10327 effect(KILL cr);
10328
10329 ins_cost(300);
10330
10331 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10332 "jlt done\n\t"
10333 "xorl $y, $y\n"
10334 "done: " %}
10335 ins_encode %{
10336 Register Rp = $p$$Register;
10337 Register Rq = $q$$Register;
10338 Register Ry = $y$$Register;
10339 Label done;
10340 __ cmpl(Rp, Rq);
10341 __ jccb(Assembler::less, done);
10342 __ xorl(Ry, Ry);
10343 __ bind(done);
10344 %}
10345 ins_pipe(pipe_cmplt);
10346 %}
10347
10348
10349 //---------- FP Instructions------------------------------------------------
10350
10351 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10352 %{
10353 match(Set cr (CmpF src1 src2));
10354
10355 ins_cost(145);
10356 format %{ "ucomiss $src1, $src2\n\t"
10357 "jnp,s exit\n\t"
10358 "pushfq\t# saw NaN, set CF\n\t"
10359 "andq [rsp], #0xffffff2b\n\t"
10360 "popfq\n"
10361 "exit:" %}
10362 ins_encode %{
10363 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10364 emit_cmpfp_fixup(_masm);
10365 %}
10366 ins_pipe(pipe_slow);
10367 %}
10368
10369 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10370 match(Set cr (CmpF src1 src2));
10371
10372 ins_cost(100);
10373 format %{ "ucomiss $src1, $src2" %}
10374 ins_encode %{
10375 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10376 %}
10377 ins_pipe(pipe_slow);
10378 %}
10379
10380 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10381 %{
10382 match(Set cr (CmpF src1 (LoadF src2)));
10383
10384 ins_cost(145);
10385 format %{ "ucomiss $src1, $src2\n\t"
10386 "jnp,s exit\n\t"
10387 "pushfq\t# saw NaN, set CF\n\t"
10388 "andq [rsp], #0xffffff2b\n\t"
10389 "popfq\n"
10390 "exit:" %}
10391 ins_encode %{
10392 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10393 emit_cmpfp_fixup(_masm);
10394 %}
10395 ins_pipe(pipe_slow);
10396 %}
10397
10398 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10399 match(Set cr (CmpF src1 (LoadF src2)));
10400
10401 ins_cost(100);
10402 format %{ "ucomiss $src1, $src2" %}
10403 ins_encode %{
10404 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10405 %}
10406 ins_pipe(pipe_slow);
10407 %}
10408
10409 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10410 match(Set cr (CmpF src con));
10411
10412 ins_cost(145);
10413 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10414 "jnp,s exit\n\t"
10415 "pushfq\t# saw NaN, set CF\n\t"
10416 "andq [rsp], #0xffffff2b\n\t"
10417 "popfq\n"
10418 "exit:" %}
10419 ins_encode %{
10420 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10421 emit_cmpfp_fixup(_masm);
10422 %}
10423 ins_pipe(pipe_slow);
10424 %}
10425
10426 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10427 match(Set cr (CmpF src con));
10428 ins_cost(100);
10429 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10430 ins_encode %{
10431 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10432 %}
10433 ins_pipe(pipe_slow);
10434 %}
10435
10436 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10437 %{
10438 match(Set cr (CmpD src1 src2));
10439
10440 ins_cost(145);
10441 format %{ "ucomisd $src1, $src2\n\t"
10442 "jnp,s exit\n\t"
10443 "pushfq\t# saw NaN, set CF\n\t"
10444 "andq [rsp], #0xffffff2b\n\t"
10445 "popfq\n"
10446 "exit:" %}
10447 ins_encode %{
10448 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10449 emit_cmpfp_fixup(_masm);
10450 %}
10451 ins_pipe(pipe_slow);
10452 %}
10453
10454 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10455 match(Set cr (CmpD src1 src2));
10456
10457 ins_cost(100);
10458 format %{ "ucomisd $src1, $src2 test" %}
10459 ins_encode %{
10460 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10461 %}
10462 ins_pipe(pipe_slow);
10463 %}
10464
10465 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10466 %{
10467 match(Set cr (CmpD src1 (LoadD src2)));
10468
10469 ins_cost(145);
10470 format %{ "ucomisd $src1, $src2\n\t"
10471 "jnp,s exit\n\t"
10472 "pushfq\t# saw NaN, set CF\n\t"
10473 "andq [rsp], #0xffffff2b\n\t"
10474 "popfq\n"
10475 "exit:" %}
10476 ins_encode %{
10477 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10478 emit_cmpfp_fixup(_masm);
10479 %}
10480 ins_pipe(pipe_slow);
10481 %}
10482
10483 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10484 match(Set cr (CmpD src1 (LoadD src2)));
10485
10486 ins_cost(100);
10487 format %{ "ucomisd $src1, $src2" %}
10488 ins_encode %{
10489 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10490 %}
10491 ins_pipe(pipe_slow);
10492 %}
10493
10494 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10495 match(Set cr (CmpD src con));
10496
10497 ins_cost(145);
10498 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10499 "jnp,s exit\n\t"
10500 "pushfq\t# saw NaN, set CF\n\t"
10501 "andq [rsp], #0xffffff2b\n\t"
10502 "popfq\n"
10503 "exit:" %}
10504 ins_encode %{
10505 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10506 emit_cmpfp_fixup(_masm);
10507 %}
10508 ins_pipe(pipe_slow);
10509 %}
10510
10511 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10512 match(Set cr (CmpD src con));
10513 ins_cost(100);
10514 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10515 ins_encode %{
10516 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10517 %}
10518 ins_pipe(pipe_slow);
10519 %}
10520
10521 // Compare into -1,0,1
10522 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10523 %{
10524 match(Set dst (CmpF3 src1 src2));
10525 effect(KILL cr);
10526
10527 ins_cost(275);
10528 format %{ "ucomiss $src1, $src2\n\t"
10529 "movl $dst, #-1\n\t"
10530 "jp,s done\n\t"
10531 "jb,s done\n\t"
10532 "setne $dst\n\t"
10533 "movzbl $dst, $dst\n"
10534 "done:" %}
10535 ins_encode %{
10536 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10537 emit_cmpfp3(_masm, $dst$$Register);
10538 %}
10539 ins_pipe(pipe_slow);
10540 %}
10541
10542 // Compare into -1,0,1
10543 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10544 %{
10545 match(Set dst (CmpF3 src1 (LoadF src2)));
10546 effect(KILL cr);
10547
10548 ins_cost(275);
10549 format %{ "ucomiss $src1, $src2\n\t"
10550 "movl $dst, #-1\n\t"
10551 "jp,s done\n\t"
10552 "jb,s done\n\t"
10553 "setne $dst\n\t"
10554 "movzbl $dst, $dst\n"
10555 "done:" %}
10556 ins_encode %{
10557 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10558 emit_cmpfp3(_masm, $dst$$Register);
10559 %}
10560 ins_pipe(pipe_slow);
10561 %}
10562
10563 // Compare into -1,0,1
10564 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10565 match(Set dst (CmpF3 src con));
10566 effect(KILL cr);
10567
10568 ins_cost(275);
10569 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10570 "movl $dst, #-1\n\t"
10571 "jp,s done\n\t"
10572 "jb,s done\n\t"
10573 "setne $dst\n\t"
10574 "movzbl $dst, $dst\n"
10575 "done:" %}
10576 ins_encode %{
10577 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10578 emit_cmpfp3(_masm, $dst$$Register);
10579 %}
10580 ins_pipe(pipe_slow);
10581 %}
10582
10583 // Compare into -1,0,1
10584 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10585 %{
10586 match(Set dst (CmpD3 src1 src2));
10587 effect(KILL cr);
10588
10589 ins_cost(275);
10590 format %{ "ucomisd $src1, $src2\n\t"
10591 "movl $dst, #-1\n\t"
10592 "jp,s done\n\t"
10593 "jb,s done\n\t"
10594 "setne $dst\n\t"
10595 "movzbl $dst, $dst\n"
10596 "done:" %}
10597 ins_encode %{
10598 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10599 emit_cmpfp3(_masm, $dst$$Register);
10600 %}
10601 ins_pipe(pipe_slow);
10602 %}
10603
10604 // Compare into -1,0,1
10605 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10606 %{
10607 match(Set dst (CmpD3 src1 (LoadD src2)));
10608 effect(KILL cr);
10609
10610 ins_cost(275);
10611 format %{ "ucomisd $src1, $src2\n\t"
10612 "movl $dst, #-1\n\t"
10613 "jp,s done\n\t"
10614 "jb,s done\n\t"
10615 "setne $dst\n\t"
10616 "movzbl $dst, $dst\n"
10617 "done:" %}
10618 ins_encode %{
10619 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10620 emit_cmpfp3(_masm, $dst$$Register);
10621 %}
10622 ins_pipe(pipe_slow);
10623 %}
10624
10625 // Compare into -1,0,1
10626 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10627 match(Set dst (CmpD3 src con));
10628 effect(KILL cr);
10629
10630 ins_cost(275);
10631 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10632 "movl $dst, #-1\n\t"
10633 "jp,s done\n\t"
10634 "jb,s done\n\t"
10635 "setne $dst\n\t"
10636 "movzbl $dst, $dst\n"
10637 "done:" %}
10638 ins_encode %{
10639 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10640 emit_cmpfp3(_masm, $dst$$Register);
10641 %}
10642 ins_pipe(pipe_slow);
10643 %}
10644
10645 //----------Arithmetic Conversion Instructions---------------------------------
10646
10647 instruct roundFloat_nop(regF dst)
10648 %{
10649 match(Set dst (RoundFloat dst));
10650
10651 ins_cost(0);
10652 ins_encode();
10653 ins_pipe(empty);
10654 %}
10655
10656 instruct roundDouble_nop(regD dst)
10657 %{
10658 match(Set dst (RoundDouble dst));
10659
10660 ins_cost(0);
10661 ins_encode();
10662 ins_pipe(empty);
10663 %}
10664
10665 instruct convF2D_reg_reg(regD dst, regF src)
10666 %{
10667 match(Set dst (ConvF2D src));
10668
10669 format %{ "cvtss2sd $dst, $src" %}
10670 ins_encode %{
10671 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10672 %}
10673 ins_pipe(pipe_slow); // XXX
10674 %}
10675
10676 instruct convF2D_reg_mem(regD dst, memory src)
10677 %{
10678 match(Set dst (ConvF2D (LoadF src)));
10679
10680 format %{ "cvtss2sd $dst, $src" %}
10681 ins_encode %{
10682 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10683 %}
10684 ins_pipe(pipe_slow); // XXX
10685 %}
10686
10687 instruct convD2F_reg_reg(regF dst, regD src)
10688 %{
10689 match(Set dst (ConvD2F src));
10690
10691 format %{ "cvtsd2ss $dst, $src" %}
10692 ins_encode %{
10693 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10694 %}
10695 ins_pipe(pipe_slow); // XXX
10696 %}
10697
10698 instruct convD2F_reg_mem(regF dst, memory src)
10699 %{
10700 match(Set dst (ConvD2F (LoadD src)));
10701
10702 format %{ "cvtsd2ss $dst, $src" %}
10703 ins_encode %{
10704 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10705 %}
10706 ins_pipe(pipe_slow); // XXX
10707 %}
10708
10709 // XXX do mem variants
10710 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10711 %{
10712 match(Set dst (ConvF2I src));
10713 effect(KILL cr);
10714
10715 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10716 "cmpl $dst, #0x80000000\n\t"
10717 "jne,s done\n\t"
10718 "subq rsp, #8\n\t"
10719 "movss [rsp], $src\n\t"
10720 "call f2i_fixup\n\t"
10721 "popq $dst\n"
10722 "done: "%}
10723 ins_encode %{
10724 Label done;
10725 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10726 __ cmpl($dst$$Register, 0x80000000);
10727 __ jccb(Assembler::notEqual, done);
10728 __ subptr(rsp, 8);
10729 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10730 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10731 __ pop($dst$$Register);
10732 __ bind(done);
10733 %}
10734 ins_pipe(pipe_slow);
10735 %}
10736
10737 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10738 %{
10739 match(Set dst (ConvF2L src));
10740 effect(KILL cr);
10741
10742 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10743 "cmpq $dst, [0x8000000000000000]\n\t"
10744 "jne,s done\n\t"
10745 "subq rsp, #8\n\t"
10746 "movss [rsp], $src\n\t"
10747 "call f2l_fixup\n\t"
10748 "popq $dst\n"
10749 "done: "%}
10750 ins_encode %{
10751 Label done;
10752 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10753 __ cmp64($dst$$Register,
10754 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10755 __ jccb(Assembler::notEqual, done);
10756 __ subptr(rsp, 8);
10757 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10758 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10759 __ pop($dst$$Register);
10760 __ bind(done);
10761 %}
10762 ins_pipe(pipe_slow);
10763 %}
10764
10765 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10766 %{
10767 match(Set dst (ConvD2I src));
10768 effect(KILL cr);
10769
10770 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10771 "cmpl $dst, #0x80000000\n\t"
10772 "jne,s done\n\t"
10773 "subq rsp, #8\n\t"
10774 "movsd [rsp], $src\n\t"
10775 "call d2i_fixup\n\t"
10776 "popq $dst\n"
10777 "done: "%}
10778 ins_encode %{
10779 Label done;
10780 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10781 __ cmpl($dst$$Register, 0x80000000);
10782 __ jccb(Assembler::notEqual, done);
10783 __ subptr(rsp, 8);
10784 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10785 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10786 __ pop($dst$$Register);
10787 __ bind(done);
10788 %}
10789 ins_pipe(pipe_slow);
10790 %}
10791
10792 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10793 %{
10794 match(Set dst (ConvD2L src));
10795 effect(KILL cr);
10796
10797 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10798 "cmpq $dst, [0x8000000000000000]\n\t"
10799 "jne,s done\n\t"
10800 "subq rsp, #8\n\t"
10801 "movsd [rsp], $src\n\t"
10802 "call d2l_fixup\n\t"
10803 "popq $dst\n"
10804 "done: "%}
10805 ins_encode %{
10806 Label done;
10807 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10808 __ cmp64($dst$$Register,
10809 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10810 __ jccb(Assembler::notEqual, done);
10811 __ subptr(rsp, 8);
10812 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10813 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10814 __ pop($dst$$Register);
10815 __ bind(done);
10816 %}
10817 ins_pipe(pipe_slow);
10818 %}
10819
10820 instruct convI2F_reg_reg(regF dst, rRegI src)
10821 %{
10822 predicate(!UseXmmI2F);
10823 match(Set dst (ConvI2F src));
10824
10825 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10826 ins_encode %{
10827 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10828 %}
10829 ins_pipe(pipe_slow); // XXX
10830 %}
10831
10832 instruct convI2F_reg_mem(regF dst, memory src)
10833 %{
10834 match(Set dst (ConvI2F (LoadI src)));
10835
10836 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10837 ins_encode %{
10838 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10839 %}
10840 ins_pipe(pipe_slow); // XXX
10841 %}
10842
10843 instruct convI2D_reg_reg(regD dst, rRegI src)
10844 %{
10845 predicate(!UseXmmI2D);
10846 match(Set dst (ConvI2D src));
10847
10848 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10849 ins_encode %{
10850 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10851 %}
10852 ins_pipe(pipe_slow); // XXX
10853 %}
10854
10855 instruct convI2D_reg_mem(regD dst, memory src)
10856 %{
10857 match(Set dst (ConvI2D (LoadI src)));
10858
10859 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10860 ins_encode %{
10861 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10862 %}
10863 ins_pipe(pipe_slow); // XXX
10864 %}
10865
10866 instruct convXI2F_reg(regF dst, rRegI src)
10867 %{
10868 predicate(UseXmmI2F);
10869 match(Set dst (ConvI2F src));
10870
10871 format %{ "movdl $dst, $src\n\t"
10872 "cvtdq2psl $dst, $dst\t# i2f" %}
10873 ins_encode %{
10874 __ movdl($dst$$XMMRegister, $src$$Register);
10875 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10876 %}
10877 ins_pipe(pipe_slow); // XXX
10878 %}
10879
10880 instruct convXI2D_reg(regD dst, rRegI src)
10881 %{
10882 predicate(UseXmmI2D);
10883 match(Set dst (ConvI2D src));
10884
10885 format %{ "movdl $dst, $src\n\t"
10886 "cvtdq2pdl $dst, $dst\t# i2d" %}
10887 ins_encode %{
10888 __ movdl($dst$$XMMRegister, $src$$Register);
10889 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10890 %}
10891 ins_pipe(pipe_slow); // XXX
10892 %}
10893
10894 instruct convL2F_reg_reg(regF dst, rRegL src)
10895 %{
10896 match(Set dst (ConvL2F src));
10897
10898 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10899 ins_encode %{
10900 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10901 %}
10902 ins_pipe(pipe_slow); // XXX
10903 %}
10904
10905 instruct convL2F_reg_mem(regF dst, memory src)
10906 %{
10907 match(Set dst (ConvL2F (LoadL src)));
10908
10909 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10910 ins_encode %{
10911 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10912 %}
10913 ins_pipe(pipe_slow); // XXX
10914 %}
10915
10916 instruct convL2D_reg_reg(regD dst, rRegL src)
10917 %{
10918 match(Set dst (ConvL2D src));
10919
10920 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10921 ins_encode %{
10922 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10923 %}
10924 ins_pipe(pipe_slow); // XXX
10925 %}
10926
10927 instruct convL2D_reg_mem(regD dst, memory src)
10928 %{
10929 match(Set dst (ConvL2D (LoadL src)));
10930
10931 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10932 ins_encode %{
10933 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10934 %}
10935 ins_pipe(pipe_slow); // XXX
10936 %}
10937
10938 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10939 %{
10940 match(Set dst (ConvI2L src));
10941
10942 ins_cost(125);
10943 format %{ "movslq $dst, $src\t# i2l" %}
10944 ins_encode %{
10945 __ movslq($dst$$Register, $src$$Register);
10946 %}
10947 ins_pipe(ialu_reg_reg);
10948 %}
10949
10950 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10951 // %{
10952 // match(Set dst (ConvI2L src));
10953 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10954 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10955 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10956 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10957 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10958 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10959
10960 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10961 // ins_encode(enc_copy(dst, src));
10962 // // opcode(0x63); // needs REX.W
10963 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10964 // ins_pipe(ialu_reg_reg);
10965 // %}
10966
10967 // Zero-extend convert int to long
10968 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10969 %{
10970 match(Set dst (AndL (ConvI2L src) mask));
10971
10972 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10973 ins_encode %{
10974 if ($dst$$reg != $src$$reg) {
10975 __ movl($dst$$Register, $src$$Register);
10976 }
10977 %}
10978 ins_pipe(ialu_reg_reg);
10979 %}
10980
10981 // Zero-extend convert int to long
10982 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10983 %{
10984 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10985
10986 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10987 ins_encode %{
10988 __ movl($dst$$Register, $src$$Address);
10989 %}
10990 ins_pipe(ialu_reg_mem);
10991 %}
10992
10993 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10994 %{
10995 match(Set dst (AndL src mask));
10996
10997 format %{ "movl $dst, $src\t# zero-extend long" %}
10998 ins_encode %{
10999 __ movl($dst$$Register, $src$$Register);
11000 %}
11001 ins_pipe(ialu_reg_reg);
11002 %}
11003
11004 instruct convL2I_reg_reg(rRegI dst, rRegL src)
11005 %{
11006 match(Set dst (ConvL2I src));
11007
11008 format %{ "movl $dst, $src\t# l2i" %}
11009 ins_encode %{
11010 __ movl($dst$$Register, $src$$Register);
11011 %}
11012 ins_pipe(ialu_reg_reg);
11013 %}
11014
11015
11016 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11017 match(Set dst (MoveF2I src));
11018 effect(DEF dst, USE src);
11019
11020 ins_cost(125);
11021 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
11022 ins_encode %{
11023 __ movl($dst$$Register, Address(rsp, $src$$disp));
11024 %}
11025 ins_pipe(ialu_reg_mem);
11026 %}
11027
11028 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11029 match(Set dst (MoveI2F src));
11030 effect(DEF dst, USE src);
11031
11032 ins_cost(125);
11033 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
11034 ins_encode %{
11035 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11036 %}
11037 ins_pipe(pipe_slow);
11038 %}
11039
11040 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
11041 match(Set dst (MoveD2L src));
11042 effect(DEF dst, USE src);
11043
11044 ins_cost(125);
11045 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
11046 ins_encode %{
11047 __ movq($dst$$Register, Address(rsp, $src$$disp));
11048 %}
11049 ins_pipe(ialu_reg_mem);
11050 %}
11051
11052 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
11053 predicate(!UseXmmLoadAndClearUpper);
11054 match(Set dst (MoveL2D src));
11055 effect(DEF dst, USE src);
11056
11057 ins_cost(125);
11058 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
11059 ins_encode %{
11060 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11061 %}
11062 ins_pipe(pipe_slow);
11063 %}
11064
11065 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11066 predicate(UseXmmLoadAndClearUpper);
11067 match(Set dst (MoveL2D src));
11068 effect(DEF dst, USE src);
11069
11070 ins_cost(125);
11071 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
11072 ins_encode %{
11073 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11074 %}
11075 ins_pipe(pipe_slow);
11076 %}
11077
11078
11079 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11080 match(Set dst (MoveF2I src));
11081 effect(DEF dst, USE src);
11082
11083 ins_cost(95); // XXX
11084 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
11085 ins_encode %{
11086 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11087 %}
11088 ins_pipe(pipe_slow);
11089 %}
11090
11091 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11092 match(Set dst (MoveI2F src));
11093 effect(DEF dst, USE src);
11094
11095 ins_cost(100);
11096 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
11097 ins_encode %{
11098 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11099 %}
11100 ins_pipe( ialu_mem_reg );
11101 %}
11102
11103 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11104 match(Set dst (MoveD2L src));
11105 effect(DEF dst, USE src);
11106
11107 ins_cost(95); // XXX
11108 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
11109 ins_encode %{
11110 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11111 %}
11112 ins_pipe(pipe_slow);
11113 %}
11114
11115 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
11116 match(Set dst (MoveL2D src));
11117 effect(DEF dst, USE src);
11118
11119 ins_cost(100);
11120 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
11121 ins_encode %{
11122 __ movq(Address(rsp, $dst$$disp), $src$$Register);
11123 %}
11124 ins_pipe(ialu_mem_reg);
11125 %}
11126
11127 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
11128 match(Set dst (MoveF2I src));
11129 effect(DEF dst, USE src);
11130 ins_cost(85);
11131 format %{ "movd $dst,$src\t# MoveF2I" %}
11132 ins_encode %{
11133 __ movdl($dst$$Register, $src$$XMMRegister);
11134 %}
11135 ins_pipe( pipe_slow );
11136 %}
11137
11138 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
11139 match(Set dst (MoveD2L src));
11140 effect(DEF dst, USE src);
11141 ins_cost(85);
11142 format %{ "movd $dst,$src\t# MoveD2L" %}
11143 ins_encode %{
11144 __ movdq($dst$$Register, $src$$XMMRegister);
11145 %}
11146 ins_pipe( pipe_slow );
11147 %}
11148
11149 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11150 match(Set dst (MoveI2F src));
11151 effect(DEF dst, USE src);
11152 ins_cost(100);
11153 format %{ "movd $dst,$src\t# MoveI2F" %}
11154 ins_encode %{
11155 __ movdl($dst$$XMMRegister, $src$$Register);
11156 %}
11157 ins_pipe( pipe_slow );
11158 %}
11159
11160 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11161 match(Set dst (MoveL2D src));
11162 effect(DEF dst, USE src);
11163 ins_cost(100);
11164 format %{ "movd $dst,$src\t# MoveL2D" %}
11165 ins_encode %{
11166 __ movdq($dst$$XMMRegister, $src$$Register);
11167 %}
11168 ins_pipe( pipe_slow );
11169 %}
11170
11171
11172 // =======================================================================
11173 // fast clearing of an array
11174 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11175 Universe dummy, rFlagsReg cr)
11176 %{
11177 predicate(!((ClearArrayNode*)n)->is_large());
11178 match(Set dummy (ClearArray cnt base));
11179 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11180
11181 format %{ $$template
11182 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11183 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11184 $$emit$$"jg LARGE\n\t"
11185 $$emit$$"dec rcx\n\t"
11186 $$emit$$"js DONE\t# Zero length\n\t"
11187 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11188 $$emit$$"dec rcx\n\t"
11189 $$emit$$"jge LOOP\n\t"
11190 $$emit$$"jmp DONE\n\t"
11191 $$emit$$"# LARGE:\n\t"
11192 if (UseFastStosb) {
11193 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11194 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11195 } else if (UseXMMForObjInit) {
11196 $$emit$$"mov rdi,rax\n\t"
11197 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11198 $$emit$$"jmpq L_zero_64_bytes\n\t"
11199 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11200 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11201 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11202 $$emit$$"add 0x40,rax\n\t"
11203 $$emit$$"# L_zero_64_bytes:\n\t"
11204 $$emit$$"sub 0x8,rcx\n\t"
11205 $$emit$$"jge L_loop\n\t"
11206 $$emit$$"add 0x4,rcx\n\t"
11207 $$emit$$"jl L_tail\n\t"
11208 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11209 $$emit$$"add 0x20,rax\n\t"
11210 $$emit$$"sub 0x4,rcx\n\t"
11211 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11212 $$emit$$"add 0x4,rcx\n\t"
11213 $$emit$$"jle L_end\n\t"
11214 $$emit$$"dec rcx\n\t"
11215 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11216 $$emit$$"vmovq xmm0,(rax)\n\t"
11217 $$emit$$"add 0x8,rax\n\t"
11218 $$emit$$"dec rcx\n\t"
11219 $$emit$$"jge L_sloop\n\t"
11220 $$emit$$"# L_end:\n\t"
11221 } else {
11222 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11223 }
11224 $$emit$$"# DONE"
11225 %}
11226 ins_encode %{
11227 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11228 $tmp$$XMMRegister, false);
11229 %}
11230 ins_pipe(pipe_slow);
11231 %}
11232
11233 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11234 Universe dummy, rFlagsReg cr)
11235 %{
11236 predicate(((ClearArrayNode*)n)->is_large());
11237 match(Set dummy (ClearArray cnt base));
11238 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11239
11240 format %{ $$template
11241 if (UseFastStosb) {
11242 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11243 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11244 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11245 } else if (UseXMMForObjInit) {
11246 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11247 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11248 $$emit$$"jmpq L_zero_64_bytes\n\t"
11249 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11250 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11251 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11252 $$emit$$"add 0x40,rax\n\t"
11253 $$emit$$"# L_zero_64_bytes:\n\t"
11254 $$emit$$"sub 0x8,rcx\n\t"
11255 $$emit$$"jge L_loop\n\t"
11256 $$emit$$"add 0x4,rcx\n\t"
11257 $$emit$$"jl L_tail\n\t"
11258 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11259 $$emit$$"add 0x20,rax\n\t"
11260 $$emit$$"sub 0x4,rcx\n\t"
11261 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11262 $$emit$$"add 0x4,rcx\n\t"
11263 $$emit$$"jle L_end\n\t"
11264 $$emit$$"dec rcx\n\t"
11265 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11266 $$emit$$"vmovq xmm0,(rax)\n\t"
11267 $$emit$$"add 0x8,rax\n\t"
11268 $$emit$$"dec rcx\n\t"
11269 $$emit$$"jge L_sloop\n\t"
11270 $$emit$$"# L_end:\n\t"
11271 } else {
11272 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11273 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11274 }
11275 %}
11276 ins_encode %{
11277 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11278 $tmp$$XMMRegister, true);
11279 %}
11280 ins_pipe(pipe_slow);
11281 %}
11282
11283 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11284 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11285 %{
11286 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11287 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11288 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11289
11290 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11291 ins_encode %{
11292 __ string_compare($str1$$Register, $str2$$Register,
11293 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11294 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11295 %}
11296 ins_pipe( pipe_slow );
11297 %}
11298
11299 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11300 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11301 %{
11302 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11303 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11304 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11305
11306 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11307 ins_encode %{
11308 __ string_compare($str1$$Register, $str2$$Register,
11309 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11310 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11311 %}
11312 ins_pipe( pipe_slow );
11313 %}
11314
11315 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11316 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11317 %{
11318 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11319 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11320 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11321
11322 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11323 ins_encode %{
11324 __ string_compare($str1$$Register, $str2$$Register,
11325 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11326 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11327 %}
11328 ins_pipe( pipe_slow );
11329 %}
11330
11331 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11332 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11333 %{
11334 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11335 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11336 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11337
11338 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11339 ins_encode %{
11340 __ string_compare($str2$$Register, $str1$$Register,
11341 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11342 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11343 %}
11344 ins_pipe( pipe_slow );
11345 %}
11346
11347 // fast search of substring with known size.
11348 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11349 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11350 %{
11351 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11352 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11353 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11354
11355 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11356 ins_encode %{
11357 int icnt2 = (int)$int_cnt2$$constant;
11358 if (icnt2 >= 16) {
11359 // IndexOf for constant substrings with size >= 16 elements
11360 // which don't need to be loaded through stack.
11361 __ string_indexofC8($str1$$Register, $str2$$Register,
11362 $cnt1$$Register, $cnt2$$Register,
11363 icnt2, $result$$Register,
11364 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11365 } else {
11366 // Small strings are loaded through stack if they cross page boundary.
11367 __ string_indexof($str1$$Register, $str2$$Register,
11368 $cnt1$$Register, $cnt2$$Register,
11369 icnt2, $result$$Register,
11370 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11371 }
11372 %}
11373 ins_pipe( pipe_slow );
11374 %}
11375
11376 // fast search of substring with known size.
11377 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11378 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11379 %{
11380 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11381 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11382 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11383
11384 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11385 ins_encode %{
11386 int icnt2 = (int)$int_cnt2$$constant;
11387 if (icnt2 >= 8) {
11388 // IndexOf for constant substrings with size >= 8 elements
11389 // which don't need to be loaded through stack.
11390 __ string_indexofC8($str1$$Register, $str2$$Register,
11391 $cnt1$$Register, $cnt2$$Register,
11392 icnt2, $result$$Register,
11393 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11394 } else {
11395 // Small strings are loaded through stack if they cross page boundary.
11396 __ string_indexof($str1$$Register, $str2$$Register,
11397 $cnt1$$Register, $cnt2$$Register,
11398 icnt2, $result$$Register,
11399 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11400 }
11401 %}
11402 ins_pipe( pipe_slow );
11403 %}
11404
11405 // fast search of substring with known size.
11406 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11407 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11408 %{
11409 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11410 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11411 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11412
11413 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11414 ins_encode %{
11415 int icnt2 = (int)$int_cnt2$$constant;
11416 if (icnt2 >= 8) {
11417 // IndexOf for constant substrings with size >= 8 elements
11418 // which don't need to be loaded through stack.
11419 __ string_indexofC8($str1$$Register, $str2$$Register,
11420 $cnt1$$Register, $cnt2$$Register,
11421 icnt2, $result$$Register,
11422 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11423 } else {
11424 // Small strings are loaded through stack if they cross page boundary.
11425 __ string_indexof($str1$$Register, $str2$$Register,
11426 $cnt1$$Register, $cnt2$$Register,
11427 icnt2, $result$$Register,
11428 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11429 }
11430 %}
11431 ins_pipe( pipe_slow );
11432 %}
11433
11434 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11435 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11436 %{
11437 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11438 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11439 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11440
11441 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11442 ins_encode %{
11443 __ string_indexof($str1$$Register, $str2$$Register,
11444 $cnt1$$Register, $cnt2$$Register,
11445 (-1), $result$$Register,
11446 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11447 %}
11448 ins_pipe( pipe_slow );
11449 %}
11450
11451 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11452 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11453 %{
11454 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11455 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11456 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11457
11458 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11459 ins_encode %{
11460 __ string_indexof($str1$$Register, $str2$$Register,
11461 $cnt1$$Register, $cnt2$$Register,
11462 (-1), $result$$Register,
11463 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11464 %}
11465 ins_pipe( pipe_slow );
11466 %}
11467
11468 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11469 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11470 %{
11471 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11472 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11473 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11474
11475 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11476 ins_encode %{
11477 __ string_indexof($str1$$Register, $str2$$Register,
11478 $cnt1$$Register, $cnt2$$Register,
11479 (-1), $result$$Register,
11480 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11481 %}
11482 ins_pipe( pipe_slow );
11483 %}
11484
11485 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11486 rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr)
11487 %{
11488 predicate(UseSSE42Intrinsics);
11489 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11490 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11491 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11492 ins_encode %{
11493 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11494 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
11495 %}
11496 ins_pipe( pipe_slow );
11497 %}
11498
11499 // fast string equals
11500 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11501 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11502 %{
11503 match(Set result (StrEquals (Binary str1 str2) cnt));
11504 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11505
11506 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11507 ins_encode %{
11508 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11509 $cnt$$Register, $result$$Register, $tmp3$$Register,
11510 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11511 %}
11512 ins_pipe( pipe_slow );
11513 %}
11514
11515 // fast array equals
11516 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11517 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11518 %{
11519 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11520 match(Set result (AryEq ary1 ary2));
11521 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11522
11523 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11524 ins_encode %{
11525 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11526 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11527 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11528 %}
11529 ins_pipe( pipe_slow );
11530 %}
11531
11532 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11533 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11534 %{
11535 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11536 match(Set result (AryEq ary1 ary2));
11537 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11538
11539 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11540 ins_encode %{
11541 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11542 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11543 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11544 %}
11545 ins_pipe( pipe_slow );
11546 %}
11547
11548 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11549 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11550 %{
11551 match(Set result (HasNegatives ary1 len));
11552 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11553
11554 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11555 ins_encode %{
11556 __ has_negatives($ary1$$Register, $len$$Register,
11557 $result$$Register, $tmp3$$Register,
11558 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11559 %}
11560 ins_pipe( pipe_slow );
11561 %}
11562
11563 // fast char[] to byte[] compression
11564 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11565 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11566 match(Set result (StrCompressedCopy src (Binary dst len)));
11567 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11568
11569 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11570 ins_encode %{
11571 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11572 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11573 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11574 %}
11575 ins_pipe( pipe_slow );
11576 %}
11577
11578 // fast byte[] to char[] inflation
11579 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11580 legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11581 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11582 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11583
11584 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11585 ins_encode %{
11586 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11587 $tmp1$$XMMRegister, $tmp2$$Register);
11588 %}
11589 ins_pipe( pipe_slow );
11590 %}
11591
11592 // encode char[] to byte[] in ISO_8859_1
11593 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11594 legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11595 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11596 match(Set result (EncodeISOArray src (Binary dst len)));
11597 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11598
11599 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11600 ins_encode %{
11601 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11602 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11603 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11604 %}
11605 ins_pipe( pipe_slow );
11606 %}
11607
11608 //----------Overflow Math Instructions-----------------------------------------
11609
11610 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11611 %{
11612 match(Set cr (OverflowAddI op1 op2));
11613 effect(DEF cr, USE_KILL op1, USE op2);
11614
11615 format %{ "addl $op1, $op2\t# overflow check int" %}
11616
11617 ins_encode %{
11618 __ addl($op1$$Register, $op2$$Register);
11619 %}
11620 ins_pipe(ialu_reg_reg);
11621 %}
11622
11623 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11624 %{
11625 match(Set cr (OverflowAddI op1 op2));
11626 effect(DEF cr, USE_KILL op1, USE op2);
11627
11628 format %{ "addl $op1, $op2\t# overflow check int" %}
11629
11630 ins_encode %{
11631 __ addl($op1$$Register, $op2$$constant);
11632 %}
11633 ins_pipe(ialu_reg_reg);
11634 %}
11635
11636 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11637 %{
11638 match(Set cr (OverflowAddL op1 op2));
11639 effect(DEF cr, USE_KILL op1, USE op2);
11640
11641 format %{ "addq $op1, $op2\t# overflow check long" %}
11642 ins_encode %{
11643 __ addq($op1$$Register, $op2$$Register);
11644 %}
11645 ins_pipe(ialu_reg_reg);
11646 %}
11647
11648 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11649 %{
11650 match(Set cr (OverflowAddL op1 op2));
11651 effect(DEF cr, USE_KILL op1, USE op2);
11652
11653 format %{ "addq $op1, $op2\t# overflow check long" %}
11654 ins_encode %{
11655 __ addq($op1$$Register, $op2$$constant);
11656 %}
11657 ins_pipe(ialu_reg_reg);
11658 %}
11659
11660 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11661 %{
11662 match(Set cr (OverflowSubI op1 op2));
11663
11664 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11665 ins_encode %{
11666 __ cmpl($op1$$Register, $op2$$Register);
11667 %}
11668 ins_pipe(ialu_reg_reg);
11669 %}
11670
11671 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11672 %{
11673 match(Set cr (OverflowSubI op1 op2));
11674
11675 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11676 ins_encode %{
11677 __ cmpl($op1$$Register, $op2$$constant);
11678 %}
11679 ins_pipe(ialu_reg_reg);
11680 %}
11681
11682 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11683 %{
11684 match(Set cr (OverflowSubL op1 op2));
11685
11686 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11687 ins_encode %{
11688 __ cmpq($op1$$Register, $op2$$Register);
11689 %}
11690 ins_pipe(ialu_reg_reg);
11691 %}
11692
11693 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11694 %{
11695 match(Set cr (OverflowSubL op1 op2));
11696
11697 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11698 ins_encode %{
11699 __ cmpq($op1$$Register, $op2$$constant);
11700 %}
11701 ins_pipe(ialu_reg_reg);
11702 %}
11703
11704 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11705 %{
11706 match(Set cr (OverflowSubI zero op2));
11707 effect(DEF cr, USE_KILL op2);
11708
11709 format %{ "negl $op2\t# overflow check int" %}
11710 ins_encode %{
11711 __ negl($op2$$Register);
11712 %}
11713 ins_pipe(ialu_reg_reg);
11714 %}
11715
11716 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11717 %{
11718 match(Set cr (OverflowSubL zero op2));
11719 effect(DEF cr, USE_KILL op2);
11720
11721 format %{ "negq $op2\t# overflow check long" %}
11722 ins_encode %{
11723 __ negq($op2$$Register);
11724 %}
11725 ins_pipe(ialu_reg_reg);
11726 %}
11727
11728 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11729 %{
11730 match(Set cr (OverflowMulI op1 op2));
11731 effect(DEF cr, USE_KILL op1, USE op2);
11732
11733 format %{ "imull $op1, $op2\t# overflow check int" %}
11734 ins_encode %{
11735 __ imull($op1$$Register, $op2$$Register);
11736 %}
11737 ins_pipe(ialu_reg_reg_alu0);
11738 %}
11739
11740 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11741 %{
11742 match(Set cr (OverflowMulI op1 op2));
11743 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11744
11745 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11746 ins_encode %{
11747 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11748 %}
11749 ins_pipe(ialu_reg_reg_alu0);
11750 %}
11751
11752 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11753 %{
11754 match(Set cr (OverflowMulL op1 op2));
11755 effect(DEF cr, USE_KILL op1, USE op2);
11756
11757 format %{ "imulq $op1, $op2\t# overflow check long" %}
11758 ins_encode %{
11759 __ imulq($op1$$Register, $op2$$Register);
11760 %}
11761 ins_pipe(ialu_reg_reg_alu0);
11762 %}
11763
11764 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11765 %{
11766 match(Set cr (OverflowMulL op1 op2));
11767 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11768
11769 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11770 ins_encode %{
11771 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11772 %}
11773 ins_pipe(ialu_reg_reg_alu0);
11774 %}
11775
11776
11777 //----------Control Flow Instructions------------------------------------------
11778 // Signed compare Instructions
11779
11780 // XXX more variants!!
11781 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11782 %{
11783 match(Set cr (CmpI op1 op2));
11784 effect(DEF cr, USE op1, USE op2);
11785
11786 format %{ "cmpl $op1, $op2" %}
11787 opcode(0x3B); /* Opcode 3B /r */
11788 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11789 ins_pipe(ialu_cr_reg_reg);
11790 %}
11791
11792 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11793 %{
11794 match(Set cr (CmpI op1 op2));
11795
11796 format %{ "cmpl $op1, $op2" %}
11797 opcode(0x81, 0x07); /* Opcode 81 /7 */
11798 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11799 ins_pipe(ialu_cr_reg_imm);
11800 %}
11801
11802 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11803 %{
11804 match(Set cr (CmpI op1 (LoadI op2)));
11805
11806 ins_cost(500); // XXX
11807 format %{ "cmpl $op1, $op2" %}
11808 opcode(0x3B); /* Opcode 3B /r */
11809 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11810 ins_pipe(ialu_cr_reg_mem);
11811 %}
11812
11813 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11814 %{
11815 match(Set cr (CmpI src zero));
11816
11817 format %{ "testl $src, $src" %}
11818 opcode(0x85);
11819 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11820 ins_pipe(ialu_cr_reg_imm);
11821 %}
11822
11823 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11824 %{
11825 match(Set cr (CmpI (AndI src con) zero));
11826
11827 format %{ "testl $src, $con" %}
11828 opcode(0xF7, 0x00);
11829 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11830 ins_pipe(ialu_cr_reg_imm);
11831 %}
11832
11833 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11834 %{
11835 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11836
11837 format %{ "testl $src, $mem" %}
11838 opcode(0x85);
11839 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11840 ins_pipe(ialu_cr_reg_mem);
11841 %}
11842
11843 // Unsigned compare Instructions; really, same as signed except they
11844 // produce an rFlagsRegU instead of rFlagsReg.
11845 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11846 %{
11847 match(Set cr (CmpU op1 op2));
11848
11849 format %{ "cmpl $op1, $op2\t# unsigned" %}
11850 opcode(0x3B); /* Opcode 3B /r */
11851 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11852 ins_pipe(ialu_cr_reg_reg);
11853 %}
11854
11855 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11856 %{
11857 match(Set cr (CmpU op1 op2));
11858
11859 format %{ "cmpl $op1, $op2\t# unsigned" %}
11860 opcode(0x81,0x07); /* Opcode 81 /7 */
11861 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11862 ins_pipe(ialu_cr_reg_imm);
11863 %}
11864
11865 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11866 %{
11867 match(Set cr (CmpU op1 (LoadI op2)));
11868
11869 ins_cost(500); // XXX
11870 format %{ "cmpl $op1, $op2\t# unsigned" %}
11871 opcode(0x3B); /* Opcode 3B /r */
11872 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11873 ins_pipe(ialu_cr_reg_mem);
11874 %}
11875
11876 // // // Cisc-spilled version of cmpU_rReg
11877 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11878 // //%{
11879 // // match(Set cr (CmpU (LoadI op1) op2));
11880 // //
11881 // // format %{ "CMPu $op1,$op2" %}
11882 // // ins_cost(500);
11883 // // opcode(0x39); /* Opcode 39 /r */
11884 // // ins_encode( OpcP, reg_mem( op1, op2) );
11885 // //%}
11886
11887 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11888 %{
11889 match(Set cr (CmpU src zero));
11890
11891 format %{ "testl $src, $src\t# unsigned" %}
11892 opcode(0x85);
11893 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11894 ins_pipe(ialu_cr_reg_imm);
11895 %}
11896
11897 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11898 %{
11899 match(Set cr (CmpP op1 op2));
11900
11901 format %{ "cmpq $op1, $op2\t# ptr" %}
11902 opcode(0x3B); /* Opcode 3B /r */
11903 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11904 ins_pipe(ialu_cr_reg_reg);
11905 %}
11906
11907 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11908 %{
11909 match(Set cr (CmpP op1 (LoadP op2)));
11910
11911 ins_cost(500); // XXX
11912 format %{ "cmpq $op1, $op2\t# ptr" %}
11913 opcode(0x3B); /* Opcode 3B /r */
11914 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11915 ins_pipe(ialu_cr_reg_mem);
11916 %}
11917
11918 // // // Cisc-spilled version of cmpP_rReg
11919 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11920 // //%{
11921 // // match(Set cr (CmpP (LoadP op1) op2));
11922 // //
11923 // // format %{ "CMPu $op1,$op2" %}
11924 // // ins_cost(500);
11925 // // opcode(0x39); /* Opcode 39 /r */
11926 // // ins_encode( OpcP, reg_mem( op1, op2) );
11927 // //%}
11928
11929 // XXX this is generalized by compP_rReg_mem???
11930 // Compare raw pointer (used in out-of-heap check).
11931 // Only works because non-oop pointers must be raw pointers
11932 // and raw pointers have no anti-dependencies.
11933 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11934 %{
11935 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11936 match(Set cr (CmpP op1 (LoadP op2)));
11937
11938 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11939 opcode(0x3B); /* Opcode 3B /r */
11940 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11941 ins_pipe(ialu_cr_reg_mem);
11942 %}
11943
11944 // This will generate a signed flags result. This should be OK since
11945 // any compare to a zero should be eq/neq.
11946 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11947 %{
11948 match(Set cr (CmpP src zero));
11949
11950 format %{ "testq $src, $src\t# ptr" %}
11951 opcode(0x85);
11952 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11953 ins_pipe(ialu_cr_reg_imm);
11954 %}
11955
11956 // This will generate a signed flags result. This should be OK since
11957 // any compare to a zero should be eq/neq.
11958 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11959 %{
11960 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11961 match(Set cr (CmpP (LoadP op) zero));
11962
11963 ins_cost(500); // XXX
11964 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11965 opcode(0xF7); /* Opcode F7 /0 */
11966 ins_encode(REX_mem_wide(op),
11967 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11968 ins_pipe(ialu_cr_reg_imm);
11969 %}
11970
11971 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11972 %{
11973 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11974 match(Set cr (CmpP (LoadP mem) zero));
11975
11976 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11977 ins_encode %{
11978 __ cmpq(r12, $mem$$Address);
11979 %}
11980 ins_pipe(ialu_cr_reg_mem);
11981 %}
11982
11983 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11984 %{
11985 match(Set cr (CmpN op1 op2));
11986
11987 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11988 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11989 ins_pipe(ialu_cr_reg_reg);
11990 %}
11991
11992 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11993 %{
11994 match(Set cr (CmpN src (LoadN mem)));
11995
11996 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11997 ins_encode %{
11998 __ cmpl($src$$Register, $mem$$Address);
11999 %}
12000 ins_pipe(ialu_cr_reg_mem);
12001 %}
12002
12003 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
12004 match(Set cr (CmpN op1 op2));
12005
12006 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
12007 ins_encode %{
12008 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
12009 %}
12010 ins_pipe(ialu_cr_reg_imm);
12011 %}
12012
12013 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
12014 %{
12015 match(Set cr (CmpN src (LoadN mem)));
12016
12017 format %{ "cmpl $mem, $src\t# compressed ptr" %}
12018 ins_encode %{
12019 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
12020 %}
12021 ins_pipe(ialu_cr_reg_mem);
12022 %}
12023
12024 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
12025 match(Set cr (CmpN op1 op2));
12026
12027 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
12028 ins_encode %{
12029 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
12030 %}
12031 ins_pipe(ialu_cr_reg_imm);
12032 %}
12033
12034 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
12035 %{
12036 match(Set cr (CmpN src (LoadNKlass mem)));
12037
12038 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
12039 ins_encode %{
12040 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
12041 %}
12042 ins_pipe(ialu_cr_reg_mem);
12043 %}
12044
12045 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
12046 match(Set cr (CmpN src zero));
12047
12048 format %{ "testl $src, $src\t# compressed ptr" %}
12049 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
12050 ins_pipe(ialu_cr_reg_imm);
12051 %}
12052
12053 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
12054 %{
12055 predicate(Universe::narrow_oop_base() != NULL);
12056 match(Set cr (CmpN (LoadN mem) zero));
12057
12058 ins_cost(500); // XXX
12059 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
12060 ins_encode %{
12061 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
12062 %}
12063 ins_pipe(ialu_cr_reg_mem);
12064 %}
12065
12066 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
12067 %{
12068 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
12069 match(Set cr (CmpN (LoadN mem) zero));
12070
12071 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
12072 ins_encode %{
12073 __ cmpl(r12, $mem$$Address);
12074 %}
12075 ins_pipe(ialu_cr_reg_mem);
12076 %}
12077
12078 // Yanked all unsigned pointer compare operations.
12079 // Pointer compares are done with CmpP which is already unsigned.
12080
12081 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
12082 %{
12083 match(Set cr (CmpL op1 op2));
12084
12085 format %{ "cmpq $op1, $op2" %}
12086 opcode(0x3B); /* Opcode 3B /r */
12087 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12088 ins_pipe(ialu_cr_reg_reg);
12089 %}
12090
12091 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
12092 %{
12093 match(Set cr (CmpL op1 op2));
12094
12095 format %{ "cmpq $op1, $op2" %}
12096 opcode(0x81, 0x07); /* Opcode 81 /7 */
12097 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12098 ins_pipe(ialu_cr_reg_imm);
12099 %}
12100
12101 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
12102 %{
12103 match(Set cr (CmpL op1 (LoadL op2)));
12104
12105 format %{ "cmpq $op1, $op2" %}
12106 opcode(0x3B); /* Opcode 3B /r */
12107 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12108 ins_pipe(ialu_cr_reg_mem);
12109 %}
12110
12111 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
12112 %{
12113 match(Set cr (CmpL src zero));
12114
12115 format %{ "testq $src, $src" %}
12116 opcode(0x85);
12117 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12118 ins_pipe(ialu_cr_reg_imm);
12119 %}
12120
12121 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
12122 %{
12123 match(Set cr (CmpL (AndL src con) zero));
12124
12125 format %{ "testq $src, $con\t# long" %}
12126 opcode(0xF7, 0x00);
12127 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
12128 ins_pipe(ialu_cr_reg_imm);
12129 %}
12130
12131 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12132 %{
12133 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12134
12135 format %{ "testq $src, $mem" %}
12136 opcode(0x85);
12137 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12138 ins_pipe(ialu_cr_reg_mem);
12139 %}
12140
12141 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12142 %{
12143 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12144
12145 format %{ "testq $src, $mem" %}
12146 opcode(0x85);
12147 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12148 ins_pipe(ialu_cr_reg_mem);
12149 %}
12150
12151 // Manifest a CmpL result in an integer register. Very painful.
12152 // This is the test to avoid.
12153 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12154 %{
12155 match(Set dst (CmpL3 src1 src2));
12156 effect(KILL flags);
12157
12158 ins_cost(275); // XXX
12159 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12160 "movl $dst, -1\n\t"
12161 "jl,s done\n\t"
12162 "setne $dst\n\t"
12163 "movzbl $dst, $dst\n\t"
12164 "done:" %}
12165 ins_encode(cmpl3_flag(src1, src2, dst));
12166 ins_pipe(pipe_slow);
12167 %}
12168
12169 // Unsigned long compare Instructions; really, same as signed long except they
12170 // produce an rFlagsRegU instead of rFlagsReg.
12171 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12172 %{
12173 match(Set cr (CmpUL op1 op2));
12174
12175 format %{ "cmpq $op1, $op2\t# unsigned" %}
12176 opcode(0x3B); /* Opcode 3B /r */
12177 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12178 ins_pipe(ialu_cr_reg_reg);
12179 %}
12180
12181 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12182 %{
12183 match(Set cr (CmpUL op1 op2));
12184
12185 format %{ "cmpq $op1, $op2\t# unsigned" %}
12186 opcode(0x81, 0x07); /* Opcode 81 /7 */
12187 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12188 ins_pipe(ialu_cr_reg_imm);
12189 %}
12190
12191 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12192 %{
12193 match(Set cr (CmpUL op1 (LoadL op2)));
12194
12195 format %{ "cmpq $op1, $op2\t# unsigned" %}
12196 opcode(0x3B); /* Opcode 3B /r */
12197 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12198 ins_pipe(ialu_cr_reg_mem);
12199 %}
12200
12201 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12202 %{
12203 match(Set cr (CmpUL src zero));
12204
12205 format %{ "testq $src, $src\t# unsigned" %}
12206 opcode(0x85);
12207 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12208 ins_pipe(ialu_cr_reg_imm);
12209 %}
12210
12211 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12212 %{
12213 match(Set cr (CmpI (LoadB mem) imm));
12214
12215 ins_cost(125);
12216 format %{ "cmpb $mem, $imm" %}
12217 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12218 ins_pipe(ialu_cr_reg_mem);
12219 %}
12220
12221 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
12222 %{
12223 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12224
12225 ins_cost(125);
12226 format %{ "testb $mem, $imm\t# ubyte" %}
12227 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12228 ins_pipe(ialu_cr_reg_mem);
12229 %}
12230
12231 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
12232 %{
12233 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12234
12235 ins_cost(125);
12236 format %{ "testb $mem, $imm\t# byte" %}
12237 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12238 ins_pipe(ialu_cr_reg_mem);
12239 %}
12240
12241 //----------Max and Min--------------------------------------------------------
12242 // Min Instructions
12243
12244 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12245 %{
12246 effect(USE_DEF dst, USE src, USE cr);
12247
12248 format %{ "cmovlgt $dst, $src\t# min" %}
12249 opcode(0x0F, 0x4F);
12250 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12251 ins_pipe(pipe_cmov_reg);
12252 %}
12253
12254
12255 instruct minI_rReg(rRegI dst, rRegI src)
12256 %{
12257 match(Set dst (MinI dst src));
12258
12259 ins_cost(200);
12260 expand %{
12261 rFlagsReg cr;
12262 compI_rReg(cr, dst, src);
12263 cmovI_reg_g(dst, src, cr);
12264 %}
12265 %}
12266
12267 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12268 %{
12269 effect(USE_DEF dst, USE src, USE cr);
12270
12271 format %{ "cmovllt $dst, $src\t# max" %}
12272 opcode(0x0F, 0x4C);
12273 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12274 ins_pipe(pipe_cmov_reg);
12275 %}
12276
12277
12278 instruct maxI_rReg(rRegI dst, rRegI src)
12279 %{
12280 match(Set dst (MaxI dst src));
12281
12282 ins_cost(200);
12283 expand %{
12284 rFlagsReg cr;
12285 compI_rReg(cr, dst, src);
12286 cmovI_reg_l(dst, src, cr);
12287 %}
12288 %}
12289
12290 // ============================================================================
12291 // Branch Instructions
12292
12293 // Jump Direct - Label defines a relative address from JMP+1
12294 instruct jmpDir(label labl)
12295 %{
12296 match(Goto);
12297 effect(USE labl);
12298
12299 ins_cost(300);
12300 format %{ "jmp $labl" %}
12301 size(5);
12302 ins_encode %{
12303 Label* L = $labl$$label;
12304 __ jmp(*L, false); // Always long jump
12305 %}
12306 ins_pipe(pipe_jmp);
12307 %}
12308
12309 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12310 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12311 %{
12312 match(If cop cr);
12313 effect(USE labl);
12314
12315 ins_cost(300);
12316 format %{ "j$cop $labl" %}
12317 size(6);
12318 ins_encode %{
12319 Label* L = $labl$$label;
12320 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12321 %}
12322 ins_pipe(pipe_jcc);
12323 %}
12324
12325 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12326 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12327 %{
12328 predicate(!n->has_vector_mask_set());
12329 match(CountedLoopEnd cop cr);
12330 effect(USE labl);
12331
12332 ins_cost(300);
12333 format %{ "j$cop $labl\t# loop end" %}
12334 size(6);
12335 ins_encode %{
12336 Label* L = $labl$$label;
12337 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12338 %}
12339 ins_pipe(pipe_jcc);
12340 %}
12341
12342 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12343 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12344 predicate(!n->has_vector_mask_set());
12345 match(CountedLoopEnd cop cmp);
12346 effect(USE labl);
12347
12348 ins_cost(300);
12349 format %{ "j$cop,u $labl\t# loop end" %}
12350 size(6);
12351 ins_encode %{
12352 Label* L = $labl$$label;
12353 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12354 %}
12355 ins_pipe(pipe_jcc);
12356 %}
12357
12358 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12359 predicate(!n->has_vector_mask_set());
12360 match(CountedLoopEnd cop cmp);
12361 effect(USE labl);
12362
12363 ins_cost(200);
12364 format %{ "j$cop,u $labl\t# loop end" %}
12365 size(6);
12366 ins_encode %{
12367 Label* L = $labl$$label;
12368 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12369 %}
12370 ins_pipe(pipe_jcc);
12371 %}
12372
12373 // mask version
12374 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12375 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12376 %{
12377 predicate(n->has_vector_mask_set());
12378 match(CountedLoopEnd cop cr);
12379 effect(USE labl);
12380
12381 ins_cost(400);
12382 format %{ "j$cop $labl\t# loop end\n\t"
12383 "restorevectmask \t# vector mask restore for loops" %}
12384 size(10);
12385 ins_encode %{
12386 Label* L = $labl$$label;
12387 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12388 __ restorevectmask();
12389 %}
12390 ins_pipe(pipe_jcc);
12391 %}
12392
12393 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12394 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12395 predicate(n->has_vector_mask_set());
12396 match(CountedLoopEnd cop cmp);
12397 effect(USE labl);
12398
12399 ins_cost(400);
12400 format %{ "j$cop,u $labl\t# loop end\n\t"
12401 "restorevectmask \t# vector mask restore for loops" %}
12402 size(10);
12403 ins_encode %{
12404 Label* L = $labl$$label;
12405 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12406 __ restorevectmask();
12407 %}
12408 ins_pipe(pipe_jcc);
12409 %}
12410
12411 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12412 predicate(n->has_vector_mask_set());
12413 match(CountedLoopEnd cop cmp);
12414 effect(USE labl);
12415
12416 ins_cost(300);
12417 format %{ "j$cop,u $labl\t# loop end\n\t"
12418 "restorevectmask \t# vector mask restore for loops" %}
12419 size(10);
12420 ins_encode %{
12421 Label* L = $labl$$label;
12422 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12423 __ restorevectmask();
12424 %}
12425 ins_pipe(pipe_jcc);
12426 %}
12427
12428 // Jump Direct Conditional - using unsigned comparison
12429 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12430 match(If cop cmp);
12431 effect(USE labl);
12432
12433 ins_cost(300);
12434 format %{ "j$cop,u $labl" %}
12435 size(6);
12436 ins_encode %{
12437 Label* L = $labl$$label;
12438 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12439 %}
12440 ins_pipe(pipe_jcc);
12441 %}
12442
12443 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12444 match(If cop cmp);
12445 effect(USE labl);
12446
12447 ins_cost(200);
12448 format %{ "j$cop,u $labl" %}
12449 size(6);
12450 ins_encode %{
12451 Label* L = $labl$$label;
12452 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12453 %}
12454 ins_pipe(pipe_jcc);
12455 %}
12456
12457 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12458 match(If cop cmp);
12459 effect(USE labl);
12460
12461 ins_cost(200);
12462 format %{ $$template
12463 if ($cop$$cmpcode == Assembler::notEqual) {
12464 $$emit$$"jp,u $labl\n\t"
12465 $$emit$$"j$cop,u $labl"
12466 } else {
12467 $$emit$$"jp,u done\n\t"
12468 $$emit$$"j$cop,u $labl\n\t"
12469 $$emit$$"done:"
12470 }
12471 %}
12472 ins_encode %{
12473 Label* l = $labl$$label;
12474 if ($cop$$cmpcode == Assembler::notEqual) {
12475 __ jcc(Assembler::parity, *l, false);
12476 __ jcc(Assembler::notEqual, *l, false);
12477 } else if ($cop$$cmpcode == Assembler::equal) {
12478 Label done;
12479 __ jccb(Assembler::parity, done);
12480 __ jcc(Assembler::equal, *l, false);
12481 __ bind(done);
12482 } else {
12483 ShouldNotReachHere();
12484 }
12485 %}
12486 ins_pipe(pipe_jcc);
12487 %}
12488
12489 // ============================================================================
12490 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12491 // superklass array for an instance of the superklass. Set a hidden
12492 // internal cache on a hit (cache is checked with exposed code in
12493 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12494 // encoding ALSO sets flags.
12495
12496 instruct partialSubtypeCheck(rdi_RegP result,
12497 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12498 rFlagsReg cr)
12499 %{
12500 match(Set result (PartialSubtypeCheck sub super));
12501 effect(KILL rcx, KILL cr);
12502
12503 ins_cost(1100); // slightly larger than the next version
12504 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12505 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12506 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12507 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12508 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12509 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12510 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12511 "miss:\t" %}
12512
12513 opcode(0x1); // Force a XOR of RDI
12514 ins_encode(enc_PartialSubtypeCheck());
12515 ins_pipe(pipe_slow);
12516 %}
12517
12518 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12519 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12520 immP0 zero,
12521 rdi_RegP result)
12522 %{
12523 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12524 effect(KILL rcx, KILL result);
12525
12526 ins_cost(1000);
12527 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12528 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12529 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12530 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12531 "jne,s miss\t\t# Missed: flags nz\n\t"
12532 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12533 "miss:\t" %}
12534
12535 opcode(0x0); // No need to XOR RDI
12536 ins_encode(enc_PartialSubtypeCheck());
12537 ins_pipe(pipe_slow);
12538 %}
12539
12540 // ============================================================================
12541 // Branch Instructions -- short offset versions
12542 //
12543 // These instructions are used to replace jumps of a long offset (the default
12544 // match) with jumps of a shorter offset. These instructions are all tagged
12545 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12546 // match rules in general matching. Instead, the ADLC generates a conversion
12547 // method in the MachNode which can be used to do in-place replacement of the
12548 // long variant with the shorter variant. The compiler will determine if a
12549 // branch can be taken by the is_short_branch_offset() predicate in the machine
12550 // specific code section of the file.
12551
12552 // Jump Direct - Label defines a relative address from JMP+1
12553 instruct jmpDir_short(label labl) %{
12554 match(Goto);
12555 effect(USE labl);
12556
12557 ins_cost(300);
12558 format %{ "jmp,s $labl" %}
12559 size(2);
12560 ins_encode %{
12561 Label* L = $labl$$label;
12562 __ jmpb(*L);
12563 %}
12564 ins_pipe(pipe_jmp);
12565 ins_short_branch(1);
12566 %}
12567
12568 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12569 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12570 match(If cop cr);
12571 effect(USE labl);
12572
12573 ins_cost(300);
12574 format %{ "j$cop,s $labl" %}
12575 size(2);
12576 ins_encode %{
12577 Label* L = $labl$$label;
12578 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12579 %}
12580 ins_pipe(pipe_jcc);
12581 ins_short_branch(1);
12582 %}
12583
12584 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12585 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12586 match(CountedLoopEnd cop cr);
12587 effect(USE labl);
12588
12589 ins_cost(300);
12590 format %{ "j$cop,s $labl\t# loop end" %}
12591 size(2);
12592 ins_encode %{
12593 Label* L = $labl$$label;
12594 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12595 %}
12596 ins_pipe(pipe_jcc);
12597 ins_short_branch(1);
12598 %}
12599
12600 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12601 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12602 match(CountedLoopEnd cop cmp);
12603 effect(USE labl);
12604
12605 ins_cost(300);
12606 format %{ "j$cop,us $labl\t# loop end" %}
12607 size(2);
12608 ins_encode %{
12609 Label* L = $labl$$label;
12610 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12611 %}
12612 ins_pipe(pipe_jcc);
12613 ins_short_branch(1);
12614 %}
12615
12616 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12617 match(CountedLoopEnd cop cmp);
12618 effect(USE labl);
12619
12620 ins_cost(300);
12621 format %{ "j$cop,us $labl\t# loop end" %}
12622 size(2);
12623 ins_encode %{
12624 Label* L = $labl$$label;
12625 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12626 %}
12627 ins_pipe(pipe_jcc);
12628 ins_short_branch(1);
12629 %}
12630
12631 // Jump Direct Conditional - using unsigned comparison
12632 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12633 match(If cop cmp);
12634 effect(USE labl);
12635
12636 ins_cost(300);
12637 format %{ "j$cop,us $labl" %}
12638 size(2);
12639 ins_encode %{
12640 Label* L = $labl$$label;
12641 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12642 %}
12643 ins_pipe(pipe_jcc);
12644 ins_short_branch(1);
12645 %}
12646
12647 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12648 match(If cop cmp);
12649 effect(USE labl);
12650
12651 ins_cost(300);
12652 format %{ "j$cop,us $labl" %}
12653 size(2);
12654 ins_encode %{
12655 Label* L = $labl$$label;
12656 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12657 %}
12658 ins_pipe(pipe_jcc);
12659 ins_short_branch(1);
12660 %}
12661
12662 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12663 match(If cop cmp);
12664 effect(USE labl);
12665
12666 ins_cost(300);
12667 format %{ $$template
12668 if ($cop$$cmpcode == Assembler::notEqual) {
12669 $$emit$$"jp,u,s $labl\n\t"
12670 $$emit$$"j$cop,u,s $labl"
12671 } else {
12672 $$emit$$"jp,u,s done\n\t"
12673 $$emit$$"j$cop,u,s $labl\n\t"
12674 $$emit$$"done:"
12675 }
12676 %}
12677 size(4);
12678 ins_encode %{
12679 Label* l = $labl$$label;
12680 if ($cop$$cmpcode == Assembler::notEqual) {
12681 __ jccb(Assembler::parity, *l);
12682 __ jccb(Assembler::notEqual, *l);
12683 } else if ($cop$$cmpcode == Assembler::equal) {
12684 Label done;
12685 __ jccb(Assembler::parity, done);
12686 __ jccb(Assembler::equal, *l);
12687 __ bind(done);
12688 } else {
12689 ShouldNotReachHere();
12690 }
12691 %}
12692 ins_pipe(pipe_jcc);
12693 ins_short_branch(1);
12694 %}
12695
12696 // ============================================================================
12697 // inlined locking and unlocking
12698
12699 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12700 predicate(Compile::current()->use_rtm());
12701 match(Set cr (FastLock object box));
12702 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12703 ins_cost(300);
12704 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12705 ins_encode %{
12706 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12707 $scr$$Register, $cx1$$Register, $cx2$$Register,
12708 _counters, _rtm_counters, _stack_rtm_counters,
12709 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12710 true, ra_->C->profile_rtm());
12711 %}
12712 ins_pipe(pipe_slow);
12713 %}
12714
12715 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12716 predicate(!Compile::current()->use_rtm());
12717 match(Set cr (FastLock object box));
12718 effect(TEMP tmp, TEMP scr, USE_KILL box);
12719 ins_cost(300);
12720 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12721 ins_encode %{
12722 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12723 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12724 %}
12725 ins_pipe(pipe_slow);
12726 %}
12727
12728 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12729 match(Set cr (FastUnlock object box));
12730 effect(TEMP tmp, USE_KILL box);
12731 ins_cost(300);
12732 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12733 ins_encode %{
12734 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12735 %}
12736 ins_pipe(pipe_slow);
12737 %}
12738
12739
12740 // ============================================================================
12741 // Safepoint Instructions
12742 instruct safePoint_poll(rFlagsReg cr)
12743 %{
12744 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12745 match(SafePoint);
12746 effect(KILL cr);
12747
12748 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12749 "# Safepoint: poll for GC" %}
12750 ins_cost(125);
12751 ins_encode %{
12752 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12753 __ testl(rax, addr);
12754 %}
12755 ins_pipe(ialu_reg_mem);
12756 %}
12757
12758 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12759 %{
12760 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12761 match(SafePoint poll);
12762 effect(KILL cr, USE poll);
12763
12764 format %{ "testl rax, [$poll]\t"
12765 "# Safepoint: poll for GC" %}
12766 ins_cost(125);
12767 ins_encode %{
12768 __ relocate(relocInfo::poll_type);
12769 __ testl(rax, Address($poll$$Register, 0));
12770 %}
12771 ins_pipe(ialu_reg_mem);
12772 %}
12773
12774 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12775 %{
12776 predicate(SafepointMechanism::uses_thread_local_poll());
12777 match(SafePoint poll);
12778 effect(KILL cr, USE poll);
12779
12780 format %{ "testl rax, [$poll]\t"
12781 "# Safepoint: poll for GC" %}
12782 ins_cost(125);
12783 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12784 ins_encode %{
12785 __ relocate(relocInfo::poll_type);
12786 address pre_pc = __ pc();
12787 __ testl(rax, Address($poll$$Register, 0));
12788 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12789 %}
12790 ins_pipe(ialu_reg_mem);
12791 %}
12792
12793 // ============================================================================
12794 // Procedure Call/Return Instructions
12795 // Call Java Static Instruction
12796 // Note: If this code changes, the corresponding ret_addr_offset() and
12797 // compute_padding() functions will have to be adjusted.
12798 instruct CallStaticJavaDirect(method meth) %{
12799 match(CallStaticJava);
12800 effect(USE meth);
12801
12802 ins_cost(300);
12803 format %{ "call,static " %}
12804 opcode(0xE8); /* E8 cd */
12805 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12806 ins_pipe(pipe_slow);
12807 ins_alignment(4);
12808 %}
12809
12810 // Call Java Dynamic Instruction
12811 // Note: If this code changes, the corresponding ret_addr_offset() and
12812 // compute_padding() functions will have to be adjusted.
12813 instruct CallDynamicJavaDirect(method meth)
12814 %{
12815 match(CallDynamicJava);
12816 effect(USE meth);
12817
12818 ins_cost(300);
12819 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12820 "call,dynamic " %}
12821 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12822 ins_pipe(pipe_slow);
12823 ins_alignment(4);
12824 %}
12825
12826 // Call Runtime Instruction
12827 instruct CallRuntimeDirect(method meth)
12828 %{
12829 match(CallRuntime);
12830 effect(USE meth);
12831
12832 ins_cost(300);
12833 format %{ "call,runtime " %}
12834 ins_encode(clear_avx, Java_To_Runtime(meth));
12835 ins_pipe(pipe_slow);
12836 %}
12837
12838 // Call runtime without safepoint
12839 instruct CallLeafDirect(method meth)
12840 %{
12841 match(CallLeaf);
12842 effect(USE meth);
12843
12844 ins_cost(300);
12845 format %{ "call_leaf,runtime " %}
12846 ins_encode(clear_avx, Java_To_Runtime(meth));
12847 ins_pipe(pipe_slow);
12848 %}
12849
12850 // Call runtime without safepoint
12851 instruct CallLeafNoFPDirect(method meth)
12852 %{
12853 match(CallLeafNoFP);
12854 effect(USE meth);
12855
12856 ins_cost(300);
12857 format %{ "call_leaf_nofp,runtime " %}
12858 ins_encode(clear_avx, Java_To_Runtime(meth));
12859 ins_pipe(pipe_slow);
12860 %}
12861
12862 // Return Instruction
12863 // Remove the return address & jump to it.
12864 // Notice: We always emit a nop after a ret to make sure there is room
12865 // for safepoint patching
12866 instruct Ret()
12867 %{
12868 match(Return);
12869
12870 format %{ "ret" %}
12871 opcode(0xC3);
12872 ins_encode(OpcP);
12873 ins_pipe(pipe_jmp);
12874 %}
12875
12876 // Tail Call; Jump from runtime stub to Java code.
12877 // Also known as an 'interprocedural jump'.
12878 // Target of jump will eventually return to caller.
12879 // TailJump below removes the return address.
12880 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12881 %{
12882 match(TailCall jump_target method_oop);
12883
12884 ins_cost(300);
12885 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12886 opcode(0xFF, 0x4); /* Opcode FF /4 */
12887 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12888 ins_pipe(pipe_jmp);
12889 %}
12890
12891 // Tail Jump; remove the return address; jump to target.
12892 // TailCall above leaves the return address around.
12893 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12894 %{
12895 match(TailJump jump_target ex_oop);
12896
12897 ins_cost(300);
12898 format %{ "popq rdx\t# pop return address\n\t"
12899 "jmp $jump_target" %}
12900 opcode(0xFF, 0x4); /* Opcode FF /4 */
12901 ins_encode(Opcode(0x5a), // popq rdx
12902 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12903 ins_pipe(pipe_jmp);
12904 %}
12905
12906 // Create exception oop: created by stack-crawling runtime code.
12907 // Created exception is now available to this handler, and is setup
12908 // just prior to jumping to this handler. No code emitted.
12909 instruct CreateException(rax_RegP ex_oop)
12910 %{
12911 match(Set ex_oop (CreateEx));
12912
12913 size(0);
12914 // use the following format syntax
12915 format %{ "# exception oop is in rax; no code emitted" %}
12916 ins_encode();
12917 ins_pipe(empty);
12918 %}
12919
12920 // Rethrow exception:
12921 // The exception oop will come in the first argument position.
12922 // Then JUMP (not call) to the rethrow stub code.
12923 instruct RethrowException()
12924 %{
12925 match(Rethrow);
12926
12927 // use the following format syntax
12928 format %{ "jmp rethrow_stub" %}
12929 ins_encode(enc_rethrow);
12930 ins_pipe(pipe_jmp);
12931 %}
12932
12933 // ============================================================================
12934 // This name is KNOWN by the ADLC and cannot be changed.
12935 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12936 // for this guy.
12937 instruct tlsLoadP(r15_RegP dst) %{
12938 match(Set dst (ThreadLocal));
12939 effect(DEF dst);
12940
12941 size(0);
12942 format %{ "# TLS is in R15" %}
12943 ins_encode( /*empty encoding*/ );
12944 ins_pipe(ialu_reg_reg);
12945 %}
12946
12947
12948 //----------PEEPHOLE RULES-----------------------------------------------------
12949 // These must follow all instruction definitions as they use the names
12950 // defined in the instructions definitions.
12951 //
12952 // peepmatch ( root_instr_name [preceding_instruction]* );
12953 //
12954 // peepconstraint %{
12955 // (instruction_number.operand_name relational_op instruction_number.operand_name
12956 // [, ...] );
12957 // // instruction numbers are zero-based using left to right order in peepmatch
12958 //
12959 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12960 // // provide an instruction_number.operand_name for each operand that appears
12961 // // in the replacement instruction's match rule
12962 //
12963 // ---------VM FLAGS---------------------------------------------------------
12964 //
12965 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12966 //
12967 // Each peephole rule is given an identifying number starting with zero and
12968 // increasing by one in the order seen by the parser. An individual peephole
12969 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12970 // on the command-line.
12971 //
12972 // ---------CURRENT LIMITATIONS----------------------------------------------
12973 //
12974 // Only match adjacent instructions in same basic block
12975 // Only equality constraints
12976 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12977 // Only one replacement instruction
12978 //
12979 // ---------EXAMPLE----------------------------------------------------------
12980 //
12981 // // pertinent parts of existing instructions in architecture description
12982 // instruct movI(rRegI dst, rRegI src)
12983 // %{
12984 // match(Set dst (CopyI src));
12985 // %}
12986 //
12987 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12988 // %{
12989 // match(Set dst (AddI dst src));
12990 // effect(KILL cr);
12991 // %}
12992 //
12993 // // Change (inc mov) to lea
12994 // peephole %{
12995 // // increment preceeded by register-register move
12996 // peepmatch ( incI_rReg movI );
12997 // // require that the destination register of the increment
12998 // // match the destination register of the move
12999 // peepconstraint ( 0.dst == 1.dst );
13000 // // construct a replacement instruction that sets
13001 // // the destination to ( move's source register + one )
13002 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
13003 // %}
13004 //
13005
13006 // Implementation no longer uses movX instructions since
13007 // machine-independent system no longer uses CopyX nodes.
13008 //
13009 // peephole
13010 // %{
13011 // peepmatch (incI_rReg movI);
13012 // peepconstraint (0.dst == 1.dst);
13013 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13014 // %}
13015
13016 // peephole
13017 // %{
13018 // peepmatch (decI_rReg movI);
13019 // peepconstraint (0.dst == 1.dst);
13020 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13021 // %}
13022
13023 // peephole
13024 // %{
13025 // peepmatch (addI_rReg_imm movI);
13026 // peepconstraint (0.dst == 1.dst);
13027 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13028 // %}
13029
13030 // peephole
13031 // %{
13032 // peepmatch (incL_rReg movL);
13033 // peepconstraint (0.dst == 1.dst);
13034 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13035 // %}
13036
13037 // peephole
13038 // %{
13039 // peepmatch (decL_rReg movL);
13040 // peepconstraint (0.dst == 1.dst);
13041 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13042 // %}
13043
13044 // peephole
13045 // %{
13046 // peepmatch (addL_rReg_imm movL);
13047 // peepconstraint (0.dst == 1.dst);
13048 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13049 // %}
13050
13051 // peephole
13052 // %{
13053 // peepmatch (addP_rReg_imm movP);
13054 // peepconstraint (0.dst == 1.dst);
13055 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
13056 // %}
13057
13058 // // Change load of spilled value to only a spill
13059 // instruct storeI(memory mem, rRegI src)
13060 // %{
13061 // match(Set mem (StoreI mem src));
13062 // %}
13063 //
13064 // instruct loadI(rRegI dst, memory mem)
13065 // %{
13066 // match(Set dst (LoadI mem));
13067 // %}
13068 //
13069
13070 peephole
13071 %{
13072 peepmatch (loadI storeI);
13073 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13074 peepreplace (storeI(1.mem 1.mem 1.src));
13075 %}
13076
13077 peephole
13078 %{
13079 peepmatch (loadL storeL);
13080 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13081 peepreplace (storeL(1.mem 1.mem 1.src));
13082 %}
13083
13084 //----------SMARTSPILL RULES---------------------------------------------------
13085 // These must follow all instruction definitions as they use the names
13086 // defined in the instructions definitions.