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src/hotspot/cpu/s390/s390.ad
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rev 54763 : 8213084: Rework and enhance Print[Opto]Assembly output
Reviewed-by:
@@ -1,8 +1,8 @@
//
-// Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved.
-// Copyright (c) 2017, SAP SE. All rights reserved.
+// Copyright (c) 2017, 2019, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2017, 2019 SAP SE. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License version 2 only, as
// published by the Free Software Foundation.
@@ -1386,11 +1386,10 @@
// ic_miss_stub to find the proper method.
__ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
__ z_br(R1_ic_miss_stub_addr);
__ bind(valid);
}
-
}
uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
// Determine size dynamically.
return MachNode::size(ra_);
@@ -4721,22 +4720,22 @@
// Load narrow oop
instruct loadN(iRegN dst, memory mem) %{
match(Set dst (LoadN mem));
ins_cost(MEMORY_REF_COST);
size(Z_DISP3_SIZE);
- format %{ "LoadN $dst,$mem\t# (cOop)" %}
+ format %{ "LoadN $dst,$mem\t # (cOop)" %}
opcode(LLGF_ZOPC, LLGF_ZOPC);
ins_encode(z_form_rt_mem_opt(dst, mem));
ins_pipe(pipe_class_dummy);
%}
// Load narrow Klass Pointer
instruct loadNKlass(iRegN dst, memory mem) %{
match(Set dst (LoadNKlass mem));
ins_cost(MEMORY_REF_COST);
size(Z_DISP3_SIZE);
- format %{ "LoadNKlass $dst,$mem\t# (klass cOop)" %}
+ format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %}
opcode(LLGF_ZOPC, LLGF_ZOPC);
ins_encode(z_form_rt_mem_opt(dst, mem));
ins_pipe(pipe_class_dummy);
%}
@@ -4785,22 +4784,22 @@
instruct decodeLoadN(iRegP dst, memory mem) %{
match(Set dst (DecodeN (LoadN mem)));
predicate(false && (Universe::narrow_oop_base()==NULL)&&(Universe::narrow_oop_shift()==0));
ins_cost(MEMORY_REF_COST);
size(Z_DISP3_SIZE);
- format %{ "DecodeLoadN $dst,$mem\t# (cOop Load+Decode)" %}
+ format %{ "DecodeLoadN $dst,$mem\t # (cOop Load+Decode)" %}
opcode(LLGF_ZOPC, LLGF_ZOPC);
ins_encode(z_form_rt_mem_opt(dst, mem));
ins_pipe(pipe_class_dummy);
%}
instruct decodeLoadNKlass(iRegP dst, memory mem) %{
match(Set dst (DecodeNKlass (LoadNKlass mem)));
predicate(false && (Universe::narrow_klass_base()==NULL)&&(Universe::narrow_klass_shift()==0));
ins_cost(MEMORY_REF_COST);
size(Z_DISP3_SIZE);
- format %{ "DecodeLoadNKlass $dst,$mem\t# (load/decode NKlass)" %}
+ format %{ "DecodeLoadNKlass $dst,$mem\t # (load/decode NKlass)" %}
opcode(LLGF_ZOPC, LLGF_ZOPC);
ins_encode(z_form_rt_mem_opt(dst, mem));
ins_pipe(pipe_class_dummy);
%}
@@ -4824,11 +4823,11 @@
match(Set dst (DecodeN src));
effect(KILL cr);
predicate(Universe::narrow_oop_base() == NULL || !ExpandLoadingBaseDecode);
ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
// TODO: s390 port size(VARIABLE_SIZE);
- format %{ "decodeN $dst,$src\t# (decode cOop)" %}
+ format %{ "decodeN $dst,$src\t # (decode cOop)" %}
ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %}
ins_pipe(pipe_class_dummy);
%}
// General Klass decoder
@@ -4848,11 +4847,11 @@
predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
(Universe::narrow_oop_base()== NULL || !ExpandLoadingBaseDecode_NN));
ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
// TODO: s390 port size(VARIABLE_SIZE);
- format %{ "decodeN $dst,$src\t# (decode cOop NN)" %}
+ format %{ "decodeN $dst,$src\t # (decode cOop NN)" %}
ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
ins_pipe(pipe_class_dummy);
%}
instruct loadBase(iRegL dst, immL baseImm) %{
@@ -4871,11 +4870,11 @@
// generate wrong code. Oop_decoder generates additional lgr when
// dst==base.
effect(KILL cr);
predicate(false);
// TODO: s390 port size(VARIABLE_SIZE);
- format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t# (decode cOop)" %}
+ format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
ins_encode %{
__ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
(jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base()));
%}
ins_pipe(pipe_class_dummy);
@@ -4885,11 +4884,11 @@
instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
match(Set dst (DecodeN src base));
effect(KILL cr);
predicate(false);
// TODO: s390 port size(VARIABLE_SIZE);
- format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t# (decode cOop)" %}
+ format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
ins_encode %{
__ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
(jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base()));
%}
ins_pipe(pipe_class_dummy);
@@ -4935,11 +4934,11 @@
(Universe::narrow_oop_base() == 0 ||
Universe::narrow_oop_base_disjoint() ||
!ExpandLoadingBaseEncode));
ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
// TODO: s390 port size(VARIABLE_SIZE);
- format %{ "encodeP $dst,$src\t# (encode cOop)" %}
+ format %{ "encodeP $dst,$src\t # (encode cOop)" %}
ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
ins_pipe(pipe_class_dummy);
%}
// General class encoder
@@ -4958,11 +4957,11 @@
(Universe::narrow_oop_base() == 0 ||
Universe::narrow_oop_base_disjoint() ||
!ExpandLoadingBaseEncode_NN));
ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
// TODO: s390 port size(VARIABLE_SIZE);
- format %{ "encodeP $dst,$src\t# (encode cOop)" %}
+ format %{ "encodeP $dst,$src\t # (encode cOop)" %}
ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
ins_pipe(pipe_class_dummy);
%}
// Encoder for heapbased mode peeling off loading the base.
@@ -4970,11 +4969,11 @@
match(Set dst (EncodeP src (Binary base dst)));
effect(TEMP_DEF dst);
predicate(false);
ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
// TODO: s390 port size(VARIABLE_SIZE);
- format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t# (encode cOop)" %}
+ format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %}
ins_encode %{
jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
(((uint64_t)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift());
__ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
%}
@@ -4986,11 +4985,11 @@
match(Set dst (EncodeP src base));
effect(USE pow2_offset);
predicate(false);
ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
// TODO: s390 port size(VARIABLE_SIZE);
- format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t# (encode cOop)" %}
+ format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %}
ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
ins_pipe(pipe_class_dummy);
%}
// Encoder for heapbased mode peeling off loading the base.
@@ -5039,22 +5038,22 @@
// Store Compressed Pointer
instruct storeN(memory mem, iRegN_P2N src) %{
match(Set mem (StoreN mem src));
ins_cost(MEMORY_REF_COST);
size(Z_DISP_SIZE);
- format %{ "ST $src,$mem\t# (cOop)" %}
+ format %{ "ST $src,$mem\t # (cOop)" %}
opcode(STY_ZOPC, ST_ZOPC);
ins_encode(z_form_rt_mem_opt(src, mem));
ins_pipe(pipe_class_dummy);
%}
// Store Compressed Klass pointer
instruct storeNKlass(memory mem, iRegN src) %{
match(Set mem (StoreNKlass mem src));
ins_cost(MEMORY_REF_COST);
size(Z_DISP_SIZE);
- format %{ "ST $src,$mem\t# (cKlass)" %}
+ format %{ "ST $src,$mem\t # (cKlass)" %}
opcode(STY_ZOPC, ST_ZOPC);
ins_encode(z_form_rt_mem_opt(src, mem));
ins_pipe(pipe_class_dummy);
%}
@@ -5062,21 +5061,21 @@
instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
match(Set cr (CmpN src1 src2));
ins_cost(DEFAULT_COST);
size(2);
- format %{ "CLR $src1,$src2\t# (cOop)" %}
+ format %{ "CLR $src1,$src2\t # (cOop)" %}
opcode(CLR_ZOPC);
ins_encode(z_rrform(src1, src2));
ins_pipe(pipe_class_dummy);
%}
instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
match(Set cr (CmpN src1 src2));
ins_cost(DEFAULT_COST);
size(6);
- format %{ "CLFI $src1,$src2\t# (cOop) compare immediate narrow" %}
+ format %{ "CLFI $src1,$src2\t # (cOop) compare immediate narrow" %}
ins_encode %{
AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
__ relocate(cOop.rspec(), 1);
__ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
%}
@@ -5085,11 +5084,11 @@
instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
match(Set cr (CmpN src1 src2));
ins_cost(DEFAULT_COST);
size(6);
- format %{ "CLFI $src1,$src2\t# (NKlass) compare immediate narrow" %}
+ format %{ "CLFI $src1,$src2\t # (NKlass) compare immediate narrow" %}
ins_encode %{
AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
__ relocate(NKlass.rspec(), 1);
__ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
%}
@@ -5098,11 +5097,11 @@
instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
match(Set cr (CmpN src1 src2));
ins_cost(DEFAULT_COST);
size(2);
- format %{ "LTR $src1,$src2\t# (cOop) LTR because comparing against zero" %}
+ format %{ "LTR $src1,$src2\t # (cOop) LTR because comparing against zero" %}
opcode(LTR_ZOPC);
ins_encode(z_rrform(src1, src1));
ins_pipe(pipe_class_dummy);
%}
@@ -6793,11 +6792,11 @@
instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
match(Set dst (LShiftI src nbits));
effect(KILL cr); // R1 is killed, too.
ins_cost(3 * DEFAULT_COST);
size(14);
- format %{ "SLL $dst,$src,[$nbits] & 31\t# use RISC-like SLLG also for int" %}
+ format %{ "SLL $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %}
ins_encode %{
__ z_lgr(Z_R1_scratch, $nbits$$Register);
__ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
__ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
%}
@@ -6807,11 +6806,11 @@
// Register Shift Left Immediate
// Constant shift count is masked in ideal graph already.
instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
match(Set dst (LShiftI src nbits));
size(6);
- format %{ "SLL $dst,$src,$nbits\t# use RISC-like SLLG also for int" %}
+ format %{ "SLL $dst,$src,$nbits\t # use RISC-like SLLG also for int" %}
ins_encode %{
int Nbit = $nbits$$constant;
assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
__ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
%}
@@ -7123,22 +7122,22 @@
%}
instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
match(Set cr (OverflowSubI zero op2));
effect(DEF cr, USE op2);
- format %{ "NEG $op2\t# overflow check int" %}
+ format %{ "NEG $op2\t # overflow check int" %}
ins_encode %{
__ clear_reg(Z_R0_scratch, false, false);
__ z_sr(Z_R0_scratch, $op2$$Register);
%}
ins_pipe(pipe_class_dummy);
%}
instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
match(Set cr (OverflowSubL zero op2));
effect(DEF cr, USE op2);
- format %{ "NEGG $op2\t# overflow check long" %}
+ format %{ "NEGG $op2\t # overflow check long" %}
ins_encode %{
__ clear_reg(Z_R0_scratch, true, false);
__ z_sgr(Z_R0_scratch, $op2$$Register);
%}
ins_pipe(pipe_class_dummy);
@@ -9189,11 +9188,11 @@
// Same match rule as `branchConFar'.
match(If cmp cr);
effect(USE lbl);
ins_cost(BRANCH_COST);
size(4);
- format %{ "branch_con_short,$cmp $cr, $lbl" %}
+ format %{ "branch_con_short,$cmp $lbl" %}
ins_encode(z_enc_branch_con_short(cmp, lbl));
ins_pipe(pipe_class_dummy);
// If set to 1 this indicates that the current instruction is a
// short variant of a long branch. This avoids using this
// instruction in first-pass matching. It will then only be used in
@@ -9211,11 +9210,11 @@
match(If cmp cr);
effect(USE cr, USE lbl);
// Make more expensive to prefer compare_and_branch over separate instructions.
ins_cost(2 * BRANCH_COST);
size(6);
- format %{ "branch_con_far,$cmp $cr, $lbl" %}
+ format %{ "branch_con_far,$cmp $lbl" %}
ins_encode(z_enc_branch_con_far(cmp, lbl));
ins_pipe(pipe_class_dummy);
// This is not a short variant of a branch, but the long variant..
ins_short_branch(0);
%}
@@ -9780,11 +9779,11 @@
// TailJump below removes the return address.
instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{
match(TailCall jump_target method_oop);
ins_cost(CALL_COST);
size(2);
- format %{ "Jmp $jump_target\t# $method_oop holds method oop" %}
+ format %{ "Jmp $jump_target\t # $method_oop holds method oop" %}
ins_encode %{ __ z_br($jump_target$$Register); %}
ins_pipe(pipe_class_dummy);
%}
// Return Instruction
@@ -10788,22 +10787,22 @@
instruct bytes_reverse_int(iRegI dst, iRegI src) %{
match(Set dst (ReverseBytesI src));
predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
ins_cost(DEFAULT_COST);
size(4);
- format %{ "LRVR $dst,$src\t# byte reverse int" %}
+ format %{ "LRVR $dst,$src\t # byte reverse int" %}
opcode(LRVR_ZOPC);
ins_encode(z_rreform(dst, src));
ins_pipe(pipe_class_dummy);
%}
instruct bytes_reverse_long(iRegL dst, iRegL src) %{
match(Set dst (ReverseBytesL src));
predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
ins_cost(DEFAULT_COST);
// TODO: s390 port size(FIXED_SIZE);
- format %{ "LRVGR $dst,$src\t# byte reverse long" %}
+ format %{ "LRVGR $dst,$src\t # byte reverse long" %}
opcode(LRVGR_ZOPC);
ins_encode(z_rreform(dst, src));
ins_pipe(pipe_class_dummy);
%}
@@ -10819,12 +10818,12 @@
instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
match(Set dst (CountLeadingZerosI src));
effect(KILL tmp, KILL cr);
ins_cost(3 * DEFAULT_COST);
size(14);
- format %{ "SLLG $dst,$src,32\t# no need to always count 32 zeroes first\n\t"
- "IILH $dst,0x8000 \t# insert \"stop bit\" to force result 32 for zero src.\n\t"
+ format %{ "SLLG $dst,$src,32\t # no need to always count 32 zeroes first\n\t"
+ "IILH $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t"
"FLOGR $dst,$dst"
%}
ins_encode %{
// Performance experiments indicate that "FLOGR" is using some kind of
// iteration to find the leftmost "1" bit.
@@ -10857,11 +10856,11 @@
instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
match(Set dst (CountLeadingZerosL src));
effect(KILL tmp, KILL cr);
ins_cost(DEFAULT_COST);
size(4);
- format %{ "FLOGR $dst,$src \t# count leading zeros (long)\n\t" %}
+ format %{ "FLOGR $dst,$src \t # count leading zeros (long)\n\t" %}
ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
ins_pipe(pipe_class_dummy);
%}
// trailing zeroes
@@ -10882,18 +10881,18 @@
instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
match(Set dst (CountTrailingZerosI src));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(8 * DEFAULT_COST);
// TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
- format %{ "LLGFR $dst,$src \t# clear upper 32 bits (we are dealing with int)\n\t"
- "LCGFR $tmp,$src \t# load 2's complement (32->64 bit)\n\t"
- "AGHI $dst,-1 \t# tmp1 = src-1\n\t"
- "AGHI $tmp,-1 \t# tmp2 = -src-1 = ~src\n\t"
- "NGR $dst,$tmp \t# tmp3 = tmp1&tmp2\n\t"
- "FLOGR $dst,$dst \t# count trailing zeros (int)\n\t"
- "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t"
- "LCR $dst,$dst \t# res = -tmp4"
+ format %{ "LLGFR $dst,$src \t # clear upper 32 bits (we are dealing with int)\n\t"
+ "LCGFR $tmp,$src \t # load 2's complement (32->64 bit)\n\t"
+ "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
+ "AGHI $tmp,-1 \t # tmp2 = -src-1 = ~src\n\t"
+ "NGR $dst,$tmp \t # tmp3 = tmp1&tmp2\n\t"
+ "FLOGR $dst,$dst \t # count trailing zeros (int)\n\t"
+ "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
+ "LCR $dst,$dst \t # res = -tmp4"
%}
ins_encode %{
Register Rdst = $dst$$Register;
Register Rsrc = $src$$Register;
// Rtmp only needed for for zero-argument shortcut. With kill effect in
@@ -10935,16 +10934,16 @@
instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
match(Set dst (CountTrailingZerosL src));
effect(TEMP_DEF dst, KILL tmp, KILL cr);
ins_cost(8 * DEFAULT_COST);
// TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
- format %{ "LCGR $dst,$src \t# preserve src\n\t"
- "NGR $dst,$src \t#"
- "AGHI $dst,-1 \t# tmp1 = src-1\n\t"
- "FLOGR $dst,$dst \t# count trailing zeros (long), kill $tmp\n\t"
- "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t"
- "LCR $dst,$dst \t#"
+ format %{ "LCGR $dst,$src \t # preserve src\n\t"
+ "NGR $dst,$src \t #\n\t"
+ "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
+ "FLOGR $dst,$dst \t # count trailing zeros (long), kill $tmp\n\t"
+ "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
+ "LCR $dst,$dst \t #"
%}
ins_encode %{
Register Rdst = $dst$$Register;
Register Rsrc = $src$$Register;
assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
@@ -10967,11 +10966,11 @@
match(Set dst (PopCountI src));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
predicate(UsePopCountInstruction && VM_Version::has_PopCount());
ins_cost(DEFAULT_COST);
size(24);
- format %{ "POPCNT $dst,$src\t# pop count int" %}
+ format %{ "POPCNT $dst,$src\t # pop count int" %}
ins_encode %{
Register Rdst = $dst$$Register;
Register Rsrc = $src$$Register;
Register Rtmp = $tmp$$Register;
@@ -10994,11 +10993,11 @@
match(Set dst (PopCountL src));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
predicate(UsePopCountInstruction && VM_Version::has_PopCount());
ins_cost(DEFAULT_COST);
// TODO: s390 port size(FIXED_SIZE);
- format %{ "POPCNT $dst,$src\t# pop count long" %}
+ format %{ "POPCNT $dst,$src\t # pop count long" %}
ins_encode %{
Register Rdst = $dst$$Register;
Register Rsrc = $src$$Register;
Register Rtmp = $tmp$$Register;
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