1 // 2 // Copyright (c) 1998, 2019, Oracle and/or its affiliates. All rights reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 // or visit www.oracle.com if you need additional information or have any 21 // questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 // 64-bit build means 64-bit pointers means hi/lo pairs 315 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 316 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 317 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 318 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 319 // Lock encodings use G3 and G4 internally 320 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 321 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 322 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 323 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 324 // Special class for storeP instructions, which can store SP or RPC to TLS. 325 // It is also used for memory addressing, allowing direct TLS addressing. 326 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 327 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 328 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 329 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 330 // R_L7 is the lowest-priority callee-save (i.e., NS) register 331 // We use it to save R_G2 across calls out of Java. 332 reg_class l7_regP(R_L7H,R_L7); 333 334 // Other special pointer regs 335 reg_class g1_regP(R_G1H,R_G1); 336 reg_class g2_regP(R_G2H,R_G2); 337 reg_class g3_regP(R_G3H,R_G3); 338 reg_class g4_regP(R_G4H,R_G4); 339 reg_class g5_regP(R_G5H,R_G5); 340 reg_class i0_regP(R_I0H,R_I0); 341 reg_class o0_regP(R_O0H,R_O0); 342 reg_class o1_regP(R_O1H,R_O1); 343 reg_class o2_regP(R_O2H,R_O2); 344 reg_class o7_regP(R_O7H,R_O7); 345 346 347 // ---------------------------- 348 // Long Register Classes 349 // ---------------------------- 350 // Longs in 1 register. Aligned adjacent hi/lo pairs. 351 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 352 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 353 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 354 // 64-bit, longs in 1 register: use all 64-bit integer registers 355 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 356 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 357 ); 358 359 reg_class g1_regL(R_G1H,R_G1); 360 reg_class g3_regL(R_G3H,R_G3); 361 reg_class o2_regL(R_O2H,R_O2); 362 reg_class o7_regL(R_O7H,R_O7); 363 364 // ---------------------------- 365 // Special Class for Condition Code Flags Register 366 reg_class int_flags(CCR); 367 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 368 reg_class float_flag0(FCC0); 369 370 371 // ---------------------------- 372 // Float Point Register Classes 373 // ---------------------------- 374 // Skip F30/F31, they are reserved for mem-mem copies 375 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 376 377 // Paired floating point registers--they show up in the same order as the floats, 378 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 379 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 380 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 381 /* Use extra V9 double registers; this AD file does not support V8 */ 382 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 383 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 384 ); 385 386 // Paired floating point registers--they show up in the same order as the floats, 387 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 388 // This class is usable for mis-aligned loads as happen in I2C adapters. 389 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 390 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 391 %} 392 393 //----------DEFINITION BLOCK--------------------------------------------------- 394 // Define name --> value mappings to inform the ADLC of an integer valued name 395 // Current support includes integer values in the range [0, 0x7FFFFFFF] 396 // Format: 397 // int_def <name> ( <int_value>, <expression>); 398 // Generated Code in ad_<arch>.hpp 399 // #define <name> (<expression>) 400 // // value == <int_value> 401 // Generated code in ad_<arch>.cpp adlc_verification() 402 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 403 // 404 definitions %{ 405 // The default cost (of an ALU instruction). 406 int_def DEFAULT_COST ( 100, 100); 407 int_def HUGE_COST (1000000, 1000000); 408 409 // Memory refs are twice as expensive as run-of-the-mill. 410 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 411 412 // Branches are even more expensive. 413 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 414 int_def CALL_COST ( 300, DEFAULT_COST * 3); 415 %} 416 417 418 //----------SOURCE BLOCK------------------------------------------------------- 419 // This is a block of C++ code which provides values, functions, and 420 // definitions necessary in the rest of the architecture description 421 source_hpp %{ 422 // Header information of the source block. 423 // Method declarations/definitions which are used outside 424 // the ad-scope can conveniently be defined here. 425 // 426 // To keep related declarations/definitions/uses close together, 427 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 428 429 // Must be visible to the DFA in dfa_sparc.cpp 430 extern bool can_branch_register( Node *bol, Node *cmp ); 431 432 extern bool use_block_zeroing(Node* count); 433 434 // Macros to extract hi & lo halves from a long pair. 435 // G0 is not part of any long pair, so assert on that. 436 // Prevents accidentally using G1 instead of G0. 437 #define LONG_HI_REG(x) (x) 438 #define LONG_LO_REG(x) (x) 439 440 class CallStubImpl { 441 442 //-------------------------------------------------------------- 443 //---< Used for optimization in Compile::Shorten_branches >--- 444 //-------------------------------------------------------------- 445 446 public: 447 // Size of call trampoline stub. 448 static uint size_call_trampoline() { 449 return 0; // no call trampolines on this platform 450 } 451 452 // number of relocations needed by a call trampoline stub 453 static uint reloc_call_trampoline() { 454 return 0; // no call trampolines on this platform 455 } 456 }; 457 458 class HandlerImpl { 459 460 public: 461 462 static int emit_exception_handler(CodeBuffer &cbuf); 463 static int emit_deopt_handler(CodeBuffer& cbuf); 464 465 static uint size_exception_handler() { 466 return ( NativeJump::instruction_size ); // sethi;jmp;nop 467 } 468 469 static uint size_deopt_handler() { 470 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 471 } 472 }; 473 474 %} 475 476 source %{ 477 #define __ _masm. 478 479 // tertiary op of a LoadP or StoreP encoding 480 #define REGP_OP true 481 482 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 483 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 484 static Register reg_to_register_object(int register_encoding); 485 486 // Used by the DFA in dfa_sparc.cpp. 487 // Check for being able to use a V9 branch-on-register. Requires a 488 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 489 // extended. Doesn't work following an integer ADD, for example, because of 490 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 491 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 492 // replace them with zero, which could become sign-extension in a different OS 493 // release. There's no obvious reason why an interrupt will ever fill these 494 // bits with non-zero junk (the registers are reloaded with standard LD 495 // instructions which either zero-fill or sign-fill). 496 bool can_branch_register( Node *bol, Node *cmp ) { 497 if( !BranchOnRegister ) return false; 498 if( cmp->Opcode() == Op_CmpP ) 499 return true; // No problems with pointer compares 500 if( cmp->Opcode() == Op_CmpL ) 501 return true; // No problems with long compares 502 503 if( !SparcV9RegsHiBitsZero ) return false; 504 if( bol->as_Bool()->_test._test != BoolTest::ne && 505 bol->as_Bool()->_test._test != BoolTest::eq ) 506 return false; 507 508 // Check for comparing against a 'safe' value. Any operation which 509 // clears out the high word is safe. Thus, loads and certain shifts 510 // are safe, as are non-negative constants. Any operation which 511 // preserves zero bits in the high word is safe as long as each of its 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their 513 // inputs are safe. At present, the only important case to recognize 514 // seems to be loads. Constants should fold away, and shifts & 515 // logicals can use the 'cc' forms. 516 Node *x = cmp->in(1); 517 if( x->is_Load() ) return true; 518 if( x->is_Phi() ) { 519 for( uint i = 1; i < x->req(); i++ ) 520 if( !x->in(i)->is_Load() ) 521 return false; 522 return true; 523 } 524 return false; 525 } 526 527 bool use_block_zeroing(Node* count) { 528 // Use BIS for zeroing if count is not constant 529 // or it is >= BlockZeroingLowLimit. 530 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); 531 } 532 533 // **************************************************************************** 534 535 // REQUIRED FUNCTIONALITY 536 537 // !!!!! Special hack to get all type of calls to specify the byte offset 538 // from the start of the call to the point where the return address 539 // will point. 540 // The "return address" is the address of the call instruction, plus 8. 541 542 int MachCallStaticJavaNode::ret_addr_offset() { 543 int offset = NativeCall::instruction_size; // call; delay slot 544 if (_method_handle_invoke) 545 offset += 4; // restore SP 546 return offset; 547 } 548 549 int MachCallDynamicJavaNode::ret_addr_offset() { 550 int vtable_index = this->_vtable_index; 551 if (vtable_index < 0) { 552 // must be invalid_vtable_index, not nonvirtual_vtable_index 553 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 554 return (NativeMovConstReg::instruction_size + 555 NativeCall::instruction_size); // sethi; setlo; call; delay slot 556 } else { 557 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 558 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes(); 559 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 560 int klass_load_size; 561 if (UseCompressedClassPointers) { 562 assert(Universe::heap() != NULL, "java heap should be initialized"); 563 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 564 } else { 565 klass_load_size = 1*BytesPerInstWord; 566 } 567 if (Assembler::is_simm13(v_off)) { 568 return klass_load_size + 569 (2*BytesPerInstWord + // ld_ptr, ld_ptr 570 NativeCall::instruction_size); // call; delay slot 571 } else { 572 return klass_load_size + 573 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 574 NativeCall::instruction_size); // call; delay slot 575 } 576 } 577 } 578 579 int MachCallRuntimeNode::ret_addr_offset() { 580 if (MacroAssembler::is_far_target(entry_point())) { 581 return NativeFarCall::instruction_size; 582 } else { 583 return NativeCall::instruction_size; 584 } 585 } 586 587 // Indicate if the safepoint node needs the polling page as an input. 588 // Since Sparc does not have absolute addressing, it does. 589 bool SafePointNode::needs_polling_address_input() { 590 return true; 591 } 592 593 // emit an interrupt that is caught by the debugger (for debugging compiler) 594 void emit_break(CodeBuffer &cbuf) { 595 MacroAssembler _masm(&cbuf); 596 __ breakpoint_trap(); 597 } 598 599 #ifndef PRODUCT 600 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 601 st->print("TA"); 602 } 603 #endif 604 605 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 606 emit_break(cbuf); 607 } 608 609 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 610 return MachNode::size(ra_); 611 } 612 613 // Traceable jump 614 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 615 MacroAssembler _masm(&cbuf); 616 Register rdest = reg_to_register_object(jump_target); 617 __ JMP(rdest, 0); 618 __ delayed()->nop(); 619 } 620 621 // Traceable jump and set exception pc 622 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 623 MacroAssembler _masm(&cbuf); 624 Register rdest = reg_to_register_object(jump_target); 625 __ JMP(rdest, 0); 626 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 627 } 628 629 void emit_nop(CodeBuffer &cbuf) { 630 MacroAssembler _masm(&cbuf); 631 __ nop(); 632 } 633 634 void emit_illtrap(CodeBuffer &cbuf) { 635 MacroAssembler _masm(&cbuf); 636 __ illtrap(0); 637 } 638 639 640 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 641 assert(n->rule() != loadUB_rule, ""); 642 643 intptr_t offset = 0; 644 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 645 const Node* addr = n->get_base_and_disp(offset, adr_type); 646 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 647 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 648 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 649 atype = atype->add_offset(offset); 650 assert(disp32 == offset, "wrong disp32"); 651 return atype->_offset; 652 } 653 654 655 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 656 assert(n->rule() != loadUB_rule, ""); 657 658 intptr_t offset = 0; 659 Node* addr = n->in(2); 660 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 661 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 662 Node* a = addr->in(2/*AddPNode::Address*/); 663 Node* o = addr->in(3/*AddPNode::Offset*/); 664 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 665 atype = a->bottom_type()->is_ptr()->add_offset(offset); 666 assert(atype->isa_oop_ptr(), "still an oop"); 667 } 668 offset = atype->is_ptr()->_offset; 669 if (offset != Type::OffsetBot) offset += disp32; 670 return offset; 671 } 672 673 static inline jlong replicate_immI(int con, int count, int width) { 674 // Load a constant replicated "count" times with width "width" 675 assert(count*width == 8 && width <= 4, "sanity"); 676 int bit_width = width * 8; 677 jlong val = con; 678 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits 679 for (int i = 0; i < count - 1; i++) { 680 val |= (val << bit_width); 681 } 682 return val; 683 } 684 685 static inline jlong replicate_immF(float con) { 686 // Replicate float con 2 times and pack into vector. 687 int val = *((int*)&con); 688 jlong lval = val; 689 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 690 return lval; 691 } 692 693 // Standard Sparc opcode form2 field breakdown 694 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 695 f0 &= (1<<19)-1; // Mask displacement to 19 bits 696 int op = (f30 << 30) | 697 (f29 << 29) | 698 (f25 << 25) | 699 (f22 << 22) | 700 (f20 << 20) | 701 (f19 << 19) | 702 (f0 << 0); 703 cbuf.insts()->emit_int32(op); 704 } 705 706 // Standard Sparc opcode form2 field breakdown 707 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 708 f0 >>= 10; // Drop 10 bits 709 f0 &= (1<<22)-1; // Mask displacement to 22 bits 710 int op = (f30 << 30) | 711 (f25 << 25) | 712 (f22 << 22) | 713 (f0 << 0); 714 cbuf.insts()->emit_int32(op); 715 } 716 717 // Standard Sparc opcode form3 field breakdown 718 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 719 int op = (f30 << 30) | 720 (f25 << 25) | 721 (f19 << 19) | 722 (f14 << 14) | 723 (f5 << 5) | 724 (f0 << 0); 725 cbuf.insts()->emit_int32(op); 726 } 727 728 // Standard Sparc opcode form3 field breakdown 729 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 730 simm13 &= (1<<13)-1; // Mask to 13 bits 731 int op = (f30 << 30) | 732 (f25 << 25) | 733 (f19 << 19) | 734 (f14 << 14) | 735 (1 << 13) | // bit to indicate immediate-mode 736 (simm13<<0); 737 cbuf.insts()->emit_int32(op); 738 } 739 740 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 741 simm10 &= (1<<10)-1; // Mask to 10 bits 742 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 743 } 744 745 #ifdef ASSERT 746 // Helper function for VerifyOops in emit_form3_mem_reg 747 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 748 warning("VerifyOops encountered unexpected instruction:"); 749 n->dump(2); 750 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 751 } 752 #endif 753 754 755 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, 756 int src1_enc, int disp32, int src2_enc, int dst_enc) { 757 758 #ifdef ASSERT 759 // The following code implements the +VerifyOops feature. 760 // It verifies oop values which are loaded into or stored out of 761 // the current method activation. +VerifyOops complements techniques 762 // like ScavengeALot, because it eagerly inspects oops in transit, 763 // as they enter or leave the stack, as opposed to ScavengeALot, 764 // which inspects oops "at rest", in the stack or heap, at safepoints. 765 // For this reason, +VerifyOops can sometimes detect bugs very close 766 // to their point of creation. It can also serve as a cross-check 767 // on the validity of oop maps, when used toegether with ScavengeALot. 768 769 // It would be good to verify oops at other points, especially 770 // when an oop is used as a base pointer for a load or store. 771 // This is presently difficult, because it is hard to know when 772 // a base address is biased or not. (If we had such information, 773 // it would be easy and useful to make a two-argument version of 774 // verify_oop which unbiases the base, and performs verification.) 775 776 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 777 bool is_verified_oop_base = false; 778 bool is_verified_oop_load = false; 779 bool is_verified_oop_store = false; 780 int tmp_enc = -1; 781 if (VerifyOops && src1_enc != R_SP_enc) { 782 // classify the op, mainly for an assert check 783 int st_op = 0, ld_op = 0; 784 switch (primary) { 785 case Assembler::stb_op3: st_op = Op_StoreB; break; 786 case Assembler::sth_op3: st_op = Op_StoreC; break; 787 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 788 case Assembler::stw_op3: st_op = Op_StoreI; break; 789 case Assembler::std_op3: st_op = Op_StoreL; break; 790 case Assembler::stf_op3: st_op = Op_StoreF; break; 791 case Assembler::stdf_op3: st_op = Op_StoreD; break; 792 793 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 794 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; 795 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 796 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 797 case Assembler::ldx_op3: // may become LoadP or stay LoadI 798 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 799 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 800 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 801 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 802 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 803 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 804 805 default: ShouldNotReachHere(); 806 } 807 if (tertiary == REGP_OP) { 808 if (st_op == Op_StoreI) st_op = Op_StoreP; 809 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 810 else ShouldNotReachHere(); 811 if (st_op) { 812 // a store 813 // inputs are (0:control, 1:memory, 2:address, 3:value) 814 Node* n2 = n->in(3); 815 if (n2 != NULL) { 816 const Type* t = n2->bottom_type(); 817 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 818 } 819 } else { 820 // a load 821 const Type* t = n->bottom_type(); 822 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 823 } 824 } 825 826 if (ld_op) { 827 // a Load 828 // inputs are (0:control, 1:memory, 2:address) 829 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 830 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 831 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 832 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 833 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 834 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 835 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 836 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 837 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 838 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 839 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 840 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && 841 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && 842 !(n->rule() == loadUB_rule)) { 843 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 844 } 845 } else if (st_op) { 846 // a Store 847 // inputs are (0:control, 1:memory, 2:address, 3:value) 848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 853 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && 854 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 855 verify_oops_warning(n, n->ideal_Opcode(), st_op); 856 } 857 } 858 859 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 860 Node* addr = n->in(2); 861 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 862 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 863 if (atype != NULL) { 864 intptr_t offset = get_offset_from_base(n, atype, disp32); 865 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 866 if (offset != offset_2) { 867 get_offset_from_base(n, atype, disp32); 868 get_offset_from_base_2(n, atype, disp32); 869 } 870 assert(offset == offset_2, "different offsets"); 871 if (offset == disp32) { 872 // we now know that src1 is a true oop pointer 873 is_verified_oop_base = true; 874 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 875 if( primary == Assembler::ldd_op3 ) { 876 is_verified_oop_base = false; // Cannot 'ldd' into O7 877 } else { 878 tmp_enc = dst_enc; 879 dst_enc = R_O7_enc; // Load into O7; preserve source oop 880 assert(src1_enc != dst_enc, ""); 881 } 882 } 883 } 884 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 885 || offset == oopDesc::mark_offset_in_bytes())) { 886 // loading the mark should not be allowed either, but 887 // we don't check this since it conflicts with InlineObjectHash 888 // usage of LoadINode to get the mark. We could keep the 889 // check if we create a new LoadMarkNode 890 // but do not verify the object before its header is initialized 891 ShouldNotReachHere(); 892 } 893 } 894 } 895 } 896 } 897 #endif 898 899 uint instr = (Assembler::ldst_op << 30) 900 | (dst_enc << 25) 901 | (primary << 19) 902 | (src1_enc << 14); 903 904 uint index = src2_enc; 905 int disp = disp32; 906 907 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { 908 disp += STACK_BIAS; 909 // Check that stack offset fits, load into O7 if not 910 if (!Assembler::is_simm13(disp)) { 911 MacroAssembler _masm(&cbuf); 912 __ set(disp, O7); 913 if (index != R_G0_enc) { 914 __ add(O7, reg_to_register_object(index), O7); 915 } 916 index = R_O7_enc; 917 disp = 0; 918 } 919 } 920 921 if( disp == 0 ) { 922 // use reg-reg form 923 // bit 13 is already zero 924 instr |= index; 925 } else { 926 // use reg-imm form 927 instr |= 0x00002000; // set bit 13 to one 928 instr |= disp & 0x1FFF; 929 } 930 931 cbuf.insts()->emit_int32(instr); 932 933 #ifdef ASSERT 934 if (VerifyOops) { 935 MacroAssembler _masm(&cbuf); 936 if (is_verified_oop_base) { 937 __ verify_oop(reg_to_register_object(src1_enc)); 938 } 939 if (is_verified_oop_store) { 940 __ verify_oop(reg_to_register_object(dst_enc)); 941 } 942 if (tmp_enc != -1) { 943 __ mov(O7, reg_to_register_object(tmp_enc)); 944 } 945 if (is_verified_oop_load) { 946 __ verify_oop(reg_to_register_object(dst_enc)); 947 } 948 } 949 #endif 950 } 951 952 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) { 953 // The method which records debug information at every safepoint 954 // expects the call to be the first instruction in the snippet as 955 // it creates a PcDesc structure which tracks the offset of a call 956 // from the start of the codeBlob. This offset is computed as 957 // code_end() - code_begin() of the code which has been emitted 958 // so far. 959 // In this particular case we have skirted around the problem by 960 // putting the "mov" instruction in the delay slot but the problem 961 // may bite us again at some other point and a cleaner/generic 962 // solution using relocations would be needed. 963 MacroAssembler _masm(&cbuf); 964 __ set_inst_mark(); 965 966 // We flush the current window just so that there is a valid stack copy 967 // the fact that the current window becomes active again instantly is 968 // not a problem there is nothing live in it. 969 970 #ifdef ASSERT 971 int startpos = __ offset(); 972 #endif /* ASSERT */ 973 974 __ call((address)entry_point, rspec); 975 976 if (preserve_g2) __ delayed()->mov(G2, L7); 977 else __ delayed()->nop(); 978 979 if (preserve_g2) __ mov(L7, G2); 980 981 #ifdef ASSERT 982 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 983 // Trash argument dump slots. 984 __ set(0xb0b8ac0db0b8ac0d, G1); 985 __ mov(G1, G5); 986 __ stx(G1, SP, STACK_BIAS + 0x80); 987 __ stx(G1, SP, STACK_BIAS + 0x88); 988 __ stx(G1, SP, STACK_BIAS + 0x90); 989 __ stx(G1, SP, STACK_BIAS + 0x98); 990 __ stx(G1, SP, STACK_BIAS + 0xA0); 991 __ stx(G1, SP, STACK_BIAS + 0xA8); 992 } 993 #endif /*ASSERT*/ 994 } 995 996 //============================================================================= 997 // REQUIRED FUNCTIONALITY for encoding 998 void emit_lo(CodeBuffer &cbuf, int val) { } 999 void emit_hi(CodeBuffer &cbuf, int val) { } 1000 1001 1002 //============================================================================= 1003 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); 1004 1005 int Compile::ConstantTable::calculate_table_base_offset() const { 1006 if (UseRDPCForConstantTableBase) { 1007 // The table base offset might be less but then it fits into 1008 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). 1009 return Assembler::min_simm13(); 1010 } else { 1011 int offset = -(size() / 2); 1012 if (!Assembler::is_simm13(offset)) { 1013 offset = Assembler::min_simm13(); 1014 } 1015 return offset; 1016 } 1017 } 1018 1019 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 1020 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1021 ShouldNotReachHere(); 1022 } 1023 1024 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1025 Compile* C = ra_->C; 1026 Compile::ConstantTable& constant_table = C->constant_table(); 1027 MacroAssembler _masm(&cbuf); 1028 1029 Register r = as_Register(ra_->get_encode(this)); 1030 CodeSection* consts_section = __ code()->consts(); 1031 int consts_size = consts_section->align_at_start(consts_section->size()); 1032 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size); 1033 1034 if (UseRDPCForConstantTableBase) { 1035 // For the following RDPC logic to work correctly the consts 1036 // section must be allocated right before the insts section. This 1037 // assert checks for that. The layout and the SECT_* constants 1038 // are defined in src/share/vm/asm/codeBuffer.hpp. 1039 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); 1040 int insts_offset = __ offset(); 1041 1042 // Layout: 1043 // 1044 // |----------- consts section ------------|----------- insts section -----------... 1045 // |------ constant table -----|- padding -|------------------x---- 1046 // \ current PC (RDPC instruction) 1047 // |<------------- consts_size ----------->|<- insts_offset ->| 1048 // \ table base 1049 // The table base offset is later added to the load displacement 1050 // so it has to be negative. 1051 int table_base_offset = -(consts_size + insts_offset); 1052 int disp; 1053 1054 // If the displacement from the current PC to the constant table 1055 // base fits into simm13 we set the constant table base to the 1056 // current PC. 1057 if (Assembler::is_simm13(table_base_offset)) { 1058 constant_table.set_table_base_offset(table_base_offset); 1059 disp = 0; 1060 } else { 1061 // Otherwise we set the constant table base offset to the 1062 // maximum negative displacement of load instructions to keep 1063 // the disp as small as possible: 1064 // 1065 // |<------------- consts_size ----------->|<- insts_offset ->| 1066 // |<--------- min_simm13 --------->|<-------- disp --------->| 1067 // \ table base 1068 table_base_offset = Assembler::min_simm13(); 1069 constant_table.set_table_base_offset(table_base_offset); 1070 disp = (consts_size + insts_offset) + table_base_offset; 1071 } 1072 1073 __ rdpc(r); 1074 1075 if (disp == 0) { 1076 // Emitting an additional 'nop' instruction in order not to cause a code 1077 // size adjustment in the code following the table setup (if the instruction 1078 // immediately following after this section is a CTI). 1079 __ nop(); 1080 } 1081 else { 1082 assert(r != O7, "need temporary"); 1083 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); 1084 } 1085 } 1086 else { 1087 // Materialize the constant table base. 1088 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); 1089 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1090 AddressLiteral base(baseaddr, rspec); 1091 __ set(base, r); 1092 } 1093 } 1094 1095 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { 1096 if (UseRDPCForConstantTableBase) { 1097 // This is really the worst case but generally it's only 1 instruction. 1098 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; 1099 } else { 1100 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; 1101 } 1102 } 1103 1104 #ifndef PRODUCT 1105 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1106 char reg[128]; 1107 ra_->dump_register(this, reg); 1108 if (UseRDPCForConstantTableBase) { 1109 st->print("RDPC %s\t! constant table base", reg); 1110 } else { 1111 st->print("SET &constanttable,%s\t! constant table base", reg); 1112 } 1113 } 1114 #endif 1115 1116 1117 //============================================================================= 1118 1119 #ifndef PRODUCT 1120 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1121 Compile* C = ra_->C; 1122 1123 for (int i = 0; i < OptoPrologueNops; i++) { 1124 st->print_cr("NOP"); st->print("\t"); 1125 } 1126 1127 if( VerifyThread ) { 1128 st->print_cr("Verify_Thread"); st->print("\t"); 1129 } 1130 1131 size_t framesize = C->frame_size_in_bytes(); 1132 int bangsize = C->bang_size_in_bytes(); 1133 1134 // Calls to C2R adapters often do not accept exceptional returns. 1135 // We require that their callers must bang for them. But be careful, because 1136 // some VM calls (such as call site linkage) can use several kilobytes of 1137 // stack. But the stack safety zone should account for that. 1138 // See bugs 4446381, 4468289, 4497237. 1139 if (C->need_stack_bang(bangsize)) { 1140 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t"); 1141 } 1142 1143 if (Assembler::is_simm13(-framesize)) { 1144 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize); 1145 } else { 1146 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1147 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1148 st->print ("SAVE R_SP,R_G3,R_SP"); 1149 } 1150 1151 } 1152 #endif 1153 1154 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1155 Compile* C = ra_->C; 1156 MacroAssembler _masm(&cbuf); 1157 1158 for (int i = 0; i < OptoPrologueNops; i++) { 1159 __ nop(); 1160 } 1161 1162 __ verify_thread(); 1163 1164 size_t framesize = C->frame_size_in_bytes(); 1165 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1166 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1167 int bangsize = C->bang_size_in_bytes(); 1168 1169 // Calls to C2R adapters often do not accept exceptional returns. 1170 // We require that their callers must bang for them. But be careful, because 1171 // some VM calls (such as call site linkage) can use several kilobytes of 1172 // stack. But the stack safety zone should account for that. 1173 // See bugs 4446381, 4468289, 4497237. 1174 if (C->need_stack_bang(bangsize)) { 1175 __ generate_stack_overflow_check(bangsize); 1176 } 1177 1178 if (Assembler::is_simm13(-framesize)) { 1179 __ save(SP, -framesize, SP); 1180 } else { 1181 __ sethi(-framesize & ~0x3ff, G3); 1182 __ add(G3, -framesize & 0x3ff, G3); 1183 __ save(SP, G3, SP); 1184 } 1185 C->set_frame_complete( __ offset() ); 1186 1187 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { 1188 // NOTE: We set the table base offset here because users might be 1189 // emitted before MachConstantBaseNode. 1190 Compile::ConstantTable& constant_table = C->constant_table(); 1191 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 1192 } 1193 } 1194 1195 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1196 return MachNode::size(ra_); 1197 } 1198 1199 int MachPrologNode::reloc() const { 1200 return 10; // a large enough number 1201 } 1202 1203 //============================================================================= 1204 #ifndef PRODUCT 1205 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1206 Compile* C = ra_->C; 1207 1208 if(do_polling() && ra_->C->is_method_compilation()) { 1209 if (SafepointMechanism::uses_global_page_poll()) { 1210 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1211 } else { 1212 st->print("LDX [R_G2 + #poll_offset],L0\t! Load local polling address\n\t"); 1213 } 1214 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1215 } 1216 1217 if(do_polling()) { 1218 if (UseCBCond && !ra_->C->is_method_compilation()) { 1219 st->print("NOP\n\t"); 1220 } 1221 st->print("RET\n\t"); 1222 } 1223 1224 st->print("RESTORE"); 1225 } 1226 #endif 1227 1228 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1229 MacroAssembler _masm(&cbuf); 1230 Compile* C = ra_->C; 1231 1232 __ verify_thread(); 1233 1234 if (StackReservedPages > 0 && C->has_reserved_stack_access()) { 1235 __ reserved_stack_check(); 1236 } 1237 1238 // If this does safepoint polling, then do it here 1239 if(do_polling() && ra_->C->is_method_compilation()) { 1240 if (SafepointMechanism::uses_thread_local_poll()) { 1241 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), L0); 1242 } else { 1243 AddressLiteral polling_page(os::get_polling_page()); 1244 __ sethi(polling_page, L0); 1245 } 1246 __ relocate(relocInfo::poll_return_type); 1247 __ ld_ptr(L0, 0, G0); 1248 } 1249 1250 // If this is a return, then stuff the restore in the delay slot 1251 if(do_polling()) { 1252 if (UseCBCond && !ra_->C->is_method_compilation()) { 1253 // Insert extra padding for the case when the epilogue is preceded by 1254 // a cbcond jump, which can't be followed by a CTI instruction 1255 __ nop(); 1256 } 1257 __ ret(); 1258 __ delayed()->restore(); 1259 } else { 1260 __ restore(); 1261 } 1262 } 1263 1264 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1265 return MachNode::size(ra_); 1266 } 1267 1268 int MachEpilogNode::reloc() const { 1269 return 16; // a large enough number 1270 } 1271 1272 const Pipeline * MachEpilogNode::pipeline() const { 1273 return MachNode::pipeline_class(); 1274 } 1275 1276 int MachEpilogNode::safepoint_offset() const { 1277 assert(SafepointMechanism::uses_global_page_poll(), "sanity"); 1278 assert( do_polling(), "no return for this epilog node"); 1279 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; 1280 } 1281 1282 //============================================================================= 1283 1284 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1285 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1286 static enum RC rc_class( OptoReg::Name reg ) { 1287 if (!OptoReg::is_valid(reg)) return rc_bad; 1288 if (OptoReg::is_stack(reg)) return rc_stack; 1289 VMReg r = OptoReg::as_VMReg(reg); 1290 if (r->is_Register()) return rc_int; 1291 assert(r->is_FloatRegister(), "must be"); 1292 return rc_float; 1293 } 1294 1295 #ifndef PRODUCT 1296 ATTRIBUTE_PRINTF(2, 3) 1297 static void print_helper(outputStream* st, const char* format, ...) { 1298 const int tab_size = 8; 1299 if (st->position() > tab_size) { 1300 st->cr(); 1301 st->sp(); 1302 } 1303 va_list ap; 1304 va_start(ap, format); 1305 st->vprint(format, ap); 1306 va_end(ap); 1307 } 1308 #endif // !PRODUCT 1309 1310 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) { 1311 if (cbuf) { 1312 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1313 } 1314 #ifndef PRODUCT 1315 else { 1316 if (is_load) { 1317 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg)); 1318 } else { 1319 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset); 1320 } 1321 } 1322 #endif 1323 } 1324 1325 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) { 1326 if (cbuf) { 1327 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]); 1328 } 1329 #ifndef PRODUCT 1330 else { 1331 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst)); 1332 } 1333 #endif 1334 } 1335 1336 static void mach_spill_copy_implementation_helper(const MachNode* mach, 1337 CodeBuffer *cbuf, 1338 PhaseRegAlloc *ra_, 1339 outputStream* st) { 1340 // Get registers to move 1341 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1)); 1342 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1)); 1343 OptoReg::Name dst_second = ra_->get_reg_second(mach); 1344 OptoReg::Name dst_first = ra_->get_reg_first(mach); 1345 1346 enum RC src_second_rc = rc_class(src_second); 1347 enum RC src_first_rc = rc_class(src_first); 1348 enum RC dst_second_rc = rc_class(dst_second); 1349 enum RC dst_first_rc = rc_class(dst_first); 1350 1351 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register"); 1352 1353 if (src_first == dst_first && src_second == dst_second) { 1354 return; // Self copy, no move 1355 } 1356 1357 // -------------------------------------- 1358 // Check for mem-mem move. Load into unused float registers and fall into 1359 // the float-store case. 1360 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) { 1361 int offset = ra_->reg2offset(src_first); 1362 // Further check for aligned-adjacent pair, so we can use a double load 1363 if ((src_first&1) == 0 && src_first+1 == src_second) { 1364 src_second = OptoReg::Name(R_F31_num); 1365 src_second_rc = rc_float; 1366 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st); 1367 } else { 1368 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st); 1369 } 1370 src_first = OptoReg::Name(R_F30_num); 1371 src_first_rc = rc_float; 1372 } 1373 1374 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1375 int offset = ra_->reg2offset(src_second); 1376 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st); 1377 src_second = OptoReg::Name(R_F31_num); 1378 src_second_rc = rc_float; 1379 } 1380 1381 // -------------------------------------- 1382 // Check for float->int copy; requires a trip through memory 1383 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { 1384 int offset = frame::register_save_words*wordSize; 1385 if (cbuf) { 1386 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16); 1387 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1388 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1389 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16); 1390 } 1391 #ifndef PRODUCT 1392 else { 1393 print_helper(st, "SUB R_SP,16,R_SP"); 1394 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1395 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1396 print_helper(st, "ADD R_SP,16,R_SP"); 1397 } 1398 #endif 1399 } 1400 1401 // Check for float->int copy on T4 1402 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { 1403 // Further check for aligned-adjacent pair, so we can use a double move 1404 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1405 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st); 1406 return; 1407 } 1408 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st); 1409 } 1410 // Check for int->float copy on T4 1411 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { 1412 // Further check for aligned-adjacent pair, so we can use a double move 1413 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1414 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st); 1415 return; 1416 } 1417 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st); 1418 } 1419 1420 // -------------------------------------- 1421 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1422 // In such cases, I have to do the big-endian swap. For aligned targets, the 1423 // hardware does the flop for me. Doubles are always aligned, so no problem 1424 // there. Misaligned sources only come from native-long-returns (handled 1425 // special below). 1426 1427 // -------------------------------------- 1428 // Check for integer reg-reg copy 1429 if (src_first_rc == rc_int && dst_first_rc == rc_int) { 1430 // Else normal reg-reg copy 1431 assert(src_second != dst_first, "smashed second before evacuating it"); 1432 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st); 1433 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers"); 1434 // This moves an aligned adjacent pair. 1435 // See if we are done. 1436 if (src_first + 1 == src_second && dst_first + 1 == dst_second) { 1437 return; 1438 } 1439 } 1440 1441 // Check for integer store 1442 if (src_first_rc == rc_int && dst_first_rc == rc_stack) { 1443 int offset = ra_->reg2offset(dst_first); 1444 // Further check for aligned-adjacent pair, so we can use a double store 1445 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1446 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st); 1447 return; 1448 } 1449 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st); 1450 } 1451 1452 // Check for integer load 1453 if (dst_first_rc == rc_int && src_first_rc == rc_stack) { 1454 int offset = ra_->reg2offset(src_first); 1455 // Further check for aligned-adjacent pair, so we can use a double load 1456 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1457 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st); 1458 return; 1459 } 1460 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1461 } 1462 1463 // Check for float reg-reg copy 1464 if (src_first_rc == rc_float && dst_first_rc == rc_float) { 1465 // Further check for aligned-adjacent pair, so we can use a double move 1466 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1467 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st); 1468 return; 1469 } 1470 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st); 1471 } 1472 1473 // Check for float store 1474 if (src_first_rc == rc_float && dst_first_rc == rc_stack) { 1475 int offset = ra_->reg2offset(dst_first); 1476 // Further check for aligned-adjacent pair, so we can use a double store 1477 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1478 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st); 1479 return; 1480 } 1481 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1482 } 1483 1484 // Check for float load 1485 if (dst_first_rc == rc_float && src_first_rc == rc_stack) { 1486 int offset = ra_->reg2offset(src_first); 1487 // Further check for aligned-adjacent pair, so we can use a double load 1488 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1489 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st); 1490 return; 1491 } 1492 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st); 1493 } 1494 1495 // -------------------------------------------------------------------- 1496 // Check for hi bits still needing moving. Only happens for misaligned 1497 // arguments to native calls. 1498 if (src_second == dst_second) { 1499 return; // Self copy; no move 1500 } 1501 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad"); 1502 1503 Unimplemented(); 1504 } 1505 1506 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, 1507 PhaseRegAlloc *ra_, 1508 bool do_size, 1509 outputStream* st) const { 1510 assert(!do_size, "not supported"); 1511 mach_spill_copy_implementation_helper(this, cbuf, ra_, st); 1512 return 0; 1513 } 1514 1515 #ifndef PRODUCT 1516 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1517 implementation( NULL, ra_, false, st ); 1518 } 1519 #endif 1520 1521 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1522 implementation( &cbuf, ra_, false, NULL ); 1523 } 1524 1525 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1526 return MachNode::size(ra_); 1527 } 1528 1529 //============================================================================= 1530 #ifndef PRODUCT 1531 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const { 1532 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1533 } 1534 #endif 1535 1536 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1537 MacroAssembler _masm(&cbuf); 1538 for (int i = 0; i < _count; i += 1) { 1539 __ nop(); 1540 } 1541 } 1542 1543 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1544 return 4 * _count; 1545 } 1546 1547 1548 //============================================================================= 1549 #ifndef PRODUCT 1550 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1551 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1552 int reg = ra_->get_reg_first(this); 1553 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1554 } 1555 #endif 1556 1557 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1558 MacroAssembler _masm(&cbuf); 1559 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1560 int reg = ra_->get_encode(this); 1561 1562 if (Assembler::is_simm13(offset)) { 1563 __ add(SP, offset, reg_to_register_object(reg)); 1564 } else { 1565 __ set(offset, O7); 1566 __ add(SP, O7, reg_to_register_object(reg)); 1567 } 1568 } 1569 1570 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1571 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1572 assert(ra_ == ra_->C->regalloc(), "sanity"); 1573 return ra_->C->scratch_emit_size(this); 1574 } 1575 1576 //============================================================================= 1577 #ifndef PRODUCT 1578 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1579 st->print_cr("\nUEP:"); 1580 if (UseCompressedClassPointers) { 1581 assert(Universe::heap() != NULL, "java heap should be initialized"); 1582 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1583 if (Universe::narrow_klass_base() != 0) { 1584 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); 1585 if (Universe::narrow_klass_shift() != 0) { 1586 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1587 } 1588 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1589 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); 1590 } else { 1591 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1592 } 1593 } else { 1594 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1595 } 1596 st->print_cr("\tCMP R_G5,R_G3" ); 1597 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1598 } 1599 #endif 1600 1601 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1602 MacroAssembler _masm(&cbuf); 1603 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1604 Register temp_reg = G3; 1605 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1606 1607 // Load klass from receiver 1608 __ load_klass(O0, temp_reg); 1609 // Compare against expected klass 1610 __ cmp(temp_reg, G5_ic_reg); 1611 // Branch to miss code, checks xcc or icc depending 1612 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1613 } 1614 1615 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1616 return MachNode::size(ra_); 1617 } 1618 1619 1620 //============================================================================= 1621 1622 1623 // Emit exception handler code. 1624 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { 1625 Register temp_reg = G3; 1626 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1627 MacroAssembler _masm(&cbuf); 1628 1629 address base = __ start_a_stub(size_exception_handler()); 1630 if (base == NULL) { 1631 ciEnv::current()->record_failure("CodeCache is full"); 1632 return 0; // CodeBuffer::expand failed 1633 } 1634 1635 int offset = __ offset(); 1636 1637 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1638 __ delayed()->nop(); 1639 1640 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1641 1642 __ end_a_stub(); 1643 1644 return offset; 1645 } 1646 1647 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1648 // Can't use any of the current frame's registers as we may have deopted 1649 // at a poll and everything (including G3) can be live. 1650 Register temp_reg = L0; 1651 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1652 MacroAssembler _masm(&cbuf); 1653 1654 address base = __ start_a_stub(size_deopt_handler()); 1655 if (base == NULL) { 1656 ciEnv::current()->record_failure("CodeCache is full"); 1657 return 0; // CodeBuffer::expand failed 1658 } 1659 1660 int offset = __ offset(); 1661 __ save_frame(0); 1662 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1663 __ delayed()->restore(); 1664 1665 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1666 1667 __ end_a_stub(); 1668 return offset; 1669 1670 } 1671 1672 // Given a register encoding, produce a Integer Register object 1673 static Register reg_to_register_object(int register_encoding) { 1674 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1675 return as_Register(register_encoding); 1676 } 1677 1678 // Given a register encoding, produce a single-precision Float Register object 1679 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1680 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1681 return as_SingleFloatRegister(register_encoding); 1682 } 1683 1684 // Given a register encoding, produce a double-precision Float Register object 1685 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1686 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1687 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1688 return as_DoubleFloatRegister(register_encoding); 1689 } 1690 1691 const bool Matcher::match_rule_supported(int opcode) { 1692 if (!has_match_rule(opcode)) 1693 return false; 1694 1695 switch (opcode) { 1696 case Op_CountLeadingZerosI: 1697 case Op_CountLeadingZerosL: 1698 case Op_CountTrailingZerosI: 1699 case Op_CountTrailingZerosL: 1700 case Op_PopCountI: 1701 case Op_PopCountL: 1702 if (!UsePopCountInstruction) 1703 return false; 1704 case Op_CompareAndSwapL: 1705 case Op_CompareAndSwapP: 1706 if (!VM_Version::supports_cx8()) 1707 return false; 1708 break; 1709 } 1710 1711 return true; // Per default match rules are supported. 1712 } 1713 1714 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { 1715 1716 // TODO 1717 // identify extra cases that we might want to provide match rules for 1718 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen 1719 bool ret_value = match_rule_supported(opcode); 1720 // Add rules here. 1721 1722 return ret_value; // Per default match rules are supported. 1723 } 1724 1725 const bool Matcher::has_predicated_vectors(void) { 1726 return false; 1727 } 1728 1729 const int Matcher::float_pressure(int default_pressure_threshold) { 1730 return default_pressure_threshold; 1731 } 1732 1733 int Matcher::regnum_to_fpu_offset(int regnum) { 1734 return regnum - 32; // The FP registers are in the second chunk 1735 } 1736 1737 #ifdef ASSERT 1738 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1739 #endif 1740 1741 // Vector width in bytes 1742 const int Matcher::vector_width_in_bytes(BasicType bt) { 1743 assert(MaxVectorSize == 8, ""); 1744 return 8; 1745 } 1746 1747 // Vector ideal reg 1748 const uint Matcher::vector_ideal_reg(int size) { 1749 assert(MaxVectorSize == 8, ""); 1750 return Op_RegD; 1751 } 1752 1753 const uint Matcher::vector_shift_count_ideal_reg(int size) { 1754 fatal("vector shift is not supported"); 1755 return Node::NotAMachineReg; 1756 } 1757 1758 // Limits on vector size (number of elements) loaded into vector. 1759 const int Matcher::max_vector_size(const BasicType bt) { 1760 assert(is_java_primitive(bt), "only primitive type vectors"); 1761 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1762 } 1763 1764 const int Matcher::min_vector_size(const BasicType bt) { 1765 return max_vector_size(bt); // Same as max. 1766 } 1767 1768 // SPARC doesn't support misaligned vectors store/load. 1769 const bool Matcher::misaligned_vectors_ok() { 1770 return false; 1771 } 1772 1773 // Current (2013) SPARC platforms need to read original key 1774 // to construct decryption expanded key 1775 const bool Matcher::pass_original_key_for_aes() { 1776 return true; 1777 } 1778 1779 // NOTE: All currently supported SPARC HW provides fast conversion. 1780 const bool Matcher::convL2FSupported(void) { return true; } 1781 1782 // Is this branch offset short enough that a short branch can be used? 1783 // 1784 // NOTE: If the platform does not provide any short branch variants, then 1785 // this method should return false for offset 0. 1786 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1787 // The passed offset is relative to address of the branch. 1788 // Don't need to adjust the offset. 1789 return UseCBCond && Assembler::is_simm12(offset); 1790 } 1791 1792 const bool Matcher::isSimpleConstant64(jlong value) { 1793 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1794 // Depends on optimizations in MacroAssembler::setx. 1795 int hi = (int)(value >> 32); 1796 int lo = (int)(value & ~0); 1797 return (hi == 0) || (hi == -1) || (lo == 0); 1798 } 1799 1800 // No scaling for the parameter the ClearArray node. 1801 const bool Matcher::init_array_count_is_in_bytes = true; 1802 1803 // No additional cost for CMOVL. 1804 const int Matcher::long_cmove_cost() { return 0; } 1805 1806 // CMOVF/CMOVD are expensive on e.g., T4 and SPARC64. 1807 const int Matcher::float_cmove_cost() { 1808 return VM_Version::has_fast_cmove() ? 0 : ConditionalMoveLimit; 1809 } 1810 1811 // Does the CPU require late expand (see block.cpp for description of late expand)? 1812 const bool Matcher::require_postalloc_expand = false; 1813 1814 // Do we need to mask the count passed to shift instructions or does 1815 // the cpu only look at the lower 5/6 bits anyway? 1816 const bool Matcher::need_masked_shift_count = false; 1817 1818 bool Matcher::narrow_oop_use_complex_address() { 1819 assert(UseCompressedOops, "only for compressed oops code"); 1820 return false; 1821 } 1822 1823 bool Matcher::narrow_klass_use_complex_address() { 1824 assert(UseCompressedClassPointers, "only for compressed klass code"); 1825 return false; 1826 } 1827 1828 bool Matcher::const_oop_prefer_decode() { 1829 // TODO: Check if loading ConP from TOC in heap-based mode is better: 1830 // Prefer ConN+DecodeN over ConP in simple compressed oops mode. 1831 // return Universe::narrow_oop_base() == NULL; 1832 return true; 1833 } 1834 1835 bool Matcher::const_klass_prefer_decode() { 1836 // TODO: Check if loading ConP from TOC in heap-based mode is better: 1837 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. 1838 // return Universe::narrow_klass_base() == NULL; 1839 return true; 1840 } 1841 1842 // Is it better to copy float constants, or load them directly from memory? 1843 // Intel can load a float constant from a direct address, requiring no 1844 // extra registers. Most RISCs will have to materialize an address into a 1845 // register first, so they would do better to copy the constant from stack. 1846 const bool Matcher::rematerialize_float_constants = false; 1847 1848 // If CPU can load and store mis-aligned doubles directly then no fixup is 1849 // needed. Else we split the double into 2 integer pieces and move it 1850 // piece-by-piece. Only happens when passing doubles into C code as the 1851 // Java calling convention forces doubles to be aligned. 1852 const bool Matcher::misaligned_doubles_ok = true; 1853 1854 // No-op on SPARC. 1855 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1856 } 1857 1858 // Advertise here if the CPU requires explicit rounding operations 1859 // to implement the UseStrictFP mode. 1860 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1861 1862 // Are floats converted to double when stored to stack during deoptimization? 1863 // Sparc does not handle callee-save floats. 1864 bool Matcher::float_in_double() { return false; } 1865 1866 // Do ints take an entire long register or just half? 1867 // Note that we if-def off of _LP64. 1868 // The relevant question is how the int is callee-saved. In _LP64 1869 // the whole long is written but de-opt'ing will have to extract 1870 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1871 const bool Matcher::int_in_long = true; 1872 1873 // Return whether or not this register is ever used as an argument. This 1874 // function is used on startup to build the trampoline stubs in generateOptoStub. 1875 // Registers not mentioned will be killed by the VM call in the trampoline, and 1876 // arguments in those registers not be available to the callee. 1877 bool Matcher::can_be_java_arg( int reg ) { 1878 // Standard sparc 6 args in registers 1879 if( reg == R_I0_num || 1880 reg == R_I1_num || 1881 reg == R_I2_num || 1882 reg == R_I3_num || 1883 reg == R_I4_num || 1884 reg == R_I5_num ) return true; 1885 // 64-bit builds can pass 64-bit pointers and longs in 1886 // the high I registers 1887 if( reg == R_I0H_num || 1888 reg == R_I1H_num || 1889 reg == R_I2H_num || 1890 reg == R_I3H_num || 1891 reg == R_I4H_num || 1892 reg == R_I5H_num ) return true; 1893 1894 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1895 return true; 1896 } 1897 1898 // A few float args in registers 1899 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1900 1901 return false; 1902 } 1903 1904 bool Matcher::is_spillable_arg( int reg ) { 1905 return can_be_java_arg(reg); 1906 } 1907 1908 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 1909 // Use hardware SDIVX instruction when it is 1910 // faster than a code which use multiply. 1911 return VM_Version::has_fast_idiv(); 1912 } 1913 1914 // Register for DIVI projection of divmodI 1915 RegMask Matcher::divI_proj_mask() { 1916 ShouldNotReachHere(); 1917 return RegMask(); 1918 } 1919 1920 // Register for MODI projection of divmodI 1921 RegMask Matcher::modI_proj_mask() { 1922 ShouldNotReachHere(); 1923 return RegMask(); 1924 } 1925 1926 // Register for DIVL projection of divmodL 1927 RegMask Matcher::divL_proj_mask() { 1928 ShouldNotReachHere(); 1929 return RegMask(); 1930 } 1931 1932 // Register for MODL projection of divmodL 1933 RegMask Matcher::modL_proj_mask() { 1934 ShouldNotReachHere(); 1935 return RegMask(); 1936 } 1937 1938 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1939 return L7_REGP_mask(); 1940 } 1941 1942 1943 const bool Matcher::convi2l_type_required = true; 1944 1945 // Should the Matcher clone shifts on addressing modes, expecting them 1946 // to be subsumed into complex addressing expressions or compute them 1947 // into registers? 1948 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 1949 return clone_base_plus_offset_address(m, mstack, address_visited); 1950 } 1951 1952 void Compile::reshape_address(AddPNode* addp) { 1953 } 1954 1955 %} 1956 1957 1958 // The intptr_t operand types, defined by textual substitution. 1959 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1960 #define immX immL 1961 #define immX13 immL13 1962 #define immX13m7 immL13m7 1963 #define iRegX iRegL 1964 #define g1RegX g1RegL 1965 1966 //----------ENCODING BLOCK----------------------------------------------------- 1967 // This block specifies the encoding classes used by the compiler to output 1968 // byte streams. Encoding classes are parameterized macros used by 1969 // Machine Instruction Nodes in order to generate the bit encoding of the 1970 // instruction. Operands specify their base encoding interface with the 1971 // interface keyword. There are currently supported four interfaces, 1972 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1973 // operand to generate a function which returns its register number when 1974 // queried. CONST_INTER causes an operand to generate a function which 1975 // returns the value of the constant when queried. MEMORY_INTER causes an 1976 // operand to generate four functions which return the Base Register, the 1977 // Index Register, the Scale Value, and the Offset Value of the operand when 1978 // queried. COND_INTER causes an operand to generate six functions which 1979 // return the encoding code (ie - encoding bits for the instruction) 1980 // associated with each basic boolean condition for a conditional instruction. 1981 // 1982 // Instructions specify two basic values for encoding. Again, a function 1983 // is available to check if the constant displacement is an oop. They use the 1984 // ins_encode keyword to specify their encoding classes (which must be 1985 // a sequence of enc_class names, and their parameters, specified in 1986 // the encoding block), and they use the 1987 // opcode keyword to specify, in order, their primary, secondary, and 1988 // tertiary opcode. Only the opcode sections which a particular instruction 1989 // needs for encoding need to be specified. 1990 encode %{ 1991 enc_class enc_untested %{ 1992 #ifdef ASSERT 1993 MacroAssembler _masm(&cbuf); 1994 __ untested("encoding"); 1995 #endif 1996 %} 1997 1998 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 1999 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, 2000 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2001 %} 2002 2003 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 2004 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2005 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2006 %} 2007 2008 enc_class form3_mem_prefetch_read( memory mem ) %{ 2009 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2010 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2011 %} 2012 2013 enc_class form3_mem_prefetch_write( memory mem ) %{ 2014 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2015 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2016 %} 2017 2018 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2019 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2020 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2021 guarantee($mem$$index == R_G0_enc, "double index?"); 2022 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2023 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2024 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2025 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2026 %} 2027 2028 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2029 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2030 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2031 guarantee($mem$$index == R_G0_enc, "double index?"); 2032 // Load long with 2 instructions 2033 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2034 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2035 %} 2036 2037 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2038 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2039 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2040 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2041 %} 2042 2043 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2044 // Encode a reg-reg copy. If it is useless, then empty encoding. 2045 if( $rs2$$reg != $rd$$reg ) 2046 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 2047 %} 2048 2049 // Target lo half of long 2050 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 2051 // Encode a reg-reg copy. If it is useless, then empty encoding. 2052 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 2053 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2054 %} 2055 2056 // Source lo half of long 2057 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2058 // Encode a reg-reg copy. If it is useless, then empty encoding. 2059 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2060 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2061 %} 2062 2063 // Target hi half of long 2064 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2065 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2066 %} 2067 2068 // Source lo half of long, and leave it sign extended. 2069 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2070 // Sign extend low half 2071 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2072 %} 2073 2074 // Source hi half of long, and leave it sign extended. 2075 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2076 // Shift high half to low half 2077 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2078 %} 2079 2080 // Source hi half of long 2081 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2082 // Encode a reg-reg copy. If it is useless, then empty encoding. 2083 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2084 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2085 %} 2086 2087 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2088 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2089 %} 2090 2091 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2092 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2093 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2094 %} 2095 2096 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2097 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2098 // clear if nothing else is happening 2099 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2100 // blt,a,pn done 2101 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2102 // mov dst,-1 in delay slot 2103 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2104 %} 2105 2106 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2107 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2108 %} 2109 2110 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2111 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2112 %} 2113 2114 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2115 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2116 %} 2117 2118 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2119 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2120 %} 2121 2122 enc_class move_return_pc_to_o1() %{ 2123 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2124 %} 2125 2126 /* %%% merge with enc_to_bool */ 2127 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2128 MacroAssembler _masm(&cbuf); 2129 2130 Register src_reg = reg_to_register_object($src$$reg); 2131 Register dst_reg = reg_to_register_object($dst$$reg); 2132 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2133 %} 2134 2135 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2136 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2137 MacroAssembler _masm(&cbuf); 2138 2139 Register p_reg = reg_to_register_object($p$$reg); 2140 Register q_reg = reg_to_register_object($q$$reg); 2141 Register y_reg = reg_to_register_object($y$$reg); 2142 Register tmp_reg = reg_to_register_object($tmp$$reg); 2143 2144 __ subcc( p_reg, q_reg, p_reg ); 2145 __ add ( p_reg, y_reg, tmp_reg ); 2146 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2147 %} 2148 2149 enc_class form_d2i_helper(regD src, regF dst) %{ 2150 // fcmp %fcc0,$src,$src 2151 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2152 // branch %fcc0 not-nan, predict taken 2153 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2154 // fdtoi $src,$dst 2155 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2156 // fitos $dst,$dst (if nan) 2157 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2158 // clear $dst (if nan) 2159 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2160 // carry on here... 2161 %} 2162 2163 enc_class form_d2l_helper(regD src, regD dst) %{ 2164 // fcmp %fcc0,$src,$src check for NAN 2165 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2166 // branch %fcc0 not-nan, predict taken 2167 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2168 // fdtox $src,$dst convert in delay slot 2169 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2170 // fxtod $dst,$dst (if nan) 2171 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2172 // clear $dst (if nan) 2173 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2174 // carry on here... 2175 %} 2176 2177 enc_class form_f2i_helper(regF src, regF dst) %{ 2178 // fcmps %fcc0,$src,$src 2179 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2180 // branch %fcc0 not-nan, predict taken 2181 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2182 // fstoi $src,$dst 2183 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2184 // fitos $dst,$dst (if nan) 2185 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2186 // clear $dst (if nan) 2187 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2188 // carry on here... 2189 %} 2190 2191 enc_class form_f2l_helper(regF src, regD dst) %{ 2192 // fcmps %fcc0,$src,$src 2193 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2194 // branch %fcc0 not-nan, predict taken 2195 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2196 // fstox $src,$dst 2197 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2198 // fxtod $dst,$dst (if nan) 2199 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2200 // clear $dst (if nan) 2201 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2202 // carry on here... 2203 %} 2204 2205 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2206 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2207 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2208 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2209 2210 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2211 2212 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2213 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2214 2215 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2216 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2217 %} 2218 2219 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2220 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2221 %} 2222 2223 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2224 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2225 %} 2226 2227 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2228 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2229 %} 2230 2231 enc_class form3_convI2F(regF rs2, regF rd) %{ 2232 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2233 %} 2234 2235 // Encloding class for traceable jumps 2236 enc_class form_jmpl(g3RegP dest) %{ 2237 emit_jmpl(cbuf, $dest$$reg); 2238 %} 2239 2240 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2241 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2242 %} 2243 2244 enc_class form2_nop() %{ 2245 emit_nop(cbuf); 2246 %} 2247 2248 enc_class form2_illtrap() %{ 2249 emit_illtrap(cbuf); 2250 %} 2251 2252 2253 // Compare longs and convert into -1, 0, 1. 2254 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2255 // CMP $src1,$src2 2256 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2257 // blt,a,pn done 2258 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2259 // mov dst,-1 in delay slot 2260 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2261 // bgt,a,pn done 2262 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2263 // mov dst,1 in delay slot 2264 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2265 // CLR $dst 2266 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2267 %} 2268 2269 enc_class enc_PartialSubtypeCheck() %{ 2270 MacroAssembler _masm(&cbuf); 2271 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2272 __ delayed()->nop(); 2273 %} 2274 2275 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ 2276 MacroAssembler _masm(&cbuf); 2277 Label* L = $labl$$label; 2278 Assembler::Predict predict_taken = 2279 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2280 2281 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 2282 __ delayed()->nop(); 2283 %} 2284 2285 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2286 MacroAssembler _masm(&cbuf); 2287 Label* L = $labl$$label; 2288 Assembler::Predict predict_taken = 2289 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2290 2291 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); 2292 __ delayed()->nop(); 2293 %} 2294 2295 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2296 int op = (Assembler::arith_op << 30) | 2297 ($dst$$reg << 25) | 2298 (Assembler::movcc_op3 << 19) | 2299 (1 << 18) | // cc2 bit for 'icc' 2300 ($cmp$$cmpcode << 14) | 2301 (0 << 13) | // select register move 2302 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2303 ($src$$reg << 0); 2304 cbuf.insts()->emit_int32(op); 2305 %} 2306 2307 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2308 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2309 int op = (Assembler::arith_op << 30) | 2310 ($dst$$reg << 25) | 2311 (Assembler::movcc_op3 << 19) | 2312 (1 << 18) | // cc2 bit for 'icc' 2313 ($cmp$$cmpcode << 14) | 2314 (1 << 13) | // select immediate move 2315 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2316 (simm11 << 0); 2317 cbuf.insts()->emit_int32(op); 2318 %} 2319 2320 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2321 int op = (Assembler::arith_op << 30) | 2322 ($dst$$reg << 25) | 2323 (Assembler::movcc_op3 << 19) | 2324 (0 << 18) | // cc2 bit for 'fccX' 2325 ($cmp$$cmpcode << 14) | 2326 (0 << 13) | // select register move 2327 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2328 ($src$$reg << 0); 2329 cbuf.insts()->emit_int32(op); 2330 %} 2331 2332 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2333 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2334 int op = (Assembler::arith_op << 30) | 2335 ($dst$$reg << 25) | 2336 (Assembler::movcc_op3 << 19) | 2337 (0 << 18) | // cc2 bit for 'fccX' 2338 ($cmp$$cmpcode << 14) | 2339 (1 << 13) | // select immediate move 2340 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2341 (simm11 << 0); 2342 cbuf.insts()->emit_int32(op); 2343 %} 2344 2345 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2346 int op = (Assembler::arith_op << 30) | 2347 ($dst$$reg << 25) | 2348 (Assembler::fpop2_op3 << 19) | 2349 (0 << 18) | 2350 ($cmp$$cmpcode << 14) | 2351 (1 << 13) | // select register move 2352 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2353 ($primary << 5) | // select single, double or quad 2354 ($src$$reg << 0); 2355 cbuf.insts()->emit_int32(op); 2356 %} 2357 2358 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2359 int op = (Assembler::arith_op << 30) | 2360 ($dst$$reg << 25) | 2361 (Assembler::fpop2_op3 << 19) | 2362 (0 << 18) | 2363 ($cmp$$cmpcode << 14) | 2364 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2365 ($primary << 5) | // select single, double or quad 2366 ($src$$reg << 0); 2367 cbuf.insts()->emit_int32(op); 2368 %} 2369 2370 // Used by the MIN/MAX encodings. Same as a CMOV, but 2371 // the condition comes from opcode-field instead of an argument. 2372 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2373 int op = (Assembler::arith_op << 30) | 2374 ($dst$$reg << 25) | 2375 (Assembler::movcc_op3 << 19) | 2376 (1 << 18) | // cc2 bit for 'icc' 2377 ($primary << 14) | 2378 (0 << 13) | // select register move 2379 (0 << 11) | // cc1, cc0 bits for 'icc' 2380 ($src$$reg << 0); 2381 cbuf.insts()->emit_int32(op); 2382 %} 2383 2384 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2385 int op = (Assembler::arith_op << 30) | 2386 ($dst$$reg << 25) | 2387 (Assembler::movcc_op3 << 19) | 2388 (6 << 16) | // cc2 bit for 'xcc' 2389 ($primary << 14) | 2390 (0 << 13) | // select register move 2391 (0 << 11) | // cc1, cc0 bits for 'icc' 2392 ($src$$reg << 0); 2393 cbuf.insts()->emit_int32(op); 2394 %} 2395 2396 enc_class Set13( immI13 src, iRegI rd ) %{ 2397 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2398 %} 2399 2400 enc_class SetHi22( immI src, iRegI rd ) %{ 2401 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2402 %} 2403 2404 enc_class Set32( immI src, iRegI rd ) %{ 2405 MacroAssembler _masm(&cbuf); 2406 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2407 %} 2408 2409 enc_class call_epilog %{ 2410 if( VerifyStackAtCalls ) { 2411 MacroAssembler _masm(&cbuf); 2412 int framesize = ra_->C->frame_size_in_bytes(); 2413 Register temp_reg = G3; 2414 __ add(SP, framesize, temp_reg); 2415 __ cmp(temp_reg, FP); 2416 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2417 } 2418 %} 2419 2420 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2421 // to G1 so the register allocator will not have to deal with the misaligned register 2422 // pair. 2423 enc_class adjust_long_from_native_call %{ 2424 %} 2425 2426 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2427 // CALL directly to the runtime 2428 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2429 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true); 2430 %} 2431 2432 enc_class preserve_SP %{ 2433 MacroAssembler _masm(&cbuf); 2434 __ mov(SP, L7_mh_SP_save); 2435 %} 2436 2437 enc_class restore_SP %{ 2438 MacroAssembler _masm(&cbuf); 2439 __ mov(L7_mh_SP_save, SP); 2440 %} 2441 2442 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2443 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2444 // who we intended to call. 2445 if (!_method) { 2446 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec()); 2447 } else { 2448 int method_index = resolved_method_index(cbuf); 2449 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index) 2450 : static_call_Relocation::spec(method_index); 2451 emit_call_reloc(cbuf, $meth$$method, rspec); 2452 2453 // Emit stub for static call. 2454 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 2455 if (stub == NULL) { 2456 ciEnv::current()->record_failure("CodeCache is full"); 2457 return; 2458 } 2459 } 2460 %} 2461 2462 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2463 MacroAssembler _masm(&cbuf); 2464 __ set_inst_mark(); 2465 int vtable_index = this->_vtable_index; 2466 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2467 if (vtable_index < 0) { 2468 // must be invalid_vtable_index, not nonvirtual_vtable_index 2469 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 2470 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2471 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2472 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2473 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf)); 2474 } else { 2475 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2476 // Just go thru the vtable 2477 // get receiver klass (receiver already checked for non-null) 2478 // If we end up going thru a c2i adapter interpreter expects method in G5 2479 int off = __ offset(); 2480 __ load_klass(O0, G3_scratch); 2481 int klass_load_size; 2482 if (UseCompressedClassPointers) { 2483 assert(Universe::heap() != NULL, "java heap should be initialized"); 2484 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 2485 } else { 2486 klass_load_size = 1*BytesPerInstWord; 2487 } 2488 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes(); 2489 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 2490 if (Assembler::is_simm13(v_off)) { 2491 __ ld_ptr(G3, v_off, G5_method); 2492 } else { 2493 // Generate 2 instructions 2494 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2495 __ or3(G5_method, v_off & 0x3ff, G5_method); 2496 // ld_ptr, set_hi, set 2497 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2498 "Unexpected instruction size(s)"); 2499 __ ld_ptr(G3, G5_method, G5_method); 2500 } 2501 // NOTE: for vtable dispatches, the vtable entry will never be null. 2502 // However it may very well end up in handle_wrong_method if the 2503 // method is abstract for the particular class. 2504 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); 2505 // jump to target (either compiled code or c2iadapter) 2506 __ jmpl(G3_scratch, G0, O7); 2507 __ delayed()->nop(); 2508 } 2509 %} 2510 2511 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2512 MacroAssembler _masm(&cbuf); 2513 2514 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2515 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2516 // we might be calling a C2I adapter which needs it. 2517 2518 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2519 // Load nmethod 2520 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); 2521 2522 // CALL to compiled java, indirect the contents of G3 2523 __ set_inst_mark(); 2524 __ callr(temp_reg, G0); 2525 __ delayed()->nop(); 2526 %} 2527 2528 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2529 MacroAssembler _masm(&cbuf); 2530 Register Rdividend = reg_to_register_object($src1$$reg); 2531 Register Rdivisor = reg_to_register_object($src2$$reg); 2532 Register Rresult = reg_to_register_object($dst$$reg); 2533 2534 __ sra(Rdivisor, 0, Rdivisor); 2535 __ sra(Rdividend, 0, Rdividend); 2536 __ sdivx(Rdividend, Rdivisor, Rresult); 2537 %} 2538 2539 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2540 MacroAssembler _masm(&cbuf); 2541 2542 Register Rdividend = reg_to_register_object($src1$$reg); 2543 int divisor = $imm$$constant; 2544 Register Rresult = reg_to_register_object($dst$$reg); 2545 2546 __ sra(Rdividend, 0, Rdividend); 2547 __ sdivx(Rdividend, divisor, Rresult); 2548 %} 2549 2550 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2551 MacroAssembler _masm(&cbuf); 2552 Register Rsrc1 = reg_to_register_object($src1$$reg); 2553 Register Rsrc2 = reg_to_register_object($src2$$reg); 2554 Register Rdst = reg_to_register_object($dst$$reg); 2555 2556 __ sra( Rsrc1, 0, Rsrc1 ); 2557 __ sra( Rsrc2, 0, Rsrc2 ); 2558 __ mulx( Rsrc1, Rsrc2, Rdst ); 2559 __ srlx( Rdst, 32, Rdst ); 2560 %} 2561 2562 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2563 MacroAssembler _masm(&cbuf); 2564 Register Rdividend = reg_to_register_object($src1$$reg); 2565 Register Rdivisor = reg_to_register_object($src2$$reg); 2566 Register Rresult = reg_to_register_object($dst$$reg); 2567 Register Rscratch = reg_to_register_object($scratch$$reg); 2568 2569 assert(Rdividend != Rscratch, ""); 2570 assert(Rdivisor != Rscratch, ""); 2571 2572 __ sra(Rdividend, 0, Rdividend); 2573 __ sra(Rdivisor, 0, Rdivisor); 2574 __ sdivx(Rdividend, Rdivisor, Rscratch); 2575 __ mulx(Rscratch, Rdivisor, Rscratch); 2576 __ sub(Rdividend, Rscratch, Rresult); 2577 %} 2578 2579 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2580 MacroAssembler _masm(&cbuf); 2581 2582 Register Rdividend = reg_to_register_object($src1$$reg); 2583 int divisor = $imm$$constant; 2584 Register Rresult = reg_to_register_object($dst$$reg); 2585 Register Rscratch = reg_to_register_object($scratch$$reg); 2586 2587 assert(Rdividend != Rscratch, ""); 2588 2589 __ sra(Rdividend, 0, Rdividend); 2590 __ sdivx(Rdividend, divisor, Rscratch); 2591 __ mulx(Rscratch, divisor, Rscratch); 2592 __ sub(Rdividend, Rscratch, Rresult); 2593 %} 2594 2595 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2596 MacroAssembler _masm(&cbuf); 2597 2598 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2599 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2600 2601 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2602 %} 2603 2604 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2605 MacroAssembler _masm(&cbuf); 2606 2607 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2608 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2609 2610 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2611 %} 2612 2613 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2614 MacroAssembler _masm(&cbuf); 2615 2616 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2617 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2618 2619 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2620 %} 2621 2622 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2623 MacroAssembler _masm(&cbuf); 2624 2625 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2626 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2627 2628 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2629 %} 2630 2631 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2632 MacroAssembler _masm(&cbuf); 2633 2634 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2635 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2636 2637 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2638 %} 2639 2640 2641 enc_class fmadds (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{ 2642 MacroAssembler _masm(&cbuf); 2643 2644 FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg); 2645 FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg); 2646 FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg); 2647 FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg); 2648 2649 __ fmadd(FloatRegisterImpl::S, Fra, Frb, Frc, Frd); 2650 %} 2651 2652 enc_class fmaddd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{ 2653 MacroAssembler _masm(&cbuf); 2654 2655 FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg); 2656 FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg); 2657 FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg); 2658 FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg); 2659 2660 __ fmadd(FloatRegisterImpl::D, Fra, Frb, Frc, Frd); 2661 %} 2662 2663 enc_class fmsubs (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{ 2664 MacroAssembler _masm(&cbuf); 2665 2666 FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg); 2667 FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg); 2668 FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg); 2669 FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg); 2670 2671 __ fmsub(FloatRegisterImpl::S, Fra, Frb, Frc, Frd); 2672 %} 2673 2674 enc_class fmsubd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{ 2675 MacroAssembler _masm(&cbuf); 2676 2677 FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg); 2678 FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg); 2679 FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg); 2680 FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg); 2681 2682 __ fmsub(FloatRegisterImpl::D, Fra, Frb, Frc, Frd); 2683 %} 2684 2685 enc_class fnmadds (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{ 2686 MacroAssembler _masm(&cbuf); 2687 2688 FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg); 2689 FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg); 2690 FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg); 2691 FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg); 2692 2693 __ fnmadd(FloatRegisterImpl::S, Fra, Frb, Frc, Frd); 2694 %} 2695 2696 enc_class fnmaddd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{ 2697 MacroAssembler _masm(&cbuf); 2698 2699 FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg); 2700 FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg); 2701 FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg); 2702 FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg); 2703 2704 __ fnmadd(FloatRegisterImpl::D, Fra, Frb, Frc, Frd); 2705 %} 2706 2707 enc_class fnmsubs (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{ 2708 MacroAssembler _masm(&cbuf); 2709 2710 FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg); 2711 FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg); 2712 FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg); 2713 FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg); 2714 2715 __ fnmsub(FloatRegisterImpl::S, Fra, Frb, Frc, Frd); 2716 %} 2717 2718 enc_class fnmsubd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{ 2719 MacroAssembler _masm(&cbuf); 2720 2721 FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg); 2722 FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg); 2723 FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg); 2724 FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg); 2725 2726 __ fnmsub(FloatRegisterImpl::D, Fra, Frb, Frc, Frd); 2727 %} 2728 2729 2730 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2731 MacroAssembler _masm(&cbuf); 2732 2733 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2734 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2735 2736 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2737 %} 2738 2739 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2740 MacroAssembler _masm(&cbuf); 2741 2742 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2743 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2744 2745 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2746 %} 2747 2748 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2749 MacroAssembler _masm(&cbuf); 2750 2751 Register Roop = reg_to_register_object($oop$$reg); 2752 Register Rbox = reg_to_register_object($box$$reg); 2753 Register Rscratch = reg_to_register_object($scratch$$reg); 2754 Register Rmark = reg_to_register_object($scratch2$$reg); 2755 2756 assert(Roop != Rscratch, ""); 2757 assert(Roop != Rmark, ""); 2758 assert(Rbox != Rscratch, ""); 2759 assert(Rbox != Rmark, ""); 2760 2761 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2762 %} 2763 2764 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2765 MacroAssembler _masm(&cbuf); 2766 2767 Register Roop = reg_to_register_object($oop$$reg); 2768 Register Rbox = reg_to_register_object($box$$reg); 2769 Register Rscratch = reg_to_register_object($scratch$$reg); 2770 Register Rmark = reg_to_register_object($scratch2$$reg); 2771 2772 assert(Roop != Rscratch, ""); 2773 assert(Roop != Rmark, ""); 2774 assert(Rbox != Rscratch, ""); 2775 assert(Rbox != Rmark, ""); 2776 2777 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2778 %} 2779 2780 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2781 MacroAssembler _masm(&cbuf); 2782 Register Rmem = reg_to_register_object($mem$$reg); 2783 Register Rold = reg_to_register_object($old$$reg); 2784 Register Rnew = reg_to_register_object($new$$reg); 2785 2786 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2787 __ cmp( Rold, Rnew ); 2788 %} 2789 2790 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2791 Register Rmem = reg_to_register_object($mem$$reg); 2792 Register Rold = reg_to_register_object($old$$reg); 2793 Register Rnew = reg_to_register_object($new$$reg); 2794 2795 MacroAssembler _masm(&cbuf); 2796 __ mov(Rnew, O7); 2797 __ casx(Rmem, Rold, O7); 2798 __ cmp( Rold, O7 ); 2799 %} 2800 2801 // raw int cas, used for compareAndSwap 2802 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2803 Register Rmem = reg_to_register_object($mem$$reg); 2804 Register Rold = reg_to_register_object($old$$reg); 2805 Register Rnew = reg_to_register_object($new$$reg); 2806 2807 MacroAssembler _masm(&cbuf); 2808 __ mov(Rnew, O7); 2809 __ cas(Rmem, Rold, O7); 2810 __ cmp( Rold, O7 ); 2811 %} 2812 2813 // raw int cas without using tmp register for compareAndExchange 2814 enc_class enc_casi_exch( iRegP mem, iRegL old, iRegL new) %{ 2815 Register Rmem = reg_to_register_object($mem$$reg); 2816 Register Rold = reg_to_register_object($old$$reg); 2817 Register Rnew = reg_to_register_object($new$$reg); 2818 2819 MacroAssembler _masm(&cbuf); 2820 __ cas(Rmem, Rold, Rnew); 2821 %} 2822 2823 // 64-bit cas without using tmp register for compareAndExchange 2824 enc_class enc_casx_exch( iRegP mem, iRegL old, iRegL new) %{ 2825 Register Rmem = reg_to_register_object($mem$$reg); 2826 Register Rold = reg_to_register_object($old$$reg); 2827 Register Rnew = reg_to_register_object($new$$reg); 2828 2829 MacroAssembler _masm(&cbuf); 2830 __ casx(Rmem, Rold, Rnew); 2831 %} 2832 2833 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2834 Register Rres = reg_to_register_object($res$$reg); 2835 2836 MacroAssembler _masm(&cbuf); 2837 __ mov(1, Rres); 2838 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2839 %} 2840 2841 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2842 Register Rres = reg_to_register_object($res$$reg); 2843 2844 MacroAssembler _masm(&cbuf); 2845 __ mov(1, Rres); 2846 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2847 %} 2848 2849 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2850 MacroAssembler _masm(&cbuf); 2851 Register Rdst = reg_to_register_object($dst$$reg); 2852 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2853 : reg_to_DoubleFloatRegister_object($src1$$reg); 2854 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2855 : reg_to_DoubleFloatRegister_object($src2$$reg); 2856 2857 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2858 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2859 %} 2860 2861 enc_class enc_rethrow() %{ 2862 cbuf.set_insts_mark(); 2863 Register temp_reg = G3; 2864 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 2865 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 2866 MacroAssembler _masm(&cbuf); 2867 #ifdef ASSERT 2868 __ save_frame(0); 2869 AddressLiteral last_rethrow_addrlit(&last_rethrow); 2870 __ sethi(last_rethrow_addrlit, L1); 2871 Address addr(L1, last_rethrow_addrlit.low10()); 2872 __ rdpc(L2); 2873 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 2874 __ st_ptr(L2, addr); 2875 __ restore(); 2876 #endif 2877 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 2878 __ delayed()->nop(); 2879 %} 2880 2881 enc_class emit_mem_nop() %{ 2882 // Generates the instruction LDUXA [o6,g0],#0x82,g0 2883 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 2884 %} 2885 2886 enc_class emit_fadd_nop() %{ 2887 // Generates the instruction FMOVS f31,f31 2888 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 2889 %} 2890 2891 enc_class emit_br_nop() %{ 2892 // Generates the instruction BPN,PN . 2893 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 2894 %} 2895 2896 enc_class enc_membar_acquire %{ 2897 MacroAssembler _masm(&cbuf); 2898 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 2899 %} 2900 2901 enc_class enc_membar_release %{ 2902 MacroAssembler _masm(&cbuf); 2903 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 2904 %} 2905 2906 enc_class enc_membar_volatile %{ 2907 MacroAssembler _masm(&cbuf); 2908 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 2909 %} 2910 2911 %} 2912 2913 //----------FRAME-------------------------------------------------------------- 2914 // Definition of frame structure and management information. 2915 // 2916 // S T A C K L A Y O U T Allocators stack-slot number 2917 // | (to get allocators register number 2918 // G Owned by | | v add VMRegImpl::stack0) 2919 // r CALLER | | 2920 // o | +--------+ pad to even-align allocators stack-slot 2921 // w V | pad0 | numbers; owned by CALLER 2922 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 2923 // h ^ | in | 5 2924 // | | args | 4 Holes in incoming args owned by SELF 2925 // | | | | 3 2926 // | | +--------+ 2927 // V | | old out| Empty on Intel, window on Sparc 2928 // | old |preserve| Must be even aligned. 2929 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 2930 // | | in | 3 area for Intel ret address 2931 // Owned by |preserve| Empty on Sparc. 2932 // SELF +--------+ 2933 // | | pad2 | 2 pad to align old SP 2934 // | +--------+ 1 2935 // | | locks | 0 2936 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 2937 // | | pad1 | 11 pad to align new SP 2938 // | +--------+ 2939 // | | | 10 2940 // | | spills | 9 spills 2941 // V | | 8 (pad0 slot for callee) 2942 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 2943 // ^ | out | 7 2944 // | | args | 6 Holes in outgoing args owned by CALLEE 2945 // Owned by +--------+ 2946 // CALLEE | new out| 6 Empty on Intel, window on Sparc 2947 // | new |preserve| Must be even-aligned. 2948 // | SP-+--------+----> Matcher::_new_SP, even aligned 2949 // | | | 2950 // 2951 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 2952 // known from SELF's arguments and the Java calling convention. 2953 // Region 6-7 is determined per call site. 2954 // Note 2: If the calling convention leaves holes in the incoming argument 2955 // area, those holes are owned by SELF. Holes in the outgoing area 2956 // are owned by the CALLEE. Holes should not be nessecary in the 2957 // incoming area, as the Java calling convention is completely under 2958 // the control of the AD file. Doubles can be sorted and packed to 2959 // avoid holes. Holes in the outgoing arguments may be necessary for 2960 // varargs C calling conventions. 2961 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 2962 // even aligned with pad0 as needed. 2963 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 2964 // region 6-11 is even aligned; it may be padded out more so that 2965 // the region from SP to FP meets the minimum stack alignment. 2966 2967 frame %{ 2968 // What direction does stack grow in (assumed to be same for native & Java) 2969 stack_direction(TOWARDS_LOW); 2970 2971 // These two registers define part of the calling convention 2972 // between compiled code and the interpreter. 2973 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C 2974 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 2975 2976 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 2977 cisc_spilling_operand_name(indOffset); 2978 2979 // Number of stack slots consumed by a Monitor enter 2980 sync_stack_slots(2); 2981 2982 // Compiled code's Frame Pointer 2983 frame_pointer(R_SP); 2984 2985 // Stack alignment requirement 2986 stack_alignment(StackAlignmentInBytes); 2987 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 2988 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 2989 2990 // Number of stack slots between incoming argument block and the start of 2991 // a new frame. The PROLOG must add this many slots to the stack. The 2992 // EPILOG must remove this many slots. 2993 in_preserve_stack_slots(0); 2994 2995 // Number of outgoing stack slots killed above the out_preserve_stack_slots 2996 // for calls to C. Supports the var-args backing area for register parms. 2997 // ADLC doesn't support parsing expressions, so I folded the math by hand. 2998 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 2999 varargs_C_out_slots_killed(12); 3000 3001 // The after-PROLOG location of the return address. Location of 3002 // return address specifies a type (REG or STACK) and a number 3003 // representing the register number (i.e. - use a register name) or 3004 // stack slot. 3005 return_addr(REG R_I7); // Ret Addr is in register I7 3006 3007 // Body of function which returns an OptoRegs array locating 3008 // arguments either in registers or in stack slots for calling 3009 // java 3010 calling_convention %{ 3011 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3012 3013 %} 3014 3015 // Body of function which returns an OptoRegs array locating 3016 // arguments either in registers or in stack slots for calling 3017 // C. 3018 c_calling_convention %{ 3019 // This is obviously always outgoing 3020 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3021 %} 3022 3023 // Location of native (C/C++) and interpreter return values. This is specified to 3024 // be the same as Java. In the 32-bit VM, long values are actually returned from 3025 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3026 // to and from the register pairs is done by the appropriate call and epilog 3027 // opcodes. This simplifies the register allocator. 3028 c_return_value %{ 3029 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3030 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3031 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3032 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3033 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3034 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3035 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3036 %} 3037 3038 // Location of compiled Java return values. Same as C 3039 return_value %{ 3040 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3041 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3042 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3043 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3044 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3045 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3046 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3047 %} 3048 3049 %} 3050 3051 3052 //----------ATTRIBUTES--------------------------------------------------------- 3053 //----------Operand Attributes------------------------------------------------- 3054 op_attrib op_cost(1); // Required cost attribute 3055 3056 //----------Instruction Attributes--------------------------------------------- 3057 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3058 ins_attrib ins_size(32); // Required size attribute (in bits) 3059 3060 // avoid_back_to_back attribute is an expression that must return 3061 // one of the following values defined in MachNode: 3062 // AVOID_NONE - instruction can be placed anywhere 3063 // AVOID_BEFORE - instruction cannot be placed after an 3064 // instruction with MachNode::AVOID_AFTER 3065 // AVOID_AFTER - the next instruction cannot be the one 3066 // with MachNode::AVOID_BEFORE 3067 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at 3068 // the same time 3069 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE); 3070 3071 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3072 // non-matching short branch variant of some 3073 // long branch? 3074 3075 //----------OPERANDS----------------------------------------------------------- 3076 // Operand definitions must precede instruction definitions for correct parsing 3077 // in the ADLC because operands constitute user defined types which are used in 3078 // instruction definitions. 3079 3080 //----------Simple Operands---------------------------------------------------- 3081 // Immediate Operands 3082 // Integer Immediate: 32-bit 3083 operand immI() %{ 3084 match(ConI); 3085 3086 op_cost(0); 3087 // formats are generated automatically for constants and base registers 3088 format %{ %} 3089 interface(CONST_INTER); 3090 %} 3091 3092 // Integer Immediate: 0-bit 3093 operand immI0() %{ 3094 predicate(n->get_int() == 0); 3095 match(ConI); 3096 op_cost(0); 3097 3098 format %{ %} 3099 interface(CONST_INTER); 3100 %} 3101 3102 // Integer Immediate: 5-bit 3103 operand immI5() %{ 3104 predicate(Assembler::is_simm5(n->get_int())); 3105 match(ConI); 3106 op_cost(0); 3107 format %{ %} 3108 interface(CONST_INTER); 3109 %} 3110 3111 // Integer Immediate: 8-bit 3112 operand immI8() %{ 3113 predicate(Assembler::is_simm8(n->get_int())); 3114 match(ConI); 3115 op_cost(0); 3116 format %{ %} 3117 interface(CONST_INTER); 3118 %} 3119 3120 // Integer Immediate: the value 10 3121 operand immI10() %{ 3122 predicate(n->get_int() == 10); 3123 match(ConI); 3124 op_cost(0); 3125 3126 format %{ %} 3127 interface(CONST_INTER); 3128 %} 3129 3130 // Integer Immediate: 11-bit 3131 operand immI11() %{ 3132 predicate(Assembler::is_simm11(n->get_int())); 3133 match(ConI); 3134 op_cost(0); 3135 format %{ %} 3136 interface(CONST_INTER); 3137 %} 3138 3139 // Integer Immediate: 13-bit 3140 operand immI13() %{ 3141 predicate(Assembler::is_simm13(n->get_int())); 3142 match(ConI); 3143 op_cost(0); 3144 3145 format %{ %} 3146 interface(CONST_INTER); 3147 %} 3148 3149 // Integer Immediate: 13-bit minus 7 3150 operand immI13m7() %{ 3151 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3152 match(ConI); 3153 op_cost(0); 3154 3155 format %{ %} 3156 interface(CONST_INTER); 3157 %} 3158 3159 // Integer Immediate: 16-bit 3160 operand immI16() %{ 3161 predicate(Assembler::is_simm16(n->get_int())); 3162 match(ConI); 3163 op_cost(0); 3164 format %{ %} 3165 interface(CONST_INTER); 3166 %} 3167 3168 // Integer Immediate: the values 1-31 3169 operand immI_1_31() %{ 3170 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3171 match(ConI); 3172 op_cost(0); 3173 3174 format %{ %} 3175 interface(CONST_INTER); 3176 %} 3177 3178 // Integer Immediate: the values 32-63 3179 operand immI_32_63() %{ 3180 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3181 match(ConI); 3182 op_cost(0); 3183 3184 format %{ %} 3185 interface(CONST_INTER); 3186 %} 3187 3188 // Immediates for special shifts (sign extend) 3189 3190 // Integer Immediate: the value 16 3191 operand immI_16() %{ 3192 predicate(n->get_int() == 16); 3193 match(ConI); 3194 op_cost(0); 3195 3196 format %{ %} 3197 interface(CONST_INTER); 3198 %} 3199 3200 // Integer Immediate: the value 24 3201 operand immI_24() %{ 3202 predicate(n->get_int() == 24); 3203 match(ConI); 3204 op_cost(0); 3205 3206 format %{ %} 3207 interface(CONST_INTER); 3208 %} 3209 // Integer Immediate: the value 255 3210 operand immI_255() %{ 3211 predicate( n->get_int() == 255 ); 3212 match(ConI); 3213 op_cost(0); 3214 3215 format %{ %} 3216 interface(CONST_INTER); 3217 %} 3218 3219 // Integer Immediate: the value 65535 3220 operand immI_65535() %{ 3221 predicate(n->get_int() == 65535); 3222 match(ConI); 3223 op_cost(0); 3224 3225 format %{ %} 3226 interface(CONST_INTER); 3227 %} 3228 3229 // Integer Immediate: the values 0-31 3230 operand immU5() %{ 3231 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3232 match(ConI); 3233 op_cost(0); 3234 3235 format %{ %} 3236 interface(CONST_INTER); 3237 %} 3238 3239 // Integer Immediate: 6-bit 3240 operand immU6() %{ 3241 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3242 match(ConI); 3243 op_cost(0); 3244 format %{ %} 3245 interface(CONST_INTER); 3246 %} 3247 3248 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) 3249 operand immU12() %{ 3250 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3251 match(ConI); 3252 op_cost(0); 3253 3254 format %{ %} 3255 interface(CONST_INTER); 3256 %} 3257 3258 // Unsigned Long Immediate: 12-bit (non-negative that fits in simm13) 3259 operand immUL12() %{ 3260 predicate((0 <= n->get_long()) && (n->get_long() == (int)n->get_long()) && Assembler::is_simm13((int)n->get_long())); 3261 match(ConL); 3262 op_cost(0); 3263 3264 format %{ %} 3265 interface(CONST_INTER); 3266 %} 3267 3268 // Integer Immediate non-negative 3269 operand immU31() 3270 %{ 3271 predicate(n->get_int() >= 0); 3272 match(ConI); 3273 3274 op_cost(0); 3275 format %{ %} 3276 interface(CONST_INTER); 3277 %} 3278 3279 // Long Immediate: the value FF 3280 operand immL_FF() %{ 3281 predicate( n->get_long() == 0xFFL ); 3282 match(ConL); 3283 op_cost(0); 3284 3285 format %{ %} 3286 interface(CONST_INTER); 3287 %} 3288 3289 // Long Immediate: the value FFFF 3290 operand immL_FFFF() %{ 3291 predicate( n->get_long() == 0xFFFFL ); 3292 match(ConL); 3293 op_cost(0); 3294 3295 format %{ %} 3296 interface(CONST_INTER); 3297 %} 3298 3299 // Pointer Immediate: 32 or 64-bit 3300 operand immP() %{ 3301 match(ConP); 3302 3303 op_cost(5); 3304 // formats are generated automatically for constants and base registers 3305 format %{ %} 3306 interface(CONST_INTER); 3307 %} 3308 3309 // Pointer Immediate: 64-bit 3310 operand immP_set() %{ 3311 predicate(!VM_Version::has_fast_ld()); 3312 match(ConP); 3313 3314 op_cost(5); 3315 // formats are generated automatically for constants and base registers 3316 format %{ %} 3317 interface(CONST_INTER); 3318 %} 3319 3320 // Pointer Immediate: 64-bit 3321 // From Niagara2 processors on a load should be better than materializing. 3322 operand immP_load() %{ 3323 predicate(VM_Version::has_fast_ld() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); 3324 match(ConP); 3325 3326 op_cost(5); 3327 // formats are generated automatically for constants and base registers 3328 format %{ %} 3329 interface(CONST_INTER); 3330 %} 3331 3332 // Pointer Immediate: 64-bit 3333 operand immP_no_oop_cheap() %{ 3334 predicate(VM_Version::has_fast_ld() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); 3335 match(ConP); 3336 3337 op_cost(5); 3338 // formats are generated automatically for constants and base registers 3339 format %{ %} 3340 interface(CONST_INTER); 3341 %} 3342 3343 operand immP13() %{ 3344 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3345 match(ConP); 3346 op_cost(0); 3347 3348 format %{ %} 3349 interface(CONST_INTER); 3350 %} 3351 3352 operand immP0() %{ 3353 predicate(n->get_ptr() == 0); 3354 match(ConP); 3355 op_cost(0); 3356 3357 format %{ %} 3358 interface(CONST_INTER); 3359 %} 3360 3361 operand immP_poll() %{ 3362 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3363 match(ConP); 3364 3365 // formats are generated automatically for constants and base registers 3366 format %{ %} 3367 interface(CONST_INTER); 3368 %} 3369 3370 // Pointer Immediate 3371 operand immN() 3372 %{ 3373 match(ConN); 3374 3375 op_cost(10); 3376 format %{ %} 3377 interface(CONST_INTER); 3378 %} 3379 3380 operand immNKlass() 3381 %{ 3382 match(ConNKlass); 3383 3384 op_cost(10); 3385 format %{ %} 3386 interface(CONST_INTER); 3387 %} 3388 3389 // NULL Pointer Immediate 3390 operand immN0() 3391 %{ 3392 predicate(n->get_narrowcon() == 0); 3393 match(ConN); 3394 3395 op_cost(0); 3396 format %{ %} 3397 interface(CONST_INTER); 3398 %} 3399 3400 operand immL() %{ 3401 match(ConL); 3402 op_cost(40); 3403 // formats are generated automatically for constants and base registers 3404 format %{ %} 3405 interface(CONST_INTER); 3406 %} 3407 3408 operand immL0() %{ 3409 predicate(n->get_long() == 0L); 3410 match(ConL); 3411 op_cost(0); 3412 // formats are generated automatically for constants and base registers 3413 format %{ %} 3414 interface(CONST_INTER); 3415 %} 3416 3417 // Integer Immediate: 5-bit 3418 operand immL5() %{ 3419 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); 3420 match(ConL); 3421 op_cost(0); 3422 format %{ %} 3423 interface(CONST_INTER); 3424 %} 3425 3426 // Long Immediate: 13-bit 3427 operand immL13() %{ 3428 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3429 match(ConL); 3430 op_cost(0); 3431 3432 format %{ %} 3433 interface(CONST_INTER); 3434 %} 3435 3436 // Long Immediate: 13-bit minus 7 3437 operand immL13m7() %{ 3438 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3439 match(ConL); 3440 op_cost(0); 3441 3442 format %{ %} 3443 interface(CONST_INTER); 3444 %} 3445 3446 // Long Immediate: low 32-bit mask 3447 operand immL_32bits() %{ 3448 predicate(n->get_long() == 0xFFFFFFFFL); 3449 match(ConL); 3450 op_cost(0); 3451 3452 format %{ %} 3453 interface(CONST_INTER); 3454 %} 3455 3456 // Long Immediate: cheap (materialize in <= 3 instructions) 3457 operand immL_cheap() %{ 3458 predicate(!VM_Version::has_fast_ld() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); 3459 match(ConL); 3460 op_cost(0); 3461 3462 format %{ %} 3463 interface(CONST_INTER); 3464 %} 3465 3466 // Long Immediate: expensive (materialize in > 3 instructions) 3467 operand immL_expensive() %{ 3468 predicate(VM_Version::has_fast_ld() && MacroAssembler::insts_for_set64(n->get_long()) > 3); 3469 match(ConL); 3470 op_cost(0); 3471 3472 format %{ %} 3473 interface(CONST_INTER); 3474 %} 3475 3476 // Double Immediate 3477 operand immD() %{ 3478 match(ConD); 3479 3480 op_cost(40); 3481 format %{ %} 3482 interface(CONST_INTER); 3483 %} 3484 3485 // Double Immediate: +0.0d 3486 operand immD0() %{ 3487 predicate(jlong_cast(n->getd()) == 0); 3488 match(ConD); 3489 3490 op_cost(0); 3491 format %{ %} 3492 interface(CONST_INTER); 3493 %} 3494 3495 // Float Immediate 3496 operand immF() %{ 3497 match(ConF); 3498 3499 op_cost(20); 3500 format %{ %} 3501 interface(CONST_INTER); 3502 %} 3503 3504 // Float Immediate: +0.0f 3505 operand immF0() %{ 3506 predicate(jint_cast(n->getf()) == 0); 3507 match(ConF); 3508 3509 op_cost(0); 3510 format %{ %} 3511 interface(CONST_INTER); 3512 %} 3513 3514 // Integer Register Operands 3515 // Integer Register 3516 operand iRegI() %{ 3517 constraint(ALLOC_IN_RC(int_reg)); 3518 match(RegI); 3519 3520 match(notemp_iRegI); 3521 match(g1RegI); 3522 match(o0RegI); 3523 match(iRegIsafe); 3524 3525 format %{ %} 3526 interface(REG_INTER); 3527 %} 3528 3529 operand notemp_iRegI() %{ 3530 constraint(ALLOC_IN_RC(notemp_int_reg)); 3531 match(RegI); 3532 3533 match(o0RegI); 3534 3535 format %{ %} 3536 interface(REG_INTER); 3537 %} 3538 3539 operand o0RegI() %{ 3540 constraint(ALLOC_IN_RC(o0_regI)); 3541 match(iRegI); 3542 3543 format %{ %} 3544 interface(REG_INTER); 3545 %} 3546 3547 // Pointer Register 3548 operand iRegP() %{ 3549 constraint(ALLOC_IN_RC(ptr_reg)); 3550 match(RegP); 3551 3552 match(lock_ptr_RegP); 3553 match(g1RegP); 3554 match(g2RegP); 3555 match(g3RegP); 3556 match(g4RegP); 3557 match(i0RegP); 3558 match(o0RegP); 3559 match(o1RegP); 3560 match(l7RegP); 3561 3562 format %{ %} 3563 interface(REG_INTER); 3564 %} 3565 3566 operand sp_ptr_RegP() %{ 3567 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3568 match(RegP); 3569 match(iRegP); 3570 3571 format %{ %} 3572 interface(REG_INTER); 3573 %} 3574 3575 operand lock_ptr_RegP() %{ 3576 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3577 match(RegP); 3578 match(i0RegP); 3579 match(o0RegP); 3580 match(o1RegP); 3581 match(l7RegP); 3582 3583 format %{ %} 3584 interface(REG_INTER); 3585 %} 3586 3587 operand g1RegP() %{ 3588 constraint(ALLOC_IN_RC(g1_regP)); 3589 match(iRegP); 3590 3591 format %{ %} 3592 interface(REG_INTER); 3593 %} 3594 3595 operand g2RegP() %{ 3596 constraint(ALLOC_IN_RC(g2_regP)); 3597 match(iRegP); 3598 3599 format %{ %} 3600 interface(REG_INTER); 3601 %} 3602 3603 operand g3RegP() %{ 3604 constraint(ALLOC_IN_RC(g3_regP)); 3605 match(iRegP); 3606 3607 format %{ %} 3608 interface(REG_INTER); 3609 %} 3610 3611 operand g1RegI() %{ 3612 constraint(ALLOC_IN_RC(g1_regI)); 3613 match(iRegI); 3614 3615 format %{ %} 3616 interface(REG_INTER); 3617 %} 3618 3619 operand g3RegI() %{ 3620 constraint(ALLOC_IN_RC(g3_regI)); 3621 match(iRegI); 3622 3623 format %{ %} 3624 interface(REG_INTER); 3625 %} 3626 3627 operand g4RegI() %{ 3628 constraint(ALLOC_IN_RC(g4_regI)); 3629 match(iRegI); 3630 3631 format %{ %} 3632 interface(REG_INTER); 3633 %} 3634 3635 operand g4RegP() %{ 3636 constraint(ALLOC_IN_RC(g4_regP)); 3637 match(iRegP); 3638 3639 format %{ %} 3640 interface(REG_INTER); 3641 %} 3642 3643 operand i0RegP() %{ 3644 constraint(ALLOC_IN_RC(i0_regP)); 3645 match(iRegP); 3646 3647 format %{ %} 3648 interface(REG_INTER); 3649 %} 3650 3651 operand o0RegP() %{ 3652 constraint(ALLOC_IN_RC(o0_regP)); 3653 match(iRegP); 3654 3655 format %{ %} 3656 interface(REG_INTER); 3657 %} 3658 3659 operand o1RegP() %{ 3660 constraint(ALLOC_IN_RC(o1_regP)); 3661 match(iRegP); 3662 3663 format %{ %} 3664 interface(REG_INTER); 3665 %} 3666 3667 operand o2RegP() %{ 3668 constraint(ALLOC_IN_RC(o2_regP)); 3669 match(iRegP); 3670 3671 format %{ %} 3672 interface(REG_INTER); 3673 %} 3674 3675 operand o7RegP() %{ 3676 constraint(ALLOC_IN_RC(o7_regP)); 3677 match(iRegP); 3678 3679 format %{ %} 3680 interface(REG_INTER); 3681 %} 3682 3683 operand l7RegP() %{ 3684 constraint(ALLOC_IN_RC(l7_regP)); 3685 match(iRegP); 3686 3687 format %{ %} 3688 interface(REG_INTER); 3689 %} 3690 3691 operand o7RegI() %{ 3692 constraint(ALLOC_IN_RC(o7_regI)); 3693 match(iRegI); 3694 3695 format %{ %} 3696 interface(REG_INTER); 3697 %} 3698 3699 operand iRegN() %{ 3700 constraint(ALLOC_IN_RC(int_reg)); 3701 match(RegN); 3702 3703 format %{ %} 3704 interface(REG_INTER); 3705 %} 3706 3707 // Long Register 3708 operand iRegL() %{ 3709 constraint(ALLOC_IN_RC(long_reg)); 3710 match(RegL); 3711 3712 format %{ %} 3713 interface(REG_INTER); 3714 %} 3715 3716 operand o2RegL() %{ 3717 constraint(ALLOC_IN_RC(o2_regL)); 3718 match(iRegL); 3719 3720 format %{ %} 3721 interface(REG_INTER); 3722 %} 3723 3724 operand o7RegL() %{ 3725 constraint(ALLOC_IN_RC(o7_regL)); 3726 match(iRegL); 3727 3728 format %{ %} 3729 interface(REG_INTER); 3730 %} 3731 3732 operand g1RegL() %{ 3733 constraint(ALLOC_IN_RC(g1_regL)); 3734 match(iRegL); 3735 3736 format %{ %} 3737 interface(REG_INTER); 3738 %} 3739 3740 operand g3RegL() %{ 3741 constraint(ALLOC_IN_RC(g3_regL)); 3742 match(iRegL); 3743 3744 format %{ %} 3745 interface(REG_INTER); 3746 %} 3747 3748 // Int Register safe 3749 // This is 64bit safe 3750 operand iRegIsafe() %{ 3751 constraint(ALLOC_IN_RC(long_reg)); 3752 3753 match(iRegI); 3754 3755 format %{ %} 3756 interface(REG_INTER); 3757 %} 3758 3759 // Condition Code Flag Register 3760 operand flagsReg() %{ 3761 constraint(ALLOC_IN_RC(int_flags)); 3762 match(RegFlags); 3763 3764 format %{ "ccr" %} // both ICC and XCC 3765 interface(REG_INTER); 3766 %} 3767 3768 // Condition Code Register, unsigned comparisons. 3769 operand flagsRegU() %{ 3770 constraint(ALLOC_IN_RC(int_flags)); 3771 match(RegFlags); 3772 3773 format %{ "icc_U" %} 3774 interface(REG_INTER); 3775 %} 3776 3777 // Condition Code Register, pointer comparisons. 3778 operand flagsRegP() %{ 3779 constraint(ALLOC_IN_RC(int_flags)); 3780 match(RegFlags); 3781 3782 format %{ "xcc_P" %} 3783 interface(REG_INTER); 3784 %} 3785 3786 // Condition Code Register, long comparisons. 3787 operand flagsRegL() %{ 3788 constraint(ALLOC_IN_RC(int_flags)); 3789 match(RegFlags); 3790 3791 format %{ "xcc_L" %} 3792 interface(REG_INTER); 3793 %} 3794 3795 // Condition Code Register, unsigned long comparisons. 3796 operand flagsRegUL() %{ 3797 constraint(ALLOC_IN_RC(int_flags)); 3798 match(RegFlags); 3799 3800 format %{ "xcc_UL" %} 3801 interface(REG_INTER); 3802 %} 3803 3804 // Condition Code Register, floating comparisons, unordered same as "less". 3805 operand flagsRegF() %{ 3806 constraint(ALLOC_IN_RC(float_flags)); 3807 match(RegFlags); 3808 match(flagsRegF0); 3809 3810 format %{ %} 3811 interface(REG_INTER); 3812 %} 3813 3814 operand flagsRegF0() %{ 3815 constraint(ALLOC_IN_RC(float_flag0)); 3816 match(RegFlags); 3817 3818 format %{ %} 3819 interface(REG_INTER); 3820 %} 3821 3822 3823 // Condition Code Flag Register used by long compare 3824 operand flagsReg_long_LTGE() %{ 3825 constraint(ALLOC_IN_RC(int_flags)); 3826 match(RegFlags); 3827 format %{ "icc_LTGE" %} 3828 interface(REG_INTER); 3829 %} 3830 operand flagsReg_long_EQNE() %{ 3831 constraint(ALLOC_IN_RC(int_flags)); 3832 match(RegFlags); 3833 format %{ "icc_EQNE" %} 3834 interface(REG_INTER); 3835 %} 3836 operand flagsReg_long_LEGT() %{ 3837 constraint(ALLOC_IN_RC(int_flags)); 3838 match(RegFlags); 3839 format %{ "icc_LEGT" %} 3840 interface(REG_INTER); 3841 %} 3842 3843 3844 operand regD() %{ 3845 constraint(ALLOC_IN_RC(dflt_reg)); 3846 match(RegD); 3847 3848 match(regD_low); 3849 3850 format %{ %} 3851 interface(REG_INTER); 3852 %} 3853 3854 operand regF() %{ 3855 constraint(ALLOC_IN_RC(sflt_reg)); 3856 match(RegF); 3857 3858 format %{ %} 3859 interface(REG_INTER); 3860 %} 3861 3862 operand regD_low() %{ 3863 constraint(ALLOC_IN_RC(dflt_low_reg)); 3864 match(regD); 3865 3866 format %{ %} 3867 interface(REG_INTER); 3868 %} 3869 3870 // Special Registers 3871 3872 // Method Register 3873 operand inline_cache_regP(iRegP reg) %{ 3874 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 3875 match(reg); 3876 format %{ %} 3877 interface(REG_INTER); 3878 %} 3879 3880 operand interpreter_method_oop_regP(iRegP reg) %{ 3881 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 3882 match(reg); 3883 format %{ %} 3884 interface(REG_INTER); 3885 %} 3886 3887 3888 //----------Complex Operands--------------------------------------------------- 3889 // Indirect Memory Reference 3890 operand indirect(sp_ptr_RegP reg) %{ 3891 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3892 match(reg); 3893 3894 op_cost(100); 3895 format %{ "[$reg]" %} 3896 interface(MEMORY_INTER) %{ 3897 base($reg); 3898 index(0x0); 3899 scale(0x0); 3900 disp(0x0); 3901 %} 3902 %} 3903 3904 // Indirect with simm13 Offset 3905 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 3906 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3907 match(AddP reg offset); 3908 3909 op_cost(100); 3910 format %{ "[$reg + $offset]" %} 3911 interface(MEMORY_INTER) %{ 3912 base($reg); 3913 index(0x0); 3914 scale(0x0); 3915 disp($offset); 3916 %} 3917 %} 3918 3919 // Indirect with simm13 Offset minus 7 3920 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 3921 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3922 match(AddP reg offset); 3923 3924 op_cost(100); 3925 format %{ "[$reg + $offset]" %} 3926 interface(MEMORY_INTER) %{ 3927 base($reg); 3928 index(0x0); 3929 scale(0x0); 3930 disp($offset); 3931 %} 3932 %} 3933 3934 // Note: Intel has a swapped version also, like this: 3935 //operand indOffsetX(iRegI reg, immP offset) %{ 3936 // constraint(ALLOC_IN_RC(int_reg)); 3937 // match(AddP offset reg); 3938 // 3939 // op_cost(100); 3940 // format %{ "[$reg + $offset]" %} 3941 // interface(MEMORY_INTER) %{ 3942 // base($reg); 3943 // index(0x0); 3944 // scale(0x0); 3945 // disp($offset); 3946 // %} 3947 //%} 3948 //// However, it doesn't make sense for SPARC, since 3949 // we have no particularly good way to embed oops in 3950 // single instructions. 3951 3952 // Indirect with Register Index 3953 operand indIndex(iRegP addr, iRegX index) %{ 3954 constraint(ALLOC_IN_RC(ptr_reg)); 3955 match(AddP addr index); 3956 3957 op_cost(100); 3958 format %{ "[$addr + $index]" %} 3959 interface(MEMORY_INTER) %{ 3960 base($addr); 3961 index($index); 3962 scale(0x0); 3963 disp(0x0); 3964 %} 3965 %} 3966 3967 //----------Special Memory Operands-------------------------------------------- 3968 // Stack Slot Operand - This operand is used for loading and storing temporary 3969 // values on the stack where a match requires a value to 3970 // flow through memory. 3971 operand stackSlotI(sRegI reg) %{ 3972 constraint(ALLOC_IN_RC(stack_slots)); 3973 op_cost(100); 3974 //match(RegI); 3975 format %{ "[$reg]" %} 3976 interface(MEMORY_INTER) %{ 3977 base(0xE); // R_SP 3978 index(0x0); 3979 scale(0x0); 3980 disp($reg); // Stack Offset 3981 %} 3982 %} 3983 3984 operand stackSlotP(sRegP reg) %{ 3985 constraint(ALLOC_IN_RC(stack_slots)); 3986 op_cost(100); 3987 //match(RegP); 3988 format %{ "[$reg]" %} 3989 interface(MEMORY_INTER) %{ 3990 base(0xE); // R_SP 3991 index(0x0); 3992 scale(0x0); 3993 disp($reg); // Stack Offset 3994 %} 3995 %} 3996 3997 operand stackSlotF(sRegF reg) %{ 3998 constraint(ALLOC_IN_RC(stack_slots)); 3999 op_cost(100); 4000 //match(RegF); 4001 format %{ "[$reg]" %} 4002 interface(MEMORY_INTER) %{ 4003 base(0xE); // R_SP 4004 index(0x0); 4005 scale(0x0); 4006 disp($reg); // Stack Offset 4007 %} 4008 %} 4009 operand stackSlotD(sRegD reg) %{ 4010 constraint(ALLOC_IN_RC(stack_slots)); 4011 op_cost(100); 4012 //match(RegD); 4013 format %{ "[$reg]" %} 4014 interface(MEMORY_INTER) %{ 4015 base(0xE); // R_SP 4016 index(0x0); 4017 scale(0x0); 4018 disp($reg); // Stack Offset 4019 %} 4020 %} 4021 operand stackSlotL(sRegL reg) %{ 4022 constraint(ALLOC_IN_RC(stack_slots)); 4023 op_cost(100); 4024 //match(RegL); 4025 format %{ "[$reg]" %} 4026 interface(MEMORY_INTER) %{ 4027 base(0xE); // R_SP 4028 index(0x0); 4029 scale(0x0); 4030 disp($reg); // Stack Offset 4031 %} 4032 %} 4033 4034 // Operands for expressing Control Flow 4035 // NOTE: Label is a predefined operand which should not be redefined in 4036 // the AD file. It is generically handled within the ADLC. 4037 4038 //----------Conditional Branch Operands---------------------------------------- 4039 // Comparison Op - This is the operation of the comparison, and is limited to 4040 // the following set of codes: 4041 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4042 // 4043 // Other attributes of the comparison, such as unsignedness, are specified 4044 // by the comparison instruction that sets a condition code flags register. 4045 // That result is represented by a flags operand whose subtype is appropriate 4046 // to the unsignedness (etc.) of the comparison. 4047 // 4048 // Later, the instruction which matches both the Comparison Op (a Bool) and 4049 // the flags (produced by the Cmp) specifies the coding of the comparison op 4050 // by matching a specific subtype of Bool operand below, such as cmpOpU. 4051 4052 operand cmpOp() %{ 4053 match(Bool); 4054 4055 format %{ "" %} 4056 interface(COND_INTER) %{ 4057 equal(0x1); 4058 not_equal(0x9); 4059 less(0x3); 4060 greater_equal(0xB); 4061 less_equal(0x2); 4062 greater(0xA); 4063 overflow(0x7); 4064 no_overflow(0xF); 4065 %} 4066 %} 4067 4068 // Comparison Op, unsigned 4069 operand cmpOpU() %{ 4070 match(Bool); 4071 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4072 n->as_Bool()->_test._test != BoolTest::no_overflow); 4073 4074 format %{ "u" %} 4075 interface(COND_INTER) %{ 4076 equal(0x1); 4077 not_equal(0x9); 4078 less(0x5); 4079 greater_equal(0xD); 4080 less_equal(0x4); 4081 greater(0xC); 4082 overflow(0x7); 4083 no_overflow(0xF); 4084 %} 4085 %} 4086 4087 // Comparison Op, pointer (same as unsigned) 4088 operand cmpOpP() %{ 4089 match(Bool); 4090 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4091 n->as_Bool()->_test._test != BoolTest::no_overflow); 4092 4093 format %{ "p" %} 4094 interface(COND_INTER) %{ 4095 equal(0x1); 4096 not_equal(0x9); 4097 less(0x5); 4098 greater_equal(0xD); 4099 less_equal(0x4); 4100 greater(0xC); 4101 overflow(0x7); 4102 no_overflow(0xF); 4103 %} 4104 %} 4105 4106 // Comparison Op, branch-register encoding 4107 operand cmpOp_reg() %{ 4108 match(Bool); 4109 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4110 n->as_Bool()->_test._test != BoolTest::no_overflow); 4111 4112 format %{ "" %} 4113 interface(COND_INTER) %{ 4114 equal (0x1); 4115 not_equal (0x5); 4116 less (0x3); 4117 greater_equal(0x7); 4118 less_equal (0x2); 4119 greater (0x6); 4120 overflow(0x7); // not supported 4121 no_overflow(0xF); // not supported 4122 %} 4123 %} 4124 4125 // Comparison Code, floating, unordered same as less 4126 operand cmpOpF() %{ 4127 match(Bool); 4128 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4129 n->as_Bool()->_test._test != BoolTest::no_overflow); 4130 4131 format %{ "fl" %} 4132 interface(COND_INTER) %{ 4133 equal(0x9); 4134 not_equal(0x1); 4135 less(0x3); 4136 greater_equal(0xB); 4137 less_equal(0xE); 4138 greater(0x6); 4139 4140 overflow(0x7); // not supported 4141 no_overflow(0xF); // not supported 4142 %} 4143 %} 4144 4145 // Used by long compare 4146 operand cmpOp_commute() %{ 4147 match(Bool); 4148 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4149 n->as_Bool()->_test._test != BoolTest::no_overflow); 4150 4151 format %{ "" %} 4152 interface(COND_INTER) %{ 4153 equal(0x1); 4154 not_equal(0x9); 4155 less(0xA); 4156 greater_equal(0x2); 4157 less_equal(0xB); 4158 greater(0x3); 4159 overflow(0x7); 4160 no_overflow(0xF); 4161 %} 4162 %} 4163 4164 //----------OPERAND CLASSES---------------------------------------------------- 4165 // Operand Classes are groups of operands that are used to simplify 4166 // instruction definitions by not requiring the AD writer to specify separate 4167 // instructions for every form of operand when the instruction accepts 4168 // multiple operand types with the same basic encoding and format. The classic 4169 // case of this is memory operands. 4170 opclass memory( indirect, indOffset13, indIndex ); 4171 opclass indIndexMemory( indIndex ); 4172 4173 //----------PIPELINE----------------------------------------------------------- 4174 pipeline %{ 4175 4176 //----------ATTRIBUTES--------------------------------------------------------- 4177 attributes %{ 4178 fixed_size_instructions; // Fixed size instructions 4179 branch_has_delay_slot; // Branch has delay slot following 4180 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4181 instruction_unit_size = 4; // An instruction is 4 bytes long 4182 instruction_fetch_unit_size = 16; // The processor fetches one line 4183 instruction_fetch_units = 1; // of 16 bytes 4184 4185 // List of nop instructions 4186 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4187 %} 4188 4189 //----------RESOURCES---------------------------------------------------------- 4190 // Resources are the functional units available to the machine 4191 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4192 4193 //----------PIPELINE DESCRIPTION----------------------------------------------- 4194 // Pipeline Description specifies the stages in the machine's pipeline 4195 4196 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4197 4198 //----------PIPELINE CLASSES--------------------------------------------------- 4199 // Pipeline Classes describe the stages in which input and output are 4200 // referenced by the hardware pipeline. 4201 4202 // Integer ALU reg-reg operation 4203 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4204 single_instruction; 4205 dst : E(write); 4206 src1 : R(read); 4207 src2 : R(read); 4208 IALU : R; 4209 %} 4210 4211 // Integer ALU reg-reg long operation 4212 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4213 instruction_count(2); 4214 dst : E(write); 4215 src1 : R(read); 4216 src2 : R(read); 4217 IALU : R; 4218 IALU : R; 4219 %} 4220 4221 // Integer ALU reg-reg long dependent operation 4222 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4223 instruction_count(1); multiple_bundles; 4224 dst : E(write); 4225 src1 : R(read); 4226 src2 : R(read); 4227 cr : E(write); 4228 IALU : R(2); 4229 %} 4230 4231 // Integer ALU reg-imm operaion 4232 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4233 single_instruction; 4234 dst : E(write); 4235 src1 : R(read); 4236 IALU : R; 4237 %} 4238 4239 // Integer ALU reg-reg operation with condition code 4240 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4241 single_instruction; 4242 dst : E(write); 4243 cr : E(write); 4244 src1 : R(read); 4245 src2 : R(read); 4246 IALU : R; 4247 %} 4248 4249 // Integer ALU reg-imm operation with condition code 4250 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4251 single_instruction; 4252 dst : E(write); 4253 cr : E(write); 4254 src1 : R(read); 4255 IALU : R; 4256 %} 4257 4258 // Integer ALU zero-reg operation 4259 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4260 single_instruction; 4261 dst : E(write); 4262 src2 : R(read); 4263 IALU : R; 4264 %} 4265 4266 // Integer ALU zero-reg operation with condition code only 4267 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4268 single_instruction; 4269 cr : E(write); 4270 src : R(read); 4271 IALU : R; 4272 %} 4273 4274 // Integer ALU reg-reg operation with condition code only 4275 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4276 single_instruction; 4277 cr : E(write); 4278 src1 : R(read); 4279 src2 : R(read); 4280 IALU : R; 4281 %} 4282 4283 // Integer ALU reg-imm operation with condition code only 4284 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4285 single_instruction; 4286 cr : E(write); 4287 src1 : R(read); 4288 IALU : R; 4289 %} 4290 4291 // Integer ALU reg-reg-zero operation with condition code only 4292 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4293 single_instruction; 4294 cr : E(write); 4295 src1 : R(read); 4296 src2 : R(read); 4297 IALU : R; 4298 %} 4299 4300 // Integer ALU reg-imm-zero operation with condition code only 4301 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4302 single_instruction; 4303 cr : E(write); 4304 src1 : R(read); 4305 IALU : R; 4306 %} 4307 4308 // Integer ALU reg-reg operation with condition code, src1 modified 4309 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4310 single_instruction; 4311 cr : E(write); 4312 src1 : E(write); 4313 src1 : R(read); 4314 src2 : R(read); 4315 IALU : R; 4316 %} 4317 4318 // Integer ALU reg-imm operation with condition code, src1 modified 4319 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4320 single_instruction; 4321 cr : E(write); 4322 src1 : E(write); 4323 src1 : R(read); 4324 IALU : R; 4325 %} 4326 4327 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4328 multiple_bundles; 4329 dst : E(write)+4; 4330 cr : E(write); 4331 src1 : R(read); 4332 src2 : R(read); 4333 IALU : R(3); 4334 BR : R(2); 4335 %} 4336 4337 // Integer ALU operation 4338 pipe_class ialu_none(iRegI dst) %{ 4339 single_instruction; 4340 dst : E(write); 4341 IALU : R; 4342 %} 4343 4344 // Integer ALU reg operation 4345 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4346 single_instruction; may_have_no_code; 4347 dst : E(write); 4348 src : R(read); 4349 IALU : R; 4350 %} 4351 4352 // Integer ALU reg conditional operation 4353 // This instruction has a 1 cycle stall, and cannot execute 4354 // in the same cycle as the instruction setting the condition 4355 // code. We kludge this by pretending to read the condition code 4356 // 1 cycle earlier, and by marking the functional units as busy 4357 // for 2 cycles with the result available 1 cycle later than 4358 // is really the case. 4359 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4360 single_instruction; 4361 op2_out : C(write); 4362 op1 : R(read); 4363 cr : R(read); // This is really E, with a 1 cycle stall 4364 BR : R(2); 4365 MS : R(2); 4366 %} 4367 4368 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4369 instruction_count(1); multiple_bundles; 4370 dst : C(write)+1; 4371 src : R(read)+1; 4372 IALU : R(1); 4373 BR : E(2); 4374 MS : E(2); 4375 %} 4376 4377 // Integer ALU reg operation 4378 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4379 single_instruction; may_have_no_code; 4380 dst : E(write); 4381 src : R(read); 4382 IALU : R; 4383 %} 4384 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4385 single_instruction; may_have_no_code; 4386 dst : E(write); 4387 src : R(read); 4388 IALU : R; 4389 %} 4390 4391 // Two integer ALU reg operations 4392 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4393 instruction_count(2); 4394 dst : E(write); 4395 src : R(read); 4396 A0 : R; 4397 A1 : R; 4398 %} 4399 4400 // Two integer ALU reg operations 4401 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4402 instruction_count(2); may_have_no_code; 4403 dst : E(write); 4404 src : R(read); 4405 A0 : R; 4406 A1 : R; 4407 %} 4408 4409 // Integer ALU imm operation 4410 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4411 single_instruction; 4412 dst : E(write); 4413 IALU : R; 4414 %} 4415 4416 // Integer ALU reg-reg with carry operation 4417 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4418 single_instruction; 4419 dst : E(write); 4420 src1 : R(read); 4421 src2 : R(read); 4422 IALU : R; 4423 %} 4424 4425 // Integer ALU cc operation 4426 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4427 single_instruction; 4428 dst : E(write); 4429 cc : R(read); 4430 IALU : R; 4431 %} 4432 4433 // Integer ALU cc / second IALU operation 4434 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4435 instruction_count(1); multiple_bundles; 4436 dst : E(write)+1; 4437 src : R(read); 4438 IALU : R; 4439 %} 4440 4441 // Integer ALU cc / second IALU operation 4442 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4443 instruction_count(1); multiple_bundles; 4444 dst : E(write)+1; 4445 p : R(read); 4446 q : R(read); 4447 IALU : R; 4448 %} 4449 4450 // Integer ALU hi-lo-reg operation 4451 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4452 instruction_count(1); multiple_bundles; 4453 dst : E(write)+1; 4454 IALU : R(2); 4455 %} 4456 4457 // Float ALU hi-lo-reg operation (with temp) 4458 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4459 instruction_count(1); multiple_bundles; 4460 dst : E(write)+1; 4461 IALU : R(2); 4462 %} 4463 4464 // Long Constant 4465 pipe_class loadConL( iRegL dst, immL src ) %{ 4466 instruction_count(2); multiple_bundles; 4467 dst : E(write)+1; 4468 IALU : R(2); 4469 IALU : R(2); 4470 %} 4471 4472 // Pointer Constant 4473 pipe_class loadConP( iRegP dst, immP src ) %{ 4474 instruction_count(0); multiple_bundles; 4475 fixed_latency(6); 4476 %} 4477 4478 // Polling Address 4479 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4480 instruction_count(0); multiple_bundles; 4481 fixed_latency(6); 4482 %} 4483 4484 // Long Constant small 4485 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4486 instruction_count(2); 4487 dst : E(write); 4488 IALU : R; 4489 IALU : R; 4490 %} 4491 4492 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4493 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4494 instruction_count(1); multiple_bundles; 4495 src : R(read); 4496 dst : M(write)+1; 4497 IALU : R; 4498 MS : E; 4499 %} 4500 4501 // Integer ALU nop operation 4502 pipe_class ialu_nop() %{ 4503 single_instruction; 4504 IALU : R; 4505 %} 4506 4507 // Integer ALU nop operation 4508 pipe_class ialu_nop_A0() %{ 4509 single_instruction; 4510 A0 : R; 4511 %} 4512 4513 // Integer ALU nop operation 4514 pipe_class ialu_nop_A1() %{ 4515 single_instruction; 4516 A1 : R; 4517 %} 4518 4519 // Integer Multiply reg-reg operation 4520 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4521 single_instruction; 4522 dst : E(write); 4523 src1 : R(read); 4524 src2 : R(read); 4525 MS : R(5); 4526 %} 4527 4528 // Integer Multiply reg-imm operation 4529 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4530 single_instruction; 4531 dst : E(write); 4532 src1 : R(read); 4533 MS : R(5); 4534 %} 4535 4536 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4537 single_instruction; 4538 dst : E(write)+4; 4539 src1 : R(read); 4540 src2 : R(read); 4541 MS : R(6); 4542 %} 4543 4544 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4545 single_instruction; 4546 dst : E(write)+4; 4547 src1 : R(read); 4548 MS : R(6); 4549 %} 4550 4551 // Integer Divide reg-reg 4552 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4553 instruction_count(1); multiple_bundles; 4554 dst : E(write); 4555 temp : E(write); 4556 src1 : R(read); 4557 src2 : R(read); 4558 temp : R(read); 4559 MS : R(38); 4560 %} 4561 4562 // Integer Divide reg-imm 4563 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4564 instruction_count(1); multiple_bundles; 4565 dst : E(write); 4566 temp : E(write); 4567 src1 : R(read); 4568 temp : R(read); 4569 MS : R(38); 4570 %} 4571 4572 // Long Divide 4573 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4574 dst : E(write)+71; 4575 src1 : R(read); 4576 src2 : R(read)+1; 4577 MS : R(70); 4578 %} 4579 4580 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4581 dst : E(write)+71; 4582 src1 : R(read); 4583 MS : R(70); 4584 %} 4585 4586 // Floating Point Add Float 4587 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4588 single_instruction; 4589 dst : X(write); 4590 src1 : E(read); 4591 src2 : E(read); 4592 FA : R; 4593 %} 4594 4595 // Floating Point Add Double 4596 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4597 single_instruction; 4598 dst : X(write); 4599 src1 : E(read); 4600 src2 : E(read); 4601 FA : R; 4602 %} 4603 4604 // Floating Point Conditional Move based on integer flags 4605 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4606 single_instruction; 4607 dst : X(write); 4608 src : E(read); 4609 cr : R(read); 4610 FA : R(2); 4611 BR : R(2); 4612 %} 4613 4614 // Floating Point Conditional Move based on integer flags 4615 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4616 single_instruction; 4617 dst : X(write); 4618 src : E(read); 4619 cr : R(read); 4620 FA : R(2); 4621 BR : R(2); 4622 %} 4623 4624 // Floating Point Multiply Float 4625 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4626 single_instruction; 4627 dst : X(write); 4628 src1 : E(read); 4629 src2 : E(read); 4630 FM : R; 4631 %} 4632 4633 // Floating Point Multiply Double 4634 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4635 single_instruction; 4636 dst : X(write); 4637 src1 : E(read); 4638 src2 : E(read); 4639 FM : R; 4640 %} 4641 4642 // Floating Point Divide Float 4643 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4644 single_instruction; 4645 dst : X(write); 4646 src1 : E(read); 4647 src2 : E(read); 4648 FM : R; 4649 FDIV : C(14); 4650 %} 4651 4652 // Floating Point Divide Double 4653 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4654 single_instruction; 4655 dst : X(write); 4656 src1 : E(read); 4657 src2 : E(read); 4658 FM : R; 4659 FDIV : C(17); 4660 %} 4661 4662 // Fused floating-point multiply-add float. 4663 pipe_class fmaF_regx4(regF dst, regF src1, regF src2, regF src3) %{ 4664 single_instruction; 4665 dst : X(write); 4666 src1 : E(read); 4667 src2 : E(read); 4668 src3 : E(read); 4669 FM : R; 4670 %} 4671 4672 // Fused gloating-point multiply-add double. 4673 pipe_class fmaD_regx4(regD dst, regD src1, regD src2, regD src3) %{ 4674 single_instruction; 4675 dst : X(write); 4676 src1 : E(read); 4677 src2 : E(read); 4678 src3 : E(read); 4679 FM : R; 4680 %} 4681 4682 // Floating Point Move/Negate/Abs Float 4683 pipe_class faddF_reg(regF dst, regF src) %{ 4684 single_instruction; 4685 dst : W(write); 4686 src : E(read); 4687 FA : R(1); 4688 %} 4689 4690 // Floating Point Move/Negate/Abs Double 4691 pipe_class faddD_reg(regD dst, regD src) %{ 4692 single_instruction; 4693 dst : W(write); 4694 src : E(read); 4695 FA : R; 4696 %} 4697 4698 // Floating Point Convert F->D 4699 pipe_class fcvtF2D(regD dst, regF src) %{ 4700 single_instruction; 4701 dst : X(write); 4702 src : E(read); 4703 FA : R; 4704 %} 4705 4706 // Floating Point Convert I->D 4707 pipe_class fcvtI2D(regD dst, regF src) %{ 4708 single_instruction; 4709 dst : X(write); 4710 src : E(read); 4711 FA : R; 4712 %} 4713 4714 // Floating Point Convert LHi->D 4715 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4716 single_instruction; 4717 dst : X(write); 4718 src : E(read); 4719 FA : R; 4720 %} 4721 4722 // Floating Point Convert L->D 4723 pipe_class fcvtL2D(regD dst, regF src) %{ 4724 single_instruction; 4725 dst : X(write); 4726 src : E(read); 4727 FA : R; 4728 %} 4729 4730 // Floating Point Convert L->F 4731 pipe_class fcvtL2F(regD dst, regF src) %{ 4732 single_instruction; 4733 dst : X(write); 4734 src : E(read); 4735 FA : R; 4736 %} 4737 4738 // Floating Point Convert D->F 4739 pipe_class fcvtD2F(regD dst, regF src) %{ 4740 single_instruction; 4741 dst : X(write); 4742 src : E(read); 4743 FA : R; 4744 %} 4745 4746 // Floating Point Convert I->L 4747 pipe_class fcvtI2L(regD dst, regF src) %{ 4748 single_instruction; 4749 dst : X(write); 4750 src : E(read); 4751 FA : R; 4752 %} 4753 4754 // Floating Point Convert D->F 4755 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4756 instruction_count(1); multiple_bundles; 4757 dst : X(write)+6; 4758 src : E(read); 4759 FA : R; 4760 %} 4761 4762 // Floating Point Convert D->L 4763 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4764 instruction_count(1); multiple_bundles; 4765 dst : X(write)+6; 4766 src : E(read); 4767 FA : R; 4768 %} 4769 4770 // Floating Point Convert F->I 4771 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4772 instruction_count(1); multiple_bundles; 4773 dst : X(write)+6; 4774 src : E(read); 4775 FA : R; 4776 %} 4777 4778 // Floating Point Convert F->L 4779 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4780 instruction_count(1); multiple_bundles; 4781 dst : X(write)+6; 4782 src : E(read); 4783 FA : R; 4784 %} 4785 4786 // Floating Point Convert I->F 4787 pipe_class fcvtI2F(regF dst, regF src) %{ 4788 single_instruction; 4789 dst : X(write); 4790 src : E(read); 4791 FA : R; 4792 %} 4793 4794 // Floating Point Compare 4795 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4796 single_instruction; 4797 cr : X(write); 4798 src1 : E(read); 4799 src2 : E(read); 4800 FA : R; 4801 %} 4802 4803 // Floating Point Compare 4804 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4805 single_instruction; 4806 cr : X(write); 4807 src1 : E(read); 4808 src2 : E(read); 4809 FA : R; 4810 %} 4811 4812 // Floating Add Nop 4813 pipe_class fadd_nop() %{ 4814 single_instruction; 4815 FA : R; 4816 %} 4817 4818 // Integer Store to Memory 4819 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 4820 single_instruction; 4821 mem : R(read); 4822 src : C(read); 4823 MS : R; 4824 %} 4825 4826 // Integer Store to Memory 4827 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 4828 single_instruction; 4829 mem : R(read); 4830 src : C(read); 4831 MS : R; 4832 %} 4833 4834 // Integer Store Zero to Memory 4835 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 4836 single_instruction; 4837 mem : R(read); 4838 MS : R; 4839 %} 4840 4841 // Special Stack Slot Store 4842 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 4843 single_instruction; 4844 stkSlot : R(read); 4845 src : C(read); 4846 MS : R; 4847 %} 4848 4849 // Special Stack Slot Store 4850 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 4851 instruction_count(2); multiple_bundles; 4852 stkSlot : R(read); 4853 src : C(read); 4854 MS : R(2); 4855 %} 4856 4857 // Float Store 4858 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 4859 single_instruction; 4860 mem : R(read); 4861 src : C(read); 4862 MS : R; 4863 %} 4864 4865 // Float Store 4866 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 4867 single_instruction; 4868 mem : R(read); 4869 MS : R; 4870 %} 4871 4872 // Double Store 4873 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 4874 instruction_count(1); 4875 mem : R(read); 4876 src : C(read); 4877 MS : R; 4878 %} 4879 4880 // Double Store 4881 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 4882 single_instruction; 4883 mem : R(read); 4884 MS : R; 4885 %} 4886 4887 // Special Stack Slot Float Store 4888 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 4889 single_instruction; 4890 stkSlot : R(read); 4891 src : C(read); 4892 MS : R; 4893 %} 4894 4895 // Special Stack Slot Double Store 4896 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 4897 single_instruction; 4898 stkSlot : R(read); 4899 src : C(read); 4900 MS : R; 4901 %} 4902 4903 // Integer Load (when sign bit propagation not needed) 4904 pipe_class iload_mem(iRegI dst, memory mem) %{ 4905 single_instruction; 4906 mem : R(read); 4907 dst : C(write); 4908 MS : R; 4909 %} 4910 4911 // Integer Load from stack operand 4912 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 4913 single_instruction; 4914 mem : R(read); 4915 dst : C(write); 4916 MS : R; 4917 %} 4918 4919 // Integer Load (when sign bit propagation or masking is needed) 4920 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 4921 single_instruction; 4922 mem : R(read); 4923 dst : M(write); 4924 MS : R; 4925 %} 4926 4927 // Float Load 4928 pipe_class floadF_mem(regF dst, memory mem) %{ 4929 single_instruction; 4930 mem : R(read); 4931 dst : M(write); 4932 MS : R; 4933 %} 4934 4935 // Float Load 4936 pipe_class floadD_mem(regD dst, memory mem) %{ 4937 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 4938 mem : R(read); 4939 dst : M(write); 4940 MS : R; 4941 %} 4942 4943 // Float Load 4944 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 4945 single_instruction; 4946 stkSlot : R(read); 4947 dst : M(write); 4948 MS : R; 4949 %} 4950 4951 // Float Load 4952 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 4953 single_instruction; 4954 stkSlot : R(read); 4955 dst : M(write); 4956 MS : R; 4957 %} 4958 4959 // Memory Nop 4960 pipe_class mem_nop() %{ 4961 single_instruction; 4962 MS : R; 4963 %} 4964 4965 pipe_class sethi(iRegP dst, immI src) %{ 4966 single_instruction; 4967 dst : E(write); 4968 IALU : R; 4969 %} 4970 4971 pipe_class loadPollP(iRegP poll) %{ 4972 single_instruction; 4973 poll : R(read); 4974 MS : R; 4975 %} 4976 4977 pipe_class br(Universe br, label labl) %{ 4978 single_instruction_with_delay_slot; 4979 BR : R; 4980 %} 4981 4982 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 4983 single_instruction_with_delay_slot; 4984 cr : E(read); 4985 BR : R; 4986 %} 4987 4988 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 4989 single_instruction_with_delay_slot; 4990 op1 : E(read); 4991 BR : R; 4992 MS : R; 4993 %} 4994 4995 // Compare and branch 4996 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 4997 instruction_count(2); has_delay_slot; 4998 cr : E(write); 4999 src1 : R(read); 5000 src2 : R(read); 5001 IALU : R; 5002 BR : R; 5003 %} 5004 5005 // Compare and branch 5006 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ 5007 instruction_count(2); has_delay_slot; 5008 cr : E(write); 5009 src1 : R(read); 5010 IALU : R; 5011 BR : R; 5012 %} 5013 5014 // Compare and branch using cbcond 5015 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ 5016 single_instruction; 5017 src1 : E(read); 5018 src2 : E(read); 5019 IALU : R; 5020 BR : R; 5021 %} 5022 5023 // Compare and branch using cbcond 5024 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ 5025 single_instruction; 5026 src1 : E(read); 5027 IALU : R; 5028 BR : R; 5029 %} 5030 5031 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5032 single_instruction_with_delay_slot; 5033 cr : E(read); 5034 BR : R; 5035 %} 5036 5037 pipe_class br_nop() %{ 5038 single_instruction; 5039 BR : R; 5040 %} 5041 5042 pipe_class simple_call(method meth) %{ 5043 instruction_count(2); multiple_bundles; force_serialization; 5044 fixed_latency(100); 5045 BR : R(1); 5046 MS : R(1); 5047 A0 : R(1); 5048 %} 5049 5050 pipe_class compiled_call(method meth) %{ 5051 instruction_count(1); multiple_bundles; force_serialization; 5052 fixed_latency(100); 5053 MS : R(1); 5054 %} 5055 5056 pipe_class call(method meth) %{ 5057 instruction_count(0); multiple_bundles; force_serialization; 5058 fixed_latency(100); 5059 %} 5060 5061 pipe_class tail_call(Universe ignore, label labl) %{ 5062 single_instruction; has_delay_slot; 5063 fixed_latency(100); 5064 BR : R(1); 5065 MS : R(1); 5066 %} 5067 5068 pipe_class ret(Universe ignore) %{ 5069 single_instruction; has_delay_slot; 5070 BR : R(1); 5071 MS : R(1); 5072 %} 5073 5074 pipe_class ret_poll(g3RegP poll) %{ 5075 instruction_count(3); has_delay_slot; 5076 poll : E(read); 5077 MS : R; 5078 %} 5079 5080 // The real do-nothing guy 5081 pipe_class empty( ) %{ 5082 instruction_count(0); 5083 %} 5084 5085 pipe_class long_memory_op() %{ 5086 instruction_count(0); multiple_bundles; force_serialization; 5087 fixed_latency(25); 5088 MS : R(1); 5089 %} 5090 5091 // Check-cast 5092 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5093 array : R(read); 5094 match : R(read); 5095 IALU : R(2); 5096 BR : R(2); 5097 MS : R; 5098 %} 5099 5100 // Convert FPU flags into +1,0,-1 5101 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5102 src1 : E(read); 5103 src2 : E(read); 5104 dst : E(write); 5105 FA : R; 5106 MS : R(2); 5107 BR : R(2); 5108 %} 5109 5110 // Compare for p < q, and conditionally add y 5111 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5112 p : E(read); 5113 q : E(read); 5114 y : E(read); 5115 IALU : R(3) 5116 %} 5117 5118 // Perform a compare, then move conditionally in a branch delay slot. 5119 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5120 src2 : E(read); 5121 srcdst : E(read); 5122 IALU : R; 5123 BR : R; 5124 %} 5125 5126 // Define the class for the Nop node 5127 define %{ 5128 MachNop = ialu_nop; 5129 %} 5130 5131 %} 5132 5133 //----------INSTRUCTIONS------------------------------------------------------- 5134 5135 //------------Special Stack Slot instructions - no match rules----------------- 5136 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5137 // No match rule to avoid chain rule match. 5138 effect(DEF dst, USE src); 5139 ins_cost(MEMORY_REF_COST); 5140 format %{ "LDF $src,$dst\t! stkI to regF" %} 5141 opcode(Assembler::ldf_op3); 5142 ins_encode(simple_form3_mem_reg(src, dst)); 5143 ins_pipe(floadF_stk); 5144 %} 5145 5146 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5147 // No match rule to avoid chain rule match. 5148 effect(DEF dst, USE src); 5149 ins_cost(MEMORY_REF_COST); 5150 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5151 opcode(Assembler::lddf_op3); 5152 ins_encode(simple_form3_mem_reg(src, dst)); 5153 ins_pipe(floadD_stk); 5154 %} 5155 5156 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5157 // No match rule to avoid chain rule match. 5158 effect(DEF dst, USE src); 5159 ins_cost(MEMORY_REF_COST); 5160 format %{ "STF $src,$dst\t! regF to stkI" %} 5161 opcode(Assembler::stf_op3); 5162 ins_encode(simple_form3_mem_reg(dst, src)); 5163 ins_pipe(fstoreF_stk_reg); 5164 %} 5165 5166 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5167 // No match rule to avoid chain rule match. 5168 effect(DEF dst, USE src); 5169 ins_cost(MEMORY_REF_COST); 5170 format %{ "STDF $src,$dst\t! regD to stkL" %} 5171 opcode(Assembler::stdf_op3); 5172 ins_encode(simple_form3_mem_reg(dst, src)); 5173 ins_pipe(fstoreD_stk_reg); 5174 %} 5175 5176 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5177 effect(DEF dst, USE src); 5178 ins_cost(MEMORY_REF_COST*2); 5179 format %{ "STW $src,$dst.hi\t! long\n\t" 5180 "STW R_G0,$dst.lo" %} 5181 opcode(Assembler::stw_op3); 5182 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5183 ins_pipe(lstoreI_stk_reg); 5184 %} 5185 5186 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5187 // No match rule to avoid chain rule match. 5188 effect(DEF dst, USE src); 5189 ins_cost(MEMORY_REF_COST); 5190 format %{ "STX $src,$dst\t! regL to stkD" %} 5191 opcode(Assembler::stx_op3); 5192 ins_encode(simple_form3_mem_reg( dst, src ) ); 5193 ins_pipe(istore_stk_reg); 5194 %} 5195 5196 //---------- Chain stack slots between similar types -------- 5197 5198 // Load integer from stack slot 5199 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5200 match(Set dst src); 5201 ins_cost(MEMORY_REF_COST); 5202 5203 format %{ "LDUW $src,$dst\t!stk" %} 5204 opcode(Assembler::lduw_op3); 5205 ins_encode(simple_form3_mem_reg( src, dst ) ); 5206 ins_pipe(iload_mem); 5207 %} 5208 5209 // Store integer to stack slot 5210 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5211 match(Set dst src); 5212 ins_cost(MEMORY_REF_COST); 5213 5214 format %{ "STW $src,$dst\t!stk" %} 5215 opcode(Assembler::stw_op3); 5216 ins_encode(simple_form3_mem_reg( dst, src ) ); 5217 ins_pipe(istore_mem_reg); 5218 %} 5219 5220 // Load long from stack slot 5221 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5222 match(Set dst src); 5223 5224 ins_cost(MEMORY_REF_COST); 5225 format %{ "LDX $src,$dst\t! long" %} 5226 opcode(Assembler::ldx_op3); 5227 ins_encode(simple_form3_mem_reg( src, dst ) ); 5228 ins_pipe(iload_mem); 5229 %} 5230 5231 // Store long to stack slot 5232 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5233 match(Set dst src); 5234 5235 ins_cost(MEMORY_REF_COST); 5236 format %{ "STX $src,$dst\t! long" %} 5237 opcode(Assembler::stx_op3); 5238 ins_encode(simple_form3_mem_reg( dst, src ) ); 5239 ins_pipe(istore_mem_reg); 5240 %} 5241 5242 // Load pointer from stack slot, 64-bit encoding 5243 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5244 match(Set dst src); 5245 ins_cost(MEMORY_REF_COST); 5246 format %{ "LDX $src,$dst\t!ptr" %} 5247 opcode(Assembler::ldx_op3); 5248 ins_encode(simple_form3_mem_reg( src, dst ) ); 5249 ins_pipe(iload_mem); 5250 %} 5251 5252 // Store pointer to stack slot 5253 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5254 match(Set dst src); 5255 ins_cost(MEMORY_REF_COST); 5256 format %{ "STX $src,$dst\t!ptr" %} 5257 opcode(Assembler::stx_op3); 5258 ins_encode(simple_form3_mem_reg( dst, src ) ); 5259 ins_pipe(istore_mem_reg); 5260 %} 5261 5262 //------------Special Nop instructions for bundling - no match rules----------- 5263 // Nop using the A0 functional unit 5264 instruct Nop_A0() %{ 5265 ins_cost(0); 5266 5267 format %{ "NOP ! Alu Pipeline" %} 5268 opcode(Assembler::or_op3, Assembler::arith_op); 5269 ins_encode( form2_nop() ); 5270 ins_pipe(ialu_nop_A0); 5271 %} 5272 5273 // Nop using the A1 functional unit 5274 instruct Nop_A1( ) %{ 5275 ins_cost(0); 5276 5277 format %{ "NOP ! Alu Pipeline" %} 5278 opcode(Assembler::or_op3, Assembler::arith_op); 5279 ins_encode( form2_nop() ); 5280 ins_pipe(ialu_nop_A1); 5281 %} 5282 5283 // Nop using the memory functional unit 5284 instruct Nop_MS( ) %{ 5285 ins_cost(0); 5286 5287 format %{ "NOP ! Memory Pipeline" %} 5288 ins_encode( emit_mem_nop ); 5289 ins_pipe(mem_nop); 5290 %} 5291 5292 // Nop using the floating add functional unit 5293 instruct Nop_FA( ) %{ 5294 ins_cost(0); 5295 5296 format %{ "NOP ! Floating Add Pipeline" %} 5297 ins_encode( emit_fadd_nop ); 5298 ins_pipe(fadd_nop); 5299 %} 5300 5301 // Nop using the branch functional unit 5302 instruct Nop_BR( ) %{ 5303 ins_cost(0); 5304 5305 format %{ "NOP ! Branch Pipeline" %} 5306 ins_encode( emit_br_nop ); 5307 ins_pipe(br_nop); 5308 %} 5309 5310 //----------Load/Store/Move Instructions--------------------------------------- 5311 //----------Load Instructions-------------------------------------------------- 5312 // Load Byte (8bit signed) 5313 instruct loadB(iRegI dst, memory mem) %{ 5314 match(Set dst (LoadB mem)); 5315 ins_cost(MEMORY_REF_COST); 5316 5317 size(4); 5318 format %{ "LDSB $mem,$dst\t! byte" %} 5319 ins_encode %{ 5320 __ ldsb($mem$$Address, $dst$$Register); 5321 %} 5322 ins_pipe(iload_mask_mem); 5323 %} 5324 5325 // Load Byte (8bit signed) into a Long Register 5326 instruct loadB2L(iRegL dst, memory mem) %{ 5327 match(Set dst (ConvI2L (LoadB mem))); 5328 ins_cost(MEMORY_REF_COST); 5329 5330 size(4); 5331 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5332 ins_encode %{ 5333 __ ldsb($mem$$Address, $dst$$Register); 5334 %} 5335 ins_pipe(iload_mask_mem); 5336 %} 5337 5338 // Load Unsigned Byte (8bit UNsigned) into an int reg 5339 instruct loadUB(iRegI dst, memory mem) %{ 5340 match(Set dst (LoadUB mem)); 5341 ins_cost(MEMORY_REF_COST); 5342 5343 size(4); 5344 format %{ "LDUB $mem,$dst\t! ubyte" %} 5345 ins_encode %{ 5346 __ ldub($mem$$Address, $dst$$Register); 5347 %} 5348 ins_pipe(iload_mem); 5349 %} 5350 5351 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5352 instruct loadUB2L(iRegL dst, memory mem) %{ 5353 match(Set dst (ConvI2L (LoadUB mem))); 5354 ins_cost(MEMORY_REF_COST); 5355 5356 size(4); 5357 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5358 ins_encode %{ 5359 __ ldub($mem$$Address, $dst$$Register); 5360 %} 5361 ins_pipe(iload_mem); 5362 %} 5363 5364 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register 5365 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{ 5366 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5367 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5368 5369 size(2*4); 5370 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t" 5371 "AND $dst,right_n_bits($mask, 8),$dst" %} 5372 ins_encode %{ 5373 __ ldub($mem$$Address, $dst$$Register); 5374 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register); 5375 %} 5376 ins_pipe(iload_mem); 5377 %} 5378 5379 // Load Short (16bit signed) 5380 instruct loadS(iRegI dst, memory mem) %{ 5381 match(Set dst (LoadS mem)); 5382 ins_cost(MEMORY_REF_COST); 5383 5384 size(4); 5385 format %{ "LDSH $mem,$dst\t! short" %} 5386 ins_encode %{ 5387 __ ldsh($mem$$Address, $dst$$Register); 5388 %} 5389 ins_pipe(iload_mask_mem); 5390 %} 5391 5392 // Load Short (16 bit signed) to Byte (8 bit signed) 5393 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5394 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5395 ins_cost(MEMORY_REF_COST); 5396 5397 size(4); 5398 5399 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5400 ins_encode %{ 5401 __ ldsb($mem$$Address, $dst$$Register, 1); 5402 %} 5403 ins_pipe(iload_mask_mem); 5404 %} 5405 5406 // Load Short (16bit signed) into a Long Register 5407 instruct loadS2L(iRegL dst, memory mem) %{ 5408 match(Set dst (ConvI2L (LoadS mem))); 5409 ins_cost(MEMORY_REF_COST); 5410 5411 size(4); 5412 format %{ "LDSH $mem,$dst\t! short -> long" %} 5413 ins_encode %{ 5414 __ ldsh($mem$$Address, $dst$$Register); 5415 %} 5416 ins_pipe(iload_mask_mem); 5417 %} 5418 5419 // Load Unsigned Short/Char (16bit UNsigned) 5420 instruct loadUS(iRegI dst, memory mem) %{ 5421 match(Set dst (LoadUS mem)); 5422 ins_cost(MEMORY_REF_COST); 5423 5424 size(4); 5425 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5426 ins_encode %{ 5427 __ lduh($mem$$Address, $dst$$Register); 5428 %} 5429 ins_pipe(iload_mem); 5430 %} 5431 5432 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5433 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5434 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5435 ins_cost(MEMORY_REF_COST); 5436 5437 size(4); 5438 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5439 ins_encode %{ 5440 __ ldsb($mem$$Address, $dst$$Register, 1); 5441 %} 5442 ins_pipe(iload_mask_mem); 5443 %} 5444 5445 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5446 instruct loadUS2L(iRegL dst, memory mem) %{ 5447 match(Set dst (ConvI2L (LoadUS mem))); 5448 ins_cost(MEMORY_REF_COST); 5449 5450 size(4); 5451 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5452 ins_encode %{ 5453 __ lduh($mem$$Address, $dst$$Register); 5454 %} 5455 ins_pipe(iload_mem); 5456 %} 5457 5458 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5459 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5460 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5461 ins_cost(MEMORY_REF_COST); 5462 5463 size(4); 5464 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5465 ins_encode %{ 5466 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5467 %} 5468 ins_pipe(iload_mem); 5469 %} 5470 5471 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5472 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5473 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5474 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5475 5476 size(2*4); 5477 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5478 "AND $dst,$mask,$dst" %} 5479 ins_encode %{ 5480 Register Rdst = $dst$$Register; 5481 __ lduh($mem$$Address, Rdst); 5482 __ and3(Rdst, $mask$$constant, Rdst); 5483 %} 5484 ins_pipe(iload_mem); 5485 %} 5486 5487 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register 5488 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5489 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5490 effect(TEMP dst, TEMP tmp); 5491 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5492 5493 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t" 5494 "SET right_n_bits($mask, 16),$tmp\n\t" 5495 "AND $dst,$tmp,$dst" %} 5496 ins_encode %{ 5497 Register Rdst = $dst$$Register; 5498 Register Rtmp = $tmp$$Register; 5499 __ lduh($mem$$Address, Rdst); 5500 __ set($mask$$constant & right_n_bits(16), Rtmp); 5501 __ and3(Rdst, Rtmp, Rdst); 5502 %} 5503 ins_pipe(iload_mem); 5504 %} 5505 5506 // Load Integer 5507 instruct loadI(iRegI dst, memory mem) %{ 5508 match(Set dst (LoadI mem)); 5509 ins_cost(MEMORY_REF_COST); 5510 5511 size(4); 5512 format %{ "LDUW $mem,$dst\t! int" %} 5513 ins_encode %{ 5514 __ lduw($mem$$Address, $dst$$Register); 5515 %} 5516 ins_pipe(iload_mem); 5517 %} 5518 5519 // Load Integer to Byte (8 bit signed) 5520 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5521 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5522 ins_cost(MEMORY_REF_COST); 5523 5524 size(4); 5525 5526 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5527 ins_encode %{ 5528 __ ldsb($mem$$Address, $dst$$Register, 3); 5529 %} 5530 ins_pipe(iload_mask_mem); 5531 %} 5532 5533 // Load Integer to Unsigned Byte (8 bit UNsigned) 5534 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5535 match(Set dst (AndI (LoadI mem) mask)); 5536 ins_cost(MEMORY_REF_COST); 5537 5538 size(4); 5539 5540 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5541 ins_encode %{ 5542 __ ldub($mem$$Address, $dst$$Register, 3); 5543 %} 5544 ins_pipe(iload_mask_mem); 5545 %} 5546 5547 // Load Integer to Short (16 bit signed) 5548 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5549 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5550 ins_cost(MEMORY_REF_COST); 5551 5552 size(4); 5553 5554 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5555 ins_encode %{ 5556 __ ldsh($mem$$Address, $dst$$Register, 2); 5557 %} 5558 ins_pipe(iload_mask_mem); 5559 %} 5560 5561 // Load Integer to Unsigned Short (16 bit UNsigned) 5562 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5563 match(Set dst (AndI (LoadI mem) mask)); 5564 ins_cost(MEMORY_REF_COST); 5565 5566 size(4); 5567 5568 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5569 ins_encode %{ 5570 __ lduh($mem$$Address, $dst$$Register, 2); 5571 %} 5572 ins_pipe(iload_mask_mem); 5573 %} 5574 5575 // Load Integer into a Long Register 5576 instruct loadI2L(iRegL dst, memory mem) %{ 5577 match(Set dst (ConvI2L (LoadI mem))); 5578 ins_cost(MEMORY_REF_COST); 5579 5580 size(4); 5581 format %{ "LDSW $mem,$dst\t! int -> long" %} 5582 ins_encode %{ 5583 __ ldsw($mem$$Address, $dst$$Register); 5584 %} 5585 ins_pipe(iload_mask_mem); 5586 %} 5587 5588 // Load Integer with mask 0xFF into a Long Register 5589 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5590 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5591 ins_cost(MEMORY_REF_COST); 5592 5593 size(4); 5594 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5595 ins_encode %{ 5596 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5597 %} 5598 ins_pipe(iload_mem); 5599 %} 5600 5601 // Load Integer with mask 0xFFFF into a Long Register 5602 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5603 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5604 ins_cost(MEMORY_REF_COST); 5605 5606 size(4); 5607 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5608 ins_encode %{ 5609 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5610 %} 5611 ins_pipe(iload_mem); 5612 %} 5613 5614 // Load Integer with a 12-bit mask into a Long Register 5615 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ 5616 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5617 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5618 5619 size(2*4); 5620 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" 5621 "AND $dst,$mask,$dst" %} 5622 ins_encode %{ 5623 Register Rdst = $dst$$Register; 5624 __ lduw($mem$$Address, Rdst); 5625 __ and3(Rdst, $mask$$constant, Rdst); 5626 %} 5627 ins_pipe(iload_mem); 5628 %} 5629 5630 // Load Integer with a 31-bit mask into a Long Register 5631 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ 5632 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5633 effect(TEMP dst, TEMP tmp); 5634 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5635 5636 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" 5637 "SET $mask,$tmp\n\t" 5638 "AND $dst,$tmp,$dst" %} 5639 ins_encode %{ 5640 Register Rdst = $dst$$Register; 5641 Register Rtmp = $tmp$$Register; 5642 __ lduw($mem$$Address, Rdst); 5643 __ set($mask$$constant, Rtmp); 5644 __ and3(Rdst, Rtmp, Rdst); 5645 %} 5646 ins_pipe(iload_mem); 5647 %} 5648 5649 // Load Unsigned Integer into a Long Register 5650 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ 5651 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5652 ins_cost(MEMORY_REF_COST); 5653 5654 size(4); 5655 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5656 ins_encode %{ 5657 __ lduw($mem$$Address, $dst$$Register); 5658 %} 5659 ins_pipe(iload_mem); 5660 %} 5661 5662 // Load Long - aligned 5663 instruct loadL(iRegL dst, memory mem ) %{ 5664 match(Set dst (LoadL mem)); 5665 ins_cost(MEMORY_REF_COST); 5666 5667 size(4); 5668 format %{ "LDX $mem,$dst\t! long" %} 5669 ins_encode %{ 5670 __ ldx($mem$$Address, $dst$$Register); 5671 %} 5672 ins_pipe(iload_mem); 5673 %} 5674 5675 // Load Long - UNaligned 5676 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5677 match(Set dst (LoadL_unaligned mem)); 5678 effect(KILL tmp); 5679 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5680 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5681 "\tLDUW $mem ,$dst\n" 5682 "\tSLLX #32, $dst, $dst\n" 5683 "\tOR $dst, R_O7, $dst" %} 5684 opcode(Assembler::lduw_op3); 5685 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5686 ins_pipe(iload_mem); 5687 %} 5688 5689 // Load Range 5690 instruct loadRange(iRegI dst, memory mem) %{ 5691 match(Set dst (LoadRange mem)); 5692 ins_cost(MEMORY_REF_COST); 5693 5694 format %{ "LDUW $mem,$dst\t! range" %} 5695 opcode(Assembler::lduw_op3); 5696 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5697 ins_pipe(iload_mem); 5698 %} 5699 5700 // Load Integer into %f register (for fitos/fitod) 5701 instruct loadI_freg(regF dst, memory mem) %{ 5702 match(Set dst (LoadI mem)); 5703 ins_cost(MEMORY_REF_COST); 5704 5705 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5706 opcode(Assembler::ldf_op3); 5707 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5708 ins_pipe(floadF_mem); 5709 %} 5710 5711 // Load Pointer 5712 instruct loadP(iRegP dst, memory mem) %{ 5713 match(Set dst (LoadP mem)); 5714 ins_cost(MEMORY_REF_COST); 5715 size(4); 5716 5717 format %{ "LDX $mem,$dst\t! ptr" %} 5718 ins_encode %{ 5719 __ ldx($mem$$Address, $dst$$Register); 5720 %} 5721 ins_pipe(iload_mem); 5722 %} 5723 5724 // Load Compressed Pointer 5725 instruct loadN(iRegN dst, memory mem) %{ 5726 match(Set dst (LoadN mem)); 5727 ins_cost(MEMORY_REF_COST); 5728 size(4); 5729 5730 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5731 ins_encode %{ 5732 __ lduw($mem$$Address, $dst$$Register); 5733 %} 5734 ins_pipe(iload_mem); 5735 %} 5736 5737 // Load Klass Pointer 5738 instruct loadKlass(iRegP dst, memory mem) %{ 5739 match(Set dst (LoadKlass mem)); 5740 ins_cost(MEMORY_REF_COST); 5741 size(4); 5742 5743 format %{ "LDX $mem,$dst\t! klass ptr" %} 5744 ins_encode %{ 5745 __ ldx($mem$$Address, $dst$$Register); 5746 %} 5747 ins_pipe(iload_mem); 5748 %} 5749 5750 // Load narrow Klass Pointer 5751 instruct loadNKlass(iRegN dst, memory mem) %{ 5752 match(Set dst (LoadNKlass mem)); 5753 ins_cost(MEMORY_REF_COST); 5754 size(4); 5755 5756 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5757 ins_encode %{ 5758 __ lduw($mem$$Address, $dst$$Register); 5759 %} 5760 ins_pipe(iload_mem); 5761 %} 5762 5763 // Load Double 5764 instruct loadD(regD dst, memory mem) %{ 5765 match(Set dst (LoadD mem)); 5766 ins_cost(MEMORY_REF_COST); 5767 5768 format %{ "LDDF $mem,$dst" %} 5769 opcode(Assembler::lddf_op3); 5770 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5771 ins_pipe(floadD_mem); 5772 %} 5773 5774 // Load Double - UNaligned 5775 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 5776 match(Set dst (LoadD_unaligned mem)); 5777 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5778 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 5779 "\tLDF $mem+4,$dst.lo\t!" %} 5780 opcode(Assembler::ldf_op3); 5781 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 5782 ins_pipe(iload_mem); 5783 %} 5784 5785 // Load Float 5786 instruct loadF(regF dst, memory mem) %{ 5787 match(Set dst (LoadF mem)); 5788 ins_cost(MEMORY_REF_COST); 5789 5790 format %{ "LDF $mem,$dst" %} 5791 opcode(Assembler::ldf_op3); 5792 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5793 ins_pipe(floadF_mem); 5794 %} 5795 5796 // Load Constant 5797 instruct loadConI( iRegI dst, immI src ) %{ 5798 match(Set dst src); 5799 ins_cost(DEFAULT_COST * 3/2); 5800 format %{ "SET $src,$dst" %} 5801 ins_encode( Set32(src, dst) ); 5802 ins_pipe(ialu_hi_lo_reg); 5803 %} 5804 5805 instruct loadConI13( iRegI dst, immI13 src ) %{ 5806 match(Set dst src); 5807 5808 size(4); 5809 format %{ "MOV $src,$dst" %} 5810 ins_encode( Set13( src, dst ) ); 5811 ins_pipe(ialu_imm); 5812 %} 5813 5814 instruct loadConP_set(iRegP dst, immP_set con) %{ 5815 match(Set dst con); 5816 ins_cost(DEFAULT_COST * 3/2); 5817 format %{ "SET $con,$dst\t! ptr" %} 5818 ins_encode %{ 5819 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 5820 intptr_t val = $con$$constant; 5821 if (constant_reloc == relocInfo::oop_type) { 5822 __ set_oop_constant((jobject) val, $dst$$Register); 5823 } else if (constant_reloc == relocInfo::metadata_type) { 5824 __ set_metadata_constant((Metadata*)val, $dst$$Register); 5825 } else { // non-oop pointers, e.g. card mark base, heap top 5826 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 5827 __ set(val, $dst$$Register); 5828 } 5829 %} 5830 ins_pipe(loadConP); 5831 %} 5832 5833 instruct loadConP_load(iRegP dst, immP_load con) %{ 5834 match(Set dst con); 5835 ins_cost(MEMORY_REF_COST); 5836 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} 5837 ins_encode %{ 5838 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 5839 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); 5840 %} 5841 ins_pipe(loadConP); 5842 %} 5843 5844 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ 5845 match(Set dst con); 5846 ins_cost(DEFAULT_COST * 3/2); 5847 format %{ "SET $con,$dst\t! non-oop ptr" %} 5848 ins_encode %{ 5849 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) { 5850 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register); 5851 } else { 5852 __ set($con$$constant, $dst$$Register); 5853 } 5854 %} 5855 ins_pipe(loadConP); 5856 %} 5857 5858 instruct loadConP0(iRegP dst, immP0 src) %{ 5859 match(Set dst src); 5860 5861 size(4); 5862 format %{ "CLR $dst\t!ptr" %} 5863 ins_encode %{ 5864 __ clr($dst$$Register); 5865 %} 5866 ins_pipe(ialu_imm); 5867 %} 5868 5869 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 5870 match(Set dst src); 5871 ins_cost(DEFAULT_COST); 5872 format %{ "SET $src,$dst\t!ptr" %} 5873 ins_encode %{ 5874 AddressLiteral polling_page(os::get_polling_page()); 5875 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 5876 %} 5877 ins_pipe(loadConP_poll); 5878 %} 5879 5880 instruct loadConN0(iRegN dst, immN0 src) %{ 5881 match(Set dst src); 5882 5883 size(4); 5884 format %{ "CLR $dst\t! compressed NULL ptr" %} 5885 ins_encode %{ 5886 __ clr($dst$$Register); 5887 %} 5888 ins_pipe(ialu_imm); 5889 %} 5890 5891 instruct loadConN(iRegN dst, immN src) %{ 5892 match(Set dst src); 5893 ins_cost(DEFAULT_COST * 3/2); 5894 format %{ "SET $src,$dst\t! compressed ptr" %} 5895 ins_encode %{ 5896 Register dst = $dst$$Register; 5897 __ set_narrow_oop((jobject)$src$$constant, dst); 5898 %} 5899 ins_pipe(ialu_hi_lo_reg); 5900 %} 5901 5902 instruct loadConNKlass(iRegN dst, immNKlass src) %{ 5903 match(Set dst src); 5904 ins_cost(DEFAULT_COST * 3/2); 5905 format %{ "SET $src,$dst\t! compressed klass ptr" %} 5906 ins_encode %{ 5907 Register dst = $dst$$Register; 5908 __ set_narrow_klass((Klass*)$src$$constant, dst); 5909 %} 5910 ins_pipe(ialu_hi_lo_reg); 5911 %} 5912 5913 // Materialize long value (predicated by immL_cheap). 5914 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ 5915 match(Set dst con); 5916 effect(KILL tmp); 5917 ins_cost(DEFAULT_COST * 3); 5918 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} 5919 ins_encode %{ 5920 __ set64($con$$constant, $dst$$Register, $tmp$$Register); 5921 %} 5922 ins_pipe(loadConL); 5923 %} 5924 5925 // Load long value from constant table (predicated by immL_expensive). 5926 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ 5927 match(Set dst con); 5928 ins_cost(MEMORY_REF_COST); 5929 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} 5930 ins_encode %{ 5931 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 5932 __ ldx($constanttablebase, con_offset, $dst$$Register); 5933 %} 5934 ins_pipe(loadConL); 5935 %} 5936 5937 instruct loadConL0( iRegL dst, immL0 src ) %{ 5938 match(Set dst src); 5939 ins_cost(DEFAULT_COST); 5940 size(4); 5941 format %{ "CLR $dst\t! long" %} 5942 ins_encode( Set13( src, dst ) ); 5943 ins_pipe(ialu_imm); 5944 %} 5945 5946 instruct loadConL13( iRegL dst, immL13 src ) %{ 5947 match(Set dst src); 5948 ins_cost(DEFAULT_COST * 2); 5949 5950 size(4); 5951 format %{ "MOV $src,$dst\t! long" %} 5952 ins_encode( Set13( src, dst ) ); 5953 ins_pipe(ialu_imm); 5954 %} 5955 5956 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ 5957 match(Set dst con); 5958 effect(KILL tmp); 5959 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} 5960 ins_encode %{ 5961 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 5962 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); 5963 %} 5964 ins_pipe(loadConFD); 5965 %} 5966 5967 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ 5968 match(Set dst con); 5969 effect(KILL tmp); 5970 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} 5971 ins_encode %{ 5972 // XXX This is a quick fix for 6833573. 5973 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 5974 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 5975 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 5976 %} 5977 ins_pipe(loadConFD); 5978 %} 5979 5980 // Prefetch instructions for allocation. 5981 // Must be safe to execute with invalid address (cannot fault). 5982 5983 instruct prefetchAlloc( memory mem ) %{ 5984 predicate(AllocatePrefetchInstr == 0); 5985 match( PrefetchAllocation mem ); 5986 ins_cost(MEMORY_REF_COST); 5987 5988 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} 5989 opcode(Assembler::prefetch_op3); 5990 ins_encode( form3_mem_prefetch_write( mem ) ); 5991 ins_pipe(iload_mem); 5992 %} 5993 5994 // Use BIS instruction to prefetch for allocation. 5995 // Could fault, need space at the end of TLAB. 5996 instruct prefetchAlloc_bis( iRegP dst ) %{ 5997 predicate(AllocatePrefetchInstr == 1); 5998 match( PrefetchAllocation dst ); 5999 ins_cost(MEMORY_REF_COST); 6000 size(4); 6001 6002 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} 6003 ins_encode %{ 6004 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); 6005 %} 6006 ins_pipe(istore_mem_reg); 6007 %} 6008 6009 // Next code is used for finding next cache line address to prefetch. 6010 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ 6011 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 6012 ins_cost(DEFAULT_COST); 6013 size(4); 6014 6015 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 6016 ins_encode %{ 6017 __ and3($src$$Register, $mask$$constant, $dst$$Register); 6018 %} 6019 ins_pipe(ialu_reg_imm); 6020 %} 6021 6022 //----------Store Instructions------------------------------------------------- 6023 // Store Byte 6024 instruct storeB(memory mem, iRegI src) %{ 6025 match(Set mem (StoreB mem src)); 6026 ins_cost(MEMORY_REF_COST); 6027 6028 format %{ "STB $src,$mem\t! byte" %} 6029 opcode(Assembler::stb_op3); 6030 ins_encode(simple_form3_mem_reg( mem, src ) ); 6031 ins_pipe(istore_mem_reg); 6032 %} 6033 6034 instruct storeB0(memory mem, immI0 src) %{ 6035 match(Set mem (StoreB mem src)); 6036 ins_cost(MEMORY_REF_COST); 6037 6038 format %{ "STB $src,$mem\t! byte" %} 6039 opcode(Assembler::stb_op3); 6040 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6041 ins_pipe(istore_mem_zero); 6042 %} 6043 6044 instruct storeCM0(memory mem, immI0 src) %{ 6045 match(Set mem (StoreCM mem src)); 6046 ins_cost(MEMORY_REF_COST); 6047 6048 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 6049 opcode(Assembler::stb_op3); 6050 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6051 ins_pipe(istore_mem_zero); 6052 %} 6053 6054 // Store Char/Short 6055 instruct storeC(memory mem, iRegI src) %{ 6056 match(Set mem (StoreC mem src)); 6057 ins_cost(MEMORY_REF_COST); 6058 6059 format %{ "STH $src,$mem\t! short" %} 6060 opcode(Assembler::sth_op3); 6061 ins_encode(simple_form3_mem_reg( mem, src ) ); 6062 ins_pipe(istore_mem_reg); 6063 %} 6064 6065 instruct storeC0(memory mem, immI0 src) %{ 6066 match(Set mem (StoreC mem src)); 6067 ins_cost(MEMORY_REF_COST); 6068 6069 format %{ "STH $src,$mem\t! short" %} 6070 opcode(Assembler::sth_op3); 6071 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6072 ins_pipe(istore_mem_zero); 6073 %} 6074 6075 // Store Integer 6076 instruct storeI(memory mem, iRegI src) %{ 6077 match(Set mem (StoreI mem src)); 6078 ins_cost(MEMORY_REF_COST); 6079 6080 format %{ "STW $src,$mem" %} 6081 opcode(Assembler::stw_op3); 6082 ins_encode(simple_form3_mem_reg( mem, src ) ); 6083 ins_pipe(istore_mem_reg); 6084 %} 6085 6086 // Store Long 6087 instruct storeL(memory mem, iRegL src) %{ 6088 match(Set mem (StoreL mem src)); 6089 ins_cost(MEMORY_REF_COST); 6090 format %{ "STX $src,$mem\t! long" %} 6091 opcode(Assembler::stx_op3); 6092 ins_encode(simple_form3_mem_reg( mem, src ) ); 6093 ins_pipe(istore_mem_reg); 6094 %} 6095 6096 instruct storeI0(memory mem, immI0 src) %{ 6097 match(Set mem (StoreI mem src)); 6098 ins_cost(MEMORY_REF_COST); 6099 6100 format %{ "STW $src,$mem" %} 6101 opcode(Assembler::stw_op3); 6102 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6103 ins_pipe(istore_mem_zero); 6104 %} 6105 6106 instruct storeL0(memory mem, immL0 src) %{ 6107 match(Set mem (StoreL mem src)); 6108 ins_cost(MEMORY_REF_COST); 6109 6110 format %{ "STX $src,$mem" %} 6111 opcode(Assembler::stx_op3); 6112 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6113 ins_pipe(istore_mem_zero); 6114 %} 6115 6116 // Store Integer from float register (used after fstoi) 6117 instruct storeI_Freg(memory mem, regF src) %{ 6118 match(Set mem (StoreI mem src)); 6119 ins_cost(MEMORY_REF_COST); 6120 6121 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6122 opcode(Assembler::stf_op3); 6123 ins_encode(simple_form3_mem_reg( mem, src ) ); 6124 ins_pipe(fstoreF_mem_reg); 6125 %} 6126 6127 // Store Pointer 6128 instruct storeP(memory dst, sp_ptr_RegP src) %{ 6129 match(Set dst (StoreP dst src)); 6130 ins_cost(MEMORY_REF_COST); 6131 6132 format %{ "STX $src,$dst\t! ptr" %} 6133 opcode(Assembler::stx_op3, 0, REGP_OP); 6134 ins_encode( form3_mem_reg( dst, src ) ); 6135 ins_pipe(istore_mem_spORreg); 6136 %} 6137 6138 instruct storeP0(memory dst, immP0 src) %{ 6139 match(Set dst (StoreP dst src)); 6140 ins_cost(MEMORY_REF_COST); 6141 6142 format %{ "STX $src,$dst\t! ptr" %} 6143 opcode(Assembler::stx_op3, 0, REGP_OP); 6144 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6145 ins_pipe(istore_mem_zero); 6146 %} 6147 6148 // Store Compressed Pointer 6149 instruct storeN(memory dst, iRegN src) %{ 6150 match(Set dst (StoreN dst src)); 6151 ins_cost(MEMORY_REF_COST); 6152 size(4); 6153 6154 format %{ "STW $src,$dst\t! compressed ptr" %} 6155 ins_encode %{ 6156 Register base = as_Register($dst$$base); 6157 Register index = as_Register($dst$$index); 6158 Register src = $src$$Register; 6159 if (index != G0) { 6160 __ stw(src, base, index); 6161 } else { 6162 __ stw(src, base, $dst$$disp); 6163 } 6164 %} 6165 ins_pipe(istore_mem_spORreg); 6166 %} 6167 6168 instruct storeNKlass(memory dst, iRegN src) %{ 6169 match(Set dst (StoreNKlass dst src)); 6170 ins_cost(MEMORY_REF_COST); 6171 size(4); 6172 6173 format %{ "STW $src,$dst\t! compressed klass ptr" %} 6174 ins_encode %{ 6175 Register base = as_Register($dst$$base); 6176 Register index = as_Register($dst$$index); 6177 Register src = $src$$Register; 6178 if (index != G0) { 6179 __ stw(src, base, index); 6180 } else { 6181 __ stw(src, base, $dst$$disp); 6182 } 6183 %} 6184 ins_pipe(istore_mem_spORreg); 6185 %} 6186 6187 instruct storeN0(memory dst, immN0 src) %{ 6188 match(Set dst (StoreN dst src)); 6189 ins_cost(MEMORY_REF_COST); 6190 size(4); 6191 6192 format %{ "STW $src,$dst\t! compressed ptr" %} 6193 ins_encode %{ 6194 Register base = as_Register($dst$$base); 6195 Register index = as_Register($dst$$index); 6196 if (index != G0) { 6197 __ stw(0, base, index); 6198 } else { 6199 __ stw(0, base, $dst$$disp); 6200 } 6201 %} 6202 ins_pipe(istore_mem_zero); 6203 %} 6204 6205 // Store Double 6206 instruct storeD( memory mem, regD src) %{ 6207 match(Set mem (StoreD mem src)); 6208 ins_cost(MEMORY_REF_COST); 6209 6210 format %{ "STDF $src,$mem" %} 6211 opcode(Assembler::stdf_op3); 6212 ins_encode(simple_form3_mem_reg( mem, src ) ); 6213 ins_pipe(fstoreD_mem_reg); 6214 %} 6215 6216 instruct storeD0( memory mem, immD0 src) %{ 6217 match(Set mem (StoreD mem src)); 6218 ins_cost(MEMORY_REF_COST); 6219 6220 format %{ "STX $src,$mem" %} 6221 opcode(Assembler::stx_op3); 6222 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6223 ins_pipe(fstoreD_mem_zero); 6224 %} 6225 6226 // Store Float 6227 instruct storeF( memory mem, regF src) %{ 6228 match(Set mem (StoreF mem src)); 6229 ins_cost(MEMORY_REF_COST); 6230 6231 format %{ "STF $src,$mem" %} 6232 opcode(Assembler::stf_op3); 6233 ins_encode(simple_form3_mem_reg( mem, src ) ); 6234 ins_pipe(fstoreF_mem_reg); 6235 %} 6236 6237 instruct storeF0( memory mem, immF0 src) %{ 6238 match(Set mem (StoreF mem src)); 6239 ins_cost(MEMORY_REF_COST); 6240 6241 format %{ "STW $src,$mem\t! storeF0" %} 6242 opcode(Assembler::stw_op3); 6243 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6244 ins_pipe(fstoreF_mem_zero); 6245 %} 6246 6247 // Convert oop pointer into compressed form 6248 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6249 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6250 match(Set dst (EncodeP src)); 6251 format %{ "encode_heap_oop $src, $dst" %} 6252 ins_encode %{ 6253 __ encode_heap_oop($src$$Register, $dst$$Register); 6254 %} 6255 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE); 6256 ins_pipe(ialu_reg); 6257 %} 6258 6259 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6260 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6261 match(Set dst (EncodeP src)); 6262 format %{ "encode_heap_oop_not_null $src, $dst" %} 6263 ins_encode %{ 6264 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6265 %} 6266 ins_pipe(ialu_reg); 6267 %} 6268 6269 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6270 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6271 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6272 match(Set dst (DecodeN src)); 6273 format %{ "decode_heap_oop $src, $dst" %} 6274 ins_encode %{ 6275 __ decode_heap_oop($src$$Register, $dst$$Register); 6276 %} 6277 ins_pipe(ialu_reg); 6278 %} 6279 6280 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6281 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6282 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6283 match(Set dst (DecodeN src)); 6284 format %{ "decode_heap_oop_not_null $src, $dst" %} 6285 ins_encode %{ 6286 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6287 %} 6288 ins_pipe(ialu_reg); 6289 %} 6290 6291 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ 6292 match(Set dst (EncodePKlass src)); 6293 format %{ "encode_klass_not_null $src, $dst" %} 6294 ins_encode %{ 6295 __ encode_klass_not_null($src$$Register, $dst$$Register); 6296 %} 6297 ins_pipe(ialu_reg); 6298 %} 6299 6300 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ 6301 match(Set dst (DecodeNKlass src)); 6302 format %{ "decode_klass_not_null $src, $dst" %} 6303 ins_encode %{ 6304 __ decode_klass_not_null($src$$Register, $dst$$Register); 6305 %} 6306 ins_pipe(ialu_reg); 6307 %} 6308 6309 //----------MemBar Instructions----------------------------------------------- 6310 // Memory barrier flavors 6311 6312 instruct membar_acquire() %{ 6313 match(MemBarAcquire); 6314 match(LoadFence); 6315 ins_cost(4*MEMORY_REF_COST); 6316 6317 size(0); 6318 format %{ "MEMBAR-acquire" %} 6319 ins_encode( enc_membar_acquire ); 6320 ins_pipe(long_memory_op); 6321 %} 6322 6323 instruct membar_acquire_lock() %{ 6324 match(MemBarAcquireLock); 6325 ins_cost(0); 6326 6327 size(0); 6328 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6329 ins_encode( ); 6330 ins_pipe(empty); 6331 %} 6332 6333 instruct membar_release() %{ 6334 match(MemBarRelease); 6335 match(StoreFence); 6336 ins_cost(4*MEMORY_REF_COST); 6337 6338 size(0); 6339 format %{ "MEMBAR-release" %} 6340 ins_encode( enc_membar_release ); 6341 ins_pipe(long_memory_op); 6342 %} 6343 6344 instruct membar_release_lock() %{ 6345 match(MemBarReleaseLock); 6346 ins_cost(0); 6347 6348 size(0); 6349 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6350 ins_encode( ); 6351 ins_pipe(empty); 6352 %} 6353 6354 instruct membar_volatile() %{ 6355 match(MemBarVolatile); 6356 ins_cost(4*MEMORY_REF_COST); 6357 6358 size(4); 6359 format %{ "MEMBAR-volatile" %} 6360 ins_encode( enc_membar_volatile ); 6361 ins_pipe(long_memory_op); 6362 %} 6363 6364 instruct unnecessary_membar_volatile() %{ 6365 match(MemBarVolatile); 6366 predicate(Matcher::post_store_load_barrier(n)); 6367 ins_cost(0); 6368 6369 size(0); 6370 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6371 ins_encode( ); 6372 ins_pipe(empty); 6373 %} 6374 6375 instruct membar_storestore() %{ 6376 match(MemBarStoreStore); 6377 ins_cost(0); 6378 6379 size(0); 6380 format %{ "!MEMBAR-storestore (empty encoding)" %} 6381 ins_encode( ); 6382 ins_pipe(empty); 6383 %} 6384 6385 //----------Register Move Instructions----------------------------------------- 6386 instruct roundDouble_nop(regD dst) %{ 6387 match(Set dst (RoundDouble dst)); 6388 ins_cost(0); 6389 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6390 ins_encode( ); 6391 ins_pipe(empty); 6392 %} 6393 6394 6395 instruct roundFloat_nop(regF dst) %{ 6396 match(Set dst (RoundFloat dst)); 6397 ins_cost(0); 6398 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6399 ins_encode( ); 6400 ins_pipe(empty); 6401 %} 6402 6403 6404 // Cast Index to Pointer for unsafe natives 6405 instruct castX2P(iRegX src, iRegP dst) %{ 6406 match(Set dst (CastX2P src)); 6407 6408 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6409 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6410 ins_pipe(ialu_reg); 6411 %} 6412 6413 // Cast Pointer to Index for unsafe natives 6414 instruct castP2X(iRegP src, iRegX dst) %{ 6415 match(Set dst (CastP2X src)); 6416 6417 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6418 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6419 ins_pipe(ialu_reg); 6420 %} 6421 6422 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6423 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6424 match(Set stkSlot src); // chain rule 6425 ins_cost(MEMORY_REF_COST); 6426 format %{ "STDF $src,$stkSlot\t!stk" %} 6427 opcode(Assembler::stdf_op3); 6428 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6429 ins_pipe(fstoreD_stk_reg); 6430 %} 6431 6432 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6433 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6434 match(Set dst stkSlot); // chain rule 6435 ins_cost(MEMORY_REF_COST); 6436 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6437 opcode(Assembler::lddf_op3); 6438 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6439 ins_pipe(floadD_stk); 6440 %} 6441 6442 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6443 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6444 match(Set stkSlot src); // chain rule 6445 ins_cost(MEMORY_REF_COST); 6446 format %{ "STF $src,$stkSlot\t!stk" %} 6447 opcode(Assembler::stf_op3); 6448 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6449 ins_pipe(fstoreF_stk_reg); 6450 %} 6451 6452 //----------Conditional Move--------------------------------------------------- 6453 // Conditional move 6454 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6455 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6456 ins_cost(150); 6457 format %{ "MOV$cmp $pcc,$src,$dst" %} 6458 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6459 ins_pipe(ialu_reg); 6460 %} 6461 6462 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6463 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6464 ins_cost(140); 6465 format %{ "MOV$cmp $pcc,$src,$dst" %} 6466 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6467 ins_pipe(ialu_imm); 6468 %} 6469 6470 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6471 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6472 ins_cost(150); 6473 size(4); 6474 format %{ "MOV$cmp $icc,$src,$dst" %} 6475 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6476 ins_pipe(ialu_reg); 6477 %} 6478 6479 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6480 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6481 ins_cost(140); 6482 size(4); 6483 format %{ "MOV$cmp $icc,$src,$dst" %} 6484 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6485 ins_pipe(ialu_imm); 6486 %} 6487 6488 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6489 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6490 ins_cost(150); 6491 size(4); 6492 format %{ "MOV$cmp $icc,$src,$dst" %} 6493 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6494 ins_pipe(ialu_reg); 6495 %} 6496 6497 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6498 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6499 ins_cost(140); 6500 size(4); 6501 format %{ "MOV$cmp $icc,$src,$dst" %} 6502 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6503 ins_pipe(ialu_imm); 6504 %} 6505 6506 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6507 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6508 ins_cost(150); 6509 size(4); 6510 format %{ "MOV$cmp $fcc,$src,$dst" %} 6511 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6512 ins_pipe(ialu_reg); 6513 %} 6514 6515 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6516 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6517 ins_cost(140); 6518 size(4); 6519 format %{ "MOV$cmp $fcc,$src,$dst" %} 6520 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6521 ins_pipe(ialu_imm); 6522 %} 6523 6524 // Conditional move for RegN. Only cmov(reg,reg). 6525 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6526 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6527 ins_cost(150); 6528 format %{ "MOV$cmp $pcc,$src,$dst" %} 6529 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6530 ins_pipe(ialu_reg); 6531 %} 6532 6533 // This instruction also works with CmpN so we don't need cmovNN_reg. 6534 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6535 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6536 ins_cost(150); 6537 size(4); 6538 format %{ "MOV$cmp $icc,$src,$dst" %} 6539 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6540 ins_pipe(ialu_reg); 6541 %} 6542 6543 // This instruction also works with CmpN so we don't need cmovNN_reg. 6544 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6545 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6546 ins_cost(150); 6547 size(4); 6548 format %{ "MOV$cmp $icc,$src,$dst" %} 6549 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6550 ins_pipe(ialu_reg); 6551 %} 6552 6553 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6554 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6555 ins_cost(150); 6556 size(4); 6557 format %{ "MOV$cmp $fcc,$src,$dst" %} 6558 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6559 ins_pipe(ialu_reg); 6560 %} 6561 6562 // Conditional move 6563 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6564 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6565 ins_cost(150); 6566 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6567 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6568 ins_pipe(ialu_reg); 6569 %} 6570 6571 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6572 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6573 ins_cost(140); 6574 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6575 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6576 ins_pipe(ialu_imm); 6577 %} 6578 6579 // This instruction also works with CmpN so we don't need cmovPN_reg. 6580 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6581 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6582 ins_cost(150); 6583 6584 size(4); 6585 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6586 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6587 ins_pipe(ialu_reg); 6588 %} 6589 6590 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6591 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6592 ins_cost(150); 6593 6594 size(4); 6595 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6596 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6597 ins_pipe(ialu_reg); 6598 %} 6599 6600 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6601 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6602 ins_cost(140); 6603 6604 size(4); 6605 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6606 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6607 ins_pipe(ialu_imm); 6608 %} 6609 6610 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6611 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6612 ins_cost(140); 6613 6614 size(4); 6615 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6616 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6617 ins_pipe(ialu_imm); 6618 %} 6619 6620 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6621 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6622 ins_cost(150); 6623 size(4); 6624 format %{ "MOV$cmp $fcc,$src,$dst" %} 6625 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6626 ins_pipe(ialu_imm); 6627 %} 6628 6629 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6630 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6631 ins_cost(140); 6632 size(4); 6633 format %{ "MOV$cmp $fcc,$src,$dst" %} 6634 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6635 ins_pipe(ialu_imm); 6636 %} 6637 6638 // Conditional move 6639 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6640 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6641 ins_cost(150); 6642 opcode(0x101); 6643 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6644 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6645 ins_pipe(int_conditional_float_move); 6646 %} 6647 6648 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6649 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6650 ins_cost(150); 6651 6652 size(4); 6653 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6654 opcode(0x101); 6655 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6656 ins_pipe(int_conditional_float_move); 6657 %} 6658 6659 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 6660 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6661 ins_cost(150); 6662 6663 size(4); 6664 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6665 opcode(0x101); 6666 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6667 ins_pipe(int_conditional_float_move); 6668 %} 6669 6670 // Conditional move, 6671 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6672 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6673 ins_cost(150); 6674 size(4); 6675 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6676 opcode(0x1); 6677 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6678 ins_pipe(int_conditional_double_move); 6679 %} 6680 6681 // Conditional move 6682 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6683 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6684 ins_cost(150); 6685 size(4); 6686 opcode(0x102); 6687 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6688 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6689 ins_pipe(int_conditional_double_move); 6690 %} 6691 6692 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6693 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6694 ins_cost(150); 6695 6696 size(4); 6697 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6698 opcode(0x102); 6699 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6700 ins_pipe(int_conditional_double_move); 6701 %} 6702 6703 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 6704 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6705 ins_cost(150); 6706 6707 size(4); 6708 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6709 opcode(0x102); 6710 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6711 ins_pipe(int_conditional_double_move); 6712 %} 6713 6714 // Conditional move, 6715 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6716 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6717 ins_cost(150); 6718 size(4); 6719 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6720 opcode(0x2); 6721 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6722 ins_pipe(int_conditional_double_move); 6723 %} 6724 6725 // Conditional move 6726 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6727 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6728 ins_cost(150); 6729 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6730 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6731 ins_pipe(ialu_reg); 6732 %} 6733 6734 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6735 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6736 ins_cost(140); 6737 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6738 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6739 ins_pipe(ialu_imm); 6740 %} 6741 6742 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6743 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6744 ins_cost(150); 6745 6746 size(4); 6747 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6748 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6749 ins_pipe(ialu_reg); 6750 %} 6751 6752 6753 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 6754 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6755 ins_cost(150); 6756 6757 size(4); 6758 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6759 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6760 ins_pipe(ialu_reg); 6761 %} 6762 6763 6764 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6765 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6766 ins_cost(150); 6767 6768 size(4); 6769 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6770 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6771 ins_pipe(ialu_reg); 6772 %} 6773 6774 6775 6776 //----------OS and Locking Instructions---------------------------------------- 6777 6778 // This name is KNOWN by the ADLC and cannot be changed. 6779 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 6780 // for this guy. 6781 instruct tlsLoadP(g2RegP dst) %{ 6782 match(Set dst (ThreadLocal)); 6783 6784 size(0); 6785 ins_cost(0); 6786 format %{ "# TLS is in G2" %} 6787 ins_encode( /*empty encoding*/ ); 6788 ins_pipe(ialu_none); 6789 %} 6790 6791 instruct checkCastPP( iRegP dst ) %{ 6792 match(Set dst (CheckCastPP dst)); 6793 6794 size(0); 6795 format %{ "# checkcastPP of $dst" %} 6796 ins_encode( /*empty encoding*/ ); 6797 ins_pipe(empty); 6798 %} 6799 6800 6801 instruct castPP( iRegP dst ) %{ 6802 match(Set dst (CastPP dst)); 6803 format %{ "# castPP of $dst" %} 6804 ins_encode( /*empty encoding*/ ); 6805 ins_pipe(empty); 6806 %} 6807 6808 instruct castII( iRegI dst ) %{ 6809 match(Set dst (CastII dst)); 6810 format %{ "# castII of $dst" %} 6811 ins_encode( /*empty encoding*/ ); 6812 ins_cost(0); 6813 ins_pipe(empty); 6814 %} 6815 6816 //----------Arithmetic Instructions-------------------------------------------- 6817 // Addition Instructions 6818 // Register Addition 6819 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6820 match(Set dst (AddI src1 src2)); 6821 6822 size(4); 6823 format %{ "ADD $src1,$src2,$dst" %} 6824 ins_encode %{ 6825 __ add($src1$$Register, $src2$$Register, $dst$$Register); 6826 %} 6827 ins_pipe(ialu_reg_reg); 6828 %} 6829 6830 // Immediate Addition 6831 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6832 match(Set dst (AddI src1 src2)); 6833 6834 size(4); 6835 format %{ "ADD $src1,$src2,$dst" %} 6836 opcode(Assembler::add_op3, Assembler::arith_op); 6837 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6838 ins_pipe(ialu_reg_imm); 6839 %} 6840 6841 // Pointer Register Addition 6842 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 6843 match(Set dst (AddP src1 src2)); 6844 6845 size(4); 6846 format %{ "ADD $src1,$src2,$dst" %} 6847 opcode(Assembler::add_op3, Assembler::arith_op); 6848 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6849 ins_pipe(ialu_reg_reg); 6850 %} 6851 6852 // Pointer Immediate Addition 6853 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 6854 match(Set dst (AddP src1 src2)); 6855 6856 size(4); 6857 format %{ "ADD $src1,$src2,$dst" %} 6858 opcode(Assembler::add_op3, Assembler::arith_op); 6859 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6860 ins_pipe(ialu_reg_imm); 6861 %} 6862 6863 // Long Addition 6864 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6865 match(Set dst (AddL src1 src2)); 6866 6867 size(4); 6868 format %{ "ADD $src1,$src2,$dst\t! long" %} 6869 opcode(Assembler::add_op3, Assembler::arith_op); 6870 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6871 ins_pipe(ialu_reg_reg); 6872 %} 6873 6874 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 6875 match(Set dst (AddL src1 con)); 6876 6877 size(4); 6878 format %{ "ADD $src1,$con,$dst" %} 6879 opcode(Assembler::add_op3, Assembler::arith_op); 6880 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 6881 ins_pipe(ialu_reg_imm); 6882 %} 6883 6884 //----------Conditional_store-------------------------------------------------- 6885 // Conditional-store of the updated heap-top. 6886 // Used during allocation of the shared heap. 6887 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 6888 6889 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 6890 instruct loadPLocked(iRegP dst, memory mem) %{ 6891 match(Set dst (LoadPLocked mem)); 6892 ins_cost(MEMORY_REF_COST); 6893 6894 format %{ "LDX $mem,$dst\t! ptr" %} 6895 opcode(Assembler::ldx_op3, 0, REGP_OP); 6896 ins_encode( form3_mem_reg( mem, dst ) ); 6897 ins_pipe(iload_mem); 6898 %} 6899 6900 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 6901 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 6902 effect( KILL newval ); 6903 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 6904 "CMP R_G3,$oldval\t\t! See if we made progress" %} 6905 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 6906 ins_pipe( long_memory_op ); 6907 %} 6908 6909 // Conditional-store of an int value. 6910 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 6911 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 6912 effect( KILL newval ); 6913 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 6914 "CMP $oldval,$newval\t\t! See if we made progress" %} 6915 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 6916 ins_pipe( long_memory_op ); 6917 %} 6918 6919 // Conditional-store of a long value. 6920 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 6921 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 6922 effect( KILL newval ); 6923 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 6924 "CMP $oldval,$newval\t\t! See if we made progress" %} 6925 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 6926 ins_pipe( long_memory_op ); 6927 %} 6928 6929 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 6930 6931 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6932 predicate(VM_Version::supports_cx8()); 6933 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 6934 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval))); 6935 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6936 format %{ 6937 "MOV $newval,O7\n\t" 6938 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6939 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6940 "MOV 1,$res\n\t" 6941 "MOVne xcc,R_G0,$res" 6942 %} 6943 ins_encode( enc_casx(mem_ptr, oldval, newval), 6944 enc_lflags_ne_to_boolean(res) ); 6945 ins_pipe( long_memory_op ); 6946 %} 6947 6948 6949 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6950 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 6951 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval))); 6952 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6953 format %{ 6954 "MOV $newval,O7\n\t" 6955 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6956 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6957 "MOV 1,$res\n\t" 6958 "MOVne icc,R_G0,$res" 6959 %} 6960 ins_encode( enc_casi(mem_ptr, oldval, newval), 6961 enc_iflags_ne_to_boolean(res) ); 6962 ins_pipe( long_memory_op ); 6963 %} 6964 6965 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6966 predicate(VM_Version::supports_cx8()); 6967 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 6968 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); 6969 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6970 format %{ 6971 "MOV $newval,O7\n\t" 6972 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6973 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6974 "MOV 1,$res\n\t" 6975 "MOVne xcc,R_G0,$res" 6976 %} 6977 ins_encode( enc_casx(mem_ptr, oldval, newval), 6978 enc_lflags_ne_to_boolean(res) ); 6979 ins_pipe( long_memory_op ); 6980 %} 6981 6982 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6983 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 6984 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval))); 6985 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6986 format %{ 6987 "MOV $newval,O7\n\t" 6988 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6989 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6990 "MOV 1,$res\n\t" 6991 "MOVne icc,R_G0,$res" 6992 %} 6993 ins_encode( enc_casi(mem_ptr, oldval, newval), 6994 enc_iflags_ne_to_boolean(res) ); 6995 ins_pipe( long_memory_op ); 6996 %} 6997 6998 instruct compareAndExchangeI(iRegP mem_ptr, iRegI oldval, iRegI newval) 6999 %{ 7000 match(Set newval (CompareAndExchangeI mem_ptr (Binary oldval newval))); 7001 effect( USE mem_ptr ); 7002 7003 format %{ 7004 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 7005 %} 7006 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) ); 7007 ins_pipe( long_memory_op ); 7008 %} 7009 7010 instruct compareAndExchangeL(iRegP mem_ptr, iRegL oldval, iRegL newval) 7011 %{ 7012 match(Set newval (CompareAndExchangeL mem_ptr (Binary oldval newval))); 7013 effect( USE mem_ptr ); 7014 7015 format %{ 7016 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 7017 %} 7018 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) ); 7019 ins_pipe( long_memory_op ); 7020 %} 7021 7022 instruct compareAndExchangeP(iRegP mem_ptr, iRegP oldval, iRegP newval) 7023 %{ 7024 match(Set newval (CompareAndExchangeP mem_ptr (Binary oldval newval))); 7025 effect( USE mem_ptr ); 7026 7027 format %{ 7028 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 7029 %} 7030 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) ); 7031 ins_pipe( long_memory_op ); 7032 %} 7033 7034 instruct compareAndExchangeN(iRegP mem_ptr, iRegN oldval, iRegN newval) 7035 %{ 7036 match(Set newval (CompareAndExchangeN mem_ptr (Binary oldval newval))); 7037 effect( USE mem_ptr ); 7038 7039 format %{ 7040 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 7041 %} 7042 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) ); 7043 ins_pipe( long_memory_op ); 7044 %} 7045 7046 instruct xchgI( memory mem, iRegI newval) %{ 7047 match(Set newval (GetAndSetI mem newval)); 7048 format %{ "SWAP [$mem],$newval" %} 7049 size(4); 7050 ins_encode %{ 7051 __ swap($mem$$Address, $newval$$Register); 7052 %} 7053 ins_pipe( long_memory_op ); 7054 %} 7055 7056 7057 instruct xchgN( memory mem, iRegN newval) %{ 7058 match(Set newval (GetAndSetN mem newval)); 7059 format %{ "SWAP [$mem],$newval" %} 7060 size(4); 7061 ins_encode %{ 7062 __ swap($mem$$Address, $newval$$Register); 7063 %} 7064 ins_pipe( long_memory_op ); 7065 %} 7066 7067 //--------------------- 7068 // Subtraction Instructions 7069 // Register Subtraction 7070 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7071 match(Set dst (SubI src1 src2)); 7072 7073 size(4); 7074 format %{ "SUB $src1,$src2,$dst" %} 7075 opcode(Assembler::sub_op3, Assembler::arith_op); 7076 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7077 ins_pipe(ialu_reg_reg); 7078 %} 7079 7080 // Immediate Subtraction 7081 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7082 match(Set dst (SubI src1 src2)); 7083 7084 size(4); 7085 format %{ "SUB $src1,$src2,$dst" %} 7086 opcode(Assembler::sub_op3, Assembler::arith_op); 7087 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7088 ins_pipe(ialu_reg_imm); 7089 %} 7090 7091 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7092 match(Set dst (SubI zero src2)); 7093 7094 size(4); 7095 format %{ "NEG $src2,$dst" %} 7096 opcode(Assembler::sub_op3, Assembler::arith_op); 7097 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7098 ins_pipe(ialu_zero_reg); 7099 %} 7100 7101 // Long subtraction 7102 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7103 match(Set dst (SubL src1 src2)); 7104 7105 size(4); 7106 format %{ "SUB $src1,$src2,$dst\t! long" %} 7107 opcode(Assembler::sub_op3, Assembler::arith_op); 7108 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7109 ins_pipe(ialu_reg_reg); 7110 %} 7111 7112 // Immediate Subtraction 7113 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7114 match(Set dst (SubL src1 con)); 7115 7116 size(4); 7117 format %{ "SUB $src1,$con,$dst\t! long" %} 7118 opcode(Assembler::sub_op3, Assembler::arith_op); 7119 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7120 ins_pipe(ialu_reg_imm); 7121 %} 7122 7123 // Long negation 7124 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7125 match(Set dst (SubL zero src2)); 7126 7127 size(4); 7128 format %{ "NEG $src2,$dst\t! long" %} 7129 opcode(Assembler::sub_op3, Assembler::arith_op); 7130 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7131 ins_pipe(ialu_zero_reg); 7132 %} 7133 7134 // Multiplication Instructions 7135 // Integer Multiplication 7136 // Register Multiplication 7137 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7138 match(Set dst (MulI src1 src2)); 7139 7140 size(4); 7141 format %{ "MULX $src1,$src2,$dst" %} 7142 opcode(Assembler::mulx_op3, Assembler::arith_op); 7143 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7144 ins_pipe(imul_reg_reg); 7145 %} 7146 7147 // Immediate Multiplication 7148 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7149 match(Set dst (MulI src1 src2)); 7150 7151 size(4); 7152 format %{ "MULX $src1,$src2,$dst" %} 7153 opcode(Assembler::mulx_op3, Assembler::arith_op); 7154 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7155 ins_pipe(imul_reg_imm); 7156 %} 7157 7158 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7159 match(Set dst (MulL src1 src2)); 7160 ins_cost(DEFAULT_COST * 5); 7161 size(4); 7162 format %{ "MULX $src1,$src2,$dst\t! long" %} 7163 opcode(Assembler::mulx_op3, Assembler::arith_op); 7164 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7165 ins_pipe(mulL_reg_reg); 7166 %} 7167 7168 // Immediate Multiplication 7169 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7170 match(Set dst (MulL src1 src2)); 7171 ins_cost(DEFAULT_COST * 5); 7172 size(4); 7173 format %{ "MULX $src1,$src2,$dst" %} 7174 opcode(Assembler::mulx_op3, Assembler::arith_op); 7175 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7176 ins_pipe(mulL_reg_imm); 7177 %} 7178 7179 // Integer Division 7180 // Register Division 7181 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7182 match(Set dst (DivI src1 src2)); 7183 ins_cost((2+71)*DEFAULT_COST); 7184 7185 format %{ "SRA $src2,0,$src2\n\t" 7186 "SRA $src1,0,$src1\n\t" 7187 "SDIVX $src1,$src2,$dst" %} 7188 ins_encode( idiv_reg( src1, src2, dst ) ); 7189 ins_pipe(sdiv_reg_reg); 7190 %} 7191 7192 // Immediate Division 7193 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7194 match(Set dst (DivI src1 src2)); 7195 ins_cost((2+71)*DEFAULT_COST); 7196 7197 format %{ "SRA $src1,0,$src1\n\t" 7198 "SDIVX $src1,$src2,$dst" %} 7199 ins_encode( idiv_imm( src1, src2, dst ) ); 7200 ins_pipe(sdiv_reg_imm); 7201 %} 7202 7203 //----------Div-By-10-Expansion------------------------------------------------ 7204 // Extract hi bits of a 32x32->64 bit multiply. 7205 // Expand rule only, not matched 7206 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7207 effect( DEF dst, USE src1, USE src2 ); 7208 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7209 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7210 ins_encode( enc_mul_hi(dst,src1,src2)); 7211 ins_pipe(sdiv_reg_reg); 7212 %} 7213 7214 // Magic constant, reciprocal of 10 7215 instruct loadConI_x66666667(iRegIsafe dst) %{ 7216 effect( DEF dst ); 7217 7218 size(8); 7219 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7220 ins_encode( Set32(0x66666667, dst) ); 7221 ins_pipe(ialu_hi_lo_reg); 7222 %} 7223 7224 // Register Shift Right Arithmetic Long by 32-63 7225 instruct sra_31( iRegI dst, iRegI src ) %{ 7226 effect( DEF dst, USE src ); 7227 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7228 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7229 ins_pipe(ialu_reg_reg); 7230 %} 7231 7232 // Arithmetic Shift Right by 8-bit immediate 7233 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7234 effect( DEF dst, USE src ); 7235 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7236 opcode(Assembler::sra_op3, Assembler::arith_op); 7237 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7238 ins_pipe(ialu_reg_imm); 7239 %} 7240 7241 // Integer DIV with 10 7242 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7243 match(Set dst (DivI src div)); 7244 ins_cost((6+6)*DEFAULT_COST); 7245 expand %{ 7246 iRegIsafe tmp1; // Killed temps; 7247 iRegIsafe tmp2; // Killed temps; 7248 iRegI tmp3; // Killed temps; 7249 iRegI tmp4; // Killed temps; 7250 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7251 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7252 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7253 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7254 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7255 %} 7256 %} 7257 7258 // Register Long Division 7259 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7260 match(Set dst (DivL src1 src2)); 7261 ins_cost(DEFAULT_COST*71); 7262 size(4); 7263 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7264 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7265 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7266 ins_pipe(divL_reg_reg); 7267 %} 7268 7269 // Register Long Division 7270 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7271 match(Set dst (DivL src1 src2)); 7272 ins_cost(DEFAULT_COST*71); 7273 size(4); 7274 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7275 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7276 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7277 ins_pipe(divL_reg_imm); 7278 %} 7279 7280 // Integer Remainder 7281 // Register Remainder 7282 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7283 match(Set dst (ModI src1 src2)); 7284 effect( KILL ccr, KILL temp); 7285 7286 format %{ "SREM $src1,$src2,$dst" %} 7287 ins_encode( irem_reg(src1, src2, dst, temp) ); 7288 ins_pipe(sdiv_reg_reg); 7289 %} 7290 7291 // Immediate Remainder 7292 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7293 match(Set dst (ModI src1 src2)); 7294 effect( KILL ccr, KILL temp); 7295 7296 format %{ "SREM $src1,$src2,$dst" %} 7297 ins_encode( irem_imm(src1, src2, dst, temp) ); 7298 ins_pipe(sdiv_reg_imm); 7299 %} 7300 7301 // Register Long Remainder 7302 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7303 effect(DEF dst, USE src1, USE src2); 7304 size(4); 7305 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7306 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7307 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7308 ins_pipe(divL_reg_reg); 7309 %} 7310 7311 // Register Long Division 7312 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7313 effect(DEF dst, USE src1, USE src2); 7314 size(4); 7315 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7316 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7317 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7318 ins_pipe(divL_reg_imm); 7319 %} 7320 7321 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7322 effect(DEF dst, USE src1, USE src2); 7323 size(4); 7324 format %{ "MULX $src1,$src2,$dst\t! long" %} 7325 opcode(Assembler::mulx_op3, Assembler::arith_op); 7326 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7327 ins_pipe(mulL_reg_reg); 7328 %} 7329 7330 // Immediate Multiplication 7331 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7332 effect(DEF dst, USE src1, USE src2); 7333 size(4); 7334 format %{ "MULX $src1,$src2,$dst" %} 7335 opcode(Assembler::mulx_op3, Assembler::arith_op); 7336 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7337 ins_pipe(mulL_reg_imm); 7338 %} 7339 7340 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7341 effect(DEF dst, USE src1, USE src2); 7342 size(4); 7343 format %{ "SUB $src1,$src2,$dst\t! long" %} 7344 opcode(Assembler::sub_op3, Assembler::arith_op); 7345 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7346 ins_pipe(ialu_reg_reg); 7347 %} 7348 7349 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7350 effect(DEF dst, USE src1, USE src2); 7351 size(4); 7352 format %{ "SUB $src1,$src2,$dst\t! long" %} 7353 opcode(Assembler::sub_op3, Assembler::arith_op); 7354 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7355 ins_pipe(ialu_reg_reg); 7356 %} 7357 7358 // Register Long Remainder 7359 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7360 match(Set dst (ModL src1 src2)); 7361 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7362 expand %{ 7363 iRegL tmp1; 7364 iRegL tmp2; 7365 divL_reg_reg_1(tmp1, src1, src2); 7366 mulL_reg_reg_1(tmp2, tmp1, src2); 7367 subL_reg_reg_1(dst, src1, tmp2); 7368 %} 7369 %} 7370 7371 // Register Long Remainder 7372 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7373 match(Set dst (ModL src1 src2)); 7374 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7375 expand %{ 7376 iRegL tmp1; 7377 iRegL tmp2; 7378 divL_reg_imm13_1(tmp1, src1, src2); 7379 mulL_reg_imm13_1(tmp2, tmp1, src2); 7380 subL_reg_reg_2 (dst, src1, tmp2); 7381 %} 7382 %} 7383 7384 // Integer Shift Instructions 7385 // Register Shift Left 7386 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7387 match(Set dst (LShiftI src1 src2)); 7388 7389 size(4); 7390 format %{ "SLL $src1,$src2,$dst" %} 7391 opcode(Assembler::sll_op3, Assembler::arith_op); 7392 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7393 ins_pipe(ialu_reg_reg); 7394 %} 7395 7396 // Register Shift Left Immediate 7397 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7398 match(Set dst (LShiftI src1 src2)); 7399 7400 size(4); 7401 format %{ "SLL $src1,$src2,$dst" %} 7402 opcode(Assembler::sll_op3, Assembler::arith_op); 7403 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7404 ins_pipe(ialu_reg_imm); 7405 %} 7406 7407 // Register Shift Left 7408 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7409 match(Set dst (LShiftL src1 src2)); 7410 7411 size(4); 7412 format %{ "SLLX $src1,$src2,$dst" %} 7413 opcode(Assembler::sllx_op3, Assembler::arith_op); 7414 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7415 ins_pipe(ialu_reg_reg); 7416 %} 7417 7418 // Register Shift Left Immediate 7419 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7420 match(Set dst (LShiftL src1 src2)); 7421 7422 size(4); 7423 format %{ "SLLX $src1,$src2,$dst" %} 7424 opcode(Assembler::sllx_op3, Assembler::arith_op); 7425 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7426 ins_pipe(ialu_reg_imm); 7427 %} 7428 7429 // Register Arithmetic Shift Right 7430 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7431 match(Set dst (RShiftI src1 src2)); 7432 size(4); 7433 format %{ "SRA $src1,$src2,$dst" %} 7434 opcode(Assembler::sra_op3, Assembler::arith_op); 7435 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7436 ins_pipe(ialu_reg_reg); 7437 %} 7438 7439 // Register Arithmetic Shift Right Immediate 7440 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7441 match(Set dst (RShiftI src1 src2)); 7442 7443 size(4); 7444 format %{ "SRA $src1,$src2,$dst" %} 7445 opcode(Assembler::sra_op3, Assembler::arith_op); 7446 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7447 ins_pipe(ialu_reg_imm); 7448 %} 7449 7450 // Register Shift Right Arithmatic Long 7451 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7452 match(Set dst (RShiftL src1 src2)); 7453 7454 size(4); 7455 format %{ "SRAX $src1,$src2,$dst" %} 7456 opcode(Assembler::srax_op3, Assembler::arith_op); 7457 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7458 ins_pipe(ialu_reg_reg); 7459 %} 7460 7461 // Register Shift Left Immediate 7462 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7463 match(Set dst (RShiftL src1 src2)); 7464 7465 size(4); 7466 format %{ "SRAX $src1,$src2,$dst" %} 7467 opcode(Assembler::srax_op3, Assembler::arith_op); 7468 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7469 ins_pipe(ialu_reg_imm); 7470 %} 7471 7472 // Register Shift Right 7473 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7474 match(Set dst (URShiftI src1 src2)); 7475 7476 size(4); 7477 format %{ "SRL $src1,$src2,$dst" %} 7478 opcode(Assembler::srl_op3, Assembler::arith_op); 7479 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7480 ins_pipe(ialu_reg_reg); 7481 %} 7482 7483 // Register Shift Right Immediate 7484 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7485 match(Set dst (URShiftI src1 src2)); 7486 7487 size(4); 7488 format %{ "SRL $src1,$src2,$dst" %} 7489 opcode(Assembler::srl_op3, Assembler::arith_op); 7490 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7491 ins_pipe(ialu_reg_imm); 7492 %} 7493 7494 // Register Shift Right 7495 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7496 match(Set dst (URShiftL src1 src2)); 7497 7498 size(4); 7499 format %{ "SRLX $src1,$src2,$dst" %} 7500 opcode(Assembler::srlx_op3, Assembler::arith_op); 7501 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7502 ins_pipe(ialu_reg_reg); 7503 %} 7504 7505 // Register Shift Right Immediate 7506 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7507 match(Set dst (URShiftL src1 src2)); 7508 7509 size(4); 7510 format %{ "SRLX $src1,$src2,$dst" %} 7511 opcode(Assembler::srlx_op3, Assembler::arith_op); 7512 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7513 ins_pipe(ialu_reg_imm); 7514 %} 7515 7516 // Register Shift Right Immediate with a CastP2X 7517 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7518 match(Set dst (URShiftL (CastP2X src1) src2)); 7519 size(4); 7520 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7521 opcode(Assembler::srlx_op3, Assembler::arith_op); 7522 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7523 ins_pipe(ialu_reg_imm); 7524 %} 7525 7526 7527 //----------Floating Point Arithmetic Instructions----------------------------- 7528 7529 // Add float single precision 7530 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7531 match(Set dst (AddF src1 src2)); 7532 7533 size(4); 7534 format %{ "FADDS $src1,$src2,$dst" %} 7535 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7536 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7537 ins_pipe(faddF_reg_reg); 7538 %} 7539 7540 // Add float double precision 7541 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7542 match(Set dst (AddD src1 src2)); 7543 7544 size(4); 7545 format %{ "FADDD $src1,$src2,$dst" %} 7546 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7547 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7548 ins_pipe(faddD_reg_reg); 7549 %} 7550 7551 // Sub float single precision 7552 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7553 match(Set dst (SubF src1 src2)); 7554 7555 size(4); 7556 format %{ "FSUBS $src1,$src2,$dst" %} 7557 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7558 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7559 ins_pipe(faddF_reg_reg); 7560 %} 7561 7562 // Sub float double precision 7563 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7564 match(Set dst (SubD src1 src2)); 7565 7566 size(4); 7567 format %{ "FSUBD $src1,$src2,$dst" %} 7568 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7569 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7570 ins_pipe(faddD_reg_reg); 7571 %} 7572 7573 // Mul float single precision 7574 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7575 match(Set dst (MulF src1 src2)); 7576 7577 size(4); 7578 format %{ "FMULS $src1,$src2,$dst" %} 7579 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7580 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7581 ins_pipe(fmulF_reg_reg); 7582 %} 7583 7584 // Mul float double precision 7585 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7586 match(Set dst (MulD src1 src2)); 7587 7588 size(4); 7589 format %{ "FMULD $src1,$src2,$dst" %} 7590 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7591 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7592 ins_pipe(fmulD_reg_reg); 7593 %} 7594 7595 // Div float single precision 7596 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7597 match(Set dst (DivF src1 src2)); 7598 7599 size(4); 7600 format %{ "FDIVS $src1,$src2,$dst" %} 7601 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7602 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7603 ins_pipe(fdivF_reg_reg); 7604 %} 7605 7606 // Div float double precision 7607 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7608 match(Set dst (DivD src1 src2)); 7609 7610 size(4); 7611 format %{ "FDIVD $src1,$src2,$dst" %} 7612 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7613 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7614 ins_pipe(fdivD_reg_reg); 7615 %} 7616 7617 // Absolute float double precision 7618 instruct absD_reg(regD dst, regD src) %{ 7619 match(Set dst (AbsD src)); 7620 7621 format %{ "FABSd $src,$dst" %} 7622 ins_encode(fabsd(dst, src)); 7623 ins_pipe(faddD_reg); 7624 %} 7625 7626 // Absolute float single precision 7627 instruct absF_reg(regF dst, regF src) %{ 7628 match(Set dst (AbsF src)); 7629 7630 format %{ "FABSs $src,$dst" %} 7631 ins_encode(fabss(dst, src)); 7632 ins_pipe(faddF_reg); 7633 %} 7634 7635 instruct negF_reg(regF dst, regF src) %{ 7636 match(Set dst (NegF src)); 7637 7638 size(4); 7639 format %{ "FNEGs $src,$dst" %} 7640 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7641 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7642 ins_pipe(faddF_reg); 7643 %} 7644 7645 instruct negD_reg(regD dst, regD src) %{ 7646 match(Set dst (NegD src)); 7647 7648 format %{ "FNEGd $src,$dst" %} 7649 ins_encode(fnegd(dst, src)); 7650 ins_pipe(faddD_reg); 7651 %} 7652 7653 // Sqrt float double precision 7654 instruct sqrtF_reg_reg(regF dst, regF src) %{ 7655 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7656 7657 size(4); 7658 format %{ "FSQRTS $src,$dst" %} 7659 ins_encode(fsqrts(dst, src)); 7660 ins_pipe(fdivF_reg_reg); 7661 %} 7662 7663 // Sqrt float double precision 7664 instruct sqrtD_reg_reg(regD dst, regD src) %{ 7665 match(Set dst (SqrtD src)); 7666 7667 size(4); 7668 format %{ "FSQRTD $src,$dst" %} 7669 ins_encode(fsqrtd(dst, src)); 7670 ins_pipe(fdivD_reg_reg); 7671 %} 7672 7673 // Single/Double precision fused floating-point multiply-add (d = a * b + c). 7674 instruct fmaF_regx4(regF dst, regF a, regF b, regF c) %{ 7675 predicate(UseFMA); 7676 match(Set dst (FmaF c (Binary a b))); 7677 format %{ "fmadds $a,$b,$c,$dst\t# $dst = $a * $b + $c" %} 7678 ins_encode(fmadds(dst, a, b, c)); 7679 ins_pipe(fmaF_regx4); 7680 %} 7681 7682 instruct fmaD_regx4(regD dst, regD a, regD b, regD c) %{ 7683 predicate(UseFMA); 7684 match(Set dst (FmaD c (Binary a b))); 7685 format %{ "fmaddd $a,$b,$c,$dst\t# $dst = $a * $b + $c" %} 7686 ins_encode(fmaddd(dst, a, b, c)); 7687 ins_pipe(fmaD_regx4); 7688 %} 7689 7690 // Additional patterns matching complement versions that we can map directly to 7691 // variants of the fused multiply-add instructions. 7692 7693 // Single/Double precision fused floating-point multiply-sub (d = a * b - c) 7694 instruct fmsubF_regx4(regF dst, regF a, regF b, regF c) %{ 7695 predicate(UseFMA); 7696 match(Set dst (FmaF (NegF c) (Binary a b))); 7697 format %{ "fmsubs $a,$b,$c,$dst\t# $dst = $a * $b - $c" %} 7698 ins_encode(fmsubs(dst, a, b, c)); 7699 ins_pipe(fmaF_regx4); 7700 %} 7701 7702 instruct fmsubD_regx4(regD dst, regD a, regD b, regD c) %{ 7703 predicate(UseFMA); 7704 match(Set dst (FmaD (NegD c) (Binary a b))); 7705 format %{ "fmsubd $a,$b,$c,$dst\t# $dst = $a * $b - $c" %} 7706 ins_encode(fmsubd(dst, a, b, c)); 7707 ins_pipe(fmaD_regx4); 7708 %} 7709 7710 // Single/Double precision fused floating-point neg. multiply-add, 7711 // d = -1 * a * b - c = -(a * b + c) 7712 instruct fnmaddF_regx4(regF dst, regF a, regF b, regF c) %{ 7713 predicate(UseFMA); 7714 match(Set dst (FmaF (NegF c) (Binary (NegF a) b))); 7715 match(Set dst (FmaF (NegF c) (Binary a (NegF b)))); 7716 format %{ "fnmadds $a,$b,$c,$dst\t# $dst = -($a * $b + $c)" %} 7717 ins_encode(fnmadds(dst, a, b, c)); 7718 ins_pipe(fmaF_regx4); 7719 %} 7720 7721 instruct fnmaddD_regx4(regD dst, regD a, regD b, regD c) %{ 7722 predicate(UseFMA); 7723 match(Set dst (FmaD (NegD c) (Binary (NegD a) b))); 7724 match(Set dst (FmaD (NegD c) (Binary a (NegD b)))); 7725 format %{ "fnmaddd $a,$b,$c,$dst\t# $dst = -($a * $b + $c)" %} 7726 ins_encode(fnmaddd(dst, a, b, c)); 7727 ins_pipe(fmaD_regx4); 7728 %} 7729 7730 // Single/Double precision fused floating-point neg. multiply-sub, 7731 // d = -1 * a * b + c = -(a * b - c) 7732 instruct fnmsubF_regx4(regF dst, regF a, regF b, regF c) %{ 7733 predicate(UseFMA); 7734 match(Set dst (FmaF c (Binary (NegF a) b))); 7735 match(Set dst (FmaF c (Binary a (NegF b)))); 7736 format %{ "fnmsubs $a,$b,$c,$dst\t# $dst = -($a * $b - $c)" %} 7737 ins_encode(fnmsubs(dst, a, b, c)); 7738 ins_pipe(fmaF_regx4); 7739 %} 7740 7741 instruct fnmsubD_regx4(regD dst, regD a, regD b, regD c) %{ 7742 predicate(UseFMA); 7743 match(Set dst (FmaD c (Binary (NegD a) b))); 7744 match(Set dst (FmaD c (Binary a (NegD b)))); 7745 format %{ "fnmsubd $a,$b,$c,$dst\t# $dst = -($a * $b - $c)" %} 7746 ins_encode(fnmsubd(dst, a, b, c)); 7747 ins_pipe(fmaD_regx4); 7748 %} 7749 7750 //----------Logical Instructions----------------------------------------------- 7751 // And Instructions 7752 // Register And 7753 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7754 match(Set dst (AndI src1 src2)); 7755 7756 size(4); 7757 format %{ "AND $src1,$src2,$dst" %} 7758 opcode(Assembler::and_op3, Assembler::arith_op); 7759 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7760 ins_pipe(ialu_reg_reg); 7761 %} 7762 7763 // Immediate And 7764 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7765 match(Set dst (AndI src1 src2)); 7766 7767 size(4); 7768 format %{ "AND $src1,$src2,$dst" %} 7769 opcode(Assembler::and_op3, Assembler::arith_op); 7770 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7771 ins_pipe(ialu_reg_imm); 7772 %} 7773 7774 // Register And Long 7775 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7776 match(Set dst (AndL src1 src2)); 7777 7778 ins_cost(DEFAULT_COST); 7779 size(4); 7780 format %{ "AND $src1,$src2,$dst\t! long" %} 7781 opcode(Assembler::and_op3, Assembler::arith_op); 7782 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7783 ins_pipe(ialu_reg_reg); 7784 %} 7785 7786 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7787 match(Set dst (AndL src1 con)); 7788 7789 ins_cost(DEFAULT_COST); 7790 size(4); 7791 format %{ "AND $src1,$con,$dst\t! long" %} 7792 opcode(Assembler::and_op3, Assembler::arith_op); 7793 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7794 ins_pipe(ialu_reg_imm); 7795 %} 7796 7797 // Or Instructions 7798 // Register Or 7799 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7800 match(Set dst (OrI src1 src2)); 7801 7802 size(4); 7803 format %{ "OR $src1,$src2,$dst" %} 7804 opcode(Assembler::or_op3, Assembler::arith_op); 7805 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7806 ins_pipe(ialu_reg_reg); 7807 %} 7808 7809 // Immediate Or 7810 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7811 match(Set dst (OrI src1 src2)); 7812 7813 size(4); 7814 format %{ "OR $src1,$src2,$dst" %} 7815 opcode(Assembler::or_op3, Assembler::arith_op); 7816 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7817 ins_pipe(ialu_reg_imm); 7818 %} 7819 7820 // Register Or Long 7821 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7822 match(Set dst (OrL src1 src2)); 7823 7824 ins_cost(DEFAULT_COST); 7825 size(4); 7826 format %{ "OR $src1,$src2,$dst\t! long" %} 7827 opcode(Assembler::or_op3, Assembler::arith_op); 7828 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7829 ins_pipe(ialu_reg_reg); 7830 %} 7831 7832 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7833 match(Set dst (OrL src1 con)); 7834 ins_cost(DEFAULT_COST*2); 7835 7836 ins_cost(DEFAULT_COST); 7837 size(4); 7838 format %{ "OR $src1,$con,$dst\t! long" %} 7839 opcode(Assembler::or_op3, Assembler::arith_op); 7840 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7841 ins_pipe(ialu_reg_imm); 7842 %} 7843 7844 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 7845 match(Set dst (OrL src1 (CastP2X src2))); 7846 7847 ins_cost(DEFAULT_COST); 7848 size(4); 7849 format %{ "OR $src1,$src2,$dst\t! long" %} 7850 opcode(Assembler::or_op3, Assembler::arith_op); 7851 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7852 ins_pipe(ialu_reg_reg); 7853 %} 7854 7855 // Xor Instructions 7856 // Register Xor 7857 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7858 match(Set dst (XorI src1 src2)); 7859 7860 size(4); 7861 format %{ "XOR $src1,$src2,$dst" %} 7862 opcode(Assembler::xor_op3, Assembler::arith_op); 7863 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7864 ins_pipe(ialu_reg_reg); 7865 %} 7866 7867 // Immediate Xor 7868 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7869 match(Set dst (XorI src1 src2)); 7870 7871 size(4); 7872 format %{ "XOR $src1,$src2,$dst" %} 7873 opcode(Assembler::xor_op3, Assembler::arith_op); 7874 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7875 ins_pipe(ialu_reg_imm); 7876 %} 7877 7878 // Register Xor Long 7879 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7880 match(Set dst (XorL src1 src2)); 7881 7882 ins_cost(DEFAULT_COST); 7883 size(4); 7884 format %{ "XOR $src1,$src2,$dst\t! long" %} 7885 opcode(Assembler::xor_op3, Assembler::arith_op); 7886 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7887 ins_pipe(ialu_reg_reg); 7888 %} 7889 7890 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7891 match(Set dst (XorL src1 con)); 7892 7893 ins_cost(DEFAULT_COST); 7894 size(4); 7895 format %{ "XOR $src1,$con,$dst\t! long" %} 7896 opcode(Assembler::xor_op3, Assembler::arith_op); 7897 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7898 ins_pipe(ialu_reg_imm); 7899 %} 7900 7901 //----------Convert to Boolean------------------------------------------------- 7902 // Nice hack for 32-bit tests but doesn't work for 7903 // 64-bit pointers. 7904 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 7905 match(Set dst (Conv2B src)); 7906 effect( KILL ccr ); 7907 ins_cost(DEFAULT_COST*2); 7908 format %{ "CMP R_G0,$src\n\t" 7909 "ADDX R_G0,0,$dst" %} 7910 ins_encode( enc_to_bool( src, dst ) ); 7911 ins_pipe(ialu_reg_ialu); 7912 %} 7913 7914 instruct convP2B( iRegI dst, iRegP src ) %{ 7915 match(Set dst (Conv2B src)); 7916 ins_cost(DEFAULT_COST*2); 7917 format %{ "MOV $src,$dst\n\t" 7918 "MOVRNZ $src,1,$dst" %} 7919 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 7920 ins_pipe(ialu_clr_and_mover); 7921 %} 7922 7923 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ 7924 match(Set dst (CmpLTMask src zero)); 7925 effect(KILL ccr); 7926 size(4); 7927 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} 7928 ins_encode %{ 7929 __ sra($src$$Register, 31, $dst$$Register); 7930 %} 7931 ins_pipe(ialu_reg_imm); 7932 %} 7933 7934 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 7935 match(Set dst (CmpLTMask p q)); 7936 effect( KILL ccr ); 7937 ins_cost(DEFAULT_COST*4); 7938 format %{ "CMP $p,$q\n\t" 7939 "MOV #0,$dst\n\t" 7940 "BLT,a .+8\n\t" 7941 "MOV #-1,$dst" %} 7942 ins_encode( enc_ltmask(p,q,dst) ); 7943 ins_pipe(ialu_reg_reg_ialu); 7944 %} 7945 7946 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 7947 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 7948 effect(KILL ccr, TEMP tmp); 7949 ins_cost(DEFAULT_COST*3); 7950 7951 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 7952 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 7953 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} 7954 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); 7955 ins_pipe(cadd_cmpltmask); 7956 %} 7957 7958 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ 7959 match(Set p (AndI (CmpLTMask p q) y)); 7960 effect(KILL ccr); 7961 ins_cost(DEFAULT_COST*3); 7962 7963 format %{ "CMP $p,$q\n\t" 7964 "MOV $y,$p\n\t" 7965 "MOVge G0,$p" %} 7966 ins_encode %{ 7967 __ cmp($p$$Register, $q$$Register); 7968 __ mov($y$$Register, $p$$Register); 7969 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); 7970 %} 7971 ins_pipe(ialu_reg_reg_ialu); 7972 %} 7973 7974 //----------------------------------------------------------------- 7975 // Direct raw moves between float and general registers using VIS3. 7976 7977 // ins_pipe(faddF_reg); 7978 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ 7979 predicate(UseVIS >= 3); 7980 match(Set dst (MoveF2I src)); 7981 7982 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} 7983 ins_encode %{ 7984 __ movstouw($src$$FloatRegister, $dst$$Register); 7985 %} 7986 ins_pipe(ialu_reg_reg); 7987 %} 7988 7989 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ 7990 predicate(UseVIS >= 3); 7991 match(Set dst (MoveI2F src)); 7992 7993 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} 7994 ins_encode %{ 7995 __ movwtos($src$$Register, $dst$$FloatRegister); 7996 %} 7997 ins_pipe(ialu_reg_reg); 7998 %} 7999 8000 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ 8001 predicate(UseVIS >= 3); 8002 match(Set dst (MoveD2L src)); 8003 8004 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} 8005 ins_encode %{ 8006 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); 8007 %} 8008 ins_pipe(ialu_reg_reg); 8009 %} 8010 8011 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ 8012 predicate(UseVIS >= 3); 8013 match(Set dst (MoveL2D src)); 8014 8015 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} 8016 ins_encode %{ 8017 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); 8018 %} 8019 ins_pipe(ialu_reg_reg); 8020 %} 8021 8022 8023 // Raw moves between float and general registers using stack. 8024 8025 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8026 match(Set dst (MoveF2I src)); 8027 effect(DEF dst, USE src); 8028 ins_cost(MEMORY_REF_COST); 8029 8030 format %{ "LDUW $src,$dst\t! MoveF2I" %} 8031 opcode(Assembler::lduw_op3); 8032 ins_encode(simple_form3_mem_reg( src, dst ) ); 8033 ins_pipe(iload_mem); 8034 %} 8035 8036 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8037 match(Set dst (MoveI2F src)); 8038 effect(DEF dst, USE src); 8039 ins_cost(MEMORY_REF_COST); 8040 8041 format %{ "LDF $src,$dst\t! MoveI2F" %} 8042 opcode(Assembler::ldf_op3); 8043 ins_encode(simple_form3_mem_reg(src, dst)); 8044 ins_pipe(floadF_stk); 8045 %} 8046 8047 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8048 match(Set dst (MoveD2L src)); 8049 effect(DEF dst, USE src); 8050 ins_cost(MEMORY_REF_COST); 8051 8052 format %{ "LDX $src,$dst\t! MoveD2L" %} 8053 opcode(Assembler::ldx_op3); 8054 ins_encode(simple_form3_mem_reg( src, dst ) ); 8055 ins_pipe(iload_mem); 8056 %} 8057 8058 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8059 match(Set dst (MoveL2D src)); 8060 effect(DEF dst, USE src); 8061 ins_cost(MEMORY_REF_COST); 8062 8063 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8064 opcode(Assembler::lddf_op3); 8065 ins_encode(simple_form3_mem_reg(src, dst)); 8066 ins_pipe(floadD_stk); 8067 %} 8068 8069 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8070 match(Set dst (MoveF2I src)); 8071 effect(DEF dst, USE src); 8072 ins_cost(MEMORY_REF_COST); 8073 8074 format %{ "STF $src,$dst\t! MoveF2I" %} 8075 opcode(Assembler::stf_op3); 8076 ins_encode(simple_form3_mem_reg(dst, src)); 8077 ins_pipe(fstoreF_stk_reg); 8078 %} 8079 8080 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8081 match(Set dst (MoveI2F src)); 8082 effect(DEF dst, USE src); 8083 ins_cost(MEMORY_REF_COST); 8084 8085 format %{ "STW $src,$dst\t! MoveI2F" %} 8086 opcode(Assembler::stw_op3); 8087 ins_encode(simple_form3_mem_reg( dst, src ) ); 8088 ins_pipe(istore_mem_reg); 8089 %} 8090 8091 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8092 match(Set dst (MoveD2L src)); 8093 effect(DEF dst, USE src); 8094 ins_cost(MEMORY_REF_COST); 8095 8096 format %{ "STDF $src,$dst\t! MoveD2L" %} 8097 opcode(Assembler::stdf_op3); 8098 ins_encode(simple_form3_mem_reg(dst, src)); 8099 ins_pipe(fstoreD_stk_reg); 8100 %} 8101 8102 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8103 match(Set dst (MoveL2D src)); 8104 effect(DEF dst, USE src); 8105 ins_cost(MEMORY_REF_COST); 8106 8107 format %{ "STX $src,$dst\t! MoveL2D" %} 8108 opcode(Assembler::stx_op3); 8109 ins_encode(simple_form3_mem_reg( dst, src ) ); 8110 ins_pipe(istore_mem_reg); 8111 %} 8112 8113 8114 //----------Arithmetic Conversion Instructions--------------------------------- 8115 // The conversions operations are all Alpha sorted. Please keep it that way! 8116 8117 instruct convD2F_reg(regF dst, regD src) %{ 8118 match(Set dst (ConvD2F src)); 8119 size(4); 8120 format %{ "FDTOS $src,$dst" %} 8121 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 8122 ins_encode(form3_opf_rs2D_rdF(src, dst)); 8123 ins_pipe(fcvtD2F); 8124 %} 8125 8126 8127 // Convert a double to an int in a float register. 8128 // If the double is a NAN, stuff a zero in instead. 8129 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 8130 effect(DEF dst, USE src, KILL fcc0); 8131 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8132 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8133 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8134 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8135 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8136 "skip:" %} 8137 ins_encode(form_d2i_helper(src,dst)); 8138 ins_pipe(fcvtD2I); 8139 %} 8140 8141 instruct convD2I_stk(stackSlotI dst, regD src) %{ 8142 match(Set dst (ConvD2I src)); 8143 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8144 expand %{ 8145 regF tmp; 8146 convD2I_helper(tmp, src); 8147 regF_to_stkI(dst, tmp); 8148 %} 8149 %} 8150 8151 instruct convD2I_reg(iRegI dst, regD src) %{ 8152 predicate(UseVIS >= 3); 8153 match(Set dst (ConvD2I src)); 8154 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8155 expand %{ 8156 regF tmp; 8157 convD2I_helper(tmp, src); 8158 MoveF2I_reg_reg(dst, tmp); 8159 %} 8160 %} 8161 8162 8163 // Convert a double to a long in a double register. 8164 // If the double is a NAN, stuff a zero in instead. 8165 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8166 effect(DEF dst, USE src, KILL fcc0); 8167 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8168 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8169 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8170 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8171 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8172 "skip:" %} 8173 ins_encode(form_d2l_helper(src,dst)); 8174 ins_pipe(fcvtD2L); 8175 %} 8176 8177 instruct convD2L_stk(stackSlotL dst, regD src) %{ 8178 match(Set dst (ConvD2L src)); 8179 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8180 expand %{ 8181 regD tmp; 8182 convD2L_helper(tmp, src); 8183 regD_to_stkL(dst, tmp); 8184 %} 8185 %} 8186 8187 instruct convD2L_reg(iRegL dst, regD src) %{ 8188 predicate(UseVIS >= 3); 8189 match(Set dst (ConvD2L src)); 8190 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8191 expand %{ 8192 regD tmp; 8193 convD2L_helper(tmp, src); 8194 MoveD2L_reg_reg(dst, tmp); 8195 %} 8196 %} 8197 8198 8199 instruct convF2D_reg(regD dst, regF src) %{ 8200 match(Set dst (ConvF2D src)); 8201 format %{ "FSTOD $src,$dst" %} 8202 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8203 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8204 ins_pipe(fcvtF2D); 8205 %} 8206 8207 8208 // Convert a float to an int in a float register. 8209 // If the float is a NAN, stuff a zero in instead. 8210 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8211 effect(DEF dst, USE src, KILL fcc0); 8212 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8213 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8214 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8215 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8216 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8217 "skip:" %} 8218 ins_encode(form_f2i_helper(src,dst)); 8219 ins_pipe(fcvtF2I); 8220 %} 8221 8222 instruct convF2I_stk(stackSlotI dst, regF src) %{ 8223 match(Set dst (ConvF2I src)); 8224 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8225 expand %{ 8226 regF tmp; 8227 convF2I_helper(tmp, src); 8228 regF_to_stkI(dst, tmp); 8229 %} 8230 %} 8231 8232 instruct convF2I_reg(iRegI dst, regF src) %{ 8233 predicate(UseVIS >= 3); 8234 match(Set dst (ConvF2I src)); 8235 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8236 expand %{ 8237 regF tmp; 8238 convF2I_helper(tmp, src); 8239 MoveF2I_reg_reg(dst, tmp); 8240 %} 8241 %} 8242 8243 8244 // Convert a float to a long in a float register. 8245 // If the float is a NAN, stuff a zero in instead. 8246 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8247 effect(DEF dst, USE src, KILL fcc0); 8248 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8249 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8250 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8251 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8252 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8253 "skip:" %} 8254 ins_encode(form_f2l_helper(src,dst)); 8255 ins_pipe(fcvtF2L); 8256 %} 8257 8258 instruct convF2L_stk(stackSlotL dst, regF src) %{ 8259 match(Set dst (ConvF2L src)); 8260 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8261 expand %{ 8262 regD tmp; 8263 convF2L_helper(tmp, src); 8264 regD_to_stkL(dst, tmp); 8265 %} 8266 %} 8267 8268 instruct convF2L_reg(iRegL dst, regF src) %{ 8269 predicate(UseVIS >= 3); 8270 match(Set dst (ConvF2L src)); 8271 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8272 expand %{ 8273 regD tmp; 8274 convF2L_helper(tmp, src); 8275 MoveD2L_reg_reg(dst, tmp); 8276 %} 8277 %} 8278 8279 8280 instruct convI2D_helper(regD dst, regF tmp) %{ 8281 effect(USE tmp, DEF dst); 8282 format %{ "FITOD $tmp,$dst" %} 8283 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8284 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8285 ins_pipe(fcvtI2D); 8286 %} 8287 8288 instruct convI2D_stk(stackSlotI src, regD dst) %{ 8289 match(Set dst (ConvI2D src)); 8290 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8291 expand %{ 8292 regF tmp; 8293 stkI_to_regF(tmp, src); 8294 convI2D_helper(dst, tmp); 8295 %} 8296 %} 8297 8298 instruct convI2D_reg(regD_low dst, iRegI src) %{ 8299 predicate(UseVIS >= 3); 8300 match(Set dst (ConvI2D src)); 8301 expand %{ 8302 regF tmp; 8303 MoveI2F_reg_reg(tmp, src); 8304 convI2D_helper(dst, tmp); 8305 %} 8306 %} 8307 8308 instruct convI2D_mem(regD_low dst, memory mem) %{ 8309 match(Set dst (ConvI2D (LoadI mem))); 8310 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8311 format %{ "LDF $mem,$dst\n\t" 8312 "FITOD $dst,$dst" %} 8313 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8314 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8315 ins_pipe(floadF_mem); 8316 %} 8317 8318 8319 instruct convI2F_helper(regF dst, regF tmp) %{ 8320 effect(DEF dst, USE tmp); 8321 format %{ "FITOS $tmp,$dst" %} 8322 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8323 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8324 ins_pipe(fcvtI2F); 8325 %} 8326 8327 instruct convI2F_stk(regF dst, stackSlotI src) %{ 8328 match(Set dst (ConvI2F src)); 8329 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8330 expand %{ 8331 regF tmp; 8332 stkI_to_regF(tmp,src); 8333 convI2F_helper(dst, tmp); 8334 %} 8335 %} 8336 8337 instruct convI2F_reg(regF dst, iRegI src) %{ 8338 predicate(UseVIS >= 3); 8339 match(Set dst (ConvI2F src)); 8340 ins_cost(DEFAULT_COST); 8341 expand %{ 8342 regF tmp; 8343 MoveI2F_reg_reg(tmp, src); 8344 convI2F_helper(dst, tmp); 8345 %} 8346 %} 8347 8348 instruct convI2F_mem( regF dst, memory mem ) %{ 8349 match(Set dst (ConvI2F (LoadI mem))); 8350 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8351 format %{ "LDF $mem,$dst\n\t" 8352 "FITOS $dst,$dst" %} 8353 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8354 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8355 ins_pipe(floadF_mem); 8356 %} 8357 8358 8359 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8360 match(Set dst (ConvI2L src)); 8361 size(4); 8362 format %{ "SRA $src,0,$dst\t! int->long" %} 8363 opcode(Assembler::sra_op3, Assembler::arith_op); 8364 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8365 ins_pipe(ialu_reg_reg); 8366 %} 8367 8368 // Zero-extend convert int to long 8369 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8370 match(Set dst (AndL (ConvI2L src) mask) ); 8371 size(4); 8372 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8373 opcode(Assembler::srl_op3, Assembler::arith_op); 8374 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8375 ins_pipe(ialu_reg_reg); 8376 %} 8377 8378 // Zero-extend long 8379 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8380 match(Set dst (AndL src mask) ); 8381 size(4); 8382 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8383 opcode(Assembler::srl_op3, Assembler::arith_op); 8384 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8385 ins_pipe(ialu_reg_reg); 8386 %} 8387 8388 8389 //----------- 8390 // Long to Double conversion using V8 opcodes. 8391 // Still useful because cheetah traps and becomes 8392 // amazingly slow for some common numbers. 8393 8394 // Magic constant, 0x43300000 8395 instruct loadConI_x43300000(iRegI dst) %{ 8396 effect(DEF dst); 8397 size(4); 8398 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8399 ins_encode(SetHi22(0x43300000, dst)); 8400 ins_pipe(ialu_none); 8401 %} 8402 8403 // Magic constant, 0x41f00000 8404 instruct loadConI_x41f00000(iRegI dst) %{ 8405 effect(DEF dst); 8406 size(4); 8407 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8408 ins_encode(SetHi22(0x41f00000, dst)); 8409 ins_pipe(ialu_none); 8410 %} 8411 8412 // Construct a double from two float halves 8413 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8414 effect(DEF dst, USE src1, USE src2); 8415 size(8); 8416 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8417 "FMOVS $src2.lo,$dst.lo" %} 8418 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8419 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8420 ins_pipe(faddD_reg_reg); 8421 %} 8422 8423 // Convert integer in high half of a double register (in the lower half of 8424 // the double register file) to double 8425 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8426 effect(DEF dst, USE src); 8427 size(4); 8428 format %{ "FITOD $src,$dst" %} 8429 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8430 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8431 ins_pipe(fcvtLHi2D); 8432 %} 8433 8434 // Add float double precision 8435 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8436 effect(DEF dst, USE src1, USE src2); 8437 size(4); 8438 format %{ "FADDD $src1,$src2,$dst" %} 8439 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8440 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8441 ins_pipe(faddD_reg_reg); 8442 %} 8443 8444 // Sub float double precision 8445 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8446 effect(DEF dst, USE src1, USE src2); 8447 size(4); 8448 format %{ "FSUBD $src1,$src2,$dst" %} 8449 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8450 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8451 ins_pipe(faddD_reg_reg); 8452 %} 8453 8454 // Mul float double precision 8455 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8456 effect(DEF dst, USE src1, USE src2); 8457 size(4); 8458 format %{ "FMULD $src1,$src2,$dst" %} 8459 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8460 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8461 ins_pipe(fmulD_reg_reg); 8462 %} 8463 8464 // Long to Double conversion using fast fxtof 8465 instruct convL2D_helper(regD dst, regD tmp) %{ 8466 effect(DEF dst, USE tmp); 8467 size(4); 8468 format %{ "FXTOD $tmp,$dst" %} 8469 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8470 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8471 ins_pipe(fcvtL2D); 8472 %} 8473 8474 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ 8475 match(Set dst (ConvL2D src)); 8476 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8477 expand %{ 8478 regD tmp; 8479 stkL_to_regD(tmp, src); 8480 convL2D_helper(dst, tmp); 8481 %} 8482 %} 8483 8484 instruct convL2D_reg(regD dst, iRegL src) %{ 8485 predicate(UseVIS >= 3); 8486 match(Set dst (ConvL2D src)); 8487 expand %{ 8488 regD tmp; 8489 MoveL2D_reg_reg(tmp, src); 8490 convL2D_helper(dst, tmp); 8491 %} 8492 %} 8493 8494 // Long to Float conversion using fast fxtof 8495 instruct convL2F_helper(regF dst, regD tmp) %{ 8496 effect(DEF dst, USE tmp); 8497 size(4); 8498 format %{ "FXTOS $tmp,$dst" %} 8499 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8500 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8501 ins_pipe(fcvtL2F); 8502 %} 8503 8504 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ 8505 match(Set dst (ConvL2F src)); 8506 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8507 expand %{ 8508 regD tmp; 8509 stkL_to_regD(tmp, src); 8510 convL2F_helper(dst, tmp); 8511 %} 8512 %} 8513 8514 instruct convL2F_reg(regF dst, iRegL src) %{ 8515 predicate(UseVIS >= 3); 8516 match(Set dst (ConvL2F src)); 8517 ins_cost(DEFAULT_COST); 8518 expand %{ 8519 regD tmp; 8520 MoveL2D_reg_reg(tmp, src); 8521 convL2F_helper(dst, tmp); 8522 %} 8523 %} 8524 8525 //----------- 8526 8527 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8528 match(Set dst (ConvL2I src)); 8529 size(4); 8530 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8531 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8532 ins_pipe(ialu_reg); 8533 %} 8534 8535 // Register Shift Right Immediate 8536 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8537 match(Set dst (ConvL2I (RShiftL src cnt))); 8538 8539 size(4); 8540 format %{ "SRAX $src,$cnt,$dst" %} 8541 opcode(Assembler::srax_op3, Assembler::arith_op); 8542 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8543 ins_pipe(ialu_reg_imm); 8544 %} 8545 8546 //----------Control Flow Instructions------------------------------------------ 8547 // Compare Instructions 8548 // Compare Integers 8549 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8550 match(Set icc (CmpI op1 op2)); 8551 effect( DEF icc, USE op1, USE op2 ); 8552 8553 size(4); 8554 format %{ "CMP $op1,$op2" %} 8555 opcode(Assembler::subcc_op3, Assembler::arith_op); 8556 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8557 ins_pipe(ialu_cconly_reg_reg); 8558 %} 8559 8560 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8561 match(Set icc (CmpU op1 op2)); 8562 8563 size(4); 8564 format %{ "CMP $op1,$op2\t! unsigned" %} 8565 opcode(Assembler::subcc_op3, Assembler::arith_op); 8566 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8567 ins_pipe(ialu_cconly_reg_reg); 8568 %} 8569 8570 instruct compUL_iReg(flagsRegUL xcc, iRegL op1, iRegL op2) %{ 8571 match(Set xcc (CmpUL op1 op2)); 8572 effect(DEF xcc, USE op1, USE op2); 8573 8574 size(4); 8575 format %{ "CMP $op1,$op2\t! unsigned long" %} 8576 opcode(Assembler::subcc_op3, Assembler::arith_op); 8577 ins_encode(form3_rs1_rs2_rd(op1, op2, R_G0)); 8578 ins_pipe(ialu_cconly_reg_reg); 8579 %} 8580 8581 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8582 match(Set icc (CmpI op1 op2)); 8583 effect( DEF icc, USE op1 ); 8584 8585 size(4); 8586 format %{ "CMP $op1,$op2" %} 8587 opcode(Assembler::subcc_op3, Assembler::arith_op); 8588 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8589 ins_pipe(ialu_cconly_reg_imm); 8590 %} 8591 8592 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8593 match(Set icc (CmpI (AndI op1 op2) zero)); 8594 8595 size(4); 8596 format %{ "BTST $op2,$op1" %} 8597 opcode(Assembler::andcc_op3, Assembler::arith_op); 8598 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8599 ins_pipe(ialu_cconly_reg_reg_zero); 8600 %} 8601 8602 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8603 match(Set icc (CmpI (AndI op1 op2) zero)); 8604 8605 size(4); 8606 format %{ "BTST $op2,$op1" %} 8607 opcode(Assembler::andcc_op3, Assembler::arith_op); 8608 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8609 ins_pipe(ialu_cconly_reg_imm_zero); 8610 %} 8611 8612 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8613 match(Set xcc (CmpL op1 op2)); 8614 effect( DEF xcc, USE op1, USE op2 ); 8615 8616 size(4); 8617 format %{ "CMP $op1,$op2\t\t! long" %} 8618 opcode(Assembler::subcc_op3, Assembler::arith_op); 8619 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8620 ins_pipe(ialu_cconly_reg_reg); 8621 %} 8622 8623 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8624 match(Set xcc (CmpL op1 con)); 8625 effect( DEF xcc, USE op1, USE con ); 8626 8627 size(4); 8628 format %{ "CMP $op1,$con\t\t! long" %} 8629 opcode(Assembler::subcc_op3, Assembler::arith_op); 8630 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8631 ins_pipe(ialu_cconly_reg_reg); 8632 %} 8633 8634 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8635 match(Set xcc (CmpL (AndL op1 op2) zero)); 8636 effect( DEF xcc, USE op1, USE op2 ); 8637 8638 size(4); 8639 format %{ "BTST $op1,$op2\t\t! long" %} 8640 opcode(Assembler::andcc_op3, Assembler::arith_op); 8641 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8642 ins_pipe(ialu_cconly_reg_reg); 8643 %} 8644 8645 // useful for checking the alignment of a pointer: 8646 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8647 match(Set xcc (CmpL (AndL op1 con) zero)); 8648 effect( DEF xcc, USE op1, USE con ); 8649 8650 size(4); 8651 format %{ "BTST $op1,$con\t\t! long" %} 8652 opcode(Assembler::andcc_op3, Assembler::arith_op); 8653 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8654 ins_pipe(ialu_cconly_reg_reg); 8655 %} 8656 8657 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ 8658 match(Set icc (CmpU op1 op2)); 8659 8660 size(4); 8661 format %{ "CMP $op1,$op2\t! unsigned" %} 8662 opcode(Assembler::subcc_op3, Assembler::arith_op); 8663 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8664 ins_pipe(ialu_cconly_reg_imm); 8665 %} 8666 8667 instruct compUL_iReg_imm13(flagsRegUL xcc, iRegL op1, immUL12 op2) %{ 8668 match(Set xcc (CmpUL op1 op2)); 8669 effect(DEF xcc, USE op1, USE op2); 8670 8671 size(4); 8672 format %{ "CMP $op1,$op2\t! unsigned long" %} 8673 opcode(Assembler::subcc_op3, Assembler::arith_op); 8674 ins_encode(form3_rs1_simm13_rd(op1, op2, R_G0)); 8675 ins_pipe(ialu_cconly_reg_imm); 8676 %} 8677 8678 // Compare Pointers 8679 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8680 match(Set pcc (CmpP op1 op2)); 8681 8682 size(4); 8683 format %{ "CMP $op1,$op2\t! ptr" %} 8684 opcode(Assembler::subcc_op3, Assembler::arith_op); 8685 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8686 ins_pipe(ialu_cconly_reg_reg); 8687 %} 8688 8689 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8690 match(Set pcc (CmpP op1 op2)); 8691 8692 size(4); 8693 format %{ "CMP $op1,$op2\t! ptr" %} 8694 opcode(Assembler::subcc_op3, Assembler::arith_op); 8695 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8696 ins_pipe(ialu_cconly_reg_imm); 8697 %} 8698 8699 // Compare Narrow oops 8700 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8701 match(Set icc (CmpN op1 op2)); 8702 8703 size(4); 8704 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8705 opcode(Assembler::subcc_op3, Assembler::arith_op); 8706 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8707 ins_pipe(ialu_cconly_reg_reg); 8708 %} 8709 8710 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8711 match(Set icc (CmpN op1 op2)); 8712 8713 size(4); 8714 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8715 opcode(Assembler::subcc_op3, Assembler::arith_op); 8716 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8717 ins_pipe(ialu_cconly_reg_imm); 8718 %} 8719 8720 //----------Max and Min-------------------------------------------------------- 8721 // Min Instructions 8722 // Conditional move for min 8723 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8724 effect( USE_DEF op2, USE op1, USE icc ); 8725 8726 size(4); 8727 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8728 opcode(Assembler::less); 8729 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8730 ins_pipe(ialu_reg_flags); 8731 %} 8732 8733 // Min Register with Register. 8734 instruct minI_eReg(iRegI op1, iRegI op2) %{ 8735 match(Set op2 (MinI op1 op2)); 8736 ins_cost(DEFAULT_COST*2); 8737 expand %{ 8738 flagsReg icc; 8739 compI_iReg(icc,op1,op2); 8740 cmovI_reg_lt(op2,op1,icc); 8741 %} 8742 %} 8743 8744 // Max Instructions 8745 // Conditional move for max 8746 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8747 effect( USE_DEF op2, USE op1, USE icc ); 8748 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8749 opcode(Assembler::greater); 8750 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8751 ins_pipe(ialu_reg_flags); 8752 %} 8753 8754 // Max Register with Register 8755 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8756 match(Set op2 (MaxI op1 op2)); 8757 ins_cost(DEFAULT_COST*2); 8758 expand %{ 8759 flagsReg icc; 8760 compI_iReg(icc,op1,op2); 8761 cmovI_reg_gt(op2,op1,icc); 8762 %} 8763 %} 8764 8765 8766 //----------Float Compares---------------------------------------------------- 8767 // Compare floating, generate condition code 8768 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8769 match(Set fcc (CmpF src1 src2)); 8770 8771 size(4); 8772 format %{ "FCMPs $fcc,$src1,$src2" %} 8773 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8774 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8775 ins_pipe(faddF_fcc_reg_reg_zero); 8776 %} 8777 8778 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8779 match(Set fcc (CmpD src1 src2)); 8780 8781 size(4); 8782 format %{ "FCMPd $fcc,$src1,$src2" %} 8783 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8784 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8785 ins_pipe(faddD_fcc_reg_reg_zero); 8786 %} 8787 8788 8789 // Compare floating, generate -1,0,1 8790 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8791 match(Set dst (CmpF3 src1 src2)); 8792 effect(KILL fcc0); 8793 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8794 format %{ "fcmpl $dst,$src1,$src2" %} 8795 // Primary = float 8796 opcode( true ); 8797 ins_encode( floating_cmp( dst, src1, src2 ) ); 8798 ins_pipe( floating_cmp ); 8799 %} 8800 8801 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 8802 match(Set dst (CmpD3 src1 src2)); 8803 effect(KILL fcc0); 8804 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8805 format %{ "dcmpl $dst,$src1,$src2" %} 8806 // Primary = double (not float) 8807 opcode( false ); 8808 ins_encode( floating_cmp( dst, src1, src2 ) ); 8809 ins_pipe( floating_cmp ); 8810 %} 8811 8812 //----------Branches--------------------------------------------------------- 8813 // Jump 8814 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 8815 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 8816 match(Jump switch_val); 8817 effect(TEMP table); 8818 8819 ins_cost(350); 8820 8821 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" 8822 "LD [O7 + $switch_val], O7\n\t" 8823 "JUMP O7" %} 8824 ins_encode %{ 8825 // Calculate table address into a register. 8826 Register table_reg; 8827 Register label_reg = O7; 8828 // If we are calculating the size of this instruction don't trust 8829 // zero offsets because they might change when 8830 // MachConstantBaseNode decides to optimize the constant table 8831 // base. 8832 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { 8833 table_reg = $constanttablebase; 8834 } else { 8835 table_reg = O7; 8836 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); 8837 __ add($constanttablebase, con_offset, table_reg); 8838 } 8839 8840 // Jump to base address + switch value 8841 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); 8842 __ jmp(label_reg, G0); 8843 __ delayed()->nop(); 8844 %} 8845 ins_pipe(ialu_reg_reg); 8846 %} 8847 8848 // Direct Branch. Use V8 version with longer range. 8849 instruct branch(label labl) %{ 8850 match(Goto); 8851 effect(USE labl); 8852 8853 size(8); 8854 ins_cost(BRANCH_COST); 8855 format %{ "BA $labl" %} 8856 ins_encode %{ 8857 Label* L = $labl$$label; 8858 __ ba(*L); 8859 __ delayed()->nop(); 8860 %} 8861 ins_avoid_back_to_back(AVOID_BEFORE); 8862 ins_pipe(br); 8863 %} 8864 8865 // Direct Branch, short with no delay slot 8866 instruct branch_short(label labl) %{ 8867 match(Goto); 8868 predicate(UseCBCond); 8869 effect(USE labl); 8870 8871 size(4); // Assuming no NOP inserted. 8872 ins_cost(BRANCH_COST); 8873 format %{ "BA $labl\t! short branch" %} 8874 ins_encode %{ 8875 Label* L = $labl$$label; 8876 assert(__ use_cbcond(*L), "back to back cbcond"); 8877 __ ba_short(*L); 8878 %} 8879 ins_short_branch(1); 8880 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 8881 ins_pipe(cbcond_reg_imm); 8882 %} 8883 8884 // Conditional Direct Branch 8885 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 8886 match(If cmp icc); 8887 effect(USE labl); 8888 8889 size(8); 8890 ins_cost(BRANCH_COST); 8891 format %{ "BP$cmp $icc,$labl" %} 8892 // Prim = bits 24-22, Secnd = bits 31-30 8893 ins_encode( enc_bp( labl, cmp, icc ) ); 8894 ins_avoid_back_to_back(AVOID_BEFORE); 8895 ins_pipe(br_cc); 8896 %} 8897 8898 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8899 match(If cmp icc); 8900 effect(USE labl); 8901 8902 ins_cost(BRANCH_COST); 8903 format %{ "BP$cmp $icc,$labl" %} 8904 // Prim = bits 24-22, Secnd = bits 31-30 8905 ins_encode( enc_bp( labl, cmp, icc ) ); 8906 ins_avoid_back_to_back(AVOID_BEFORE); 8907 ins_pipe(br_cc); 8908 %} 8909 8910 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 8911 match(If cmp pcc); 8912 effect(USE labl); 8913 8914 size(8); 8915 ins_cost(BRANCH_COST); 8916 format %{ "BP$cmp $pcc,$labl" %} 8917 ins_encode %{ 8918 Label* L = $labl$$label; 8919 Assembler::Predict predict_taken = 8920 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8921 8922 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 8923 __ delayed()->nop(); 8924 %} 8925 ins_avoid_back_to_back(AVOID_BEFORE); 8926 ins_pipe(br_cc); 8927 %} 8928 8929 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 8930 match(If cmp fcc); 8931 effect(USE labl); 8932 8933 size(8); 8934 ins_cost(BRANCH_COST); 8935 format %{ "FBP$cmp $fcc,$labl" %} 8936 ins_encode %{ 8937 Label* L = $labl$$label; 8938 Assembler::Predict predict_taken = 8939 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8940 8941 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); 8942 __ delayed()->nop(); 8943 %} 8944 ins_avoid_back_to_back(AVOID_BEFORE); 8945 ins_pipe(br_fcc); 8946 %} 8947 8948 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 8949 match(CountedLoopEnd cmp icc); 8950 effect(USE labl); 8951 8952 size(8); 8953 ins_cost(BRANCH_COST); 8954 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8955 // Prim = bits 24-22, Secnd = bits 31-30 8956 ins_encode( enc_bp( labl, cmp, icc ) ); 8957 ins_avoid_back_to_back(AVOID_BEFORE); 8958 ins_pipe(br_cc); 8959 %} 8960 8961 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8962 match(CountedLoopEnd cmp icc); 8963 effect(USE labl); 8964 8965 size(8); 8966 ins_cost(BRANCH_COST); 8967 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8968 // Prim = bits 24-22, Secnd = bits 31-30 8969 ins_encode( enc_bp( labl, cmp, icc ) ); 8970 ins_avoid_back_to_back(AVOID_BEFORE); 8971 ins_pipe(br_cc); 8972 %} 8973 8974 // Compare and branch instructions 8975 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 8976 match(If cmp (CmpI op1 op2)); 8977 effect(USE labl, KILL icc); 8978 8979 size(12); 8980 ins_cost(BRANCH_COST); 8981 format %{ "CMP $op1,$op2\t! int\n\t" 8982 "BP$cmp $labl" %} 8983 ins_encode %{ 8984 Label* L = $labl$$label; 8985 Assembler::Predict predict_taken = 8986 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8987 __ cmp($op1$$Register, $op2$$Register); 8988 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8989 __ delayed()->nop(); 8990 %} 8991 ins_pipe(cmp_br_reg_reg); 8992 %} 8993 8994 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 8995 match(If cmp (CmpI op1 op2)); 8996 effect(USE labl, KILL icc); 8997 8998 size(12); 8999 ins_cost(BRANCH_COST); 9000 format %{ "CMP $op1,$op2\t! int\n\t" 9001 "BP$cmp $labl" %} 9002 ins_encode %{ 9003 Label* L = $labl$$label; 9004 Assembler::Predict predict_taken = 9005 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9006 __ cmp($op1$$Register, $op2$$constant); 9007 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9008 __ delayed()->nop(); 9009 %} 9010 ins_pipe(cmp_br_reg_imm); 9011 %} 9012 9013 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9014 match(If cmp (CmpU op1 op2)); 9015 effect(USE labl, KILL icc); 9016 9017 size(12); 9018 ins_cost(BRANCH_COST); 9019 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9020 "BP$cmp $labl" %} 9021 ins_encode %{ 9022 Label* L = $labl$$label; 9023 Assembler::Predict predict_taken = 9024 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9025 __ cmp($op1$$Register, $op2$$Register); 9026 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9027 __ delayed()->nop(); 9028 %} 9029 ins_pipe(cmp_br_reg_reg); 9030 %} 9031 9032 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9033 match(If cmp (CmpU op1 op2)); 9034 effect(USE labl, KILL icc); 9035 9036 size(12); 9037 ins_cost(BRANCH_COST); 9038 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9039 "BP$cmp $labl" %} 9040 ins_encode %{ 9041 Label* L = $labl$$label; 9042 Assembler::Predict predict_taken = 9043 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9044 __ cmp($op1$$Register, $op2$$constant); 9045 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9046 __ delayed()->nop(); 9047 %} 9048 ins_pipe(cmp_br_reg_imm); 9049 %} 9050 9051 instruct cmpUL_reg_branch(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{ 9052 match(If cmp (CmpUL op1 op2)); 9053 effect(USE labl, KILL xcc); 9054 9055 size(12); 9056 ins_cost(BRANCH_COST); 9057 format %{ "CMP $op1,$op2\t! unsigned long\n\t" 9058 "BP$cmp $labl" %} 9059 ins_encode %{ 9060 Label* L = $labl$$label; 9061 Assembler::Predict predict_taken = 9062 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9063 __ cmp($op1$$Register, $op2$$Register); 9064 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9065 __ delayed()->nop(); 9066 %} 9067 ins_pipe(cmp_br_reg_reg); 9068 %} 9069 9070 instruct cmpUL_imm_branch(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{ 9071 match(If cmp (CmpUL op1 op2)); 9072 effect(USE labl, KILL xcc); 9073 9074 size(12); 9075 ins_cost(BRANCH_COST); 9076 format %{ "CMP $op1,$op2\t! unsigned long\n\t" 9077 "BP$cmp $labl" %} 9078 ins_encode %{ 9079 Label* L = $labl$$label; 9080 Assembler::Predict predict_taken = 9081 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9082 __ cmp($op1$$Register, $op2$$constant); 9083 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9084 __ delayed()->nop(); 9085 %} 9086 ins_pipe(cmp_br_reg_imm); 9087 %} 9088 9089 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9090 match(If cmp (CmpL op1 op2)); 9091 effect(USE labl, KILL xcc); 9092 9093 size(12); 9094 ins_cost(BRANCH_COST); 9095 format %{ "CMP $op1,$op2\t! long\n\t" 9096 "BP$cmp $labl" %} 9097 ins_encode %{ 9098 Label* L = $labl$$label; 9099 Assembler::Predict predict_taken = 9100 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9101 __ cmp($op1$$Register, $op2$$Register); 9102 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9103 __ delayed()->nop(); 9104 %} 9105 ins_pipe(cmp_br_reg_reg); 9106 %} 9107 9108 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9109 match(If cmp (CmpL op1 op2)); 9110 effect(USE labl, KILL xcc); 9111 9112 size(12); 9113 ins_cost(BRANCH_COST); 9114 format %{ "CMP $op1,$op2\t! long\n\t" 9115 "BP$cmp $labl" %} 9116 ins_encode %{ 9117 Label* L = $labl$$label; 9118 Assembler::Predict predict_taken = 9119 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9120 __ cmp($op1$$Register, $op2$$constant); 9121 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9122 __ delayed()->nop(); 9123 %} 9124 ins_pipe(cmp_br_reg_imm); 9125 %} 9126 9127 // Compare Pointers and branch 9128 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9129 match(If cmp (CmpP op1 op2)); 9130 effect(USE labl, KILL pcc); 9131 9132 size(12); 9133 ins_cost(BRANCH_COST); 9134 format %{ "CMP $op1,$op2\t! ptr\n\t" 9135 "B$cmp $labl" %} 9136 ins_encode %{ 9137 Label* L = $labl$$label; 9138 Assembler::Predict predict_taken = 9139 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9140 __ cmp($op1$$Register, $op2$$Register); 9141 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9142 __ delayed()->nop(); 9143 %} 9144 ins_pipe(cmp_br_reg_reg); 9145 %} 9146 9147 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9148 match(If cmp (CmpP op1 null)); 9149 effect(USE labl, KILL pcc); 9150 9151 size(12); 9152 ins_cost(BRANCH_COST); 9153 format %{ "CMP $op1,0\t! ptr\n\t" 9154 "B$cmp $labl" %} 9155 ins_encode %{ 9156 Label* L = $labl$$label; 9157 Assembler::Predict predict_taken = 9158 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9159 __ cmp($op1$$Register, G0); 9160 // bpr() is not used here since it has shorter distance. 9161 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9162 __ delayed()->nop(); 9163 %} 9164 ins_pipe(cmp_br_reg_reg); 9165 %} 9166 9167 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9168 match(If cmp (CmpN op1 op2)); 9169 effect(USE labl, KILL icc); 9170 9171 size(12); 9172 ins_cost(BRANCH_COST); 9173 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" 9174 "BP$cmp $labl" %} 9175 ins_encode %{ 9176 Label* L = $labl$$label; 9177 Assembler::Predict predict_taken = 9178 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9179 __ cmp($op1$$Register, $op2$$Register); 9180 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9181 __ delayed()->nop(); 9182 %} 9183 ins_pipe(cmp_br_reg_reg); 9184 %} 9185 9186 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9187 match(If cmp (CmpN op1 null)); 9188 effect(USE labl, KILL icc); 9189 9190 size(12); 9191 ins_cost(BRANCH_COST); 9192 format %{ "CMP $op1,0\t! compressed ptr\n\t" 9193 "BP$cmp $labl" %} 9194 ins_encode %{ 9195 Label* L = $labl$$label; 9196 Assembler::Predict predict_taken = 9197 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9198 __ cmp($op1$$Register, G0); 9199 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9200 __ delayed()->nop(); 9201 %} 9202 ins_pipe(cmp_br_reg_reg); 9203 %} 9204 9205 // Loop back branch 9206 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9207 match(CountedLoopEnd cmp (CmpI op1 op2)); 9208 effect(USE labl, KILL icc); 9209 9210 size(12); 9211 ins_cost(BRANCH_COST); 9212 format %{ "CMP $op1,$op2\t! int\n\t" 9213 "BP$cmp $labl\t! Loop end" %} 9214 ins_encode %{ 9215 Label* L = $labl$$label; 9216 Assembler::Predict predict_taken = 9217 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9218 __ cmp($op1$$Register, $op2$$Register); 9219 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9220 __ delayed()->nop(); 9221 %} 9222 ins_pipe(cmp_br_reg_reg); 9223 %} 9224 9225 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9226 match(CountedLoopEnd cmp (CmpI op1 op2)); 9227 effect(USE labl, KILL icc); 9228 9229 size(12); 9230 ins_cost(BRANCH_COST); 9231 format %{ "CMP $op1,$op2\t! int\n\t" 9232 "BP$cmp $labl\t! Loop end" %} 9233 ins_encode %{ 9234 Label* L = $labl$$label; 9235 Assembler::Predict predict_taken = 9236 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9237 __ cmp($op1$$Register, $op2$$constant); 9238 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9239 __ delayed()->nop(); 9240 %} 9241 ins_pipe(cmp_br_reg_imm); 9242 %} 9243 9244 // Short compare and branch instructions 9245 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9246 match(If cmp (CmpI op1 op2)); 9247 predicate(UseCBCond); 9248 effect(USE labl, KILL icc); 9249 9250 size(4); // Assuming no NOP inserted. 9251 ins_cost(BRANCH_COST); 9252 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9253 ins_encode %{ 9254 Label* L = $labl$$label; 9255 assert(__ use_cbcond(*L), "back to back cbcond"); 9256 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9257 %} 9258 ins_short_branch(1); 9259 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9260 ins_pipe(cbcond_reg_reg); 9261 %} 9262 9263 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9264 match(If cmp (CmpI op1 op2)); 9265 predicate(UseCBCond); 9266 effect(USE labl, KILL icc); 9267 9268 size(4); // Assuming no NOP inserted. 9269 ins_cost(BRANCH_COST); 9270 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9271 ins_encode %{ 9272 Label* L = $labl$$label; 9273 assert(__ use_cbcond(*L), "back to back cbcond"); 9274 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9275 %} 9276 ins_short_branch(1); 9277 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9278 ins_pipe(cbcond_reg_imm); 9279 %} 9280 9281 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9282 match(If cmp (CmpU op1 op2)); 9283 predicate(UseCBCond); 9284 effect(USE labl, KILL icc); 9285 9286 size(4); // Assuming no NOP inserted. 9287 ins_cost(BRANCH_COST); 9288 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9289 ins_encode %{ 9290 Label* L = $labl$$label; 9291 assert(__ use_cbcond(*L), "back to back cbcond"); 9292 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9293 %} 9294 ins_short_branch(1); 9295 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9296 ins_pipe(cbcond_reg_reg); 9297 %} 9298 9299 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9300 match(If cmp (CmpU op1 op2)); 9301 predicate(UseCBCond); 9302 effect(USE labl, KILL icc); 9303 9304 size(4); // Assuming no NOP inserted. 9305 ins_cost(BRANCH_COST); 9306 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9307 ins_encode %{ 9308 Label* L = $labl$$label; 9309 assert(__ use_cbcond(*L), "back to back cbcond"); 9310 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9311 %} 9312 ins_short_branch(1); 9313 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9314 ins_pipe(cbcond_reg_imm); 9315 %} 9316 9317 instruct cmpUL_reg_branch_short(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{ 9318 match(If cmp (CmpUL op1 op2)); 9319 predicate(UseCBCond); 9320 effect(USE labl, KILL xcc); 9321 9322 size(4); 9323 ins_cost(BRANCH_COST); 9324 format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %} 9325 ins_encode %{ 9326 Label* L = $labl$$label; 9327 assert(__ use_cbcond(*L), "back to back cbcond"); 9328 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9329 %} 9330 ins_short_branch(1); 9331 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9332 ins_pipe(cbcond_reg_reg); 9333 %} 9334 9335 instruct cmpUL_imm_branch_short(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{ 9336 match(If cmp (CmpUL op1 op2)); 9337 predicate(UseCBCond); 9338 effect(USE labl, KILL xcc); 9339 9340 size(4); 9341 ins_cost(BRANCH_COST); 9342 format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %} 9343 ins_encode %{ 9344 Label* L = $labl$$label; 9345 assert(__ use_cbcond(*L), "back to back cbcond"); 9346 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9347 %} 9348 ins_short_branch(1); 9349 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9350 ins_pipe(cbcond_reg_imm); 9351 %} 9352 9353 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9354 match(If cmp (CmpL op1 op2)); 9355 predicate(UseCBCond); 9356 effect(USE labl, KILL xcc); 9357 9358 size(4); // Assuming no NOP inserted. 9359 ins_cost(BRANCH_COST); 9360 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9361 ins_encode %{ 9362 Label* L = $labl$$label; 9363 assert(__ use_cbcond(*L), "back to back cbcond"); 9364 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9365 %} 9366 ins_short_branch(1); 9367 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9368 ins_pipe(cbcond_reg_reg); 9369 %} 9370 9371 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9372 match(If cmp (CmpL op1 op2)); 9373 predicate(UseCBCond); 9374 effect(USE labl, KILL xcc); 9375 9376 size(4); // Assuming no NOP inserted. 9377 ins_cost(BRANCH_COST); 9378 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9379 ins_encode %{ 9380 Label* L = $labl$$label; 9381 assert(__ use_cbcond(*L), "back to back cbcond"); 9382 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9383 %} 9384 ins_short_branch(1); 9385 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9386 ins_pipe(cbcond_reg_imm); 9387 %} 9388 9389 // Compare Pointers and branch 9390 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9391 match(If cmp (CmpP op1 op2)); 9392 predicate(UseCBCond); 9393 effect(USE labl, KILL pcc); 9394 9395 size(4); // Assuming no NOP inserted. 9396 ins_cost(BRANCH_COST); 9397 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} 9398 ins_encode %{ 9399 Label* L = $labl$$label; 9400 assert(__ use_cbcond(*L), "back to back cbcond"); 9401 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); 9402 %} 9403 ins_short_branch(1); 9404 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9405 ins_pipe(cbcond_reg_reg); 9406 %} 9407 9408 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9409 match(If cmp (CmpP op1 null)); 9410 predicate(UseCBCond); 9411 effect(USE labl, KILL pcc); 9412 9413 size(4); // Assuming no NOP inserted. 9414 ins_cost(BRANCH_COST); 9415 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} 9416 ins_encode %{ 9417 Label* L = $labl$$label; 9418 assert(__ use_cbcond(*L), "back to back cbcond"); 9419 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); 9420 %} 9421 ins_short_branch(1); 9422 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9423 ins_pipe(cbcond_reg_reg); 9424 %} 9425 9426 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9427 match(If cmp (CmpN op1 op2)); 9428 predicate(UseCBCond); 9429 effect(USE labl, KILL icc); 9430 9431 size(4); // Assuming no NOP inserted. 9432 ins_cost(BRANCH_COST); 9433 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %} 9434 ins_encode %{ 9435 Label* L = $labl$$label; 9436 assert(__ use_cbcond(*L), "back to back cbcond"); 9437 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9438 %} 9439 ins_short_branch(1); 9440 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9441 ins_pipe(cbcond_reg_reg); 9442 %} 9443 9444 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9445 match(If cmp (CmpN op1 null)); 9446 predicate(UseCBCond); 9447 effect(USE labl, KILL icc); 9448 9449 size(4); // Assuming no NOP inserted. 9450 ins_cost(BRANCH_COST); 9451 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} 9452 ins_encode %{ 9453 Label* L = $labl$$label; 9454 assert(__ use_cbcond(*L), "back to back cbcond"); 9455 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); 9456 %} 9457 ins_short_branch(1); 9458 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9459 ins_pipe(cbcond_reg_reg); 9460 %} 9461 9462 // Loop back branch 9463 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9464 match(CountedLoopEnd cmp (CmpI op1 op2)); 9465 predicate(UseCBCond); 9466 effect(USE labl, KILL icc); 9467 9468 size(4); // Assuming no NOP inserted. 9469 ins_cost(BRANCH_COST); 9470 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9471 ins_encode %{ 9472 Label* L = $labl$$label; 9473 assert(__ use_cbcond(*L), "back to back cbcond"); 9474 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9475 %} 9476 ins_short_branch(1); 9477 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9478 ins_pipe(cbcond_reg_reg); 9479 %} 9480 9481 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9482 match(CountedLoopEnd cmp (CmpI op1 op2)); 9483 predicate(UseCBCond); 9484 effect(USE labl, KILL icc); 9485 9486 size(4); // Assuming no NOP inserted. 9487 ins_cost(BRANCH_COST); 9488 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9489 ins_encode %{ 9490 Label* L = $labl$$label; 9491 assert(__ use_cbcond(*L), "back to back cbcond"); 9492 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9493 %} 9494 ins_short_branch(1); 9495 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9496 ins_pipe(cbcond_reg_imm); 9497 %} 9498 9499 // Branch-on-register tests all 64 bits. We assume that values 9500 // in 64-bit registers always remains zero or sign extended 9501 // unless our code munges the high bits. Interrupts can chop 9502 // the high order bits to zero or sign at any time. 9503 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9504 match(If cmp (CmpI op1 zero)); 9505 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9506 effect(USE labl); 9507 9508 size(8); 9509 ins_cost(BRANCH_COST); 9510 format %{ "BR$cmp $op1,$labl" %} 9511 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9512 ins_avoid_back_to_back(AVOID_BEFORE); 9513 ins_pipe(br_reg); 9514 %} 9515 9516 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9517 match(If cmp (CmpP op1 null)); 9518 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9519 effect(USE labl); 9520 9521 size(8); 9522 ins_cost(BRANCH_COST); 9523 format %{ "BR$cmp $op1,$labl" %} 9524 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9525 ins_avoid_back_to_back(AVOID_BEFORE); 9526 ins_pipe(br_reg); 9527 %} 9528 9529 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9530 match(If cmp (CmpL op1 zero)); 9531 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9532 effect(USE labl); 9533 9534 size(8); 9535 ins_cost(BRANCH_COST); 9536 format %{ "BR$cmp $op1,$labl" %} 9537 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9538 ins_avoid_back_to_back(AVOID_BEFORE); 9539 ins_pipe(br_reg); 9540 %} 9541 9542 9543 // ============================================================================ 9544 // Long Compare 9545 // 9546 // Currently we hold longs in 2 registers. Comparing such values efficiently 9547 // is tricky. The flavor of compare used depends on whether we are testing 9548 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9549 // The GE test is the negated LT test. The LE test can be had by commuting 9550 // the operands (yielding a GE test) and then negating; negate again for the 9551 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9552 // NE test is negated from that. 9553 9554 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9555 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9556 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9557 // are collapsed internally in the ADLC's dfa-gen code. The match for 9558 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9559 // foo match ends up with the wrong leaf. One fix is to not match both 9560 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9561 // both forms beat the trinary form of long-compare and both are very useful 9562 // on Intel which has so few registers. 9563 9564 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9565 match(If cmp xcc); 9566 effect(USE labl); 9567 9568 size(8); 9569 ins_cost(BRANCH_COST); 9570 format %{ "BP$cmp $xcc,$labl" %} 9571 ins_encode %{ 9572 Label* L = $labl$$label; 9573 Assembler::Predict predict_taken = 9574 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9575 9576 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9577 __ delayed()->nop(); 9578 %} 9579 ins_avoid_back_to_back(AVOID_BEFORE); 9580 ins_pipe(br_cc); 9581 %} 9582 9583 instruct branchConU_long(cmpOpU cmp, flagsRegUL xcc, label labl) %{ 9584 match(If cmp xcc); 9585 effect(USE labl); 9586 9587 size(8); 9588 ins_cost(BRANCH_COST); 9589 format %{ "BP$cmp $xcc,$labl" %} 9590 ins_encode %{ 9591 Label* L = $labl$$label; 9592 Assembler::Predict predict_taken = 9593 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9594 9595 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9596 __ delayed()->nop(); 9597 %} 9598 ins_avoid_back_to_back(AVOID_BEFORE); 9599 ins_pipe(br_cc); 9600 %} 9601 9602 // Manifest a CmpL3 result in an integer register. Very painful. 9603 // This is the test to avoid. 9604 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9605 match(Set dst (CmpL3 src1 src2) ); 9606 effect( KILL ccr ); 9607 ins_cost(6*DEFAULT_COST); 9608 size(24); 9609 format %{ "CMP $src1,$src2\t\t! long\n" 9610 "\tBLT,a,pn done\n" 9611 "\tMOV -1,$dst\t! delay slot\n" 9612 "\tBGT,a,pn done\n" 9613 "\tMOV 1,$dst\t! delay slot\n" 9614 "\tCLR $dst\n" 9615 "done:" %} 9616 ins_encode( cmpl_flag(src1,src2,dst) ); 9617 ins_pipe(cmpL_reg); 9618 %} 9619 9620 // Conditional move 9621 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9622 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9623 ins_cost(150); 9624 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9625 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9626 ins_pipe(ialu_reg); 9627 %} 9628 9629 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9630 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9631 ins_cost(140); 9632 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9633 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9634 ins_pipe(ialu_imm); 9635 %} 9636 9637 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9638 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9639 ins_cost(150); 9640 format %{ "MOV$cmp $xcc,$src,$dst" %} 9641 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9642 ins_pipe(ialu_reg); 9643 %} 9644 9645 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9646 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9647 ins_cost(140); 9648 format %{ "MOV$cmp $xcc,$src,$dst" %} 9649 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9650 ins_pipe(ialu_imm); 9651 %} 9652 9653 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9654 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9655 ins_cost(150); 9656 format %{ "MOV$cmp $xcc,$src,$dst" %} 9657 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9658 ins_pipe(ialu_reg); 9659 %} 9660 9661 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9662 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9663 ins_cost(150); 9664 format %{ "MOV$cmp $xcc,$src,$dst" %} 9665 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9666 ins_pipe(ialu_reg); 9667 %} 9668 9669 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9670 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9671 ins_cost(140); 9672 format %{ "MOV$cmp $xcc,$src,$dst" %} 9673 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9674 ins_pipe(ialu_imm); 9675 %} 9676 9677 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9678 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9679 ins_cost(150); 9680 opcode(0x101); 9681 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9682 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9683 ins_pipe(int_conditional_float_move); 9684 %} 9685 9686 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9687 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9688 ins_cost(150); 9689 opcode(0x102); 9690 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9691 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9692 ins_pipe(int_conditional_float_move); 9693 %} 9694 9695 // ============================================================================ 9696 // Safepoint Instruction 9697 instruct safePoint_poll(iRegP poll) %{ 9698 match(SafePoint poll); 9699 effect(USE poll); 9700 9701 size(4); 9702 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9703 ins_encode %{ 9704 __ relocate(relocInfo::poll_type); 9705 __ ld_ptr($poll$$Register, 0, G0); 9706 %} 9707 ins_pipe(loadPollP); 9708 %} 9709 9710 // ============================================================================ 9711 // Call Instructions 9712 // Call Java Static Instruction 9713 instruct CallStaticJavaDirect( method meth ) %{ 9714 match(CallStaticJava); 9715 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9716 effect(USE meth); 9717 9718 size(8); 9719 ins_cost(CALL_COST); 9720 format %{ "CALL,static ; NOP ==> " %} 9721 ins_encode( Java_Static_Call( meth ), call_epilog ); 9722 ins_avoid_back_to_back(AVOID_BEFORE); 9723 ins_pipe(simple_call); 9724 %} 9725 9726 // Call Java Static Instruction (method handle version) 9727 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 9728 match(CallStaticJava); 9729 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9730 effect(USE meth, KILL l7_mh_SP_save); 9731 9732 size(16); 9733 ins_cost(CALL_COST); 9734 format %{ "CALL,static/MethodHandle" %} 9735 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 9736 ins_pipe(simple_call); 9737 %} 9738 9739 // Call Java Dynamic Instruction 9740 instruct CallDynamicJavaDirect( method meth ) %{ 9741 match(CallDynamicJava); 9742 effect(USE meth); 9743 9744 ins_cost(CALL_COST); 9745 format %{ "SET (empty),R_G5\n\t" 9746 "CALL,dynamic ; NOP ==> " %} 9747 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 9748 ins_pipe(call); 9749 %} 9750 9751 // Call Runtime Instruction 9752 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 9753 match(CallRuntime); 9754 effect(USE meth, KILL l7); 9755 ins_cost(CALL_COST); 9756 format %{ "CALL,runtime" %} 9757 ins_encode( Java_To_Runtime( meth ), 9758 call_epilog, adjust_long_from_native_call ); 9759 ins_avoid_back_to_back(AVOID_BEFORE); 9760 ins_pipe(simple_call); 9761 %} 9762 9763 // Call runtime without safepoint - same as CallRuntime 9764 instruct CallLeafDirect(method meth, l7RegP l7) %{ 9765 match(CallLeaf); 9766 effect(USE meth, KILL l7); 9767 ins_cost(CALL_COST); 9768 format %{ "CALL,runtime leaf" %} 9769 ins_encode( Java_To_Runtime( meth ), 9770 call_epilog, 9771 adjust_long_from_native_call ); 9772 ins_avoid_back_to_back(AVOID_BEFORE); 9773 ins_pipe(simple_call); 9774 %} 9775 9776 // Call runtime without safepoint - same as CallLeaf 9777 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 9778 match(CallLeafNoFP); 9779 effect(USE meth, KILL l7); 9780 ins_cost(CALL_COST); 9781 format %{ "CALL,runtime leaf nofp" %} 9782 ins_encode( Java_To_Runtime( meth ), 9783 call_epilog, 9784 adjust_long_from_native_call ); 9785 ins_avoid_back_to_back(AVOID_BEFORE); 9786 ins_pipe(simple_call); 9787 %} 9788 9789 // Tail Call; Jump from runtime stub to Java code. 9790 // Also known as an 'interprocedural jump'. 9791 // Target of jump will eventually return to caller. 9792 // TailJump below removes the return address. 9793 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 9794 match(TailCall jump_target method_oop ); 9795 9796 ins_cost(CALL_COST); 9797 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 9798 ins_encode(form_jmpl(jump_target)); 9799 ins_avoid_back_to_back(AVOID_BEFORE); 9800 ins_pipe(tail_call); 9801 %} 9802 9803 9804 // Return Instruction 9805 instruct Ret() %{ 9806 match(Return); 9807 9808 // The epilogue node did the ret already. 9809 size(0); 9810 format %{ "! return" %} 9811 ins_encode(); 9812 ins_pipe(empty); 9813 %} 9814 9815 9816 // Tail Jump; remove the return address; jump to target. 9817 // TailCall above leaves the return address around. 9818 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9819 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9820 // "restore" before this instruction (in Epilogue), we need to materialize it 9821 // in %i0. 9822 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 9823 match( TailJump jump_target ex_oop ); 9824 ins_cost(CALL_COST); 9825 format %{ "! discard R_O7\n\t" 9826 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 9827 ins_encode(form_jmpl_set_exception_pc(jump_target)); 9828 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 9829 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 9830 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 9831 ins_avoid_back_to_back(AVOID_BEFORE); 9832 ins_pipe(tail_call); 9833 %} 9834 9835 // Create exception oop: created by stack-crawling runtime code. 9836 // Created exception is now available to this handler, and is setup 9837 // just prior to jumping to this handler. No code emitted. 9838 instruct CreateException( o0RegP ex_oop ) 9839 %{ 9840 match(Set ex_oop (CreateEx)); 9841 ins_cost(0); 9842 9843 size(0); 9844 // use the following format syntax 9845 format %{ "! exception oop is in R_O0; no code emitted" %} 9846 ins_encode(); 9847 ins_pipe(empty); 9848 %} 9849 9850 9851 // Rethrow exception: 9852 // The exception oop will come in the first argument position. 9853 // Then JUMP (not call) to the rethrow stub code. 9854 instruct RethrowException() 9855 %{ 9856 match(Rethrow); 9857 ins_cost(CALL_COST); 9858 9859 // use the following format syntax 9860 format %{ "Jmp rethrow_stub" %} 9861 ins_encode(enc_rethrow); 9862 ins_avoid_back_to_back(AVOID_BEFORE); 9863 ins_pipe(tail_call); 9864 %} 9865 9866 9867 // Die now 9868 instruct ShouldNotReachHere( ) 9869 %{ 9870 match(Halt); 9871 ins_cost(CALL_COST); 9872 9873 size(4); 9874 // Use the following format syntax 9875 format %{ "ILLTRAP ; ShouldNotReachHere" %} 9876 ins_encode( form2_illtrap() ); 9877 ins_pipe(tail_call); 9878 %} 9879 9880 // ============================================================================ 9881 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9882 // array for an instance of the superklass. Set a hidden internal cache on a 9883 // hit (cache is checked with exposed code in gen_subtype_check()). Return 9884 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9885 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 9886 match(Set index (PartialSubtypeCheck sub super)); 9887 effect( KILL pcc, KILL o7 ); 9888 ins_cost(DEFAULT_COST*10); 9889 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 9890 ins_encode( enc_PartialSubtypeCheck() ); 9891 ins_avoid_back_to_back(AVOID_BEFORE); 9892 ins_pipe(partial_subtype_check_pipe); 9893 %} 9894 9895 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 9896 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 9897 effect( KILL idx, KILL o7 ); 9898 ins_cost(DEFAULT_COST*10); 9899 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 9900 ins_encode( enc_PartialSubtypeCheck() ); 9901 ins_avoid_back_to_back(AVOID_BEFORE); 9902 ins_pipe(partial_subtype_check_pipe); 9903 %} 9904 9905 9906 // ============================================================================ 9907 // inlined locking and unlocking 9908 9909 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 9910 match(Set pcc (FastLock object box)); 9911 9912 effect(TEMP scratch2, USE_KILL box, KILL scratch); 9913 ins_cost(100); 9914 9915 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 9916 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 9917 ins_pipe(long_memory_op); 9918 %} 9919 9920 9921 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 9922 match(Set pcc (FastUnlock object box)); 9923 effect(TEMP scratch2, USE_KILL box, KILL scratch); 9924 ins_cost(100); 9925 9926 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 9927 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 9928 ins_pipe(long_memory_op); 9929 %} 9930 9931 // The encodings are generic. 9932 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 9933 predicate(!use_block_zeroing(n->in(2)) ); 9934 match(Set dummy (ClearArray cnt base)); 9935 effect(TEMP temp, KILL ccr); 9936 ins_cost(300); 9937 format %{ "MOV $cnt,$temp\n" 9938 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 9939 " BRge loop\t\t! Clearing loop\n" 9940 " STX G0,[$base+$temp]\t! delay slot" %} 9941 9942 ins_encode %{ 9943 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 9944 Register nof_bytes_arg = $cnt$$Register; 9945 Register nof_bytes_tmp = $temp$$Register; 9946 Register base_pointer_arg = $base$$Register; 9947 9948 Label loop; 9949 __ mov(nof_bytes_arg, nof_bytes_tmp); 9950 9951 // Loop and clear, walking backwards through the array. 9952 // nof_bytes_tmp (if >0) is always the number of bytes to zero 9953 __ bind(loop); 9954 __ deccc(nof_bytes_tmp, 8); 9955 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 9956 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 9957 // %%%% this mini-loop must not cross a cache boundary! 9958 %} 9959 ins_pipe(long_memory_op); 9960 %} 9961 9962 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ 9963 predicate(use_block_zeroing(n->in(2))); 9964 match(Set dummy (ClearArray cnt base)); 9965 effect(USE_KILL cnt, USE_KILL base, KILL ccr); 9966 ins_cost(300); 9967 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 9968 9969 ins_encode %{ 9970 9971 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 9972 Register to = $base$$Register; 9973 Register count = $cnt$$Register; 9974 9975 Label Ldone; 9976 __ nop(); // Separate short branches 9977 // Use BIS for zeroing (temp is not used). 9978 __ bis_zeroing(to, count, G0, Ldone); 9979 __ bind(Ldone); 9980 9981 %} 9982 ins_pipe(long_memory_op); 9983 %} 9984 9985 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ 9986 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); 9987 match(Set dummy (ClearArray cnt base)); 9988 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); 9989 ins_cost(300); 9990 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 9991 9992 ins_encode %{ 9993 9994 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 9995 Register to = $base$$Register; 9996 Register count = $cnt$$Register; 9997 Register temp = $tmp$$Register; 9998 9999 Label Ldone; 10000 __ nop(); // Separate short branches 10001 // Use BIS for zeroing 10002 __ bis_zeroing(to, count, temp, Ldone); 10003 __ bind(Ldone); 10004 10005 %} 10006 ins_pipe(long_memory_op); 10007 %} 10008 10009 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10010 o7RegI tmp, flagsReg ccr) %{ 10011 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 10012 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10013 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 10014 ins_cost(300); 10015 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 10016 ins_encode %{ 10017 __ string_compare($str1$$Register, $str2$$Register, 10018 $cnt1$$Register, $cnt2$$Register, 10019 $tmp$$Register, $tmp$$Register, 10020 $result$$Register, StrIntrinsicNode::LL); 10021 %} 10022 ins_pipe(long_memory_op); 10023 %} 10024 10025 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10026 o7RegI tmp, flagsReg ccr) %{ 10027 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU); 10028 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10029 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 10030 ins_cost(300); 10031 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 10032 ins_encode %{ 10033 __ string_compare($str1$$Register, $str2$$Register, 10034 $cnt1$$Register, $cnt2$$Register, 10035 $tmp$$Register, $tmp$$Register, 10036 $result$$Register, StrIntrinsicNode::UU); 10037 %} 10038 ins_pipe(long_memory_op); 10039 %} 10040 10041 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10042 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{ 10043 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 10044 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10045 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2); 10046 ins_cost(300); 10047 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %} 10048 ins_encode %{ 10049 __ string_compare($str1$$Register, $str2$$Register, 10050 $cnt1$$Register, $cnt2$$Register, 10051 $tmp1$$Register, $tmp2$$Register, 10052 $result$$Register, StrIntrinsicNode::LU); 10053 %} 10054 ins_pipe(long_memory_op); 10055 %} 10056 10057 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10058 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{ 10059 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 10060 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10061 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2); 10062 ins_cost(300); 10063 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %} 10064 ins_encode %{ 10065 __ string_compare($str2$$Register, $str1$$Register, 10066 $cnt2$$Register, $cnt1$$Register, 10067 $tmp1$$Register, $tmp2$$Register, 10068 $result$$Register, StrIntrinsicNode::UL); 10069 %} 10070 ins_pipe(long_memory_op); 10071 %} 10072 10073 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 10074 o7RegI tmp, flagsReg ccr) %{ 10075 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); 10076 match(Set result (StrEquals (Binary str1 str2) cnt)); 10077 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 10078 ins_cost(300); 10079 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %} 10080 ins_encode %{ 10081 __ array_equals(false, $str1$$Register, $str2$$Register, 10082 $cnt$$Register, $tmp$$Register, 10083 $result$$Register, true /* byte */); 10084 %} 10085 ins_pipe(long_memory_op); 10086 %} 10087 10088 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 10089 o7RegI tmp, flagsReg ccr) %{ 10090 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); 10091 match(Set result (StrEquals (Binary str1 str2) cnt)); 10092 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 10093 ins_cost(300); 10094 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %} 10095 ins_encode %{ 10096 __ array_equals(false, $str1$$Register, $str2$$Register, 10097 $cnt$$Register, $tmp$$Register, 10098 $result$$Register, false /* byte */); 10099 %} 10100 ins_pipe(long_memory_op); 10101 %} 10102 10103 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 10104 o7RegI tmp2, flagsReg ccr) %{ 10105 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 10106 match(Set result (AryEq ary1 ary2)); 10107 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 10108 ins_cost(300); 10109 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 10110 ins_encode %{ 10111 __ array_equals(true, $ary1$$Register, $ary2$$Register, 10112 $tmp1$$Register, $tmp2$$Register, 10113 $result$$Register, true /* byte */); 10114 %} 10115 ins_pipe(long_memory_op); 10116 %} 10117 10118 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 10119 o7RegI tmp2, flagsReg ccr) %{ 10120 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 10121 match(Set result (AryEq ary1 ary2)); 10122 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 10123 ins_cost(300); 10124 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 10125 ins_encode %{ 10126 __ array_equals(true, $ary1$$Register, $ary2$$Register, 10127 $tmp1$$Register, $tmp2$$Register, 10128 $result$$Register, false /* byte */); 10129 %} 10130 ins_pipe(long_memory_op); 10131 %} 10132 10133 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR, 10134 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L, 10135 flagsReg ccr) 10136 %{ 10137 match(Set resultR (HasNegatives pAryR iSizeR)); 10138 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr); 10139 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %} 10140 ins_encode %{ 10141 __ has_negatives($pAryR$$Register, $iSizeR$$Register, 10142 $resultR$$Register, 10143 $tmp1L$$Register, $tmp2L$$Register, 10144 $tmp3L$$Register, $tmp4L$$Register); 10145 %} 10146 ins_pipe(long_memory_op); 10147 %} 10148 10149 // char[] to byte[] compression 10150 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{ 10151 predicate(UseVIS < 3); 10152 match(Set result (StrCompressedCopy src (Binary dst len))); 10153 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10154 ins_cost(300); 10155 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %} 10156 ins_encode %{ 10157 Label Ldone; 10158 __ signx($len$$Register); 10159 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn); 10160 __ delayed()->mov($len$$Register, $result$$Register); // copy count 10161 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone); 10162 __ bind(Ldone); 10163 %} 10164 ins_pipe(long_memory_op); 10165 %} 10166 10167 // fast char[] to byte[] compression using VIS instructions 10168 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, 10169 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4, 10170 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{ 10171 predicate(UseVIS >= 3); 10172 match(Set result (StrCompressedCopy src (Binary dst len))); 10173 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10174 ins_cost(300); 10175 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %} 10176 ins_encode %{ 10177 Label Ldone; 10178 __ signx($len$$Register); 10179 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register, 10180 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, 10181 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone); 10182 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 10183 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone); 10184 __ bind(Ldone); 10185 %} 10186 ins_pipe(long_memory_op); 10187 %} 10188 10189 // byte[] to char[] inflation 10190 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len, 10191 iRegL tmp, flagsReg ccr) %{ 10192 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10193 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10194 ins_cost(300); 10195 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %} 10196 ins_encode %{ 10197 Label Ldone; 10198 __ signx($len$$Register); 10199 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 10200 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone); 10201 __ bind(Ldone); 10202 %} 10203 ins_pipe(long_memory_op); 10204 %} 10205 10206 // fast byte[] to char[] inflation using VIS instructions 10207 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len, 10208 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{ 10209 predicate(UseVIS >= 3); 10210 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10211 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10212 ins_cost(300); 10213 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %} 10214 ins_encode %{ 10215 Label Ldone; 10216 __ signx($len$$Register); 10217 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, 10218 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone); 10219 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 10220 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone); 10221 __ bind(Ldone); 10222 %} 10223 ins_pipe(long_memory_op); 10224 %} 10225 10226 10227 //---------- Zeros Count Instructions ------------------------------------------ 10228 10229 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ 10230 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10231 match(Set dst (CountLeadingZerosI src)); 10232 effect(TEMP dst, TEMP tmp, KILL cr); 10233 10234 // x |= (x >> 1); 10235 // x |= (x >> 2); 10236 // x |= (x >> 4); 10237 // x |= (x >> 8); 10238 // x |= (x >> 16); 10239 // return (WORDBITS - popc(x)); 10240 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 10241 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 10242 "OR $dst,$tmp,$dst\n\t" 10243 "SRL $dst,2,$tmp\n\t" 10244 "OR $dst,$tmp,$dst\n\t" 10245 "SRL $dst,4,$tmp\n\t" 10246 "OR $dst,$tmp,$dst\n\t" 10247 "SRL $dst,8,$tmp\n\t" 10248 "OR $dst,$tmp,$dst\n\t" 10249 "SRL $dst,16,$tmp\n\t" 10250 "OR $dst,$tmp,$dst\n\t" 10251 "POPC $dst,$dst\n\t" 10252 "MOV 32,$tmp\n\t" 10253 "SUB $tmp,$dst,$dst" %} 10254 ins_encode %{ 10255 Register Rdst = $dst$$Register; 10256 Register Rsrc = $src$$Register; 10257 Register Rtmp = $tmp$$Register; 10258 __ srl(Rsrc, 1, Rtmp); 10259 __ srl(Rsrc, 0, Rdst); 10260 __ or3(Rdst, Rtmp, Rdst); 10261 __ srl(Rdst, 2, Rtmp); 10262 __ or3(Rdst, Rtmp, Rdst); 10263 __ srl(Rdst, 4, Rtmp); 10264 __ or3(Rdst, Rtmp, Rdst); 10265 __ srl(Rdst, 8, Rtmp); 10266 __ or3(Rdst, Rtmp, Rdst); 10267 __ srl(Rdst, 16, Rtmp); 10268 __ or3(Rdst, Rtmp, Rdst); 10269 __ popc(Rdst, Rdst); 10270 __ mov(BitsPerInt, Rtmp); 10271 __ sub(Rtmp, Rdst, Rdst); 10272 %} 10273 ins_pipe(ialu_reg); 10274 %} 10275 10276 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ 10277 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10278 match(Set dst (CountLeadingZerosL src)); 10279 effect(TEMP dst, TEMP tmp, KILL cr); 10280 10281 // x |= (x >> 1); 10282 // x |= (x >> 2); 10283 // x |= (x >> 4); 10284 // x |= (x >> 8); 10285 // x |= (x >> 16); 10286 // x |= (x >> 32); 10287 // return (WORDBITS - popc(x)); 10288 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 10289 "OR $src,$tmp,$dst\n\t" 10290 "SRLX $dst,2,$tmp\n\t" 10291 "OR $dst,$tmp,$dst\n\t" 10292 "SRLX $dst,4,$tmp\n\t" 10293 "OR $dst,$tmp,$dst\n\t" 10294 "SRLX $dst,8,$tmp\n\t" 10295 "OR $dst,$tmp,$dst\n\t" 10296 "SRLX $dst,16,$tmp\n\t" 10297 "OR $dst,$tmp,$dst\n\t" 10298 "SRLX $dst,32,$tmp\n\t" 10299 "OR $dst,$tmp,$dst\n\t" 10300 "POPC $dst,$dst\n\t" 10301 "MOV 64,$tmp\n\t" 10302 "SUB $tmp,$dst,$dst" %} 10303 ins_encode %{ 10304 Register Rdst = $dst$$Register; 10305 Register Rsrc = $src$$Register; 10306 Register Rtmp = $tmp$$Register; 10307 __ srlx(Rsrc, 1, Rtmp); 10308 __ or3( Rsrc, Rtmp, Rdst); 10309 __ srlx(Rdst, 2, Rtmp); 10310 __ or3( Rdst, Rtmp, Rdst); 10311 __ srlx(Rdst, 4, Rtmp); 10312 __ or3( Rdst, Rtmp, Rdst); 10313 __ srlx(Rdst, 8, Rtmp); 10314 __ or3( Rdst, Rtmp, Rdst); 10315 __ srlx(Rdst, 16, Rtmp); 10316 __ or3( Rdst, Rtmp, Rdst); 10317 __ srlx(Rdst, 32, Rtmp); 10318 __ or3( Rdst, Rtmp, Rdst); 10319 __ popc(Rdst, Rdst); 10320 __ mov(BitsPerLong, Rtmp); 10321 __ sub(Rtmp, Rdst, Rdst); 10322 %} 10323 ins_pipe(ialu_reg); 10324 %} 10325 10326 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ 10327 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10328 match(Set dst (CountTrailingZerosI src)); 10329 effect(TEMP dst, KILL cr); 10330 10331 // return popc(~x & (x - 1)); 10332 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 10333 "ANDN $dst,$src,$dst\n\t" 10334 "SRL $dst,R_G0,$dst\n\t" 10335 "POPC $dst,$dst" %} 10336 ins_encode %{ 10337 Register Rdst = $dst$$Register; 10338 Register Rsrc = $src$$Register; 10339 __ sub(Rsrc, 1, Rdst); 10340 __ andn(Rdst, Rsrc, Rdst); 10341 __ srl(Rdst, G0, Rdst); 10342 __ popc(Rdst, Rdst); 10343 %} 10344 ins_pipe(ialu_reg); 10345 %} 10346 10347 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ 10348 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10349 match(Set dst (CountTrailingZerosL src)); 10350 effect(TEMP dst, KILL cr); 10351 10352 // return popc(~x & (x - 1)); 10353 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 10354 "ANDN $dst,$src,$dst\n\t" 10355 "POPC $dst,$dst" %} 10356 ins_encode %{ 10357 Register Rdst = $dst$$Register; 10358 Register Rsrc = $src$$Register; 10359 __ sub(Rsrc, 1, Rdst); 10360 __ andn(Rdst, Rsrc, Rdst); 10361 __ popc(Rdst, Rdst); 10362 %} 10363 ins_pipe(ialu_reg); 10364 %} 10365 10366 10367 //---------- Population Count Instructions ------------------------------------- 10368 10369 instruct popCountI(iRegIsafe dst, iRegI src) %{ 10370 predicate(UsePopCountInstruction); 10371 match(Set dst (PopCountI src)); 10372 10373 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" 10374 "POPC $dst, $dst" %} 10375 ins_encode %{ 10376 __ srl($src$$Register, G0, $dst$$Register); 10377 __ popc($dst$$Register, $dst$$Register); 10378 %} 10379 ins_pipe(ialu_reg); 10380 %} 10381 10382 // Note: Long.bitCount(long) returns an int. 10383 instruct popCountL(iRegIsafe dst, iRegL src) %{ 10384 predicate(UsePopCountInstruction); 10385 match(Set dst (PopCountL src)); 10386 10387 format %{ "POPC $src, $dst" %} 10388 ins_encode %{ 10389 __ popc($src$$Register, $dst$$Register); 10390 %} 10391 ins_pipe(ialu_reg); 10392 %} 10393 10394 10395 // ============================================================================ 10396 //------------Bytes reverse-------------------------------------------------- 10397 10398 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 10399 match(Set dst (ReverseBytesI src)); 10400 10401 // Op cost is artificially doubled to make sure that load or store 10402 // instructions are preferred over this one which requires a spill 10403 // onto a stack slot. 10404 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10405 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10406 10407 ins_encode %{ 10408 __ set($src$$disp + STACK_BIAS, O7); 10409 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10410 %} 10411 ins_pipe( iload_mem ); 10412 %} 10413 10414 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 10415 match(Set dst (ReverseBytesL src)); 10416 10417 // Op cost is artificially doubled to make sure that load or store 10418 // instructions are preferred over this one which requires a spill 10419 // onto a stack slot. 10420 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10421 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10422 10423 ins_encode %{ 10424 __ set($src$$disp + STACK_BIAS, O7); 10425 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10426 %} 10427 ins_pipe( iload_mem ); 10428 %} 10429 10430 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 10431 match(Set dst (ReverseBytesUS src)); 10432 10433 // Op cost is artificially doubled to make sure that load or store 10434 // instructions are preferred over this one which requires a spill 10435 // onto a stack slot. 10436 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10437 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 10438 10439 ins_encode %{ 10440 // the value was spilled as an int so bias the load 10441 __ set($src$$disp + STACK_BIAS + 2, O7); 10442 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10443 %} 10444 ins_pipe( iload_mem ); 10445 %} 10446 10447 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 10448 match(Set dst (ReverseBytesS src)); 10449 10450 // Op cost is artificially doubled to make sure that load or store 10451 // instructions are preferred over this one which requires a spill 10452 // onto a stack slot. 10453 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10454 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 10455 10456 ins_encode %{ 10457 // the value was spilled as an int so bias the load 10458 __ set($src$$disp + STACK_BIAS + 2, O7); 10459 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10460 %} 10461 ins_pipe( iload_mem ); 10462 %} 10463 10464 // Load Integer reversed byte order 10465 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 10466 match(Set dst (ReverseBytesI (LoadI src))); 10467 10468 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10469 size(4); 10470 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10471 10472 ins_encode %{ 10473 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10474 %} 10475 ins_pipe(iload_mem); 10476 %} 10477 10478 // Load Long - aligned and reversed 10479 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 10480 match(Set dst (ReverseBytesL (LoadL src))); 10481 10482 ins_cost(MEMORY_REF_COST); 10483 size(4); 10484 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10485 10486 ins_encode %{ 10487 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10488 %} 10489 ins_pipe(iload_mem); 10490 %} 10491 10492 // Load unsigned short / char reversed byte order 10493 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 10494 match(Set dst (ReverseBytesUS (LoadUS src))); 10495 10496 ins_cost(MEMORY_REF_COST); 10497 size(4); 10498 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 10499 10500 ins_encode %{ 10501 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10502 %} 10503 ins_pipe(iload_mem); 10504 %} 10505 10506 // Load short reversed byte order 10507 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 10508 match(Set dst (ReverseBytesS (LoadS src))); 10509 10510 ins_cost(MEMORY_REF_COST); 10511 size(4); 10512 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 10513 10514 ins_encode %{ 10515 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10516 %} 10517 ins_pipe(iload_mem); 10518 %} 10519 10520 // Store Integer reversed byte order 10521 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 10522 match(Set dst (StoreI dst (ReverseBytesI src))); 10523 10524 ins_cost(MEMORY_REF_COST); 10525 size(4); 10526 format %{ "STWA $src, $dst\t!asi=primary_little" %} 10527 10528 ins_encode %{ 10529 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10530 %} 10531 ins_pipe(istore_mem_reg); 10532 %} 10533 10534 // Store Long reversed byte order 10535 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 10536 match(Set dst (StoreL dst (ReverseBytesL src))); 10537 10538 ins_cost(MEMORY_REF_COST); 10539 size(4); 10540 format %{ "STXA $src, $dst\t!asi=primary_little" %} 10541 10542 ins_encode %{ 10543 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10544 %} 10545 ins_pipe(istore_mem_reg); 10546 %} 10547 10548 // Store unsighed short/char reversed byte order 10549 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 10550 match(Set dst (StoreC dst (ReverseBytesUS src))); 10551 10552 ins_cost(MEMORY_REF_COST); 10553 size(4); 10554 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10555 10556 ins_encode %{ 10557 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10558 %} 10559 ins_pipe(istore_mem_reg); 10560 %} 10561 10562 // Store short reversed byte order 10563 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 10564 match(Set dst (StoreC dst (ReverseBytesS src))); 10565 10566 ins_cost(MEMORY_REF_COST); 10567 size(4); 10568 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10569 10570 ins_encode %{ 10571 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10572 %} 10573 ins_pipe(istore_mem_reg); 10574 %} 10575 10576 // ====================VECTOR INSTRUCTIONS===================================== 10577 10578 // Load Aligned Packed values into a Double Register 10579 instruct loadV8(regD dst, memory mem) %{ 10580 predicate(n->as_LoadVector()->memory_size() == 8); 10581 match(Set dst (LoadVector mem)); 10582 ins_cost(MEMORY_REF_COST); 10583 size(4); 10584 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} 10585 ins_encode %{ 10586 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); 10587 %} 10588 ins_pipe(floadD_mem); 10589 %} 10590 10591 // Store Vector in Double register to memory 10592 instruct storeV8(memory mem, regD src) %{ 10593 predicate(n->as_StoreVector()->memory_size() == 8); 10594 match(Set mem (StoreVector mem src)); 10595 ins_cost(MEMORY_REF_COST); 10596 size(4); 10597 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} 10598 ins_encode %{ 10599 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); 10600 %} 10601 ins_pipe(fstoreD_mem_reg); 10602 %} 10603 10604 // Store Zero into vector in memory 10605 instruct storeV8B_zero(memory mem, immI0 zero) %{ 10606 predicate(n->as_StoreVector()->memory_size() == 8); 10607 match(Set mem (StoreVector mem (ReplicateB zero))); 10608 ins_cost(MEMORY_REF_COST); 10609 size(4); 10610 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} 10611 ins_encode %{ 10612 __ stx(G0, $mem$$Address); 10613 %} 10614 ins_pipe(fstoreD_mem_zero); 10615 %} 10616 10617 instruct storeV4S_zero(memory mem, immI0 zero) %{ 10618 predicate(n->as_StoreVector()->memory_size() == 8); 10619 match(Set mem (StoreVector mem (ReplicateS zero))); 10620 ins_cost(MEMORY_REF_COST); 10621 size(4); 10622 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} 10623 ins_encode %{ 10624 __ stx(G0, $mem$$Address); 10625 %} 10626 ins_pipe(fstoreD_mem_zero); 10627 %} 10628 10629 instruct storeV2I_zero(memory mem, immI0 zero) %{ 10630 predicate(n->as_StoreVector()->memory_size() == 8); 10631 match(Set mem (StoreVector mem (ReplicateI zero))); 10632 ins_cost(MEMORY_REF_COST); 10633 size(4); 10634 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} 10635 ins_encode %{ 10636 __ stx(G0, $mem$$Address); 10637 %} 10638 ins_pipe(fstoreD_mem_zero); 10639 %} 10640 10641 instruct storeV2F_zero(memory mem, immF0 zero) %{ 10642 predicate(n->as_StoreVector()->memory_size() == 8); 10643 match(Set mem (StoreVector mem (ReplicateF zero))); 10644 ins_cost(MEMORY_REF_COST); 10645 size(4); 10646 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} 10647 ins_encode %{ 10648 __ stx(G0, $mem$$Address); 10649 %} 10650 ins_pipe(fstoreD_mem_zero); 10651 %} 10652 10653 // Replicate scalar to packed byte values into Double register 10654 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10655 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); 10656 match(Set dst (ReplicateB src)); 10657 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10658 format %{ "SLLX $src,56,$tmp\n\t" 10659 "SRLX $tmp, 8,$tmp2\n\t" 10660 "OR $tmp,$tmp2,$tmp\n\t" 10661 "SRLX $tmp,16,$tmp2\n\t" 10662 "OR $tmp,$tmp2,$tmp\n\t" 10663 "SRLX $tmp,32,$tmp2\n\t" 10664 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10665 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10666 ins_encode %{ 10667 Register Rsrc = $src$$Register; 10668 Register Rtmp = $tmp$$Register; 10669 Register Rtmp2 = $tmp2$$Register; 10670 __ sllx(Rsrc, 56, Rtmp); 10671 __ srlx(Rtmp, 8, Rtmp2); 10672 __ or3 (Rtmp, Rtmp2, Rtmp); 10673 __ srlx(Rtmp, 16, Rtmp2); 10674 __ or3 (Rtmp, Rtmp2, Rtmp); 10675 __ srlx(Rtmp, 32, Rtmp2); 10676 __ or3 (Rtmp, Rtmp2, Rtmp); 10677 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10678 %} 10679 ins_pipe(ialu_reg); 10680 %} 10681 10682 // Replicate scalar to packed byte values into Double stack 10683 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10684 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); 10685 match(Set dst (ReplicateB src)); 10686 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10687 format %{ "SLLX $src,56,$tmp\n\t" 10688 "SRLX $tmp, 8,$tmp2\n\t" 10689 "OR $tmp,$tmp2,$tmp\n\t" 10690 "SRLX $tmp,16,$tmp2\n\t" 10691 "OR $tmp,$tmp2,$tmp\n\t" 10692 "SRLX $tmp,32,$tmp2\n\t" 10693 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10694 "STX $tmp,$dst\t! regL to stkD" %} 10695 ins_encode %{ 10696 Register Rsrc = $src$$Register; 10697 Register Rtmp = $tmp$$Register; 10698 Register Rtmp2 = $tmp2$$Register; 10699 __ sllx(Rsrc, 56, Rtmp); 10700 __ srlx(Rtmp, 8, Rtmp2); 10701 __ or3 (Rtmp, Rtmp2, Rtmp); 10702 __ srlx(Rtmp, 16, Rtmp2); 10703 __ or3 (Rtmp, Rtmp2, Rtmp); 10704 __ srlx(Rtmp, 32, Rtmp2); 10705 __ or3 (Rtmp, Rtmp2, Rtmp); 10706 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10707 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10708 %} 10709 ins_pipe(ialu_reg); 10710 %} 10711 10712 // Replicate scalar constant to packed byte values in Double register 10713 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ 10714 predicate(n->as_Vector()->length() == 8); 10715 match(Set dst (ReplicateB con)); 10716 effect(KILL tmp); 10717 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} 10718 ins_encode %{ 10719 // XXX This is a quick fix for 6833573. 10720 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); 10721 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); 10722 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10723 %} 10724 ins_pipe(loadConFD); 10725 %} 10726 10727 // Replicate scalar to packed char/short values into Double register 10728 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10729 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); 10730 match(Set dst (ReplicateS src)); 10731 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10732 format %{ "SLLX $src,48,$tmp\n\t" 10733 "SRLX $tmp,16,$tmp2\n\t" 10734 "OR $tmp,$tmp2,$tmp\n\t" 10735 "SRLX $tmp,32,$tmp2\n\t" 10736 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10737 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10738 ins_encode %{ 10739 Register Rsrc = $src$$Register; 10740 Register Rtmp = $tmp$$Register; 10741 Register Rtmp2 = $tmp2$$Register; 10742 __ sllx(Rsrc, 48, Rtmp); 10743 __ srlx(Rtmp, 16, Rtmp2); 10744 __ or3 (Rtmp, Rtmp2, Rtmp); 10745 __ srlx(Rtmp, 32, Rtmp2); 10746 __ or3 (Rtmp, Rtmp2, Rtmp); 10747 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10748 %} 10749 ins_pipe(ialu_reg); 10750 %} 10751 10752 // Replicate scalar to packed char/short values into Double stack 10753 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10754 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); 10755 match(Set dst (ReplicateS src)); 10756 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10757 format %{ "SLLX $src,48,$tmp\n\t" 10758 "SRLX $tmp,16,$tmp2\n\t" 10759 "OR $tmp,$tmp2,$tmp\n\t" 10760 "SRLX $tmp,32,$tmp2\n\t" 10761 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10762 "STX $tmp,$dst\t! regL to stkD" %} 10763 ins_encode %{ 10764 Register Rsrc = $src$$Register; 10765 Register Rtmp = $tmp$$Register; 10766 Register Rtmp2 = $tmp2$$Register; 10767 __ sllx(Rsrc, 48, Rtmp); 10768 __ srlx(Rtmp, 16, Rtmp2); 10769 __ or3 (Rtmp, Rtmp2, Rtmp); 10770 __ srlx(Rtmp, 32, Rtmp2); 10771 __ or3 (Rtmp, Rtmp2, Rtmp); 10772 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10773 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10774 %} 10775 ins_pipe(ialu_reg); 10776 %} 10777 10778 // Replicate scalar constant to packed char/short values in Double register 10779 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ 10780 predicate(n->as_Vector()->length() == 4); 10781 match(Set dst (ReplicateS con)); 10782 effect(KILL tmp); 10783 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} 10784 ins_encode %{ 10785 // XXX This is a quick fix for 6833573. 10786 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 10787 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); 10788 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10789 %} 10790 ins_pipe(loadConFD); 10791 %} 10792 10793 // Replicate scalar to packed int values into Double register 10794 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10795 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); 10796 match(Set dst (ReplicateI src)); 10797 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10798 format %{ "SLLX $src,32,$tmp\n\t" 10799 "SRLX $tmp,32,$tmp2\n\t" 10800 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10801 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10802 ins_encode %{ 10803 Register Rsrc = $src$$Register; 10804 Register Rtmp = $tmp$$Register; 10805 Register Rtmp2 = $tmp2$$Register; 10806 __ sllx(Rsrc, 32, Rtmp); 10807 __ srlx(Rtmp, 32, Rtmp2); 10808 __ or3 (Rtmp, Rtmp2, Rtmp); 10809 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10810 %} 10811 ins_pipe(ialu_reg); 10812 %} 10813 10814 // Replicate scalar to packed int values into Double stack 10815 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10816 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); 10817 match(Set dst (ReplicateI src)); 10818 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10819 format %{ "SLLX $src,32,$tmp\n\t" 10820 "SRLX $tmp,32,$tmp2\n\t" 10821 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10822 "STX $tmp,$dst\t! regL to stkD" %} 10823 ins_encode %{ 10824 Register Rsrc = $src$$Register; 10825 Register Rtmp = $tmp$$Register; 10826 Register Rtmp2 = $tmp2$$Register; 10827 __ sllx(Rsrc, 32, Rtmp); 10828 __ srlx(Rtmp, 32, Rtmp2); 10829 __ or3 (Rtmp, Rtmp2, Rtmp); 10830 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10831 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10832 %} 10833 ins_pipe(ialu_reg); 10834 %} 10835 10836 // Replicate scalar zero constant to packed int values in Double register 10837 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ 10838 predicate(n->as_Vector()->length() == 2); 10839 match(Set dst (ReplicateI con)); 10840 effect(KILL tmp); 10841 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} 10842 ins_encode %{ 10843 // XXX This is a quick fix for 6833573. 10844 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); 10845 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); 10846 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10847 %} 10848 ins_pipe(loadConFD); 10849 %} 10850 10851 // Replicate scalar to packed float values into Double stack 10852 instruct Repl2F_stk(stackSlotD dst, regF src) %{ 10853 predicate(n->as_Vector()->length() == 2); 10854 match(Set dst (ReplicateF src)); 10855 ins_cost(MEMORY_REF_COST*2); 10856 format %{ "STF $src,$dst.hi\t! packed2F\n\t" 10857 "STF $src,$dst.lo" %} 10858 opcode(Assembler::stf_op3); 10859 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); 10860 ins_pipe(fstoreF_stk_reg); 10861 %} 10862 10863 // Replicate scalar zero constant to packed float values in Double register 10864 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ 10865 predicate(n->as_Vector()->length() == 2); 10866 match(Set dst (ReplicateF con)); 10867 effect(KILL tmp); 10868 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} 10869 ins_encode %{ 10870 // XXX This is a quick fix for 6833573. 10871 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); 10872 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); 10873 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10874 %} 10875 ins_pipe(loadConFD); 10876 %} 10877 10878 //----------PEEPHOLE RULES----------------------------------------------------- 10879 // These must follow all instruction definitions as they use the names 10880 // defined in the instructions definitions. 10881 // 10882 // peepmatch ( root_instr_name [preceding_instruction]* ); 10883 // 10884 // peepconstraint %{ 10885 // (instruction_number.operand_name relational_op instruction_number.operand_name 10886 // [, ...] ); 10887 // // instruction numbers are zero-based using left to right order in peepmatch 10888 // 10889 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 10890 // // provide an instruction_number.operand_name for each operand that appears 10891 // // in the replacement instruction's match rule 10892 // 10893 // ---------VM FLAGS--------------------------------------------------------- 10894 // 10895 // All peephole optimizations can be turned off using -XX:-OptoPeephole 10896 // 10897 // Each peephole rule is given an identifying number starting with zero and 10898 // increasing by one in the order seen by the parser. An individual peephole 10899 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10900 // on the command-line. 10901 // 10902 // ---------CURRENT LIMITATIONS---------------------------------------------- 10903 // 10904 // Only match adjacent instructions in same basic block 10905 // Only equality constraints 10906 // Only constraints between operands, not (0.dest_reg == EAX_enc) 10907 // Only one replacement instruction 10908 // 10909 // ---------EXAMPLE---------------------------------------------------------- 10910 // 10911 // // pertinent parts of existing instructions in architecture description 10912 // instruct movI(eRegI dst, eRegI src) %{ 10913 // match(Set dst (CopyI src)); 10914 // %} 10915 // 10916 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10917 // match(Set dst (AddI dst src)); 10918 // effect(KILL cr); 10919 // %} 10920 // 10921 // // Change (inc mov) to lea 10922 // peephole %{ 10923 // // increment preceeded by register-register move 10924 // peepmatch ( incI_eReg movI ); 10925 // // require that the destination register of the increment 10926 // // match the destination register of the move 10927 // peepconstraint ( 0.dst == 1.dst ); 10928 // // construct a replacement instruction that sets 10929 // // the destination to ( move's source register + one ) 10930 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 10931 // %} 10932 // 10933 10934 // // Change load of spilled value to only a spill 10935 // instruct storeI(memory mem, eRegI src) %{ 10936 // match(Set mem (StoreI mem src)); 10937 // %} 10938 // 10939 // instruct loadI(eRegI dst, memory mem) %{ 10940 // match(Set dst (LoadI mem)); 10941 // %} 10942 // 10943 // peephole %{ 10944 // peepmatch ( loadI storeI ); 10945 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 10946 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 10947 // %} 10948 10949 //----------SMARTSPILL RULES--------------------------------------------------- 10950 // These must follow all instruction definitions as they use the names 10951 // defined in the instructions definitions. 10952 // 10953 // SPARC will probably not have any of these rules due to RISC instruction set. 10954 10955 //----------PIPELINE----------------------------------------------------------- 10956 // Rules which define the behavior of the target architectures pipeline.