1 //
2 // Copyright (c) 2017, 2019, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2017, 2019 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24
25 // z/Architecture Architecture Description File
26
27 // Major contributions by AS, JL, LS.
28
29 //
30 // Following information is derived from private mail communication
31 // (Oct. 2011).
32 //
33 // General branch target alignment considerations
34 //
35 // z/Architecture does not imply a general branch target alignment requirement.
36 // There are side effects and side considerations, though, which may
37 // provide some performance benefit. These are:
38 // - Align branch target on octoword (32-byte) boundary
39 // On more recent models (from z9 on), I-fetch is done on a Octoword
40 // (32 bytes at a time) basis. To avoid I-fetching unnecessary
41 // instructions, branch targets should be 32-byte aligend. If this
42 // exact alingment cannot be achieved, having the branch target in
43 // the first doubleword still provides some benefit.
44 // - Avoid branch targets at the end of cache lines (> 64 bytes distance).
45 // Sequential instruction prefetching after the branch target starts
46 // immediately after having fetched the octoword containing the
47 // branch target. When I-fetching crosses a cache line, there may be
48 // a small stall. The worst case: the branch target (at the end of
49 // a cache line) is a L1 I-cache miss and the next line as well.
50 // Then, the entire target line must be filled first (to contine at the
51 // branch target). Only then can the next sequential line be filled.
52 // - Avoid multiple poorly predicted branches in a row.
53 //
54
55 //----------REGISTER DEFINITION BLOCK------------------------------------------
56 // This information is used by the matcher and the register allocator to
57 // describe individual registers and classes of registers within the target
58 // architecture.
59
60 register %{
61
62 //----------Architecture Description Register Definitions----------------------
63 // General Registers
64 // "reg_def" name (register save type, C convention save type,
65 // ideal register type, encoding);
66 //
67 // Register Save Types:
68 //
69 // NS = No-Save: The register allocator assumes that these registers
70 // can be used without saving upon entry to the method, &
71 // that they do not need to be saved at call sites.
72 //
73 // SOC = Save-On-Call: The register allocator assumes that these registers
74 // can be used without saving upon entry to the method,
75 // but that they must be saved at call sites.
76 //
77 // SOE = Save-On-Entry: The register allocator assumes that these registers
78 // must be saved before using them upon entry to the
79 // method, but they do not need to be saved at call sites.
80 //
81 // AS = Always-Save: The register allocator assumes that these registers
82 // must be saved before using them upon entry to the
83 // method, & that they must be saved at call sites.
84 //
85 // Ideal Register Type is used to determine how to save & restore a
86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
88 //
89 // The encoding number is the actual bit-pattern placed into the opcodes.
90
91 // z/Architecture register definitions, based on the z/Architecture Principles
92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
93 // 5th Edition, March 2001.
94 //
95 // For each 64-bit register we must define two registers: the register
96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
98 // for stores, loads, etc.
99
100 // Integer/Long Registers
101 // ----------------------------
102
103 // z/Architecture has 16 64-bit integer registers.
104
105 // types: v = volatile, nv = non-volatile, s = system
106 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1
107 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
108 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2
109 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
110 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret
111 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
112 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2
113 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
114 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3
115 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
116 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4
117 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
118 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5
119 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
120 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg());
121 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
122 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg());
123 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
124 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg());
125 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
126 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
127 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
128 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
129 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
130 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
131 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
132 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
133 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
134 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc
135 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next());
136 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP
137 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next());
138
139 // Float/Double Registers
140
141 // The rules of ADL require that double registers be defined in pairs.
142 // Each pair must be two 32-bit values, but not necessarily a pair of
143 // single float registers. In each pair, ADLC-assigned register numbers
144 // must be adjacent, with the lower number even. Finally, when the
145 // CPU stores such a register pair to memory, the word associated with
146 // the lower ADLC-assigned number must be stored to the lower address.
147
148 // z/Architecture has 16 64-bit floating-point registers. Each can store a single
149 // or double precision floating-point value.
150
151 // types: v = volatile, nv = non-volatile, s = system
152 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret
153 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
154 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg());
155 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
156 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2
157 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
158 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg());
159 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
160 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3
161 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
162 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg());
163 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
164 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg());
165 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
166 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg());
167 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
168 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg());
169 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
170 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg());
171 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
172 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
173 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
174 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
175 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
176 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
177 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
178 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
179 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
180 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
181 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
182 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
183 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
184
185
186 // Special Registers
187
188 // Condition Codes Flag Registers
189
190 // z/Architecture has the PSW (program status word) that contains
191 // (among other information) the condition code. We treat this
192 // part of the PSW as a condition register CR. It consists of 4
193 // bits. Floating point instructions influence the same condition register CR.
194
195 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile
196
197
198 // Specify priority of register selection within phases of register
199 // allocation. Highest priority is first. A useful heuristic is to
200 // give registers a low priority when they are required by machine
201 // instructions, and choose no-save registers before save-on-call, and
202 // save-on-call before save-on-entry. Registers which participate in
203 // fix calling sequences should come last. Registers which are used
204 // as pairs must fall on an even boundary.
205
206 // It's worth about 1% on SPEC geomean to get this right.
207
208 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
209 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
210 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
211 // the same as Z_R3->encoding()! Furthermore, we cannot make any
212 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
213 // Additionally, the function
214 // static enum RC rc_class(OptoReg::Name reg)
215 // maps a given <register>_num value to its chunk type (except for flags)
216 // and its current implementation relies on chunk0 and chunk1 having a
217 // size of 64 each.
218
219 alloc_class chunk0(
220 // chunk0 contains *all* 32 integer registers halves.
221
222 // potential SOE regs
223 Z_R13,Z_R13_H,
224 Z_R12,Z_R12_H,
225 Z_R11,Z_R11_H,
226 Z_R10,Z_R10_H,
227
228 Z_R9,Z_R9_H,
229 Z_R8,Z_R8_H,
230 Z_R7,Z_R7_H,
231
232 Z_R1,Z_R1_H,
233 Z_R0,Z_R0_H,
234
235 // argument registers
236 Z_R6,Z_R6_H,
237 Z_R5,Z_R5_H,
238 Z_R4,Z_R4_H,
239 Z_R3,Z_R3_H,
240 Z_R2,Z_R2_H,
241
242 // special registers
243 Z_R14,Z_R14_H,
244 Z_R15,Z_R15_H
245 );
246
247 alloc_class chunk1(
248 // Chunk1 contains *all* 64 floating-point registers halves.
249
250 Z_F15,Z_F15_H,
251 Z_F14,Z_F14_H,
252 Z_F13,Z_F13_H,
253 Z_F12,Z_F12_H,
254 Z_F11,Z_F11_H,
255 Z_F10,Z_F10_H,
256 Z_F9,Z_F9_H,
257 Z_F8,Z_F8_H,
258 // scratch register
259 Z_F7,Z_F7_H,
260 Z_F5,Z_F5_H,
261 Z_F3,Z_F3_H,
262 Z_F1,Z_F1_H,
263 // argument registers
264 Z_F6,Z_F6_H,
265 Z_F4,Z_F4_H,
266 Z_F2,Z_F2_H,
267 Z_F0,Z_F0_H
268 );
269
270 alloc_class chunk2(
271 Z_CR
272 );
273
274
275 //-------Architecture Description Register Classes-----------------------
276
277 // Several register classes are automatically defined based upon
278 // information in this architecture description.
279
280 // 1) reg_class inline_cache_reg (as defined in frame section)
281 // 2) reg_class compiler_method_oop_reg (as defined in frame section)
282 // 2) reg_class interpreter_method_oop_reg (as defined in frame section)
283 // 3) reg_class stack_slots(/* one chunk of stack-based "registers" */)
284
285 // Integer Register Classes
286 reg_class z_int_reg(
287 /*Z_R0*/ // R0
288 /*Z_R1*/
289 Z_R2,
290 Z_R3,
291 Z_R4,
292 Z_R5,
293 Z_R6,
294 Z_R7,
295 /*Z_R8,*/ // Z_thread
296 Z_R9,
297 Z_R10,
298 Z_R11,
299 Z_R12,
300 Z_R13
301 /*Z_R14*/ // return_pc
302 /*Z_R15*/ // SP
303 );
304
305 reg_class z_no_odd_int_reg(
306 /*Z_R0*/ // R0
307 /*Z_R1*/
308 Z_R2,
309 Z_R3,
310 Z_R4,
311 /*Z_R5,*/ // odd part of fix register pair
312 Z_R6,
313 Z_R7,
314 /*Z_R8,*/ // Z_thread
315 Z_R9,
316 Z_R10,
317 Z_R11,
318 Z_R12,
319 Z_R13
320 /*Z_R14*/ // return_pc
321 /*Z_R15*/ // SP
322 );
323
324 reg_class z_no_arg_int_reg(
325 /*Z_R0*/ // R0
326 /*Z_R1*/ // scratch
327 /*Z_R2*/
328 /*Z_R3*/
329 /*Z_R4*/
330 /*Z_R5*/
331 /*Z_R6*/
332 Z_R7,
333 /*Z_R8*/ // Z_thread
334 Z_R9,
335 Z_R10,
336 Z_R11,
337 Z_R12,
338 Z_R13
339 /*Z_R14*/ // return_pc
340 /*Z_R15*/ // SP
341 );
342
343 reg_class z_rarg1_int_reg(Z_R2);
344 reg_class z_rarg2_int_reg(Z_R3);
345 reg_class z_rarg3_int_reg(Z_R4);
346 reg_class z_rarg4_int_reg(Z_R5);
347 reg_class z_rarg5_int_reg(Z_R6);
348
349 // Pointer Register Classes
350
351 // 64-bit build means 64-bit pointers means hi/lo pairs.
352
353 reg_class z_rarg5_ptrN_reg(Z_R6);
354
355 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
356 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
357 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
358 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
359 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
360 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
361
362 reg_class z_ptr_reg(
363 /*Z_R0_H,Z_R0*/ // R0
364 /*Z_R1_H,Z_R1*/
365 Z_R2_H,Z_R2,
366 Z_R3_H,Z_R3,
367 Z_R4_H,Z_R4,
368 Z_R5_H,Z_R5,
369 Z_R6_H,Z_R6,
370 Z_R7_H,Z_R7,
371 /*Z_R8_H,Z_R8,*/ // Z_thread
372 Z_R9_H,Z_R9,
373 Z_R10_H,Z_R10,
374 Z_R11_H,Z_R11,
375 Z_R12_H,Z_R12,
376 Z_R13_H,Z_R13
377 /*Z_R14_H,Z_R14*/ // return_pc
378 /*Z_R15_H,Z_R15*/ // SP
379 );
380
381 reg_class z_lock_ptr_reg(
382 /*Z_R0_H,Z_R0*/ // R0
383 /*Z_R1_H,Z_R1*/
384 Z_R2_H,Z_R2,
385 Z_R3_H,Z_R3,
386 Z_R4_H,Z_R4,
387 /*Z_R5_H,Z_R5,*/
388 /*Z_R6_H,Z_R6,*/
389 Z_R7_H,Z_R7,
390 /*Z_R8_H,Z_R8,*/ // Z_thread
391 Z_R9_H,Z_R9,
392 Z_R10_H,Z_R10,
393 Z_R11_H,Z_R11,
394 Z_R12_H,Z_R12,
395 Z_R13_H,Z_R13
396 /*Z_R14_H,Z_R14*/ // return_pc
397 /*Z_R15_H,Z_R15*/ // SP
398 );
399
400 reg_class z_no_arg_ptr_reg(
401 /*Z_R0_H,Z_R0*/ // R0
402 /*Z_R1_H,Z_R1*/ // scratch
403 /*Z_R2_H,Z_R2*/
404 /*Z_R3_H,Z_R3*/
405 /*Z_R4_H,Z_R4*/
406 /*Z_R5_H,Z_R5*/
407 /*Z_R6_H,Z_R6*/
408 Z_R7_H, Z_R7,
409 /*Z_R8_H,Z_R8*/ // Z_thread
410 Z_R9_H,Z_R9,
411 Z_R10_H,Z_R10,
412 Z_R11_H,Z_R11,
413 Z_R12_H,Z_R12,
414 Z_R13_H,Z_R13
415 /*Z_R14_H,Z_R14*/ // return_pc
416 /*Z_R15_H,Z_R15*/ // SP
417 );
418
419 // Special class for storeP instructions, which can store SP or RPC to
420 // TLS. (Note: Do not generalize this to "any_reg". If you add
421 // another register, such as FP, to this mask, the allocator may try
422 // to put a temp in it.)
423 // Register class for memory access base registers,
424 // This class is a superset of z_ptr_reg including Z_thread.
425 reg_class z_memory_ptr_reg(
426 /*Z_R0_H,Z_R0*/ // R0
427 /*Z_R1_H,Z_R1*/
428 Z_R2_H,Z_R2,
429 Z_R3_H,Z_R3,
430 Z_R4_H,Z_R4,
431 Z_R5_H,Z_R5,
432 Z_R6_H,Z_R6,
433 Z_R7_H,Z_R7,
434 Z_R8_H,Z_R8, // Z_thread
435 Z_R9_H,Z_R9,
436 Z_R10_H,Z_R10,
437 Z_R11_H,Z_R11,
438 Z_R12_H,Z_R12,
439 Z_R13_H,Z_R13
440 /*Z_R14_H,Z_R14*/ // return_pc
441 /*Z_R15_H,Z_R15*/ // SP
442 );
443
444 // Other special pointer regs.
445 reg_class z_r1_regP(Z_R1_H,Z_R1);
446 reg_class z_r9_regP(Z_R9_H,Z_R9);
447
448
449 // Long Register Classes
450
451 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
452 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
453 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
454 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
455 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
456
457 // Longs in 1 register. Aligned adjacent hi/lo pairs.
458 reg_class z_long_reg(
459 /*Z_R0_H,Z_R0*/ // R0
460 /*Z_R1_H,Z_R1*/
461 Z_R2_H,Z_R2,
462 Z_R3_H,Z_R3,
463 Z_R4_H,Z_R4,
464 Z_R5_H,Z_R5,
465 Z_R6_H,Z_R6,
466 Z_R7_H,Z_R7,
467 /*Z_R8_H,Z_R8,*/ // Z_thread
468 Z_R9_H,Z_R9,
469 Z_R10_H,Z_R10,
470 Z_R11_H,Z_R11,
471 Z_R12_H,Z_R12,
472 Z_R13_H,Z_R13
473 /*Z_R14_H,Z_R14,*/ // return_pc
474 /*Z_R15_H,Z_R15*/ // SP
475 );
476
477 // z_long_reg without even registers
478 reg_class z_long_odd_reg(
479 /*Z_R0_H,Z_R0*/ // R0
480 /*Z_R1_H,Z_R1*/
481 Z_R3_H,Z_R3,
482 Z_R5_H,Z_R5,
483 Z_R7_H,Z_R7,
484 Z_R9_H,Z_R9,
485 Z_R11_H,Z_R11,
486 Z_R13_H,Z_R13
487 /*Z_R14_H,Z_R14,*/ // return_pc
488 /*Z_R15_H,Z_R15*/ // SP
489 );
490
491 // Special Class for Condition Code Flags Register
492
493 reg_class z_condition_reg(
494 Z_CR
495 );
496
497 // Scratch register for late profiling. Callee saved.
498 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
499
500
501 // Float Register Classes
502
503 reg_class z_flt_reg(
504 Z_F0,
505 /*Z_F1,*/ // scratch
506 Z_F2,
507 Z_F3,
508 Z_F4,
509 Z_F5,
510 Z_F6,
511 Z_F7,
512 Z_F8,
513 Z_F9,
514 Z_F10,
515 Z_F11,
516 Z_F12,
517 Z_F13,
518 Z_F14,
519 Z_F15
520 );
521 reg_class z_rscratch1_flt_reg(Z_F1);
522
523 // Double precision float registers have virtual `high halves' that
524 // are needed by the allocator.
525 reg_class z_dbl_reg(
526 Z_F0,Z_F0_H,
527 /*Z_F1,Z_F1_H,*/ // scratch
528 Z_F2,Z_F2_H,
529 Z_F3,Z_F3_H,
530 Z_F4,Z_F4_H,
531 Z_F5,Z_F5_H,
532 Z_F6,Z_F6_H,
533 Z_F7,Z_F7_H,
534 Z_F8,Z_F8_H,
535 Z_F9,Z_F9_H,
536 Z_F10,Z_F10_H,
537 Z_F11,Z_F11_H,
538 Z_F12,Z_F12_H,
539 Z_F13,Z_F13_H,
540 Z_F14,Z_F14_H,
541 Z_F15,Z_F15_H
542 );
543 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
544
545 %}
546
547 //----------DEFINITION BLOCK---------------------------------------------------
548 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
549 // Current support includes integer values in the range [0, 0x7FFFFFFF].
550 // Format:
551 // int_def <name> (<int_value>, <expression>);
552 // Generated Code in ad_<arch>.hpp
553 // #define <name> (<expression>)
554 // // value == <int_value>
555 // Generated code in ad_<arch>.cpp adlc_verification()
556 // assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
557 //
558 definitions %{
559 // The default cost (of an ALU instruction).
560 int_def DEFAULT_COST ( 100, 100);
561 int_def DEFAULT_COST_LOW ( 80, 80);
562 int_def DEFAULT_COST_HIGH ( 120, 120);
563 int_def HUGE_COST (1000000, 1000000);
564
565 // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
566 int_def ALU_REG_COST ( 100, DEFAULT_COST);
567 int_def ALU_MEMORY_COST ( 150, 150);
568
569 // Memory refs are twice as expensive as run-of-the-mill.
570 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20);
571 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST);
572 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20);
573
574 // Branches are even more expensive.
575 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
576 int_def CALL_COST ( 300, DEFAULT_COST * 3);
577 %}
578
579 source %{
580
581 #ifdef PRODUCT
582 #define BLOCK_COMMENT(str)
583 #define BIND(label) __ bind(label)
584 #else
585 #define BLOCK_COMMENT(str) __ block_comment(str)
586 #define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":")
587 #endif
588
589 #define __ _masm.
590
591 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6
592 #define Z_DISP3_SIZE 6
593
594 // Tertiary op of a LoadP or StoreP encoding.
595 #define REGP_OP true
596
597 // Given a register encoding, produce an Integer Register object.
598 static Register reg_to_register_object(int register_encoding);
599
600 // ****************************************************************************
601
602 // REQUIRED FUNCTIONALITY
603
604 // !!!!! Special hack to get all type of calls to specify the byte offset
605 // from the start of the call to the point where the return address
606 // will point.
607
608 int MachCallStaticJavaNode::ret_addr_offset() {
609 if (_method) {
610 return 8;
611 } else {
612 return MacroAssembler::call_far_patchable_ret_addr_offset();
613 }
614 }
615
616 int MachCallDynamicJavaNode::ret_addr_offset() {
617 // Consider size of receiver type profiling (C2 tiers).
618 int profile_receiver_type_size = 0;
619
620 int vtable_index = this->_vtable_index;
621 if (vtable_index == -4) {
622 return 14 + profile_receiver_type_size;
623 } else {
624 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
625 return 36 + profile_receiver_type_size;
626 }
627 }
628
629 int MachCallRuntimeNode::ret_addr_offset() {
630 return 12 + MacroAssembler::call_far_patchable_ret_addr_offset();
631 }
632
633 // Compute padding required for nodes which need alignment
634 //
635 // The addresses of the call instructions needs to be 4-byte aligned to
636 // ensure that they don't span a cache line so that they are atomically patchable.
637 // The actual calls get emitted at different offsets within the node emitters.
638 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
639
640 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
641 return (0 - current_offset) & 2;
642 }
643
644 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
645 return (6 - current_offset) & 2;
646 }
647
648 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
649 return (12 - current_offset) & 2;
650 }
651
652 int CallLeafDirectNode::compute_padding(int current_offset) const {
653 return (12 - current_offset) & 2;
654 }
655
656 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
657 return (12 - current_offset) & 2;
658 }
659
660 // Indicate if the safepoint node needs the polling page as an input.
661 // Since z/Architecture does not have absolute addressing, it does.
662 bool SafePointNode::needs_polling_address_input() {
663 return true;
664 }
665
666 void emit_nop(CodeBuffer &cbuf) {
667 MacroAssembler _masm(&cbuf);
668 __ z_nop();
669 }
670
671 // Emit an interrupt that is caught by the debugger (for debugging compiler).
672 void emit_break(CodeBuffer &cbuf) {
673 MacroAssembler _masm(&cbuf);
674 __ z_illtrap();
675 }
676
677 #if !defined(PRODUCT)
678 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
679 os->print("TA");
680 }
681 #endif
682
683 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
684 emit_break(cbuf);
685 }
686
687 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
688 return MachNode::size(ra_);
689 }
690
691 static inline void z_emit16(CodeBuffer &cbuf, long value) {
692 // 32bit instructions may become sign extended.
693 assert(value >= 0, "unintended sign extension (int->long)");
694 assert(value < (1L << 16), "instruction too large");
695 *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value;
696 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short));
697 }
698
699 static inline void z_emit32(CodeBuffer &cbuf, long value) {
700 // 32bit instructions may become sign extended.
701 assert(value < (1L << 32), "instruction too large");
702 *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value;
703 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int));
704 }
705
706 static inline void z_emit48(CodeBuffer &cbuf, long value) {
707 // 32bit instructions may become sign extended.
708 assert(value >= 0, "unintended sign extension (int->long)");
709 assert(value < (1L << 48), "instruction too large");
710 value = value<<16;
711 memcpy(cbuf.insts_end(), (unsigned char*)&value, 6);
712 cbuf.set_insts_end(cbuf.insts_end() + 6);
713 }
714
715 static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) {
716 if (value < 0) {
717 // There obviously has been an unintended sign extension (int->long). Revert it.
718 value = (long)((unsigned long)((unsigned int)value));
719 }
720
721 if (value < (1L << 16)) { // 2-byte instruction
722 z_emit16(cbuf, value);
723 return 2;
724 }
725
726 if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store
727 z_emit32(cbuf, value);
728 return 4;
729 }
730
731 // 6-byte instruction, probably unaligned store.
732 z_emit48(cbuf, value);
733 return 6;
734 }
735
736 // Check effective address (at runtime) for required alignment.
737 static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) {
738 MacroAssembler _masm(&cbuf);
739
740 __ z_lay(Z_R0, disp, index, base);
741 __ z_nill(Z_R0, alignment-1);
742 __ z_brc(Assembler::bcondEqual, +3);
743 __ z_illtrap();
744 }
745
746 int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype,
747 PhaseRegAlloc* ra_, bool is_native_call = false) {
748 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
749 address old_mark = __ inst_mark();
750 unsigned int start_off = __ offset();
751
752 if (is_native_call) {
753 ShouldNotReachHere();
754 }
755
756 if (rtype == relocInfo::runtime_call_w_cp_type) {
757 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
758 address call_addr = __ call_c_opt((address)entry_point);
759 if (call_addr == NULL) {
760 Compile::current()->env()->record_out_of_memory_failure();
761 return -1;
762 }
763 } else {
764 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
765 rtype == relocInfo::static_call_type, "unexpected rtype");
766 __ relocate(rtype);
767 // BRASL must be prepended with a nop to identify it in the instruction stream.
768 __ z_nop();
769 __ z_brasl(Z_R14, (address)entry_point);
770 }
771
772 unsigned int ret_off = __ offset();
773
774 return (ret_off - start_off);
775 }
776
777 static int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) {
778 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
779 address old_mark = __ inst_mark();
780 unsigned int start_off = __ offset();
781
782 relocInfo::relocType rtype = rspec.type();
783 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
784 "unexpected rtype");
785
786 __ relocate(rspec);
787 __ z_nop();
788 __ z_brasl(Z_R14, (address)entry_point);
789
790 unsigned int ret_off = __ offset();
791
792 return (ret_off - start_off);
793 }
794
795 //=============================================================================
796
797 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
798 int Compile::ConstantTable::calculate_table_base_offset() const {
799 return 0; // absolute addressing, no offset
800 }
801
802 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
803 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
804 ShouldNotReachHere();
805 }
806
807 // Even with PC-relative TOC addressing, we still need this node.
808 // Float loads/stores do not support PC-relative addresses.
809 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
810 MacroAssembler _masm(&cbuf);
811 Register Rtoc = as_Register(ra_->get_encode(this));
812 __ load_toc(Rtoc);
813 }
814
815 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
816 // PCrelative TOC access.
817 return 6; // sizeof(LARL)
818 }
819
820 #if !defined(PRODUCT)
821 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
822 Register r = as_Register(ra_->get_encode(this));
823 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name());
824 }
825 #endif
826
827 //=============================================================================
828
829 #if !defined(PRODUCT)
830 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
831 Compile* C = ra_->C;
832 st->print_cr("--- MachPrologNode ---");
833 st->print("\t");
834 for (int i = 0; i < OptoPrologueNops; i++) {
835 st->print_cr("NOP"); st->print("\t");
836 }
837
838 if (VerifyThread) {
839 st->print_cr("Verify_Thread");
840 st->print("\t");
841 }
842
843 long framesize = C->frame_size_in_bytes();
844 int bangsize = C->bang_size_in_bytes();
845
846 // Calls to C2R adapters often do not accept exceptional returns.
847 // We require that their callers must bang for them. But be
848 // careful, because some VM calls (such as call site linkage) can
849 // use several kilobytes of stack. But the stack safety zone should
850 // account for that. See bugs 4446381, 4468289, 4497237.
851 if (C->need_stack_bang(bangsize) && UseStackBanging) {
852 st->print_cr("# stack bang"); st->print("\t");
853 }
854 st->print_cr("push_frame %d", (int)-framesize);
855 st->print("\t");
856 }
857 #endif
858
859 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
860 Compile* C = ra_->C;
861 MacroAssembler _masm(&cbuf);
862
863 __ verify_thread();
864
865 size_t framesize = C->frame_size_in_bytes();
866 size_t bangsize = C->bang_size_in_bytes();
867
868 assert(framesize % wordSize == 0, "must preserve wordSize alignment");
869
870 // Calls to C2R adapters often do not accept exceptional returns.
871 // We require that their callers must bang for them. But be
872 // careful, because some VM calls (such as call site linkage) can
873 // use several kilobytes of stack. But the stack safety zone should
874 // account for that. See bugs 4446381, 4468289, 4497237.
875 if (C->need_stack_bang(bangsize) && UseStackBanging) {
876 __ generate_stack_overflow_check(bangsize);
877 }
878
879 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
880 __ save_return_pc();
881
882 // The z/Architecture abi is already accounted for in `framesize' via the
883 // 'out_preserve_stack_slots' declaration.
884 __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
885
886 if (C->has_mach_constant_base_node()) {
887 // NOTE: We set the table base offset here because users might be
888 // emitted before MachConstantBaseNode.
889 Compile::ConstantTable& constant_table = C->constant_table();
890 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
891 }
892 }
893
894 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
895 // Variable size. Determine dynamically.
896 return MachNode::size(ra_);
897 }
898
899 int MachPrologNode::reloc() const {
900 // Return number of relocatable values contained in this instruction.
901 return 1; // One reloc entry for load_const(toc).
902 }
903
904 //=============================================================================
905
906 #if !defined(PRODUCT)
907 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
908 os->print_cr("epilog");
909 os->print("\t");
910 if (do_polling() && ra_->C->is_method_compilation()) {
911 os->print_cr("load_from_polling_page Z_R1_scratch");
912 os->print("\t");
913 }
914 }
915 #endif
916
917 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
918 MacroAssembler _masm(&cbuf);
919 Compile* C = ra_->C;
920 __ verify_thread();
921
922 // If this does safepoint polling, then do it here.
923 bool need_polling = do_polling() && C->is_method_compilation();
924
925 // Pop frame, restore return_pc, and all stuff needed by interpreter.
926 int frame_size_in_bytes = Assembler::align((C->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
927 __ pop_frame_restore_retPC(frame_size_in_bytes);
928
929 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
930 __ reserved_stack_check(Z_R14);
931 }
932
933 // Touch the polling page.
934 if (need_polling) {
935 if (SafepointMechanism::uses_thread_local_poll()) {
936 __ z_lg(Z_R1_scratch, Address(Z_thread, Thread::polling_page_offset()));
937 } else {
938 AddressLiteral pp(os::get_polling_page());
939 __ load_const_optimized(Z_R1_scratch, pp);
940 }
941 // We need to mark the code position where the load from the safepoint
942 // polling page was emitted as relocInfo::poll_return_type here.
943 __ relocate(relocInfo::poll_return_type);
944 __ load_from_polling_page(Z_R1_scratch);
945 }
946 }
947
948 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
949 // Variable size. determine dynamically.
950 return MachNode::size(ra_);
951 }
952
953 int MachEpilogNode::reloc() const {
954 // Return number of relocatable values contained in this instruction.
955 return 1; // One for load_from_polling_page.
956 }
957
958 const Pipeline * MachEpilogNode::pipeline() const {
959 return MachNode::pipeline_class();
960 }
961
962 int MachEpilogNode::safepoint_offset() const {
963 assert(do_polling(), "no return for this epilog node");
964 return 0;
965 }
966
967 //=============================================================================
968
969 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack.
970 enum RC { rc_bad, rc_int, rc_float, rc_stack };
971
972 static enum RC rc_class(OptoReg::Name reg) {
973 // Return the register class for the given register. The given register
974 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
975 // enumeration in adGlobals_s390.hpp.
976
977 if (reg == OptoReg::Bad) {
978 return rc_bad;
979 }
980
981 // We have 32 integer register halves, starting at index 0.
982 if (reg < 32) {
983 return rc_int;
984 }
985
986 // We have 32 floating-point register halves, starting at index 32.
987 if (reg < 32+32) {
988 return rc_float;
989 }
990
991 // Between float regs & stack are the flags regs.
992 assert(reg >= OptoReg::stack0(), "blow up if spilling flags");
993 return rc_stack;
994 }
995
996 // Returns size as obtained from z_emit_instr.
997 static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode,
998 int reg, int offset, bool do_print, outputStream *os) {
999
1000 if (cbuf) {
1001 if (opcode > (1L<<32)) {
1002 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
1003 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
1004 } else {
1005 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
1006 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
1007 }
1008 }
1009
1010 #if !defined(PRODUCT)
1011 if (do_print) {
1012 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
1013 }
1014 #endif
1015 return (opcode > (1L << 32)) ? 6 : 4;
1016 }
1017
1018 static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
1019 if (cbuf) {
1020 MacroAssembler _masm(cbuf);
1021 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
1022 }
1023
1024 #if !defined(PRODUCT)
1025 else if (do_print) {
1026 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
1027 }
1028 #endif
1029
1030 return 6;
1031 }
1032
1033 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
1034 // Get registers to move.
1035 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1036 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1037 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1038 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1039
1040 enum RC src_hi_rc = rc_class(src_hi);
1041 enum RC src_lo_rc = rc_class(src_lo);
1042 enum RC dst_hi_rc = rc_class(dst_hi);
1043 enum RC dst_lo_rc = rc_class(dst_lo);
1044
1045 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1046 bool is64 = (src_hi_rc != rc_bad);
1047 assert(!is64 ||
1048 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
1049 "expected aligned-adjacent pairs");
1050
1051 // Generate spill code!
1052
1053 if (src_lo == dst_lo && src_hi == dst_hi) {
1054 return 0; // Self copy, no move.
1055 }
1056
1057 int src_offset = ra_->reg2offset(src_lo);
1058 int dst_offset = ra_->reg2offset(dst_lo);
1059 bool print = !do_size;
1060 bool src12 = Immediate::is_uimm12(src_offset);
1061 bool dst12 = Immediate::is_uimm12(dst_offset);
1062
1063 const char *mnemo = NULL;
1064 unsigned long opc = 0;
1065
1066 // Memory->Memory Spill. Use Z_R0 to hold the value.
1067 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1068
1069 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
1070 "expected same type of move for high parts");
1071
1072 if (src12 && dst12) {
1073 return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os);
1074 }
1075
1076 int r0 = Z_R0_num;
1077 if (is64) {
1078 return z_ld_st_helper(cbuf, "LG ", LG_ZOPC, r0, src_offset, print, os) +
1079 z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os);
1080 }
1081
1082 return z_ld_st_helper(cbuf, "LY ", LY_ZOPC, r0, src_offset, print, os) +
1083 z_ld_st_helper(cbuf, "STY ", STY_ZOPC, r0, dst_offset, print, os);
1084 }
1085
1086 // Check for float->int copy. Requires a trip through memory.
1087 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1088 Unimplemented(); // Unsafe, do not remove!
1089 }
1090
1091 // Check for integer reg-reg copy.
1092 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1093 if (cbuf) {
1094 MacroAssembler _masm(cbuf);
1095 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1096 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1097 __ z_lgr(Rdst, Rsrc);
1098 return 4;
1099 }
1100 #if !defined(PRODUCT)
1101 // else
1102 if (print) {
1103 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1104 }
1105 #endif
1106 return 4;
1107 }
1108
1109 // Check for integer store.
1110 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1111 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
1112 "expected same type of move for high parts");
1113
1114 if (is64) {
1115 return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
1116 }
1117
1118 // else
1119 mnemo = dst12 ? "ST " : "STY ";
1120 opc = dst12 ? ST_ZOPC : STY_ZOPC;
1121
1122 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1123 }
1124
1125 // Check for integer load
1126 // Always load cOops zero-extended. That doesn't hurt int loads.
1127 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1128
1129 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
1130 "expected same type of move for high parts");
1131
1132 mnemo = is64 ? "LG " : "LLGF";
1133 opc = is64 ? LG_ZOPC : LLGF_ZOPC;
1134
1135 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1136 }
1137
1138 // Check for float reg-reg copy.
1139 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1140 if (cbuf) {
1141 MacroAssembler _masm(cbuf);
1142 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1143 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1144 __ z_ldr(Rdst, Rsrc);
1145 return 2;
1146 }
1147 #if !defined(PRODUCT)
1148 // else
1149 if (print) {
1150 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1151 }
1152 #endif
1153 return 2;
1154 }
1155
1156 // Check for float store.
1157 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1158 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
1159 "expected same type of move for high parts");
1160
1161 if (is64) {
1162 mnemo = dst12 ? "STD " : "STDY ";
1163 opc = dst12 ? STD_ZOPC : STDY_ZOPC;
1164 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1165 }
1166 // else
1167
1168 mnemo = dst12 ? "STE " : "STEY ";
1169 opc = dst12 ? STE_ZOPC : STEY_ZOPC;
1170 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1171 }
1172
1173 // Check for float load.
1174 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1175 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
1176 "expected same type of move for high parts");
1177
1178 if (is64) {
1179 mnemo = src12 ? "LD " : "LDY ";
1180 opc = src12 ? LD_ZOPC : LDY_ZOPC;
1181 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1182 }
1183 // else
1184
1185 mnemo = src12 ? "LE " : "LEY ";
1186 opc = src12 ? LE_ZOPC : LEY_ZOPC;
1187 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1188 }
1189
1190 // --------------------------------------------------------------------
1191 // Check for hi bits still needing moving. Only happens for misaligned
1192 // arguments to native calls.
1193 if (src_hi == dst_hi) {
1194 return 0; // Self copy, no move.
1195 }
1196
1197 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1198 Unimplemented(); // Unsafe, do not remove!
1199
1200 return 0; // never reached, but make the compiler shut up!
1201 }
1202
1203 #if !defined(PRODUCT)
1204 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1205 if (ra_ && ra_->node_regs_max_index() > 0) {
1206 implementation(NULL, ra_, false, os);
1207 } else {
1208 if (req() == 2 && in(1)) {
1209 os->print("N%d = N%d\n", _idx, in(1)->_idx);
1210 } else {
1211 const char *c = "(";
1212 os->print("N%d = ", _idx);
1213 for (uint i = 1; i < req(); ++i) {
1214 os->print("%sN%d", c, in(i)->_idx);
1215 c = ", ";
1216 }
1217 os->print(")");
1218 }
1219 }
1220 }
1221 #endif
1222
1223 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1224 implementation(&cbuf, ra_, false, NULL);
1225 }
1226
1227 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1228 return implementation(NULL, ra_, true, NULL);
1229 }
1230
1231 //=============================================================================
1232
1233 #if !defined(PRODUCT)
1234 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
1235 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
1236 }
1237 #endif
1238
1239 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const {
1240 MacroAssembler _masm(&cbuf);
1241
1242 int rem_space = 0;
1243 if (!(ra_->C->in_scratch_emit_size())) {
1244 rem_space = cbuf.insts()->remaining();
1245 if (rem_space <= _count*2 + 8) {
1246 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
1247 }
1248 }
1249
1250 for (int i = 0; i < _count; i++) {
1251 __ z_nop();
1252 }
1253
1254 if (!(ra_->C->in_scratch_emit_size())) {
1255 if (rem_space <= _count*2 + 8) {
1256 int rem_space2 = cbuf.insts()->remaining();
1257 tty->print_cr(", after = %d", rem_space2);
1258 }
1259 }
1260 }
1261
1262 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1263 return 2 * _count;
1264 }
1265
1266 #if !defined(PRODUCT)
1267 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1268 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1269 if (ra_ && ra_->node_regs_max_index() > 0) {
1270 int reg = ra_->get_reg_first(this);
1271 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset);
1272 } else {
1273 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset);
1274 }
1275 }
1276 #endif
1277
1278 // Take care of the size function, if you make changes here!
1279 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1280 MacroAssembler _masm(&cbuf);
1281
1282 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1283 int reg = ra_->get_encode(this);
1284 __ z_lay(as_Register(reg), offset, Z_SP);
1285 }
1286
1287 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1288 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1289 return 6;
1290 }
1291
1292 %} // end source section
1293
1294 //----------SOURCE BLOCK-------------------------------------------------------
1295 // This is a block of C++ code which provides values, functions, and
1296 // definitions necessary in the rest of the architecture description
1297
1298 source_hpp %{
1299
1300 // Header information of the source block.
1301 // Method declarations/definitions which are used outside
1302 // the ad-scope can conveniently be defined here.
1303 //
1304 // To keep related declarations/definitions/uses close together,
1305 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1306
1307 //--------------------------------------------------------------
1308 // Used for optimization in Compile::Shorten_branches
1309 //--------------------------------------------------------------
1310
1311 class CallStubImpl {
1312 public:
1313
1314 // call trampolines
1315 // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
1316 static uint size_call_trampoline() {
1317 return 0; // no call trampolines on this platform
1318 }
1319
1320 // call trampolines
1321 // Number of relocations needed by a call trampoline stub.
1322 static uint reloc_call_trampoline() {
1323 return 0; // No call trampolines on this platform.
1324 }
1325 };
1326
1327 %} // end source_hpp section
1328
1329 source %{
1330
1331 #if !defined(PRODUCT)
1332 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1333 os->print_cr("---- MachUEPNode ----");
1334 os->print_cr("\tTA");
1335 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
1336 os->print_cr("\tBR(Z_R1)");
1337 os->print_cr("\tTA # pad with illtraps");
1338 os->print_cr("\t...");
1339 os->print_cr("\tTA");
1340 os->print_cr("\tLTGR Z_R2, Z_R2");
1341 os->print_cr("\tBRU ic_miss");
1342 }
1343 #endif
1344
1345 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1346 MacroAssembler _masm(&cbuf);
1347 const int ic_miss_offset = 2;
1348
1349 // Inline_cache contains a klass.
1350 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1351 // ARG1 is the receiver oop.
1352 Register R2_receiver = Z_ARG1;
1353 int klass_offset = oopDesc::klass_offset_in_bytes();
1354 AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub());
1355 Register R1_ic_miss_stub_addr = Z_R1_scratch;
1356
1357 // Null check of receiver.
1358 // This is the null check of the receiver that actually should be
1359 // done in the caller. It's here because in case of implicit null
1360 // checks we get it for free.
1361 assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()),
1362 "second word in oop should not require explicit null check.");
1363 if (!ImplicitNullChecks) {
1364 Label valid;
1365 if (VM_Version::has_CompareBranch()) {
1366 __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid);
1367 } else {
1368 __ z_ltgr(R2_receiver, R2_receiver);
1369 __ z_bre(valid);
1370 }
1371 // The ic_miss_stub will handle the null pointer exception.
1372 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
1373 __ z_br(R1_ic_miss_stub_addr);
1374 __ bind(valid);
1375 }
1376
1377 // Check whether this method is the proper implementation for the class of
1378 // the receiver (ic miss check).
1379 {
1380 Label valid;
1381 // Compare cached class against klass from receiver.
1382 // This also does an implicit null check!
1383 __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false);
1384 __ z_bre(valid);
1385 // The inline cache points to the wrong method. Call the
1386 // ic_miss_stub to find the proper method.
1387 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
1388 __ z_br(R1_ic_miss_stub_addr);
1389 __ bind(valid);
1390 }
1391 }
1392
1393 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1394 // Determine size dynamically.
1395 return MachNode::size(ra_);
1396 }
1397
1398 //=============================================================================
1399
1400 %} // interrupt source section
1401
1402 source_hpp %{ // Header information of the source block.
1403
1404 class HandlerImpl {
1405 public:
1406
1407 static int emit_exception_handler(CodeBuffer &cbuf);
1408 static int emit_deopt_handler(CodeBuffer& cbuf);
1409
1410 static uint size_exception_handler() {
1411 return NativeJump::max_instruction_size();
1412 }
1413
1414 static uint size_deopt_handler() {
1415 return NativeCall::max_instruction_size();
1416 }
1417 };
1418
1419 %} // end source_hpp section
1420
1421 source %{
1422
1423 // This exception handler code snippet is placed after the method's
1424 // code. It is the return point if an exception occurred. it jumps to
1425 // the exception blob.
1426 //
1427 // If the method gets deoptimized, the method and this code snippet
1428 // get patched.
1429 //
1430 // 1) Trampoline code gets patched into the end of this exception
1431 // handler. the trampoline code jumps to the deoptimization blob.
1432 //
1433 // 2) The return address in the method's code will get patched such
1434 // that it jumps to the trampoline.
1435 //
1436 // 3) The handler will get patched such that it does not jump to the
1437 // exception blob, but to an entry in the deoptimization blob being
1438 // aware of the exception.
1439 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1440 Register temp_reg = Z_R1;
1441 MacroAssembler _masm(&cbuf);
1442
1443 address base = __ start_a_stub(size_exception_handler());
1444 if (base == NULL) {
1445 return 0; // CodeBuffer::expand failed
1446 }
1447
1448 int offset = __ offset();
1449 // Use unconditional pc-relative jump with 32-bit range here.
1450 __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin());
1451 __ z_br(temp_reg);
1452
1453 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1454
1455 __ end_a_stub();
1456
1457 return offset;
1458 }
1459
1460 // Emit deopt handler code.
1461 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1462 MacroAssembler _masm(&cbuf);
1463 address base = __ start_a_stub(size_deopt_handler());
1464
1465 if (base == NULL) {
1466 return 0; // CodeBuffer::expand failed
1467 }
1468
1469 int offset = __ offset();
1470
1471 // Size_deopt_handler() must be exact on zarch, so for simplicity
1472 // we do not use load_const_opt here.
1473 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
1474 __ call(Z_R1);
1475 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1476
1477 __ end_a_stub();
1478 return offset;
1479 }
1480
1481 //=============================================================================
1482
1483
1484 // Given a register encoding, produce an Integer Register object.
1485 static Register reg_to_register_object(int register_encoding) {
1486 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
1487 return as_Register(register_encoding);
1488 }
1489
1490 const bool Matcher::match_rule_supported(int opcode) {
1491 if (!has_match_rule(opcode)) return false;
1492
1493 switch (opcode) {
1494 case Op_CountLeadingZerosI:
1495 case Op_CountLeadingZerosL:
1496 case Op_CountTrailingZerosI:
1497 case Op_CountTrailingZerosL:
1498 // Implementation requires FLOGR instruction, which is available since z9.
1499 return true;
1500
1501 case Op_ReverseBytesI:
1502 case Op_ReverseBytesL:
1503 return UseByteReverseInstruction;
1504
1505 // PopCount supported by H/W from z/Architecture G5 (z196) on.
1506 case Op_PopCountI:
1507 case Op_PopCountL:
1508 return UsePopCountInstruction && VM_Version::has_PopCount();
1509
1510 case Op_StrComp:
1511 return SpecialStringCompareTo;
1512 case Op_StrEquals:
1513 return SpecialStringEquals;
1514 case Op_StrIndexOf:
1515 case Op_StrIndexOfChar:
1516 return SpecialStringIndexOf;
1517
1518 case Op_GetAndAddI:
1519 case Op_GetAndAddL:
1520 return true;
1521 // return VM_Version::has_AtomicMemWithImmALUOps();
1522 case Op_GetAndSetI:
1523 case Op_GetAndSetL:
1524 case Op_GetAndSetP:
1525 case Op_GetAndSetN:
1526 return true; // General CAS implementation, always available.
1527
1528 default:
1529 return true; // Per default match rules are supported.
1530 // BUT: make sure match rule is not disabled by a false predicate!
1531 }
1532
1533 return true; // Per default match rules are supported.
1534 // BUT: make sure match rule is not disabled by a false predicate!
1535 }
1536
1537 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1538 // TODO
1539 // Identify extra cases that we might want to provide match rules for
1540 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen.
1541 bool ret_value = match_rule_supported(opcode);
1542 // Add rules here.
1543
1544 return ret_value; // Per default match rules are supported.
1545 }
1546
1547 int Matcher::regnum_to_fpu_offset(int regnum) {
1548 ShouldNotReachHere();
1549 return regnum - 32; // The FP registers are in the second chunk.
1550 }
1551
1552 const bool Matcher::has_predicated_vectors(void) {
1553 return false;
1554 }
1555
1556 const int Matcher::float_pressure(int default_pressure_threshold) {
1557 return default_pressure_threshold;
1558 }
1559
1560 const bool Matcher::convL2FSupported(void) {
1561 return true; // False means that conversion is done by runtime call.
1562 }
1563
1564 //----------SUPERWORD HELPERS----------------------------------------
1565
1566 // Vector width in bytes.
1567 const int Matcher::vector_width_in_bytes(BasicType bt) {
1568 assert(MaxVectorSize == 8, "");
1569 return 8;
1570 }
1571
1572 // Vector ideal reg.
1573 const uint Matcher::vector_ideal_reg(int size) {
1574 assert(MaxVectorSize == 8 && size == 8, "");
1575 return Op_RegL;
1576 }
1577
1578 // Limits on vector size (number of elements) loaded into vector.
1579 const int Matcher::max_vector_size(const BasicType bt) {
1580 assert(is_java_primitive(bt), "only primitive type vectors");
1581 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1582 }
1583
1584 const int Matcher::min_vector_size(const BasicType bt) {
1585 return max_vector_size(bt); // Same as max.
1586 }
1587
1588 const uint Matcher::vector_shift_count_ideal_reg(int size) {
1589 fatal("vector shift is not supported");
1590 return Node::NotAMachineReg;
1591 }
1592
1593 // z/Architecture does support misaligned store/load at minimal extra cost.
1594 const bool Matcher::misaligned_vectors_ok() {
1595 return true;
1596 }
1597
1598 // Not yet ported to z/Architecture.
1599 const bool Matcher::pass_original_key_for_aes() {
1600 return false;
1601 }
1602
1603 // RETURNS: whether this branch offset is short enough that a short
1604 // branch can be used.
1605 //
1606 // If the platform does not provide any short branch variants, then
1607 // this method should return `false' for offset 0.
1608 //
1609 // `Compile::Fill_buffer' will decide on basis of this information
1610 // whether to do the pass `Compile::Shorten_branches' at all.
1611 //
1612 // And `Compile::Shorten_branches' will decide on basis of this
1613 // information whether to replace particular branch sites by short
1614 // ones.
1615 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1616 // On zarch short branches use a 16 bit signed immediate that
1617 // is the pc-relative offset in halfword (= 2 bytes) units.
1618 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
1619 }
1620
1621 const bool Matcher::isSimpleConstant64(jlong value) {
1622 // Probably always true, even if a temp register is required.
1623 return true;
1624 }
1625
1626 // Should correspond to setting above
1627 const bool Matcher::init_array_count_is_in_bytes = false;
1628
1629 // Suppress CMOVL. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet.
1630 const int Matcher::long_cmove_cost() { return ConditionalMoveLimit; }
1631
1632 // Suppress CMOVF. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet.
1633 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1634
1635 // Does the CPU require postalloc expand (see block.cpp for description of postalloc expand)?
1636 const bool Matcher::require_postalloc_expand = false;
1637
1638 // Do we need to mask the count passed to shift instructions or does
1639 // the cpu only look at the lower 5/6 bits anyway?
1640 // 32bit shifts mask in emitter, 64bit shifts need no mask.
1641 // Constant shift counts are handled in Ideal phase.
1642 const bool Matcher::need_masked_shift_count = false;
1643
1644 // Set this as clone_shift_expressions.
1645 bool Matcher::narrow_oop_use_complex_address() {
1646 if (CompressedOops::base() == NULL && CompressedOops::shift() == 0) return true;
1647 return false;
1648 }
1649
1650 bool Matcher::narrow_klass_use_complex_address() {
1651 NOT_LP64(ShouldNotCallThis());
1652 assert(UseCompressedClassPointers, "only for compressed klass code");
1653 // TODO HS25: z port if (MatchDecodeNodes) return true;
1654 return false;
1655 }
1656
1657 bool Matcher::const_oop_prefer_decode() {
1658 // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
1659 return CompressedOops::base() == NULL;
1660 }
1661
1662 bool Matcher::const_klass_prefer_decode() {
1663 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1664 return CompressedKlassPointers::base() == NULL;
1665 }
1666
1667 // Is it better to copy float constants, or load them directly from memory?
1668 // Most RISCs will have to materialize an address into a
1669 // register first, so they would do better to copy the constant from stack.
1670 const bool Matcher::rematerialize_float_constants = false;
1671
1672 // If CPU can load and store mis-aligned doubles directly then no fixup is
1673 // needed. Else we split the double into 2 integer pieces and move it
1674 // piece-by-piece. Only happens when passing doubles into C code as the
1675 // Java calling convention forces doubles to be aligned.
1676 const bool Matcher::misaligned_doubles_ok = true;
1677
1678 // Advertise here if the CPU requires explicit rounding operations
1679 // to implement the UseStrictFP mode.
1680 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1681
1682 // Do floats take an entire double register or just half?
1683 //
1684 // A float in resides in a zarch double register. When storing it by
1685 // z_std, it cannot be restored in C-code by reloading it as a double
1686 // and casting it into a float afterwards.
1687 bool Matcher::float_in_double() { return false; }
1688
1689 // Do ints take an entire long register or just half?
1690 // The relevant question is how the int is callee-saved:
1691 // the whole long is written but de-opt'ing will have to extract
1692 // the relevant 32 bits.
1693 const bool Matcher::int_in_long = true;
1694
1695 // Constants for c2c and c calling conventions.
1696
1697 const MachRegisterNumbers z_iarg_reg[5] = {
1698 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
1699 };
1700
1701 const MachRegisterNumbers z_farg_reg[4] = {
1702 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
1703 };
1704
1705 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
1706
1707 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
1708
1709 // Return whether or not this register is ever used as an argument. This
1710 // function is used on startup to build the trampoline stubs in generateOptoStub.
1711 // Registers not mentioned will be killed by the VM call in the trampoline, and
1712 // arguments in those registers not be available to the callee.
1713 bool Matcher::can_be_java_arg(int reg) {
1714 // We return true for all registers contained in z_iarg_reg[] and
1715 // z_farg_reg[] and their virtual halves.
1716 // We must include the virtual halves in order to get STDs and LDs
1717 // instead of STWs and LWs in the trampoline stubs.
1718
1719 if (reg == Z_R2_num || reg == Z_R2_H_num ||
1720 reg == Z_R3_num || reg == Z_R3_H_num ||
1721 reg == Z_R4_num || reg == Z_R4_H_num ||
1722 reg == Z_R5_num || reg == Z_R5_H_num ||
1723 reg == Z_R6_num || reg == Z_R6_H_num) {
1724 return true;
1725 }
1726
1727 if (reg == Z_F0_num || reg == Z_F0_H_num ||
1728 reg == Z_F2_num || reg == Z_F2_H_num ||
1729 reg == Z_F4_num || reg == Z_F4_H_num ||
1730 reg == Z_F6_num || reg == Z_F6_H_num) {
1731 return true;
1732 }
1733
1734 return false;
1735 }
1736
1737 bool Matcher::is_spillable_arg(int reg) {
1738 return can_be_java_arg(reg);
1739 }
1740
1741 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
1742 return false;
1743 }
1744
1745 // Register for DIVI projection of divmodI
1746 RegMask Matcher::divI_proj_mask() {
1747 return _Z_RARG4_INT_REG_mask;
1748 }
1749
1750 // Register for MODI projection of divmodI
1751 RegMask Matcher::modI_proj_mask() {
1752 return _Z_RARG3_INT_REG_mask;
1753 }
1754
1755 // Register for DIVL projection of divmodL
1756 RegMask Matcher::divL_proj_mask() {
1757 return _Z_RARG4_LONG_REG_mask;
1758 }
1759
1760 // Register for MODL projection of divmodL
1761 RegMask Matcher::modL_proj_mask() {
1762 return _Z_RARG3_LONG_REG_mask;
1763 }
1764
1765 // Copied from sparc.
1766 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1767 return RegMask();
1768 }
1769
1770 const bool Matcher::convi2l_type_required = true;
1771
1772 // Should the Matcher clone shifts on addressing modes, expecting them
1773 // to be subsumed into complex addressing expressions or compute them
1774 // into registers?
1775 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1776 return clone_base_plus_offset_address(m, mstack, address_visited);
1777 }
1778
1779 void Compile::reshape_address(AddPNode* addp) {
1780 }
1781
1782 %} // source
1783
1784 //----------ENCODING BLOCK-----------------------------------------------------
1785 // This block specifies the encoding classes used by the compiler to output
1786 // byte streams. Encoding classes are parameterized macros used by
1787 // Machine Instruction Nodes in order to generate the bit encoding of the
1788 // instruction. Operands specify their base encoding interface with the
1789 // interface keyword. There are currently supported four interfaces,
1790 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1791 // operand to generate a function which returns its register number when
1792 // queried. CONST_INTER causes an operand to generate a function which
1793 // returns the value of the constant when queried. MEMORY_INTER causes an
1794 // operand to generate four functions which return the Base Register, the
1795 // Index Register, the Scale Value, and the Offset Value of the operand when
1796 // queried. COND_INTER causes an operand to generate six functions which
1797 // return the encoding code (ie - encoding bits for the instruction)
1798 // associated with each basic boolean condition for a conditional instruction.
1799 //
1800 // Instructions specify two basic values for encoding. Again, a function
1801 // is available to check if the constant displacement is an oop. They use the
1802 // ins_encode keyword to specify their encoding classes (which must be
1803 // a sequence of enc_class names, and their parameters, specified in
1804 // the encoding block), and they use the
1805 // opcode keyword to specify, in order, their primary, secondary, and
1806 // tertiary opcode. Only the opcode sections which a particular instruction
1807 // needs for encoding need to be specified.
1808 encode %{
1809 enc_class enc_unimplemented %{
1810 MacroAssembler _masm(&cbuf);
1811 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
1812 %}
1813
1814 enc_class enc_untested %{
1815 #ifdef ASSERT
1816 MacroAssembler _masm(&cbuf);
1817 __ untested("Untested mach node encoding in AD file.");
1818 #endif
1819 %}
1820
1821 enc_class z_rrform(iRegI dst, iRegI src) %{
1822 assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
1823 assert( ($primary >> 16) == 0, "Instruction format error");
1824 z_emit16(cbuf, $primary |
1825 Assembler::reg($dst$$reg,8,16) |
1826 Assembler::reg($src$$reg,12,16));
1827 %}
1828
1829 enc_class z_rreform(iRegI dst1, iRegI src2) %{
1830 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
1831 z_emit32(cbuf, $primary |
1832 Assembler::reg($dst1$$reg,24,32) |
1833 Assembler::reg($src2$$reg,28,32));
1834 %}
1835
1836 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
1837 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
1838 z_emit32(cbuf, $primary |
1839 Assembler::reg($dst1$$reg,24,32) |
1840 Assembler::reg($src2$$reg,28,32) |
1841 Assembler::reg($src3$$reg,16,32));
1842 %}
1843
1844 enc_class z_riform_signed(iRegI dst, immI16 src) %{
1845 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
1846 z_emit32(cbuf, $primary |
1847 Assembler::reg($dst$$reg,8,32) |
1848 Assembler::simm16($src$$constant,16,32));
1849 %}
1850
1851 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
1852 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
1853 z_emit32(cbuf, $primary |
1854 Assembler::reg($dst$$reg,8,32) |
1855 Assembler::uimm16($src$$constant,16,32));
1856 %}
1857
1858 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
1859 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1860 z_emit48(cbuf, $primary |
1861 Assembler::reg($dst1$$reg,8,48) |
1862 Assembler::reg($src3$$reg,12,48) |
1863 Assembler::simm16($src2$$constant,16,48));
1864 %}
1865
1866 enc_class z_rilform_signed(iRegI dst, immL32 src) %{
1867 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1868 z_emit48(cbuf, $primary |
1869 Assembler::reg($dst$$reg,8,48) |
1870 Assembler::simm32($src$$constant,16,48));
1871 %}
1872
1873 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
1874 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1875 z_emit48(cbuf, $primary |
1876 Assembler::reg($dst$$reg,8,48) |
1877 Assembler::uimm32($src$$constant,16,48));
1878 %}
1879
1880 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
1881 z_emit48(cbuf, $primary |
1882 Assembler::reg($dst$$reg,8,48) |
1883 Assembler::reg($src1$$reg,12,48) |
1884 Assembler::simm20($src2$$constant));
1885 %}
1886
1887 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
1888 z_emit48(cbuf, $primary |
1889 Assembler::reg($dst$$reg,8,48) |
1890 Assembler::reg($src$$reg,12,48) |
1891 Assembler::reg($shft$$reg,16,48) |
1892 Assembler::simm20(0));
1893 %}
1894
1895 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
1896 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
1897 z_emit32(cbuf, $primary |
1898 Assembler::reg($dst$$reg,8,32) |
1899 Assembler::reg($src1$$reg,12,32) |
1900 Assembler::reg($src2$$reg,16,32) |
1901 Assembler::uimm12($con$$constant,20,32));
1902 %}
1903
1904 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
1905 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
1906 z_emit32(cbuf, $primary |
1907 Assembler::reg($dst$$reg,8,32) |
1908 Assembler::reg($src$$reg,16,32) |
1909 Assembler::uimm12($con$$constant,20,32));
1910 %}
1911
1912 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
1913 z_emit48(cbuf, $primary |
1914 Assembler::reg($dst$$reg,8,48) |
1915 Assembler::reg($src1$$reg,12,48) |
1916 Assembler::reg($src2$$reg,16,48) |
1917 Assembler::simm20($con$$constant));
1918 %}
1919
1920 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
1921 z_emit48(cbuf, $primary |
1922 Assembler::reg($dst$$reg,8,48) |
1923 Assembler::reg($src$$reg,16,48) |
1924 Assembler::simm20($con$$constant));
1925 %}
1926
1927 // Direct memory arithmetic.
1928 enc_class z_siyform(memoryRSY mem, immI8 src) %{
1929 int disp = $mem$$disp;
1930 Register base = reg_to_register_object($mem$$base);
1931 int con = $src$$constant;
1932
1933 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
1934 z_emit_inst(cbuf, $primary |
1935 Assembler::regz(base,16,48) |
1936 Assembler::simm20(disp) |
1937 Assembler::simm8(con,8,48));
1938 %}
1939
1940 enc_class z_silform(memoryRS mem, immI16 src) %{
1941 z_emit_inst(cbuf, $primary |
1942 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
1943 Assembler::uimm12($mem$$disp,20,48) |
1944 Assembler::simm16($src$$constant,32,48));
1945 %}
1946
1947 // Encoder for FP ALU reg/mem instructions (support only short displacements).
1948 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
1949 Register Ridx = $mem$$index$$Register;
1950 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1951 if ($primary > (1L << 32)) {
1952 z_emit_inst(cbuf, $primary |
1953 Assembler::reg($dst$$reg, 8, 48) |
1954 Assembler::uimm12($mem$$disp, 20, 48) |
1955 Assembler::reg(Ridx, 12, 48) |
1956 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1957 } else {
1958 z_emit_inst(cbuf, $primary |
1959 Assembler::reg($dst$$reg, 8, 32) |
1960 Assembler::uimm12($mem$$disp, 20, 32) |
1961 Assembler::reg(Ridx, 12, 32) |
1962 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
1963 }
1964 %}
1965
1966 enc_class z_form_rt_mem(iRegI dst, memory mem) %{
1967 Register Ridx = $mem$$index$$Register;
1968 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1969 if ($primary > (1L<<32)) {
1970 z_emit_inst(cbuf, $primary |
1971 Assembler::reg($dst$$reg, 8, 48) |
1972 Assembler::simm20($mem$$disp) |
1973 Assembler::reg(Ridx, 12, 48) |
1974 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1975 } else {
1976 z_emit_inst(cbuf, $primary |
1977 Assembler::reg($dst$$reg, 8, 32) |
1978 Assembler::uimm12($mem$$disp, 20, 32) |
1979 Assembler::reg(Ridx, 12, 32) |
1980 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
1981 }
1982 %}
1983
1984 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
1985 int isize = $secondary > 1L << 32 ? 48 : 32;
1986 Register Ridx = $mem$$index$$Register;
1987 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1988
1989 if (Displacement::is_shortDisp((long)$mem$$disp)) {
1990 z_emit_inst(cbuf, $secondary |
1991 Assembler::reg($dst$$reg, 8, isize) |
1992 Assembler::uimm12($mem$$disp, 20, isize) |
1993 Assembler::reg(Ridx, 12, isize) |
1994 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
1995 } else if (Displacement::is_validDisp((long)$mem$$disp)) {
1996 z_emit_inst(cbuf, $primary |
1997 Assembler::reg($dst$$reg, 8, 48) |
1998 Assembler::simm20($mem$$disp) |
1999 Assembler::reg(Ridx, 12, 48) |
2000 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2001 } else {
2002 MacroAssembler _masm(&cbuf);
2003 __ load_const_optimized(Z_R1_scratch, $mem$$disp);
2004 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
2005 z_emit_inst(cbuf, $secondary |
2006 Assembler::reg($dst$$reg, 8, isize) |
2007 Assembler::uimm12(0, 20, isize) |
2008 Assembler::reg(Z_R1_scratch, 12, isize) |
2009 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2010 }
2011 %}
2012
2013 enc_class z_enc_brul(Label lbl) %{
2014 MacroAssembler _masm(&cbuf);
2015 Label* p = $lbl$$label;
2016
2017 // 'p' is `NULL' when this encoding class is used only to
2018 // determine the size of the encoded instruction.
2019 // Use a bound dummy label in that case.
2020 Label d;
2021 __ bind(d);
2022 Label& l = (NULL == p) ? d : *(p);
2023 __ z_brul(l);
2024 %}
2025
2026 enc_class z_enc_bru(Label lbl) %{
2027 MacroAssembler _masm(&cbuf);
2028 Label* p = $lbl$$label;
2029
2030 // 'p' is `NULL' when this encoding class is used only to
2031 // determine the size of the encoded instruction.
2032 // Use a bound dummy label in that case.
2033 Label d;
2034 __ bind(d);
2035 Label& l = (NULL == p) ? d : *(p);
2036 __ z_bru(l);
2037 %}
2038
2039 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
2040 MacroAssembler _masm(&cbuf);
2041 Label* p = $lbl$$label;
2042
2043 // 'p' is `NULL' when this encoding class is used only to
2044 // determine the size of the encoded instruction.
2045 // Use a bound dummy label in that case.
2046 Label d;
2047 __ bind(d);
2048 Label& l = (NULL == p) ? d : *(p);
2049 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2050 %}
2051
2052 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
2053 MacroAssembler _masm(&cbuf);
2054 Label* p = $lbl$$label;
2055
2056 // 'p' is `NULL' when this encoding class is used only to
2057 // determine the size of the encoded instruction.
2058 // Use a bound dummy label in that case.
2059 Label d;
2060 __ bind(d);
2061 Label& l = (NULL == p) ? d : *(p);
2062 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
2063 %}
2064
2065 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2066 MacroAssembler _masm(&cbuf);
2067 Label* p = $lbl$$label;
2068
2069 // 'p' is `NULL' when this encoding class is used only to
2070 // determine the size of the encoded instruction.
2071 // Use a bound dummy label in that case.
2072 Label d;
2073 __ bind(d);
2074 Label& l = (NULL == p) ? d : *(p);
2075 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2076 unsigned long instr = $primary;
2077 if (instr == CRJ_ZOPC) {
2078 __ z_crj($src1$$Register, $src2$$Register, cc, l);
2079 } else if (instr == CLRJ_ZOPC) {
2080 __ z_clrj($src1$$Register, $src2$$Register, cc, l);
2081 } else if (instr == CGRJ_ZOPC) {
2082 __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
2083 } else {
2084 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
2085 __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
2086 }
2087 %}
2088
2089 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2090 MacroAssembler _masm(&cbuf);
2091 Label* p = $lbl$$label;
2092
2093 // 'p' is `NULL' when this encoding class is used only to
2094 // determine the size of the encoded instruction.
2095 // Use a bound dummy label in that case.
2096 Label d;
2097 __ bind(d);
2098 Label& l = (NULL == p) ? d : *(p);
2099
2100 unsigned long instr = $primary;
2101 if (instr == CR_ZOPC) {
2102 __ z_cr($src1$$Register, $src2$$Register);
2103 } else if (instr == CLR_ZOPC) {
2104 __ z_clr($src1$$Register, $src2$$Register);
2105 } else if (instr == CGR_ZOPC) {
2106 __ z_cgr($src1$$Register, $src2$$Register);
2107 } else {
2108 guarantee(instr == CLGR_ZOPC, "opcode not implemented");
2109 __ z_clgr($src1$$Register, $src2$$Register);
2110 }
2111
2112 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2113 %}
2114
2115 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2116 MacroAssembler _masm(&cbuf);
2117 Label* p = $lbl$$label;
2118
2119 // 'p' is `NULL' when this encoding class is used only to
2120 // determine the size of the encoded instruction.
2121 // Use a bound dummy label in that case.
2122 Label d;
2123 __ bind(d);
2124 Label& l = (NULL == p) ? d : *(p);
2125
2126 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2127 unsigned long instr = $primary;
2128 if (instr == CIJ_ZOPC) {
2129 __ z_cij($src1$$Register, $src2$$constant, cc, l);
2130 } else if (instr == CLIJ_ZOPC) {
2131 __ z_clij($src1$$Register, $src2$$constant, cc, l);
2132 } else if (instr == CGIJ_ZOPC) {
2133 __ z_cgij($src1$$Register, $src2$$constant, cc, l);
2134 } else {
2135 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
2136 __ z_clgij($src1$$Register, $src2$$constant, cc, l);
2137 }
2138 %}
2139
2140 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2141 MacroAssembler _masm(&cbuf);
2142 Label* p = $lbl$$label;
2143
2144 // 'p' is `NULL' when this encoding class is used only to
2145 // determine the size of the encoded instruction.
2146 // Use a bound dummy label in that case.
2147 Label d;
2148 __ bind(d);
2149 Label& l = (NULL == p) ? d : *(p);
2150
2151 unsigned long instr = $primary;
2152 if (instr == CHI_ZOPC) {
2153 __ z_chi($src1$$Register, $src2$$constant);
2154 } else if (instr == CLFI_ZOPC) {
2155 __ z_clfi($src1$$Register, $src2$$constant);
2156 } else if (instr == CGHI_ZOPC) {
2157 __ z_cghi($src1$$Register, $src2$$constant);
2158 } else {
2159 guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
2160 __ z_clgfi($src1$$Register, $src2$$constant);
2161 }
2162
2163 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2164 %}
2165
2166 // Call from Java to runtime.
2167 enc_class z_enc_java_to_runtime_call(method meth) %{
2168 MacroAssembler _masm(&cbuf);
2169
2170 // Save return pc before call to the place where we need it, since
2171 // callee doesn't.
2172 unsigned int start_off = __ offset();
2173 // Compute size of "larl + stg + call_c_opt".
2174 const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size();
2175 __ get_PC(Z_R14, size_of_code);
2176 __ save_return_pc();
2177 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
2178
2179 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
2180 address call_addr = __ call_c_opt((address)$meth$$method);
2181 if (call_addr == NULL) {
2182 Compile::current()->env()->record_out_of_memory_failure();
2183 return;
2184 }
2185
2186 #ifdef ASSERT
2187 // Plausibility check for size_of_code assumptions.
2188 unsigned int actual_ret_off = __ offset();
2189 assert(start_off + size_of_code == actual_ret_off, "wrong return_pc");
2190 #endif
2191 %}
2192
2193 enc_class z_enc_java_static_call(method meth) %{
2194 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
2195 // whom we intended to call.
2196 MacroAssembler _masm(&cbuf);
2197 int ret_offset = 0;
2198
2199 if (!_method) {
2200 ret_offset = emit_call_reloc(_masm, $meth$$method,
2201 relocInfo::runtime_call_w_cp_type, ra_);
2202 } else {
2203 int method_index = resolved_method_index(cbuf);
2204 if (_optimized_virtual) {
2205 ret_offset = emit_call_reloc(_masm, $meth$$method,
2206 opt_virtual_call_Relocation::spec(method_index));
2207 } else {
2208 ret_offset = emit_call_reloc(_masm, $meth$$method,
2209 static_call_Relocation::spec(method_index));
2210 }
2211 }
2212 assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()");
2213
2214 if (_method) { // Emit stub for static call.
2215 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2216 if (stub == NULL) {
2217 ciEnv::current()->record_failure("CodeCache is full");
2218 return;
2219 }
2220 }
2221 %}
2222
2223 // Java dynamic call
2224 enc_class z_enc_java_dynamic_call(method meth) %{
2225 MacroAssembler _masm(&cbuf);
2226 unsigned int start_off = __ offset();
2227
2228 int vtable_index = this->_vtable_index;
2229 if (vtable_index == -4) {
2230 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2231 address virtual_call_oop_addr = NULL;
2232
2233 AddressLiteral empty_ic((address) Universe::non_oop_word());
2234 virtual_call_oop_addr = __ pc();
2235 bool success = __ load_const_from_toc(ic_reg, empty_ic);
2236 if (!success) {
2237 Compile::current()->env()->record_out_of_memory_failure();
2238 return;
2239 }
2240
2241 // Call to fixup routine. Fixup routine uses ScopeDesc info
2242 // to determine who we intended to call.
2243 int method_index = resolved_method_index(cbuf);
2244 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
2245 unsigned int ret_off = __ offset();
2246 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
2247 ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_);
2248 assert(_method, "lazy_constant may be wrong when _method==null");
2249 } else {
2250 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2251 // Go through the vtable. Get receiver klass. Receiver already
2252 // checked for non-null. If we'll go thru a C2I adapter, the
2253 // interpreter expects method in Z_method.
2254 // Use Z_method to temporarily hold the klass oop.
2255 // Z_R1_scratch is destroyed.
2256 __ load_klass(Z_method, Z_R2);
2257
2258 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
2259 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2260
2261 if (Displacement::is_validDisp(v_off) ) {
2262 // Can use load instruction with large offset.
2263 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
2264 } else {
2265 // Worse case, must load offset into register.
2266 __ load_const(Z_R1_scratch, v_off);
2267 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
2268 }
2269 // NOTE: for vtable dispatches, the vtable entry will never be
2270 // null. However it may very well end up in handle_wrong_method
2271 // if the method is abstract for the particular class.
2272 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
2273 // Call target. Either compiled code or C2I adapter.
2274 __ z_basr(Z_R14, Z_R1_scratch);
2275 unsigned int ret_off = __ offset();
2276 }
2277 %}
2278
2279 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
2280 MacroAssembler _masm(&cbuf);
2281 Register Rdst = reg_to_register_object($dst$$reg);
2282 Register Rsrc = reg_to_register_object($src$$reg);
2283
2284 // Don't emit code if operands are identical (same register).
2285 if (Rsrc != Rdst) {
2286 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2287
2288 if (VM_Version::has_LoadStoreConditional()) {
2289 __ z_locgr(Rdst, Rsrc, cc);
2290 } else {
2291 // Branch if not (cmp cr).
2292 Label done;
2293 __ z_brc(Assembler::inverse_condition(cc), done);
2294 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
2295 __ bind(done);
2296 }
2297 }
2298 %}
2299
2300 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
2301 MacroAssembler _masm(&cbuf);
2302 Register Rdst = reg_to_register_object($dst$$reg);
2303 int Csrc = $src$$constant;
2304 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2305 Label done;
2306 // Branch if not (cmp cr).
2307 __ z_brc(Assembler::inverse_condition(cc), done);
2308 if (Csrc == 0) {
2309 // Don't set CC.
2310 __ clear_reg(Rdst, true, false); // Use for int, long & ptr.
2311 } else {
2312 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
2313 }
2314 __ bind(done);
2315 %}
2316
2317 enc_class z_enc_cctobool(iRegI res) %{
2318 MacroAssembler _masm(&cbuf);
2319 Register Rres = reg_to_register_object($res$$reg);
2320
2321 if (VM_Version::has_LoadStoreConditional()) {
2322 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
2323 __ load_const_optimized(Rres, 1L); // true (succeed)
2324 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
2325 } else {
2326 Label done;
2327 __ load_const_optimized(Rres, 0L); // false (failed)
2328 __ z_brne(done); // Assume true to be the common case.
2329 __ load_const_optimized(Rres, 1L); // true (succeed)
2330 __ bind(done);
2331 }
2332 %}
2333
2334 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
2335 MacroAssembler _masm(&cbuf);
2336 Register Rcomp = reg_to_register_object($compare_value$$reg);
2337 Register Rnew = reg_to_register_object($exchange_value$$reg);
2338 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2339
2340 __ z_cs(Rcomp, Rnew, 0, Raddr);
2341 %}
2342
2343 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
2344 MacroAssembler _masm(&cbuf);
2345 Register Rcomp = reg_to_register_object($compare_value$$reg);
2346 Register Rnew = reg_to_register_object($exchange_value$$reg);
2347 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2348
2349 __ z_csg(Rcomp, Rnew, 0, Raddr);
2350 %}
2351
2352 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
2353 MacroAssembler _masm(&cbuf);
2354 Register Rdst = reg_to_register_object($dst$$reg);
2355 Register Rtmp = reg_to_register_object($tmp$$reg);
2356 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2357 Label retry;
2358
2359 // Iterate until swap succeeds.
2360 __ z_llgf(Rtmp, $mem$$Address); // current contents
2361 __ bind(retry);
2362 // Calculate incremented value.
2363 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2364 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2365 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2366 %}
2367
2368 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
2369 MacroAssembler _masm(&cbuf);
2370 Register Rdst = reg_to_register_object($dst$$reg);
2371 Register Rtmp = reg_to_register_object($tmp$$reg);
2372 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2373 Label retry;
2374
2375 // Iterate until swap succeeds.
2376 __ z_lg(Rtmp, $mem$$Address); // current contents
2377 __ bind(retry);
2378 // Calculate incremented value.
2379 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2380 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2381 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2382 %}
2383
2384 %} // encode
2385
2386 source %{
2387
2388 // Check whether outs are all Stores. If so, we can omit clearing the upper
2389 // 32 bits after encoding.
2390 static bool all_outs_are_Stores(const Node *n) {
2391 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
2392 Node *out = n->fast_out(k);
2393 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
2394 // Most other outs are SpillCopy, but there are various other.
2395 // jvm98 has arond 9% Encodes where we return false.
2396 return false;
2397 }
2398 }
2399 return true;
2400 }
2401
2402 %} // source
2403
2404
2405 //----------FRAME--------------------------------------------------------------
2406 // Definition of frame structure and management information.
2407
2408 frame %{
2409 // What direction does stack grow in (assumed to be same for native & Java).
2410 stack_direction(TOWARDS_LOW);
2411
2412 // These two registers define part of the calling convention between
2413 // compiled code and the interpreter.
2414
2415 // Inline Cache Register
2416 inline_cache_reg(Z_R9); // Z_inline_cache
2417
2418 // Argument pointer for I2C adapters
2419 //
2420 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
2421 // interpreter_arg_ptr_reg(Z_R6);
2422
2423 // Temporary in compiled entry-points
2424 // compiler_method_oop_reg(Z_R1);//Z_R1_scratch
2425
2426 // Method Oop Register when calling interpreter
2427 interpreter_method_oop_reg(Z_R9);//Z_method
2428
2429 // Optional: name the operand used by cisc-spilling to access
2430 // [stack_pointer + offset].
2431 cisc_spilling_operand_name(indOffset12);
2432
2433 // Number of stack slots consumed by a Monitor enter.
2434 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
2435
2436 // Compiled code's Frame Pointer
2437 //
2438 // z/Architecture stack pointer
2439 frame_pointer(Z_R15); // Z_SP
2440
2441 // Interpreter stores its frame pointer in a register which is
2442 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
2443 // interpreted java to compiled java.
2444 //
2445 // Z_state holds pointer to caller's cInterpreter.
2446 interpreter_frame_pointer(Z_R7); // Z_state
2447
2448 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
2449 stack_alignment(frame::alignment_in_bytes);
2450
2451 in_preserve_stack_slots(frame::jit_in_preserve_size_in_4_byte_units);
2452
2453 // A `slot' is assumed 4 bytes here!
2454 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
2455
2456 // Number of outgoing stack slots killed above the
2457 // out_preserve_stack_slots for calls to C. Supports the var-args
2458 // backing area for register parms.
2459 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
2460
2461 // The after-PROLOG location of the return address. Location of
2462 // return address specifies a type (REG or STACK) and a number
2463 // representing the register number (i.e. - use a register name) or
2464 // stack slot.
2465 return_addr(REG Z_R14);
2466
2467 // This is the body of the function
2468 //
2469 // void Matcher::calling_convention(OptoRegPair* sig /* array of ideal regs */,
2470 // uint length /* length of array */,
2471 // bool is_outgoing)
2472 //
2473 // The `sig' array is to be updated. Sig[j] represents the location
2474 // of the j-th argument, either a register or a stack slot.
2475
2476 // Body of function which returns an integer array locating
2477 // arguments either in registers or in stack slots. Passed an array
2478 // of ideal registers called "sig" and a "length" count. Stack-slot
2479 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2480 // arguments for a CALLEE. Incoming stack arguments are
2481 // automatically biased by the preserve_stack_slots field above.
2482 calling_convention %{
2483 // No difference between ingoing/outgoing just pass false.
2484 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2485 %}
2486
2487 // Body of function which returns an integer array locating
2488 // arguments either in registers or in stack slots. Passed an array
2489 // of ideal registers called "sig" and a "length" count. Stack-slot
2490 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2491 // arguments for a CALLEE. Incoming stack arguments are
2492 // automatically biased by the preserve_stack_slots field above.
2493 c_calling_convention %{
2494 // This is obviously always outgoing.
2495 // C argument must be in register AND stack slot.
2496 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2497 %}
2498
2499 // Location of native (C/C++) and interpreter return values. This
2500 // is specified to be the same as Java. In the 32-bit VM, long
2501 // values are actually returned from native calls in O0:O1 and
2502 // returned to the interpreter in I0:I1. The copying to and from
2503 // the register pairs is done by the appropriate call and epilog
2504 // opcodes. This simplifies the register allocator.
2505 //
2506 // Use register pair for c return value.
2507 c_return_value %{
2508 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2509 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2510 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2511 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2512 %}
2513
2514 // Use register pair for return value.
2515 // Location of compiled Java return values. Same as C
2516 return_value %{
2517 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2518 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2519 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2520 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2521 %}
2522 %}
2523
2524
2525 //----------ATTRIBUTES---------------------------------------------------------
2526
2527 //----------Operand Attributes-------------------------------------------------
2528 op_attrib op_cost(1); // Required cost attribute
2529
2530 //----------Instruction Attributes---------------------------------------------
2531
2532 // Cost attribute. required.
2533 ins_attrib ins_cost(DEFAULT_COST);
2534
2535 // Is this instruction a non-matching short branch variant of some
2536 // long branch? Not required.
2537 ins_attrib ins_short_branch(0);
2538
2539 // Indicates this is a trap based check node and final control-flow fixup
2540 // must generate a proper fall through.
2541 ins_attrib ins_is_TrapBasedCheckNode(true);
2542
2543 // Attribute of instruction to tell how many constants the instruction will generate.
2544 // (optional attribute). Default: 0.
2545 ins_attrib ins_num_consts(0);
2546
2547 // Required alignment attribute (must be a power of 2)
2548 // specifies the alignment that some part of the instruction (not
2549 // necessarily the start) requires. If > 1, a compute_padding()
2550 // function must be provided for the instruction.
2551 //
2552 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
2553 // instructions which depend on the proper alignment, because the
2554 // desired alignment isn't guaranteed for the call to "emit()" during
2555 // the size computation.
2556 ins_attrib ins_alignment(1);
2557
2558 // Enforce/prohibit rematerializations.
2559 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
2560 // then rematerialization of that instruction is prohibited and the
2561 // instruction's value will be spilled if necessary.
2562 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
2563 // then rematerialization is enforced and the instruction's value will
2564 // never get spilled. a copy of the instruction will be inserted if
2565 // necessary.
2566 // Note: this may result in rematerializations in front of every use.
2567 // (optional attribute)
2568 ins_attrib ins_cannot_rematerialize(false);
2569 ins_attrib ins_should_rematerialize(false);
2570
2571 //----------OPERANDS-----------------------------------------------------------
2572 // Operand definitions must precede instruction definitions for correct
2573 // parsing in the ADLC because operands constitute user defined types
2574 // which are used in instruction definitions.
2575
2576 //----------Simple Operands----------------------------------------------------
2577 // Immediate Operands
2578 // Please note:
2579 // Formats are generated automatically for constants and base registers.
2580
2581 //----------------------------------------------
2582 // SIGNED (shorter than INT) immediate operands
2583 //----------------------------------------------
2584
2585 // Byte Immediate: constant 'int -1'
2586 operand immB_minus1() %{
2587 // sign-ext constant zero-ext constant
2588 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
2589 match(ConI);
2590 op_cost(1);
2591 format %{ %}
2592 interface(CONST_INTER);
2593 %}
2594
2595 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
2596 operand immB_n0m1() %{
2597 // sign-ext constant zero-ext constant
2598 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
2599 match(ConI);
2600 op_cost(1);
2601 format %{ %}
2602 interface(CONST_INTER);
2603 %}
2604
2605 // Short Immediate: constant 'int -1'
2606 operand immS_minus1() %{
2607 // sign-ext constant zero-ext constant
2608 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
2609 match(ConI);
2610 op_cost(1);
2611 format %{ %}
2612 interface(CONST_INTER);
2613 %}
2614
2615 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
2616 operand immS_n0m1() %{
2617 // sign-ext constant zero-ext constant
2618 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
2619 match(ConI);
2620 op_cost(1);
2621 format %{ %}
2622 interface(CONST_INTER);
2623 %}
2624
2625 //-----------------------------------------
2626 // SIGNED INT immediate operands
2627 //-----------------------------------------
2628
2629 // Integer Immediate: 32-bit
2630 operand immI() %{
2631 match(ConI);
2632 op_cost(1);
2633 format %{ %}
2634 interface(CONST_INTER);
2635 %}
2636
2637 // Int Immediate: 20-bit
2638 operand immI20() %{
2639 predicate(Immediate::is_simm20(n->get_int()));
2640 match(ConI);
2641 op_cost(1);
2642 format %{ %}
2643 interface(CONST_INTER);
2644 %}
2645
2646 // Integer Immediate: 16-bit
2647 operand immI16() %{
2648 predicate(Immediate::is_simm16(n->get_int()));
2649 match(ConI);
2650 op_cost(1);
2651 format %{ %}
2652 interface(CONST_INTER);
2653 %}
2654
2655 // Integer Immediate: 8-bit
2656 operand immI8() %{
2657 predicate(Immediate::is_simm8(n->get_int()));
2658 match(ConI);
2659 op_cost(1);
2660 format %{ %}
2661 interface(CONST_INTER);
2662 %}
2663
2664 // Integer Immediate: constant 'int 0'
2665 operand immI_0() %{
2666 predicate(n->get_int() == 0);
2667 match(ConI);
2668 op_cost(1);
2669 format %{ %}
2670 interface(CONST_INTER);
2671 %}
2672
2673 // Integer Immediate: constant 'int -1'
2674 operand immI_minus1() %{
2675 predicate(n->get_int() == -1);
2676 match(ConI);
2677 op_cost(1);
2678 format %{ %}
2679 interface(CONST_INTER);
2680 %}
2681
2682 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
2683 operand immI_n0m1() %{
2684 predicate(n->get_int() != 0 && n->get_int() != -1);
2685 match(ConI);
2686 op_cost(1);
2687 format %{ %}
2688 interface(CONST_INTER);
2689 %}
2690
2691 //-------------------------------------------
2692 // UNSIGNED INT immediate operands
2693 //-------------------------------------------
2694
2695 // Unsigned Integer Immediate: 32-bit
2696 operand uimmI() %{
2697 match(ConI);
2698 op_cost(1);
2699 format %{ %}
2700 interface(CONST_INTER);
2701 %}
2702
2703 // Unsigned Integer Immediate: 16-bit
2704 operand uimmI16() %{
2705 predicate(Immediate::is_uimm16(n->get_int()));
2706 match(ConI);
2707 op_cost(1);
2708 format %{ %}
2709 interface(CONST_INTER);
2710 %}
2711
2712 // Unsigned Integer Immediate: 12-bit
2713 operand uimmI12() %{
2714 predicate(Immediate::is_uimm12(n->get_int()));
2715 match(ConI);
2716 op_cost(1);
2717 format %{ %}
2718 interface(CONST_INTER);
2719 %}
2720
2721 // Unsigned Integer Immediate: 12-bit
2722 operand uimmI8() %{
2723 predicate(Immediate::is_uimm8(n->get_int()));
2724 match(ConI);
2725 op_cost(1);
2726 format %{ %}
2727 interface(CONST_INTER);
2728 %}
2729
2730 // Integer Immediate: 6-bit
2731 operand uimmI6() %{
2732 predicate(Immediate::is_uimm(n->get_int(), 6));
2733 match(ConI);
2734 op_cost(1);
2735 format %{ %}
2736 interface(CONST_INTER);
2737 %}
2738
2739 // Integer Immediate: 5-bit
2740 operand uimmI5() %{
2741 predicate(Immediate::is_uimm(n->get_int(), 5));
2742 match(ConI);
2743 op_cost(1);
2744 format %{ %}
2745 interface(CONST_INTER);
2746 %}
2747
2748 // Length for SS instructions, given in DWs,
2749 // possible range [1..512], i.e. [8..4096] Bytes
2750 // used range [1..256], i.e. [8..2048] Bytes
2751 // operand type int
2752 // Unsigned Integer Immediate: 9-bit
2753 operand SSlenDW() %{
2754 predicate(Immediate::is_uimm8(n->get_long()-1));
2755 match(ConL);
2756 op_cost(1);
2757 format %{ %}
2758 interface(CONST_INTER);
2759 %}
2760
2761 //------------------------------------------
2762 // (UN)SIGNED INT specific values
2763 //------------------------------------------
2764
2765 // Integer Immediate: the value 1
2766 operand immI_1() %{
2767 predicate(n->get_int() == 1);
2768 match(ConI);
2769 op_cost(1);
2770 format %{ %}
2771 interface(CONST_INTER);
2772 %}
2773
2774 // Integer Immediate: the value 16.
2775 operand immI_16() %{
2776 predicate(n->get_int() == 16);
2777 match(ConI);
2778 op_cost(1);
2779 format %{ %}
2780 interface(CONST_INTER);
2781 %}
2782
2783 // Integer Immediate: the value 24.
2784 operand immI_24() %{
2785 predicate(n->get_int() == 24);
2786 match(ConI);
2787 op_cost(1);
2788 format %{ %}
2789 interface(CONST_INTER);
2790 %}
2791
2792 // Integer Immediate: the value 255
2793 operand immI_255() %{
2794 predicate(n->get_int() == 255);
2795 match(ConI);
2796 op_cost(1);
2797 format %{ %}
2798 interface(CONST_INTER);
2799 %}
2800
2801 // Integer Immediate: the values 32-63
2802 operand immI_32_63() %{
2803 predicate(n->get_int() >= 32 && n->get_int() <= 63);
2804 match(ConI);
2805 op_cost(1);
2806 format %{ %}
2807 interface(CONST_INTER);
2808 %}
2809
2810 // Unsigned Integer Immediate: LL-part, extended by 1s.
2811 operand uimmI_LL1() %{
2812 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
2813 match(ConI);
2814 op_cost(1);
2815 format %{ %}
2816 interface(CONST_INTER);
2817 %}
2818
2819 // Unsigned Integer Immediate: LH-part, extended by 1s.
2820 operand uimmI_LH1() %{
2821 predicate((n->get_int() & 0xFFFF) == 0xFFFF);
2822 match(ConI);
2823 op_cost(1);
2824 format %{ %}
2825 interface(CONST_INTER);
2826 %}
2827
2828 //------------------------------------------
2829 // SIGNED LONG immediate operands
2830 //------------------------------------------
2831
2832 operand immL() %{
2833 match(ConL);
2834 op_cost(1);
2835 format %{ %}
2836 interface(CONST_INTER);
2837 %}
2838
2839 // Long Immediate: 32-bit
2840 operand immL32() %{
2841 predicate(Immediate::is_simm32(n->get_long()));
2842 match(ConL);
2843 op_cost(1);
2844 format %{ %}
2845 interface(CONST_INTER);
2846 %}
2847
2848 // Long Immediate: 20-bit
2849 operand immL20() %{
2850 predicate(Immediate::is_simm20(n->get_long()));
2851 match(ConL);
2852 op_cost(1);
2853 format %{ %}
2854 interface(CONST_INTER);
2855 %}
2856
2857 // Long Immediate: 16-bit
2858 operand immL16() %{
2859 predicate(Immediate::is_simm16(n->get_long()));
2860 match(ConL);
2861 op_cost(1);
2862 format %{ %}
2863 interface(CONST_INTER);
2864 %}
2865
2866 // Long Immediate: 8-bit
2867 operand immL8() %{
2868 predicate(Immediate::is_simm8(n->get_long()));
2869 match(ConL);
2870 op_cost(1);
2871 format %{ %}
2872 interface(CONST_INTER);
2873 %}
2874
2875 //--------------------------------------------
2876 // UNSIGNED LONG immediate operands
2877 //--------------------------------------------
2878
2879 operand uimmL32() %{
2880 predicate(Immediate::is_uimm32(n->get_long()));
2881 match(ConL);
2882 op_cost(1);
2883 format %{ %}
2884 interface(CONST_INTER);
2885 %}
2886
2887 // Unsigned Long Immediate: 16-bit
2888 operand uimmL16() %{
2889 predicate(Immediate::is_uimm16(n->get_long()));
2890 match(ConL);
2891 op_cost(1);
2892 format %{ %}
2893 interface(CONST_INTER);
2894 %}
2895
2896 // Unsigned Long Immediate: 12-bit
2897 operand uimmL12() %{
2898 predicate(Immediate::is_uimm12(n->get_long()));
2899 match(ConL);
2900 op_cost(1);
2901 format %{ %}
2902 interface(CONST_INTER);
2903 %}
2904
2905 // Unsigned Long Immediate: 8-bit
2906 operand uimmL8() %{
2907 predicate(Immediate::is_uimm8(n->get_long()));
2908 match(ConL);
2909 op_cost(1);
2910 format %{ %}
2911 interface(CONST_INTER);
2912 %}
2913
2914 //-------------------------------------------
2915 // (UN)SIGNED LONG specific values
2916 //-------------------------------------------
2917
2918 // Long Immediate: the value FF
2919 operand immL_FF() %{
2920 predicate(n->get_long() == 0xFFL);
2921 match(ConL);
2922 op_cost(1);
2923 format %{ %}
2924 interface(CONST_INTER);
2925 %}
2926
2927 // Long Immediate: the value FFFF
2928 operand immL_FFFF() %{
2929 predicate(n->get_long() == 0xFFFFL);
2930 match(ConL);
2931 op_cost(1);
2932 format %{ %}
2933 interface(CONST_INTER);
2934 %}
2935
2936 // Long Immediate: the value FFFFFFFF
2937 operand immL_FFFFFFFF() %{
2938 predicate(n->get_long() == 0xFFFFFFFFL);
2939 match(ConL);
2940 op_cost(1);
2941 format %{ %}
2942 interface(CONST_INTER);
2943 %}
2944
2945 operand immL_0() %{
2946 predicate(n->get_long() == 0L);
2947 match(ConL);
2948 op_cost(1);
2949 format %{ %}
2950 interface(CONST_INTER);
2951 %}
2952
2953 // Unsigned Long Immediate: LL-part, extended by 1s.
2954 operand uimmL_LL1() %{
2955 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
2956 match(ConL);
2957 op_cost(1);
2958 format %{ %}
2959 interface(CONST_INTER);
2960 %}
2961
2962 // Unsigned Long Immediate: LH-part, extended by 1s.
2963 operand uimmL_LH1() %{
2964 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
2965 match(ConL);
2966 op_cost(1);
2967 format %{ %}
2968 interface(CONST_INTER);
2969 %}
2970
2971 // Unsigned Long Immediate: HL-part, extended by 1s.
2972 operand uimmL_HL1() %{
2973 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
2974 match(ConL);
2975 op_cost(1);
2976 format %{ %}
2977 interface(CONST_INTER);
2978 %}
2979
2980 // Unsigned Long Immediate: HH-part, extended by 1s.
2981 operand uimmL_HH1() %{
2982 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
2983 match(ConL);
2984 op_cost(1);
2985 format %{ %}
2986 interface(CONST_INTER);
2987 %}
2988
2989 // Long Immediate: low 32-bit mask
2990 operand immL_32bits() %{
2991 predicate(n->get_long() == 0xFFFFFFFFL);
2992 match(ConL);
2993 op_cost(1);
2994 format %{ %}
2995 interface(CONST_INTER);
2996 %}
2997
2998 //--------------------------------------
2999 // POINTER immediate operands
3000 //--------------------------------------
3001
3002 // Pointer Immediate: 64-bit
3003 operand immP() %{
3004 match(ConP);
3005 op_cost(1);
3006 format %{ %}
3007 interface(CONST_INTER);
3008 %}
3009
3010 // Pointer Immediate: 32-bit
3011 operand immP32() %{
3012 predicate(Immediate::is_uimm32(n->get_ptr()));
3013 match(ConP);
3014 op_cost(1);
3015 format %{ %}
3016 interface(CONST_INTER);
3017 %}
3018
3019 // Pointer Immediate: 16-bit
3020 operand immP16() %{
3021 predicate(Immediate::is_uimm16(n->get_ptr()));
3022 match(ConP);
3023 op_cost(1);
3024 format %{ %}
3025 interface(CONST_INTER);
3026 %}
3027
3028 // Pointer Immediate: 8-bit
3029 operand immP8() %{
3030 predicate(Immediate::is_uimm8(n->get_ptr()));
3031 match(ConP);
3032 op_cost(1);
3033 format %{ %}
3034 interface(CONST_INTER);
3035 %}
3036
3037 //-----------------------------------
3038 // POINTER specific values
3039 //-----------------------------------
3040
3041 // Pointer Immediate: NULL
3042 operand immP0() %{
3043 predicate(n->get_ptr() == 0);
3044 match(ConP);
3045 op_cost(1);
3046 format %{ %}
3047 interface(CONST_INTER);
3048 %}
3049
3050 //---------------------------------------------
3051 // NARROW POINTER immediate operands
3052 //---------------------------------------------
3053
3054 // Narrow Pointer Immediate
3055 operand immN() %{
3056 match(ConN);
3057 op_cost(1);
3058 format %{ %}
3059 interface(CONST_INTER);
3060 %}
3061
3062 operand immNKlass() %{
3063 match(ConNKlass);
3064 op_cost(1);
3065 format %{ %}
3066 interface(CONST_INTER);
3067 %}
3068
3069 // Narrow Pointer Immediate
3070 operand immN8() %{
3071 predicate(Immediate::is_uimm8(n->get_narrowcon()));
3072 match(ConN);
3073 op_cost(1);
3074 format %{ %}
3075 interface(CONST_INTER);
3076 %}
3077
3078 // Narrow NULL Pointer Immediate
3079 operand immN0() %{
3080 predicate(n->get_narrowcon() == 0);
3081 match(ConN);
3082 op_cost(1);
3083 format %{ %}
3084 interface(CONST_INTER);
3085 %}
3086
3087 // FLOAT and DOUBLE immediate operands
3088
3089 // Double Immediate
3090 operand immD() %{
3091 match(ConD);
3092 op_cost(1);
3093 format %{ %}
3094 interface(CONST_INTER);
3095 %}
3096
3097 // Double Immediate: +-0
3098 operand immDpm0() %{
3099 predicate(n->getd() == 0);
3100 match(ConD);
3101 op_cost(1);
3102 format %{ %}
3103 interface(CONST_INTER);
3104 %}
3105
3106 // Double Immediate: +0
3107 operand immDp0() %{
3108 predicate(jlong_cast(n->getd()) == 0);
3109 match(ConD);
3110 op_cost(1);
3111 format %{ %}
3112 interface(CONST_INTER);
3113 %}
3114
3115 // Float Immediate
3116 operand immF() %{
3117 match(ConF);
3118 op_cost(1);
3119 format %{ %}
3120 interface(CONST_INTER);
3121 %}
3122
3123 // Float Immediate: +-0
3124 operand immFpm0() %{
3125 predicate(n->getf() == 0);
3126 match(ConF);
3127 op_cost(1);
3128 format %{ %}
3129 interface(CONST_INTER);
3130 %}
3131
3132 // Float Immediate: +0
3133 operand immFp0() %{
3134 predicate(jint_cast(n->getf()) == 0);
3135 match(ConF);
3136 op_cost(1);
3137 format %{ %}
3138 interface(CONST_INTER);
3139 %}
3140
3141 // End of Immediate Operands
3142
3143 // Integer Register Operands
3144 // Integer Register
3145 operand iRegI() %{
3146 constraint(ALLOC_IN_RC(z_int_reg));
3147 match(RegI);
3148 match(noArg_iRegI);
3149 match(rarg1RegI);
3150 match(rarg2RegI);
3151 match(rarg3RegI);
3152 match(rarg4RegI);
3153 match(rarg5RegI);
3154 match(noOdd_iRegI);
3155 match(revenRegI);
3156 match(roddRegI);
3157 format %{ %}
3158 interface(REG_INTER);
3159 %}
3160
3161 operand noArg_iRegI() %{
3162 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3163 match(RegI);
3164 format %{ %}
3165 interface(REG_INTER);
3166 %}
3167
3168 // revenRegI and roddRegI constitute and even-odd-pair.
3169 operand revenRegI() %{
3170 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3171 match(iRegI);
3172 format %{ %}
3173 interface(REG_INTER);
3174 %}
3175
3176 // revenRegI and roddRegI constitute and even-odd-pair.
3177 operand roddRegI() %{
3178 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3179 match(iRegI);
3180 format %{ %}
3181 interface(REG_INTER);
3182 %}
3183
3184 operand rarg1RegI() %{
3185 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3186 match(iRegI);
3187 format %{ %}
3188 interface(REG_INTER);
3189 %}
3190
3191 operand rarg2RegI() %{
3192 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3193 match(iRegI);
3194 format %{ %}
3195 interface(REG_INTER);
3196 %}
3197
3198 operand rarg3RegI() %{
3199 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3200 match(iRegI);
3201 format %{ %}
3202 interface(REG_INTER);
3203 %}
3204
3205 operand rarg4RegI() %{
3206 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3207 match(iRegI);
3208 format %{ %}
3209 interface(REG_INTER);
3210 %}
3211
3212 operand rarg5RegI() %{
3213 constraint(ALLOC_IN_RC(z_rarg5_int_reg));
3214 match(iRegI);
3215 format %{ %}
3216 interface(REG_INTER);
3217 %}
3218
3219 operand noOdd_iRegI() %{
3220 constraint(ALLOC_IN_RC(z_no_odd_int_reg));
3221 match(RegI);
3222 match(revenRegI);
3223 format %{ %}
3224 interface(REG_INTER);
3225 %}
3226
3227 // Pointer Register
3228 operand iRegP() %{
3229 constraint(ALLOC_IN_RC(z_ptr_reg));
3230 match(RegP);
3231 match(noArg_iRegP);
3232 match(rarg1RegP);
3233 match(rarg2RegP);
3234 match(rarg3RegP);
3235 match(rarg4RegP);
3236 match(rarg5RegP);
3237 match(revenRegP);
3238 match(roddRegP);
3239 format %{ %}
3240 interface(REG_INTER);
3241 %}
3242
3243 // thread operand
3244 operand threadRegP() %{
3245 constraint(ALLOC_IN_RC(z_thread_ptr_reg));
3246 match(RegP);
3247 format %{ "Z_THREAD" %}
3248 interface(REG_INTER);
3249 %}
3250
3251 operand noArg_iRegP() %{
3252 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
3253 match(iRegP);
3254 format %{ %}
3255 interface(REG_INTER);
3256 %}
3257
3258 operand rarg1RegP() %{
3259 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
3260 match(iRegP);
3261 format %{ %}
3262 interface(REG_INTER);
3263 %}
3264
3265 operand rarg2RegP() %{
3266 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
3267 match(iRegP);
3268 format %{ %}
3269 interface(REG_INTER);
3270 %}
3271
3272 operand rarg3RegP() %{
3273 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3274 match(iRegP);
3275 format %{ %}
3276 interface(REG_INTER);
3277 %}
3278
3279 operand rarg4RegP() %{
3280 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3281 match(iRegP);
3282 format %{ %}
3283 interface(REG_INTER);
3284 %}
3285
3286 operand rarg5RegP() %{
3287 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
3288 match(iRegP);
3289 format %{ %}
3290 interface(REG_INTER);
3291 %}
3292
3293 operand memoryRegP() %{
3294 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3295 match(RegP);
3296 match(iRegP);
3297 match(threadRegP);
3298 format %{ %}
3299 interface(REG_INTER);
3300 %}
3301
3302 // revenRegP and roddRegP constitute and even-odd-pair.
3303 operand revenRegP() %{
3304 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3305 match(iRegP);
3306 format %{ %}
3307 interface(REG_INTER);
3308 %}
3309
3310 // revenRegP and roddRegP constitute and even-odd-pair.
3311 operand roddRegP() %{
3312 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3313 match(iRegP);
3314 format %{ %}
3315 interface(REG_INTER);
3316 %}
3317
3318 operand lock_ptr_RegP() %{
3319 constraint(ALLOC_IN_RC(z_lock_ptr_reg));
3320 match(RegP);
3321 format %{ %}
3322 interface(REG_INTER);
3323 %}
3324
3325 operand rscratch2RegP() %{
3326 constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg));
3327 match(RegP);
3328 format %{ %}
3329 interface(REG_INTER);
3330 %}
3331
3332 operand iRegN() %{
3333 constraint(ALLOC_IN_RC(z_int_reg));
3334 match(RegN);
3335 match(noArg_iRegN);
3336 match(rarg1RegN);
3337 match(rarg2RegN);
3338 match(rarg3RegN);
3339 match(rarg4RegN);
3340 match(rarg5RegN);
3341 format %{ %}
3342 interface(REG_INTER);
3343 %}
3344
3345 operand noArg_iRegN() %{
3346 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3347 match(iRegN);
3348 format %{ %}
3349 interface(REG_INTER);
3350 %}
3351
3352 operand rarg1RegN() %{
3353 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3354 match(iRegN);
3355 format %{ %}
3356 interface(REG_INTER);
3357 %}
3358
3359 operand rarg2RegN() %{
3360 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3361 match(iRegN);
3362 format %{ %}
3363 interface(REG_INTER);
3364 %}
3365
3366 operand rarg3RegN() %{
3367 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3368 match(iRegN);
3369 format %{ %}
3370 interface(REG_INTER);
3371 %}
3372
3373 operand rarg4RegN() %{
3374 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3375 match(iRegN);
3376 format %{ %}
3377 interface(REG_INTER);
3378 %}
3379
3380 operand rarg5RegN() %{
3381 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
3382 match(iRegN);
3383 format %{ %}
3384 interface(REG_INTER);
3385 %}
3386
3387 // Long Register
3388 operand iRegL() %{
3389 constraint(ALLOC_IN_RC(z_long_reg));
3390 match(RegL);
3391 match(revenRegL);
3392 match(roddRegL);
3393 match(allRoddRegL);
3394 match(rarg1RegL);
3395 match(rarg5RegL);
3396 format %{ %}
3397 interface(REG_INTER);
3398 %}
3399
3400 // revenRegL and roddRegL constitute and even-odd-pair.
3401 operand revenRegL() %{
3402 constraint(ALLOC_IN_RC(z_rarg3_long_reg));
3403 match(iRegL);
3404 format %{ %}
3405 interface(REG_INTER);
3406 %}
3407
3408 // revenRegL and roddRegL constitute and even-odd-pair.
3409 operand roddRegL() %{
3410 constraint(ALLOC_IN_RC(z_rarg4_long_reg));
3411 match(iRegL);
3412 format %{ %}
3413 interface(REG_INTER);
3414 %}
3415
3416 // available odd registers for iRegL
3417 operand allRoddRegL() %{
3418 constraint(ALLOC_IN_RC(z_long_odd_reg));
3419 match(iRegL);
3420 format %{ %}
3421 interface(REG_INTER);
3422 %}
3423
3424 operand rarg1RegL() %{
3425 constraint(ALLOC_IN_RC(z_rarg1_long_reg));
3426 match(iRegL);
3427 format %{ %}
3428 interface(REG_INTER);
3429 %}
3430
3431 operand rarg5RegL() %{
3432 constraint(ALLOC_IN_RC(z_rarg5_long_reg));
3433 match(iRegL);
3434 format %{ %}
3435 interface(REG_INTER);
3436 %}
3437
3438 // Condition Code Flag Registers
3439 operand flagsReg() %{
3440 constraint(ALLOC_IN_RC(z_condition_reg));
3441 match(RegFlags);
3442 format %{ "CR" %}
3443 interface(REG_INTER);
3444 %}
3445
3446 // Condition Code Flag Registers for rules with result tuples
3447 operand TD_flagsReg() %{
3448 constraint(ALLOC_IN_RC(z_condition_reg));
3449 match(RegFlags);
3450 format %{ "CR" %}
3451 interface(REG_TUPLE_DEST_INTER);
3452 %}
3453
3454 operand regD() %{
3455 constraint(ALLOC_IN_RC(z_dbl_reg));
3456 match(RegD);
3457 format %{ %}
3458 interface(REG_INTER);
3459 %}
3460
3461 operand rscratchRegD() %{
3462 constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg));
3463 match(RegD);
3464 format %{ %}
3465 interface(REG_INTER);
3466 %}
3467
3468 operand regF() %{
3469 constraint(ALLOC_IN_RC(z_flt_reg));
3470 match(RegF);
3471 format %{ %}
3472 interface(REG_INTER);
3473 %}
3474
3475 operand rscratchRegF() %{
3476 constraint(ALLOC_IN_RC(z_rscratch1_flt_reg));
3477 match(RegF);
3478 format %{ %}
3479 interface(REG_INTER);
3480 %}
3481
3482 // Special Registers
3483
3484 // Method Register
3485 operand inline_cache_regP(iRegP reg) %{
3486 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
3487 match(reg);
3488 format %{ %}
3489 interface(REG_INTER);
3490 %}
3491
3492 operand compiler_method_oop_regP(iRegP reg) %{
3493 constraint(ALLOC_IN_RC(z_r1_RegP)); // compiler_method_oop_reg
3494 match(reg);
3495 format %{ %}
3496 interface(REG_INTER);
3497 %}
3498
3499 operand interpreter_method_oop_regP(iRegP reg) %{
3500 constraint(ALLOC_IN_RC(z_r9_regP)); // interpreter_method_oop_reg
3501 match(reg);
3502 format %{ %}
3503 interface(REG_INTER);
3504 %}
3505
3506 // Operands to remove register moves in unscaled mode.
3507 // Match read/write registers with an EncodeP node if neither shift nor add are required.
3508 operand iRegP2N(iRegP reg) %{
3509 predicate(CompressedOops::shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL);
3510 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3511 match(EncodeP reg);
3512 format %{ "$reg" %}
3513 interface(REG_INTER)
3514 %}
3515
3516 operand iRegN2P(iRegN reg) %{
3517 predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0 &&
3518 _leaf->as_DecodeN()->in(0) == NULL);
3519 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3520 match(DecodeN reg);
3521 format %{ "$reg" %}
3522 interface(REG_INTER)
3523 %}
3524
3525
3526 //----------Complex Operands---------------------------------------------------
3527
3528 // Indirect Memory Reference
3529 operand indirect(memoryRegP base) %{
3530 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3531 match(base);
3532 op_cost(1);
3533 format %{ "#0[,$base]" %}
3534 interface(MEMORY_INTER) %{
3535 base($base);
3536 index(0xffffFFFF); // noreg
3537 scale(0x0);
3538 disp(0x0);
3539 %}
3540 %}
3541
3542 // Indirect with Offset (long)
3543 operand indOffset20(memoryRegP base, immL20 offset) %{
3544 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3545 match(AddP base offset);
3546 op_cost(1);
3547 format %{ "$offset[,$base]" %}
3548 interface(MEMORY_INTER) %{
3549 base($base);
3550 index(0xffffFFFF); // noreg
3551 scale(0x0);
3552 disp($offset);
3553 %}
3554 %}
3555
3556 operand indOffset20Narrow(iRegN base, immL20 offset) %{
3557 predicate(Matcher::narrow_oop_use_complex_address());
3558 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3559 match(AddP (DecodeN base) offset);
3560 op_cost(1);
3561 format %{ "$offset[,$base]" %}
3562 interface(MEMORY_INTER) %{
3563 base($base);
3564 index(0xffffFFFF); // noreg
3565 scale(0x0);
3566 disp($offset);
3567 %}
3568 %}
3569
3570 // Indirect with Offset (short)
3571 operand indOffset12(memoryRegP base, uimmL12 offset) %{
3572 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3573 match(AddP base offset);
3574 op_cost(1);
3575 format %{ "$offset[[,$base]]" %}
3576 interface(MEMORY_INTER) %{
3577 base($base);
3578 index(0xffffFFFF); // noreg
3579 scale(0x0);
3580 disp($offset);
3581 %}
3582 %}
3583
3584 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
3585 predicate(Matcher::narrow_oop_use_complex_address());
3586 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3587 match(AddP (DecodeN base) offset);
3588 op_cost(1);
3589 format %{ "$offset[[,$base]]" %}
3590 interface(MEMORY_INTER) %{
3591 base($base);
3592 index(0xffffFFFF); // noreg
3593 scale(0x0);
3594 disp($offset);
3595 %}
3596 %}
3597
3598 // Indirect with Register Index
3599 operand indIndex(memoryRegP base, iRegL index) %{
3600 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3601 match(AddP base index);
3602 op_cost(1);
3603 format %{ "#0[($index,$base)]" %}
3604 interface(MEMORY_INTER) %{
3605 base($base);
3606 index($index);
3607 scale(0x0);
3608 disp(0x0);
3609 %}
3610 %}
3611
3612 // Indirect with Offset (long) and index
3613 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
3614 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3615 match(AddP (AddP base index) offset);
3616 op_cost(1);
3617 format %{ "$offset[($index,$base)]" %}
3618 interface(MEMORY_INTER) %{
3619 base($base);
3620 index($index);
3621 scale(0x0);
3622 disp($offset);
3623 %}
3624 %}
3625
3626 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
3627 predicate(Matcher::narrow_oop_use_complex_address());
3628 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3629 match(AddP (AddP (DecodeN base) index) offset);
3630 op_cost(1);
3631 format %{ "$offset[($index,$base)]" %}
3632 interface(MEMORY_INTER) %{
3633 base($base);
3634 index($index);
3635 scale(0x0);
3636 disp($offset);
3637 %}
3638 %}
3639
3640 // Indirect with Offset (short) and index
3641 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
3642 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3643 match(AddP (AddP base index) offset);
3644 op_cost(1);
3645 format %{ "$offset[[($index,$base)]]" %}
3646 interface(MEMORY_INTER) %{
3647 base($base);
3648 index($index);
3649 scale(0x0);
3650 disp($offset);
3651 %}
3652 %}
3653
3654 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
3655 predicate(Matcher::narrow_oop_use_complex_address());
3656 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3657 match(AddP (AddP (DecodeN base) index) offset);
3658 op_cost(1);
3659 format %{ "$offset[[($index,$base)]]" %}
3660 interface(MEMORY_INTER) %{
3661 base($base);
3662 index($index);
3663 scale(0x0);
3664 disp($offset);
3665 %}
3666 %}
3667
3668 //----------Special Memory Operands--------------------------------------------
3669
3670 // Stack Slot Operand
3671 // This operand is used for loading and storing temporary values on
3672 // the stack where a match requires a value to flow through memory.
3673 operand stackSlotI(sRegI reg) %{
3674 constraint(ALLOC_IN_RC(stack_slots));
3675 op_cost(1);
3676 format %{ "[$reg(stackSlotI)]" %}
3677 interface(MEMORY_INTER) %{
3678 base(0xf); // Z_SP
3679 index(0xffffFFFF); // noreg
3680 scale(0x0);
3681 disp($reg); // stack offset
3682 %}
3683 %}
3684
3685 operand stackSlotP(sRegP reg) %{
3686 constraint(ALLOC_IN_RC(stack_slots));
3687 op_cost(1);
3688 format %{ "[$reg(stackSlotP)]" %}
3689 interface(MEMORY_INTER) %{
3690 base(0xf); // Z_SP
3691 index(0xffffFFFF); // noreg
3692 scale(0x0);
3693 disp($reg); // Stack Offset
3694 %}
3695 %}
3696
3697 operand stackSlotF(sRegF reg) %{
3698 constraint(ALLOC_IN_RC(stack_slots));
3699 op_cost(1);
3700 format %{ "[$reg(stackSlotF)]" %}
3701 interface(MEMORY_INTER) %{
3702 base(0xf); // Z_SP
3703 index(0xffffFFFF); // noreg
3704 scale(0x0);
3705 disp($reg); // Stack Offset
3706 %}
3707 %}
3708
3709 operand stackSlotD(sRegD reg) %{
3710 constraint(ALLOC_IN_RC(stack_slots));
3711 op_cost(1);
3712 //match(RegD);
3713 format %{ "[$reg(stackSlotD)]" %}
3714 interface(MEMORY_INTER) %{
3715 base(0xf); // Z_SP
3716 index(0xffffFFFF); // noreg
3717 scale(0x0);
3718 disp($reg); // Stack Offset
3719 %}
3720 %}
3721
3722 operand stackSlotL(sRegL reg) %{
3723 constraint(ALLOC_IN_RC(stack_slots));
3724 op_cost(1); //match(RegL);
3725 format %{ "[$reg(stackSlotL)]" %}
3726 interface(MEMORY_INTER) %{
3727 base(0xf); // Z_SP
3728 index(0xffffFFFF); // noreg
3729 scale(0x0);
3730 disp($reg); // Stack Offset
3731 %}
3732 %}
3733
3734 // Operands for expressing Control Flow
3735 // NOTE: Label is a predefined operand which should not be redefined in
3736 // the AD file. It is generically handled within the ADLC.
3737
3738 //----------Conditional Branch Operands----------------------------------------
3739 // Comparison Op - This is the operation of the comparison, and is limited to
3740 // the following set of codes:
3741 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3742 //
3743 // Other attributes of the comparison, such as unsignedness, are specified
3744 // by the comparison instruction that sets a condition code flags register.
3745 // That result is represented by a flags operand whose subtype is appropriate
3746 // to the unsignedness (etc.) of the comparison.
3747 //
3748 // Later, the instruction which matches both the Comparison Op (a Bool) and
3749 // the flags (produced by the Cmp) specifies the coding of the comparison op
3750 // by matching a specific subtype of Bool operand below.
3751
3752 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
3753 // have mask bit #3 set.
3754 operand cmpOpT() %{
3755 match(Bool);
3756 format %{ "" %}
3757 interface(COND_INTER) %{
3758 equal(0x8); // Assembler::bcondEqual
3759 not_equal(0x6); // Assembler::bcondNotEqual
3760 less(0x4); // Assembler::bcondLow
3761 greater_equal(0xa); // Assembler::bcondNotLow
3762 less_equal(0xc); // Assembler::bcondNotHigh
3763 greater(0x2); // Assembler::bcondHigh
3764 overflow(0x1); // Assembler::bcondOverflow
3765 no_overflow(0xe); // Assembler::bcondNotOverflow
3766 %}
3767 %}
3768
3769 // When used for floating point comparisons: unordered is treated as less.
3770 operand cmpOpF() %{
3771 match(Bool);
3772 format %{ "" %}
3773 interface(COND_INTER) %{
3774 equal(0x8);
3775 not_equal(0x7); // Includes 'unordered'.
3776 less(0x5); // Includes 'unordered'.
3777 greater_equal(0xa);
3778 less_equal(0xd); // Includes 'unordered'.
3779 greater(0x2);
3780 overflow(0x0); // Not meaningful on z/Architecture.
3781 no_overflow(0x0); // leave unchanged (zero) therefore
3782 %}
3783 %}
3784
3785 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
3786 operand cmpOp() %{
3787 match(Bool);
3788 format %{ "" %}
3789 interface(COND_INTER) %{
3790 equal(0x8);
3791 not_equal(0x7); // Includes 'unordered'.
3792 less(0x5); // Includes 'unordered'.
3793 greater_equal(0xa);
3794 less_equal(0xd); // Includes 'unordered'.
3795 greater(0x2);
3796 overflow(0x1); // Assembler::bcondOverflow
3797 no_overflow(0xe); // Assembler::bcondNotOverflow
3798 %}
3799 %}
3800
3801 //----------OPERAND CLASSES----------------------------------------------------
3802 // Operand Classes are groups of operands that are used to simplify
3803 // instruction definitions by not requiring the AD writer to specify
3804 // seperate instructions for every form of operand when the
3805 // instruction accepts multiple operand types with the same basic
3806 // encoding and format. The classic case of this is memory operands.
3807 // Indirect is not included since its use is limited to Compare & Swap
3808
3809 // Most general memory operand, allows base, index, and long displacement.
3810 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3811 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3812
3813 // General memory operand, allows base, index, and short displacement.
3814 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
3815
3816 // Memory operand, allows only base and long displacement.
3817 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
3818
3819 // Memory operand, allows only base and short displacement.
3820 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
3821
3822 // Operand classes to match encode and decode.
3823 opclass iRegN_P2N(iRegN);
3824 opclass iRegP_N2P(iRegP);
3825
3826
3827 //----------PIPELINE-----------------------------------------------------------
3828 pipeline %{
3829
3830 //----------ATTRIBUTES---------------------------------------------------------
3831 attributes %{
3832 // z/Architecture instructions are of length 2, 4, or 6 bytes.
3833 variable_size_instructions;
3834 instruction_unit_size = 2;
3835
3836 // Meaningless on z/Architecture.
3837 max_instructions_per_bundle = 1;
3838
3839 // The z/Architecture processor fetches 64 bytes...
3840 instruction_fetch_unit_size = 64;
3841
3842 // ...in one line.
3843 instruction_fetch_units = 1
3844 %}
3845
3846 //----------RESOURCES----------------------------------------------------------
3847 // Resources are the functional units available to the machine.
3848 resources(
3849 Z_BR, // branch unit
3850 Z_CR, // condition unit
3851 Z_FX1, // integer arithmetic unit 1
3852 Z_FX2, // integer arithmetic unit 2
3853 Z_LDST1, // load/store unit 1
3854 Z_LDST2, // load/store unit 2
3855 Z_FP1, // float arithmetic unit 1
3856 Z_FP2, // float arithmetic unit 2
3857 Z_LDST = Z_LDST1 | Z_LDST2,
3858 Z_FX = Z_FX1 | Z_FX2,
3859 Z_FP = Z_FP1 | Z_FP2
3860 );
3861
3862 //----------PIPELINE DESCRIPTION-----------------------------------------------
3863 // Pipeline Description specifies the stages in the machine's pipeline.
3864 pipe_desc(
3865 // TODO: adapt
3866 Z_IF, // instruction fetch
3867 Z_IC,
3868 Z_D0, // decode
3869 Z_D1, // decode
3870 Z_D2, // decode
3871 Z_D3, // decode
3872 Z_Xfer1,
3873 Z_GD, // group definition
3874 Z_MP, // map
3875 Z_ISS, // issue
3876 Z_RF, // resource fetch
3877 Z_EX1, // execute (all units)
3878 Z_EX2, // execute (FP, LDST)
3879 Z_EX3, // execute (FP, LDST)
3880 Z_EX4, // execute (FP)
3881 Z_EX5, // execute (FP)
3882 Z_EX6, // execute (FP)
3883 Z_WB, // write back
3884 Z_Xfer2,
3885 Z_CP
3886 );
3887
3888 //----------PIPELINE CLASSES---------------------------------------------------
3889 // Pipeline Classes describe the stages in which input and output are
3890 // referenced by the hardware pipeline.
3891
3892 // Providing the `ins_pipe' declarations in the instruction
3893 // specifications seems to be of little use. So we use
3894 // `pipe_class_dummy' for all our instructions at present.
3895 pipe_class pipe_class_dummy() %{
3896 single_instruction;
3897 fixed_latency(4);
3898 %}
3899
3900 // SIGTRAP based implicit range checks in compiled code.
3901 // Currently, no pipe classes are used on z/Architecture.
3902 pipe_class pipe_class_trap() %{
3903 single_instruction;
3904 %}
3905
3906 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
3907 single_instruction;
3908 dst : Z_EX1(write);
3909 src1 : Z_RF(read);
3910 src2 : Z_RF(read);
3911 Z_FX : Z_RF;
3912 %}
3913
3914 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
3915 single_instruction;
3916 mem : Z_RF(read);
3917 dst : Z_WB(write);
3918 Z_LDST : Z_RF;
3919 %}
3920
3921 define %{
3922 MachNop = pipe_class_dummy;
3923 %}
3924
3925 %}
3926
3927 //----------INSTRUCTIONS-------------------------------------------------------
3928
3929 //---------- Chain stack slots between similar types --------
3930
3931 // Load integer from stack slot.
3932 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
3933 match(Set dst src);
3934 ins_cost(MEMORY_REF_COST);
3935 // TODO: s390 port size(FIXED_SIZE);
3936 format %{ "L $dst,$src\t # stk reload int" %}
3937 opcode(L_ZOPC);
3938 ins_encode(z_form_rt_mem(dst, src));
3939 ins_pipe(pipe_class_dummy);
3940 %}
3941
3942 // Store integer to stack slot.
3943 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
3944 match(Set dst src);
3945 ins_cost(MEMORY_REF_COST);
3946 // TODO: s390 port size(FIXED_SIZE);
3947 format %{ "ST $src,$dst\t # stk spill int" %}
3948 opcode(ST_ZOPC);
3949 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3950 ins_pipe(pipe_class_dummy);
3951 %}
3952
3953 // Load long from stack slot.
3954 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
3955 match(Set dst src);
3956 ins_cost(MEMORY_REF_COST);
3957 // TODO: s390 port size(FIXED_SIZE);
3958 format %{ "LG $dst,$src\t # stk reload long" %}
3959 opcode(LG_ZOPC);
3960 ins_encode(z_form_rt_mem(dst, src));
3961 ins_pipe(pipe_class_dummy);
3962 %}
3963
3964 // Store long to stack slot.
3965 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
3966 match(Set dst src);
3967 ins_cost(MEMORY_REF_COST);
3968 size(6);
3969 format %{ "STG $src,$dst\t # stk spill long" %}
3970 opcode(STG_ZOPC);
3971 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3972 ins_pipe(pipe_class_dummy);
3973 %}
3974
3975 // Load pointer from stack slot, 64-bit encoding.
3976 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
3977 match(Set dst src);
3978 ins_cost(MEMORY_REF_COST);
3979 // TODO: s390 port size(FIXED_SIZE);
3980 format %{ "LG $dst,$src\t # stk reload ptr" %}
3981 opcode(LG_ZOPC);
3982 ins_encode(z_form_rt_mem(dst, src));
3983 ins_pipe(pipe_class_dummy);
3984 %}
3985
3986 // Store pointer to stack slot.
3987 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
3988 match(Set dst src);
3989 ins_cost(MEMORY_REF_COST);
3990 // TODO: s390 port size(FIXED_SIZE);
3991 format %{ "STG $src,$dst\t # stk spill ptr" %}
3992 opcode(STG_ZOPC);
3993 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3994 ins_pipe(pipe_class_dummy);
3995 %}
3996
3997 // Float types
3998
3999 // Load float value from stack slot.
4000 instruct stkF_to_regF(regF dst, stackSlotF src) %{
4001 match(Set dst src);
4002 ins_cost(MEMORY_REF_COST);
4003 size(4);
4004 format %{ "LE(Y) $dst,$src\t # stk reload float" %}
4005 opcode(LE_ZOPC);
4006 ins_encode(z_form_rt_mem(dst, src));
4007 ins_pipe(pipe_class_dummy);
4008 %}
4009
4010 // Store float value to stack slot.
4011 instruct regF_to_stkF(stackSlotF dst, regF src) %{
4012 match(Set dst src);
4013 ins_cost(MEMORY_REF_COST);
4014 size(4);
4015 format %{ "STE(Y) $src,$dst\t # stk spill float" %}
4016 opcode(STE_ZOPC);
4017 ins_encode(z_form_rt_mem(src, dst));
4018 ins_pipe(pipe_class_dummy);
4019 %}
4020
4021 // Load double value from stack slot.
4022 instruct stkD_to_regD(regD dst, stackSlotD src) %{
4023 match(Set dst src);
4024 ins_cost(MEMORY_REF_COST);
4025 // TODO: s390 port size(FIXED_SIZE);
4026 format %{ "LD(Y) $dst,$src\t # stk reload double" %}
4027 opcode(LD_ZOPC);
4028 ins_encode(z_form_rt_mem(dst, src));
4029 ins_pipe(pipe_class_dummy);
4030 %}
4031
4032 // Store double value to stack slot.
4033 instruct regD_to_stkD(stackSlotD dst, regD src) %{
4034 match(Set dst src);
4035 ins_cost(MEMORY_REF_COST);
4036 size(4);
4037 format %{ "STD(Y) $src,$dst\t # stk spill double" %}
4038 opcode(STD_ZOPC);
4039 ins_encode(z_form_rt_mem(src, dst));
4040 ins_pipe(pipe_class_dummy);
4041 %}
4042
4043 //----------Load/Store/Move Instructions---------------------------------------
4044
4045 //----------Load Instructions--------------------------------------------------
4046
4047 //------------------
4048 // MEMORY
4049 //------------------
4050
4051 // BYTE
4052 // Load Byte (8bit signed)
4053 instruct loadB(iRegI dst, memory mem) %{
4054 match(Set dst (LoadB mem));
4055 ins_cost(MEMORY_REF_COST);
4056 size(Z_DISP3_SIZE);
4057 format %{ "LB $dst, $mem\t # sign-extend byte to int" %}
4058 opcode(LB_ZOPC, LB_ZOPC);
4059 ins_encode(z_form_rt_mem_opt(dst, mem));
4060 ins_pipe(pipe_class_dummy);
4061 %}
4062
4063 // Load Byte (8bit signed)
4064 instruct loadB2L(iRegL dst, memory mem) %{
4065 match(Set dst (ConvI2L (LoadB mem)));
4066 ins_cost(MEMORY_REF_COST);
4067 size(Z_DISP3_SIZE);
4068 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %}
4069 opcode(LGB_ZOPC, LGB_ZOPC);
4070 ins_encode(z_form_rt_mem_opt(dst, mem));
4071 ins_pipe(pipe_class_dummy);
4072 %}
4073
4074 // Load Unsigned Byte (8bit UNsigned) into an int reg.
4075 instruct loadUB(iRegI dst, memory mem) %{
4076 match(Set dst (LoadUB mem));
4077 ins_cost(MEMORY_REF_COST);
4078 size(Z_DISP3_SIZE);
4079 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %}
4080 opcode(LLGC_ZOPC, LLGC_ZOPC);
4081 ins_encode(z_form_rt_mem_opt(dst, mem));
4082 ins_pipe(pipe_class_dummy);
4083 %}
4084
4085 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
4086 instruct loadUB2L(iRegL dst, memory mem) %{
4087 match(Set dst (ConvI2L (LoadUB mem)));
4088 ins_cost(MEMORY_REF_COST);
4089 size(Z_DISP3_SIZE);
4090 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %}
4091 opcode(LLGC_ZOPC, LLGC_ZOPC);
4092 ins_encode(z_form_rt_mem_opt(dst, mem));
4093 ins_pipe(pipe_class_dummy);
4094 %}
4095
4096 // CHAR/SHORT
4097
4098 // Load Short (16bit signed)
4099 instruct loadS(iRegI dst, memory mem) %{
4100 match(Set dst (LoadS mem));
4101 ins_cost(MEMORY_REF_COST);
4102 size(Z_DISP_SIZE);
4103 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %}
4104 opcode(LHY_ZOPC, LH_ZOPC);
4105 ins_encode(z_form_rt_mem_opt(dst, mem));
4106 ins_pipe(pipe_class_dummy);
4107 %}
4108
4109 // Load Short (16bit signed)
4110 instruct loadS2L(iRegL dst, memory mem) %{
4111 match(Set dst (ConvI2L (LoadS mem)));
4112 ins_cost(MEMORY_REF_COST);
4113 size(Z_DISP3_SIZE);
4114 format %{ "LGH $dst,$mem\t # sign-extend short to long" %}
4115 opcode(LGH_ZOPC, LGH_ZOPC);
4116 ins_encode(z_form_rt_mem_opt(dst, mem));
4117 ins_pipe(pipe_class_dummy);
4118 %}
4119
4120 // Load Char (16bit Unsigned)
4121 instruct loadUS(iRegI dst, memory mem) %{
4122 match(Set dst (LoadUS mem));
4123 ins_cost(MEMORY_REF_COST);
4124 size(Z_DISP3_SIZE);
4125 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %}
4126 opcode(LLGH_ZOPC, LLGH_ZOPC);
4127 ins_encode(z_form_rt_mem_opt(dst, mem));
4128 ins_pipe(pipe_class_dummy);
4129 %}
4130
4131 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
4132 instruct loadUS2L(iRegL dst, memory mem) %{
4133 match(Set dst (ConvI2L (LoadUS mem)));
4134 ins_cost(MEMORY_REF_COST);
4135 size(Z_DISP3_SIZE);
4136 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %}
4137 opcode(LLGH_ZOPC, LLGH_ZOPC);
4138 ins_encode(z_form_rt_mem_opt(dst, mem));
4139 ins_pipe(pipe_class_dummy);
4140 %}
4141
4142 // INT
4143
4144 // Load Integer
4145 instruct loadI(iRegI dst, memory mem) %{
4146 match(Set dst (LoadI mem));
4147 ins_cost(MEMORY_REF_COST);
4148 size(Z_DISP_SIZE);
4149 format %{ "L(Y) $dst,$mem\t #" %}
4150 opcode(LY_ZOPC, L_ZOPC);
4151 ins_encode(z_form_rt_mem_opt(dst, mem));
4152 ins_pipe(pipe_class_dummy);
4153 %}
4154
4155 // Load and convert to long.
4156 instruct loadI2L(iRegL dst, memory mem) %{
4157 match(Set dst (ConvI2L (LoadI mem)));
4158 ins_cost(MEMORY_REF_COST);
4159 size(Z_DISP3_SIZE);
4160 format %{ "LGF $dst,$mem\t #" %}
4161 opcode(LGF_ZOPC, LGF_ZOPC);
4162 ins_encode(z_form_rt_mem_opt(dst, mem));
4163 ins_pipe(pipe_class_dummy);
4164 %}
4165
4166 // Load Unsigned Integer into a Long Register
4167 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
4168 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4169 ins_cost(MEMORY_REF_COST);
4170 size(Z_DISP3_SIZE);
4171 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %}
4172 opcode(LLGF_ZOPC, LLGF_ZOPC);
4173 ins_encode(z_form_rt_mem_opt(dst, mem));
4174 ins_pipe(pipe_class_dummy);
4175 %}
4176
4177 // range = array length (=jint)
4178 // Load Range
4179 instruct loadRange(iRegI dst, memory mem) %{
4180 match(Set dst (LoadRange mem));
4181 ins_cost(MEMORY_REF_COST);
4182 size(Z_DISP_SIZE);
4183 format %{ "L(Y) $dst,$mem\t # range" %}
4184 opcode(LY_ZOPC, L_ZOPC);
4185 ins_encode(z_form_rt_mem_opt(dst, mem));
4186 ins_pipe(pipe_class_dummy);
4187 %}
4188
4189 // LONG
4190
4191 // Load Long - aligned
4192 instruct loadL(iRegL dst, memory mem) %{
4193 match(Set dst (LoadL mem));
4194 ins_cost(MEMORY_REF_COST);
4195 size(Z_DISP3_SIZE);
4196 format %{ "LG $dst,$mem\t # long" %}
4197 opcode(LG_ZOPC, LG_ZOPC);
4198 ins_encode(z_form_rt_mem_opt(dst, mem));
4199 ins_pipe(pipe_class_dummy);
4200 %}
4201
4202 // Load Long - UNaligned
4203 instruct loadL_unaligned(iRegL dst, memory mem) %{
4204 match(Set dst (LoadL_unaligned mem));
4205 ins_cost(MEMORY_REF_COST);
4206 size(Z_DISP3_SIZE);
4207 format %{ "LG $dst,$mem\t # unaligned long" %}
4208 opcode(LG_ZOPC, LG_ZOPC);
4209 ins_encode(z_form_rt_mem_opt(dst, mem));
4210 ins_pipe(pipe_class_dummy);
4211 %}
4212
4213
4214 // PTR
4215
4216 // Load Pointer
4217 instruct loadP(iRegP dst, memory mem) %{
4218 match(Set dst (LoadP mem));
4219 ins_cost(MEMORY_REF_COST);
4220 size(Z_DISP3_SIZE);
4221 format %{ "LG $dst,$mem\t # ptr" %}
4222 opcode(LG_ZOPC, LG_ZOPC);
4223 ins_encode(z_form_rt_mem_opt(dst, mem));
4224 ins_pipe(pipe_class_dummy);
4225 %}
4226
4227 // LoadP + CastP2L
4228 instruct castP2X_loadP(iRegL dst, memory mem) %{
4229 match(Set dst (CastP2X (LoadP mem)));
4230 ins_cost(MEMORY_REF_COST);
4231 size(Z_DISP3_SIZE);
4232 format %{ "LG $dst,$mem\t # ptr + p2x" %}
4233 opcode(LG_ZOPC, LG_ZOPC);
4234 ins_encode(z_form_rt_mem_opt(dst, mem));
4235 ins_pipe(pipe_class_dummy);
4236 %}
4237
4238 // Load Klass Pointer
4239 instruct loadKlass(iRegP dst, memory mem) %{
4240 match(Set dst (LoadKlass mem));
4241 ins_cost(MEMORY_REF_COST);
4242 size(Z_DISP3_SIZE);
4243 format %{ "LG $dst,$mem\t # klass ptr" %}
4244 opcode(LG_ZOPC, LG_ZOPC);
4245 ins_encode(z_form_rt_mem_opt(dst, mem));
4246 ins_pipe(pipe_class_dummy);
4247 %}
4248
4249 instruct loadTOC(iRegL dst) %{
4250 effect(DEF dst);
4251 ins_cost(DEFAULT_COST);
4252 // TODO: s390 port size(FIXED_SIZE);
4253 // TODO: check why this attribute causes many unnecessary rematerializations.
4254 //
4255 // The graphs I saw just had high register pressure. Further the
4256 // register TOC is loaded to is overwritten by the constant short
4257 // after. Here something as round robin register allocation might
4258 // help. But rematerializing seems not to hurt, jack even seems to
4259 // improve slightly.
4260 //
4261 // Without this flag we get spill-split recycle sanity check
4262 // failures in
4263 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
4264 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
4265 // tlsLoadP has a huge amount of outs and forces the TOC down to the
4266 // stack. Later tlsLoadP is rematerialized, leaving the register
4267 // allocator with TOC on the stack and a badly placed reload.
4268 ins_should_rematerialize(true);
4269 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %}
4270 ins_encode %{ __ load_toc($dst$$Register); %}
4271 ins_pipe(pipe_class_dummy);
4272 %}
4273
4274 // FLOAT
4275
4276 // Load Float
4277 instruct loadF(regF dst, memory mem) %{
4278 match(Set dst (LoadF mem));
4279 ins_cost(MEMORY_REF_COST);
4280 size(Z_DISP_SIZE);
4281 format %{ "LE(Y) $dst,$mem" %}
4282 opcode(LEY_ZOPC, LE_ZOPC);
4283 ins_encode(z_form_rt_mem_opt(dst, mem));
4284 ins_pipe(pipe_class_dummy);
4285 %}
4286
4287 // DOUBLE
4288
4289 // Load Double
4290 instruct loadD(regD dst, memory mem) %{
4291 match(Set dst (LoadD mem));
4292 ins_cost(MEMORY_REF_COST);
4293 size(Z_DISP_SIZE);
4294 format %{ "LD(Y) $dst,$mem" %}
4295 opcode(LDY_ZOPC, LD_ZOPC);
4296 ins_encode(z_form_rt_mem_opt(dst, mem));
4297 ins_pipe(pipe_class_dummy);
4298 %}
4299
4300 // Load Double - UNaligned
4301 instruct loadD_unaligned(regD dst, memory mem) %{
4302 match(Set dst (LoadD_unaligned mem));
4303 ins_cost(MEMORY_REF_COST);
4304 size(Z_DISP_SIZE);
4305 format %{ "LD(Y) $dst,$mem" %}
4306 opcode(LDY_ZOPC, LD_ZOPC);
4307 ins_encode(z_form_rt_mem_opt(dst, mem));
4308 ins_pipe(pipe_class_dummy);
4309 %}
4310
4311
4312 //----------------------
4313 // IMMEDIATES
4314 //----------------------
4315
4316 instruct loadConI(iRegI dst, immI src) %{
4317 match(Set dst src);
4318 ins_cost(DEFAULT_COST);
4319 size(6);
4320 format %{ "LGFI $dst,$src\t # (int)" %}
4321 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4322 ins_pipe(pipe_class_dummy);
4323 %}
4324
4325 instruct loadConI16(iRegI dst, immI16 src) %{
4326 match(Set dst src);
4327 ins_cost(DEFAULT_COST_LOW);
4328 size(4);
4329 format %{ "LGHI $dst,$src\t # (int)" %}
4330 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4331 ins_pipe(pipe_class_dummy);
4332 %}
4333
4334 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
4335 match(Set dst src);
4336 effect(KILL cr);
4337 ins_cost(DEFAULT_COST_LOW);
4338 size(4);
4339 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
4340 opcode(XGR_ZOPC);
4341 ins_encode(z_rreform(dst, dst));
4342 ins_pipe(pipe_class_dummy);
4343 %}
4344
4345 instruct loadConUI16(iRegI dst, uimmI16 src) %{
4346 match(Set dst src);
4347 // TODO: s390 port size(FIXED_SIZE);
4348 format %{ "LLILL $dst,$src" %}
4349 opcode(LLILL_ZOPC);
4350 ins_encode(z_riform_unsigned(dst, src) );
4351 ins_pipe(pipe_class_dummy);
4352 %}
4353
4354 // Load long constant from TOC with pcrelative address.
4355 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
4356 match(Set dst src);
4357 ins_cost(MEMORY_REF_COST_LO);
4358 size(6);
4359 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %}
4360 ins_encode %{
4361 address long_address = __ long_constant($src$$constant);
4362 if (long_address == NULL) {
4363 Compile::current()->env()->record_out_of_memory_failure();
4364 return;
4365 }
4366 __ load_long_pcrelative($dst$$Register, long_address);
4367 %}
4368 ins_pipe(pipe_class_dummy);
4369 %}
4370
4371 instruct loadConL32(iRegL dst, immL32 src) %{
4372 match(Set dst src);
4373 ins_cost(DEFAULT_COST);
4374 size(6);
4375 format %{ "LGFI $dst,$src\t # (long)" %}
4376 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4377 ins_pipe(pipe_class_dummy);
4378 %}
4379
4380 instruct loadConL16(iRegL dst, immL16 src) %{
4381 match(Set dst src);
4382 ins_cost(DEFAULT_COST_LOW);
4383 size(4);
4384 format %{ "LGHI $dst,$src\t # (long)" %}
4385 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4386 ins_pipe(pipe_class_dummy);
4387 %}
4388
4389 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
4390 match(Set dst src);
4391 effect(KILL cr);
4392 ins_cost(DEFAULT_COST_LOW);
4393 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %}
4394 opcode(XGR_ZOPC);
4395 ins_encode(z_rreform(dst, dst));
4396 ins_pipe(pipe_class_dummy);
4397 %}
4398
4399 // Load ptr constant from TOC with pc relative address.
4400 // Special handling for oop constants required.
4401 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
4402 match(Set dst src);
4403 ins_cost(MEMORY_REF_COST_LO);
4404 size(6);
4405 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %}
4406 ins_encode %{
4407 relocInfo::relocType constant_reloc = $src->constant_reloc();
4408 if (constant_reloc == relocInfo::oop_type) {
4409 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
4410 bool success = __ load_oop_from_toc($dst$$Register, a);
4411 if (!success) {
4412 Compile::current()->env()->record_out_of_memory_failure();
4413 return;
4414 }
4415 } else if (constant_reloc == relocInfo::metadata_type) {
4416 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
4417 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
4418 if (const_toc_addr == NULL) {
4419 Compile::current()->env()->record_out_of_memory_failure();
4420 return;
4421 }
4422 __ load_long_pcrelative($dst$$Register, const_toc_addr);
4423 } else { // Non-oop pointers, e.g. card mark base, heap top.
4424 address long_address = __ long_constant((jlong)$src$$constant);
4425 if (long_address == NULL) {
4426 Compile::current()->env()->record_out_of_memory_failure();
4427 return;
4428 }
4429 __ load_long_pcrelative($dst$$Register, long_address);
4430 }
4431 %}
4432 ins_pipe(pipe_class_dummy);
4433 %}
4434
4435 // We don't use immP16 to avoid problems with oops.
4436 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
4437 match(Set dst src);
4438 effect(KILL cr);
4439 size(4);
4440 format %{ "XGR $dst,$dst\t # NULL ptr" %}
4441 opcode(XGR_ZOPC);
4442 ins_encode(z_rreform(dst, dst));
4443 ins_pipe(pipe_class_dummy);
4444 %}
4445
4446 //----------Load Float Constant Instructions-------------------------------------------------
4447
4448 // We may not specify this instruction via an `expand' rule. If we do,
4449 // code selection will forget that this instruction needs a floating
4450 // point constant inserted into the code buffer. So `Shorten_branches'
4451 // will fail.
4452 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
4453 match(Set dst src);
4454 effect(KILL cr);
4455 ins_cost(MEMORY_REF_COST);
4456 size(6);
4457 // If this instruction rematerializes, it prolongs the live range
4458 // of the toc node, causing illegal graphs.
4459 ins_cannot_rematerialize(true);
4460 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
4461 ins_encode %{
4462 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4463 %}
4464 ins_pipe(pipe_class_dummy);
4465 %}
4466
4467 // E may not specify this instruction via an `expand' rule. If we do,
4468 // code selection will forget that this instruction needs a floating
4469 // point constant inserted into the code buffer. So `Shorten_branches'
4470 // will fail.
4471 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
4472 match(Set dst src);
4473 effect(KILL cr);
4474 ins_cost(MEMORY_REF_COST);
4475 size(6);
4476 // If this instruction rematerializes, it prolongs the live range
4477 // of the toc node, causing illegal graphs.
4478 ins_cannot_rematerialize(true);
4479 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
4480 ins_encode %{
4481 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4482 %}
4483 ins_pipe(pipe_class_dummy);
4484 %}
4485
4486 // Special case: Load Const 0.0F
4487
4488 // There's a special instr to clear a FP register.
4489 instruct loadConF0(regF dst, immFp0 src) %{
4490 match(Set dst src);
4491 ins_cost(DEFAULT_COST_LOW);
4492 size(4);
4493 format %{ "LZER $dst,$src\t # clear to zero" %}
4494 opcode(LZER_ZOPC);
4495 ins_encode(z_rreform(dst, Z_F0));
4496 ins_pipe(pipe_class_dummy);
4497 %}
4498
4499 // There's a special instr to clear a FP register.
4500 instruct loadConD0(regD dst, immDp0 src) %{
4501 match(Set dst src);
4502 ins_cost(DEFAULT_COST_LOW);
4503 size(4);
4504 format %{ "LZDR $dst,$src\t # clear to zero" %}
4505 opcode(LZDR_ZOPC);
4506 ins_encode(z_rreform(dst, Z_F0));
4507 ins_pipe(pipe_class_dummy);
4508 %}
4509
4510
4511 //----------Store Instructions-------------------------------------------------
4512
4513 // BYTE
4514
4515 // Store Byte
4516 instruct storeB(memory mem, iRegI src) %{
4517 match(Set mem (StoreB mem src));
4518 ins_cost(MEMORY_REF_COST);
4519 size(Z_DISP_SIZE);
4520 format %{ "STC(Y) $src,$mem\t # byte" %}
4521 opcode(STCY_ZOPC, STC_ZOPC);
4522 ins_encode(z_form_rt_mem_opt(src, mem));
4523 ins_pipe(pipe_class_dummy);
4524 %}
4525
4526 instruct storeCM(memory mem, immI_0 src) %{
4527 match(Set mem (StoreCM mem src));
4528 ins_cost(MEMORY_REF_COST);
4529 // TODO: s390 port size(VARIABLE_SIZE);
4530 format %{ "STC(Y) $src,$mem\t # CMS card-mark byte (must be 0!)" %}
4531 ins_encode %{
4532 guarantee($mem$$index$$Register != Z_R0, "content will not be used.");
4533 if ($mem$$index$$Register != noreg) {
4534 // Can't use clear_mem --> load const zero and store character.
4535 __ load_const_optimized(Z_R0_scratch, (long)0);
4536 if (Immediate::is_uimm12($mem$$disp)) {
4537 __ z_stc(Z_R0_scratch, $mem$$Address);
4538 } else {
4539 __ z_stcy(Z_R0_scratch, $mem$$Address);
4540 }
4541 } else {
4542 __ clear_mem(Address($mem$$Address), 1);
4543 }
4544 %}
4545 ins_pipe(pipe_class_dummy);
4546 %}
4547
4548 // CHAR/SHORT
4549
4550 // Store Char/Short
4551 instruct storeC(memory mem, iRegI src) %{
4552 match(Set mem (StoreC mem src));
4553 ins_cost(MEMORY_REF_COST);
4554 size(Z_DISP_SIZE);
4555 format %{ "STH(Y) $src,$mem\t # short" %}
4556 opcode(STHY_ZOPC, STH_ZOPC);
4557 ins_encode(z_form_rt_mem_opt(src, mem));
4558 ins_pipe(pipe_class_dummy);
4559 %}
4560
4561 // INT
4562
4563 // Store Integer
4564 instruct storeI(memory mem, iRegI src) %{
4565 match(Set mem (StoreI mem src));
4566 ins_cost(MEMORY_REF_COST);
4567 size(Z_DISP_SIZE);
4568 format %{ "ST(Y) $src,$mem\t # int" %}
4569 opcode(STY_ZOPC, ST_ZOPC);
4570 ins_encode(z_form_rt_mem_opt(src, mem));
4571 ins_pipe(pipe_class_dummy);
4572 %}
4573
4574 // LONG
4575
4576 // Store Long
4577 instruct storeL(memory mem, iRegL src) %{
4578 match(Set mem (StoreL mem src));
4579 ins_cost(MEMORY_REF_COST);
4580 size(Z_DISP3_SIZE);
4581 format %{ "STG $src,$mem\t # long" %}
4582 opcode(STG_ZOPC, STG_ZOPC);
4583 ins_encode(z_form_rt_mem_opt(src, mem));
4584 ins_pipe(pipe_class_dummy);
4585 %}
4586
4587 // PTR
4588
4589 // Store Pointer
4590 instruct storeP(memory dst, memoryRegP src) %{
4591 match(Set dst (StoreP dst src));
4592 ins_cost(MEMORY_REF_COST);
4593 size(Z_DISP3_SIZE);
4594 format %{ "STG $src,$dst\t # ptr" %}
4595 opcode(STG_ZOPC, STG_ZOPC);
4596 ins_encode(z_form_rt_mem_opt(src, dst));
4597 ins_pipe(pipe_class_dummy);
4598 %}
4599
4600 // FLOAT
4601
4602 // Store Float
4603 instruct storeF(memory mem, regF src) %{
4604 match(Set mem (StoreF mem src));
4605 ins_cost(MEMORY_REF_COST);
4606 size(Z_DISP_SIZE);
4607 format %{ "STE(Y) $src,$mem\t # float" %}
4608 opcode(STEY_ZOPC, STE_ZOPC);
4609 ins_encode(z_form_rt_mem_opt(src, mem));
4610 ins_pipe(pipe_class_dummy);
4611 %}
4612
4613 // DOUBLE
4614
4615 // Store Double
4616 instruct storeD(memory mem, regD src) %{
4617 match(Set mem (StoreD mem src));
4618 ins_cost(MEMORY_REF_COST);
4619 size(Z_DISP_SIZE);
4620 format %{ "STD(Y) $src,$mem\t # double" %}
4621 opcode(STDY_ZOPC, STD_ZOPC);
4622 ins_encode(z_form_rt_mem_opt(src, mem));
4623 ins_pipe(pipe_class_dummy);
4624 %}
4625
4626 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
4627
4628 // Should support match rule for PrefetchAllocation.
4629 // Still needed after 8068977 for PrefetchAllocate.
4630 instruct prefetchAlloc(memory mem) %{
4631 match(PrefetchAllocation mem);
4632 predicate(VM_Version::has_Prefetch());
4633 ins_cost(DEFAULT_COST);
4634 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
4635 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
4636 ins_pipe(pipe_class_dummy);
4637 %}
4638
4639 //----------Memory init instructions------------------------------------------
4640
4641 // Move Immediate to 1-byte memory.
4642 instruct memInitB(memoryRSY mem, immI8 src) %{
4643 match(Set mem (StoreB mem src));
4644 ins_cost(MEMORY_REF_COST);
4645 // TODO: s390 port size(VARIABLE_SIZE);
4646 format %{ "MVI $mem,$src\t # direct mem init 1" %}
4647 ins_encode %{
4648 if (Immediate::is_uimm12((long)$mem$$disp)) {
4649 __ z_mvi($mem$$Address, $src$$constant);
4650 } else {
4651 __ z_mviy($mem$$Address, $src$$constant);
4652 }
4653 %}
4654 ins_pipe(pipe_class_dummy);
4655 %}
4656
4657 // Move Immediate to 2-byte memory.
4658 instruct memInitC(memoryRS mem, immI16 src) %{
4659 match(Set mem (StoreC mem src));
4660 ins_cost(MEMORY_REF_COST);
4661 size(6);
4662 format %{ "MVHHI $mem,$src\t # direct mem init 2" %}
4663 opcode(MVHHI_ZOPC);
4664 ins_encode(z_silform(mem, src));
4665 ins_pipe(pipe_class_dummy);
4666 %}
4667
4668 // Move Immediate to 4-byte memory.
4669 instruct memInitI(memoryRS mem, immI16 src) %{
4670 match(Set mem (StoreI mem src));
4671 ins_cost(MEMORY_REF_COST);
4672 size(6);
4673 format %{ "MVHI $mem,$src\t # direct mem init 4" %}
4674 opcode(MVHI_ZOPC);
4675 ins_encode(z_silform(mem, src));
4676 ins_pipe(pipe_class_dummy);
4677 %}
4678
4679
4680 // Move Immediate to 8-byte memory.
4681 instruct memInitL(memoryRS mem, immL16 src) %{
4682 match(Set mem (StoreL mem src));
4683 ins_cost(MEMORY_REF_COST);
4684 size(6);
4685 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4686 opcode(MVGHI_ZOPC);
4687 ins_encode(z_silform(mem, src));
4688 ins_pipe(pipe_class_dummy);
4689 %}
4690
4691 // Move Immediate to 8-byte memory.
4692 instruct memInitP(memoryRS mem, immP16 src) %{
4693 match(Set mem (StoreP mem src));
4694 ins_cost(MEMORY_REF_COST);
4695 size(6);
4696 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4697 opcode(MVGHI_ZOPC);
4698 ins_encode(z_silform(mem, src));
4699 ins_pipe(pipe_class_dummy);
4700 %}
4701
4702
4703 //----------Instructions for compressed pointers (cOop and NKlass)-------------
4704
4705 // See cOop encoding classes for elaborate comment.
4706
4707 // Moved here because it is needed in expand rules for encode.
4708 // Long negation.
4709 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
4710 match(Set dst (SubL zero src));
4711 effect(KILL cr);
4712 size(4);
4713 format %{ "NEG $dst, $src\t # long" %}
4714 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
4715 ins_pipe(pipe_class_dummy);
4716 %}
4717
4718 // Load Compressed Pointer
4719
4720 // Load narrow oop
4721 instruct loadN(iRegN dst, memory mem) %{
4722 match(Set dst (LoadN mem));
4723 ins_cost(MEMORY_REF_COST);
4724 size(Z_DISP3_SIZE);
4725 format %{ "LoadN $dst,$mem\t # (cOop)" %}
4726 opcode(LLGF_ZOPC, LLGF_ZOPC);
4727 ins_encode(z_form_rt_mem_opt(dst, mem));
4728 ins_pipe(pipe_class_dummy);
4729 %}
4730
4731 // Load narrow Klass Pointer
4732 instruct loadNKlass(iRegN dst, memory mem) %{
4733 match(Set dst (LoadNKlass mem));
4734 ins_cost(MEMORY_REF_COST);
4735 size(Z_DISP3_SIZE);
4736 format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %}
4737 opcode(LLGF_ZOPC, LLGF_ZOPC);
4738 ins_encode(z_form_rt_mem_opt(dst, mem));
4739 ins_pipe(pipe_class_dummy);
4740 %}
4741
4742 // Load constant Compressed Pointer
4743
4744 instruct loadConN(iRegN dst, immN src) %{
4745 match(Set dst src);
4746 ins_cost(DEFAULT_COST);
4747 size(6);
4748 format %{ "loadConN $dst,$src\t # (cOop)" %}
4749 ins_encode %{
4750 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
4751 __ relocate(cOop.rspec(), 1);
4752 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
4753 %}
4754 ins_pipe(pipe_class_dummy);
4755 %}
4756
4757 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
4758 match(Set dst src);
4759 effect(KILL cr);
4760 ins_cost(DEFAULT_COST_LOW);
4761 size(4);
4762 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
4763 opcode(XGR_ZOPC);
4764 ins_encode(z_rreform(dst, dst));
4765 ins_pipe(pipe_class_dummy);
4766 %}
4767
4768 instruct loadConNKlass(iRegN dst, immNKlass src) %{
4769 match(Set dst src);
4770 ins_cost(DEFAULT_COST);
4771 size(6);
4772 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
4773 ins_encode %{
4774 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4775 __ relocate(NKlass.rspec(), 1);
4776 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
4777 %}
4778 ins_pipe(pipe_class_dummy);
4779 %}
4780
4781 // Load and Decode Compressed Pointer
4782 // optimized variants for Unscaled cOops
4783
4784 instruct decodeLoadN(iRegP dst, memory mem) %{
4785 match(Set dst (DecodeN (LoadN mem)));
4786 predicate(false && (CompressedOops::base()==NULL)&&(CompressedOops::shift()==0));
4787 ins_cost(MEMORY_REF_COST);
4788 size(Z_DISP3_SIZE);
4789 format %{ "DecodeLoadN $dst,$mem\t # (cOop Load+Decode)" %}
4790 opcode(LLGF_ZOPC, LLGF_ZOPC);
4791 ins_encode(z_form_rt_mem_opt(dst, mem));
4792 ins_pipe(pipe_class_dummy);
4793 %}
4794
4795 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
4796 match(Set dst (DecodeNKlass (LoadNKlass mem)));
4797 predicate(false && (CompressedKlassPointers::base()==NULL)&&(CompressedKlassPointers::shift()==0));
4798 ins_cost(MEMORY_REF_COST);
4799 size(Z_DISP3_SIZE);
4800 format %{ "DecodeLoadNKlass $dst,$mem\t # (load/decode NKlass)" %}
4801 opcode(LLGF_ZOPC, LLGF_ZOPC);
4802 ins_encode(z_form_rt_mem_opt(dst, mem));
4803 ins_pipe(pipe_class_dummy);
4804 %}
4805
4806 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
4807 match(Set dst (DecodeNKlass src));
4808 ins_cost(3 * DEFAULT_COST);
4809 size(12);
4810 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %}
4811 ins_encode %{
4812 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4813 __ relocate(NKlass.rspec(), 1);
4814 __ load_const($dst$$Register, (Klass*)NKlass.value());
4815 %}
4816 ins_pipe(pipe_class_dummy);
4817 %}
4818
4819 // Decode Compressed Pointer
4820
4821 // General decoder
4822 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
4823 match(Set dst (DecodeN src));
4824 effect(KILL cr);
4825 predicate(CompressedOops::base() == NULL || !ExpandLoadingBaseDecode);
4826 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4827 // TODO: s390 port size(VARIABLE_SIZE);
4828 format %{ "decodeN $dst,$src\t # (decode cOop)" %}
4829 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %}
4830 ins_pipe(pipe_class_dummy);
4831 %}
4832
4833 // General Klass decoder
4834 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
4835 match(Set dst (DecodeNKlass src));
4836 effect(KILL cr);
4837 ins_cost(3 * DEFAULT_COST);
4838 format %{ "decode_klass $dst,$src" %}
4839 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
4840 ins_pipe(pipe_class_dummy);
4841 %}
4842
4843 // General decoder
4844 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
4845 match(Set dst (DecodeN src));
4846 effect(KILL cr);
4847 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4848 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4849 (CompressedOops::base()== NULL || !ExpandLoadingBaseDecode_NN));
4850 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4851 // TODO: s390 port size(VARIABLE_SIZE);
4852 format %{ "decodeN $dst,$src\t # (decode cOop NN)" %}
4853 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
4854 ins_pipe(pipe_class_dummy);
4855 %}
4856
4857 instruct loadBase(iRegL dst, immL baseImm) %{
4858 effect(DEF dst, USE baseImm);
4859 predicate(false);
4860 format %{ "llihl $dst=$baseImm \t// load heap base" %}
4861 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
4862 ins_pipe(pipe_class_dummy);
4863 %}
4864
4865 // Decoder for heapbased mode peeling off loading the base.
4866 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4867 match(Set dst (DecodeN src base));
4868 // Note: Effect TEMP dst was used with the intention to get
4869 // different regs for dst and base, but this has caused ADLC to
4870 // generate wrong code. Oop_decoder generates additional lgr when
4871 // dst==base.
4872 effect(KILL cr);
4873 predicate(false);
4874 // TODO: s390 port size(VARIABLE_SIZE);
4875 format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
4876 ins_encode %{
4877 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
4878 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
4879 %}
4880 ins_pipe(pipe_class_dummy);
4881 %}
4882
4883 // Decoder for heapbased mode peeling off loading the base.
4884 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4885 match(Set dst (DecodeN src base));
4886 effect(KILL cr);
4887 predicate(false);
4888 // TODO: s390 port size(VARIABLE_SIZE);
4889 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
4890 ins_encode %{
4891 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
4892 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
4893 %}
4894 ins_pipe(pipe_class_dummy);
4895 %}
4896
4897 // Decoder for heapbased mode peeling off loading the base.
4898 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4899 match(Set dst (DecodeN src));
4900 predicate(CompressedOops::base() != NULL && ExpandLoadingBaseDecode);
4901 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4902 // TODO: s390 port size(VARIABLE_SIZE);
4903 expand %{
4904 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
4905 iRegL base;
4906 loadBase(base, baseImm);
4907 decodeN_base(dst, src, base, cr);
4908 %}
4909 %}
4910
4911 // Decoder for heapbased mode peeling off loading the base.
4912 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4913 match(Set dst (DecodeN src));
4914 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4915 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4916 CompressedOops::base() != NULL && ExpandLoadingBaseDecode_NN);
4917 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4918 // TODO: s390 port size(VARIABLE_SIZE);
4919 expand %{
4920 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
4921 iRegL base;
4922 loadBase(base, baseImm);
4923 decodeN_NN_base(dst, src, base, cr);
4924 %}
4925 %}
4926
4927 // Encode Compressed Pointer
4928
4929 // General encoder
4930 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
4931 match(Set dst (EncodeP src));
4932 effect(KILL cr);
4933 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
4934 (CompressedOops::base() == 0 ||
4935 CompressedOops::base_disjoint() ||
4936 !ExpandLoadingBaseEncode));
4937 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4938 // TODO: s390 port size(VARIABLE_SIZE);
4939 format %{ "encodeP $dst,$src\t # (encode cOop)" %}
4940 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
4941 ins_pipe(pipe_class_dummy);
4942 %}
4943
4944 // General class encoder
4945 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
4946 match(Set dst (EncodePKlass src));
4947 effect(KILL cr);
4948 format %{ "encode_klass $dst,$src" %}
4949 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
4950 ins_pipe(pipe_class_dummy);
4951 %}
4952
4953 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
4954 match(Set dst (EncodeP src));
4955 effect(KILL cr);
4956 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
4957 (CompressedOops::base() == 0 ||
4958 CompressedOops::base_disjoint() ||
4959 !ExpandLoadingBaseEncode_NN));
4960 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4961 // TODO: s390 port size(VARIABLE_SIZE);
4962 format %{ "encodeP $dst,$src\t # (encode cOop)" %}
4963 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
4964 ins_pipe(pipe_class_dummy);
4965 %}
4966
4967 // Encoder for heapbased mode peeling off loading the base.
4968 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
4969 match(Set dst (EncodeP src (Binary base dst)));
4970 effect(TEMP_DEF dst);
4971 predicate(false);
4972 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4973 // TODO: s390 port size(VARIABLE_SIZE);
4974 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %}
4975 ins_encode %{
4976 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
4977 (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift());
4978 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
4979 %}
4980 ins_pipe(pipe_class_dummy);
4981 %}
4982
4983 // Encoder for heapbased mode peeling off loading the base.
4984 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
4985 match(Set dst (EncodeP src base));
4986 effect(USE pow2_offset);
4987 predicate(false);
4988 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4989 // TODO: s390 port size(VARIABLE_SIZE);
4990 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %}
4991 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
4992 ins_pipe(pipe_class_dummy);
4993 %}
4994
4995 // Encoder for heapbased mode peeling off loading the base.
4996 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
4997 match(Set dst (EncodeP src));
4998 effect(KILL cr);
4999 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
5000 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode));
5001 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5002 // TODO: s390 port size(VARIABLE_SIZE);
5003 expand %{
5004 immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %}
5005 immL_0 zero %{ (0) %}
5006 flagsReg ccr;
5007 iRegL base;
5008 iRegL negBase;
5009 loadBase(base, baseImm);
5010 negL_reg_reg(negBase, zero, base, ccr);
5011 encodeP_base(dst, src, negBase);
5012 %}
5013 %}
5014
5015 // Encoder for heapbased mode peeling off loading the base.
5016 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5017 match(Set dst (EncodeP src));
5018 effect(KILL cr);
5019 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5020 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN));
5021 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5022 // TODO: s390 port size(VARIABLE_SIZE);
5023 expand %{
5024 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5025 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %}
5026 immL_0 zero %{ 0 %}
5027 flagsReg ccr;
5028 iRegL base;
5029 iRegL negBase;
5030 loadBase(base, baseImm);
5031 negL_reg_reg(negBase, zero, base, ccr);
5032 encodeP_NN_base(dst, src, negBase, pow2_offset);
5033 %}
5034 %}
5035
5036 // Store Compressed Pointer
5037
5038 // Store Compressed Pointer
5039 instruct storeN(memory mem, iRegN_P2N src) %{
5040 match(Set mem (StoreN mem src));
5041 ins_cost(MEMORY_REF_COST);
5042 size(Z_DISP_SIZE);
5043 format %{ "ST $src,$mem\t # (cOop)" %}
5044 opcode(STY_ZOPC, ST_ZOPC);
5045 ins_encode(z_form_rt_mem_opt(src, mem));
5046 ins_pipe(pipe_class_dummy);
5047 %}
5048
5049 // Store Compressed Klass pointer
5050 instruct storeNKlass(memory mem, iRegN src) %{
5051 match(Set mem (StoreNKlass mem src));
5052 ins_cost(MEMORY_REF_COST);
5053 size(Z_DISP_SIZE);
5054 format %{ "ST $src,$mem\t # (cKlass)" %}
5055 opcode(STY_ZOPC, ST_ZOPC);
5056 ins_encode(z_form_rt_mem_opt(src, mem));
5057 ins_pipe(pipe_class_dummy);
5058 %}
5059
5060 // Compare Compressed Pointers
5061
5062 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
5063 match(Set cr (CmpN src1 src2));
5064 ins_cost(DEFAULT_COST);
5065 size(2);
5066 format %{ "CLR $src1,$src2\t # (cOop)" %}
5067 opcode(CLR_ZOPC);
5068 ins_encode(z_rrform(src1, src2));
5069 ins_pipe(pipe_class_dummy);
5070 %}
5071
5072 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
5073 match(Set cr (CmpN src1 src2));
5074 ins_cost(DEFAULT_COST);
5075 size(6);
5076 format %{ "CLFI $src1,$src2\t # (cOop) compare immediate narrow" %}
5077 ins_encode %{
5078 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
5079 __ relocate(cOop.rspec(), 1);
5080 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
5081 %}
5082 ins_pipe(pipe_class_dummy);
5083 %}
5084
5085 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
5086 match(Set cr (CmpN src1 src2));
5087 ins_cost(DEFAULT_COST);
5088 size(6);
5089 format %{ "CLFI $src1,$src2\t # (NKlass) compare immediate narrow" %}
5090 ins_encode %{
5091 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
5092 __ relocate(NKlass.rspec(), 1);
5093 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
5094 %}
5095 ins_pipe(pipe_class_dummy);
5096 %}
5097
5098 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
5099 match(Set cr (CmpN src1 src2));
5100 ins_cost(DEFAULT_COST);
5101 size(2);
5102 format %{ "LTR $src1,$src2\t # (cOop) LTR because comparing against zero" %}
5103 opcode(LTR_ZOPC);
5104 ins_encode(z_rrform(src1, src1));
5105 ins_pipe(pipe_class_dummy);
5106 %}
5107
5108
5109 //----------MemBar Instructions-----------------------------------------------
5110
5111 // Memory barrier flavors
5112
5113 instruct membar_acquire() %{
5114 match(MemBarAcquire);
5115 match(LoadFence);
5116 ins_cost(4*MEMORY_REF_COST);
5117 size(0);
5118 format %{ "MEMBAR-acquire" %}
5119 ins_encode %{ __ z_acquire(); %}
5120 ins_pipe(pipe_class_dummy);
5121 %}
5122
5123 instruct membar_acquire_lock() %{
5124 match(MemBarAcquireLock);
5125 ins_cost(0);
5126 size(0);
5127 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
5128 ins_encode(/*empty*/);
5129 ins_pipe(pipe_class_dummy);
5130 %}
5131
5132 instruct membar_release() %{
5133 match(MemBarRelease);
5134 match(StoreFence);
5135 ins_cost(4 * MEMORY_REF_COST);
5136 size(0);
5137 format %{ "MEMBAR-release" %}
5138 ins_encode %{ __ z_release(); %}
5139 ins_pipe(pipe_class_dummy);
5140 %}
5141
5142 instruct membar_release_lock() %{
5143 match(MemBarReleaseLock);
5144 ins_cost(0);
5145 size(0);
5146 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
5147 ins_encode(/*empty*/);
5148 ins_pipe(pipe_class_dummy);
5149 %}
5150
5151 instruct membar_volatile() %{
5152 match(MemBarVolatile);
5153 ins_cost(4 * MEMORY_REF_COST);
5154 size(2);
5155 format %{ "MEMBAR-volatile" %}
5156 ins_encode %{ __ z_fence(); %}
5157 ins_pipe(pipe_class_dummy);
5158 %}
5159
5160 instruct unnecessary_membar_volatile() %{
5161 match(MemBarVolatile);
5162 predicate(Matcher::post_store_load_barrier(n));
5163 ins_cost(0);
5164 size(0);
5165 format %{ "# MEMBAR-volatile (empty)" %}
5166 ins_encode(/*empty*/);
5167 ins_pipe(pipe_class_dummy);
5168 %}
5169
5170 instruct membar_CPUOrder() %{
5171 match(MemBarCPUOrder);
5172 ins_cost(0);
5173 // TODO: s390 port size(FIXED_SIZE);
5174 format %{ "MEMBAR-CPUOrder (empty)" %}
5175 ins_encode(/*empty*/);
5176 ins_pipe(pipe_class_dummy);
5177 %}
5178
5179 instruct membar_storestore() %{
5180 match(MemBarStoreStore);
5181 ins_cost(0);
5182 size(0);
5183 format %{ "MEMBAR-storestore (empty)" %}
5184 ins_encode();
5185 ins_pipe(pipe_class_dummy);
5186 %}
5187
5188
5189 //----------Register Move Instructions-----------------------------------------
5190 instruct roundDouble_nop(regD dst) %{
5191 match(Set dst (RoundDouble dst));
5192 ins_cost(0);
5193 // TODO: s390 port size(FIXED_SIZE);
5194 // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
5195 ins_encode();
5196 ins_pipe(pipe_class_dummy);
5197 %}
5198
5199 instruct roundFloat_nop(regF dst) %{
5200 match(Set dst (RoundFloat dst));
5201 ins_cost(0);
5202 // TODO: s390 port size(FIXED_SIZE);
5203 // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
5204 ins_encode();
5205 ins_pipe(pipe_class_dummy);
5206 %}
5207
5208 // Cast Long to Pointer for unsafe natives.
5209 instruct castX2P(iRegP dst, iRegL src) %{
5210 match(Set dst (CastX2P src));
5211 // TODO: s390 port size(VARIABLE_SIZE);
5212 format %{ "LGR $dst,$src\t # CastX2P" %}
5213 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5214 ins_pipe(pipe_class_dummy);
5215 %}
5216
5217 // Cast Pointer to Long for unsafe natives.
5218 instruct castP2X(iRegL dst, iRegP_N2P src) %{
5219 match(Set dst (CastP2X src));
5220 // TODO: s390 port size(VARIABLE_SIZE);
5221 format %{ "LGR $dst,$src\t # CastP2X" %}
5222 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5223 ins_pipe(pipe_class_dummy);
5224 %}
5225
5226 instruct stfSSD(stackSlotD stkSlot, regD src) %{
5227 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5228 match(Set stkSlot src); // chain rule
5229 ins_cost(MEMORY_REF_COST);
5230 // TODO: s390 port size(FIXED_SIZE);
5231 format %{ " STD $src,$stkSlot\t # stk" %}
5232 opcode(STD_ZOPC);
5233 ins_encode(z_form_rt_mem(src, stkSlot));
5234 ins_pipe(pipe_class_dummy);
5235 %}
5236
5237 instruct stfSSF(stackSlotF stkSlot, regF src) %{
5238 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5239 match(Set stkSlot src); // chain rule
5240 ins_cost(MEMORY_REF_COST);
5241 // TODO: s390 port size(FIXED_SIZE);
5242 format %{ "STE $src,$stkSlot\t # stk" %}
5243 opcode(STE_ZOPC);
5244 ins_encode(z_form_rt_mem(src, stkSlot));
5245 ins_pipe(pipe_class_dummy);
5246 %}
5247
5248 //----------Conditional Move---------------------------------------------------
5249
5250 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
5251 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5252 ins_cost(DEFAULT_COST + BRANCH_COST);
5253 // TODO: s390 port size(VARIABLE_SIZE);
5254 format %{ "CMoveN,$cmp $dst,$src" %}
5255 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5256 ins_pipe(pipe_class_dummy);
5257 %}
5258
5259 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
5260 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5261 ins_cost(DEFAULT_COST + BRANCH_COST);
5262 // TODO: s390 port size(VARIABLE_SIZE);
5263 format %{ "CMoveN,$cmp $dst,$src" %}
5264 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5265 ins_pipe(pipe_class_dummy);
5266 %}
5267
5268 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
5269 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5270 ins_cost(DEFAULT_COST + BRANCH_COST);
5271 // TODO: s390 port size(VARIABLE_SIZE);
5272 format %{ "CMoveI,$cmp $dst,$src" %}
5273 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5274 ins_pipe(pipe_class_dummy);
5275 %}
5276
5277 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
5278 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5279 ins_cost(DEFAULT_COST + BRANCH_COST);
5280 // TODO: s390 port size(VARIABLE_SIZE);
5281 format %{ "CMoveI,$cmp $dst,$src" %}
5282 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5283 ins_pipe(pipe_class_dummy);
5284 %}
5285
5286 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
5287 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5288 ins_cost(DEFAULT_COST + BRANCH_COST);
5289 // TODO: s390 port size(VARIABLE_SIZE);
5290 format %{ "CMoveP,$cmp $dst,$src" %}
5291 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5292 ins_pipe(pipe_class_dummy);
5293 %}
5294
5295 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
5296 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5297 ins_cost(DEFAULT_COST + BRANCH_COST);
5298 // TODO: s390 port size(VARIABLE_SIZE);
5299 format %{ "CMoveP,$cmp $dst,$src" %}
5300 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5301 ins_pipe(pipe_class_dummy);
5302 %}
5303
5304 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
5305 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
5306 ins_cost(DEFAULT_COST + BRANCH_COST);
5307 // TODO: s390 port size(VARIABLE_SIZE);
5308 format %{ "CMoveF,$cmp $dst,$src" %}
5309 ins_encode %{
5310 // Don't emit code if operands are identical (same register).
5311 if ($dst$$FloatRegister != $src$$FloatRegister) {
5312 Label done;
5313 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5314 __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
5315 __ bind(done);
5316 }
5317 %}
5318 ins_pipe(pipe_class_dummy);
5319 %}
5320
5321 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
5322 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
5323 ins_cost(DEFAULT_COST + BRANCH_COST);
5324 // TODO: s390 port size(VARIABLE_SIZE);
5325 format %{ "CMoveD,$cmp $dst,$src" %}
5326 ins_encode %{
5327 // Don't emit code if operands are identical (same register).
5328 if ($dst$$FloatRegister != $src$$FloatRegister) {
5329 Label done;
5330 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5331 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
5332 __ bind(done);
5333 }
5334 %}
5335 ins_pipe(pipe_class_dummy);
5336 %}
5337
5338 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
5339 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5340 ins_cost(DEFAULT_COST + BRANCH_COST);
5341 // TODO: s390 port size(VARIABLE_SIZE);
5342 format %{ "CMoveL,$cmp $dst,$src" %}
5343 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5344 ins_pipe(pipe_class_dummy);
5345 %}
5346
5347 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
5348 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5349 ins_cost(DEFAULT_COST + BRANCH_COST);
5350 // TODO: s390 port size(VARIABLE_SIZE);
5351 format %{ "CMoveL,$cmp $dst,$src" %}
5352 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5353 ins_pipe(pipe_class_dummy);
5354 %}
5355
5356 //----------OS and Locking Instructions----------------------------------------
5357
5358 // This name is KNOWN by the ADLC and cannot be changed.
5359 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
5360 // for this guy.
5361 instruct tlsLoadP(threadRegP dst) %{
5362 match(Set dst (ThreadLocal));
5363 ins_cost(0);
5364 size(0);
5365 ins_should_rematerialize(true);
5366 format %{ "# $dst=ThreadLocal" %}
5367 ins_encode(/* empty */);
5368 ins_pipe(pipe_class_dummy);
5369 %}
5370
5371 instruct checkCastPP(iRegP dst) %{
5372 match(Set dst (CheckCastPP dst));
5373 size(0);
5374 format %{ "# checkcastPP of $dst" %}
5375 ins_encode(/*empty*/);
5376 ins_pipe(pipe_class_dummy);
5377 %}
5378
5379 instruct castPP(iRegP dst) %{
5380 match(Set dst (CastPP dst));
5381 size(0);
5382 format %{ "# castPP of $dst" %}
5383 ins_encode(/*empty*/);
5384 ins_pipe(pipe_class_dummy);
5385 %}
5386
5387 instruct castII(iRegI dst) %{
5388 match(Set dst (CastII dst));
5389 size(0);
5390 format %{ "# castII of $dst" %}
5391 ins_encode(/*empty*/);
5392 ins_pipe(pipe_class_dummy);
5393 %}
5394
5395
5396 //----------Conditional_store--------------------------------------------------
5397 // Conditional-store of the updated heap-top.
5398 // Used during allocation of the shared heap.
5399 // Sets flags (EQ) on success.
5400
5401 // Implement LoadPLocked. Must be ordered against changes of the memory location
5402 // by storePConditional.
5403 // Don't know whether this is ever used.
5404 instruct loadPLocked(iRegP dst, memory mem) %{
5405 match(Set dst (LoadPLocked mem));
5406 ins_cost(MEMORY_REF_COST);
5407 size(Z_DISP3_SIZE);
5408 format %{ "LG $dst,$mem\t # LoadPLocked" %}
5409 opcode(LG_ZOPC, LG_ZOPC);
5410 ins_encode(z_form_rt_mem_opt(dst, mem));
5411 ins_pipe(pipe_class_dummy);
5412 %}
5413
5414 // As compareAndSwapP, but return flag register instead of boolean value in
5415 // int register.
5416 // This instruction is matched if UseTLAB is off. Needed to pass
5417 // option tests. Mem_ptr must be a memory operand, else this node
5418 // does not get Flag_needs_anti_dependence_check set by adlc. If this
5419 // is not set this node can be rematerialized which leads to errors.
5420 instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{
5421 match(Set cr (StorePConditional mem_ptr (Binary oldval newval)));
5422 effect(KILL oldval);
5423 // TODO: s390 port size(FIXED_SIZE);
5424 format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
5425 ins_encode(z_enc_casL(oldval, newval, mem_ptr));
5426 ins_pipe(pipe_class_dummy);
5427 %}
5428
5429 // As compareAndSwapL, but return flag register instead of boolean value in
5430 // int register.
5431 // Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory
5432 // operand, else this node does not get
5433 // Flag_needs_anti_dependence_check set by adlc. If this is not set
5434 // this node can be rematerialized which leads to errors.
5435 instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{
5436 match(Set cr (StoreLConditional mem_ptr (Binary oldval newval)));
5437 effect(KILL oldval);
5438 // TODO: s390 port size(FIXED_SIZE);
5439 format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
5440 ins_encode(z_enc_casL(oldval, newval, mem_ptr));
5441 ins_pipe(pipe_class_dummy);
5442 %}
5443
5444 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
5445
5446 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
5447 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
5448 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5449 size(16);
5450 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
5451 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5452 z_enc_cctobool(res));
5453 ins_pipe(pipe_class_dummy);
5454 %}
5455
5456 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
5457 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
5458 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5459 size(18);
5460 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
5461 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5462 z_enc_cctobool(res));
5463 ins_pipe(pipe_class_dummy);
5464 %}
5465
5466 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
5467 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
5468 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5469 size(18);
5470 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
5471 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5472 z_enc_cctobool(res));
5473 ins_pipe(pipe_class_dummy);
5474 %}
5475
5476 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
5477 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
5478 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5479 size(16);
5480 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
5481 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5482 z_enc_cctobool(res));
5483 ins_pipe(pipe_class_dummy);
5484 %}
5485
5486 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
5487
5488 // Exploit: direct memory arithmetic
5489 // Prereqs: - instructions available
5490 // - instructions guarantee atomicity
5491 // - immediate operand to be added
5492 // - immediate operand is small enough (8-bit signed).
5493 // - result of instruction is not used
5494 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
5495 match(Set dummy (GetAndAddI mem src));
5496 effect(KILL cr);
5497 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5498 ins_cost(MEMORY_REF_COST);
5499 size(6);
5500 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %}
5501 opcode(ASI_ZOPC);
5502 ins_encode(z_siyform(mem, src));
5503 ins_pipe(pipe_class_dummy);
5504 %}
5505
5506 // Fallback: direct memory arithmetic not available
5507 // Disadvantages: - CS-Loop required, very expensive.
5508 // - more code generated (26 to xx bytes vs. 6 bytes)
5509 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
5510 match(Set dst (GetAndAddI mem src));
5511 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5512 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5513 format %{ "BEGIN ATOMIC {\n\t"
5514 " LGF $dst,[$mem]\n\t"
5515 " AHIK $tmp,$dst,$src\n\t"
5516 " CSY $dst,$tmp,$mem\n\t"
5517 " retry if failed\n\t"
5518 "} END ATOMIC"
5519 %}
5520 ins_encode %{
5521 Register Rdst = $dst$$Register;
5522 Register Rtmp = $tmp$$Register;
5523 int Isrc = $src$$constant;
5524 Label retry;
5525
5526 // Iterate until update with incremented value succeeds.
5527 __ z_lgf(Rdst, $mem$$Address); // current contents
5528 __ bind(retry);
5529 // Calculate incremented value.
5530 if (VM_Version::has_DistinctOpnds()) {
5531 __ z_ahik(Rtmp, Rdst, Isrc);
5532 } else {
5533 __ z_lr(Rtmp, Rdst);
5534 __ z_ahi(Rtmp, Isrc);
5535 }
5536 // Swap into memory location.
5537 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5538 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5539 %}
5540 ins_pipe(pipe_class_dummy);
5541 %}
5542
5543 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
5544 match(Set dst (GetAndAddI mem src));
5545 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5546 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
5547 format %{ "BEGIN ATOMIC {\n\t"
5548 " LGF $dst,[$mem]\n\t"
5549 " LGR $tmp,$dst\n\t"
5550 " AFI $tmp,$src\n\t"
5551 " CSY $dst,$tmp,$mem\n\t"
5552 " retry if failed\n\t"
5553 "} END ATOMIC"
5554 %}
5555 ins_encode %{
5556 Register Rdst = $dst$$Register;
5557 Register Rtmp = $tmp$$Register;
5558 int Isrc = $src$$constant;
5559 Label retry;
5560
5561 // Iterate until update with incremented value succeeds.
5562 __ z_lgf(Rdst, $mem$$Address); // current contents
5563 __ bind(retry);
5564 // Calculate incremented value.
5565 __ z_lr(Rtmp, Rdst);
5566 __ z_afi(Rtmp, Isrc);
5567 // Swap into memory location.
5568 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5569 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5570 %}
5571 ins_pipe(pipe_class_dummy);
5572 %}
5573
5574 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
5575 match(Set dst (GetAndAddI mem src));
5576 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5577 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5578 format %{ "BEGIN ATOMIC {\n\t"
5579 " LGF $dst,[$mem]\n\t"
5580 " ARK $tmp,$dst,$src\n\t"
5581 " CSY $dst,$tmp,$mem\n\t"
5582 " retry if failed\n\t"
5583 "} END ATOMIC"
5584 %}
5585 ins_encode %{
5586 Register Rsrc = $src$$Register;
5587 Register Rdst = $dst$$Register;
5588 Register Rtmp = $tmp$$Register;
5589 Label retry;
5590
5591 // Iterate until update with incremented value succeeds.
5592 __ z_lgf(Rdst, $mem$$Address); // current contents
5593 __ bind(retry);
5594 // Calculate incremented value.
5595 if (VM_Version::has_DistinctOpnds()) {
5596 __ z_ark(Rtmp, Rdst, Rsrc);
5597 } else {
5598 __ z_lr(Rtmp, Rdst);
5599 __ z_ar(Rtmp, Rsrc);
5600 }
5601 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5602 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5603 %}
5604 ins_pipe(pipe_class_dummy);
5605 %}
5606
5607
5608 // Exploit: direct memory arithmetic
5609 // Prereqs: - instructions available
5610 // - instructions guarantee atomicity
5611 // - immediate operand to be added
5612 // - immediate operand is small enough (8-bit signed).
5613 // - result of instruction is not used
5614 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
5615 match(Set dummy (GetAndAddL mem src));
5616 effect(KILL cr);
5617 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5618 ins_cost(MEMORY_REF_COST);
5619 size(6);
5620 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %}
5621 opcode(AGSI_ZOPC);
5622 ins_encode(z_siyform(mem, src));
5623 ins_pipe(pipe_class_dummy);
5624 %}
5625
5626 // Fallback: direct memory arithmetic not available
5627 // Disadvantages: - CS-Loop required, very expensive.
5628 // - more code generated (26 to xx bytes vs. 6 bytes)
5629 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
5630 match(Set dst (GetAndAddL mem src));
5631 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5632 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5633 format %{ "BEGIN ATOMIC {\n\t"
5634 " LG $dst,[$mem]\n\t"
5635 " AGHIK $tmp,$dst,$src\n\t"
5636 " CSG $dst,$tmp,$mem\n\t"
5637 " retry if failed\n\t"
5638 "} END ATOMIC"
5639 %}
5640 ins_encode %{
5641 Register Rdst = $dst$$Register;
5642 Register Rtmp = $tmp$$Register;
5643 int Isrc = $src$$constant;
5644 Label retry;
5645
5646 // Iterate until update with incremented value succeeds.
5647 __ z_lg(Rdst, $mem$$Address); // current contents
5648 __ bind(retry);
5649 // Calculate incremented value.
5650 if (VM_Version::has_DistinctOpnds()) {
5651 __ z_aghik(Rtmp, Rdst, Isrc);
5652 } else {
5653 __ z_lgr(Rtmp, Rdst);
5654 __ z_aghi(Rtmp, Isrc);
5655 }
5656 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5657 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5658 %}
5659 ins_pipe(pipe_class_dummy);
5660 %}
5661
5662 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
5663 match(Set dst (GetAndAddL mem src));
5664 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5665 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5666 format %{ "BEGIN ATOMIC {\n\t"
5667 " LG $dst,[$mem]\n\t"
5668 " LGR $tmp,$dst\n\t"
5669 " AGFI $tmp,$src\n\t"
5670 " CSG $dst,$tmp,$mem\n\t"
5671 " retry if failed\n\t"
5672 "} END ATOMIC"
5673 %}
5674 ins_encode %{
5675 Register Rdst = $dst$$Register;
5676 Register Rtmp = $tmp$$Register;
5677 int Isrc = $src$$constant;
5678 Label retry;
5679
5680 // Iterate until update with incremented value succeeds.
5681 __ z_lg(Rdst, $mem$$Address); // current contents
5682 __ bind(retry);
5683 // Calculate incremented value.
5684 __ z_lgr(Rtmp, Rdst);
5685 __ z_agfi(Rtmp, Isrc);
5686 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5687 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5688 %}
5689 ins_pipe(pipe_class_dummy);
5690 %}
5691
5692 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
5693 match(Set dst (GetAndAddL mem src));
5694 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5695 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5696 format %{ "BEGIN ATOMIC {\n\t"
5697 " LG $dst,[$mem]\n\t"
5698 " AGRK $tmp,$dst,$src\n\t"
5699 " CSG $dst,$tmp,$mem\n\t"
5700 " retry if failed\n\t"
5701 "} END ATOMIC"
5702 %}
5703 ins_encode %{
5704 Register Rsrc = $src$$Register;
5705 Register Rdst = $dst$$Register;
5706 Register Rtmp = $tmp$$Register;
5707 Label retry;
5708
5709 // Iterate until update with incremented value succeeds.
5710 __ z_lg(Rdst, $mem$$Address); // current contents
5711 __ bind(retry);
5712 // Calculate incremented value.
5713 if (VM_Version::has_DistinctOpnds()) {
5714 __ z_agrk(Rtmp, Rdst, Rsrc);
5715 } else {
5716 __ z_lgr(Rtmp, Rdst);
5717 __ z_agr(Rtmp, Rsrc);
5718 }
5719 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5720 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5721 %}
5722 ins_pipe(pipe_class_dummy);
5723 %}
5724
5725 // Increment value in memory, save old value in dst.
5726 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
5727 match(Set dst (GetAndAddI mem src));
5728 predicate(VM_Version::has_LoadAndALUAtomicV1());
5729 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5730 size(6);
5731 format %{ "LAA $dst,$src,[$mem]" %}
5732 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
5733 ins_pipe(pipe_class_dummy);
5734 %}
5735
5736 // Increment value in memory, save old value in dst.
5737 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
5738 match(Set dst (GetAndAddL mem src));
5739 predicate(VM_Version::has_LoadAndALUAtomicV1());
5740 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5741 size(6);
5742 format %{ "LAAG $dst,$src,[$mem]" %}
5743 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
5744 ins_pipe(pipe_class_dummy);
5745 %}
5746
5747
5748 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
5749 match(Set dst (GetAndSetI mem dst));
5750 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5751 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
5752 ins_encode(z_enc_SwapI(mem, dst, tmp));
5753 ins_pipe(pipe_class_dummy);
5754 %}
5755
5756 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
5757 match(Set dst (GetAndSetL mem dst));
5758 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5759 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
5760 ins_encode(z_enc_SwapL(mem, dst, tmp));
5761 ins_pipe(pipe_class_dummy);
5762 %}
5763
5764 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
5765 match(Set dst (GetAndSetN mem dst));
5766 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5767 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
5768 ins_encode(z_enc_SwapI(mem, dst, tmp));
5769 ins_pipe(pipe_class_dummy);
5770 %}
5771
5772 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
5773 match(Set dst (GetAndSetP mem dst));
5774 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5775 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
5776 ins_encode(z_enc_SwapL(mem, dst, tmp));
5777 ins_pipe(pipe_class_dummy);
5778 %}
5779
5780
5781 //----------Arithmetic Instructions--------------------------------------------
5782
5783 // The rules are sorted by right operand type and operand length. Please keep
5784 // it that way.
5785 // Left operand type is always reg. Left operand len is I, L, P
5786 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
5787 // Special instruction formats, e.g. multi-operand, are inserted at the end.
5788
5789 // ADD
5790
5791 // REG = REG + REG
5792
5793 // Register Addition
5794 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
5795 match(Set dst (AddI dst src));
5796 effect(KILL cr);
5797 // TODO: s390 port size(FIXED_SIZE);
5798 format %{ "AR $dst,$src\t # int CISC ALU" %}
5799 opcode(AR_ZOPC);
5800 ins_encode(z_rrform(dst, src));
5801 ins_pipe(pipe_class_dummy);
5802 %}
5803
5804 // Avoid use of LA(Y) for general ALU operation.
5805 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
5806 match(Set dst (AddI src1 src2));
5807 effect(KILL cr);
5808 predicate(VM_Version::has_DistinctOpnds());
5809 ins_cost(DEFAULT_COST);
5810 size(4);
5811 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %}
5812 opcode(ARK_ZOPC);
5813 ins_encode(z_rrfform(dst, src1, src2));
5814 ins_pipe(pipe_class_dummy);
5815 %}
5816
5817 // REG = REG + IMM
5818
5819 // Avoid use of LA(Y) for general ALU operation.
5820 // Immediate Addition
5821 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
5822 match(Set dst (AddI dst con));
5823 effect(KILL cr);
5824 ins_cost(DEFAULT_COST);
5825 // TODO: s390 port size(FIXED_SIZE);
5826 format %{ "AHI $dst,$con\t # int CISC ALU" %}
5827 opcode(AHI_ZOPC);
5828 ins_encode(z_riform_signed(dst, con));
5829 ins_pipe(pipe_class_dummy);
5830 %}
5831
5832 // Avoid use of LA(Y) for general ALU operation.
5833 // Immediate Addition
5834 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
5835 match(Set dst (AddI src con));
5836 effect(KILL cr);
5837 predicate( VM_Version::has_DistinctOpnds());
5838 ins_cost(DEFAULT_COST);
5839 // TODO: s390 port size(FIXED_SIZE);
5840 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %}
5841 opcode(AHIK_ZOPC);
5842 ins_encode(z_rieform_d(dst, src, con));
5843 ins_pipe(pipe_class_dummy);
5844 %}
5845
5846 // Immediate Addition
5847 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
5848 match(Set dst (AddI dst src));
5849 effect(KILL cr);
5850 ins_cost(DEFAULT_COST_HIGH);
5851 size(6);
5852 format %{ "AFI $dst,$src" %}
5853 opcode(AFI_ZOPC);
5854 ins_encode(z_rilform_signed(dst, src));
5855 ins_pipe(pipe_class_dummy);
5856 %}
5857
5858 // Immediate Addition
5859 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
5860 match(Set dst (AddI src con));
5861 predicate(PreferLAoverADD);
5862 ins_cost(DEFAULT_COST_LOW);
5863 size(4);
5864 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %}
5865 opcode(LA_ZOPC);
5866 ins_encode(z_rxform_imm_reg(dst, con, src));
5867 ins_pipe(pipe_class_dummy);
5868 %}
5869
5870 // Immediate Addition
5871 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
5872 match(Set dst (AddI src con));
5873 predicate(PreferLAoverADD);
5874 ins_cost(DEFAULT_COST);
5875 size(6);
5876 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %}
5877 opcode(LAY_ZOPC);
5878 ins_encode(z_rxyform_imm_reg(dst, con, src));
5879 ins_pipe(pipe_class_dummy);
5880 %}
5881
5882 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
5883 match(Set dst (AddI (AddI src1 src2) con));
5884 predicate( PreferLAoverADD);
5885 ins_cost(DEFAULT_COST_LOW);
5886 size(4);
5887 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %}
5888 opcode(LA_ZOPC);
5889 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
5890 ins_pipe(pipe_class_dummy);
5891 %}
5892
5893 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
5894 match(Set dst (AddI (AddI src1 src2) con));
5895 predicate(PreferLAoverADD);
5896 ins_cost(DEFAULT_COST);
5897 size(6);
5898 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %}
5899 opcode(LAY_ZOPC);
5900 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
5901 ins_pipe(pipe_class_dummy);
5902 %}
5903
5904 // REG = REG + MEM
5905
5906 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
5907 match(Set dst (AddI dst (LoadI src)));
5908 effect(KILL cr);
5909 ins_cost(MEMORY_REF_COST);
5910 // TODO: s390 port size(VARIABLE_SIZE);
5911 format %{ "A(Y) $dst, $src\t # int" %}
5912 opcode(AY_ZOPC, A_ZOPC);
5913 ins_encode(z_form_rt_mem_opt(dst, src));
5914 ins_pipe(pipe_class_dummy);
5915 %}
5916
5917 // MEM = MEM + IMM
5918
5919 // Add Immediate to 4-byte memory operand and result
5920 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
5921 match(Set mem (StoreI mem (AddI (LoadI mem) src)));
5922 effect(KILL cr);
5923 predicate(VM_Version::has_MemWithImmALUOps());
5924 ins_cost(MEMORY_REF_COST);
5925 size(6);
5926 format %{ "ASI $mem,$src\t # direct mem add 4" %}
5927 opcode(ASI_ZOPC);
5928 ins_encode(z_siyform(mem, src));
5929 ins_pipe(pipe_class_dummy);
5930 %}
5931
5932
5933 //
5934
5935 // REG = REG + REG
5936
5937 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
5938 match(Set dst (AddL dst (ConvI2L src)));
5939 effect(KILL cr);
5940 size(4);
5941 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %}
5942 opcode(AGFR_ZOPC);
5943 ins_encode(z_rreform(dst, src));
5944 ins_pipe(pipe_class_dummy);
5945 %}
5946
5947 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
5948 match(Set dst (AddL dst src));
5949 effect(KILL cr);
5950 // TODO: s390 port size(FIXED_SIZE);
5951 format %{ "AGR $dst, $src\t # long CISC ALU" %}
5952 opcode(AGR_ZOPC);
5953 ins_encode(z_rreform(dst, src));
5954 ins_pipe(pipe_class_dummy);
5955 %}
5956
5957 // Avoid use of LA(Y) for general ALU operation.
5958 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
5959 match(Set dst (AddL src1 src2));
5960 effect(KILL cr);
5961 predicate(VM_Version::has_DistinctOpnds());
5962 ins_cost(DEFAULT_COST);
5963 size(4);
5964 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %}
5965 opcode(AGRK_ZOPC);
5966 ins_encode(z_rrfform(dst, src1, src2));
5967 ins_pipe(pipe_class_dummy);
5968 %}
5969
5970 // REG = REG + IMM
5971
5972 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
5973 match(Set dst (AddL src con));
5974 predicate( PreferLAoverADD);
5975 ins_cost(DEFAULT_COST_LOW);
5976 size(4);
5977 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %}
5978 opcode(LA_ZOPC);
5979 ins_encode(z_rxform_imm_reg(dst, con, src));
5980 ins_pipe(pipe_class_dummy);
5981 %}
5982
5983 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
5984 match(Set dst (AddL src con));
5985 predicate(PreferLAoverADD);
5986 ins_cost(DEFAULT_COST);
5987 size(6);
5988 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %}
5989 opcode(LAY_ZOPC);
5990 ins_encode(z_rxyform_imm_reg(dst, con, src));
5991 ins_pipe(pipe_class_dummy);
5992 %}
5993
5994 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
5995 match(Set dst (AddL dst con));
5996 effect(KILL cr);
5997 ins_cost(DEFAULT_COST_HIGH);
5998 size(6);
5999 format %{ "AGFI $dst,$con\t # long CISC ALU" %}
6000 opcode(AGFI_ZOPC);
6001 ins_encode(z_rilform_signed(dst, con));
6002 ins_pipe(pipe_class_dummy);
6003 %}
6004
6005 // Avoid use of LA(Y) for general ALU operation.
6006 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
6007 match(Set dst (AddL dst con));
6008 effect(KILL cr);
6009 ins_cost(DEFAULT_COST);
6010 // TODO: s390 port size(FIXED_SIZE);
6011 format %{ "AGHI $dst,$con\t # long CISC ALU" %}
6012 opcode(AGHI_ZOPC);
6013 ins_encode(z_riform_signed(dst, con));
6014 ins_pipe(pipe_class_dummy);
6015 %}
6016
6017 // Avoid use of LA(Y) for general ALU operation.
6018 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
6019 match(Set dst (AddL src con));
6020 effect(KILL cr);
6021 predicate( VM_Version::has_DistinctOpnds());
6022 ins_cost(DEFAULT_COST);
6023 size(6);
6024 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %}
6025 opcode(AGHIK_ZOPC);
6026 ins_encode(z_rieform_d(dst, src, con));
6027 ins_pipe(pipe_class_dummy);
6028 %}
6029
6030 // REG = REG + MEM
6031
6032 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6033 match(Set dst (AddL dst (ConvI2L (LoadI src))));
6034 effect(KILL cr);
6035 ins_cost(MEMORY_REF_COST);
6036 size(Z_DISP3_SIZE);
6037 format %{ "AGF $dst, $src\t # long/int" %}
6038 opcode(AGF_ZOPC, AGF_ZOPC);
6039 ins_encode(z_form_rt_mem_opt(dst, src));
6040 ins_pipe(pipe_class_dummy);
6041 %}
6042
6043 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6044 match(Set dst (AddL dst (LoadL src)));
6045 effect(KILL cr);
6046 ins_cost(MEMORY_REF_COST);
6047 size(Z_DISP3_SIZE);
6048 format %{ "AG $dst, $src\t # long" %}
6049 opcode(AG_ZOPC, AG_ZOPC);
6050 ins_encode(z_form_rt_mem_opt(dst, src));
6051 ins_pipe(pipe_class_dummy);
6052 %}
6053
6054 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
6055 match(Set dst (AddL (AddL src1 src2) con));
6056 predicate( PreferLAoverADD);
6057 ins_cost(DEFAULT_COST_LOW);
6058 size(4);
6059 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %}
6060 opcode(LA_ZOPC);
6061 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6062 ins_pipe(pipe_class_dummy);
6063 %}
6064
6065 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
6066 match(Set dst (AddL (AddL src1 src2) con));
6067 predicate(PreferLAoverADD);
6068 ins_cost(DEFAULT_COST);
6069 size(6);
6070 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %}
6071 opcode(LAY_ZOPC);
6072 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6073 ins_pipe(pipe_class_dummy);
6074 %}
6075
6076 // MEM = MEM + IMM
6077
6078 // Add Immediate to 8-byte memory operand and result.
6079 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6080 match(Set mem (StoreL mem (AddL (LoadL mem) src)));
6081 effect(KILL cr);
6082 predicate(VM_Version::has_MemWithImmALUOps());
6083 ins_cost(MEMORY_REF_COST);
6084 size(6);
6085 format %{ "AGSI $mem,$src\t # direct mem add 8" %}
6086 opcode(AGSI_ZOPC);
6087 ins_encode(z_siyform(mem, src));
6088 ins_pipe(pipe_class_dummy);
6089 %}
6090
6091
6092 // REG = REG + REG
6093
6094 // Ptr Addition
6095 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
6096 match(Set dst (AddP src1 src2));
6097 predicate( PreferLAoverADD);
6098 ins_cost(DEFAULT_COST);
6099 size(4);
6100 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
6101 opcode(LA_ZOPC);
6102 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
6103 ins_pipe(pipe_class_dummy);
6104 %}
6105
6106 // Ptr Addition
6107 // Avoid use of LA(Y) for general ALU operation.
6108 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
6109 match(Set dst (AddP dst src));
6110 effect(KILL cr);
6111 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6112 ins_cost(DEFAULT_COST);
6113 // TODO: s390 port size(FIXED_SIZE);
6114 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %}
6115 opcode(ALGR_ZOPC);
6116 ins_encode(z_rreform(dst, src));
6117 ins_pipe(pipe_class_dummy);
6118 %}
6119
6120 // Ptr Addition
6121 // Avoid use of LA(Y) for general ALU operation.
6122 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
6123 match(Set dst (AddP src1 src2));
6124 effect(KILL cr);
6125 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6126 ins_cost(DEFAULT_COST);
6127 // TODO: s390 port size(FIXED_SIZE);
6128 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %}
6129 opcode(ALGRK_ZOPC);
6130 ins_encode(z_rrfform(dst, src1, src2));
6131 ins_pipe(pipe_class_dummy);
6132 %}
6133
6134 // REG = REG + IMM
6135
6136 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
6137 match(Set dst (AddP src con));
6138 predicate( PreferLAoverADD);
6139 ins_cost(DEFAULT_COST_LOW);
6140 size(4);
6141 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %}
6142 opcode(LA_ZOPC);
6143 ins_encode(z_rxform_imm_reg(dst, con, src));
6144 ins_pipe(pipe_class_dummy);
6145 %}
6146
6147 // Avoid use of LA(Y) for general ALU operation.
6148 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
6149 match(Set dst (AddP dst src));
6150 effect(KILL cr);
6151 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6152 ins_cost(DEFAULT_COST);
6153 // TODO: s390 port size(FIXED_SIZE);
6154 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %}
6155 opcode(AGHI_ZOPC);
6156 ins_encode(z_riform_signed(dst, src));
6157 ins_pipe(pipe_class_dummy);
6158 %}
6159
6160 // Avoid use of LA(Y) for general ALU operation.
6161 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
6162 match(Set dst (AddP src con));
6163 effect(KILL cr);
6164 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6165 ins_cost(DEFAULT_COST);
6166 // TODO: s390 port size(FIXED_SIZE);
6167 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
6168 opcode(ALGHSIK_ZOPC);
6169 ins_encode(z_rieform_d(dst, src, con));
6170 ins_pipe(pipe_class_dummy);
6171 %}
6172
6173 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
6174 match(Set dst (AddP src con));
6175 predicate(PreferLAoverADD);
6176 ins_cost(DEFAULT_COST);
6177 size(6);
6178 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %}
6179 opcode(LAY_ZOPC);
6180 ins_encode(z_rxyform_imm_reg(dst, con, src));
6181 ins_pipe(pipe_class_dummy);
6182 %}
6183
6184 // Pointer Immediate Addition
6185 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
6186 match(Set dst (AddP dst src));
6187 effect(KILL cr);
6188 ins_cost(DEFAULT_COST_HIGH);
6189 // TODO: s390 port size(FIXED_SIZE);
6190 format %{ "AGFI $dst,$src\t # ptr" %}
6191 opcode(AGFI_ZOPC);
6192 ins_encode(z_rilform_signed(dst, src));
6193 ins_pipe(pipe_class_dummy);
6194 %}
6195
6196 // REG = REG1 + REG2 + IMM
6197
6198 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
6199 match(Set dst (AddP (AddP src1 src2) con));
6200 predicate( PreferLAoverADD);
6201 ins_cost(DEFAULT_COST_LOW);
6202 size(4);
6203 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6204 opcode(LA_ZOPC);
6205 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6206 ins_pipe(pipe_class_dummy);
6207 %}
6208
6209 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
6210 match(Set dst (AddP (AddP src1 src2) con));
6211 predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0);
6212 ins_cost(DEFAULT_COST_LOW);
6213 size(4);
6214 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6215 opcode(LA_ZOPC);
6216 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6217 ins_pipe(pipe_class_dummy);
6218 %}
6219
6220 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
6221 match(Set dst (AddP (AddP src1 src2) con));
6222 predicate(PreferLAoverADD);
6223 ins_cost(DEFAULT_COST);
6224 // TODO: s390 port size(FIXED_SIZE);
6225 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6226 opcode(LAY_ZOPC);
6227 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6228 ins_pipe(pipe_class_dummy);
6229 %}
6230
6231 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
6232 match(Set dst (AddP (AddP src1 src2) con));
6233 predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0);
6234 ins_cost(DEFAULT_COST);
6235 // TODO: s390 port size(FIXED_SIZE);
6236 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6237 opcode(LAY_ZOPC);
6238 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6239 ins_pipe(pipe_class_dummy);
6240 %}
6241
6242 // MEM = MEM + IMM
6243
6244 // Add Immediate to 8-byte memory operand and result
6245 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6246 match(Set mem (StoreP mem (AddP (LoadP mem) src)));
6247 effect(KILL cr);
6248 predicate(VM_Version::has_MemWithImmALUOps());
6249 ins_cost(MEMORY_REF_COST);
6250 size(6);
6251 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %}
6252 opcode(AGSI_ZOPC);
6253 ins_encode(z_siyform(mem, src));
6254 ins_pipe(pipe_class_dummy);
6255 %}
6256
6257 // SUB
6258
6259 // Register Subtraction
6260 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
6261 match(Set dst (SubI dst src));
6262 effect(KILL cr);
6263 // TODO: s390 port size(FIXED_SIZE);
6264 format %{ "SR $dst,$src\t # int CISC ALU" %}
6265 opcode(SR_ZOPC);
6266 ins_encode(z_rrform(dst, src));
6267 ins_pipe(pipe_class_dummy);
6268 %}
6269
6270 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
6271 match(Set dst (SubI src1 src2));
6272 effect(KILL cr);
6273 predicate(VM_Version::has_DistinctOpnds());
6274 ins_cost(DEFAULT_COST);
6275 size(4);
6276 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %}
6277 opcode(SRK_ZOPC);
6278 ins_encode(z_rrfform(dst, src1, src2));
6279 ins_pipe(pipe_class_dummy);
6280 %}
6281
6282 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6283 match(Set dst (SubI dst (LoadI src)));
6284 effect(KILL cr);
6285 ins_cost(MEMORY_REF_COST);
6286 // TODO: s390 port size(VARIABLE_SIZE);
6287 format %{ "S(Y) $dst, $src\t # int" %}
6288 opcode(SY_ZOPC, S_ZOPC);
6289 ins_encode(z_form_rt_mem_opt(dst, src));
6290 ins_pipe(pipe_class_dummy);
6291 %}
6292
6293 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
6294 match(Set dst (SubI zero src));
6295 effect(KILL cr);
6296 size(2);
6297 format %{ "NEG $dst, $src" %}
6298 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
6299 ins_pipe(pipe_class_dummy);
6300 %}
6301
6302 //
6303
6304 // Long subtraction
6305 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6306 match(Set dst (SubL dst src));
6307 effect(KILL cr);
6308 // TODO: s390 port size(FIXED_SIZE);
6309 format %{ "SGR $dst,$src\t # int CISC ALU" %}
6310 opcode(SGR_ZOPC);
6311 ins_encode(z_rreform(dst, src));
6312 ins_pipe(pipe_class_dummy);
6313 %}
6314
6315 // Avoid use of LA(Y) for general ALU operation.
6316 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6317 match(Set dst (SubL src1 src2));
6318 effect(KILL cr);
6319 predicate(VM_Version::has_DistinctOpnds());
6320 ins_cost(DEFAULT_COST);
6321 size(4);
6322 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %}
6323 opcode(SGRK_ZOPC);
6324 ins_encode(z_rrfform(dst, src1, src2));
6325 ins_pipe(pipe_class_dummy);
6326 %}
6327
6328 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
6329 match(Set dst (SubL dst (ConvI2L src)));
6330 effect(KILL cr);
6331 size(4);
6332 format %{ "SGFR $dst, $src\t # int CISC ALU" %}
6333 opcode(SGFR_ZOPC);
6334 ins_encode(z_rreform(dst, src));
6335 ins_pipe(pipe_class_dummy);
6336 %}
6337
6338 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6339 match(Set dst (SubL dst (ConvI2L (LoadI src))));
6340 effect(KILL cr);
6341 ins_cost(MEMORY_REF_COST);
6342 size(Z_DISP3_SIZE);
6343 format %{ "SGF $dst, $src\t # long/int" %}
6344 opcode(SGF_ZOPC, SGF_ZOPC);
6345 ins_encode(z_form_rt_mem_opt(dst, src));
6346 ins_pipe(pipe_class_dummy);
6347 %}
6348
6349 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6350 match(Set dst (SubL dst (LoadL src)));
6351 effect(KILL cr);
6352 ins_cost(MEMORY_REF_COST);
6353 size(Z_DISP3_SIZE);
6354 format %{ "SG $dst, $src\t # long" %}
6355 opcode(SG_ZOPC, SG_ZOPC);
6356 ins_encode(z_form_rt_mem_opt(dst, src));
6357 ins_pipe(pipe_class_dummy);
6358 %}
6359
6360 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
6361
6362 // MUL
6363
6364 // Register Multiplication
6365 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
6366 match(Set dst (MulI dst src));
6367 ins_cost(DEFAULT_COST);
6368 size(4);
6369 format %{ "MSR $dst, $src" %}
6370 opcode(MSR_ZOPC);
6371 ins_encode(z_rreform(dst, src));
6372 ins_pipe(pipe_class_dummy);
6373 %}
6374
6375 // Immediate Multiplication
6376 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
6377 match(Set dst (MulI dst con));
6378 ins_cost(DEFAULT_COST);
6379 // TODO: s390 port size(FIXED_SIZE);
6380 format %{ "MHI $dst,$con" %}
6381 opcode(MHI_ZOPC);
6382 ins_encode(z_riform_signed(dst,con));
6383 ins_pipe(pipe_class_dummy);
6384 %}
6385
6386 // Immediate (32bit) Multiplication
6387 instruct mulI_reg_imm32(iRegI dst, immI con) %{
6388 match(Set dst (MulI dst con));
6389 ins_cost(DEFAULT_COST);
6390 size(6);
6391 format %{ "MSFI $dst,$con" %}
6392 opcode(MSFI_ZOPC);
6393 ins_encode(z_rilform_signed(dst,con));
6394 ins_pipe(pipe_class_dummy);
6395 %}
6396
6397 instruct mulI_Reg_mem(iRegI dst, memory src)%{
6398 match(Set dst (MulI dst (LoadI src)));
6399 ins_cost(MEMORY_REF_COST);
6400 // TODO: s390 port size(VARIABLE_SIZE);
6401 format %{ "MS(Y) $dst, $src\t # int" %}
6402 opcode(MSY_ZOPC, MS_ZOPC);
6403 ins_encode(z_form_rt_mem_opt(dst, src));
6404 ins_pipe(pipe_class_dummy);
6405 %}
6406
6407 //
6408
6409 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
6410 match(Set dst (MulL dst (ConvI2L src)));
6411 ins_cost(DEFAULT_COST);
6412 // TODO: s390 port size(FIXED_SIZE);
6413 format %{ "MSGFR $dst $src\t # long/int" %}
6414 opcode(MSGFR_ZOPC);
6415 ins_encode(z_rreform(dst, src));
6416 ins_pipe(pipe_class_dummy);
6417 %}
6418
6419 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
6420 match(Set dst (MulL dst src));
6421 ins_cost(DEFAULT_COST);
6422 size(4);
6423 format %{ "MSGR $dst $src\t # long" %}
6424 opcode(MSGR_ZOPC);
6425 ins_encode(z_rreform(dst, src));
6426 ins_pipe(pipe_class_dummy);
6427 %}
6428
6429 // Immediate Multiplication
6430 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
6431 match(Set dst (MulL dst src));
6432 ins_cost(DEFAULT_COST);
6433 // TODO: s390 port size(FIXED_SIZE);
6434 format %{ "MGHI $dst,$src\t # long" %}
6435 opcode(MGHI_ZOPC);
6436 ins_encode(z_riform_signed(dst, src));
6437 ins_pipe(pipe_class_dummy);
6438 %}
6439
6440 // Immediate (32bit) Multiplication
6441 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
6442 match(Set dst (MulL dst con));
6443 ins_cost(DEFAULT_COST);
6444 size(6);
6445 format %{ "MSGFI $dst,$con" %}
6446 opcode(MSGFI_ZOPC);
6447 ins_encode(z_rilform_signed(dst,con));
6448 ins_pipe(pipe_class_dummy);
6449 %}
6450
6451 instruct mulL_Reg_memI(iRegL dst, memory src)%{
6452 match(Set dst (MulL dst (ConvI2L (LoadI src))));
6453 ins_cost(MEMORY_REF_COST);
6454 size(Z_DISP3_SIZE);
6455 format %{ "MSGF $dst, $src\t # long" %}
6456 opcode(MSGF_ZOPC, MSGF_ZOPC);
6457 ins_encode(z_form_rt_mem_opt(dst, src));
6458 ins_pipe(pipe_class_dummy);
6459 %}
6460
6461 instruct mulL_Reg_mem(iRegL dst, memory src)%{
6462 match(Set dst (MulL dst (LoadL src)));
6463 ins_cost(MEMORY_REF_COST);
6464 size(Z_DISP3_SIZE);
6465 format %{ "MSG $dst, $src\t # long" %}
6466 opcode(MSG_ZOPC, MSG_ZOPC);
6467 ins_encode(z_form_rt_mem_opt(dst, src));
6468 ins_pipe(pipe_class_dummy);
6469 %}
6470
6471 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{
6472 match(Set Rdst (MulHiL Rsrc1 Rsrc2));
6473 effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr);
6474 ins_cost(7*DEFAULT_COST);
6475 // TODO: s390 port size(VARIABLE_SIZE);
6476 format %{ "MulHiL $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %}
6477 ins_encode%{
6478 Register dst = $Rdst$$Register;
6479 Register src1 = $Rsrc1$$Register;
6480 Register src2 = $Rsrc2$$Register;
6481 Register tmp1 = $Rtmp1$$Register;
6482 Register tmp2 = $Rdst$$Register;
6483 // z/Architecture has only unsigned multiply (64 * 64 -> 128).
6484 // implementing mulhs(a,b) = mulhu(a,b) – (a & (b>>63)) – (b & (a>>63))
6485 __ z_srag(tmp2, src1, 63); // a>>63
6486 __ z_srag(tmp1, src2, 63); // b>>63
6487 __ z_ngr(tmp2, src2); // b & (a>>63)
6488 __ z_ngr(tmp1, src1); // a & (b>>63)
6489 __ z_agr(tmp1, tmp2); // ((a & (b>>63)) + (b & (a>>63)))
6490 __ z_mlgr(dst, src2); // tricky: 128-bit product is written to even/odd pair (dst,src1),
6491 // multiplicand is taken from oddReg (src1), multiplier in src2.
6492 __ z_sgr(dst, tmp1);
6493 %}
6494 ins_pipe(pipe_class_dummy);
6495 %}
6496
6497 // DIV
6498
6499 // Integer DIVMOD with Register, both quotient and mod results
6500 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
6501 match(DivModI dst1src1 src2);
6502 effect(KILL cr);
6503 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6504 size((VM_Version::has_CompareBranch() ? 24 : 26));
6505 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
6506 ins_encode %{
6507 Register d1s1 = $dst1src1$$Register;
6508 Register d2 = $dst2$$Register;
6509 Register s2 = $src2$$Register;
6510
6511 assert_different_registers(d1s1, s2);
6512
6513 Label do_div, done_div;
6514 if (VM_Version::has_CompareBranch()) {
6515 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
6516 } else {
6517 __ z_chi(s2, -1);
6518 __ z_brne(do_div);
6519 }
6520 __ z_lcr(d1s1, d1s1);
6521 __ clear_reg(d2, false, false);
6522 __ z_bru(done_div);
6523 __ bind(do_div);
6524 __ z_lgfr(d1s1, d1s1);
6525 __ z_dsgfr(d2, s2);
6526 __ bind(done_div);
6527 %}
6528 ins_pipe(pipe_class_dummy);
6529 %}
6530
6531
6532 // Register Division
6533 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
6534 match(Set dst (DivI src1 src2));
6535 effect(KILL tmp, KILL cr);
6536 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6537 size((VM_Version::has_CompareBranch() ? 20 : 22));
6538 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
6539 ins_encode %{
6540 Register a = $src1$$Register;
6541 Register b = $src2$$Register;
6542 Register t = $dst$$Register;
6543
6544 assert_different_registers(t, b);
6545
6546 Label do_div, done_div;
6547 if (VM_Version::has_CompareBranch()) {
6548 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6549 } else {
6550 __ z_chi(b, -1);
6551 __ z_brne(do_div);
6552 }
6553 __ z_lcr(t, a);
6554 __ z_bru(done_div);
6555 __ bind(do_div);
6556 __ z_lgfr(t, a);
6557 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
6558 __ bind(done_div);
6559 %}
6560 ins_pipe(pipe_class_dummy);
6561 %}
6562
6563 // Immediate Division
6564 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
6565 match(Set dst (DivI src1 src2));
6566 effect(KILL tmp, KILL cr); // R0 is killed, too.
6567 ins_cost(2 * DEFAULT_COST);
6568 // TODO: s390 port size(VARIABLE_SIZE);
6569 format %{ "DIV_const $dst,$src1,$src2" %}
6570 ins_encode %{
6571 // No sign extension of Rdividend needed here.
6572 if ($src2$$constant != -1) {
6573 __ z_lghi(Z_R0_scratch, $src2$$constant);
6574 __ z_lgfr($dst$$Register, $src1$$Register);
6575 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6576 } else {
6577 __ z_lcr($dst$$Register, $src1$$Register);
6578 }
6579 %}
6580 ins_pipe(pipe_class_dummy);
6581 %}
6582
6583 // Long DIVMOD with Register, both quotient and mod results
6584 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
6585 match(DivModL dst1src1 src2);
6586 effect(KILL cr);
6587 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6588 size((VM_Version::has_CompareBranch() ? 22 : 24));
6589 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
6590 ins_encode %{
6591 Register d1s1 = $dst1src1$$Register;
6592 Register d2 = $dst2$$Register;
6593 Register s2 = $src2$$Register;
6594
6595 Label do_div, done_div;
6596 if (VM_Version::has_CompareBranch()) {
6597 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
6598 } else {
6599 __ z_cghi(s2, -1);
6600 __ z_brne(do_div);
6601 }
6602 __ z_lcgr(d1s1, d1s1);
6603 // indicate unused result
6604 (void) __ clear_reg(d2, true, false);
6605 __ z_bru(done_div);
6606 __ bind(do_div);
6607 __ z_dsgr(d2, s2);
6608 __ bind(done_div);
6609 %}
6610 ins_pipe(pipe_class_dummy);
6611 %}
6612
6613 // Register Long Division
6614 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
6615 match(Set dst (DivL dst src));
6616 effect(KILL tmp, KILL cr);
6617 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6618 size((VM_Version::has_CompareBranch() ? 18 : 20));
6619 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %}
6620 ins_encode %{
6621 Register b = $src$$Register;
6622 Register t = $dst$$Register;
6623
6624 Label done_div;
6625 __ z_lcgr(t, t); // Does no harm. divisor is in other register.
6626 if (VM_Version::has_CompareBranch()) {
6627 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6628 } else {
6629 __ z_cghi(b, -1);
6630 __ z_bre(done_div);
6631 }
6632 __ z_lcgr(t, t); // Restore sign.
6633 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
6634 __ bind(done_div);
6635 %}
6636 ins_pipe(pipe_class_dummy);
6637 %}
6638
6639 // Immediate Long Division
6640 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
6641 match(Set dst (DivL src1 src2));
6642 effect(KILL tmp, KILL cr); // R0 is killed, too.
6643 ins_cost(2 * DEFAULT_COST);
6644 // TODO: s390 port size(VARIABLE_SIZE);
6645 format %{ "DIVG_const $dst,$src1,$src2\t # long" %}
6646 ins_encode %{
6647 if ($src2$$constant != -1) {
6648 __ z_lghi(Z_R0_scratch, $src2$$constant);
6649 __ lgr_if_needed($dst$$Register, $src1$$Register);
6650 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6651 } else {
6652 __ z_lcgr($dst$$Register, $src1$$Register);
6653 }
6654 %}
6655 ins_pipe(pipe_class_dummy);
6656 %}
6657
6658 // REM
6659
6660 // Integer Remainder
6661 // Register Remainder
6662 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
6663 match(Set dst (ModI src1 src2));
6664 effect(KILL tmp, KILL cr);
6665 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6666 // TODO: s390 port size(VARIABLE_SIZE);
6667 format %{ "MOD_checked $dst,$src1,$src2" %}
6668 ins_encode %{
6669 Register a = $src1$$Register;
6670 Register b = $src2$$Register;
6671 Register t = $dst$$Register;
6672 assert_different_registers(t->successor(), b);
6673
6674 Label do_div, done_div;
6675
6676 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
6677 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs.
6678 if (VM_Version::has_CompareBranch()) {
6679 __ z_cij(b, -1, Assembler::bcondEqual, done_div);
6680 } else {
6681 __ z_chi(b, -1);
6682 __ z_bre(done_div);
6683 }
6684 __ z_lgfr(t->successor(), a);
6685 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6686 } else {
6687 if (VM_Version::has_CompareBranch()) {
6688 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6689 } else {
6690 __ z_chi(b, -1);
6691 __ z_brne(do_div);
6692 }
6693 __ clear_reg(t, true, false);
6694 __ z_bru(done_div);
6695 __ bind(do_div);
6696 __ z_lgfr(t->successor(), a);
6697 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6698 }
6699 __ bind(done_div);
6700 %}
6701 ins_pipe(pipe_class_dummy);
6702 %}
6703
6704 // Immediate Remainder
6705 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
6706 match(Set dst (ModI src1 src2));
6707 effect(KILL tmp, KILL cr); // R0 is killed, too.
6708 ins_cost(3 * DEFAULT_COST);
6709 // TODO: s390 port size(VARIABLE_SIZE);
6710 format %{ "MOD_const $dst,src1,$src2" %}
6711 ins_encode %{
6712 assert_different_registers($dst$$Register, $src1$$Register);
6713 assert_different_registers($dst$$Register->successor(), $src1$$Register);
6714 int divisor = $src2$$constant;
6715
6716 if (divisor != -1) {
6717 __ z_lghi(Z_R0_scratch, divisor);
6718 __ z_lgfr($dst$$Register->successor(), $src1$$Register);
6719 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6720 } else {
6721 __ clear_reg($dst$$Register, true, false);
6722 }
6723 %}
6724 ins_pipe(pipe_class_dummy);
6725 %}
6726
6727 // Register Long Remainder
6728 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
6729 match(Set dst (ModL src1 src2));
6730 effect(KILL src1, KILL cr); // R0 is killed, too.
6731 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6732 // TODO: s390 port size(VARIABLE_SIZE);
6733 format %{ "MODG_checked $dst,$src1,$src2" %}
6734 ins_encode %{
6735 Register a = $src1$$Register;
6736 Register b = $src2$$Register;
6737 Register t = $dst$$Register;
6738 assert(t->successor() == a, "(t,a) is an even-odd pair" );
6739
6740 Label do_div, done_div;
6741 if (t->encoding() != b->encoding()) {
6742 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
6743 if (VM_Version::has_CompareBranch()) {
6744 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6745 } else {
6746 __ z_cghi(b, -1);
6747 __ z_bre(done_div);
6748 }
6749 __ z_dsgr(t, b);
6750 } else {
6751 if (VM_Version::has_CompareBranch()) {
6752 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
6753 } else {
6754 __ z_cghi(b, -1);
6755 __ z_brne(do_div);
6756 }
6757 __ clear_reg(t, true, false);
6758 __ z_bru(done_div);
6759 __ bind(do_div);
6760 __ z_dsgr(t, b);
6761 }
6762 __ bind(done_div);
6763 %}
6764 ins_pipe(pipe_class_dummy);
6765 %}
6766
6767 // Register Long Remainder
6768 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
6769 match(Set dst (ModL src1 src2));
6770 effect(KILL tmp, KILL cr); // R0 is killed, too.
6771 ins_cost(3 * DEFAULT_COST);
6772 // TODO: s390 port size(VARIABLE_SIZE);
6773 format %{ "MODG_const $dst,src1,$src2\t # long" %}
6774 ins_encode %{
6775 int divisor = $src2$$constant;
6776 if (divisor != -1) {
6777 __ z_lghi(Z_R0_scratch, divisor);
6778 __ z_lgr($dst$$Register->successor(), $src1$$Register);
6779 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6780 } else {
6781 __ clear_reg($dst$$Register, true, false);
6782 }
6783 %}
6784 ins_pipe(pipe_class_dummy);
6785 %}
6786
6787 // SHIFT
6788
6789 // Shift left logical
6790
6791 // Register Shift Left variable
6792 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
6793 match(Set dst (LShiftI src nbits));
6794 effect(KILL cr); // R1 is killed, too.
6795 ins_cost(3 * DEFAULT_COST);
6796 size(14);
6797 format %{ "SLL $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %}
6798 ins_encode %{
6799 __ z_lgr(Z_R1_scratch, $nbits$$Register);
6800 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6801 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
6802 %}
6803 ins_pipe(pipe_class_dummy);
6804 %}
6805
6806 // Register Shift Left Immediate
6807 // Constant shift count is masked in ideal graph already.
6808 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
6809 match(Set dst (LShiftI src nbits));
6810 size(6);
6811 format %{ "SLL $dst,$src,$nbits\t # use RISC-like SLLG also for int" %}
6812 ins_encode %{
6813 int Nbit = $nbits$$constant;
6814 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6815 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6816 %}
6817 ins_pipe(pipe_class_dummy);
6818 %}
6819
6820 // Register Shift Left Immediate by 1bit
6821 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
6822 match(Set dst (LShiftI src nbits));
6823 predicate(PreferLAoverADD);
6824 ins_cost(DEFAULT_COST_LOW);
6825 size(4);
6826 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %}
6827 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
6828 ins_pipe(pipe_class_dummy);
6829 %}
6830
6831 // Register Shift Left Long
6832 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
6833 match(Set dst (LShiftL src1 nbits));
6834 size(6);
6835 format %{ "SLLG $dst,$src1,[$nbits]" %}
6836 opcode(SLLG_ZOPC);
6837 ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
6838 ins_pipe(pipe_class_dummy);
6839 %}
6840
6841 // Register Shift Left Long Immediate
6842 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
6843 match(Set dst (LShiftL src1 nbits));
6844 size(6);
6845 format %{ "SLLG $dst,$src1,$nbits" %}
6846 opcode(SLLG_ZOPC);
6847 ins_encode(z_rsyform_const(dst, src1, nbits));
6848 ins_pipe(pipe_class_dummy);
6849 %}
6850
6851 // Register Shift Left Long Immediate by 1bit
6852 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
6853 match(Set dst (LShiftL src1 nbits));
6854 predicate(PreferLAoverADD);
6855 ins_cost(DEFAULT_COST_LOW);
6856 size(4);
6857 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
6858 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
6859 ins_pipe(pipe_class_dummy);
6860 %}
6861
6862 // Shift right arithmetic
6863
6864 // Register Arithmetic Shift Right
6865 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
6866 match(Set dst (RShiftI dst src));
6867 effect(KILL cr); // R1 is killed, too.
6868 ins_cost(3 * DEFAULT_COST);
6869 size(12);
6870 format %{ "SRA $dst,[$src] & 31" %}
6871 ins_encode %{
6872 __ z_lgr(Z_R1_scratch, $src$$Register);
6873 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6874 __ z_sra($dst$$Register, 0, Z_R1_scratch);
6875 %}
6876 ins_pipe(pipe_class_dummy);
6877 %}
6878
6879 // Register Arithmetic Shift Right Immediate
6880 // Constant shift count is masked in ideal graph already.
6881 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
6882 match(Set dst (RShiftI dst src));
6883 effect(KILL cr);
6884 size(4);
6885 format %{ "SRA $dst,$src" %}
6886 ins_encode %{
6887 int Nbit = $src$$constant;
6888 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6889 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6890 %}
6891 ins_pipe(pipe_class_dummy);
6892 %}
6893
6894 // Register Arithmetic Shift Right Long
6895 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
6896 match(Set dst (RShiftL src1 src2));
6897 effect(KILL cr);
6898 size(6);
6899 format %{ "SRAG $dst,$src1,[$src2]" %}
6900 opcode(SRAG_ZOPC);
6901 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6902 ins_pipe(pipe_class_dummy);
6903 %}
6904
6905 // Register Arithmetic Shift Right Long Immediate
6906 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
6907 match(Set dst (RShiftL src1 src2));
6908 effect(KILL cr);
6909 size(6);
6910 format %{ "SRAG $dst,$src1,$src2" %}
6911 opcode(SRAG_ZOPC);
6912 ins_encode(z_rsyform_const(dst, src1, src2));
6913 ins_pipe(pipe_class_dummy);
6914 %}
6915
6916 // Shift right logical
6917
6918 // Register Shift Right
6919 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
6920 match(Set dst (URShiftI dst src));
6921 effect(KILL cr); // R1 is killed, too.
6922 ins_cost(3 * DEFAULT_COST);
6923 size(12);
6924 format %{ "SRL $dst,[$src] & 31" %}
6925 ins_encode %{
6926 __ z_lgr(Z_R1_scratch, $src$$Register);
6927 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6928 __ z_srl($dst$$Register, 0, Z_R1_scratch);
6929 %}
6930 ins_pipe(pipe_class_dummy);
6931 %}
6932
6933 // Register Shift Right Immediate
6934 // Constant shift count is masked in ideal graph already.
6935 instruct srlI_reg_imm(iRegI dst, immI src) %{
6936 match(Set dst (URShiftI dst src));
6937 size(4);
6938 format %{ "SRL $dst,$src" %}
6939 ins_encode %{
6940 int Nbit = $src$$constant;
6941 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6942 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6943 %}
6944 ins_pipe(pipe_class_dummy);
6945 %}
6946
6947 // Register Shift Right Long
6948 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
6949 match(Set dst (URShiftL src1 src2));
6950 size(6);
6951 format %{ "SRLG $dst,$src1,[$src2]" %}
6952 opcode(SRLG_ZOPC);
6953 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6954 ins_pipe(pipe_class_dummy);
6955 %}
6956
6957 // Register Shift Right Long Immediate
6958 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
6959 match(Set dst (URShiftL src1 src2));
6960 size(6);
6961 format %{ "SRLG $dst,$src1,$src2" %}
6962 opcode(SRLG_ZOPC);
6963 ins_encode(z_rsyform_const(dst, src1, src2));
6964 ins_pipe(pipe_class_dummy);
6965 %}
6966
6967 // Register Shift Right Immediate with a CastP2X
6968 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
6969 match(Set dst (URShiftL (CastP2X src1) src2));
6970 size(6);
6971 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
6972 opcode(SRLG_ZOPC);
6973 ins_encode(z_rsyform_const(dst, src1, src2));
6974 ins_pipe(pipe_class_dummy);
6975 %}
6976
6977 //----------Rotate Instructions------------------------------------------------
6978
6979 // Rotate left 32bit.
6980 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
6981 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
6982 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
6983 size(6);
6984 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %}
6985 opcode(RLL_ZOPC);
6986 ins_encode(z_rsyform_const(dst, src, lshift));
6987 ins_pipe(pipe_class_dummy);
6988 %}
6989
6990 // Rotate left 64bit.
6991 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
6992 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
6993 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
6994 size(6);
6995 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %}
6996 opcode(RLLG_ZOPC);
6997 ins_encode(z_rsyform_const(dst, src, lshift));
6998 ins_pipe(pipe_class_dummy);
6999 %}
7000
7001 // Rotate right 32bit.
7002 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
7003 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
7004 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7005 // TODO: s390 port size(FIXED_SIZE);
7006 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %}
7007 opcode(RLL_ZOPC);
7008 ins_encode(z_rsyform_const(dst, src, rshift));
7009 ins_pipe(pipe_class_dummy);
7010 %}
7011
7012 // Rotate right 64bit.
7013 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
7014 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
7015 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7016 // TODO: s390 port size(FIXED_SIZE);
7017 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %}
7018 opcode(RLLG_ZOPC);
7019 ins_encode(z_rsyform_const(dst, src, rshift));
7020 ins_pipe(pipe_class_dummy);
7021 %}
7022
7023
7024 //----------Overflow Math Instructions-----------------------------------------
7025
7026 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7027 match(Set cr (OverflowAddI op1 op2));
7028 effect(DEF cr, USE op1, USE op2);
7029 // TODO: s390 port size(FIXED_SIZE);
7030 format %{ "AR $op1,$op2\t # overflow check int" %}
7031 ins_encode %{
7032 __ z_lr(Z_R0_scratch, $op1$$Register);
7033 __ z_ar(Z_R0_scratch, $op2$$Register);
7034 %}
7035 ins_pipe(pipe_class_dummy);
7036 %}
7037
7038 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7039 match(Set cr (OverflowAddI op1 op2));
7040 effect(DEF cr, USE op1, USE op2);
7041 // TODO: s390 port size(VARIABLE_SIZE);
7042 format %{ "AR $op1,$op2\t # overflow check int" %}
7043 ins_encode %{
7044 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7045 __ z_ar(Z_R0_scratch, $op1$$Register);
7046 %}
7047 ins_pipe(pipe_class_dummy);
7048 %}
7049
7050 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7051 match(Set cr (OverflowAddL op1 op2));
7052 effect(DEF cr, USE op1, USE op2);
7053 // TODO: s390 port size(FIXED_SIZE);
7054 format %{ "AGR $op1,$op2\t # overflow check long" %}
7055 ins_encode %{
7056 __ z_lgr(Z_R0_scratch, $op1$$Register);
7057 __ z_agr(Z_R0_scratch, $op2$$Register);
7058 %}
7059 ins_pipe(pipe_class_dummy);
7060 %}
7061
7062 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7063 match(Set cr (OverflowAddL op1 op2));
7064 effect(DEF cr, USE op1, USE op2);
7065 // TODO: s390 port size(VARIABLE_SIZE);
7066 format %{ "AGR $op1,$op2\t # overflow check long" %}
7067 ins_encode %{
7068 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7069 __ z_agr(Z_R0_scratch, $op1$$Register);
7070 %}
7071 ins_pipe(pipe_class_dummy);
7072 %}
7073
7074 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7075 match(Set cr (OverflowSubI op1 op2));
7076 effect(DEF cr, USE op1, USE op2);
7077 // TODO: s390 port size(FIXED_SIZE);
7078 format %{ "SR $op1,$op2\t # overflow check int" %}
7079 ins_encode %{
7080 __ z_lr(Z_R0_scratch, $op1$$Register);
7081 __ z_sr(Z_R0_scratch, $op2$$Register);
7082 %}
7083 ins_pipe(pipe_class_dummy);
7084 %}
7085
7086 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7087 match(Set cr (OverflowSubI op1 op2));
7088 effect(DEF cr, USE op1, USE op2);
7089 // TODO: s390 port size(VARIABLE_SIZE);
7090 format %{ "SR $op1,$op2\t # overflow check int" %}
7091 ins_encode %{
7092 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7093 __ z_lr(Z_R0_scratch, $op1$$Register);
7094 __ z_sr(Z_R0_scratch, Z_R1_scratch);
7095 %}
7096 ins_pipe(pipe_class_dummy);
7097 %}
7098
7099 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7100 match(Set cr (OverflowSubL op1 op2));
7101 effect(DEF cr, USE op1, USE op2);
7102 // TODO: s390 port size(FIXED_SIZE);
7103 format %{ "SGR $op1,$op2\t # overflow check long" %}
7104 ins_encode %{
7105 __ z_lgr(Z_R0_scratch, $op1$$Register);
7106 __ z_sgr(Z_R0_scratch, $op2$$Register);
7107 %}
7108 ins_pipe(pipe_class_dummy);
7109 %}
7110
7111 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7112 match(Set cr (OverflowSubL op1 op2));
7113 effect(DEF cr, USE op1, USE op2);
7114 // TODO: s390 port size(VARIABLE_SIZE);
7115 format %{ "SGR $op1,$op2\t # overflow check long" %}
7116 ins_encode %{
7117 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7118 __ z_lgr(Z_R0_scratch, $op1$$Register);
7119 __ z_sgr(Z_R0_scratch, Z_R1_scratch);
7120 %}
7121 ins_pipe(pipe_class_dummy);
7122 %}
7123
7124 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
7125 match(Set cr (OverflowSubI zero op2));
7126 effect(DEF cr, USE op2);
7127 format %{ "NEG $op2\t # overflow check int" %}
7128 ins_encode %{
7129 __ clear_reg(Z_R0_scratch, false, false);
7130 __ z_sr(Z_R0_scratch, $op2$$Register);
7131 %}
7132 ins_pipe(pipe_class_dummy);
7133 %}
7134
7135 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
7136 match(Set cr (OverflowSubL zero op2));
7137 effect(DEF cr, USE op2);
7138 format %{ "NEGG $op2\t # overflow check long" %}
7139 ins_encode %{
7140 __ clear_reg(Z_R0_scratch, true, false);
7141 __ z_sgr(Z_R0_scratch, $op2$$Register);
7142 %}
7143 ins_pipe(pipe_class_dummy);
7144 %}
7145
7146 // No intrinsics for multiplication, since there is no easy way
7147 // to check for overflow.
7148
7149
7150 //----------Floating Point Arithmetic Instructions-----------------------------
7151
7152 // ADD
7153
7154 // Add float single precision
7155 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
7156 match(Set dst (AddF dst src));
7157 effect(KILL cr);
7158 ins_cost(ALU_REG_COST);
7159 size(4);
7160 format %{ "AEBR $dst,$src" %}
7161 opcode(AEBR_ZOPC);
7162 ins_encode(z_rreform(dst, src));
7163 ins_pipe(pipe_class_dummy);
7164 %}
7165
7166 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7167 match(Set dst (AddF dst (LoadF src)));
7168 effect(KILL cr);
7169 ins_cost(ALU_MEMORY_COST);
7170 size(6);
7171 format %{ "AEB $dst,$src\t # floatMemory" %}
7172 opcode(AEB_ZOPC);
7173 ins_encode(z_form_rt_memFP(dst, src));
7174 ins_pipe(pipe_class_dummy);
7175 %}
7176
7177 // Add float double precision
7178 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
7179 match(Set dst (AddD dst src));
7180 effect(KILL cr);
7181 ins_cost(ALU_REG_COST);
7182 size(4);
7183 format %{ "ADBR $dst,$src" %}
7184 opcode(ADBR_ZOPC);
7185 ins_encode(z_rreform(dst, src));
7186 ins_pipe(pipe_class_dummy);
7187 %}
7188
7189 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7190 match(Set dst (AddD dst (LoadD src)));
7191 effect(KILL cr);
7192 ins_cost(ALU_MEMORY_COST);
7193 size(6);
7194 format %{ "ADB $dst,$src\t # doubleMemory" %}
7195 opcode(ADB_ZOPC);
7196 ins_encode(z_form_rt_memFP(dst, src));
7197 ins_pipe(pipe_class_dummy);
7198 %}
7199
7200 // SUB
7201
7202 // Sub float single precision
7203 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
7204 match(Set dst (SubF dst src));
7205 effect(KILL cr);
7206 ins_cost(ALU_REG_COST);
7207 size(4);
7208 format %{ "SEBR $dst,$src" %}
7209 opcode(SEBR_ZOPC);
7210 ins_encode(z_rreform(dst, src));
7211 ins_pipe(pipe_class_dummy);
7212 %}
7213
7214 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7215 match(Set dst (SubF dst (LoadF src)));
7216 effect(KILL cr);
7217 ins_cost(ALU_MEMORY_COST);
7218 size(6);
7219 format %{ "SEB $dst,$src\t # floatMemory" %}
7220 opcode(SEB_ZOPC);
7221 ins_encode(z_form_rt_memFP(dst, src));
7222 ins_pipe(pipe_class_dummy);
7223 %}
7224
7225 // Sub float double precision
7226 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
7227 match(Set dst (SubD dst src));
7228 effect(KILL cr);
7229 ins_cost(ALU_REG_COST);
7230 size(4);
7231 format %{ "SDBR $dst,$src" %}
7232 opcode(SDBR_ZOPC);
7233 ins_encode(z_rreform(dst, src));
7234 ins_pipe(pipe_class_dummy);
7235 %}
7236
7237 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7238 match(Set dst (SubD dst (LoadD src)));
7239 effect(KILL cr);
7240 ins_cost(ALU_MEMORY_COST);
7241 size(6);
7242 format %{ "SDB $dst,$src\t # doubleMemory" %}
7243 opcode(SDB_ZOPC);
7244 ins_encode(z_form_rt_memFP(dst, src));
7245 ins_pipe(pipe_class_dummy);
7246 %}
7247
7248 // MUL
7249
7250 // Mul float single precision
7251 instruct mulF_reg_reg(regF dst, regF src) %{
7252 match(Set dst (MulF dst src));
7253 // CC unchanged by MUL.
7254 ins_cost(ALU_REG_COST);
7255 size(4);
7256 format %{ "MEEBR $dst,$src" %}
7257 opcode(MEEBR_ZOPC);
7258 ins_encode(z_rreform(dst, src));
7259 ins_pipe(pipe_class_dummy);
7260 %}
7261
7262 instruct mulF_reg_mem(regF dst, memoryRX src)%{
7263 match(Set dst (MulF dst (LoadF src)));
7264 // CC unchanged by MUL.
7265 ins_cost(ALU_MEMORY_COST);
7266 size(6);
7267 format %{ "MEEB $dst,$src\t # floatMemory" %}
7268 opcode(MEEB_ZOPC);
7269 ins_encode(z_form_rt_memFP(dst, src));
7270 ins_pipe(pipe_class_dummy);
7271 %}
7272
7273 // Mul float double precision
7274 instruct mulD_reg_reg(regD dst, regD src) %{
7275 match(Set dst (MulD dst src));
7276 // CC unchanged by MUL.
7277 ins_cost(ALU_REG_COST);
7278 size(4);
7279 format %{ "MDBR $dst,$src" %}
7280 opcode(MDBR_ZOPC);
7281 ins_encode(z_rreform(dst, src));
7282 ins_pipe(pipe_class_dummy);
7283 %}
7284
7285 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7286 match(Set dst (MulD dst (LoadD src)));
7287 // CC unchanged by MUL.
7288 ins_cost(ALU_MEMORY_COST);
7289 size(6);
7290 format %{ "MDB $dst,$src\t # doubleMemory" %}
7291 opcode(MDB_ZOPC);
7292 ins_encode(z_form_rt_memFP(dst, src));
7293 ins_pipe(pipe_class_dummy);
7294 %}
7295
7296 // Multiply-Accumulate
7297 // src1 * src2 + dst
7298 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
7299 match(Set dst (FmaF dst (Binary src1 src2)));
7300 // CC unchanged by MUL-ADD.
7301 ins_cost(ALU_REG_COST);
7302 size(4);
7303 format %{ "MAEBR $dst, $src1, $src2" %}
7304 ins_encode %{
7305 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7306 %}
7307 ins_pipe(pipe_class_dummy);
7308 %}
7309
7310 // src1 * src2 + dst
7311 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
7312 match(Set dst (FmaD dst (Binary src1 src2)));
7313 // CC unchanged by MUL-ADD.
7314 ins_cost(ALU_REG_COST);
7315 size(4);
7316 format %{ "MADBR $dst, $src1, $src2" %}
7317 ins_encode %{
7318 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7319 %}
7320 ins_pipe(pipe_class_dummy);
7321 %}
7322
7323 // src1 * src2 - dst
7324 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
7325 match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
7326 // CC unchanged by MUL-SUB.
7327 ins_cost(ALU_REG_COST);
7328 size(4);
7329 format %{ "MSEBR $dst, $src1, $src2" %}
7330 ins_encode %{
7331 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7332 %}
7333 ins_pipe(pipe_class_dummy);
7334 %}
7335
7336 // src1 * src2 - dst
7337 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
7338 match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
7339 // CC unchanged by MUL-SUB.
7340 ins_cost(ALU_REG_COST);
7341 size(4);
7342 format %{ "MSDBR $dst, $src1, $src2" %}
7343 ins_encode %{
7344 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7345 %}
7346 ins_pipe(pipe_class_dummy);
7347 %}
7348
7349 // src1 * src2 + dst
7350 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7351 match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
7352 // CC unchanged by MUL-ADD.
7353 ins_cost(ALU_MEMORY_COST);
7354 size(6);
7355 format %{ "MAEB $dst, $src1, $src2" %}
7356 ins_encode %{
7357 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
7358 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7359 %}
7360 ins_pipe(pipe_class_dummy);
7361 %}
7362
7363 // src1 * src2 + dst
7364 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7365 match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
7366 // CC unchanged by MUL-ADD.
7367 ins_cost(ALU_MEMORY_COST);
7368 size(6);
7369 format %{ "MADB $dst, $src1, $src2" %}
7370 ins_encode %{
7371 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
7372 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7373 %}
7374 ins_pipe(pipe_class_dummy);
7375 %}
7376
7377 // src1 * src2 - dst
7378 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7379 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
7380 // CC unchanged by MUL-SUB.
7381 ins_cost(ALU_MEMORY_COST);
7382 size(6);
7383 format %{ "MSEB $dst, $src1, $src2" %}
7384 ins_encode %{
7385 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
7386 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7387 %}
7388 ins_pipe(pipe_class_dummy);
7389 %}
7390
7391 // src1 * src2 - dst
7392 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7393 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
7394 // CC unchanged by MUL-SUB.
7395 ins_cost(ALU_MEMORY_COST);
7396 size(6);
7397 format %{ "MSDB $dst, $src1, $src2" %}
7398 ins_encode %{
7399 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
7400 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7401 %}
7402 ins_pipe(pipe_class_dummy);
7403 %}
7404
7405 // src1 * src2 + dst
7406 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7407 match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
7408 // CC unchanged by MUL-ADD.
7409 ins_cost(ALU_MEMORY_COST);
7410 size(6);
7411 format %{ "MAEB $dst, $src1, $src2" %}
7412 ins_encode %{
7413 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
7414 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7415 %}
7416 ins_pipe(pipe_class_dummy);
7417 %}
7418
7419 // src1 * src2 + dst
7420 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7421 match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
7422 // CC unchanged by MUL-ADD.
7423 ins_cost(ALU_MEMORY_COST);
7424 size(6);
7425 format %{ "MADB $dst, $src1, $src2" %}
7426 ins_encode %{
7427 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
7428 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7429 %}
7430 ins_pipe(pipe_class_dummy);
7431 %}
7432
7433 // src1 * src2 - dst
7434 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7435 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
7436 // CC unchanged by MUL-SUB.
7437 ins_cost(ALU_MEMORY_COST);
7438 size(6);
7439 format %{ "MSEB $dst, $src1, $src2" %}
7440 ins_encode %{
7441 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
7442 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7443 %}
7444 ins_pipe(pipe_class_dummy);
7445 %}
7446
7447 // src1 * src2 - dst
7448 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7449 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
7450 // CC unchanged by MUL-SUB.
7451 ins_cost(ALU_MEMORY_COST);
7452 size(6);
7453 format %{ "MSDB $dst, $src1, $src2" %}
7454 ins_encode %{
7455 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
7456 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7457 %}
7458 ins_pipe(pipe_class_dummy);
7459 %}
7460
7461 // DIV
7462
7463 // Div float single precision
7464 instruct divF_reg_reg(regF dst, regF src) %{
7465 match(Set dst (DivF dst src));
7466 // CC unchanged by DIV.
7467 ins_cost(ALU_REG_COST);
7468 size(4);
7469 format %{ "DEBR $dst,$src" %}
7470 opcode(DEBR_ZOPC);
7471 ins_encode(z_rreform(dst, src));
7472 ins_pipe(pipe_class_dummy);
7473 %}
7474
7475 instruct divF_reg_mem(regF dst, memoryRX src)%{
7476 match(Set dst (DivF dst (LoadF src)));
7477 // CC unchanged by DIV.
7478 ins_cost(ALU_MEMORY_COST);
7479 size(6);
7480 format %{ "DEB $dst,$src\t # floatMemory" %}
7481 opcode(DEB_ZOPC);
7482 ins_encode(z_form_rt_memFP(dst, src));
7483 ins_pipe(pipe_class_dummy);
7484 %}
7485
7486 // Div float double precision
7487 instruct divD_reg_reg(regD dst, regD src) %{
7488 match(Set dst (DivD dst src));
7489 // CC unchanged by DIV.
7490 ins_cost(ALU_REG_COST);
7491 size(4);
7492 format %{ "DDBR $dst,$src" %}
7493 opcode(DDBR_ZOPC);
7494 ins_encode(z_rreform(dst, src));
7495 ins_pipe(pipe_class_dummy);
7496 %}
7497
7498 instruct divD_reg_mem(regD dst, memoryRX src)%{
7499 match(Set dst (DivD dst (LoadD src)));
7500 // CC unchanged by DIV.
7501 ins_cost(ALU_MEMORY_COST);
7502 size(6);
7503 format %{ "DDB $dst,$src\t # doubleMemory" %}
7504 opcode(DDB_ZOPC);
7505 ins_encode(z_form_rt_memFP(dst, src));
7506 ins_pipe(pipe_class_dummy);
7507 %}
7508
7509 // ABS
7510
7511 // Absolute float single precision
7512 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
7513 match(Set dst (AbsF src));
7514 effect(KILL cr);
7515 size(4);
7516 format %{ "LPEBR $dst,$src\t float" %}
7517 opcode(LPEBR_ZOPC);
7518 ins_encode(z_rreform(dst, src));
7519 ins_pipe(pipe_class_dummy);
7520 %}
7521
7522 // Absolute float double precision
7523 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
7524 match(Set dst (AbsD src));
7525 effect(KILL cr);
7526 size(4);
7527 format %{ "LPDBR $dst,$src\t double" %}
7528 opcode(LPDBR_ZOPC);
7529 ins_encode(z_rreform(dst, src));
7530 ins_pipe(pipe_class_dummy);
7531 %}
7532
7533 // NEG(ABS)
7534
7535 // Negative absolute float single precision
7536 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
7537 match(Set dst (NegF (AbsF src)));
7538 effect(KILL cr);
7539 size(4);
7540 format %{ "LNEBR $dst,$src\t float" %}
7541 opcode(LNEBR_ZOPC);
7542 ins_encode(z_rreform(dst, src));
7543 ins_pipe(pipe_class_dummy);
7544 %}
7545
7546 // Negative absolute float double precision
7547 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
7548 match(Set dst (NegD (AbsD src)));
7549 effect(KILL cr);
7550 size(4);
7551 format %{ "LNDBR $dst,$src\t double" %}
7552 opcode(LNDBR_ZOPC);
7553 ins_encode(z_rreform(dst, src));
7554 ins_pipe(pipe_class_dummy);
7555 %}
7556
7557 // NEG
7558
7559 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
7560 match(Set dst (NegF src));
7561 effect(KILL cr);
7562 size(4);
7563 format %{ "NegF $dst,$src\t float" %}
7564 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
7565 ins_pipe(pipe_class_dummy);
7566 %}
7567
7568 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
7569 match(Set dst (NegD src));
7570 effect(KILL cr);
7571 size(4);
7572 format %{ "NegD $dst,$src\t double" %}
7573 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
7574 ins_pipe(pipe_class_dummy);
7575 %}
7576
7577 // SQRT
7578
7579 // Sqrt float precision
7580 instruct sqrtF_reg(regF dst, regF src) %{
7581 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7582 // CC remains unchanged.
7583 ins_cost(ALU_REG_COST);
7584 size(4);
7585 format %{ "SQEBR $dst,$src" %}
7586 opcode(SQEBR_ZOPC);
7587 ins_encode(z_rreform(dst, src));
7588 ins_pipe(pipe_class_dummy);
7589 %}
7590
7591 // Sqrt double precision
7592 instruct sqrtD_reg(regD dst, regD src) %{
7593 match(Set dst (SqrtD src));
7594 // CC remains unchanged.
7595 ins_cost(ALU_REG_COST);
7596 size(4);
7597 format %{ "SQDBR $dst,$src" %}
7598 opcode(SQDBR_ZOPC);
7599 ins_encode(z_rreform(dst, src));
7600 ins_pipe(pipe_class_dummy);
7601 %}
7602
7603 instruct sqrtF_mem(regF dst, memoryRX src) %{
7604 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7605 // CC remains unchanged.
7606 ins_cost(ALU_MEMORY_COST);
7607 size(6);
7608 format %{ "SQEB $dst,$src\t # floatMemory" %}
7609 opcode(SQEB_ZOPC);
7610 ins_encode(z_form_rt_memFP(dst, src));
7611 ins_pipe(pipe_class_dummy);
7612 %}
7613
7614 instruct sqrtD_mem(regD dst, memoryRX src) %{
7615 match(Set dst (SqrtD src));
7616 // CC remains unchanged.
7617 ins_cost(ALU_MEMORY_COST);
7618 // TODO: s390 port size(FIXED_SIZE);
7619 format %{ "SQDB $dst,$src\t # doubleMemory" %}
7620 opcode(SQDB_ZOPC);
7621 ins_encode(z_form_rt_memFP(dst, src));
7622 ins_pipe(pipe_class_dummy);
7623 %}
7624
7625 //----------Logical Instructions-----------------------------------------------
7626
7627 // Register And
7628 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7629 match(Set dst (AndI dst src));
7630 effect(KILL cr);
7631 ins_cost(DEFAULT_COST_LOW);
7632 size(2);
7633 format %{ "NR $dst,$src\t # int" %}
7634 opcode(NR_ZOPC);
7635 ins_encode(z_rrform(dst, src));
7636 ins_pipe(pipe_class_dummy);
7637 %}
7638
7639 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7640 match(Set dst (AndI dst (LoadI src)));
7641 effect(KILL cr);
7642 ins_cost(MEMORY_REF_COST);
7643 // TODO: s390 port size(VARIABLE_SIZE);
7644 format %{ "N(Y) $dst, $src\t # int" %}
7645 opcode(NY_ZOPC, N_ZOPC);
7646 ins_encode(z_form_rt_mem_opt(dst, src));
7647 ins_pipe(pipe_class_dummy);
7648 %}
7649
7650 // Immediate And
7651 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7652 match(Set dst (AndI dst src));
7653 effect(KILL cr);
7654 ins_cost(DEFAULT_COST_HIGH);
7655 size(6);
7656 format %{ "NILF $dst,$src" %}
7657 opcode(NILF_ZOPC);
7658 ins_encode(z_rilform_unsigned(dst, src));
7659 ins_pipe(pipe_class_dummy);
7660 %}
7661
7662 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
7663 match(Set dst (AndI dst src));
7664 effect(KILL cr);
7665 ins_cost(DEFAULT_COST);
7666 size(4);
7667 format %{ "NILH $dst,$src" %}
7668 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7669 ins_pipe(pipe_class_dummy);
7670 %}
7671
7672 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
7673 match(Set dst (AndI dst src));
7674 effect(KILL cr);
7675 ins_cost(DEFAULT_COST);
7676 size(4);
7677 format %{ "NILL $dst,$src" %}
7678 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7679 ins_pipe(pipe_class_dummy);
7680 %}
7681
7682 // Register And Long
7683 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7684 match(Set dst (AndL dst src));
7685 effect(KILL cr);
7686 ins_cost(DEFAULT_COST);
7687 size(4);
7688 format %{ "NGR $dst,$src\t # long" %}
7689 opcode(NGR_ZOPC);
7690 ins_encode(z_rreform(dst, src));
7691 ins_pipe(pipe_class_dummy);
7692 %}
7693
7694 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7695 match(Set dst (AndL dst (LoadL src)));
7696 effect(KILL cr);
7697 ins_cost(MEMORY_REF_COST);
7698 size(Z_DISP3_SIZE);
7699 format %{ "NG $dst, $src\t # long" %}
7700 opcode(NG_ZOPC, NG_ZOPC);
7701 ins_encode(z_form_rt_mem_opt(dst, src));
7702 ins_pipe(pipe_class_dummy);
7703 %}
7704
7705 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
7706 match(Set dst (AndL dst src));
7707 effect(KILL cr);
7708 ins_cost(DEFAULT_COST);
7709 size(4);
7710 format %{ "NILL $dst,$src\t # long" %}
7711 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7712 ins_pipe(pipe_class_dummy);
7713 %}
7714
7715 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
7716 match(Set dst (AndL dst src));
7717 effect(KILL cr);
7718 ins_cost(DEFAULT_COST);
7719 size(4);
7720 format %{ "NILH $dst,$src\t # long" %}
7721 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7722 ins_pipe(pipe_class_dummy);
7723 %}
7724
7725 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
7726 match(Set dst (AndL dst src));
7727 effect(KILL cr);
7728 ins_cost(DEFAULT_COST);
7729 size(4);
7730 format %{ "NIHL $dst,$src\t # long" %}
7731 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
7732 ins_pipe(pipe_class_dummy);
7733 %}
7734
7735 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
7736 match(Set dst (AndL dst src));
7737 effect(KILL cr);
7738 ins_cost(DEFAULT_COST);
7739 size(4);
7740 format %{ "NIHH $dst,$src\t # long" %}
7741 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
7742 ins_pipe(pipe_class_dummy);
7743 %}
7744
7745 // OR
7746
7747 // Or Instructions
7748 // Register Or
7749 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7750 match(Set dst (OrI dst src));
7751 effect(KILL cr);
7752 size(2);
7753 format %{ "OR $dst,$src" %}
7754 opcode(OR_ZOPC);
7755 ins_encode(z_rrform(dst, src));
7756 ins_pipe(pipe_class_dummy);
7757 %}
7758
7759 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7760 match(Set dst (OrI dst (LoadI src)));
7761 effect(KILL cr);
7762 ins_cost(MEMORY_REF_COST);
7763 // TODO: s390 port size(VARIABLE_SIZE);
7764 format %{ "O(Y) $dst, $src\t # int" %}
7765 opcode(OY_ZOPC, O_ZOPC);
7766 ins_encode(z_form_rt_mem_opt(dst, src));
7767 ins_pipe(pipe_class_dummy);
7768 %}
7769
7770 // Immediate Or
7771 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
7772 match(Set dst (OrI dst con));
7773 effect(KILL cr);
7774 size(4);
7775 format %{ "OILL $dst,$con" %}
7776 opcode(OILL_ZOPC);
7777 ins_encode(z_riform_unsigned(dst,con));
7778 ins_pipe(pipe_class_dummy);
7779 %}
7780
7781 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
7782 match(Set dst (OrI dst con));
7783 effect(KILL cr);
7784 ins_cost(DEFAULT_COST_HIGH);
7785 size(6);
7786 format %{ "OILF $dst,$con" %}
7787 opcode(OILF_ZOPC);
7788 ins_encode(z_rilform_unsigned(dst,con));
7789 ins_pipe(pipe_class_dummy);
7790 %}
7791
7792 // Register Or Long
7793 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7794 match(Set dst (OrL dst src));
7795 effect(KILL cr);
7796 ins_cost(DEFAULT_COST);
7797 size(4);
7798 format %{ "OGR $dst,$src\t # long" %}
7799 opcode(OGR_ZOPC);
7800 ins_encode(z_rreform(dst, src));
7801 ins_pipe(pipe_class_dummy);
7802 %}
7803
7804 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7805 match(Set dst (OrL dst (LoadL src)));
7806 effect(KILL cr);
7807 ins_cost(MEMORY_REF_COST);
7808 size(Z_DISP3_SIZE);
7809 format %{ "OG $dst, $src\t # long" %}
7810 opcode(OG_ZOPC, OG_ZOPC);
7811 ins_encode(z_form_rt_mem_opt(dst, src));
7812 ins_pipe(pipe_class_dummy);
7813 %}
7814
7815 // Immediate Or long
7816 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
7817 match(Set dst (OrL dst con));
7818 effect(KILL cr);
7819 ins_cost(DEFAULT_COST);
7820 size(4);
7821 format %{ "OILL $dst,$con\t # long" %}
7822 opcode(OILL_ZOPC);
7823 ins_encode(z_riform_unsigned(dst,con));
7824 ins_pipe(pipe_class_dummy);
7825 %}
7826
7827 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
7828 match(Set dst (OrI dst con));
7829 effect(KILL cr);
7830 ins_cost(DEFAULT_COST_HIGH);
7831 // TODO: s390 port size(FIXED_SIZE);
7832 format %{ "OILF $dst,$con\t # long" %}
7833 opcode(OILF_ZOPC);
7834 ins_encode(z_rilform_unsigned(dst,con));
7835 ins_pipe(pipe_class_dummy);
7836 %}
7837
7838 // XOR
7839
7840 // Register Xor
7841 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7842 match(Set dst (XorI dst src));
7843 effect(KILL cr);
7844 size(2);
7845 format %{ "XR $dst,$src" %}
7846 opcode(XR_ZOPC);
7847 ins_encode(z_rrform(dst, src));
7848 ins_pipe(pipe_class_dummy);
7849 %}
7850
7851 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7852 match(Set dst (XorI dst (LoadI src)));
7853 effect(KILL cr);
7854 ins_cost(MEMORY_REF_COST);
7855 // TODO: s390 port size(VARIABLE_SIZE);
7856 format %{ "X(Y) $dst, $src\t # int" %}
7857 opcode(XY_ZOPC, X_ZOPC);
7858 ins_encode(z_form_rt_mem_opt(dst, src));
7859 ins_pipe(pipe_class_dummy);
7860 %}
7861
7862 // Immediate Xor
7863 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7864 match(Set dst (XorI dst src));
7865 effect(KILL cr);
7866 ins_cost(DEFAULT_COST_HIGH);
7867 size(6);
7868 format %{ "XILF $dst,$src" %}
7869 opcode(XILF_ZOPC);
7870 ins_encode(z_rilform_unsigned(dst, src));
7871 ins_pipe(pipe_class_dummy);
7872 %}
7873
7874 // Register Xor Long
7875 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7876 match(Set dst (XorL dst src));
7877 effect(KILL cr);
7878 ins_cost(DEFAULT_COST);
7879 size(4);
7880 format %{ "XGR $dst,$src\t # long" %}
7881 opcode(XGR_ZOPC);
7882 ins_encode(z_rreform(dst, src));
7883 ins_pipe(pipe_class_dummy);
7884 %}
7885
7886 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7887 match(Set dst (XorL dst (LoadL src)));
7888 effect(KILL cr);
7889 ins_cost(MEMORY_REF_COST);
7890 size(Z_DISP3_SIZE);
7891 format %{ "XG $dst, $src\t # long" %}
7892 opcode(XG_ZOPC, XG_ZOPC);
7893 ins_encode(z_form_rt_mem_opt(dst, src));
7894 ins_pipe(pipe_class_dummy);
7895 %}
7896
7897 // Immediate Xor Long
7898 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
7899 match(Set dst (XorL dst con));
7900 effect(KILL cr);
7901 ins_cost(DEFAULT_COST_HIGH);
7902 size(6);
7903 format %{ "XILF $dst,$con\t # long" %}
7904 opcode(XILF_ZOPC);
7905 ins_encode(z_rilform_unsigned(dst,con));
7906 ins_pipe(pipe_class_dummy);
7907 %}
7908
7909 //----------Convert to Boolean-------------------------------------------------
7910
7911 // Convert integer to boolean.
7912 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
7913 match(Set dst (Conv2B src));
7914 effect(KILL cr);
7915 ins_cost(3 * DEFAULT_COST);
7916 size(6);
7917 format %{ "convI2B $dst,$src" %}
7918 ins_encode %{
7919 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
7920 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest)
7921 %}
7922 ins_pipe(pipe_class_dummy);
7923 %}
7924
7925 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
7926 match(Set dst (Conv2B src));
7927 effect(KILL cr);
7928 ins_cost(3 * DEFAULT_COST);
7929 size(10);
7930 format %{ "convP2B $dst,$src" %}
7931 ins_encode %{
7932 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
7933 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
7934 %}
7935 ins_pipe(pipe_class_dummy);
7936 %}
7937
7938 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7939 match(Set dst (CmpLTMask dst src));
7940 effect(KILL cr);
7941 ins_cost(2 * DEFAULT_COST);
7942 size(18);
7943 format %{ "Set $dst CmpLTMask $dst,$src" %}
7944 ins_encode %{
7945 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
7946 __ z_lgfr(Z_R0_scratch, $src$$Register);
7947 __ z_lgfr($dst$$Register, $dst$$Register);
7948 __ z_sgr($dst$$Register, Z_R0_scratch);
7949 __ z_srag($dst$$Register, $dst$$Register, 63);
7950 %}
7951 ins_pipe(pipe_class_dummy);
7952 %}
7953
7954 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
7955 match(Set dst (CmpLTMask dst zero));
7956 effect(KILL cr);
7957 ins_cost(DEFAULT_COST);
7958 size(4);
7959 format %{ "Set $dst CmpLTMask $dst,$zero" %}
7960 ins_encode %{ __ z_sra($dst$$Register, 31); %}
7961 ins_pipe(pipe_class_dummy);
7962 %}
7963
7964
7965 //----------Arithmetic Conversion Instructions---------------------------------
7966 // The conversions operations are all Alpha sorted. Please keep it that way!
7967
7968 instruct convD2F_reg(regF dst, regD src) %{
7969 match(Set dst (ConvD2F src));
7970 // CC remains unchanged.
7971 size(4);
7972 format %{ "LEDBR $dst,$src" %}
7973 opcode(LEDBR_ZOPC);
7974 ins_encode(z_rreform(dst, src));
7975 ins_pipe(pipe_class_dummy);
7976 %}
7977
7978 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
7979 match(Set dst (ConvF2I src));
7980 effect(KILL cr);
7981 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7982 size(16);
7983 format %{ "convF2I $dst,$src" %}
7984 ins_encode %{
7985 Label done;
7986 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
7987 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
7988 __ z_brno(done); // Result is zero if unordered argument.
7989 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
7990 __ bind(done);
7991 %}
7992 ins_pipe(pipe_class_dummy);
7993 %}
7994
7995 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
7996 match(Set dst (ConvD2I src));
7997 effect(KILL cr);
7998 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7999 size(16);
8000 format %{ "convD2I $dst,$src" %}
8001 ins_encode %{
8002 Label done;
8003 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
8004 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8005 __ z_brno(done); // Result is zero if unordered argument.
8006 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8007 __ bind(done);
8008 %}
8009 ins_pipe(pipe_class_dummy);
8010 %}
8011
8012 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
8013 match(Set dst (ConvF2L src));
8014 effect(KILL cr);
8015 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8016 size(16);
8017 format %{ "convF2L $dst,$src" %}
8018 ins_encode %{
8019 Label done;
8020 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8021 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
8022 __ z_brno(done); // Result is zero if unordered argument.
8023 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8024 __ bind(done);
8025 %}
8026 ins_pipe(pipe_class_dummy);
8027 %}
8028
8029 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
8030 match(Set dst (ConvD2L src));
8031 effect(KILL cr);
8032 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8033 size(16);
8034 format %{ "convD2L $dst,$src" %}
8035 ins_encode %{
8036 Label done;
8037 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8038 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8039 __ z_brno(done); // Result is zero if unordered argument.
8040 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8041 __ bind(done);
8042 %}
8043 ins_pipe(pipe_class_dummy);
8044 %}
8045
8046 instruct convF2D_reg(regD dst, regF src) %{
8047 match(Set dst (ConvF2D src));
8048 // CC remains unchanged.
8049 size(4);
8050 format %{ "LDEBR $dst,$src" %}
8051 opcode(LDEBR_ZOPC);
8052 ins_encode(z_rreform(dst, src));
8053 ins_pipe(pipe_class_dummy);
8054 %}
8055
8056 instruct convF2D_mem(regD dst, memoryRX src) %{
8057 match(Set dst (ConvF2D src));
8058 // CC remains unchanged.
8059 size(6);
8060 format %{ "LDEB $dst,$src" %}
8061 opcode(LDEB_ZOPC);
8062 ins_encode(z_form_rt_memFP(dst, src));
8063 ins_pipe(pipe_class_dummy);
8064 %}
8065
8066 instruct convI2D_reg(regD dst, iRegI src) %{
8067 match(Set dst (ConvI2D src));
8068 // CC remains unchanged.
8069 ins_cost(DEFAULT_COST);
8070 size(4);
8071 format %{ "CDFBR $dst,$src" %}
8072 opcode(CDFBR_ZOPC);
8073 ins_encode(z_rreform(dst, src));
8074 ins_pipe(pipe_class_dummy);
8075 %}
8076
8077 // Optimization that saves up to two memory operations for each conversion.
8078 instruct convI2F_ireg(regF dst, iRegI src) %{
8079 match(Set dst (ConvI2F src));
8080 // CC remains unchanged.
8081 ins_cost(DEFAULT_COST);
8082 size(4);
8083 format %{ "CEFBR $dst,$src\t # convert int to float" %}
8084 opcode(CEFBR_ZOPC);
8085 ins_encode(z_rreform(dst, src));
8086 ins_pipe(pipe_class_dummy);
8087 %}
8088
8089 instruct convI2L_reg(iRegL dst, iRegI src) %{
8090 match(Set dst (ConvI2L src));
8091 size(4);
8092 format %{ "LGFR $dst,$src\t # int->long" %}
8093 opcode(LGFR_ZOPC);
8094 ins_encode(z_rreform(dst, src));
8095 ins_pipe(pipe_class_dummy);
8096 %}
8097
8098 // Zero-extend convert int to long.
8099 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
8100 match(Set dst (AndL (ConvI2L src) mask));
8101 size(4);
8102 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %}
8103 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8104 ins_pipe(pipe_class_dummy);
8105 %}
8106
8107 // Zero-extend convert int to long.
8108 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
8109 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
8110 // Uses load_const_optmized, so size can vary.
8111 // TODO: s390 port size(VARIABLE_SIZE);
8112 format %{ "LLGF $dst, $src \t # zero-extend int to long" %}
8113 opcode(LLGF_ZOPC, LLGF_ZOPC);
8114 ins_encode(z_form_rt_mem_opt(dst, src));
8115 ins_pipe(pipe_class_dummy);
8116 %}
8117
8118 // Zero-extend long
8119 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
8120 match(Set dst (AndL src mask));
8121 size(4);
8122 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %}
8123 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8124 ins_pipe(pipe_class_dummy);
8125 %}
8126
8127 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
8128 match(Set dst (RShiftI (LShiftI src amount) amount));
8129 size(4);
8130 format %{ "LHR $dst,$src\t short->int" %}
8131 opcode(LHR_ZOPC);
8132 ins_encode(z_rreform(dst, src));
8133 ins_pipe(pipe_class_dummy);
8134 %}
8135
8136 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
8137 match(Set dst (RShiftI (LShiftI src amount) amount));
8138 size(4);
8139 format %{ "LBR $dst,$src\t byte->int" %}
8140 opcode(LBR_ZOPC);
8141 ins_encode(z_rreform(dst, src));
8142 ins_pipe(pipe_class_dummy);
8143 %}
8144
8145 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8146 match(Set dst (MoveF2I src));
8147 ins_cost(MEMORY_REF_COST);
8148 size(4);
8149 format %{ "L $dst,$src\t # MoveF2I" %}
8150 opcode(L_ZOPC);
8151 ins_encode(z_form_rt_mem(dst, src));
8152 ins_pipe(pipe_class_dummy);
8153 %}
8154
8155 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
8156 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8157 match(Set dst (MoveI2F src));
8158 ins_cost(MEMORY_REF_COST);
8159 // TODO: s390 port size(FIXED_SIZE);
8160 format %{ "LE $dst,$src\t # MoveI2F" %}
8161 opcode(LE_ZOPC);
8162 ins_encode(z_form_rt_mem(dst, src));
8163 ins_pipe(pipe_class_dummy);
8164 %}
8165
8166 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8167 match(Set dst (MoveD2L src));
8168 ins_cost(MEMORY_REF_COST);
8169 size(6);
8170 format %{ "LG $src,$dst\t # MoveD2L" %}
8171 opcode(LG_ZOPC);
8172 ins_encode(z_form_rt_mem(dst, src));
8173 ins_pipe(pipe_class_dummy);
8174 %}
8175
8176 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8177 match(Set dst (MoveL2D src));
8178 ins_cost(MEMORY_REF_COST);
8179 size(4);
8180 format %{ "LD $dst,$src\t # MoveL2D" %}
8181 opcode(LD_ZOPC);
8182 ins_encode(z_form_rt_mem(dst, src));
8183 ins_pipe(pipe_class_dummy);
8184 %}
8185
8186 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8187 match(Set dst (MoveI2F src));
8188 ins_cost(MEMORY_REF_COST);
8189 size(4);
8190 format %{ "ST $src,$dst\t # MoveI2F" %}
8191 opcode(ST_ZOPC);
8192 ins_encode(z_form_rt_mem(src, dst));
8193 ins_pipe(pipe_class_dummy);
8194 %}
8195
8196 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8197 match(Set dst (MoveD2L src));
8198 effect(DEF dst, USE src);
8199 ins_cost(MEMORY_REF_COST);
8200 size(4);
8201 format %{ "STD $src,$dst\t # MoveD2L" %}
8202 opcode(STD_ZOPC);
8203 ins_encode(z_form_rt_mem(src,dst));
8204 ins_pipe(pipe_class_dummy);
8205 %}
8206
8207 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8208 match(Set dst (MoveL2D src));
8209 ins_cost(MEMORY_REF_COST);
8210 size(6);
8211 format %{ "STG $src,$dst\t # MoveL2D" %}
8212 opcode(STG_ZOPC);
8213 ins_encode(z_form_rt_mem(src,dst));
8214 ins_pipe(pipe_class_dummy);
8215 %}
8216
8217 instruct convL2F_reg(regF dst, iRegL src) %{
8218 match(Set dst (ConvL2F src));
8219 // CC remains unchanged.
8220 ins_cost(DEFAULT_COST);
8221 size(4);
8222 format %{ "CEGBR $dst,$src" %}
8223 opcode(CEGBR_ZOPC);
8224 ins_encode(z_rreform(dst, src));
8225 ins_pipe(pipe_class_dummy);
8226 %}
8227
8228 instruct convL2D_reg(regD dst, iRegL src) %{
8229 match(Set dst (ConvL2D src));
8230 // CC remains unchanged.
8231 ins_cost(DEFAULT_COST);
8232 size(4);
8233 format %{ "CDGBR $dst,$src" %}
8234 opcode(CDGBR_ZOPC);
8235 ins_encode(z_rreform(dst, src));
8236 ins_pipe(pipe_class_dummy);
8237 %}
8238
8239 instruct convL2I_reg(iRegI dst, iRegL src) %{
8240 match(Set dst (ConvL2I src));
8241 // TODO: s390 port size(VARIABLE_SIZE);
8242 format %{ "LR $dst,$src\t # long->int (if needed)" %}
8243 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
8244 ins_pipe(pipe_class_dummy);
8245 %}
8246
8247 // Register Shift Right Immediate
8248 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
8249 match(Set dst (ConvL2I (RShiftL src cnt)));
8250 effect(KILL cr);
8251 size(6);
8252 format %{ "SRAG $dst,$src,$cnt" %}
8253 opcode(SRAG_ZOPC);
8254 ins_encode(z_rsyform_const(dst, src, cnt));
8255 ins_pipe(pipe_class_dummy);
8256 %}
8257
8258 //----------TRAP based zero checks and range checks----------------------------
8259
8260 // SIGTRAP based implicit range checks in compiled code.
8261 // A range check in the ideal world has one of the following shapes:
8262 // - (If le (CmpU length index)), (IfTrue throw exception)
8263 // - (If lt (CmpU index length)), (IfFalse throw exception)
8264 //
8265 // Match range check 'If le (CmpU length index)'
8266 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
8267 match(If cmp (CmpU length index));
8268 effect(USE labl);
8269 predicate(TrapBasedRangeChecks &&
8270 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
8271 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
8272 Matcher::branches_to_uncommon_trap(_leaf));
8273 ins_cost(1);
8274 // TODO: s390 port size(FIXED_SIZE);
8275
8276 ins_is_TrapBasedCheckNode(true);
8277
8278 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
8279 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
8280 ins_pipe(pipe_class_trap);
8281 %}
8282
8283 // Match range check 'If lt (CmpU index length)'
8284 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
8285 match(If cmp (CmpU index length));
8286 effect(USE labl, KILL cr);
8287 predicate(TrapBasedRangeChecks &&
8288 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8289 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8290 Matcher::branches_to_uncommon_trap(_leaf));
8291 ins_cost(1);
8292 // TODO: s390 port size(FIXED_SIZE);
8293
8294 ins_is_TrapBasedCheckNode(true);
8295
8296 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
8297 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
8298 ins_pipe(pipe_class_trap);
8299 %}
8300
8301 // Match range check 'If lt (CmpU index length)'
8302 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
8303 match(If cmp (CmpU index length));
8304 effect(USE labl);
8305 predicate(TrapBasedRangeChecks &&
8306 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8307 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8308 Matcher::branches_to_uncommon_trap(_leaf));
8309 ins_cost(1);
8310 // TODO: s390 port size(FIXED_SIZE);
8311
8312 ins_is_TrapBasedCheckNode(true);
8313
8314 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
8315 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
8316 ins_pipe(pipe_class_trap);
8317 %}
8318
8319 // Implicit zero checks (more implicit null checks).
8320 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
8321 match(If cmp (CmpP value zero));
8322 effect(USE labl);
8323 predicate(TrapBasedNullChecks &&
8324 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8325 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8326 Matcher::branches_to_uncommon_trap(_leaf));
8327 size(6);
8328
8329 ins_is_TrapBasedCheckNode(true);
8330
8331 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
8332 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
8333 ins_pipe(pipe_class_trap);
8334 %}
8335
8336 // Implicit zero checks (more implicit null checks).
8337 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
8338 match(If cmp (CmpN value zero));
8339 effect(USE labl);
8340 predicate(TrapBasedNullChecks &&
8341 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8342 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8343 Matcher::branches_to_uncommon_trap(_leaf));
8344 size(6);
8345
8346 ins_is_TrapBasedCheckNode(true);
8347
8348 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
8349 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
8350 ins_pipe(pipe_class_trap);
8351 %}
8352
8353 //----------Compare instructions-----------------------------------------------
8354
8355 // INT signed
8356
8357 // Compare Integers
8358 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8359 match(Set cr (CmpI op1 op2));
8360 size(2);
8361 format %{ "CR $op1,$op2" %}
8362 opcode(CR_ZOPC);
8363 ins_encode(z_rrform(op1, op2));
8364 ins_pipe(pipe_class_dummy);
8365 %}
8366
8367 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
8368 match(Set cr (CmpI op1 op2));
8369 size(6);
8370 format %{ "CFI $op1,$op2" %}
8371 opcode(CFI_ZOPC);
8372 ins_encode(z_rilform_signed(op1, op2));
8373 ins_pipe(pipe_class_dummy);
8374 %}
8375
8376 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
8377 match(Set cr (CmpI op1 op2));
8378 size(4);
8379 format %{ "CHI $op1,$op2" %}
8380 opcode(CHI_ZOPC);
8381 ins_encode(z_riform_signed(op1, op2));
8382 ins_pipe(pipe_class_dummy);
8383 %}
8384
8385 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8386 match(Set cr (CmpI op1 zero));
8387 ins_cost(DEFAULT_COST_LOW);
8388 size(2);
8389 format %{ "LTR $op1,$op1" %}
8390 opcode(LTR_ZOPC);
8391 ins_encode(z_rrform(op1, op1));
8392 ins_pipe(pipe_class_dummy);
8393 %}
8394
8395 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8396 match(Set cr (CmpI op1 (LoadI op2)));
8397 ins_cost(MEMORY_REF_COST);
8398 // TODO: s390 port size(VARIABLE_SIZE);
8399 format %{ "C(Y) $op1, $op2\t # int" %}
8400 opcode(CY_ZOPC, C_ZOPC);
8401 ins_encode(z_form_rt_mem_opt(op1, op2));
8402 ins_pipe(pipe_class_dummy);
8403 %}
8404
8405 // INT unsigned
8406
8407 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8408 match(Set cr (CmpU op1 op2));
8409 size(2);
8410 format %{ "CLR $op1,$op2\t # unsigned" %}
8411 opcode(CLR_ZOPC);
8412 ins_encode(z_rrform(op1, op2));
8413 ins_pipe(pipe_class_dummy);
8414 %}
8415
8416 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8417 match(Set cr (CmpU op1 op2));
8418 size(6);
8419 format %{ "CLFI $op1,$op2\t # unsigned" %}
8420 opcode(CLFI_ZOPC);
8421 ins_encode(z_rilform_unsigned(op1, op2));
8422 ins_pipe(pipe_class_dummy);
8423 %}
8424
8425 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8426 match(Set cr (CmpU op1 (LoadI op2)));
8427 ins_cost(MEMORY_REF_COST);
8428 // TODO: s390 port size(VARIABLE_SIZE);
8429 format %{ "CL(Y) $op1, $op2\t # unsigned" %}
8430 opcode(CLY_ZOPC, CL_ZOPC);
8431 ins_encode(z_form_rt_mem_opt(op1, op2));
8432 ins_pipe(pipe_class_dummy);
8433 %}
8434
8435 // LONG signed
8436
8437 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8438 match(Set cr (CmpL op1 op2));
8439 size(4);
8440 format %{ "CGR $op1,$op2\t # long" %}
8441 opcode(CGR_ZOPC);
8442 ins_encode(z_rreform(op1, op2));
8443 ins_pipe(pipe_class_dummy);
8444 %}
8445
8446 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
8447 match(Set cr (CmpL op1 (ConvI2L op2)));
8448 size(4);
8449 format %{ "CGFR $op1,$op2\t # long/int" %}
8450 opcode(CGFR_ZOPC);
8451 ins_encode(z_rreform(op1, op2));
8452 ins_pipe(pipe_class_dummy);
8453 %}
8454
8455 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
8456 match(Set cr (CmpL op1 con));
8457 size(6);
8458 format %{ "CGFI $op1,$con" %}
8459 opcode(CGFI_ZOPC);
8460 ins_encode(z_rilform_signed(op1, con));
8461 ins_pipe(pipe_class_dummy);
8462 %}
8463
8464 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
8465 match(Set cr (CmpL op1 con));
8466 size(4);
8467 format %{ "CGHI $op1,$con" %}
8468 opcode(CGHI_ZOPC);
8469 ins_encode(z_riform_signed(op1, con));
8470 ins_pipe(pipe_class_dummy);
8471 %}
8472
8473 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
8474 match(Set cr (CmpL op1 con));
8475 ins_cost(DEFAULT_COST_LOW);
8476 size(4);
8477 format %{ "LTGR $op1,$op1" %}
8478 opcode(LTGR_ZOPC);
8479 ins_encode(z_rreform(op1, op1));
8480 ins_pipe(pipe_class_dummy);
8481 %}
8482
8483 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
8484 match(Set cr (CmpL (ConvI2L op1) con));
8485 ins_cost(DEFAULT_COST_LOW);
8486 size(4);
8487 format %{ "LTGFR $op1,$op1" %}
8488 opcode(LTGFR_ZOPC);
8489 ins_encode(z_rreform(op1, op1));
8490 ins_pipe(pipe_class_dummy);
8491 %}
8492
8493 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
8494 match(Set cr (CmpL dst (LoadL src)));
8495 ins_cost(MEMORY_REF_COST);
8496 size(Z_DISP3_SIZE);
8497 format %{ "CG $dst, $src\t # long" %}
8498 opcode(CG_ZOPC, CG_ZOPC);
8499 ins_encode(z_form_rt_mem_opt(dst, src));
8500 ins_pipe(pipe_class_dummy);
8501 %}
8502
8503 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
8504 match(Set cr (CmpL dst (ConvI2L (LoadI src))));
8505 ins_cost(MEMORY_REF_COST);
8506 size(Z_DISP3_SIZE);
8507 format %{ "CGF $dst, $src\t # long/int" %}
8508 opcode(CGF_ZOPC, CGF_ZOPC);
8509 ins_encode(z_form_rt_mem_opt(dst, src));
8510 ins_pipe(pipe_class_dummy);
8511 %}
8512
8513 // LONG unsigned
8514 // Added CmpUL for LoopPredicate.
8515 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8516 match(Set cr (CmpUL op1 op2));
8517 size(4);
8518 format %{ "CLGR $op1,$op2\t # long" %}
8519 opcode(CLGR_ZOPC);
8520 ins_encode(z_rreform(op1, op2));
8521 ins_pipe(pipe_class_dummy);
8522 %}
8523
8524 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{
8525 match(Set cr (CmpUL op1 con));
8526 size(6);
8527 format %{ "CLGFI $op1,$con" %}
8528 opcode(CLGFI_ZOPC);
8529 ins_encode(z_rilform_unsigned(op1, con));
8530 ins_pipe(pipe_class_dummy);
8531 %}
8532
8533 // PTR unsigned
8534
8535 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
8536 match(Set cr (CmpP op1 op2));
8537 size(4);
8538 format %{ "CLGR $op1,$op2\t # ptr" %}
8539 opcode(CLGR_ZOPC);
8540 ins_encode(z_rreform(op1, op2));
8541 ins_pipe(pipe_class_dummy);
8542 %}
8543
8544 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
8545 match(Set cr (CmpP op1 op2));
8546 ins_cost(DEFAULT_COST_LOW);
8547 size(4);
8548 format %{ "LTGR $op1, $op1\t # ptr" %}
8549 opcode(LTGR_ZOPC);
8550 ins_encode(z_rreform(op1, op1));
8551 ins_pipe(pipe_class_dummy);
8552 %}
8553
8554 // Don't use LTGFR which performs sign extend.
8555 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
8556 match(Set cr (CmpP (DecodeN op1) op2));
8557 predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0);
8558 ins_cost(DEFAULT_COST_LOW);
8559 size(2);
8560 format %{ "LTR $op1, $op1\t # ptr" %}
8561 opcode(LTR_ZOPC);
8562 ins_encode(z_rrform(op1, op1));
8563 ins_pipe(pipe_class_dummy);
8564 %}
8565
8566 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
8567 match(Set cr (CmpP dst (LoadP src)));
8568 ins_cost(MEMORY_REF_COST);
8569 size(Z_DISP3_SIZE);
8570 format %{ "CLG $dst, $src\t # ptr" %}
8571 opcode(CLG_ZOPC, CLG_ZOPC);
8572 ins_encode(z_form_rt_mem_opt(dst, src));
8573 ins_pipe(pipe_class_dummy);
8574 %}
8575
8576 //----------Max and Min--------------------------------------------------------
8577
8578 // Max Register with Register
8579 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8580 match(Set dst (MinI src1 src2));
8581 effect(KILL cr);
8582 predicate(VM_Version::has_LoadStoreConditional());
8583 ins_cost(3 * DEFAULT_COST);
8584 // TODO: s390 port size(VARIABLE_SIZE);
8585 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
8586 ins_encode %{
8587 Register Rdst = $dst$$Register;
8588 Register Rsrc1 = $src1$$Register;
8589 Register Rsrc2 = $src2$$Register;
8590
8591 if (Rsrc1 == Rsrc2) {
8592 if (Rdst != Rsrc1) {
8593 __ z_lgfr(Rdst, Rsrc1);
8594 }
8595 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8596 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow.
8597 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8598 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8599 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow.
8600 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
8601 } else {
8602 // Rdst is disjoint from operands, move in either case.
8603 __ z_cr(Rsrc1, Rsrc2);
8604 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8605 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8606 }
8607 %}
8608 ins_pipe(pipe_class_dummy);
8609 %}
8610
8611 // Min Register with Register.
8612 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8613 match(Set dst (MinI src1 src2));
8614 effect(KILL cr);
8615 predicate(VM_Version::has_CompareBranch());
8616 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8617 // TODO: s390 port size(VARIABLE_SIZE);
8618 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
8619 ins_encode %{
8620 Register Rdst = $dst$$Register;
8621 Register Rsrc1 = $src1$$Register;
8622 Register Rsrc2 = $src2$$Register;
8623 Label done;
8624
8625 if (Rsrc1 == Rsrc2) {
8626 if (Rdst != Rsrc1) {
8627 __ z_lgfr(Rdst, Rsrc1);
8628 }
8629 } else if (Rdst == Rsrc1) {
8630 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8631 __ z_lgfr(Rdst, Rsrc2);
8632 } else if (Rdst == Rsrc2) {
8633 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
8634 __ z_lgfr(Rdst, Rsrc1);
8635 } else {
8636 __ z_lgfr(Rdst, Rsrc1);
8637 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8638 __ z_lgfr(Rdst, Rsrc2);
8639 }
8640 __ bind(done);
8641 %}
8642 ins_pipe(pipe_class_dummy);
8643 %}
8644
8645 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8646 match(Set dst (MinI src1 src2));
8647 effect(KILL cr);
8648 predicate(!VM_Version::has_CompareBranch());
8649 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8650 // TODO: s390 port size(VARIABLE_SIZE);
8651 format %{ "MinI $dst $src1,$src2\t MinI" %}
8652 ins_encode %{
8653 Register Rdst = $dst$$Register;
8654 Register Rsrc1 = $src1$$Register;
8655 Register Rsrc2 = $src2$$Register;
8656 Label done;
8657
8658 if (Rsrc1 == Rsrc2) {
8659 if (Rdst != Rsrc1) {
8660 __ z_lgfr(Rdst, Rsrc1);
8661 }
8662 } else if (Rdst == Rsrc1) {
8663 __ z_cr(Rsrc1, Rsrc2);
8664 __ z_brl(done);
8665 __ z_lgfr(Rdst, Rsrc2);
8666 } else if (Rdst == Rsrc2) {
8667 __ z_cr(Rsrc2, Rsrc1);
8668 __ z_brl(done);
8669 __ z_lgfr(Rdst, Rsrc1);
8670 } else {
8671 __ z_lgfr(Rdst, Rsrc1);
8672 __ z_cr(Rsrc1, Rsrc2);
8673 __ z_brl(done);
8674 __ z_lgfr(Rdst, Rsrc2);
8675 }
8676 __ bind(done);
8677 %}
8678 ins_pipe(pipe_class_dummy);
8679 %}
8680
8681 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8682 match(Set dst (MinI src1 src2));
8683 effect(KILL cr);
8684 predicate(VM_Version::has_LoadStoreConditional());
8685 ins_cost(3 * DEFAULT_COST);
8686 // TODO: s390 port size(VARIABLE_SIZE);
8687 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
8688 ins_encode %{
8689 Register Rdst = $dst$$Register;
8690 Register Rsrc1 = $src1$$Register;
8691 int Isrc2 = $src2$$constant;
8692
8693 if (Rdst == Rsrc1) {
8694 __ load_const_optimized(Z_R0_scratch, Isrc2);
8695 __ z_cfi(Rsrc1, Isrc2);
8696 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8697 } else {
8698 __ load_const_optimized(Rdst, Isrc2);
8699 __ z_cfi(Rsrc1, Isrc2);
8700 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8701 }
8702 %}
8703 ins_pipe(pipe_class_dummy);
8704 %}
8705
8706 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8707 match(Set dst (MinI src1 src2));
8708 effect(KILL cr);
8709 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8710 // TODO: s390 port size(VARIABLE_SIZE);
8711 format %{ "MinI $dst $src1,$src2\t MinI const32" %}
8712 ins_encode %{
8713 Label done;
8714 if ($dst$$Register != $src1$$Register) {
8715 __ z_lgfr($dst$$Register, $src1$$Register);
8716 }
8717 __ z_cfi($src1$$Register, $src2$$constant);
8718 __ z_brl(done);
8719 __ z_lgfi($dst$$Register, $src2$$constant);
8720 __ bind(done);
8721 %}
8722 ins_pipe(pipe_class_dummy);
8723 %}
8724
8725 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8726 match(Set dst (MinI src1 src2));
8727 effect(KILL cr);
8728 predicate(VM_Version::has_LoadStoreConditional());
8729 ins_cost(3 * DEFAULT_COST);
8730 // TODO: s390 port size(VARIABLE_SIZE);
8731 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
8732 ins_encode %{
8733 Register Rdst = $dst$$Register;
8734 Register Rsrc1 = $src1$$Register;
8735 int Isrc2 = $src2$$constant;
8736
8737 if (Rdst == Rsrc1) {
8738 __ load_const_optimized(Z_R0_scratch, Isrc2);
8739 __ z_chi(Rsrc1, Isrc2);
8740 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8741 } else {
8742 __ load_const_optimized(Rdst, Isrc2);
8743 __ z_chi(Rsrc1, Isrc2);
8744 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8745 }
8746 %}
8747 ins_pipe(pipe_class_dummy);
8748 %}
8749
8750 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8751 match(Set dst (MinI src1 src2));
8752 effect(KILL cr);
8753 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8754 // TODO: s390 port size(VARIABLE_SIZE);
8755 format %{ "MinI $dst $src1,$src2\t MinI const16" %}
8756 ins_encode %{
8757 Label done;
8758 if ($dst$$Register != $src1$$Register) {
8759 __ z_lgfr($dst$$Register, $src1$$Register);
8760 }
8761 __ z_chi($src1$$Register, $src2$$constant);
8762 __ z_brl(done);
8763 __ z_lghi($dst$$Register, $src2$$constant);
8764 __ bind(done);
8765 %}
8766 ins_pipe(pipe_class_dummy);
8767 %}
8768
8769 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8770 match(Set dst (MinI src1 src2));
8771 effect(KILL cr);
8772 predicate(VM_Version::has_CompareBranch());
8773 ins_cost(DEFAULT_COST + BRANCH_COST);
8774 // TODO: s390 port size(VARIABLE_SIZE);
8775 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
8776 ins_encode %{
8777 Label done;
8778 if ($dst$$Register != $src1$$Register) {
8779 __ z_lgfr($dst$$Register, $src1$$Register);
8780 }
8781 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
8782 __ z_lghi($dst$$Register, $src2$$constant);
8783 __ bind(done);
8784 %}
8785 ins_pipe(pipe_class_dummy);
8786 %}
8787
8788 // Max Register with Register
8789 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8790 match(Set dst (MaxI src1 src2));
8791 effect(KILL cr);
8792 predicate(VM_Version::has_LoadStoreConditional());
8793 ins_cost(3 * DEFAULT_COST);
8794 // TODO: s390 port size(VARIABLE_SIZE);
8795 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
8796 ins_encode %{
8797 Register Rdst = $dst$$Register;
8798 Register Rsrc1 = $src1$$Register;
8799 Register Rsrc2 = $src2$$Register;
8800
8801 if (Rsrc1 == Rsrc2) {
8802 if (Rdst != Rsrc1) {
8803 __ z_lgfr(Rdst, Rsrc1);
8804 }
8805 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8806 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh.
8807 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8808 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8809 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh.
8810 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
8811 } else { // Rdst is disjoint from operands, move in either case.
8812 __ z_cr(Rsrc1, Rsrc2);
8813 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8814 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8815 }
8816 %}
8817 ins_pipe(pipe_class_dummy);
8818 %}
8819
8820 // Max Register with Register
8821 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8822 match(Set dst (MaxI src1 src2));
8823 effect(KILL cr);
8824 predicate(VM_Version::has_CompareBranch());
8825 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8826 // TODO: s390 port size(VARIABLE_SIZE);
8827 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
8828 ins_encode %{
8829 Register Rdst = $dst$$Register;
8830 Register Rsrc1 = $src1$$Register;
8831 Register Rsrc2 = $src2$$Register;
8832 Label done;
8833
8834 if (Rsrc1 == Rsrc2) {
8835 if (Rdst != Rsrc1) {
8836 __ z_lgfr(Rdst, Rsrc1);
8837 }
8838 } else if (Rdst == Rsrc1) {
8839 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
8840 __ z_lgfr(Rdst, Rsrc2);
8841 } else if (Rdst == Rsrc2) {
8842 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
8843 __ z_lgfr(Rdst, Rsrc1);
8844 } else {
8845 __ z_lgfr(Rdst, Rsrc1);
8846 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
8847 __ z_lgfr(Rdst, Rsrc2);
8848 }
8849 __ bind(done);
8850 %}
8851 ins_pipe(pipe_class_dummy);
8852 %}
8853
8854 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8855 match(Set dst (MaxI src1 src2));
8856 effect(KILL cr);
8857 predicate(!VM_Version::has_CompareBranch());
8858 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8859 // TODO: s390 port size(VARIABLE_SIZE);
8860 format %{ "MaxI $dst $src1,$src2\t MaxI" %}
8861 ins_encode %{
8862 Register Rdst = $dst$$Register;
8863 Register Rsrc1 = $src1$$Register;
8864 Register Rsrc2 = $src2$$Register;
8865 Label done;
8866
8867 if (Rsrc1 == Rsrc2) {
8868 if (Rdst != Rsrc1) {
8869 __ z_lgfr(Rdst, Rsrc1);
8870 }
8871 } else if (Rdst == Rsrc1) {
8872 __ z_cr(Rsrc1, Rsrc2);
8873 __ z_brh(done);
8874 __ z_lgfr(Rdst, Rsrc2);
8875 } else if (Rdst == Rsrc2) {
8876 __ z_cr(Rsrc2, Rsrc1);
8877 __ z_brh(done);
8878 __ z_lgfr(Rdst, Rsrc1);
8879 } else {
8880 __ z_lgfr(Rdst, Rsrc1);
8881 __ z_cr(Rsrc1, Rsrc2);
8882 __ z_brh(done);
8883 __ z_lgfr(Rdst, Rsrc2);
8884 }
8885
8886 __ bind(done);
8887 %}
8888
8889 ins_pipe(pipe_class_dummy);
8890 %}
8891
8892 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8893 match(Set dst (MaxI src1 src2));
8894 effect(KILL cr);
8895 predicate(VM_Version::has_LoadStoreConditional());
8896 ins_cost(3 * DEFAULT_COST);
8897 // TODO: s390 port size(VARIABLE_SIZE);
8898 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
8899 ins_encode %{
8900 Register Rdst = $dst$$Register;
8901 Register Rsrc1 = $src1$$Register;
8902 int Isrc2 = $src2$$constant;
8903
8904 if (Rdst == Rsrc1) {
8905 __ load_const_optimized(Z_R0_scratch, Isrc2);
8906 __ z_cfi(Rsrc1, Isrc2);
8907 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
8908 } else {
8909 __ load_const_optimized(Rdst, Isrc2);
8910 __ z_cfi(Rsrc1, Isrc2);
8911 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8912 }
8913 %}
8914 ins_pipe(pipe_class_dummy);
8915 %}
8916
8917 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8918 match(Set dst (MaxI src1 src2));
8919 effect(KILL cr);
8920 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8921 // TODO: s390 port size(VARIABLE_SIZE);
8922 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
8923 ins_encode %{
8924 Label done;
8925 if ($dst$$Register != $src1$$Register) {
8926 __ z_lgfr($dst$$Register, $src1$$Register);
8927 }
8928 __ z_cfi($src1$$Register, $src2$$constant);
8929 __ z_brh(done);
8930 __ z_lgfi($dst$$Register, $src2$$constant);
8931 __ bind(done);
8932 %}
8933 ins_pipe(pipe_class_dummy);
8934 %}
8935
8936 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8937 match(Set dst (MaxI src1 src2));
8938 effect(KILL cr);
8939 predicate(VM_Version::has_LoadStoreConditional());
8940 ins_cost(3 * DEFAULT_COST);
8941 // TODO: s390 port size(VARIABLE_SIZE);
8942 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
8943 ins_encode %{
8944 Register Rdst = $dst$$Register;
8945 Register Rsrc1 = $src1$$Register;
8946 int Isrc2 = $src2$$constant;
8947 if (Rdst == Rsrc1) {
8948 __ load_const_optimized(Z_R0_scratch, Isrc2);
8949 __ z_chi(Rsrc1, Isrc2);
8950 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
8951 } else {
8952 __ load_const_optimized(Rdst, Isrc2);
8953 __ z_chi(Rsrc1, Isrc2);
8954 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8955 }
8956 %}
8957 ins_pipe(pipe_class_dummy);
8958 %}
8959
8960 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8961 match(Set dst (MaxI src1 src2));
8962 effect(KILL cr);
8963 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8964 // TODO: s390 port size(VARIABLE_SIZE);
8965 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
8966 ins_encode %{
8967 Label done;
8968 if ($dst$$Register != $src1$$Register) {
8969 __ z_lgfr($dst$$Register, $src1$$Register);
8970 }
8971 __ z_chi($src1$$Register, $src2$$constant);
8972 __ z_brh(done);
8973 __ z_lghi($dst$$Register, $src2$$constant);
8974 __ bind(done);
8975 %}
8976 ins_pipe(pipe_class_dummy);
8977 %}
8978
8979 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8980 match(Set dst (MaxI src1 src2));
8981 effect(KILL cr);
8982 predicate(VM_Version::has_CompareBranch());
8983 ins_cost(DEFAULT_COST + BRANCH_COST);
8984 // TODO: s390 port size(VARIABLE_SIZE);
8985 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
8986 ins_encode %{
8987 Label done;
8988 if ($dst$$Register != $src1$$Register) {
8989 __ z_lgfr($dst$$Register, $src1$$Register);
8990 }
8991 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
8992 __ z_lghi($dst$$Register, $src2$$constant);
8993 __ bind(done);
8994 %}
8995 ins_pipe(pipe_class_dummy);
8996 %}
8997
8998 //----------Abs---------------------------------------------------------------
8999
9000 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
9001 match(Set dst (AbsI src));
9002 effect(KILL cr);
9003 ins_cost(DEFAULT_COST_LOW);
9004 // TODO: s390 port size(FIXED_SIZE);
9005 format %{ "LPR $dst, $src" %}
9006 opcode(LPR_ZOPC);
9007 ins_encode(z_rrform(dst, src));
9008 ins_pipe(pipe_class_dummy);
9009 %}
9010
9011 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
9012 match(Set dst (SubI zero (AbsI src)));
9013 effect(KILL cr);
9014 ins_cost(DEFAULT_COST_LOW);
9015 // TODO: s390 port size(FIXED_SIZE);
9016 format %{ "LNR $dst, $src" %}
9017 opcode(LNR_ZOPC);
9018 ins_encode(z_rrform(dst, src));
9019 ins_pipe(pipe_class_dummy);
9020 %}
9021
9022 //----------Float Compares----------------------------------------------------
9023
9024 // Compare floating, generate condition code.
9025 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
9026 match(Set cr (CmpF src1 src2));
9027 ins_cost(ALU_REG_COST);
9028 size(4);
9029 format %{ "FCMPcc $src1,$src2\t # float" %}
9030 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
9031 ins_pipe(pipe_class_dummy);
9032 %}
9033
9034 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
9035 match(Set cr (CmpD src1 src2));
9036 ins_cost(ALU_REG_COST);
9037 size(4);
9038 format %{ "FCMPcc $src1,$src2 \t # double" %}
9039 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
9040 ins_pipe(pipe_class_dummy);
9041 %}
9042
9043 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
9044 match(Set cr (CmpF src1 (LoadF src2)));
9045 ins_cost(ALU_MEMORY_COST);
9046 size(6);
9047 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
9048 opcode(CEB_ZOPC);
9049 ins_encode(z_form_rt_memFP(src1, src2));
9050 ins_pipe(pipe_class_dummy);
9051 %}
9052
9053 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
9054 match(Set cr (CmpD src1 (LoadD src2)));
9055 ins_cost(ALU_MEMORY_COST);
9056 size(6);
9057 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
9058 opcode(CDB_ZOPC);
9059 ins_encode(z_form_rt_memFP(src1, src2));
9060 ins_pipe(pipe_class_dummy);
9061 %}
9062
9063 // Compare floating, generate condition code
9064 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
9065 match(Set cr (CmpF src1 src2));
9066 ins_cost(DEFAULT_COST);
9067 size(4);
9068 format %{ "LTEBR $src1,$src1\t # float" %}
9069 opcode(LTEBR_ZOPC);
9070 ins_encode(z_rreform(src1, src1));
9071 ins_pipe(pipe_class_dummy);
9072 %}
9073
9074 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
9075 match(Set cr (CmpD src1 src2));
9076 ins_cost(DEFAULT_COST);
9077 size(4);
9078 format %{ "LTDBR $src1,$src1 \t # double" %}
9079 opcode(LTDBR_ZOPC);
9080 ins_encode(z_rreform(src1, src1));
9081 ins_pipe(pipe_class_dummy);
9082 %}
9083
9084 // Compare floating, generate -1,0,1
9085 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
9086 match(Set dst (CmpF3 src1 src2));
9087 effect(KILL cr);
9088 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9089 size(24);
9090 format %{ "CmpF3 $dst,$src1,$src2" %}
9091 ins_encode %{
9092 // compare registers
9093 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
9094 // Convert condition code into -1,0,1, where
9095 // -1 means unordered or less
9096 // 0 means equal
9097 // 1 means greater.
9098 if (VM_Version::has_LoadStoreConditional()) {
9099 Register one = Z_R0_scratch;
9100 Register minus_one = Z_R1_scratch;
9101 __ z_lghi(minus_one, -1);
9102 __ z_lghi(one, 1);
9103 __ z_lghi( $dst$$Register, 0);
9104 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9105 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9106 } else {
9107 Label done;
9108 __ clear_reg($dst$$Register, true, false);
9109 __ z_bre(done);
9110 __ z_lhi($dst$$Register, 1);
9111 __ z_brh(done);
9112 __ z_lhi($dst$$Register, -1);
9113 __ bind(done);
9114 }
9115 %}
9116 ins_pipe(pipe_class_dummy);
9117 %}
9118
9119 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
9120 match(Set dst (CmpD3 src1 src2));
9121 effect(KILL cr);
9122 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9123 size(24);
9124 format %{ "CmpD3 $dst,$src1,$src2" %}
9125 ins_encode %{
9126 // compare registers
9127 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
9128 // Convert condition code into -1,0,1, where
9129 // -1 means unordered or less
9130 // 0 means equal
9131 // 1 means greater.
9132 if (VM_Version::has_LoadStoreConditional()) {
9133 Register one = Z_R0_scratch;
9134 Register minus_one = Z_R1_scratch;
9135 __ z_lghi(minus_one, -1);
9136 __ z_lghi(one, 1);
9137 __ z_lghi( $dst$$Register, 0);
9138 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9139 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9140 } else {
9141 Label done;
9142 // indicate unused result
9143 (void) __ clear_reg($dst$$Register, true, false);
9144 __ z_bre(done);
9145 __ z_lhi($dst$$Register, 1);
9146 __ z_brh(done);
9147 __ z_lhi($dst$$Register, -1);
9148 __ bind(done);
9149 }
9150 %}
9151 ins_pipe(pipe_class_dummy);
9152 %}
9153
9154 //----------Branches---------------------------------------------------------
9155 // Jump
9156
9157 // Direct Branch.
9158 instruct branch(label labl) %{
9159 match(Goto);
9160 effect(USE labl);
9161 ins_cost(BRANCH_COST);
9162 size(4);
9163 format %{ "BRU $labl" %}
9164 ins_encode(z_enc_bru(labl));
9165 ins_pipe(pipe_class_dummy);
9166 // If set to 1 this indicates that the current instruction is a
9167 // short variant of a long branch. This avoids using this
9168 // instruction in first-pass matching. It will then only be used in
9169 // the `Shorten_branches' pass.
9170 ins_short_branch(1);
9171 %}
9172
9173 // Direct Branch.
9174 instruct branchFar(label labl) %{
9175 match(Goto);
9176 effect(USE labl);
9177 ins_cost(BRANCH_COST);
9178 size(6);
9179 format %{ "BRUL $labl" %}
9180 ins_encode(z_enc_brul(labl));
9181 ins_pipe(pipe_class_dummy);
9182 // This is not a short variant of a branch, but the long variant.
9183 ins_short_branch(0);
9184 %}
9185
9186 // Conditional Near Branch
9187 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
9188 // Same match rule as `branchConFar'.
9189 match(If cmp cr);
9190 effect(USE lbl);
9191 ins_cost(BRANCH_COST);
9192 size(4);
9193 format %{ "branch_con_short,$cmp $lbl" %}
9194 ins_encode(z_enc_branch_con_short(cmp, lbl));
9195 ins_pipe(pipe_class_dummy);
9196 // If set to 1 this indicates that the current instruction is a
9197 // short variant of a long branch. This avoids using this
9198 // instruction in first-pass matching. It will then only be used in
9199 // the `Shorten_branches' pass.
9200 ins_short_branch(1);
9201 %}
9202
9203 // This is for cases when the z/Architecture conditional branch instruction
9204 // does not reach far enough. So we emit a far branch here, which is
9205 // more expensive.
9206 //
9207 // Conditional Far Branch
9208 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
9209 // Same match rule as `branchCon'.
9210 match(If cmp cr);
9211 effect(USE cr, USE lbl);
9212 // Make more expensive to prefer compare_and_branch over separate instructions.
9213 ins_cost(2 * BRANCH_COST);
9214 size(6);
9215 format %{ "branch_con_far,$cmp $lbl" %}
9216 ins_encode(z_enc_branch_con_far(cmp, lbl));
9217 ins_pipe(pipe_class_dummy);
9218 // This is not a short variant of a branch, but the long variant..
9219 ins_short_branch(0);
9220 %}
9221
9222 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
9223 match(CountedLoopEnd cmp cr);
9224 effect(USE labl);
9225 ins_cost(BRANCH_COST);
9226 size(4);
9227 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %}
9228 ins_encode(z_enc_branch_con_short(cmp, labl));
9229 ins_pipe(pipe_class_dummy);
9230 // If set to 1 this indicates that the current instruction is a
9231 // short variant of a long branch. This avoids using this
9232 // instruction in first-pass matching. It will then only be used in
9233 // the `Shorten_branches' pass.
9234 ins_short_branch(1);
9235 %}
9236
9237 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
9238 match(CountedLoopEnd cmp cr);
9239 effect(USE labl);
9240 ins_cost(BRANCH_COST);
9241 size(6);
9242 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %}
9243 ins_encode(z_enc_branch_con_far(cmp, labl));
9244 ins_pipe(pipe_class_dummy);
9245 // This is not a short variant of a branch, but the long variant.
9246 ins_short_branch(0);
9247 %}
9248
9249 //----------Compare and Branch (short distance)------------------------------
9250
9251 // INT REG operands for loop counter processing.
9252 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9253 match(CountedLoopEnd boolnode (CmpI src1 src2));
9254 effect(USE labl, KILL cr);
9255 predicate(VM_Version::has_CompareBranch());
9256 ins_cost(BRANCH_COST);
9257 // TODO: s390 port size(FIXED_SIZE);
9258 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9259 opcode(CRJ_ZOPC);
9260 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9261 ins_pipe(pipe_class_dummy);
9262 ins_short_branch(1);
9263 %}
9264
9265 // INT REG operands.
9266 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9267 match(If boolnode (CmpI src1 src2));
9268 effect(USE labl, KILL cr);
9269 predicate(VM_Version::has_CompareBranch());
9270 ins_cost(BRANCH_COST);
9271 // TODO: s390 port size(FIXED_SIZE);
9272 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9273 opcode(CRJ_ZOPC);
9274 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9275 ins_pipe(pipe_class_dummy);
9276 ins_short_branch(1);
9277 %}
9278
9279 // Unsigned INT REG operands
9280 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9281 match(If boolnode (CmpU src1 src2));
9282 effect(USE labl, KILL cr);
9283 predicate(VM_Version::has_CompareBranch());
9284 ins_cost(BRANCH_COST);
9285 // TODO: s390 port size(FIXED_SIZE);
9286 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9287 opcode(CLRJ_ZOPC);
9288 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9289 ins_pipe(pipe_class_dummy);
9290 ins_short_branch(1);
9291 %}
9292
9293 // LONG REG operands
9294 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9295 match(If boolnode (CmpL src1 src2));
9296 effect(USE labl, KILL cr);
9297 predicate(VM_Version::has_CompareBranch());
9298 ins_cost(BRANCH_COST);
9299 // TODO: s390 port size(FIXED_SIZE);
9300 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9301 opcode(CGRJ_ZOPC);
9302 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9303 ins_pipe(pipe_class_dummy);
9304 ins_short_branch(1);
9305 %}
9306
9307 // PTR REG operands
9308
9309 // Separate rules for regular and narrow oops. ADLC can't recognize
9310 // rules with polymorphic operands to be sisters -> shorten_branches
9311 // will not shorten.
9312
9313 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9314 match(If boolnode (CmpP src1 src2));
9315 effect(USE labl, KILL cr);
9316 predicate(VM_Version::has_CompareBranch());
9317 ins_cost(BRANCH_COST);
9318 // TODO: s390 port size(FIXED_SIZE);
9319 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9320 opcode(CLGRJ_ZOPC);
9321 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9322 ins_pipe(pipe_class_dummy);
9323 ins_short_branch(1);
9324 %}
9325
9326 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9327 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9328 effect(USE labl, KILL cr);
9329 predicate(VM_Version::has_CompareBranch());
9330 ins_cost(BRANCH_COST);
9331 // TODO: s390 port size(FIXED_SIZE);
9332 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9333 opcode(CLGRJ_ZOPC);
9334 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9335 ins_pipe(pipe_class_dummy);
9336 ins_short_branch(1);
9337 %}
9338
9339 // INT REG/IMM operands for loop counter processing
9340 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9341 match(CountedLoopEnd boolnode (CmpI src1 src2));
9342 effect(USE labl, KILL cr);
9343 predicate(VM_Version::has_CompareBranch());
9344 ins_cost(BRANCH_COST);
9345 // TODO: s390 port size(FIXED_SIZE);
9346 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9347 opcode(CIJ_ZOPC);
9348 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9349 ins_pipe(pipe_class_dummy);
9350 ins_short_branch(1);
9351 %}
9352
9353 // INT REG/IMM operands
9354 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9355 match(If boolnode (CmpI src1 src2));
9356 effect(USE labl, KILL cr);
9357 predicate(VM_Version::has_CompareBranch());
9358 ins_cost(BRANCH_COST);
9359 // TODO: s390 port size(FIXED_SIZE);
9360 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9361 opcode(CIJ_ZOPC);
9362 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9363 ins_pipe(pipe_class_dummy);
9364 ins_short_branch(1);
9365 %}
9366
9367 // INT REG/IMM operands
9368 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9369 match(If boolnode (CmpU src1 src2));
9370 effect(USE labl, KILL cr);
9371 predicate(VM_Version::has_CompareBranch());
9372 ins_cost(BRANCH_COST);
9373 // TODO: s390 port size(FIXED_SIZE);
9374 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9375 opcode(CLIJ_ZOPC);
9376 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9377 ins_pipe(pipe_class_dummy);
9378 ins_short_branch(1);
9379 %}
9380
9381 // LONG REG/IMM operands
9382 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9383 match(If boolnode (CmpL src1 src2));
9384 effect(USE labl, KILL cr);
9385 predicate(VM_Version::has_CompareBranch());
9386 ins_cost(BRANCH_COST);
9387 // TODO: s390 port size(FIXED_SIZE);
9388 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9389 opcode(CGIJ_ZOPC);
9390 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9391 ins_pipe(pipe_class_dummy);
9392 ins_short_branch(1);
9393 %}
9394
9395 // PTR REG-imm operands
9396
9397 // Separate rules for regular and narrow oops. ADLC can't recognize
9398 // rules with polymorphic operands to be sisters -> shorten_branches
9399 // will not shorten.
9400
9401 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9402 match(If boolnode (CmpP src1 src2));
9403 effect(USE labl, KILL cr);
9404 predicate(VM_Version::has_CompareBranch());
9405 ins_cost(BRANCH_COST);
9406 // TODO: s390 port size(FIXED_SIZE);
9407 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9408 opcode(CLGIJ_ZOPC);
9409 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9410 ins_pipe(pipe_class_dummy);
9411 ins_short_branch(1);
9412 %}
9413
9414 // Compare against zero only, do not mix N and P oops (encode/decode required).
9415 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9416 match(If boolnode (CmpP (DecodeN src1) src2));
9417 effect(USE labl, KILL cr);
9418 predicate(VM_Version::has_CompareBranch());
9419 ins_cost(BRANCH_COST);
9420 // TODO: s390 port size(FIXED_SIZE);
9421 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9422 opcode(CLGIJ_ZOPC);
9423 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9424 ins_pipe(pipe_class_dummy);
9425 ins_short_branch(1);
9426 %}
9427
9428 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9429 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9430 effect(USE labl, KILL cr);
9431 predicate(VM_Version::has_CompareBranch());
9432 ins_cost(BRANCH_COST);
9433 // TODO: s390 port size(FIXED_SIZE);
9434 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9435 opcode(CLGIJ_ZOPC);
9436 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9437 ins_pipe(pipe_class_dummy);
9438 ins_short_branch(1);
9439 %}
9440
9441
9442 //----------Compare and Branch (far distance)------------------------------
9443
9444 // INT REG operands for loop counter processing
9445 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9446 match(CountedLoopEnd boolnode (CmpI src1 src2));
9447 effect(USE labl, KILL cr);
9448 predicate(VM_Version::has_CompareBranch());
9449 ins_cost(BRANCH_COST+DEFAULT_COST);
9450 // TODO: s390 port size(FIXED_SIZE);
9451 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9452 opcode(CR_ZOPC, BRCL_ZOPC);
9453 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9454 ins_pipe(pipe_class_dummy);
9455 ins_short_branch(0);
9456 %}
9457
9458 // INT REG operands
9459 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9460 match(If boolnode (CmpI src1 src2));
9461 effect(USE labl, KILL cr);
9462 predicate(VM_Version::has_CompareBranch());
9463 ins_cost(BRANCH_COST+DEFAULT_COST);
9464 // TODO: s390 port size(FIXED_SIZE);
9465 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9466 opcode(CR_ZOPC, BRCL_ZOPC);
9467 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9468 ins_pipe(pipe_class_dummy);
9469 ins_short_branch(0);
9470 %}
9471
9472 // INT REG operands
9473 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9474 match(If boolnode (CmpU src1 src2));
9475 effect(USE labl, KILL cr);
9476 predicate(VM_Version::has_CompareBranch());
9477 ins_cost(BRANCH_COST+DEFAULT_COST);
9478 // TODO: s390 port size(FIXED_SIZE);
9479 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9480 opcode(CLR_ZOPC, BRCL_ZOPC);
9481 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9482 ins_pipe(pipe_class_dummy);
9483 ins_short_branch(0);
9484 %}
9485
9486 // LONG REG operands
9487 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9488 match(If boolnode (CmpL src1 src2));
9489 effect(USE labl, KILL cr);
9490 predicate(VM_Version::has_CompareBranch());
9491 ins_cost(BRANCH_COST+DEFAULT_COST);
9492 // TODO: s390 port size(FIXED_SIZE);
9493 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9494 opcode(CGR_ZOPC, BRCL_ZOPC);
9495 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9496 ins_pipe(pipe_class_dummy);
9497 ins_short_branch(0);
9498 %}
9499
9500 // PTR REG operands
9501
9502 // Separate rules for regular and narrow oops. ADLC can't recognize
9503 // rules with polymorphic operands to be sisters -> shorten_branches
9504 // will not shorten.
9505
9506 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9507 match(If boolnode (CmpP src1 src2));
9508 effect(USE labl, KILL cr);
9509 predicate(VM_Version::has_CompareBranch());
9510 ins_cost(BRANCH_COST+DEFAULT_COST);
9511 // TODO: s390 port size(FIXED_SIZE);
9512 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9513 opcode(CLGR_ZOPC, BRCL_ZOPC);
9514 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9515 ins_pipe(pipe_class_dummy);
9516 ins_short_branch(0);
9517 %}
9518
9519 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9520 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9521 effect(USE labl, KILL cr);
9522 predicate(VM_Version::has_CompareBranch());
9523 ins_cost(BRANCH_COST+DEFAULT_COST);
9524 // TODO: s390 port size(FIXED_SIZE);
9525 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9526 opcode(CLGR_ZOPC, BRCL_ZOPC);
9527 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9528 ins_pipe(pipe_class_dummy);
9529 ins_short_branch(0);
9530 %}
9531
9532 // INT REG/IMM operands for loop counter processing
9533 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9534 match(CountedLoopEnd boolnode (CmpI src1 src2));
9535 effect(USE labl, KILL cr);
9536 predicate(VM_Version::has_CompareBranch());
9537 ins_cost(BRANCH_COST+DEFAULT_COST);
9538 // TODO: s390 port size(FIXED_SIZE);
9539 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9540 opcode(CHI_ZOPC, BRCL_ZOPC);
9541 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9542 ins_pipe(pipe_class_dummy);
9543 ins_short_branch(0);
9544 %}
9545
9546 // INT REG/IMM operands
9547 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9548 match(If boolnode (CmpI src1 src2));
9549 effect(USE labl, KILL cr);
9550 predicate(VM_Version::has_CompareBranch());
9551 ins_cost(BRANCH_COST+DEFAULT_COST);
9552 // TODO: s390 port size(FIXED_SIZE);
9553 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9554 opcode(CHI_ZOPC, BRCL_ZOPC);
9555 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9556 ins_pipe(pipe_class_dummy);
9557 ins_short_branch(0);
9558 %}
9559
9560 // INT REG/IMM operands
9561 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9562 match(If boolnode (CmpU src1 src2));
9563 effect(USE labl, KILL cr);
9564 predicate(VM_Version::has_CompareBranch());
9565 ins_cost(BRANCH_COST+DEFAULT_COST);
9566 // TODO: s390 port size(FIXED_SIZE);
9567 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9568 opcode(CLFI_ZOPC, BRCL_ZOPC);
9569 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9570 ins_pipe(pipe_class_dummy);
9571 ins_short_branch(0);
9572 %}
9573
9574 // LONG REG/IMM operands
9575 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9576 match(If boolnode (CmpL src1 src2));
9577 effect(USE labl, KILL cr);
9578 predicate(VM_Version::has_CompareBranch());
9579 ins_cost(BRANCH_COST+DEFAULT_COST);
9580 // TODO: s390 port size(FIXED_SIZE);
9581 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9582 opcode(CGHI_ZOPC, BRCL_ZOPC);
9583 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9584 ins_pipe(pipe_class_dummy);
9585 ins_short_branch(0);
9586 %}
9587
9588 // PTR REG-imm operands
9589
9590 // Separate rules for regular and narrow oops. ADLC can't recognize
9591 // rules with polymorphic operands to be sisters -> shorten_branches
9592 // will not shorten.
9593
9594 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9595 match(If boolnode (CmpP src1 src2));
9596 effect(USE labl, KILL cr);
9597 predicate(VM_Version::has_CompareBranch());
9598 ins_cost(BRANCH_COST+DEFAULT_COST);
9599 // TODO: s390 port size(FIXED_SIZE);
9600 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9601 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9602 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9603 ins_pipe(pipe_class_dummy);
9604 ins_short_branch(0);
9605 %}
9606
9607 // Compare against zero only, do not mix N and P oops (encode/decode required).
9608 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9609 match(If boolnode (CmpP (DecodeN src1) src2));
9610 effect(USE labl, KILL cr);
9611 predicate(VM_Version::has_CompareBranch());
9612 ins_cost(BRANCH_COST+DEFAULT_COST);
9613 // TODO: s390 port size(FIXED_SIZE);
9614 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9615 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9616 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9617 ins_pipe(pipe_class_dummy);
9618 ins_short_branch(0);
9619 %}
9620
9621 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9622 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9623 effect(USE labl, KILL cr);
9624 predicate(VM_Version::has_CompareBranch());
9625 ins_cost(BRANCH_COST+DEFAULT_COST);
9626 // TODO: s390 port size(FIXED_SIZE);
9627 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9628 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9629 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9630 ins_pipe(pipe_class_dummy);
9631 ins_short_branch(0);
9632 %}
9633
9634 // ============================================================================
9635 // Long Compare
9636
9637 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9638 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9639 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9640 // are collapsed internally in the ADLC's dfa-gen code. The match for
9641 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9642 // foo match ends up with the wrong leaf. One fix is to not match both
9643 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9644 // both forms beat the trinary form of long-compare and both are very useful
9645 // on platforms which have few registers.
9646
9647 // Manifest a CmpL3 result in an integer register. Very painful.
9648 // This is the test to avoid.
9649 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
9650 match(Set dst (CmpL3 src1 src2));
9651 effect(KILL cr);
9652 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9653 size(24);
9654 format %{ "CmpL3 $dst,$src1,$src2" %}
9655 ins_encode %{
9656 Label done;
9657 // compare registers
9658 __ z_cgr($src1$$Register, $src2$$Register);
9659 // Convert condition code into -1,0,1, where
9660 // -1 means less
9661 // 0 means equal
9662 // 1 means greater.
9663 if (VM_Version::has_LoadStoreConditional()) {
9664 Register one = Z_R0_scratch;
9665 Register minus_one = Z_R1_scratch;
9666 __ z_lghi(minus_one, -1);
9667 __ z_lghi(one, 1);
9668 __ z_lghi( $dst$$Register, 0);
9669 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9670 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
9671 } else {
9672 __ clear_reg($dst$$Register, true, false);
9673 __ z_bre(done);
9674 __ z_lhi($dst$$Register, 1);
9675 __ z_brh(done);
9676 __ z_lhi($dst$$Register, -1);
9677 }
9678 __ bind(done);
9679 %}
9680 ins_pipe(pipe_class_dummy);
9681 %}
9682
9683 // ============================================================================
9684 // Safepoint Instruction
9685
9686 instruct safePoint() %{
9687 match(SafePoint);
9688 predicate(false);
9689 // TODO: s390 port size(FIXED_SIZE);
9690 format %{ "UNIMPLEMENTED Safepoint_ " %}
9691 ins_encode(enc_unimplemented());
9692 ins_pipe(pipe_class_dummy);
9693 %}
9694
9695 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
9696 match(SafePoint poll);
9697 effect(USE poll, KILL cr); // R0 is killed, too.
9698 // TODO: s390 port size(FIXED_SIZE);
9699 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %}
9700 ins_encode %{
9701 // Mark the code position where the load from the safepoint
9702 // polling page was emitted as relocInfo::poll_type.
9703 __ relocate(relocInfo::poll_type);
9704 __ load_from_polling_page($poll$$Register);
9705 %}
9706 ins_pipe(pipe_class_dummy);
9707 %}
9708
9709 // ============================================================================
9710
9711 // Call Instructions
9712
9713 // Call Java Static Instruction
9714 instruct CallStaticJavaDirect_dynTOC(method meth) %{
9715 match(CallStaticJava);
9716 effect(USE meth);
9717 ins_cost(CALL_COST);
9718 // TODO: s390 port size(VARIABLE_SIZE);
9719 format %{ "CALL,static dynTOC $meth; ==> " %}
9720 ins_encode( z_enc_java_static_call(meth) );
9721 ins_pipe(pipe_class_dummy);
9722 ins_alignment(2);
9723 %}
9724
9725 // Call Java Dynamic Instruction
9726 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
9727 match(CallDynamicJava);
9728 effect(USE meth);
9729 ins_cost(CALL_COST);
9730 // TODO: s390 port size(VARIABLE_SIZE);
9731 format %{ "CALL,dynamic dynTOC $meth; ==> " %}
9732 ins_encode(z_enc_java_dynamic_call(meth));
9733 ins_pipe(pipe_class_dummy);
9734 ins_alignment(2);
9735 %}
9736
9737 // Call Runtime Instruction
9738 instruct CallRuntimeDirect(method meth) %{
9739 match(CallRuntime);
9740 effect(USE meth);
9741 ins_cost(CALL_COST);
9742 // TODO: s390 port size(VARIABLE_SIZE);
9743 ins_num_consts(1);
9744 ins_alignment(2);
9745 format %{ "CALL,runtime" %}
9746 ins_encode( z_enc_java_to_runtime_call(meth) );
9747 ins_pipe(pipe_class_dummy);
9748 %}
9749
9750 // Call runtime without safepoint - same as CallRuntime
9751 instruct CallLeafDirect(method meth) %{
9752 match(CallLeaf);
9753 effect(USE meth);
9754 ins_cost(CALL_COST);
9755 // TODO: s390 port size(VARIABLE_SIZE);
9756 ins_num_consts(1);
9757 ins_alignment(2);
9758 format %{ "CALL,runtime leaf $meth" %}
9759 ins_encode( z_enc_java_to_runtime_call(meth) );
9760 ins_pipe(pipe_class_dummy);
9761 %}
9762
9763 // Call runtime without safepoint - same as CallLeaf
9764 instruct CallLeafNoFPDirect(method meth) %{
9765 match(CallLeafNoFP);
9766 effect(USE meth);
9767 ins_cost(CALL_COST);
9768 // TODO: s390 port size(VARIABLE_SIZE);
9769 ins_num_consts(1);
9770 format %{ "CALL,runtime leaf nofp $meth" %}
9771 ins_encode( z_enc_java_to_runtime_call(meth) );
9772 ins_pipe(pipe_class_dummy);
9773 ins_alignment(2);
9774 %}
9775
9776 // Tail Call; Jump from runtime stub to Java code.
9777 // Also known as an 'interprocedural jump'.
9778 // Target of jump will eventually return to caller.
9779 // TailJump below removes the return address.
9780 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{
9781 match(TailCall jump_target method_oop);
9782 ins_cost(CALL_COST);
9783 size(2);
9784 format %{ "Jmp $jump_target\t # $method_oop holds method oop" %}
9785 ins_encode %{ __ z_br($jump_target$$Register); %}
9786 ins_pipe(pipe_class_dummy);
9787 %}
9788
9789 // Return Instruction
9790 instruct Ret() %{
9791 match(Return);
9792 size(2);
9793 format %{ "BR(Z_R14) // branch to link register" %}
9794 ins_encode %{ __ z_br(Z_R14); %}
9795 ins_pipe(pipe_class_dummy);
9796 %}
9797
9798 // Tail Jump; remove the return address; jump to target.
9799 // TailCall above leaves the return address around.
9800 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9801 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9802 // "restore" before this instruction (in Epilogue), we need to materialize it
9803 // in %i0.
9804 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
9805 match(TailJump jump_target ex_oop);
9806 ins_cost(CALL_COST);
9807 size(8);
9808 format %{ "TailJump $jump_target" %}
9809 ins_encode %{
9810 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
9811 __ z_br($jump_target$$Register);
9812 %}
9813 ins_pipe(pipe_class_dummy);
9814 %}
9815
9816 // Create exception oop: created by stack-crawling runtime code.
9817 // Created exception is now available to this handler, and is setup
9818 // just prior to jumping to this handler. No code emitted.
9819 instruct CreateException(rarg1RegP ex_oop) %{
9820 match(Set ex_oop (CreateEx));
9821 ins_cost(0);
9822 size(0);
9823 format %{ "# exception oop; no code emitted" %}
9824 ins_encode(/*empty*/);
9825 ins_pipe(pipe_class_dummy);
9826 %}
9827
9828 // Rethrow exception: The exception oop will come in the first
9829 // argument position. Then JUMP (not call) to the rethrow stub code.
9830 instruct RethrowException() %{
9831 match(Rethrow);
9832 ins_cost(CALL_COST);
9833 // TODO: s390 port size(VARIABLE_SIZE);
9834 format %{ "Jmp rethrow_stub" %}
9835 ins_encode %{
9836 cbuf.set_insts_mark();
9837 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
9838 __ z_br(Z_R1_scratch);
9839 %}
9840 ins_pipe(pipe_class_dummy);
9841 %}
9842
9843 // Die now.
9844 instruct ShouldNotReachHere() %{
9845 match(Halt);
9846 ins_cost(CALL_COST);
9847 size(2);
9848 format %{ "ILLTRAP; ShouldNotReachHere" %}
9849 ins_encode %{ __ z_illtrap(); %}
9850 ins_pipe(pipe_class_dummy);
9851 %}
9852
9853 // ============================================================================
9854 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9855 // array for an instance of the superklass. Set a hidden internal cache on a
9856 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9857 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9858 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
9859 rarg4RegP scratch1, rarg5RegP scratch2) %{
9860 match(Set index (PartialSubtypeCheck sub super));
9861 effect(KILL pcc, KILL scratch1, KILL scratch2);
9862 ins_cost(10 * DEFAULT_COST);
9863 // TODO: s390 port size(FIXED_SIZE);
9864 format %{ " CALL PartialSubtypeCheck\n" %}
9865 ins_encode %{
9866 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
9867 __ load_const_optimized(Z_ARG4, stub_address);
9868 __ z_basr(Z_R14, Z_ARG4);
9869 %}
9870 ins_pipe(pipe_class_dummy);
9871 %}
9872
9873 instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero,
9874 rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{
9875 match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero));
9876 effect(KILL scratch1, KILL scratch2, KILL index);
9877 ins_cost(10 * DEFAULT_COST);
9878 // TODO: s390 port size(FIXED_SIZE);
9879 format %{ "CALL PartialSubtypeCheck_vs_zero\n" %}
9880 ins_encode %{
9881 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
9882 __ load_const_optimized(Z_ARG4, stub_address);
9883 __ z_basr(Z_R14, Z_ARG4);
9884 %}
9885 ins_pipe(pipe_class_dummy);
9886 %}
9887
9888 // ============================================================================
9889 // inlined locking and unlocking
9890
9891 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
9892 match(Set pcc (FastLock oop box));
9893 effect(TEMP tmp1, TEMP tmp2);
9894 ins_cost(100);
9895 // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized.
9896 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
9897 ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
9898 UseBiasedLocking && !UseOptoBiasInlining); %}
9899 ins_pipe(pipe_class_dummy);
9900 %}
9901
9902 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
9903 match(Set pcc (FastUnlock oop box));
9904 effect(TEMP tmp1, TEMP tmp2);
9905 ins_cost(100);
9906 // TODO: s390 port size(FIXED_SIZE); // emitted code depends on UseBiasedLocking being on/off.
9907 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
9908 ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
9909 UseBiasedLocking && !UseOptoBiasInlining); %}
9910 ins_pipe(pipe_class_dummy);
9911 %}
9912
9913 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
9914 match(Set dummy (ClearArray cnt base));
9915 effect(KILL cr);
9916 ins_cost(100);
9917 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions.
9918 format %{ "ClearArrayConst $cnt,$base" %}
9919 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
9920 ins_pipe(pipe_class_dummy);
9921 %}
9922
9923 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
9924 match(Set dummy (ClearArray cnt base));
9925 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
9926 ins_cost(200);
9927 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader.
9928 format %{ "ClearArrayConstBig $cnt,$base" %}
9929 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %}
9930 ins_pipe(pipe_class_dummy);
9931 %}
9932
9933 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
9934 match(Set dummy (ClearArray cnt base));
9935 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
9936 ins_cost(300);
9937 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
9938 format %{ "ClearArrayVar $cnt,$base" %}
9939 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %}
9940 ins_pipe(pipe_class_dummy);
9941 %}
9942
9943 // ============================================================================
9944 // CompactStrings
9945
9946 // String equals
9947 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9948 match(Set result (StrEquals (Binary str1 str2) cnt));
9949 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9950 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
9951 ins_cost(300);
9952 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
9953 ins_encode %{
9954 __ array_equals(false, $str1$$Register, $str2$$Register,
9955 $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
9956 $result$$Register, true /* byte */);
9957 %}
9958 ins_pipe(pipe_class_dummy);
9959 %}
9960
9961 instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9962 match(Set result (StrEquals (Binary str1 str2) cnt));
9963 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9964 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
9965 ins_cost(300);
9966 format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %}
9967 ins_encode %{
9968 __ array_equals(false, $str1$$Register, $str2$$Register,
9969 $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
9970 $result$$Register, false /* byte */);
9971 %}
9972 ins_pipe(pipe_class_dummy);
9973 %}
9974
9975 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
9976 match(Set result (StrEquals (Binary str1 str2) cnt));
9977 effect(KILL cr); // R0 is killed, too.
9978 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
9979 ins_cost(100);
9980 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
9981 ins_encode %{
9982 const int cnt_imm = $cnt$$constant;
9983 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
9984 __ z_lhi($result$$Register, 1);
9985 if (cnt_imm) {
9986 if (VM_Version::has_LoadStoreConditional()) {
9987 __ z_lhi(Z_R0_scratch, 0);
9988 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
9989 } else {
9990 Label Lskip;
9991 __ z_bre(Lskip);
9992 __ clear_reg($result$$Register);
9993 __ bind(Lskip);
9994 }
9995 }
9996 %}
9997 ins_pipe(pipe_class_dummy);
9998 %}
9999
10000 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
10001 match(Set result (StrEquals (Binary str1 str2) cnt));
10002 effect(KILL cr); // R0 is killed, too.
10003 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
10004 ins_cost(100);
10005 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
10006 ins_encode %{
10007 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
10008 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
10009 __ z_lhi($result$$Register, 1);
10010 if (cnt_imm) {
10011 if (VM_Version::has_LoadStoreConditional()) {
10012 __ z_lhi(Z_R0_scratch, 0);
10013 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10014 } else {
10015 Label Lskip;
10016 __ z_bre(Lskip);
10017 __ clear_reg($result$$Register);
10018 __ bind(Lskip);
10019 }
10020 }
10021 %}
10022 ins_pipe(pipe_class_dummy);
10023 %}
10024
10025 // Array equals
10026 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10027 match(Set result (AryEq ary1 ary2));
10028 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10029 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10030 ins_cost(300);
10031 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10032 ins_encode %{
10033 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10034 noreg, $oddReg$$Register, $evenReg$$Register,
10035 $result$$Register, true /* byte */);
10036 %}
10037 ins_pipe(pipe_class_dummy);
10038 %}
10039
10040 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10041 match(Set result (AryEq ary1 ary2));
10042 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10043 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10044 ins_cost(300);
10045 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10046 ins_encode %{
10047 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10048 noreg, $oddReg$$Register, $evenReg$$Register,
10049 $result$$Register, false /* byte */);
10050 %}
10051 ins_pipe(pipe_class_dummy);
10052 %}
10053
10054 // String CompareTo
10055 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10056 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10057 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10058 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10059 ins_cost(300);
10060 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10061 ins_encode %{
10062 __ string_compare($str1$$Register, $str2$$Register,
10063 $cnt1$$Register, $cnt2$$Register,
10064 $oddReg$$Register, $evenReg$$Register,
10065 $result$$Register, StrIntrinsicNode::LL);
10066 %}
10067 ins_pipe(pipe_class_dummy);
10068 %}
10069
10070 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10071 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10072 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10073 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
10074 ins_cost(300);
10075 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10076 ins_encode %{
10077 __ string_compare($str1$$Register, $str2$$Register,
10078 $cnt1$$Register, $cnt2$$Register,
10079 $oddReg$$Register, $evenReg$$Register,
10080 $result$$Register, StrIntrinsicNode::UU);
10081 %}
10082 ins_pipe(pipe_class_dummy);
10083 %}
10084
10085 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10086 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10087 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10088 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10089 ins_cost(300);
10090 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10091 ins_encode %{
10092 __ string_compare($str1$$Register, $str2$$Register,
10093 $cnt1$$Register, $cnt2$$Register,
10094 $oddReg$$Register, $evenReg$$Register,
10095 $result$$Register, StrIntrinsicNode::LU);
10096 %}
10097 ins_pipe(pipe_class_dummy);
10098 %}
10099
10100 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10101 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10102 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10103 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10104 ins_cost(300);
10105 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10106 ins_encode %{
10107 __ string_compare($str2$$Register, $str1$$Register,
10108 $cnt2$$Register, $cnt1$$Register,
10109 $oddReg$$Register, $evenReg$$Register,
10110 $result$$Register, StrIntrinsicNode::UL);
10111 %}
10112 ins_pipe(pipe_class_dummy);
10113 %}
10114
10115 // String IndexOfChar
10116 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10117 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10118 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10119 ins_cost(200);
10120 format %{ "String IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10121 ins_encode %{
10122 __ string_indexof_char($result$$Register,
10123 $haystack$$Register, $haycnt$$Register,
10124 $ch$$Register, 0 /* unused, ch is in register */,
10125 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10126 %}
10127 ins_pipe(pipe_class_dummy);
10128 %}
10129
10130 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10131 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10132 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10133 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10134 ins_cost(200);
10135 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10136 ins_encode %{
10137 immPOper *needleOper = (immPOper *)$needle;
10138 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10139 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10140 jchar chr;
10141 #ifdef VM_LITTLE_ENDIAN
10142 Unimplemented();
10143 #else
10144 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10145 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10146 #endif
10147 __ string_indexof_char($result$$Register,
10148 $haystack$$Register, $haycnt$$Register,
10149 noreg, chr,
10150 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10151 %}
10152 ins_pipe(pipe_class_dummy);
10153 %}
10154
10155 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10156 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10157 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10158 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10159 ins_cost(200);
10160 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10161 ins_encode %{
10162 immPOper *needleOper = (immPOper *)$needle;
10163 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10164 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10165 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10166 __ string_indexof_char($result$$Register,
10167 $haystack$$Register, $haycnt$$Register,
10168 noreg, chr,
10169 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10170 %}
10171 ins_pipe(pipe_class_dummy);
10172 %}
10173
10174 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10175 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10176 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10177 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10178 ins_cost(200);
10179 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10180 ins_encode %{
10181 immPOper *needleOper = (immPOper *)$needle;
10182 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10183 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10184 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10185 __ string_indexof_char($result$$Register,
10186 $haystack$$Register, $haycnt$$Register,
10187 noreg, chr,
10188 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10189 %}
10190 ins_pipe(pipe_class_dummy);
10191 %}
10192
10193 // String IndexOf
10194 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10195 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10196 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10197 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10198 ins_cost(250);
10199 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10200 ins_encode %{
10201 __ string_indexof($result$$Register,
10202 $haystack$$Register, $haycnt$$Register,
10203 $needle$$Register, noreg, $needlecntImm$$constant,
10204 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10205 %}
10206 ins_pipe(pipe_class_dummy);
10207 %}
10208
10209 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10210 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10211 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10212 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10213 ins_cost(250);
10214 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10215 ins_encode %{
10216 __ string_indexof($result$$Register,
10217 $haystack$$Register, $haycnt$$Register,
10218 $needle$$Register, noreg, $needlecntImm$$constant,
10219 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10220 %}
10221 ins_pipe(pipe_class_dummy);
10222 %}
10223
10224 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10225 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10226 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10227 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10228 ins_cost(250);
10229 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10230 ins_encode %{
10231 __ string_indexof($result$$Register,
10232 $haystack$$Register, $haycnt$$Register,
10233 $needle$$Register, noreg, $needlecntImm$$constant,
10234 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10235 %}
10236 ins_pipe(pipe_class_dummy);
10237 %}
10238
10239 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10240 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10241 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10242 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10243 ins_cost(300);
10244 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10245 ins_encode %{
10246 __ string_indexof($result$$Register,
10247 $haystack$$Register, $haycnt$$Register,
10248 $needle$$Register, $needlecnt$$Register, 0,
10249 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10250 %}
10251 ins_pipe(pipe_class_dummy);
10252 %}
10253
10254 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10255 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10256 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10257 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10258 ins_cost(300);
10259 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10260 ins_encode %{
10261 __ string_indexof($result$$Register,
10262 $haystack$$Register, $haycnt$$Register,
10263 $needle$$Register, $needlecnt$$Register, 0,
10264 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10265 %}
10266 ins_pipe(pipe_class_dummy);
10267 %}
10268
10269 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10270 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10271 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10272 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10273 ins_cost(300);
10274 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10275 ins_encode %{
10276 __ string_indexof($result$$Register,
10277 $haystack$$Register, $haycnt$$Register,
10278 $needle$$Register, $needlecnt$$Register, 0,
10279 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10280 %}
10281 ins_pipe(pipe_class_dummy);
10282 %}
10283
10284 // char[] to byte[] compression
10285 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
10286 match(Set result (StrCompressedCopy src (Binary dst len)));
10287 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10288 ins_cost(300);
10289 format %{ "String Compress $src->$dst($len) -> $result" %}
10290 ins_encode %{
10291 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10292 $tmp$$Register, false);
10293 %}
10294 ins_pipe(pipe_class_dummy);
10295 %}
10296
10297 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10298 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10299 // match(Set dummy (StrInflatedCopy src (Binary dst len)));
10300 // effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10301 // predicate(VM_Version::has_ETF2Enhancements());
10302 // ins_cost(300);
10303 // format %{ "String Inflate (trot) $dst,$src($len)" %}
10304 // ins_encode %{
10305 // __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10306 // %}
10307 // ins_pipe(pipe_class_dummy);
10308 //%}
10309
10310 // byte[] to char[] inflation
10311 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, flagsReg cr) %{
10312 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10313 effect(TEMP tmp, KILL cr); // R0, R1 are killed, too.
10314 ins_cost(300);
10315 format %{ "String Inflate $src->$dst($len)" %}
10316 ins_encode %{
10317 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10318 %}
10319 ins_pipe(pipe_class_dummy);
10320 %}
10321
10322 // byte[] to char[] inflation
10323 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, flagsReg cr) %{
10324 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10325 effect(TEMP tmp, KILL cr); // R0, R1 are killed, too.
10326 ins_cost(300);
10327 format %{ "String Inflate (constLen) $src->$dst($len)" %}
10328 ins_encode %{
10329 __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant);
10330 %}
10331 ins_pipe(pipe_class_dummy);
10332 %}
10333
10334 // StringCoding.java intrinsics
10335 instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10336 match(Set result (HasNegatives ary1 len));
10337 effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10338 ins_cost(300);
10339 format %{ "has negatives byte[] $ary1($len) -> $result" %}
10340 ins_encode %{
10341 __ has_negatives($result$$Register, $ary1$$Register, $len$$Register,
10342 $oddReg$$Register, $evenReg$$Register, $tmp$$Register);
10343 %}
10344 ins_pipe(pipe_class_dummy);
10345 %}
10346
10347 // encode char[] to byte[] in ISO_8859_1
10348 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
10349 match(Set result (EncodeISOArray src (Binary dst len)));
10350 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10351 ins_cost(300);
10352 format %{ "Encode array $src->$dst($len) -> $result" %}
10353 ins_encode %{
10354 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10355 $tmp$$Register, true);
10356 %}
10357 ins_pipe(pipe_class_dummy);
10358 %}
10359
10360
10361 //----------PEEPHOLE RULES-----------------------------------------------------
10362 // These must follow all instruction definitions as they use the names
10363 // defined in the instructions definitions.
10364 //
10365 // peepmatch (root_instr_name [preceeding_instruction]*);
10366 //
10367 // peepconstraint %{
10368 // (instruction_number.operand_name relational_op instruction_number.operand_name
10369 // [, ...]);
10370 // // instruction numbers are zero-based using left to right order in peepmatch
10371 //
10372 // peepreplace (instr_name([instruction_number.operand_name]*));
10373 // // provide an instruction_number.operand_name for each operand that appears
10374 // // in the replacement instruction's match rule
10375 //
10376 // ---------VM FLAGS---------------------------------------------------------
10377 //
10378 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10379 //
10380 // Each peephole rule is given an identifying number starting with zero and
10381 // increasing by one in the order seen by the parser. An individual peephole
10382 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10383 // on the command-line.
10384 //
10385 // ---------CURRENT LIMITATIONS----------------------------------------------
10386 //
10387 // Only match adjacent instructions in same basic block
10388 // Only equality constraints
10389 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10390 // Only one replacement instruction
10391 //
10392 // ---------EXAMPLE----------------------------------------------------------
10393 //
10394 // // pertinent parts of existing instructions in architecture description
10395 // instruct movI(eRegI dst, eRegI src) %{
10396 // match(Set dst (CopyI src));
10397 // %}
10398 //
10399 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10400 // match(Set dst (AddI dst src));
10401 // effect(KILL cr);
10402 // %}
10403 //
10404 // // Change (inc mov) to lea
10405 // peephole %{
10406 // // increment preceeded by register-register move
10407 // peepmatch (incI_eReg movI);
10408 // // require that the destination register of the increment
10409 // // match the destination register of the move
10410 // peepconstraint (0.dst == 1.dst);
10411 // // construct a replacement instruction that sets
10412 // // the destination to (move's source register + one)
10413 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10414 // %}
10415 //
10416 // Implementation no longer uses movX instructions since
10417 // machine-independent system no longer uses CopyX nodes.
10418 //
10419 // peephole %{
10420 // peepmatch (incI_eReg movI);
10421 // peepconstraint (0.dst == 1.dst);
10422 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10423 // %}
10424 //
10425 // peephole %{
10426 // peepmatch (decI_eReg movI);
10427 // peepconstraint (0.dst == 1.dst);
10428 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10429 // %}
10430 //
10431 // peephole %{
10432 // peepmatch (addI_eReg_imm movI);
10433 // peepconstraint (0.dst == 1.dst);
10434 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10435 // %}
10436 //
10437 // peephole %{
10438 // peepmatch (addP_eReg_imm movP);
10439 // peepconstraint (0.dst == 1.dst);
10440 // peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10441 // %}
10442
10443
10444 // This peephole rule does not work, probably because ADLC can't handle two effects:
10445 // Effect 1 is defining 0.op1 and effect 2 is setting CC
10446 // condense a load from memory and subsequent test for zero
10447 // into a single, more efficient ICM instruction.
10448 // peephole %{
10449 // peepmatch (compI_iReg_imm0 loadI);
10450 // peepconstraint (1.dst == 0.op1);
10451 // peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10452 // %}
10453
10454 // // Change load of spilled value to only a spill
10455 // instruct storeI(memory mem, eRegI src) %{
10456 // match(Set mem (StoreI mem src));
10457 // %}
10458 //
10459 // instruct loadI(eRegI dst, memory mem) %{
10460 // match(Set dst (LoadI mem));
10461 // %}
10462 //
10463 peephole %{
10464 peepmatch (loadI storeI);
10465 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10466 peepreplace (storeI(1.mem 1.mem 1.src));
10467 %}
10468
10469 peephole %{
10470 peepmatch (loadL storeL);
10471 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10472 peepreplace (storeL(1.mem 1.mem 1.src));
10473 %}
10474
10475 peephole %{
10476 peepmatch (loadP storeP);
10477 peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10478 peepreplace (storeP(1.dst 1.dst 1.src));
10479 %}
10480
10481 //----------SUPERWORD RULES---------------------------------------------------
10482
10483 // Expand rules for special cases
10484
10485 instruct expand_storeF(stackSlotF mem, regF src) %{
10486 // No match rule, false predicate, for expand only.
10487 effect(DEF mem, USE src);
10488 predicate(false);
10489 ins_cost(MEMORY_REF_COST);
10490 // TODO: s390 port size(FIXED_SIZE);
10491 format %{ "STE $src,$mem\t # replicate(float2stack)" %}
10492 opcode(STE_ZOPC, STE_ZOPC);
10493 ins_encode(z_form_rt_mem(src, mem));
10494 ins_pipe(pipe_class_dummy);
10495 %}
10496
10497 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10498 // No match rule, false predicate, for expand only.
10499 effect(DEF dst, USE mem);
10500 predicate(false);
10501 ins_cost(MEMORY_REF_COST);
10502 // TODO: s390 port size(FIXED_SIZE);
10503 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10504 opcode(LLGF_ZOPC, LLGF_ZOPC);
10505 ins_encode(z_form_rt_mem(dst, mem));
10506 ins_pipe(pipe_class_dummy);
10507 %}
10508
10509 // Replicate scalar int to packed int values (8 Bytes)
10510 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10511 // Dummy match rule, false predicate, for expand only.
10512 match(Set dst (ConvI2L src));
10513 predicate(false);
10514 ins_cost(DEFAULT_COST);
10515 // TODO: s390 port size(FIXED_SIZE);
10516 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10517 ins_encode %{
10518 if ($dst$$Register == $src$$Register) {
10519 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10520 __ z_ogr($dst$$Register, Z_R0_scratch);
10521 } else {
10522 __ z_sllg($dst$$Register, $src$$Register, 64-32);
10523 __ z_ogr( $dst$$Register, $src$$Register);
10524 }
10525 %}
10526 ins_pipe(pipe_class_dummy);
10527 %}
10528
10529 // Replication
10530
10531 // Exploit rotate_then_insert, if available
10532 // Replicate scalar byte to packed byte values (8 Bytes).
10533 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10534 match(Set dst (ReplicateB src));
10535 effect(KILL cr);
10536 predicate((n->as_Vector()->length() == 8));
10537 format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10538 ins_encode %{
10539 if ($dst$$Register != $src$$Register) {
10540 __ z_lgr($dst$$Register, $src$$Register);
10541 }
10542 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false);
10543 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10544 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10545 %}
10546 ins_pipe(pipe_class_dummy);
10547 %}
10548
10549 // Replicate scalar byte to packed byte values (8 Bytes).
10550 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10551 match(Set dst (ReplicateB src));
10552 predicate(n->as_Vector()->length() == 8);
10553 ins_should_rematerialize(true);
10554 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10555 ins_encode %{
10556 int64_t Isrc8 = $src$$constant & 0x000000ff;
10557 int64_t Isrc16 = Isrc8 << 8 | Isrc8;
10558 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10559 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10560
10561 __ z_llilf($dst$$Register, Isrc32);
10562 __ z_iihf($dst$$Register, Isrc32);
10563 %}
10564 ins_pipe(pipe_class_dummy);
10565 %}
10566
10567 // Replicate scalar byte to packed byte values (8 Bytes).
10568 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10569 match(Set dst (ReplicateB src));
10570 predicate(n->as_Vector()->length() == 8);
10571 ins_should_rematerialize(true);
10572 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10573 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10574 ins_pipe(pipe_class_dummy);
10575 %}
10576
10577 // Replicate scalar byte to packed byte values (8 Bytes).
10578 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10579 match(Set dst (ReplicateB src));
10580 predicate(n->as_Vector()->length() == 8);
10581 ins_should_rematerialize(true);
10582 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10583 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10584 ins_pipe(pipe_class_dummy);
10585 %}
10586
10587 // Exploit rotate_then_insert, if available
10588 // Replicate scalar short to packed short values (8 Bytes).
10589 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10590 match(Set dst (ReplicateS src));
10591 effect(KILL cr);
10592 predicate((n->as_Vector()->length() == 4));
10593 format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10594 ins_encode %{
10595 if ($dst$$Register != $src$$Register) {
10596 __ z_lgr($dst$$Register, $src$$Register);
10597 }
10598 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10599 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10600 %}
10601 ins_pipe(pipe_class_dummy);
10602 %}
10603
10604 // Replicate scalar short to packed short values (8 Bytes).
10605 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10606 match(Set dst (ReplicateS src));
10607 predicate(n->as_Vector()->length() == 4);
10608 ins_should_rematerialize(true);
10609 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10610 ins_encode %{
10611 int64_t Isrc16 = $src$$constant & 0x0000ffff;
10612 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10613 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10614 ") should be handled by other match rules.", $src$$constant);
10615
10616 __ z_llilf($dst$$Register, Isrc32);
10617 __ z_iihf($dst$$Register, Isrc32);
10618 %}
10619 ins_pipe(pipe_class_dummy);
10620 %}
10621
10622 // Replicate scalar short to packed short values (8 Bytes).
10623 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10624 match(Set dst (ReplicateS src));
10625 predicate(n->as_Vector()->length() == 4);
10626 ins_should_rematerialize(true);
10627 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10628 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10629 ins_pipe(pipe_class_dummy);
10630 %}
10631
10632 // Replicate scalar short to packed short values (8 Bytes).
10633 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10634 match(Set dst (ReplicateS src));
10635 predicate(n->as_Vector()->length() == 4);
10636 ins_should_rematerialize(true);
10637 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10638 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10639 ins_pipe(pipe_class_dummy);
10640 %}
10641
10642 // Exploit rotate_then_insert, if available.
10643 // Replicate scalar int to packed int values (8 Bytes).
10644 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10645 match(Set dst (ReplicateI src));
10646 effect(KILL cr);
10647 predicate((n->as_Vector()->length() == 2));
10648 format %{ "REPLIC2I $dst,$src\t # pack2I" %}
10649 ins_encode %{
10650 if ($dst$$Register != $src$$Register) {
10651 __ z_lgr($dst$$Register, $src$$Register);
10652 }
10653 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10654 %}
10655 ins_pipe(pipe_class_dummy);
10656 %}
10657
10658 // Replicate scalar int to packed int values (8 Bytes).
10659 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
10660 match(Set dst (ReplicateI src));
10661 predicate(n->as_Vector()->length() == 2);
10662 ins_should_rematerialize(true);
10663 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
10664 ins_encode %{
10665 int64_t Isrc32 = $src$$constant;
10666 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
10667
10668 __ z_llilf($dst$$Register, Isrc32);
10669 __ z_iihf($dst$$Register, Isrc32);
10670 %}
10671 ins_pipe(pipe_class_dummy);
10672 %}
10673
10674 // Replicate scalar int to packed int values (8 Bytes).
10675 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
10676 match(Set dst (ReplicateI src));
10677 predicate(n->as_Vector()->length() == 2);
10678 ins_should_rematerialize(true);
10679 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
10680 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10681 ins_pipe(pipe_class_dummy);
10682 %}
10683
10684 // Replicate scalar int to packed int values (8 Bytes).
10685 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
10686 match(Set dst (ReplicateI src));
10687 predicate(n->as_Vector()->length() == 2);
10688 ins_should_rematerialize(true);
10689 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
10690 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10691 ins_pipe(pipe_class_dummy);
10692 %}
10693
10694 //
10695
10696 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
10697 match(Set dst (ReplicateF src));
10698 effect(KILL cr);
10699 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10700 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
10701 expand %{
10702 stackSlotF tmp;
10703 iRegL tmp2;
10704 expand_storeF(tmp, src);
10705 expand_LoadLogical_I2L(tmp2, tmp);
10706 expand_Repl2I_reg(dst, tmp2);
10707 %}
10708 %}
10709
10710 // Replicate scalar float to packed float values in GREG (8 Bytes).
10711 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
10712 match(Set dst (ReplicateF src));
10713 effect(KILL cr);
10714 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10715 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
10716 ins_encode %{
10717 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
10718 __ z_lgdr($dst$$Register, $src$$FloatRegister);
10719
10720 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg.
10721 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall.
10722 __ z_ogr($dst$$Register, Z_R0_scratch);
10723 %}
10724 ins_pipe(pipe_class_dummy);
10725 %}
10726
10727 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
10728 instruct Repl2F_imm(iRegL dst, immF src) %{
10729 match(Set dst (ReplicateF src));
10730 predicate(n->as_Vector()->length() == 2);
10731 ins_should_rematerialize(true);
10732 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
10733 ins_encode %{
10734 union {
10735 int Isrc32;
10736 float Fsrc32;
10737 };
10738 Fsrc32 = $src$$constant;
10739 __ z_llilf($dst$$Register, Isrc32);
10740 __ z_iihf($dst$$Register, Isrc32);
10741 %}
10742 ins_pipe(pipe_class_dummy);
10743 %}
10744
10745 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
10746 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
10747 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
10748 match(Set dst (ReplicateF src));
10749 predicate(n->as_Vector()->length() == 2);
10750 ins_should_rematerialize(true);
10751 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
10752 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10753 ins_pipe(pipe_class_dummy);
10754 %}
10755
10756 // Store
10757
10758 // Store Aligned Packed Byte register to memory (8 Bytes).
10759 instruct storeA8B(memory mem, iRegL src) %{
10760 match(Set mem (StoreVector mem src));
10761 predicate(n->as_StoreVector()->memory_size() == 8);
10762 ins_cost(MEMORY_REF_COST);
10763 // TODO: s390 port size(VARIABLE_SIZE);
10764 format %{ "STG $src,$mem\t # ST(packed8B)" %}
10765 opcode(STG_ZOPC, STG_ZOPC);
10766 ins_encode(z_form_rt_mem_opt(src, mem));
10767 ins_pipe(pipe_class_dummy);
10768 %}
10769
10770 // Load
10771
10772 instruct loadV8(iRegL dst, memory mem) %{
10773 match(Set dst (LoadVector mem));
10774 predicate(n->as_LoadVector()->memory_size() == 8);
10775 ins_cost(MEMORY_REF_COST);
10776 // TODO: s390 port size(VARIABLE_SIZE);
10777 format %{ "LG $dst,$mem\t # L(packed8B)" %}
10778 opcode(LG_ZOPC, LG_ZOPC);
10779 ins_encode(z_form_rt_mem_opt(dst, mem));
10780 ins_pipe(pipe_class_dummy);
10781 %}
10782
10783 //----------POPULATION COUNT RULES--------------------------------------------
10784
10785 // Byte reverse
10786
10787 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
10788 match(Set dst (ReverseBytesI src));
10789 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
10790 ins_cost(DEFAULT_COST);
10791 size(4);
10792 format %{ "LRVR $dst,$src\t # byte reverse int" %}
10793 opcode(LRVR_ZOPC);
10794 ins_encode(z_rreform(dst, src));
10795 ins_pipe(pipe_class_dummy);
10796 %}
10797
10798 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
10799 match(Set dst (ReverseBytesL src));
10800 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
10801 ins_cost(DEFAULT_COST);
10802 // TODO: s390 port size(FIXED_SIZE);
10803 format %{ "LRVGR $dst,$src\t # byte reverse long" %}
10804 opcode(LRVGR_ZOPC);
10805 ins_encode(z_rreform(dst, src));
10806 ins_pipe(pipe_class_dummy);
10807 %}
10808
10809 // Leading zeroes
10810
10811 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
10812 // returns the bit position of the leftmost 1 in the 64bit source register.
10813 // As the bits are numbered from left to right (0..63), the returned
10814 // position index is equivalent to the number of leading zeroes.
10815 // If no 1-bit is found (i.e. the regsiter contains zero), the instruction
10816 // returns position 64. That's exactly what we need.
10817
10818 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10819 match(Set dst (CountLeadingZerosI src));
10820 effect(KILL tmp, KILL cr);
10821 ins_cost(3 * DEFAULT_COST);
10822 size(14);
10823 format %{ "SLLG $dst,$src,32\t # no need to always count 32 zeroes first\n\t"
10824 "IILH $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t"
10825 "FLOGR $dst,$dst"
10826 %}
10827 ins_encode %{
10828 // Performance experiments indicate that "FLOGR" is using some kind of
10829 // iteration to find the leftmost "1" bit.
10830 //
10831 // The prior implementation zero-extended the 32-bit argument to 64 bit,
10832 // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
10833 // We could gain measurable speedup in micro benchmark:
10834 //
10835 // leading trailing
10836 // z10: int 2.04 1.68
10837 // long 1.00 1.02
10838 // z196: int 0.99 1.23
10839 // long 1.00 1.11
10840 //
10841 // By shifting the argument into the high-word instead of zero-extending it.
10842 // The add'l branch on condition (taken for a zero argument, very infrequent,
10843 // good prediction) is well compensated for by the savings.
10844 //
10845 // We leave the previous implementation in for some time in the future when
10846 // the "FLOGR" instruction may become less iterative.
10847
10848 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
10849 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
10850 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src.
10851 __ z_flogr($dst$$Register, $dst$$Register);
10852 %}
10853 ins_pipe(pipe_class_dummy);
10854 %}
10855
10856 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
10857 match(Set dst (CountLeadingZerosL src));
10858 effect(KILL tmp, KILL cr);
10859 ins_cost(DEFAULT_COST);
10860 size(4);
10861 format %{ "FLOGR $dst,$src \t # count leading zeros (long)\n\t" %}
10862 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
10863 ins_pipe(pipe_class_dummy);
10864 %}
10865
10866 // trailing zeroes
10867
10868 // We transform the trailing zeroes problem to a leading zeroes problem
10869 // such that can use the FLOGR instruction to our advantage.
10870
10871 // With
10872 // tmp1 = src - 1
10873 // we flip all trailing zeroes to ones and the rightmost one to zero.
10874 // All other bits remain unchanged.
10875 // With the complement
10876 // tmp2 = ~src
10877 // we get all ones in the trailing zeroes positions. Thus,
10878 // tmp3 = tmp1 & tmp2
10879 // yields ones in the trailing zeroes positions and zeroes elsewhere.
10880 // Now we can apply FLOGR and get 64-(trailing zeroes).
10881 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10882 match(Set dst (CountTrailingZerosI src));
10883 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10884 ins_cost(8 * DEFAULT_COST);
10885 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
10886 format %{ "LLGFR $dst,$src \t # clear upper 32 bits (we are dealing with int)\n\t"
10887 "LCGFR $tmp,$src \t # load 2's complement (32->64 bit)\n\t"
10888 "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
10889 "AGHI $tmp,-1 \t # tmp2 = -src-1 = ~src\n\t"
10890 "NGR $dst,$tmp \t # tmp3 = tmp1&tmp2\n\t"
10891 "FLOGR $dst,$dst \t # count trailing zeros (int)\n\t"
10892 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
10893 "LCR $dst,$dst \t # res = -tmp4"
10894 %}
10895 ins_encode %{
10896 Register Rdst = $dst$$Register;
10897 Register Rsrc = $src$$Register;
10898 // Rtmp only needed for for zero-argument shortcut. With kill effect in
10899 // match rule Rsrc = roddReg would be possible, saving one register.
10900 Register Rtmp = $tmp$$Register;
10901
10902 assert_different_registers(Rdst, Rsrc, Rtmp);
10903
10904 // Algorithm:
10905 // - Isolate the least significant (rightmost) set bit using (src & (-src)).
10906 // All other bits in the result are zero.
10907 // - Find the "leftmost one" bit position in the single-bit result from previous step.
10908 // - 63-("leftmost one" bit position) gives the # of trailing zeros.
10909
10910 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
10911 Label done;
10912 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
10913 __ z_lcgfr(Rtmp, Rsrc);
10914 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry.
10915
10916 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit.
10917 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones.
10918 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
10919 // into upper half of reg. Not relevant with sllg below.
10920 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register.
10921 __ z_bre(done); // Shortcut for argument = 1, result will be 0.
10922 // Depends on CC set by ahi above.
10923 // Taken very infrequently, good prediction, no BHT entry.
10924 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
10925 // after SLLG Rdst == 0(64bit)).
10926 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
10927 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros
10928 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
10929 __ bind(done);
10930 %}
10931 ins_pipe(pipe_class_dummy);
10932 %}
10933
10934 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
10935 match(Set dst (CountTrailingZerosL src));
10936 effect(TEMP_DEF dst, KILL tmp, KILL cr);
10937 ins_cost(8 * DEFAULT_COST);
10938 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
10939 format %{ "LCGR $dst,$src \t # preserve src\n\t"
10940 "NGR $dst,$src \t #\n\t"
10941 "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
10942 "FLOGR $dst,$dst \t # count trailing zeros (long), kill $tmp\n\t"
10943 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
10944 "LCR $dst,$dst \t #"
10945 %}
10946 ins_encode %{
10947 Register Rdst = $dst$$Register;
10948 Register Rsrc = $src$$Register;
10949 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
10950
10951 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
10952 __ z_lcgr(Rdst, Rsrc);
10953 __ z_ngr(Rdst, Rsrc);
10954 __ add2reg(Rdst, -1);
10955 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
10956 __ add2reg(Rdst, -64);
10957 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
10958 %}
10959 ins_pipe(pipe_class_dummy);
10960 %}
10961
10962
10963 // bit count
10964
10965 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10966 match(Set dst (PopCountI src));
10967 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10968 predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10969 ins_cost(DEFAULT_COST);
10970 size(24);
10971 format %{ "POPCNT $dst,$src\t # pop count int" %}
10972 ins_encode %{
10973 Register Rdst = $dst$$Register;
10974 Register Rsrc = $src$$Register;
10975 Register Rtmp = $tmp$$Register;
10976
10977 // Prefer compile-time assertion over run-time SIGILL.
10978 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10979 assert_different_registers(Rdst, Rtmp);
10980
10981 // Version 2: shows 10%(z196) improvement over original.
10982 __ z_popcnt(Rdst, Rsrc);
10983 __ z_srlg(Rtmp, Rdst, 16); // calc byte4+byte6 and byte5+byte7
10984 __ z_alr(Rdst, Rtmp); // into byte6 and byte7
10985 __ z_srlg(Rtmp, Rdst, 8); // calc (byte4+byte6) + (byte5+byte7)
10986 __ z_alr(Rdst, Rtmp); // into byte7
10987 __ z_llgcr(Rdst, Rdst); // zero-extend sum
10988 %}
10989 ins_pipe(pipe_class_dummy);
10990 %}
10991
10992 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
10993 match(Set dst (PopCountL src));
10994 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10995 predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10996 ins_cost(DEFAULT_COST);
10997 // TODO: s390 port size(FIXED_SIZE);
10998 format %{ "POPCNT $dst,$src\t # pop count long" %}
10999 ins_encode %{
11000 Register Rdst = $dst$$Register;
11001 Register Rsrc = $src$$Register;
11002 Register Rtmp = $tmp$$Register;
11003
11004 // Prefer compile-time assertion over run-time SIGILL.
11005 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
11006 assert_different_registers(Rdst, Rtmp);
11007
11008 // Original version. Using LA instead of algr seems to be a really bad idea (-35%).
11009 __ z_popcnt(Rdst, Rsrc);
11010 __ z_ahhlr(Rdst, Rdst, Rdst);
11011 __ z_sllg(Rtmp, Rdst, 16);
11012 __ z_algr(Rdst, Rtmp);
11013 __ z_sllg(Rtmp, Rdst, 8);
11014 __ z_algr(Rdst, Rtmp);
11015 __ z_srlg(Rdst, Rdst, 56);
11016 %}
11017 ins_pipe(pipe_class_dummy);
11018 %}
11019
11020 //----------SMARTSPILL RULES---------------------------------------------------
11021 // These must follow all instruction definitions as they use the names
11022 // defined in the instructions definitions.
11023
11024 // ============================================================================
11025 // TYPE PROFILING RULES