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src/hotspot/share/opto/block.cpp

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rev 54883 : 8213084: Rework and enhance Print[Opto]Assembly output
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   1 /*
   2  * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *


 250       uncommon_preds++;
 251     } else {
 252       freq_preds++;
 253       if(block->_freq < guard->_freq * guard_factor ) {
 254         uncommon_for_freq_preds++;
 255       }
 256     }
 257   }
 258   if( block->num_preds() > 1 &&
 259       // The block is uncommon if all preds are uncommon or
 260       (uncommon_preds == (block->num_preds()-1) ||
 261       // it is uncommon for all frequent preds.
 262        uncommon_for_freq_preds == freq_preds) ) {
 263     return true;
 264   }
 265   return false;
 266 }
 267 
 268 #ifndef PRODUCT
 269 void Block::dump_bidx(const Block* orig, outputStream* st) const {
 270   if (_pre_order) st->print("B%d",_pre_order);
 271   else st->print("N%d", head()->_idx);
 272 
 273   if (Verbose && orig != this) {
 274     // Dump the original block's idx
 275     st->print(" (");
 276     orig->dump_bidx(orig, st);
 277     st->print(")");
 278   }
 279 }
 280 
 281 void Block::dump_pred(const PhaseCFG* cfg, Block* orig, outputStream* st) const {
 282   if (is_connector()) {
 283     for (uint i=1; i<num_preds(); i++) {
 284       Block *p = cfg->get_block_for_node(pred(i));
 285       p->dump_pred(cfg, orig, st);
 286     }
 287   } else {
 288     dump_bidx(orig, st);
 289     st->print(" ");
 290   }
 291 }
 292 
 293 void Block::dump_head(const PhaseCFG* cfg, outputStream* st) const {
 294   // Print the basic block
 295   dump_bidx(this, st);
 296   st->print(": #\t");
 297 
 298   // Print the incoming CFG edges and the outgoing CFG edges

 299   for( uint i=0; i<_num_succs; i++ ) {
 300     non_connector_successor(i)->dump_bidx(_succs[i], st);
 301     st->print(" ");
 302   }
 303   st->print("<- ");


 304   if( head()->is_block_start() ) {

 305     for (uint i=1; i<num_preds(); i++) {
 306       Node *s = pred(i);
 307       if (cfg != NULL) {
 308         Block *p = cfg->get_block_for_node(s);
 309         p->dump_pred(cfg, p, st);
 310       } else {
 311         while (!s->is_block_start())
 312           s = s->in(0);

 313         st->print("N%d ", s->_idx );
 314       }
 315     }

 316   } else {
 317     st->print("BLOCK HEAD IS JUNK  ");
 318   }
 319 
 320   // Print loop, if any
 321   const Block *bhead = this;    // Head of self-loop
 322   Node *bh = bhead->head();
 323 
 324   if ((cfg != NULL) && bh->is_Loop() && !head()->is_Root()) {
 325     LoopNode *loop = bh->as_Loop();
 326     const Block *bx = cfg->get_block_for_node(loop->in(LoopNode::LoopBackControl));
 327     while (bx->is_connector()) {
 328       bx = cfg->get_block_for_node(bx->pred(1));
 329     }
 330     st->print("\tLoop: B%d-B%d ", bhead->_pre_order, bx->_pre_order);
 331     // Dump any loop-specific bits, especially for CountedLoops.
 332     loop->dump_spec(st);

 333   } else if (has_loop_alignment()) {
 334     st->print(" top-of-loop");
 335   }


 336   st->print(" Freq: %g",_freq);
 337   if( Verbose || WizardMode ) {
 338     st->print(" IDom: %d/#%d", _idom ? _idom->_pre_order : 0, _dom_depth);
 339     st->print(" RegPressure: %d",_reg_pressure);
 340     st->print(" IHRP Index: %d",_ihrp_index);
 341     st->print(" FRegPressure: %d",_freg_pressure);
 342     st->print(" FHRP Index: %d",_fhrp_index);
 343   }
 344   st->cr();
 345 }
 346 
 347 void Block::dump() const {
 348   dump(NULL);
 349 }
 350 
 351 void Block::dump(const PhaseCFG* cfg) const {
 352   dump_head(cfg);
 353   for (uint i=0; i< number_of_nodes(); i++) {
 354     get_node(i)->dump();
 355   }


   1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *


 250       uncommon_preds++;
 251     } else {
 252       freq_preds++;
 253       if(block->_freq < guard->_freq * guard_factor ) {
 254         uncommon_for_freq_preds++;
 255       }
 256     }
 257   }
 258   if( block->num_preds() > 1 &&
 259       // The block is uncommon if all preds are uncommon or
 260       (uncommon_preds == (block->num_preds()-1) ||
 261       // it is uncommon for all frequent preds.
 262        uncommon_for_freq_preds == freq_preds) ) {
 263     return true;
 264   }
 265   return false;
 266 }
 267 
 268 #ifndef PRODUCT
 269 void Block::dump_bidx(const Block* orig, outputStream* st) const {
 270   if (_pre_order) st->print("B%d", _pre_order);
 271   else st->print("N%d", head()->_idx);
 272 
 273   if (Verbose && orig != this) {
 274     // Dump the original block's idx
 275     st->print(" (");
 276     orig->dump_bidx(orig, st);
 277     st->print(")");
 278   }
 279 }
 280 
 281 void Block::dump_pred(const PhaseCFG* cfg, Block* orig, outputStream* st) const {
 282   if (is_connector()) {
 283     for (uint i=1; i<num_preds(); i++) {
 284       Block *p = cfg->get_block_for_node(pred(i));
 285       p->dump_pred(cfg, orig, st);
 286     }
 287   } else {
 288     dump_bidx(orig, st);
 289     st->print(" ");
 290   }
 291 }
 292 
 293 void Block::dump_head(const PhaseCFG* cfg, outputStream* st) const {
 294   // Print the basic block.
 295   dump_bidx(this, st);
 296   st->print(": ");
 297 
 298   // Print the outgoing CFG edges.
 299   st->print("#\tout( ");
 300   for( uint i=0; i<_num_succs; i++ ) {
 301     non_connector_successor(i)->dump_bidx(_succs[i], st);
 302     st->print(" ");
 303   }
 304 
 305   // Print the incoming CFG edges.
 306   st->print(") <- ");
 307   if( head()->is_block_start() ) {
 308     st->print("in( ");
 309     for (uint i=1; i<num_preds(); i++) {
 310       Node *s = pred(i);
 311       if (cfg != NULL) {
 312         Block *p = cfg->get_block_for_node(s);
 313         p->dump_pred(cfg, p, st);
 314       } else {
 315         while (!s->is_block_start()) {
 316           s = s->in(0);
 317         }
 318         st->print("N%d ", s->_idx );
 319       }
 320     }
 321     st->print(") ");
 322   } else {
 323     st->print("BLOCK HEAD IS JUNK ");
 324   }
 325 
 326   // Print loop, if any
 327   const Block *bhead = this;    // Head of self-loop
 328   Node *bh = bhead->head();
 329 
 330   if ((cfg != NULL) && bh->is_Loop() && !head()->is_Root()) {
 331     LoopNode *loop = bh->as_Loop();
 332     const Block *bx = cfg->get_block_for_node(loop->in(LoopNode::LoopBackControl));
 333     while (bx->is_connector()) {
 334       bx = cfg->get_block_for_node(bx->pred(1));
 335     }
 336     st->print("Loop( B%d-B%d ", bhead->_pre_order, bx->_pre_order);
 337     // Dump any loop-specific bits, especially for CountedLoops.
 338     loop->dump_spec(st);
 339     st->print(")");
 340   } else if (has_loop_alignment()) {
 341     st->print("top-of-loop");
 342   }
 343 
 344   // Print frequency and other optimization-relevant information
 345   st->print(" Freq: %g",_freq);
 346   if( Verbose || WizardMode ) {
 347     st->print(" IDom: %d/#%d", _idom ? _idom->_pre_order : 0, _dom_depth);
 348     st->print(" RegPressure: %d",_reg_pressure);
 349     st->print(" IHRP Index: %d",_ihrp_index);
 350     st->print(" FRegPressure: %d",_freg_pressure);
 351     st->print(" FHRP Index: %d",_fhrp_index);
 352   }
 353   st->cr();
 354 }
 355 
 356 void Block::dump() const {
 357   dump(NULL);
 358 }
 359 
 360 void Block::dump(const PhaseCFG* cfg) const {
 361   dump_head(cfg);
 362   for (uint i=0; i< number_of_nodes(); i++) {
 363     get_node(i)->dump();
 364   }


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