1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2020 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "jvm.h"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "utilities/align.hpp"
36 #include "utilities/defaultStream.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "vm_version_ppc.hpp"
39
40 #include <sys/sysinfo.h>
41 #if defined(_AIX)
42 #include <libperfstat.h>
43 #endif
44
45 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
46 #include <sys/auxv.h>
47
48 #ifndef PPC_FEATURE2_HTM_NOSC
49 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
50 #endif
51 #endif
52
53 bool VM_Version::_is_determine_features_test_running = false;
54 uint64_t VM_Version::_dscr_val = 0;
55
56 #define MSG(flag) \
57 if (flag && !FLAG_IS_DEFAULT(flag)) \
58 jio_fprintf(defaultStream::error_stream(), \
59 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
60 " -XX:+" #flag " will be disabled!\n");
61
62 void VM_Version::initialize() {
63
64 // Test which instructions are supported and measure cache line size.
65 determine_features();
66
67 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
68 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
69 if (VM_Version::has_brw()) {
70 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 10);
71 } else if (VM_Version::has_darn()) {
72 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 9);
73 } else if (VM_Version::has_lqarx()) {
74 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
75 } else if (VM_Version::has_popcntw()) {
76 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
77 } else if (VM_Version::has_cmpb()) {
78 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
79 } else if (VM_Version::has_popcntb()) {
80 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
81 } else {
82 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
83 }
84 }
85
86 bool PowerArchitecturePPC64_ok = false;
87 switch (PowerArchitecturePPC64) {
88 case 10: if (!VM_Version::has_brw() ) break;
89 case 9: if (!VM_Version::has_darn() ) break;
90 case 8: if (!VM_Version::has_lqarx() ) break;
91 case 7: if (!VM_Version::has_popcntw()) break;
92 case 6: if (!VM_Version::has_cmpb() ) break;
93 case 5: if (!VM_Version::has_popcntb()) break;
94 case 0: PowerArchitecturePPC64_ok = true; break;
95 default: break;
96 }
97 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
98 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
99
100 // Power 8: Configure Data Stream Control Register.
101 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
102 config_dscr();
103 }
104
105 if (!UseSIGTRAP) {
106 MSG(TrapBasedICMissChecks);
107 MSG(TrapBasedNotEntrantChecks);
108 MSG(TrapBasedNullChecks);
109 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
110 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
111 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
112 }
113
114 #ifdef COMPILER2
115 if (!UseSIGTRAP) {
116 MSG(TrapBasedRangeChecks);
117 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
118 }
119
120 // On Power6 test for section size.
121 if (PowerArchitecturePPC64 == 6) {
122 determine_section_size();
123 // TODO: PPC port } else {
124 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
125 }
126
127 if (PowerArchitecturePPC64 >= 8) {
128 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
129 FLAG_SET_ERGO(bool, SuperwordUseVSX, true);
130 }
131 } else {
132 if (SuperwordUseVSX) {
133 warning("SuperwordUseVSX specified, but needs at least Power8.");
134 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
135 }
136 }
137 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
138
139 if (PowerArchitecturePPC64 >= 9) {
140 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionsPPC64)) {
141 FLAG_SET_ERGO(bool, UseCountTrailingZerosInstructionsPPC64, true);
142 }
143 if (FLAG_IS_DEFAULT(UseCharacterCompareIntrinsics)) {
144 FLAG_SET_ERGO(bool, UseCharacterCompareIntrinsics, true);
145 }
146 } else {
147 if (UseCountTrailingZerosInstructionsPPC64) {
148 warning("UseCountTrailingZerosInstructionsPPC64 specified, but needs at least Power9.");
149 FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionsPPC64, false);
150 }
151 if (UseCharacterCompareIntrinsics) {
152 warning("UseCharacterCompareIntrinsics specified, but needs at least Power9.");
153 FLAG_SET_DEFAULT(UseCharacterCompareIntrinsics, false);
154 }
155 }
156
157 if (PowerArchitecturePPC64 >= 10) {
158 if (FLAG_IS_DEFAULT(UseByteReverseInstructions)) {
159 FLAG_SET_ERGO(bool, UseByteReverseInstructions, true);
160 }
161 } else {
162 if (UseByteReverseInstructions) {
163 warning("UseByteReverseInstructions specified, but needs at least Power10.");
164 FLAG_SET_DEFAULT(UseByteReverseInstructions, false);
165 }
166 }
167 #endif
168
169 // Create and print feature-string.
170 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
171 jio_snprintf(buf, sizeof(buf),
172 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
173 (has_fsqrt() ? " fsqrt" : ""),
174 (has_isel() ? " isel" : ""),
175 (has_lxarxeh() ? " lxarxeh" : ""),
176 (has_cmpb() ? " cmpb" : ""),
177 (has_popcntb() ? " popcntb" : ""),
178 (has_popcntw() ? " popcntw" : ""),
179 (has_fcfids() ? " fcfids" : ""),
180 (has_vand() ? " vand" : ""),
181 (has_lqarx() ? " lqarx" : ""),
182 (has_vcipher() ? " aes" : ""),
183 (has_vpmsumb() ? " vpmsumb" : ""),
184 (has_mfdscr() ? " mfdscr" : ""),
185 (has_vsx() ? " vsx" : ""),
186 (has_ldbrx() ? " ldbrx" : ""),
187 (has_stdbrx() ? " stdbrx" : ""),
188 (has_vshasig() ? " sha" : ""),
189 (has_tm() ? " rtm" : ""),
190 (has_darn() ? " darn" : ""),
191 (has_brw() ? " brw" : "")
192 // Make sure number of %s matches num_features!
193 );
194 _features_string = os::strdup(buf);
195 if (Verbose) {
196 print_features();
197 }
198
199 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
200 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
201 _supports_cx8 = true;
202
203 // Used by C1.
204 _supports_atomic_getset4 = true;
205 _supports_atomic_getadd4 = true;
206 _supports_atomic_getset8 = true;
207 _supports_atomic_getadd8 = true;
208
209 UseSSE = 0; // Only on x86 and x64
210
211 intx cache_line_size = L1_data_cache_line_size();
212
213 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
214
215 if (AllocatePrefetchStyle == 4) {
216 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
217 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
218 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
219 } else {
220 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
221 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
222 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
223 }
224
225 assert(AllocatePrefetchLines > 0, "invalid value");
226 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
227 AllocatePrefetchLines = 1; // Conservative value.
228 }
229
230 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
231 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
232 }
233
234 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
235
236 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (cache_line_size > ContendedPaddingWidth)) {
237 ContendedPaddingWidth = cache_line_size;
238 }
239
240 // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
241 // In all other cases, the implementation uses only generally available instructions.
242 if (!UseCRC32Intrinsics) {
243 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
244 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
245 }
246 }
247
248 // Implementation does not use any of the vector instructions available with Power8.
249 // Their exploitation is still pending (aka "work in progress").
250 if (!UseCRC32CIntrinsics) {
251 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
252 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
253 }
254 }
255
256 // TODO: Provide implementation.
257 if (UseAdler32Intrinsics) {
258 warning("Adler32Intrinsics not available on this CPU.");
259 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
260 }
261
262 // The AES intrinsic stubs require AES instruction support.
263 if (has_vcipher()) {
264 if (FLAG_IS_DEFAULT(UseAES)) {
265 UseAES = true;
266 }
267 } else if (UseAES) {
268 if (!FLAG_IS_DEFAULT(UseAES))
269 warning("AES instructions are not available on this CPU");
270 FLAG_SET_DEFAULT(UseAES, false);
271 }
272
273 if (UseAES && has_vcipher()) {
274 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
275 UseAESIntrinsics = true;
276 }
277 } else if (UseAESIntrinsics) {
278 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
279 warning("AES intrinsics are not available on this CPU");
280 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
281 }
282
283 if (UseAESCTRIntrinsics) {
284 warning("AES/CTR intrinsics are not available on this CPU");
285 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
286 }
287
288 if (UseGHASHIntrinsics) {
289 warning("GHASH intrinsics are not available on this CPU");
290 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
291 }
292
293 if (FLAG_IS_DEFAULT(UseFMA)) {
294 FLAG_SET_DEFAULT(UseFMA, true);
295 }
296
297 if (has_vshasig()) {
298 if (FLAG_IS_DEFAULT(UseSHA)) {
299 UseSHA = true;
300 }
301 } else if (UseSHA) {
302 if (!FLAG_IS_DEFAULT(UseSHA))
303 warning("SHA instructions are not available on this CPU");
304 FLAG_SET_DEFAULT(UseSHA, false);
305 }
306
307 if (UseSHA1Intrinsics) {
308 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
309 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
310 }
311
312 if (UseSHA && has_vshasig()) {
313 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
314 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
315 }
316 } else if (UseSHA256Intrinsics) {
317 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
318 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
319 }
320
321 if (UseSHA && has_vshasig()) {
322 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
323 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
324 }
325 } else if (UseSHA512Intrinsics) {
326 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
327 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
328 }
329
330 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
331 FLAG_SET_DEFAULT(UseSHA, false);
332 }
333
334 #ifdef COMPILER2
335 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
336 UseSquareToLenIntrinsic = true;
337 }
338 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
339 UseMulAddIntrinsic = true;
340 }
341 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
342 UseMultiplyToLenIntrinsic = true;
343 }
344 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
345 UseMontgomeryMultiplyIntrinsic = true;
346 }
347 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
348 UseMontgomerySquareIntrinsic = true;
349 }
350 #endif
351
352 if (UseVectorizedMismatchIntrinsic) {
353 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
354 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
355 }
356
357
358 // Adjust RTM (Restricted Transactional Memory) flags.
359 if (UseRTMLocking) {
360 // If CPU or OS do not support TM:
361 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
362 // setting during arguments processing. See use_biased_locking().
363 // VM_Version_init() is executed after UseBiasedLocking is used
364 // in Thread::allocate().
365 if (PowerArchitecturePPC64 < 8) {
366 vm_exit_during_initialization("RTM instructions are not available on this CPU.");
367 }
368
369 if (!has_tm()) {
370 vm_exit_during_initialization("RTM is not supported on this OS version.");
371 }
372 }
373
374 if (UseRTMLocking) {
375 #if INCLUDE_RTM_OPT
376 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
377 // RTM locking should be used only for applications with
378 // high lock contention. For now we do not use it by default.
379 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
380 }
381 #else
382 // Only C2 does RTM locking optimization.
383 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
384 // setting during arguments processing. See use_biased_locking().
385 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
386 #endif
387 } else { // !UseRTMLocking
388 if (UseRTMForStackLocks) {
389 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
390 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
391 }
392 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
393 }
394 if (UseRTMDeopt) {
395 FLAG_SET_DEFAULT(UseRTMDeopt, false);
396 }
397 #ifdef COMPILER2
398 if (PrintPreciseRTMLockingStatistics) {
399 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
400 }
401 #endif
402 }
403
404 // This machine allows unaligned memory accesses
405 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
406 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
407 }
408
409 check_virtualizations();
410 }
411
412 void VM_Version::check_virtualizations() {
413 #if defined(_AIX)
414 int rc = 0;
415 perfstat_partition_total_t pinfo;
416 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
417 if (rc == 1) {
418 Abstract_VM_Version::_detected_virtualization = PowerVM;
419 }
420 #else
421 const char* info_file = "/proc/ppc64/lparcfg";
422 // system_type=...qemu indicates PowerKVM
423 // e.g. system_type=IBM pSeries (emulated by qemu)
424 char line[500];
425 FILE* fp = fopen(info_file, "r");
426 if (fp == NULL) {
427 return;
428 }
429 const char* system_type="system_type="; // in case this line contains qemu, it is KVM
430 const char* num_lpars="NumLpars="; // in case of non-KVM : if this line is found it is PowerVM
431 bool num_lpars_found = false;
432
433 while (fgets(line, sizeof(line), fp) != NULL) {
434 if (strncmp(line, system_type, strlen(system_type)) == 0) {
435 if (strstr(line, "qemu") != 0) {
436 Abstract_VM_Version::_detected_virtualization = PowerKVM;
437 fclose(fp);
438 return;
439 }
440 }
441 if (strncmp(line, num_lpars, strlen(num_lpars)) == 0) {
442 num_lpars_found = true;
443 }
444 }
445 if (num_lpars_found) {
446 Abstract_VM_Version::_detected_virtualization = PowerVM;
447 } else {
448 Abstract_VM_Version::_detected_virtualization = PowerFullPartitionMode;
449 }
450 fclose(fp);
451 #endif
452 }
453
454 void VM_Version::print_platform_virtualization_info(outputStream* st) {
455 #if defined(_AIX)
456 // more info about perfstat API see
457 // https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.prftools/idprftools_perfstat_glob_partition.htm
458 int rc = 0;
459 perfstat_partition_total_t pinfo;
460 memset(&pinfo, 0, sizeof(perfstat_partition_total_t));
461 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
462 if (rc != 1) {
463 return;
464 } else {
465 st->print_cr("Virtualization type : PowerVM");
466 }
467 // CPU information
468 perfstat_cpu_total_t cpuinfo;
469 memset(&cpuinfo, 0, sizeof(perfstat_cpu_total_t));
470 rc = perfstat_cpu_total(NULL, &cpuinfo, sizeof(perfstat_cpu_total_t), 1);
471 if (rc != 1) {
472 return;
473 }
474
475 st->print_cr("Processor description : %s", cpuinfo.description);
476 st->print_cr("Processor speed : %llu Hz", cpuinfo.processorHZ);
477
478 st->print_cr("LPAR partition name : %s", pinfo.name);
479 st->print_cr("LPAR partition number : %u", pinfo.lpar_id);
480 st->print_cr("LPAR partition type : %s", pinfo.type.b.shared_enabled ? "shared" : "dedicated");
481 st->print_cr("LPAR mode : %s", pinfo.type.b.donate_enabled ? "donating" : pinfo.type.b.capped ? "capped" : "uncapped");
482 st->print_cr("LPAR partition group ID : %u", pinfo.group_id);
483 st->print_cr("LPAR shared pool ID : %u", pinfo.pool_id);
484
485 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_capable ? "capable" : "not capable");
486 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_enabled ? "on" : "off");
487 st->print_cr("AME (active memory expansion) : %s", pinfo.type.b.ame_enabled ? "on" : "off");
488
489 if (pinfo.type.b.ame_enabled) {
490 st->print_cr("AME true memory in bytes : %llu", pinfo.true_memory);
491 st->print_cr("AME expanded memory in bytes : %llu", pinfo.expanded_memory);
492 }
493
494 st->print_cr("SMT : %s", pinfo.type.b.smt_capable ? "capable" : "not capable");
495 st->print_cr("SMT : %s", pinfo.type.b.smt_enabled ? "on" : "off");
496 int ocpus = pinfo.online_cpus > 0 ? pinfo.online_cpus : 1;
497 st->print_cr("LPAR threads : %d", cpuinfo.ncpus/ocpus);
498 st->print_cr("LPAR online virtual cpus : %d", pinfo.online_cpus);
499 st->print_cr("LPAR logical cpus : %d", cpuinfo.ncpus);
500 st->print_cr("LPAR maximum virtual cpus : %u", pinfo.max_cpus);
501 st->print_cr("LPAR minimum virtual cpus : %u", pinfo.min_cpus);
502 st->print_cr("LPAR entitled capacity : %4.2f", (double) (pinfo.entitled_proc_capacity/100.0));
503 st->print_cr("LPAR online memory : %llu MB", pinfo.online_memory);
504 st->print_cr("LPAR maximum memory : %llu MB", pinfo.max_memory);
505 st->print_cr("LPAR minimum memory : %llu MB", pinfo.min_memory);
506 #else
507 const char* info_file = "/proc/ppc64/lparcfg";
508 const char* kw[] = { "system_type=", // qemu indicates PowerKVM
509 "partition_entitled_capacity=", // entitled processor capacity percentage
510 "partition_max_entitled_capacity=",
511 "capacity_weight=", // partition CPU weight
512 "partition_active_processors=",
513 "partition_potential_processors=",
514 "entitled_proc_capacity_available=",
515 "capped=", // 0 - uncapped, 1 - vcpus capped at entitled processor capacity percentage
516 "shared_processor_mode=", // (non)dedicated partition
517 "system_potential_processors=",
518 "pool=", // CPU-pool number
519 "pool_capacity=",
520 "NumLpars=", // on non-KVM machines, NumLpars is not found for full partition mode machines
521 NULL };
522 if (!print_matching_lines_from_file(info_file, st, kw)) {
523 st->print_cr(" <%s Not Available>", info_file);
524 }
525 #endif
526 }
527
528 bool VM_Version::use_biased_locking() {
529 #if INCLUDE_RTM_OPT
530 // RTM locking is most useful when there is high lock contention and
531 // low data contention. With high lock contention the lock is usually
532 // inflated and biased locking is not suitable for that case.
533 // RTM locking code requires that biased locking is off.
534 // Note: we can't switch off UseBiasedLocking in get_processor_features()
535 // because it is used by Thread::allocate() which is called before
536 // VM_Version::initialize().
537 if (UseRTMLocking && UseBiasedLocking) {
538 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
539 FLAG_SET_DEFAULT(UseBiasedLocking, false);
540 } else {
541 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
542 UseBiasedLocking = false;
543 }
544 }
545 #endif
546 return UseBiasedLocking;
547 }
548
549 void VM_Version::print_features() {
550 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
551
552 if (Verbose) {
553 if (ContendedPaddingWidth > 0) {
554 tty->cr();
555 tty->print_cr("ContendedPaddingWidth " INTX_FORMAT, ContendedPaddingWidth);
556 }
557 }
558 }
559
560 #ifdef COMPILER2
561 // Determine section size on power6: If section size is 8 instructions,
562 // there should be a difference between the two testloops of ~15 %. If
563 // no difference is detected the section is assumed to be 32 instructions.
564 void VM_Version::determine_section_size() {
565
566 int unroll = 80;
567
568 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
569
570 // Allocate space for the code.
571 ResourceMark rm;
572 CodeBuffer cb("detect_section_size", code_size, 0);
573 MacroAssembler* a = new MacroAssembler(&cb);
574
575 uint32_t *code = (uint32_t *)a->pc();
576 // Emit code.
577 void (*test1)() = (void(*)())(void *)a->function_entry();
578
579 Label l1;
580
581 a->li(R4, 1);
582 a->sldi(R4, R4, 28);
583 a->b(l1);
584 a->align(CodeEntryAlignment);
585
586 a->bind(l1);
587
588 for (int i = 0; i < unroll; i++) {
589 // Schleife 1
590 // ------- sector 0 ------------
591 // ;; 0
592 a->nop(); // 1
593 a->fpnop0(); // 2
594 a->fpnop1(); // 3
595 a->addi(R4,R4, -1); // 4
596
597 // ;; 1
598 a->nop(); // 5
599 a->fmr(F6, F6); // 6
600 a->fmr(F7, F7); // 7
601 a->endgroup(); // 8
602 // ------- sector 8 ------------
603
604 // ;; 2
605 a->nop(); // 9
606 a->nop(); // 10
607 a->fmr(F8, F8); // 11
608 a->fmr(F9, F9); // 12
609
610 // ;; 3
611 a->nop(); // 13
612 a->fmr(F10, F10); // 14
613 a->fmr(F11, F11); // 15
614 a->endgroup(); // 16
615 // -------- sector 16 -------------
616
617 // ;; 4
618 a->nop(); // 17
619 a->nop(); // 18
620 a->fmr(F15, F15); // 19
621 a->fmr(F16, F16); // 20
622
623 // ;; 5
624 a->nop(); // 21
625 a->fmr(F17, F17); // 22
626 a->fmr(F18, F18); // 23
627 a->endgroup(); // 24
628 // ------- sector 24 ------------
629
630 // ;; 6
631 a->nop(); // 25
632 a->nop(); // 26
633 a->fmr(F19, F19); // 27
634 a->fmr(F20, F20); // 28
635
636 // ;; 7
637 a->nop(); // 29
638 a->fmr(F21, F21); // 30
639 a->fmr(F22, F22); // 31
640 a->brnop0(); // 32
641
642 // ------- sector 32 ------------
643 }
644
645 // ;; 8
646 a->cmpdi(CCR0, R4, unroll); // 33
647 a->bge(CCR0, l1); // 34
648 a->blr();
649
650 // Emit code.
651 void (*test2)() = (void(*)())(void *)a->function_entry();
652 // uint32_t *code = (uint32_t *)a->pc();
653
654 Label l2;
655
656 a->li(R4, 1);
657 a->sldi(R4, R4, 28);
658 a->b(l2);
659 a->align(CodeEntryAlignment);
660
661 a->bind(l2);
662
663 for (int i = 0; i < unroll; i++) {
664 // Schleife 2
665 // ------- sector 0 ------------
666 // ;; 0
667 a->brnop0(); // 1
668 a->nop(); // 2
669 //a->cmpdi(CCR0, R4, unroll);
670 a->fpnop0(); // 3
671 a->fpnop1(); // 4
672 a->addi(R4,R4, -1); // 5
673
674 // ;; 1
675
676 a->nop(); // 6
677 a->fmr(F6, F6); // 7
678 a->fmr(F7, F7); // 8
679 // ------- sector 8 ---------------
680
681 // ;; 2
682 a->endgroup(); // 9
683
684 // ;; 3
685 a->nop(); // 10
686 a->nop(); // 11
687 a->fmr(F8, F8); // 12
688
689 // ;; 4
690 a->fmr(F9, F9); // 13
691 a->nop(); // 14
692 a->fmr(F10, F10); // 15
693
694 // ;; 5
695 a->fmr(F11, F11); // 16
696 // -------- sector 16 -------------
697
698 // ;; 6
699 a->endgroup(); // 17
700
701 // ;; 7
702 a->nop(); // 18
703 a->nop(); // 19
704 a->fmr(F15, F15); // 20
705
706 // ;; 8
707 a->fmr(F16, F16); // 21
708 a->nop(); // 22
709 a->fmr(F17, F17); // 23
710
711 // ;; 9
712 a->fmr(F18, F18); // 24
713 // -------- sector 24 -------------
714
715 // ;; 10
716 a->endgroup(); // 25
717
718 // ;; 11
719 a->nop(); // 26
720 a->nop(); // 27
721 a->fmr(F19, F19); // 28
722
723 // ;; 12
724 a->fmr(F20, F20); // 29
725 a->nop(); // 30
726 a->fmr(F21, F21); // 31
727
728 // ;; 13
729 a->fmr(F22, F22); // 32
730 }
731
732 // -------- sector 32 -------------
733 // ;; 14
734 a->cmpdi(CCR0, R4, unroll); // 33
735 a->bge(CCR0, l2); // 34
736
737 a->blr();
738 uint32_t *code_end = (uint32_t *)a->pc();
739 a->flush();
740
741 double loop1_seconds,loop2_seconds, rel_diff;
742 uint64_t start1, stop1;
743
744 start1 = os::current_thread_cpu_time(false);
745 (*test1)();
746 stop1 = os::current_thread_cpu_time(false);
747 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
748
749
750 start1 = os::current_thread_cpu_time(false);
751 (*test2)();
752 stop1 = os::current_thread_cpu_time(false);
753
754 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
755
756 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
757
758 if (PrintAssembly) {
759 ttyLocker ttyl;
760 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
761 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
762 tty->print_cr("Time loop1 :%f", loop1_seconds);
763 tty->print_cr("Time loop2 :%f", loop2_seconds);
764 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
765
766 if (rel_diff > 12.0) {
767 tty->print_cr("Section Size 8 Instructions");
768 } else{
769 tty->print_cr("Section Size 32 Instructions or Power5");
770 }
771 }
772
773 #if 0 // TODO: PPC port
774 // Set sector size (if not set explicitly).
775 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
776 if (rel_diff > 12.0) {
777 PdScheduling::power6SectorSize = 0x20;
778 } else {
779 PdScheduling::power6SectorSize = 0x80;
780 }
781 } else if (Power6SectorSize128PPC64) {
782 PdScheduling::power6SectorSize = 0x80;
783 } else {
784 PdScheduling::power6SectorSize = 0x20;
785 }
786 #endif
787 if (UsePower6SchedulerPPC64) Unimplemented();
788 }
789 #endif // COMPILER2
790
791 void VM_Version::determine_features() {
792 #if defined(ABI_ELFv2)
793 // 1 InstWord per call for the blr instruction.
794 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
795 #else
796 // 7 InstWords for each call (function descriptor + blr instruction).
797 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
798 #endif
799 int features = 0;
800
801 // create test area
802 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
803 char test_area[BUFFER_SIZE];
804 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
805
806 // Allocate space for the code.
807 ResourceMark rm;
808 CodeBuffer cb("detect_cpu_features", code_size, 0);
809 MacroAssembler* a = new MacroAssembler(&cb);
810
811 // Must be set to true so we can generate the test code.
812 _features = VM_Version::all_features_m;
813
814 // Emit code.
815 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
816 uint32_t *code = (uint32_t *)a->pc();
817 // Don't use R0 in ldarx.
818 // Keep R3_ARG1 unmodified, it contains &field (see below).
819 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
820 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
821 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
822 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
823 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
824 a->cmpb(R7, R5, R6); // code[4] -> cmpb
825 a->popcntb(R7, R5); // code[5] -> popcntb
826 a->popcntw(R7, R5); // code[6] -> popcntw
827 a->fcfids(F3, F4); // code[7] -> fcfids
828 a->vand(VR0, VR0, VR0); // code[8] -> vand
829 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
830 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
831 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
832 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
833 a->mfdscr(R0); // code[12] -> mfdscr
834 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
835 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
836 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
837 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
838 // rtm is determined by OS
839 a->darn(R7); // code[17] -> darn
840 a->brw(R5, R6); // code[18] -> brw
841 a->blr();
842
843 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
844 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
845 a->dcbz(R3_ARG1); // R3_ARG1 = addr
846 a->blr();
847
848 uint32_t *code_end = (uint32_t *)a->pc();
849 a->flush();
850 _features = VM_Version::unknown_m;
851
852 // Print the detection code.
853 if (PrintAssembly) {
854 ttyLocker ttyl;
855 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
856 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
857 }
858
859 // Measure cache line size.
860 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
861 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
862 int count = 0; // count zeroed bytes
863 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
864 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
865 _L1_data_cache_line_size = count;
866
867 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
868 VM_Version::_is_determine_features_test_running = true;
869 // We must align the first argument to 16 bytes because of the lqarx check.
870 (*test)(align_up((address)mid_of_test_area, 16), 0);
871 VM_Version::_is_determine_features_test_running = false;
872
873 // determine which instructions are legal.
874 int feature_cntr = 0;
875 if (code[feature_cntr++]) features |= fsqrt_m;
876 if (code[feature_cntr++]) features |= fsqrts_m;
877 if (code[feature_cntr++]) features |= isel_m;
878 if (code[feature_cntr++]) features |= lxarxeh_m;
879 if (code[feature_cntr++]) features |= cmpb_m;
880 if (code[feature_cntr++]) features |= popcntb_m;
881 if (code[feature_cntr++]) features |= popcntw_m;
882 if (code[feature_cntr++]) features |= fcfids_m;
883 if (code[feature_cntr++]) features |= vand_m;
884 if (code[feature_cntr++]) features |= lqarx_m;
885 if (code[feature_cntr++]) features |= vcipher_m;
886 if (code[feature_cntr++]) features |= vpmsumb_m;
887 if (code[feature_cntr++]) features |= mfdscr_m;
888 if (code[feature_cntr++]) features |= vsx_m;
889 if (code[feature_cntr++]) features |= ldbrx_m;
890 if (code[feature_cntr++]) features |= stdbrx_m;
891 if (code[feature_cntr++]) features |= vshasig_m;
892 // feature rtm_m is determined by OS
893 if (code[feature_cntr++]) features |= darn_m;
894 if (code[feature_cntr++]) features |= brw_m;
895
896 // Print the detection code.
897 if (PrintAssembly) {
898 ttyLocker ttyl;
899 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
900 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
901 }
902
903 _features = features;
904
905 #ifdef AIX
906 // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
907 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
908 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
909 // The Java property os.version, which is used in RTM tests to decide
910 // whether the feature is available, only knows major and minor versions.
911 // We don't want to change this property, as user code might depend on it.
912 // So the tests can not check on subversion 3.30, and we only enable RTM
913 // with AIX 7.2.
914 if (has_lqarx()) { // POWER8 or above
915 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
916 _features |= rtm_m;
917 }
918 }
919 #endif
920 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
921 unsigned long auxv = getauxval(AT_HWCAP2);
922
923 if (auxv & PPC_FEATURE2_HTM_NOSC) {
924 if (auxv & PPC_FEATURE2_HAS_HTM) {
925 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
926 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
927 // POWER9 DD2.1 NV has a few issues that need a couple of firmware
928 // and kernel workarounds, so there is a new mode only supported
929 // on non-virtualized P9 machines called HTM with no Suspend Mode).
930 // TM on POWER9 D2.2+ NV is not supported at all by Linux.
931 _features |= rtm_m;
932 }
933 }
934 #endif
935 }
936
937 // Power 8: Configure Data Stream Control Register.
938 void VM_Version::config_dscr() {
939 // 7 InstWords for each call (function descriptor + blr instruction).
940 const int code_size = (2+2*7)*BytesPerInstWord;
941
942 // Allocate space for the code.
943 ResourceMark rm;
944 CodeBuffer cb("config_dscr", code_size, 0);
945 MacroAssembler* a = new MacroAssembler(&cb);
946
947 // Emit code.
948 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
949 uint32_t *code = (uint32_t *)a->pc();
950 a->mfdscr(R3);
951 a->blr();
952
953 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
954 a->mtdscr(R3);
955 a->blr();
956
957 uint32_t *code_end = (uint32_t *)a->pc();
958 a->flush();
959
960 // Print the detection code.
961 if (PrintAssembly) {
962 ttyLocker ttyl;
963 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
964 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
965 }
966
967 // Apply the configuration if needed.
968 _dscr_val = (*get_dscr)();
969 if (Verbose) {
970 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
971 }
972 bool change_requested = false;
973 if (DSCR_PPC64 != (uintx)-1) {
974 _dscr_val = DSCR_PPC64;
975 change_requested = true;
976 }
977 if (DSCR_DPFD_PPC64 <= 7) {
978 uint64_t mask = 0x7;
979 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
980 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
981 change_requested = true;
982 }
983 }
984 if (DSCR_URG_PPC64 <= 7) {
985 uint64_t mask = 0x7 << 6;
986 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
987 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
988 change_requested = true;
989 }
990 }
991 if (change_requested) {
992 (*set_dscr)(_dscr_val);
993 if (Verbose) {
994 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
995 }
996 }
997 }
998
999 static uint64_t saved_features = 0;
1000
1001 void VM_Version::allow_all() {
1002 saved_features = _features;
1003 _features = all_features_m;
1004 }
1005
1006 void VM_Version::revert() {
1007 _features = saved_features;
1008 }