1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
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  24 
  25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "runtime/vm_version.hpp"
  30 
  31 class BiasedLockingCounters;
  32 
  33 // Contains all the definitions needed for x86 assembly code generation.
  34 
  35 // Calling convention
  36 class Argument {
  37  public:
  38   enum {
  39 #ifdef _LP64
  40 #ifdef _WIN64
  41     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  42     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  43 #else
  44     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  45     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  46 #endif // _WIN64
  47     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  48     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  49 #else
  50     n_register_parameters = 0   // 0 registers used to pass arguments
  51 #endif // _LP64
  52   };
  53 };
  54 
  55 
  56 #ifdef _LP64
  57 // Symbolically name the register arguments used by the c calling convention.
  58 // Windows is different from linux/solaris. So much for standards...
  59 
  60 #ifdef _WIN64
  61 
  62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  64 REGISTER_DECLARATION(Register, c_rarg2, r8);
  65 REGISTER_DECLARATION(Register, c_rarg3, r9);
  66 
  67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  71 
  72 #else
  73 
  74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  78 REGISTER_DECLARATION(Register, c_rarg4, r8);
  79 REGISTER_DECLARATION(Register, c_rarg5, r9);
  80 
  81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  89 
  90 #endif // _WIN64
  91 
  92 // Symbolically name the register arguments used by the Java calling convention.
  93 // We have control over the convention for java so we can do what we please.
  94 // What pleases us is to offset the java calling convention so that when
  95 // we call a suitable jni method the arguments are lined up and we don't
  96 // have to do little shuffling. A suitable jni method is non-static and a
  97 // small number of arguments (two fewer args on windows)
  98 //
  99 //        |-------------------------------------------------------|
 100 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
 101 //        |-------------------------------------------------------|
 102 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 103 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 104 //        |-------------------------------------------------------|
 105 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 106 //        |-------------------------------------------------------|
 107 
 108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 111 // Windows runs out of register args here
 112 #ifdef _WIN64
 113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 115 #else
 116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 118 #endif /* _WIN64 */
 119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 120 
 121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 129 
 130 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 131 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 132 
 133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 135 
 136 #else
 137 // rscratch1 will apear in 32bit code that is dead but of course must compile
 138 // Using noreg ensures if the dead code is incorrectly live and executed it
 139 // will cause an assertion failure
 140 #define rscratch1 noreg
 141 #define rscratch2 noreg
 142 
 143 #endif // _LP64
 144 
 145 // JSR 292
 146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
 149 
 150 // Address is an abstraction used to represent a memory location
 151 // using any of the amd64 addressing modes with one object.
 152 //
 153 // Note: A register location is represented via a Register, not
 154 //       via an address for efficiency & simplicity reasons.
 155 
 156 class ArrayAddress;
 157 
 158 class Address {
 159  public:
 160   enum ScaleFactor {
 161     no_scale = -1,
 162     times_1  =  0,
 163     times_2  =  1,
 164     times_4  =  2,
 165     times_8  =  3,
 166     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 167   };
 168   static ScaleFactor times(int size) {
 169     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 170     if (size == 8)  return times_8;
 171     if (size == 4)  return times_4;
 172     if (size == 2)  return times_2;
 173     return times_1;
 174   }
 175   static int scale_size(ScaleFactor scale) {
 176     assert(scale != no_scale, "");
 177     assert(((1 << (int)times_1) == 1 &&
 178             (1 << (int)times_2) == 2 &&
 179             (1 << (int)times_4) == 4 &&
 180             (1 << (int)times_8) == 8), "");
 181     return (1 << (int)scale);
 182   }
 183 
 184  private:
 185   Register         _base;
 186   Register         _index;
 187   XMMRegister      _xmmindex;
 188   ScaleFactor      _scale;
 189   int              _disp;
 190   bool             _isxmmindex;
 191   RelocationHolder _rspec;
 192 
 193   // Easily misused constructors make them private
 194   // %%% can we make these go away?
 195   NOT_LP64(Address(address loc, RelocationHolder spec);)
 196   Address(int disp, address loc, relocInfo::relocType rtype);
 197   Address(int disp, address loc, RelocationHolder spec);
 198 
 199  public:
 200 
 201  int disp() { return _disp; }
 202   // creation
 203   Address()
 204     : _base(noreg),
 205       _index(noreg),
 206       _xmmindex(xnoreg),
 207       _scale(no_scale),
 208       _disp(0),
 209       _isxmmindex(false){
 210   }
 211 
 212   // No default displacement otherwise Register can be implicitly
 213   // converted to 0(Register) which is quite a different animal.
 214 
 215   Address(Register base, int disp)
 216     : _base(base),
 217       _index(noreg),
 218       _xmmindex(xnoreg),
 219       _scale(no_scale),
 220       _disp(disp),
 221       _isxmmindex(false){
 222   }
 223 
 224   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 225     : _base (base),
 226       _index(index),
 227       _xmmindex(xnoreg),
 228       _scale(scale),
 229       _disp (disp),
 230       _isxmmindex(false) {
 231     assert(!index->is_valid() == (scale == Address::no_scale),
 232            "inconsistent address");
 233   }
 234 
 235   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 236     : _base (base),
 237       _index(index.register_or_noreg()),
 238       _xmmindex(xnoreg),
 239       _scale(scale),
 240       _disp (disp + (index.constant_or_zero() * scale_size(scale))),
 241       _isxmmindex(false){
 242     if (!index.is_register())  scale = Address::no_scale;
 243     assert(!_index->is_valid() == (scale == Address::no_scale),
 244            "inconsistent address");
 245   }
 246 
 247   Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
 248     : _base (base),
 249       _index(noreg),
 250       _xmmindex(index),
 251       _scale(scale),
 252       _disp(disp),
 253       _isxmmindex(true) {
 254       assert(!index->is_valid() == (scale == Address::no_scale),
 255              "inconsistent address");
 256   }
 257 
 258   Address plus_disp(int disp) const {
 259     Address a = (*this);
 260     a._disp += disp;
 261     return a;
 262   }
 263   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 264     Address a = (*this);
 265     a._disp += disp.constant_or_zero() * scale_size(scale);
 266     if (disp.is_register()) {
 267       assert(!a.index()->is_valid(), "competing indexes");
 268       a._index = disp.as_register();
 269       a._scale = scale;
 270     }
 271     return a;
 272   }
 273   bool is_same_address(Address a) const {
 274     // disregard _rspec
 275     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 276   }
 277 
 278   // The following two overloads are used in connection with the
 279   // ByteSize type (see sizes.hpp).  They simplify the use of
 280   // ByteSize'd arguments in assembly code. Note that their equivalent
 281   // for the optimized build are the member functions with int disp
 282   // argument since ByteSize is mapped to an int type in that case.
 283   //
 284   // Note: DO NOT introduce similar overloaded functions for WordSize
 285   // arguments as in the optimized mode, both ByteSize and WordSize
 286   // are mapped to the same type and thus the compiler cannot make a
 287   // distinction anymore (=> compiler errors).
 288 
 289 #ifdef ASSERT
 290   Address(Register base, ByteSize disp)
 291     : _base(base),
 292       _index(noreg),
 293       _xmmindex(xnoreg),
 294       _scale(no_scale),
 295       _disp(in_bytes(disp)),
 296       _isxmmindex(false){
 297   }
 298 
 299   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 300     : _base(base),
 301       _index(index),
 302       _xmmindex(xnoreg),
 303       _scale(scale),
 304       _disp(in_bytes(disp)),
 305       _isxmmindex(false){
 306     assert(!index->is_valid() == (scale == Address::no_scale),
 307            "inconsistent address");
 308   }
 309   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 310     : _base (base),
 311       _index(index.register_or_noreg()),
 312       _xmmindex(xnoreg),
 313       _scale(scale),
 314       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))),
 315       _isxmmindex(false) {
 316     if (!index.is_register())  scale = Address::no_scale;
 317     assert(!_index->is_valid() == (scale == Address::no_scale),
 318            "inconsistent address");
 319   }
 320 
 321 #endif // ASSERT
 322 
 323   // accessors
 324   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 325   Register    base()             const { return _base;  }
 326   Register    index()            const { return _index; }
 327   XMMRegister xmmindex()         const { return _xmmindex; }
 328   ScaleFactor scale()            const { return _scale; }
 329   int         disp()             const { return _disp;  }
 330   bool        isxmmindex()       const { return _isxmmindex; }
 331 
 332   // Convert the raw encoding form into the form expected by the constructor for
 333   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 334   // that to noreg for the Address constructor.
 335   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 336 
 337   static Address make_array(ArrayAddress);
 338 
 339  private:
 340   bool base_needs_rex() const {
 341     return _base != noreg && _base->encoding() >= 8;
 342   }
 343 
 344   bool index_needs_rex() const {
 345     return _index != noreg &&_index->encoding() >= 8;
 346   }
 347 
 348   bool xmmindex_needs_rex() const {
 349     return _xmmindex != xnoreg && _xmmindex->encoding() >= 8;
 350   }
 351 
 352   relocInfo::relocType reloc() const { return _rspec.type(); }
 353 
 354   friend class Assembler;
 355   friend class MacroAssembler;
 356   friend class LIR_Assembler; // base/index/scale/disp
 357 };
 358 
 359 //
 360 // AddressLiteral has been split out from Address because operands of this type
 361 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 362 // the few instructions that need to deal with address literals are unique and the
 363 // MacroAssembler does not have to implement every instruction in the Assembler
 364 // in order to search for address literals that may need special handling depending
 365 // on the instruction and the platform. As small step on the way to merging i486/amd64
 366 // directories.
 367 //
 368 class AddressLiteral {
 369   friend class ArrayAddress;
 370   RelocationHolder _rspec;
 371   // Typically we use AddressLiterals we want to use their rval
 372   // However in some situations we want the lval (effect address) of the item.
 373   // We provide a special factory for making those lvals.
 374   bool _is_lval;
 375 
 376   // If the target is far we'll need to load the ea of this to
 377   // a register to reach it. Otherwise if near we can do rip
 378   // relative addressing.
 379 
 380   address          _target;
 381 
 382  protected:
 383   // creation
 384   AddressLiteral()
 385     : _is_lval(false),
 386       _target(NULL)
 387   {}
 388 
 389   public:
 390 
 391 
 392   AddressLiteral(address target, relocInfo::relocType rtype);
 393 
 394   AddressLiteral(address target, RelocationHolder const& rspec)
 395     : _rspec(rspec),
 396       _is_lval(false),
 397       _target(target)
 398   {}
 399 
 400   AddressLiteral addr() {
 401     AddressLiteral ret = *this;
 402     ret._is_lval = true;
 403     return ret;
 404   }
 405 
 406 
 407  private:
 408 
 409   address target() { return _target; }
 410   bool is_lval() { return _is_lval; }
 411 
 412   relocInfo::relocType reloc() const { return _rspec.type(); }
 413   const RelocationHolder& rspec() const { return _rspec; }
 414 
 415   friend class Assembler;
 416   friend class MacroAssembler;
 417   friend class Address;
 418   friend class LIR_Assembler;
 419 };
 420 
 421 // Convience classes
 422 class RuntimeAddress: public AddressLiteral {
 423 
 424   public:
 425 
 426   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 427 
 428 };
 429 
 430 class ExternalAddress: public AddressLiteral {
 431  private:
 432   static relocInfo::relocType reloc_for_target(address target) {
 433     // Sometimes ExternalAddress is used for values which aren't
 434     // exactly addresses, like the card table base.
 435     // external_word_type can't be used for values in the first page
 436     // so just skip the reloc in that case.
 437     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 438   }
 439 
 440  public:
 441 
 442   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 443 
 444 };
 445 
 446 class InternalAddress: public AddressLiteral {
 447 
 448   public:
 449 
 450   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 451 
 452 };
 453 
 454 // x86 can do array addressing as a single operation since disp can be an absolute
 455 // address amd64 can't. We create a class that expresses the concept but does extra
 456 // magic on amd64 to get the final result
 457 
 458 class ArrayAddress {
 459   private:
 460 
 461   AddressLiteral _base;
 462   Address        _index;
 463 
 464   public:
 465 
 466   ArrayAddress() {};
 467   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 468   AddressLiteral base() { return _base; }
 469   Address index() { return _index; }
 470 
 471 };
 472 
 473 class InstructionAttr;
 474 
 475 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
 476 // See fxsave and xsave(EVEX enabled) documentation for layout
 477 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
 478 
 479 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 480 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 481 // is what you get. The Assembler is generating code into a CodeBuffer.
 482 
 483 class Assembler : public AbstractAssembler  {
 484   friend class AbstractAssembler; // for the non-virtual hack
 485   friend class LIR_Assembler; // as_Address()
 486   friend class StubGenerator;
 487 
 488  public:
 489   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 490     zero          = 0x4,
 491     notZero       = 0x5,
 492     equal         = 0x4,
 493     notEqual      = 0x5,
 494     less          = 0xc,
 495     lessEqual     = 0xe,
 496     greater       = 0xf,
 497     greaterEqual  = 0xd,
 498     below         = 0x2,
 499     belowEqual    = 0x6,
 500     above         = 0x7,
 501     aboveEqual    = 0x3,
 502     overflow      = 0x0,
 503     noOverflow    = 0x1,
 504     carrySet      = 0x2,
 505     carryClear    = 0x3,
 506     negative      = 0x8,
 507     positive      = 0x9,
 508     parity        = 0xa,
 509     noParity      = 0xb
 510   };
 511 
 512   enum Prefix {
 513     // segment overrides
 514     CS_segment = 0x2e,
 515     SS_segment = 0x36,
 516     DS_segment = 0x3e,
 517     ES_segment = 0x26,
 518     FS_segment = 0x64,
 519     GS_segment = 0x65,
 520 
 521     REX        = 0x40,
 522 
 523     REX_B      = 0x41,
 524     REX_X      = 0x42,
 525     REX_XB     = 0x43,
 526     REX_R      = 0x44,
 527     REX_RB     = 0x45,
 528     REX_RX     = 0x46,
 529     REX_RXB    = 0x47,
 530 
 531     REX_W      = 0x48,
 532 
 533     REX_WB     = 0x49,
 534     REX_WX     = 0x4A,
 535     REX_WXB    = 0x4B,
 536     REX_WR     = 0x4C,
 537     REX_WRB    = 0x4D,
 538     REX_WRX    = 0x4E,
 539     REX_WRXB   = 0x4F,
 540 
 541     VEX_3bytes = 0xC4,
 542     VEX_2bytes = 0xC5,
 543     EVEX_4bytes = 0x62,
 544     Prefix_EMPTY = 0x0
 545   };
 546 
 547   enum VexPrefix {
 548     VEX_B = 0x20,
 549     VEX_X = 0x40,
 550     VEX_R = 0x80,
 551     VEX_W = 0x80
 552   };
 553 
 554   enum ExexPrefix {
 555     EVEX_F  = 0x04,
 556     EVEX_V  = 0x08,
 557     EVEX_Rb = 0x10,
 558     EVEX_X  = 0x40,
 559     EVEX_Z  = 0x80
 560   };
 561 
 562   enum VexSimdPrefix {
 563     VEX_SIMD_NONE = 0x0,
 564     VEX_SIMD_66   = 0x1,
 565     VEX_SIMD_F3   = 0x2,
 566     VEX_SIMD_F2   = 0x3
 567   };
 568 
 569   enum VexOpcode {
 570     VEX_OPCODE_NONE  = 0x0,
 571     VEX_OPCODE_0F    = 0x1,
 572     VEX_OPCODE_0F_38 = 0x2,
 573     VEX_OPCODE_0F_3A = 0x3,
 574     VEX_OPCODE_MASK  = 0x1F
 575   };
 576 
 577   enum AvxVectorLen {
 578     AVX_128bit = 0x0,
 579     AVX_256bit = 0x1,
 580     AVX_512bit = 0x2,
 581     AVX_NoVec  = 0x4
 582   };
 583 
 584   enum EvexTupleType {
 585     EVEX_FV   = 0,
 586     EVEX_HV   = 4,
 587     EVEX_FVM  = 6,
 588     EVEX_T1S  = 7,
 589     EVEX_T1F  = 11,
 590     EVEX_T2   = 13,
 591     EVEX_T4   = 15,
 592     EVEX_T8   = 17,
 593     EVEX_HVM  = 18,
 594     EVEX_QVM  = 19,
 595     EVEX_OVM  = 20,
 596     EVEX_M128 = 21,
 597     EVEX_DUP  = 22,
 598     EVEX_ETUP = 23
 599   };
 600 
 601   enum EvexInputSizeInBits {
 602     EVEX_8bit  = 0,
 603     EVEX_16bit = 1,
 604     EVEX_32bit = 2,
 605     EVEX_64bit = 3,
 606     EVEX_NObit = 4
 607   };
 608 
 609   enum WhichOperand {
 610     // input to locate_operand, and format code for relocations
 611     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 612     disp32_operand = 1,          // embedded 32-bit displacement or address
 613     call32_operand = 2,          // embedded 32-bit self-relative displacement
 614 #ifndef _LP64
 615     _WhichOperand_limit = 3
 616 #else
 617      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 618     _WhichOperand_limit = 4
 619 #endif
 620   };
 621 
 622   enum ComparisonPredicate {
 623     eq = 0,
 624     lt = 1,
 625     le = 2,
 626     _false = 3,
 627     neq = 4,
 628     nlt = 5,
 629     nle = 6,
 630     _true = 7
 631   };
 632 
 633 
 634   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 635   // of instructions are freely declared without the need for wrapping them an ifdef.
 636   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 637   // In the .cpp file the implementations are wrapped so that they are dropped out
 638   // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
 639   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 640   //
 641   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 642   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 643 
 644 private:
 645 
 646   bool _legacy_mode_bw;
 647   bool _legacy_mode_dq;
 648   bool _legacy_mode_vl;
 649   bool _legacy_mode_vlbw;
 650   bool _is_managed;
 651   bool _vector_masking;    // For stub code use only
 652 
 653   class InstructionAttr *_attributes;
 654 
 655   // 64bit prefixes
 656   int prefix_and_encode(int reg_enc, bool byteinst = false);
 657   int prefixq_and_encode(int reg_enc);
 658 
 659   int prefix_and_encode(int dst_enc, int src_enc) {
 660     return prefix_and_encode(dst_enc, false, src_enc, false);
 661   }
 662   int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
 663   int prefixq_and_encode(int dst_enc, int src_enc);
 664 
 665   void prefix(Register reg);
 666   void prefix(Register dst, Register src, Prefix p);
 667   void prefix(Register dst, Address adr, Prefix p);
 668   void prefix(Address adr);
 669   void prefixq(Address adr);
 670 
 671   void prefix(Address adr, Register reg,  bool byteinst = false);
 672   void prefix(Address adr, XMMRegister reg);
 673   void prefixq(Address adr, Register reg);
 674   void prefixq(Address adr, XMMRegister reg);
 675 
 676   void prefetch_prefix(Address src);
 677 
 678   void rex_prefix(Address adr, XMMRegister xreg,
 679                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 680   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 681                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 682 
 683   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 684 
 685   void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
 686                    int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 687 
 688   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 689                   VexSimdPrefix pre, VexOpcode opc,
 690                   InstructionAttr *attributes);
 691 
 692   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 693                              VexSimdPrefix pre, VexOpcode opc,
 694                              InstructionAttr *attributes);
 695 
 696   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
 697                    VexOpcode opc, InstructionAttr *attributes);
 698 
 699   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
 700                              VexOpcode opc, InstructionAttr *attributes);
 701 
 702   // Helper functions for groups of instructions
 703   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 704 
 705   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 706   // Force generation of a 4 byte immediate value even if it fits into 8bit
 707   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 708   void emit_arith(int op1, int op2, Register dst, Register src);
 709 
 710   bool emit_compressed_disp_byte(int &disp);
 711 
 712   void emit_operand(Register reg,
 713                     Register base, Register index, Address::ScaleFactor scale,
 714                     int disp,
 715                     RelocationHolder const& rspec,
 716                     int rip_relative_correction = 0);
 717 
 718   void emit_operand(XMMRegister reg, Register base, XMMRegister index,
 719                     Address::ScaleFactor scale,
 720                     int disp, RelocationHolder const& rspec);
 721 
 722   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 723 
 724   // operands that only take the original 32bit registers
 725   void emit_operand32(Register reg, Address adr);
 726 
 727   void emit_operand(XMMRegister reg,
 728                     Register base, Register index, Address::ScaleFactor scale,
 729                     int disp,
 730                     RelocationHolder const& rspec);
 731 
 732   void emit_operand(XMMRegister reg, Address adr);
 733 
 734   void emit_operand(MMXRegister reg, Address adr);
 735 
 736   // workaround gcc (3.2.1-7) bug
 737   void emit_operand(Address adr, MMXRegister reg);
 738 
 739 
 740   // Immediate-to-memory forms
 741   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 742 
 743   void emit_farith(int b1, int b2, int i);
 744 
 745 
 746  protected:
 747   #ifdef ASSERT
 748   void check_relocation(RelocationHolder const& rspec, int format);
 749   #endif
 750 
 751   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 752   void emit_data(jint data, RelocationHolder const& rspec, int format);
 753   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 754   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 755 
 756   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 757 
 758   // These are all easily abused and hence protected
 759 
 760   // 32BIT ONLY SECTION
 761 #ifndef _LP64
 762   // Make these disappear in 64bit mode since they would never be correct
 763   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 764   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 765 
 766   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 767   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 768 
 769   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 770 #else
 771   // 64BIT ONLY SECTION
 772   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 773 
 774   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 775   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 776 
 777   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 778   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 779 #endif // _LP64
 780 
 781   // These are unique in that we are ensured by the caller that the 32bit
 782   // relative in these instructions will always be able to reach the potentially
 783   // 64bit address described by entry. Since they can take a 64bit address they
 784   // don't have the 32 suffix like the other instructions in this class.
 785 
 786   void call_literal(address entry, RelocationHolder const& rspec);
 787   void jmp_literal(address entry, RelocationHolder const& rspec);
 788 
 789   // Avoid using directly section
 790   // Instructions in this section are actually usable by anyone without danger
 791   // of failure but have performance issues that are addressed my enhanced
 792   // instructions which will do the proper thing base on the particular cpu.
 793   // We protect them because we don't trust you...
 794 
 795   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 796   // could cause a partial flag stall since they don't set CF flag.
 797   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 798   // which call inc() & dec() or add() & sub() in accordance with
 799   // the product flag UseIncDec value.
 800 
 801   void decl(Register dst);
 802   void decl(Address dst);
 803   void decq(Register dst);
 804   void decq(Address dst);
 805 
 806   void incl(Register dst);
 807   void incl(Address dst);
 808   void incq(Register dst);
 809   void incq(Address dst);
 810 
 811   // New cpus require use of movsd and movss to avoid partial register stall
 812   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 813   // The selection is done in MacroAssembler::movdbl() and movflt().
 814 
 815   // Move Scalar Single-Precision Floating-Point Values
 816   void movss(XMMRegister dst, Address src);
 817   void movss(XMMRegister dst, XMMRegister src);
 818   void movss(Address dst, XMMRegister src);
 819 
 820   // Move Scalar Double-Precision Floating-Point Values
 821   void movsd(XMMRegister dst, Address src);
 822   void movsd(XMMRegister dst, XMMRegister src);
 823   void movsd(Address dst, XMMRegister src);
 824   void movlpd(XMMRegister dst, Address src);
 825 
 826   // New cpus require use of movaps and movapd to avoid partial register stall
 827   // when moving between registers.
 828   void movaps(XMMRegister dst, XMMRegister src);
 829   void movapd(XMMRegister dst, XMMRegister src);
 830 
 831   // End avoid using directly
 832 
 833 
 834   // Instruction prefixes
 835   void prefix(Prefix p);
 836 
 837   public:
 838 
 839   // Creation
 840   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
 841     init_attributes();
 842   }
 843 
 844   // Decoding
 845   static address locate_operand(address inst, WhichOperand which);
 846   static address locate_next_instruction(address inst);
 847 
 848   // Utilities
 849   static bool is_polling_page_far() NOT_LP64({ return false;});
 850   static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
 851                                          int cur_tuple_type, int in_size_in_bits, int cur_encoding);
 852 
 853   // Generic instructions
 854   // Does 32bit or 64bit as needed for the platform. In some sense these
 855   // belong in macro assembler but there is no need for both varieties to exist
 856 
 857   void init_attributes(void) {
 858     _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
 859     _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
 860     _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
 861     _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
 862     _is_managed = false;
 863     _vector_masking = false;
 864     _attributes = NULL;
 865   }
 866 
 867   void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
 868   void clear_attributes(void) { _attributes = NULL; }
 869 
 870   void set_managed(void) { _is_managed = true; }
 871   void clear_managed(void) { _is_managed = false; }
 872   bool is_managed(void) { return _is_managed; }
 873 
 874   void lea(Register dst, Address src);
 875 
 876   void mov(Register dst, Register src);
 877 
 878   void pusha();
 879   void popa();
 880 
 881   void pushf();
 882   void popf();
 883 
 884   void push(int32_t imm32);
 885 
 886   void push(Register src);
 887 
 888   void pop(Register dst);
 889 
 890   // These are dummies to prevent surprise implicit conversions to Register
 891   void push(void* v);
 892   void pop(void* v);
 893 
 894   // These do register sized moves/scans
 895   void rep_mov();
 896   void rep_stos();
 897   void rep_stosb();
 898   void repne_scan();
 899 #ifdef _LP64
 900   void repne_scanl();
 901 #endif
 902 
 903   // Vanilla instructions in lexical order
 904 
 905   void adcl(Address dst, int32_t imm32);
 906   void adcl(Address dst, Register src);
 907   void adcl(Register dst, int32_t imm32);
 908   void adcl(Register dst, Address src);
 909   void adcl(Register dst, Register src);
 910 
 911   void adcq(Register dst, int32_t imm32);
 912   void adcq(Register dst, Address src);
 913   void adcq(Register dst, Register src);
 914 
 915   void addb(Address dst, int imm8);
 916   void addw(Address dst, int imm16);
 917 
 918   void addl(Address dst, int32_t imm32);
 919   void addl(Address dst, Register src);
 920   void addl(Register dst, int32_t imm32);
 921   void addl(Register dst, Address src);
 922   void addl(Register dst, Register src);
 923 
 924   void addq(Address dst, int32_t imm32);
 925   void addq(Address dst, Register src);
 926   void addq(Register dst, int32_t imm32);
 927   void addq(Register dst, Address src);
 928   void addq(Register dst, Register src);
 929 
 930 #ifdef _LP64
 931  //Add Unsigned Integers with Carry Flag
 932   void adcxq(Register dst, Register src);
 933 
 934  //Add Unsigned Integers with Overflow Flag
 935   void adoxq(Register dst, Register src);
 936 #endif
 937 
 938   void addr_nop_4();
 939   void addr_nop_5();
 940   void addr_nop_7();
 941   void addr_nop_8();
 942 
 943   // Add Scalar Double-Precision Floating-Point Values
 944   void addsd(XMMRegister dst, Address src);
 945   void addsd(XMMRegister dst, XMMRegister src);
 946 
 947   // Add Scalar Single-Precision Floating-Point Values
 948   void addss(XMMRegister dst, Address src);
 949   void addss(XMMRegister dst, XMMRegister src);
 950 
 951   // AES instructions
 952   void aesdec(XMMRegister dst, Address src);
 953   void aesdec(XMMRegister dst, XMMRegister src);
 954   void aesdeclast(XMMRegister dst, Address src);
 955   void aesdeclast(XMMRegister dst, XMMRegister src);
 956   void aesenc(XMMRegister dst, Address src);
 957   void aesenc(XMMRegister dst, XMMRegister src);
 958   void aesenclast(XMMRegister dst, Address src);
 959   void aesenclast(XMMRegister dst, XMMRegister src);
 960   // Vector AES instructions
 961   void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 962   void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 963   void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 964   void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 965 
 966   void andl(Address  dst, int32_t imm32);
 967   void andl(Register dst, int32_t imm32);
 968   void andl(Register dst, Address src);
 969   void andl(Register dst, Register src);
 970 
 971   void andq(Address  dst, int32_t imm32);
 972   void andq(Register dst, int32_t imm32);
 973   void andq(Register dst, Address src);
 974   void andq(Register dst, Register src);
 975 
 976   // BMI instructions
 977   void andnl(Register dst, Register src1, Register src2);
 978   void andnl(Register dst, Register src1, Address src2);
 979   void andnq(Register dst, Register src1, Register src2);
 980   void andnq(Register dst, Register src1, Address src2);
 981 
 982   void blsil(Register dst, Register src);
 983   void blsil(Register dst, Address src);
 984   void blsiq(Register dst, Register src);
 985   void blsiq(Register dst, Address src);
 986 
 987   void blsmskl(Register dst, Register src);
 988   void blsmskl(Register dst, Address src);
 989   void blsmskq(Register dst, Register src);
 990   void blsmskq(Register dst, Address src);
 991 
 992   void blsrl(Register dst, Register src);
 993   void blsrl(Register dst, Address src);
 994   void blsrq(Register dst, Register src);
 995   void blsrq(Register dst, Address src);
 996 
 997   void bsfl(Register dst, Register src);
 998   void bsrl(Register dst, Register src);
 999 
1000 #ifdef _LP64
1001   void bsfq(Register dst, Register src);
1002   void bsrq(Register dst, Register src);
1003 #endif
1004 
1005   void bswapl(Register reg);
1006 
1007   void bswapq(Register reg);
1008 
1009   void call(Label& L, relocInfo::relocType rtype);
1010   void call(Register reg);  // push pc; pc <- reg
1011   void call(Address adr);   // push pc; pc <- adr
1012 
1013   void cdql();
1014 
1015   void cdqq();
1016 
1017   void cld();
1018 
1019   void clflush(Address adr);
1020 
1021   void cmovl(Condition cc, Register dst, Register src);
1022   void cmovl(Condition cc, Register dst, Address src);
1023 
1024   void cmovq(Condition cc, Register dst, Register src);
1025   void cmovq(Condition cc, Register dst, Address src);
1026 
1027 
1028   void cmpb(Address dst, int imm8);
1029 
1030   void cmpl(Address dst, int32_t imm32);
1031 
1032   void cmpl(Register dst, int32_t imm32);
1033   void cmpl(Register dst, Register src);
1034   void cmpl(Register dst, Address src);
1035 
1036   void cmpq(Address dst, int32_t imm32);
1037   void cmpq(Address dst, Register src);
1038 
1039   void cmpq(Register dst, int32_t imm32);
1040   void cmpq(Register dst, Register src);
1041   void cmpq(Register dst, Address src);
1042 
1043   // these are dummies used to catch attempting to convert NULL to Register
1044   void cmpl(Register dst, void* junk); // dummy
1045   void cmpq(Register dst, void* junk); // dummy
1046 
1047   void cmpw(Address dst, int imm16);
1048 
1049   void cmpxchg8 (Address adr);
1050 
1051   void cmpxchgb(Register reg, Address adr);
1052   void cmpxchgl(Register reg, Address adr);
1053 
1054   void cmpxchgq(Register reg, Address adr);
1055 
1056   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1057   void comisd(XMMRegister dst, Address src);
1058   void comisd(XMMRegister dst, XMMRegister src);
1059 
1060   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1061   void comiss(XMMRegister dst, Address src);
1062   void comiss(XMMRegister dst, XMMRegister src);
1063 
1064   // Identify processor type and features
1065   void cpuid();
1066 
1067   // CRC32C
1068   void crc32(Register crc, Register v, int8_t sizeInBytes);
1069   void crc32(Register crc, Address adr, int8_t sizeInBytes);
1070 
1071   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1072   void cvtsd2ss(XMMRegister dst, XMMRegister src);
1073   void cvtsd2ss(XMMRegister dst, Address src);
1074 
1075   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1076   void cvtsi2sdl(XMMRegister dst, Register src);
1077   void cvtsi2sdl(XMMRegister dst, Address src);
1078   void cvtsi2sdq(XMMRegister dst, Register src);
1079   void cvtsi2sdq(XMMRegister dst, Address src);
1080 
1081   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1082   void cvtsi2ssl(XMMRegister dst, Register src);
1083   void cvtsi2ssl(XMMRegister dst, Address src);
1084   void cvtsi2ssq(XMMRegister dst, Register src);
1085   void cvtsi2ssq(XMMRegister dst, Address src);
1086 
1087   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1088   void cvtdq2pd(XMMRegister dst, XMMRegister src);
1089 
1090   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1091   void cvtdq2ps(XMMRegister dst, XMMRegister src);
1092 
1093   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1094   void cvtss2sd(XMMRegister dst, XMMRegister src);
1095   void cvtss2sd(XMMRegister dst, Address src);
1096 
1097   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1098   void cvttsd2sil(Register dst, Address src);
1099   void cvttsd2sil(Register dst, XMMRegister src);
1100   void cvttsd2siq(Register dst, XMMRegister src);
1101 
1102   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1103   void cvttss2sil(Register dst, XMMRegister src);
1104   void cvttss2siq(Register dst, XMMRegister src);
1105 
1106   void cvttpd2dq(XMMRegister dst, XMMRegister src);
1107 
1108   //Abs of packed Integer values
1109   void pabsb(XMMRegister dst, XMMRegister src);
1110   void pabsw(XMMRegister dst, XMMRegister src);
1111   void pabsd(XMMRegister dst, XMMRegister src);
1112   void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1113   void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1114   void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1115   void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);
1116 
1117   // Divide Scalar Double-Precision Floating-Point Values
1118   void divsd(XMMRegister dst, Address src);
1119   void divsd(XMMRegister dst, XMMRegister src);
1120 
1121   // Divide Scalar Single-Precision Floating-Point Values
1122   void divss(XMMRegister dst, Address src);
1123   void divss(XMMRegister dst, XMMRegister src);
1124 
1125   void emms();
1126 
1127   void fabs();
1128 
1129   void fadd(int i);
1130 
1131   void fadd_d(Address src);
1132   void fadd_s(Address src);
1133 
1134   // "Alternate" versions of x87 instructions place result down in FPU
1135   // stack instead of on TOS
1136 
1137   void fadda(int i); // "alternate" fadd
1138   void faddp(int i = 1);
1139 
1140   void fchs();
1141 
1142   void fcom(int i);
1143 
1144   void fcomp(int i = 1);
1145   void fcomp_d(Address src);
1146   void fcomp_s(Address src);
1147 
1148   void fcompp();
1149 
1150   void fcos();
1151 
1152   void fdecstp();
1153 
1154   void fdiv(int i);
1155   void fdiv_d(Address src);
1156   void fdivr_s(Address src);
1157   void fdiva(int i);  // "alternate" fdiv
1158   void fdivp(int i = 1);
1159 
1160   void fdivr(int i);
1161   void fdivr_d(Address src);
1162   void fdiv_s(Address src);
1163 
1164   void fdivra(int i); // "alternate" reversed fdiv
1165 
1166   void fdivrp(int i = 1);
1167 
1168   void ffree(int i = 0);
1169 
1170   void fild_d(Address adr);
1171   void fild_s(Address adr);
1172 
1173   void fincstp();
1174 
1175   void finit();
1176 
1177   void fist_s (Address adr);
1178   void fistp_d(Address adr);
1179   void fistp_s(Address adr);
1180 
1181   void fld1();
1182 
1183   void fld_d(Address adr);
1184   void fld_s(Address adr);
1185   void fld_s(int index);
1186   void fld_x(Address adr);  // extended-precision (80-bit) format
1187 
1188   void fldcw(Address src);
1189 
1190   void fldenv(Address src);
1191 
1192   void fldlg2();
1193 
1194   void fldln2();
1195 
1196   void fldz();
1197 
1198   void flog();
1199   void flog10();
1200 
1201   void fmul(int i);
1202 
1203   void fmul_d(Address src);
1204   void fmul_s(Address src);
1205 
1206   void fmula(int i);  // "alternate" fmul
1207 
1208   void fmulp(int i = 1);
1209 
1210   void fnsave(Address dst);
1211 
1212   void fnstcw(Address src);
1213 
1214   void fnstsw_ax();
1215 
1216   void fprem();
1217   void fprem1();
1218 
1219   void frstor(Address src);
1220 
1221   void fsin();
1222 
1223   void fsqrt();
1224 
1225   void fst_d(Address adr);
1226   void fst_s(Address adr);
1227 
1228   void fstp_d(Address adr);
1229   void fstp_d(int index);
1230   void fstp_s(Address adr);
1231   void fstp_x(Address adr); // extended-precision (80-bit) format
1232 
1233   void fsub(int i);
1234   void fsub_d(Address src);
1235   void fsub_s(Address src);
1236 
1237   void fsuba(int i);  // "alternate" fsub
1238 
1239   void fsubp(int i = 1);
1240 
1241   void fsubr(int i);
1242   void fsubr_d(Address src);
1243   void fsubr_s(Address src);
1244 
1245   void fsubra(int i); // "alternate" reversed fsub
1246 
1247   void fsubrp(int i = 1);
1248 
1249   void ftan();
1250 
1251   void ftst();
1252 
1253   void fucomi(int i = 1);
1254   void fucomip(int i = 1);
1255 
1256   void fwait();
1257 
1258   void fxch(int i = 1);
1259 
1260   void fxrstor(Address src);
1261   void xrstor(Address src);
1262 
1263   void fxsave(Address dst);
1264   void xsave(Address dst);
1265 
1266   void fyl2x();
1267   void frndint();
1268   void f2xm1();
1269   void fldl2e();
1270 
1271   void hlt();
1272 
1273   void idivl(Register src);
1274   void divl(Register src); // Unsigned division
1275 
1276 #ifdef _LP64
1277   void idivq(Register src);
1278 #endif
1279 
1280   void imull(Register src);
1281   void imull(Register dst, Register src);
1282   void imull(Register dst, Register src, int value);
1283   void imull(Register dst, Address src);
1284 
1285 #ifdef _LP64
1286   void imulq(Register dst, Register src);
1287   void imulq(Register dst, Register src, int value);
1288   void imulq(Register dst, Address src);
1289 #endif
1290 
1291   // jcc is the generic conditional branch generator to run-
1292   // time routines, jcc is used for branches to labels. jcc
1293   // takes a branch opcode (cc) and a label (L) and generates
1294   // either a backward branch or a forward branch and links it
1295   // to the label fixup chain. Usage:
1296   //
1297   // Label L;      // unbound label
1298   // jcc(cc, L);   // forward branch to unbound label
1299   // bind(L);      // bind label to the current pc
1300   // jcc(cc, L);   // backward branch to bound label
1301   // bind(L);      // illegal: a label may be bound only once
1302   //
1303   // Note: The same Label can be used for forward and backward branches
1304   // but it may be bound only once.
1305 
1306   void jcc(Condition cc, Label& L, bool maybe_short = true);
1307 
1308   // Conditional jump to a 8-bit offset to L.
1309   // WARNING: be very careful using this for forward jumps.  If the label is
1310   // not bound within an 8-bit offset of this instruction, a run-time error
1311   // will occur.
1312   void jccb(Condition cc, Label& L);
1313 
1314   void jmp(Address entry);    // pc <- entry
1315 
1316   // Label operations & relative jumps (PPUM Appendix D)
1317   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1318 
1319   void jmp(Register entry); // pc <- entry
1320 
1321   // Unconditional 8-bit offset jump to L.
1322   // WARNING: be very careful using this for forward jumps.  If the label is
1323   // not bound within an 8-bit offset of this instruction, a run-time error
1324   // will occur.
1325   void jmpb(Label& L);
1326 
1327   void ldmxcsr( Address src );
1328 
1329   void leal(Register dst, Address src);
1330 
1331   void leaq(Register dst, Address src);
1332 
1333   void lfence();
1334 
1335   void lock();
1336 
1337   void lzcntl(Register dst, Register src);
1338 
1339 #ifdef _LP64
1340   void lzcntq(Register dst, Register src);
1341 #endif
1342 
1343   enum Membar_mask_bits {
1344     StoreStore = 1 << 3,
1345     LoadStore  = 1 << 2,
1346     StoreLoad  = 1 << 1,
1347     LoadLoad   = 1 << 0
1348   };
1349 
1350   // Serializes memory and blows flags
1351   void membar(Membar_mask_bits order_constraint) {
1352     if (os::is_MP()) {
1353       // We only have to handle StoreLoad
1354       if (order_constraint & StoreLoad) {
1355         // All usable chips support "locked" instructions which suffice
1356         // as barriers, and are much faster than the alternative of
1357         // using cpuid instruction. We use here a locked add [esp-C],0.
1358         // This is conveniently otherwise a no-op except for blowing
1359         // flags, and introducing a false dependency on target memory
1360         // location. We can't do anything with flags, but we can avoid
1361         // memory dependencies in the current method by locked-adding
1362         // somewhere else on the stack. Doing [esp+C] will collide with
1363         // something on stack in current method, hence we go for [esp-C].
1364         // It is convenient since it is almost always in data cache, for
1365         // any small C.  We need to step back from SP to avoid data
1366         // dependencies with other things on below SP (callee-saves, for
1367         // example). Without a clear way to figure out the minimal safe
1368         // distance from SP, it makes sense to step back the complete
1369         // cache line, as this will also avoid possible second-order effects
1370         // with locked ops against the cache line. Our choice of offset
1371         // is bounded by x86 operand encoding, which should stay within
1372         // [-128; +127] to have the 8-byte displacement encoding.
1373         //
1374         // Any change to this code may need to revisit other places in
1375         // the code where this idiom is used, in particular the
1376         // orderAccess code.
1377 
1378         int offset = -VM_Version::L1_line_size();
1379         if (offset < -128) {
1380           offset = -128;
1381         }
1382 
1383         lock();
1384         addl(Address(rsp, offset), 0);// Assert the lock# signal here
1385       }
1386     }
1387   }
1388 
1389   void mfence();
1390 
1391   // Moves
1392 
1393   void mov64(Register dst, int64_t imm64);
1394 
1395   void movb(Address dst, Register src);
1396   void movb(Address dst, int imm8);
1397   void movb(Register dst, Address src);
1398 
1399   void movddup(XMMRegister dst, XMMRegister src);
1400 
1401   void kmovbl(KRegister dst, Register src);
1402   void kmovbl(Register dst, KRegister src);
1403   void kmovwl(KRegister dst, Register src);
1404   void kmovwl(KRegister dst, Address src);
1405   void kmovwl(Register dst, KRegister src);
1406   void kmovdl(KRegister dst, Register src);
1407   void kmovdl(Register dst, KRegister src);
1408   void kmovql(KRegister dst, KRegister src);
1409   void kmovql(Address dst, KRegister src);
1410   void kmovql(KRegister dst, Address src);
1411   void kmovql(KRegister dst, Register src);
1412   void kmovql(Register dst, KRegister src);
1413 
1414   void knotwl(KRegister dst, KRegister src);
1415 
1416   void kortestbl(KRegister dst, KRegister src);
1417   void kortestwl(KRegister dst, KRegister src);
1418   void kortestdl(KRegister dst, KRegister src);
1419   void kortestql(KRegister dst, KRegister src);
1420 
1421   void ktestq(KRegister src1, KRegister src2);
1422   void ktestd(KRegister src1, KRegister src2);
1423 
1424   void ktestql(KRegister dst, KRegister src);
1425 
1426   void movdl(XMMRegister dst, Register src);
1427   void movdl(Register dst, XMMRegister src);
1428   void movdl(XMMRegister dst, Address src);
1429   void movdl(Address dst, XMMRegister src);
1430 
1431   // Move Double Quadword
1432   void movdq(XMMRegister dst, Register src);
1433   void movdq(Register dst, XMMRegister src);
1434 
1435   // Move Aligned Double Quadword
1436   void movdqa(XMMRegister dst, XMMRegister src);
1437   void movdqa(XMMRegister dst, Address src);
1438 
1439   // Move Unaligned Double Quadword
1440   void movdqu(Address     dst, XMMRegister src);
1441   void movdqu(XMMRegister dst, Address src);
1442   void movdqu(XMMRegister dst, XMMRegister src);
1443 
1444   // Move Unaligned 256bit Vector
1445   void vmovdqu(Address dst, XMMRegister src);
1446   void vmovdqu(XMMRegister dst, Address src);
1447   void vmovdqu(XMMRegister dst, XMMRegister src);
1448 
1449    // Move Unaligned 512bit Vector
1450   void evmovdqub(Address dst, XMMRegister src, int vector_len);
1451   void evmovdqub(XMMRegister dst, Address src, int vector_len);
1452   void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len);
1453   void evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len);
1454   void evmovdquw(Address dst, XMMRegister src, int vector_len);
1455   void evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len);
1456   void evmovdquw(XMMRegister dst, Address src, int vector_len);
1457   void evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1458   void evmovdqul(Address dst, XMMRegister src, int vector_len);
1459   void evmovdqul(XMMRegister dst, Address src, int vector_len);
1460   void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1461   void evmovdquq(Address dst, XMMRegister src, int vector_len);
1462   void evmovdquq(XMMRegister dst, Address src, int vector_len);
1463   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1464 
1465   // Move lower 64bit to high 64bit in 128bit register
1466   void movlhps(XMMRegister dst, XMMRegister src);
1467 
1468   void movl(Register dst, int32_t imm32);
1469   void movl(Address dst, int32_t imm32);
1470   void movl(Register dst, Register src);
1471   void movl(Register dst, Address src);
1472   void movl(Address dst, Register src);
1473 
1474   // These dummies prevent using movl from converting a zero (like NULL) into Register
1475   // by giving the compiler two choices it can't resolve
1476 
1477   void movl(Address  dst, void* junk);
1478   void movl(Register dst, void* junk);
1479 
1480 #ifdef _LP64
1481   void movq(Register dst, Register src);
1482   void movq(Register dst, Address src);
1483   void movq(Address  dst, Register src);
1484 #endif
1485 
1486   void movq(Address     dst, MMXRegister src );
1487   void movq(MMXRegister dst, Address src );
1488 
1489 #ifdef _LP64
1490   // These dummies prevent using movq from converting a zero (like NULL) into Register
1491   // by giving the compiler two choices it can't resolve
1492 
1493   void movq(Address  dst, void* dummy);
1494   void movq(Register dst, void* dummy);
1495 #endif
1496 
1497   // Move Quadword
1498   void movq(Address     dst, XMMRegister src);
1499   void movq(XMMRegister dst, Address src);
1500 
1501   void movsbl(Register dst, Address src);
1502   void movsbl(Register dst, Register src);
1503 
1504 #ifdef _LP64
1505   void movsbq(Register dst, Address src);
1506   void movsbq(Register dst, Register src);
1507 
1508   // Move signed 32bit immediate to 64bit extending sign
1509   void movslq(Address  dst, int32_t imm64);
1510   void movslq(Register dst, int32_t imm64);
1511 
1512   void movslq(Register dst, Address src);
1513   void movslq(Register dst, Register src);
1514   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1515 #endif
1516 
1517   void movswl(Register dst, Address src);
1518   void movswl(Register dst, Register src);
1519 
1520 #ifdef _LP64
1521   void movswq(Register dst, Address src);
1522   void movswq(Register dst, Register src);
1523 #endif
1524 
1525   void movw(Address dst, int imm16);
1526   void movw(Register dst, Address src);
1527   void movw(Address dst, Register src);
1528 
1529   void movzbl(Register dst, Address src);
1530   void movzbl(Register dst, Register src);
1531 
1532 #ifdef _LP64
1533   void movzbq(Register dst, Address src);
1534   void movzbq(Register dst, Register src);
1535 #endif
1536 
1537   void movzwl(Register dst, Address src);
1538   void movzwl(Register dst, Register src);
1539 
1540 #ifdef _LP64
1541   void movzwq(Register dst, Address src);
1542   void movzwq(Register dst, Register src);
1543 #endif
1544 
1545   // Unsigned multiply with RAX destination register
1546   void mull(Address src);
1547   void mull(Register src);
1548 
1549 #ifdef _LP64
1550   void mulq(Address src);
1551   void mulq(Register src);
1552   void mulxq(Register dst1, Register dst2, Register src);
1553 #endif
1554 
1555   // Multiply Scalar Double-Precision Floating-Point Values
1556   void mulsd(XMMRegister dst, Address src);
1557   void mulsd(XMMRegister dst, XMMRegister src);
1558 
1559   // Multiply Scalar Single-Precision Floating-Point Values
1560   void mulss(XMMRegister dst, Address src);
1561   void mulss(XMMRegister dst, XMMRegister src);
1562 
1563   void negl(Register dst);
1564 
1565 #ifdef _LP64
1566   void negq(Register dst);
1567 #endif
1568 
1569   void nop(int i = 1);
1570 
1571   void notl(Register dst);
1572 
1573 #ifdef _LP64
1574   void notq(Register dst);
1575 #endif
1576 
1577   void orl(Address dst, int32_t imm32);
1578   void orl(Register dst, int32_t imm32);
1579   void orl(Register dst, Address src);
1580   void orl(Register dst, Register src);
1581   void orl(Address dst, Register src);
1582 
1583   void orb(Address dst, int imm8);
1584 
1585   void orq(Address dst, int32_t imm32);
1586   void orq(Register dst, int32_t imm32);
1587   void orq(Register dst, Address src);
1588   void orq(Register dst, Register src);
1589 
1590   // Pack with unsigned saturation
1591   void packuswb(XMMRegister dst, XMMRegister src);
1592   void packuswb(XMMRegister dst, Address src);
1593   void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1594 
1595   // Pemutation of 64bit words
1596   void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1597   void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1598   void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1599   void vperm2i128(XMMRegister dst,  XMMRegister nds, XMMRegister src, int imm8);
1600   void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1601   void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1602 
1603   void pause();
1604 
1605   // Undefined Instruction
1606   void ud2();
1607 
1608   // SSE4.2 string instructions
1609   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1610   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1611 
1612   void pcmpeqb(XMMRegister dst, XMMRegister src);
1613   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1614   void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1615   void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1616   void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1617 
1618   void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1619   void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1620 
1621   void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1622   void evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate of, int vector_len);
1623   void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);
1624 
1625   void pcmpeqw(XMMRegister dst, XMMRegister src);
1626   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1627   void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1628   void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1629 
1630   void pcmpeqd(XMMRegister dst, XMMRegister src);
1631   void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1632   void evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1633   void evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1634 
1635   void pcmpeqq(XMMRegister dst, XMMRegister src);
1636   void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1637   void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1638   void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1639 
1640   void pmovmskb(Register dst, XMMRegister src);
1641   void vpmovmskb(Register dst, XMMRegister src);
1642 
1643   // SSE 4.1 extract
1644   void pextrd(Register dst, XMMRegister src, int imm8);
1645   void pextrq(Register dst, XMMRegister src, int imm8);
1646   void pextrd(Address dst, XMMRegister src, int imm8);
1647   void pextrq(Address dst, XMMRegister src, int imm8);
1648   void pextrb(Address dst, XMMRegister src, int imm8);
1649   // SSE 2 extract
1650   void pextrw(Register dst, XMMRegister src, int imm8);
1651   void pextrw(Address dst, XMMRegister src, int imm8);
1652 
1653   // SSE 4.1 insert
1654   void pinsrd(XMMRegister dst, Register src, int imm8);
1655   void pinsrq(XMMRegister dst, Register src, int imm8);
1656   void pinsrd(XMMRegister dst, Address src, int imm8);
1657   void pinsrq(XMMRegister dst, Address src, int imm8);
1658   void pinsrb(XMMRegister dst, Address src, int imm8);
1659   // SSE 2 insert
1660   void pinsrw(XMMRegister dst, Register src, int imm8);
1661   void pinsrw(XMMRegister dst, Address src, int imm8);
1662 
1663   // SSE4.1 packed move
1664   void pmovzxbw(XMMRegister dst, XMMRegister src);
1665   void pmovzxbw(XMMRegister dst, Address src);
1666 
1667   void vpmovzxbw( XMMRegister dst, Address src, int vector_len);
1668   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
1669   void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1670 
1671   void evpmovwb(Address dst, XMMRegister src, int vector_len);
1672   void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
1673 
1674   void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);
1675 
1676   void evpmovdb(Address dst, XMMRegister src, int vector_len);
1677 
1678   // Sign extend moves
1679   void pmovsxbw(XMMRegister dst, XMMRegister src);
1680   void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
1681 
1682 #ifndef _LP64 // no 32bit push/pop on amd64
1683   void popl(Address dst);
1684 #endif
1685 
1686 #ifdef _LP64
1687   void popq(Address dst);
1688 #endif
1689 
1690   void popcntl(Register dst, Address src);
1691   void popcntl(Register dst, Register src);
1692 
1693   void vpopcntd(XMMRegister dst, XMMRegister src, int vector_len);
1694 
1695 #ifdef _LP64
1696   void popcntq(Register dst, Address src);
1697   void popcntq(Register dst, Register src);
1698 #endif
1699 
1700   // Prefetches (SSE, SSE2, 3DNOW only)
1701 
1702   void prefetchnta(Address src);
1703   void prefetchr(Address src);
1704   void prefetcht0(Address src);
1705   void prefetcht1(Address src);
1706   void prefetcht2(Address src);
1707   void prefetchw(Address src);
1708 
1709   // Shuffle Bytes
1710   void pshufb(XMMRegister dst, XMMRegister src);
1711   void pshufb(XMMRegister dst, Address src);
1712   void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1713 
1714   // Shuffle Packed Doublewords
1715   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1716   void pshufd(XMMRegister dst, Address src,     int mode);
1717   void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1718 
1719   // Shuffle Packed Low Words
1720   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1721   void pshuflw(XMMRegister dst, Address src,     int mode);
1722 
1723   // Shuffle packed values at 128 bit granularity
1724   void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
1725 
1726   // Shift Right by bytes Logical DoubleQuadword Immediate
1727   void psrldq(XMMRegister dst, int shift);
1728   // Shift Left by bytes Logical DoubleQuadword Immediate
1729   void pslldq(XMMRegister dst, int shift);
1730 
1731   // Logical Compare 128bit
1732   void ptest(XMMRegister dst, XMMRegister src);
1733   void ptest(XMMRegister dst, Address src);
1734   // Logical Compare 256bit
1735   void vptest(XMMRegister dst, XMMRegister src);
1736   void vptest(XMMRegister dst, Address src);
1737 
1738   // Interleave Low Bytes
1739   void punpcklbw(XMMRegister dst, XMMRegister src);
1740   void punpcklbw(XMMRegister dst, Address src);
1741 
1742   // Interleave Low Doublewords
1743   void punpckldq(XMMRegister dst, XMMRegister src);
1744   void punpckldq(XMMRegister dst, Address src);
1745 
1746   // Interleave Low Quadwords
1747   void punpcklqdq(XMMRegister dst, XMMRegister src);
1748 
1749 #ifndef _LP64 // no 32bit push/pop on amd64
1750   void pushl(Address src);
1751 #endif
1752 
1753   void pushq(Address src);
1754 
1755   void rcll(Register dst, int imm8);
1756 
1757   void rclq(Register dst, int imm8);
1758 
1759   void rcrq(Register dst, int imm8);
1760 
1761   void rcpps(XMMRegister dst, XMMRegister src);
1762 
1763   void rcpss(XMMRegister dst, XMMRegister src);
1764 
1765   void rdtsc();
1766 
1767   void ret(int imm16);
1768 
1769 #ifdef _LP64
1770   void rorq(Register dst, int imm8);
1771   void rorxq(Register dst, Register src, int imm8);
1772   void rorxd(Register dst, Register src, int imm8);
1773 #endif
1774 
1775   void sahf();
1776 
1777   void sarl(Register dst, int imm8);
1778   void sarl(Register dst);
1779 
1780   void sarq(Register dst, int imm8);
1781   void sarq(Register dst);
1782 
1783   void sbbl(Address dst, int32_t imm32);
1784   void sbbl(Register dst, int32_t imm32);
1785   void sbbl(Register dst, Address src);
1786   void sbbl(Register dst, Register src);
1787 
1788   void sbbq(Address dst, int32_t imm32);
1789   void sbbq(Register dst, int32_t imm32);
1790   void sbbq(Register dst, Address src);
1791   void sbbq(Register dst, Register src);
1792 
1793   void setb(Condition cc, Register dst);
1794 
1795   void palignr(XMMRegister dst, XMMRegister src, int imm8);
1796   void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
1797   void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
1798 
1799   void pblendw(XMMRegister dst, XMMRegister src, int imm8);
1800 
1801   void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
1802   void sha1nexte(XMMRegister dst, XMMRegister src);
1803   void sha1msg1(XMMRegister dst, XMMRegister src);
1804   void sha1msg2(XMMRegister dst, XMMRegister src);
1805   // xmm0 is implicit additional source to the following instruction.
1806   void sha256rnds2(XMMRegister dst, XMMRegister src);
1807   void sha256msg1(XMMRegister dst, XMMRegister src);
1808   void sha256msg2(XMMRegister dst, XMMRegister src);
1809 
1810   void shldl(Register dst, Register src);
1811   void shldl(Register dst, Register src, int8_t imm8);
1812 
1813   void shll(Register dst, int imm8);
1814   void shll(Register dst);
1815 
1816   void shlq(Register dst, int imm8);
1817   void shlq(Register dst);
1818 
1819   void shrdl(Register dst, Register src);
1820 
1821   void shrl(Register dst, int imm8);
1822   void shrl(Register dst);
1823 
1824   void shrq(Register dst, int imm8);
1825   void shrq(Register dst);
1826 
1827   void smovl(); // QQQ generic?
1828 
1829   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1830   void sqrtsd(XMMRegister dst, Address src);
1831   void sqrtsd(XMMRegister dst, XMMRegister src);
1832 
1833   // Compute Square Root of Scalar Single-Precision Floating-Point Value
1834   void sqrtss(XMMRegister dst, Address src);
1835   void sqrtss(XMMRegister dst, XMMRegister src);
1836 
1837   void std();
1838 
1839   void stmxcsr( Address dst );
1840 
1841   void subl(Address dst, int32_t imm32);
1842   void subl(Address dst, Register src);
1843   void subl(Register dst, int32_t imm32);
1844   void subl(Register dst, Address src);
1845   void subl(Register dst, Register src);
1846 
1847   void subq(Address dst, int32_t imm32);
1848   void subq(Address dst, Register src);
1849   void subq(Register dst, int32_t imm32);
1850   void subq(Register dst, Address src);
1851   void subq(Register dst, Register src);
1852 
1853   // Force generation of a 4 byte immediate value even if it fits into 8bit
1854   void subl_imm32(Register dst, int32_t imm32);
1855   void subq_imm32(Register dst, int32_t imm32);
1856 
1857   // Subtract Scalar Double-Precision Floating-Point Values
1858   void subsd(XMMRegister dst, Address src);
1859   void subsd(XMMRegister dst, XMMRegister src);
1860 
1861   // Subtract Scalar Single-Precision Floating-Point Values
1862   void subss(XMMRegister dst, Address src);
1863   void subss(XMMRegister dst, XMMRegister src);
1864 
1865   void testb(Register dst, int imm8);
1866   void testb(Address dst, int imm8);
1867 
1868   void testl(Register dst, int32_t imm32);
1869   void testl(Register dst, Register src);
1870   void testl(Register dst, Address src);
1871 
1872   void testq(Register dst, int32_t imm32);
1873   void testq(Register dst, Register src);
1874   void testq(Register dst, Address src);
1875 
1876   // BMI - count trailing zeros
1877   void tzcntl(Register dst, Register src);
1878   void tzcntq(Register dst, Register src);
1879 
1880   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1881   void ucomisd(XMMRegister dst, Address src);
1882   void ucomisd(XMMRegister dst, XMMRegister src);
1883 
1884   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1885   void ucomiss(XMMRegister dst, Address src);
1886   void ucomiss(XMMRegister dst, XMMRegister src);
1887 
1888   void xabort(int8_t imm8);
1889 
1890   void xaddb(Address dst, Register src);
1891   void xaddw(Address dst, Register src);
1892   void xaddl(Address dst, Register src);
1893   void xaddq(Address dst, Register src);
1894 
1895   void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1896 
1897   void xchgb(Register reg, Address adr);
1898   void xchgw(Register reg, Address adr);
1899   void xchgl(Register reg, Address adr);
1900   void xchgl(Register dst, Register src);
1901 
1902   void xchgq(Register reg, Address adr);
1903   void xchgq(Register dst, Register src);
1904 
1905   void xend();
1906 
1907   // Get Value of Extended Control Register
1908   void xgetbv();
1909 
1910   void xorl(Register dst, int32_t imm32);
1911   void xorl(Register dst, Address src);
1912   void xorl(Register dst, Register src);
1913 
1914   void xorb(Register dst, Address src);
1915 
1916   void xorq(Register dst, Address src);
1917   void xorq(Register dst, Register src);
1918 
1919   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1920 
1921   // AVX 3-operands scalar instructions (encoded with VEX prefix)
1922 
1923   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1924   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1925   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1926   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1927   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1928   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1929   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1930   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1931   void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1932   void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1933   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1934   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1935   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1936   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1937   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1938   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1939   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1940   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1941 
1942   void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1943   void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1944   void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1945   void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1946 
1947   void shlxl(Register dst, Register src1, Register src2);
1948   void shlxq(Register dst, Register src1, Register src2);
1949 
1950   //====================VECTOR ARITHMETIC=====================================
1951 
1952   // Add Packed Floating-Point Values
1953   void addpd(XMMRegister dst, XMMRegister src);
1954   void addpd(XMMRegister dst, Address src);
1955   void addps(XMMRegister dst, XMMRegister src);
1956   void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1957   void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1958   void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1959   void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1960 
1961   // Subtract Packed Floating-Point Values
1962   void subpd(XMMRegister dst, XMMRegister src);
1963   void subps(XMMRegister dst, XMMRegister src);
1964   void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1965   void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1966   void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1967   void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1968 
1969   // Multiply Packed Floating-Point Values
1970   void mulpd(XMMRegister dst, XMMRegister src);
1971   void mulpd(XMMRegister dst, Address src);
1972   void mulps(XMMRegister dst, XMMRegister src);
1973   void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1974   void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1975   void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1976   void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1977 
1978   void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1979   void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1980   void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1981   void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1982 
1983   // Divide Packed Floating-Point Values
1984   void divpd(XMMRegister dst, XMMRegister src);
1985   void divps(XMMRegister dst, XMMRegister src);
1986   void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1987   void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1988   void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1989   void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1990 
1991   // Sqrt Packed Floating-Point Values
1992   void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
1993   void vsqrtpd(XMMRegister dst, Address src, int vector_len);
1994   void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
1995   void vsqrtps(XMMRegister dst, Address src, int vector_len);
1996 
1997   // Bitwise Logical AND of Packed Floating-Point Values
1998   void andpd(XMMRegister dst, XMMRegister src);
1999   void andps(XMMRegister dst, XMMRegister src);
2000   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2001   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2002   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2003   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2004 
2005   void unpckhpd(XMMRegister dst, XMMRegister src);
2006   void unpcklpd(XMMRegister dst, XMMRegister src);
2007 
2008   // Bitwise Logical XOR of Packed Floating-Point Values
2009   void xorpd(XMMRegister dst, XMMRegister src);
2010   void xorps(XMMRegister dst, XMMRegister src);
2011   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2012   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2013   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2014   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2015 
2016   // Add horizontal packed integers
2017   void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2018   void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2019   void phaddw(XMMRegister dst, XMMRegister src);
2020   void phaddd(XMMRegister dst, XMMRegister src);
2021 
2022   // Add packed integers
2023   void paddb(XMMRegister dst, XMMRegister src);
2024   void paddw(XMMRegister dst, XMMRegister src);
2025   void paddd(XMMRegister dst, XMMRegister src);
2026   void paddd(XMMRegister dst, Address src);
2027   void paddq(XMMRegister dst, XMMRegister src);
2028   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2029   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2030   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2031   void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2032   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2033   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2034   void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2035   void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2036 
2037   // Sub packed integers
2038   void psubb(XMMRegister dst, XMMRegister src);
2039   void psubw(XMMRegister dst, XMMRegister src);
2040   void psubd(XMMRegister dst, XMMRegister src);
2041   void psubq(XMMRegister dst, XMMRegister src);
2042   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2043   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2044   void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2045   void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2046   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2047   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2048   void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2049   void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2050 
2051   // Multiply packed integers (only shorts and ints)
2052   void pmullw(XMMRegister dst, XMMRegister src);
2053   void pmulld(XMMRegister dst, XMMRegister src);
2054   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2055   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2056   void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2057   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2058   void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2059   void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2060 
2061   // Shift left packed integers
2062   void psllw(XMMRegister dst, int shift);
2063   void pslld(XMMRegister dst, int shift);
2064   void psllq(XMMRegister dst, int shift);
2065   void psllw(XMMRegister dst, XMMRegister shift);
2066   void pslld(XMMRegister dst, XMMRegister shift);
2067   void psllq(XMMRegister dst, XMMRegister shift);
2068   void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2069   void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2070   void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2071   void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2072   void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2073   void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2074   void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2075 
2076   // Logical shift right packed integers
2077   void psrlw(XMMRegister dst, int shift);
2078   void psrld(XMMRegister dst, int shift);
2079   void psrlq(XMMRegister dst, int shift);
2080   void psrlw(XMMRegister dst, XMMRegister shift);
2081   void psrld(XMMRegister dst, XMMRegister shift);
2082   void psrlq(XMMRegister dst, XMMRegister shift);
2083   void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2084   void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2085   void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2086   void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2087   void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2088   void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2089   void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2090   void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2091   void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2092 
2093   // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2094   void psraw(XMMRegister dst, int shift);
2095   void psrad(XMMRegister dst, int shift);
2096   void psraw(XMMRegister dst, XMMRegister shift);
2097   void psrad(XMMRegister dst, XMMRegister shift);
2098   void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2099   void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2100   void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2101   void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2102   void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2103   void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2104 
2105   // And packed integers
2106   void pand(XMMRegister dst, XMMRegister src);
2107   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2108   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2109   void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2110 
2111   // Andn packed integers
2112   void pandn(XMMRegister dst, XMMRegister src);
2113   void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2114 
2115   // Or packed integers
2116   void por(XMMRegister dst, XMMRegister src);
2117   void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2118   void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2119   void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2120 
2121   // Xor packed integers
2122   void pxor(XMMRegister dst, XMMRegister src);
2123   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2124   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2125   void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2126   void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2127 
2128    // Ternary logic instruction.
2129   void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);
2130 
2131   // vinserti forms
2132   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2133   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2134   void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2135   void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2136   void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2137 
2138   // vinsertf forms
2139   void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2140   void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2141   void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2142   void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2143   void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2144   void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2145 
2146   // vextracti forms
2147   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2148   void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2149   void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2150   void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2151   void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2152   void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2153   void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8);
2154 
2155   // vextractf forms
2156   void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2157   void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2158   void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2159   void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2160   void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2161   void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2162   void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2163 
2164   // xmm/mem sourced byte/word/dword/qword replicate
2165   void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2166   void vpbroadcastb(XMMRegister dst, Address src, int vector_len);
2167   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2168   void vpbroadcastw(XMMRegister dst, Address src, int vector_len);
2169   void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2170   void vpbroadcastd(XMMRegister dst, Address src, int vector_len);
2171   void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2172   void vpbroadcastq(XMMRegister dst, Address src, int vector_len);
2173 
2174   void evbroadcasti32x4(XMMRegister dst, Address src, int vector_len);
2175   void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
2176   void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);
2177 
2178   // scalar single/double precision replicate
2179   void vpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2180   void vpbroadcastss(XMMRegister dst, Address src, int vector_len);
2181   void vpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2182   void vpbroadcastsd(XMMRegister dst, Address src, int vector_len);
2183 
2184   // gpr sourced byte/word/dword/qword replicate
2185   void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2186   void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2187   void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2188   void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2189 
2190   void evpgatherdd(XMMRegister dst, KRegister k1, Address src, int vector_len);
2191 
2192   // Carry-Less Multiplication Quadword
2193   void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2194   void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2195   void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
2196   // AVX instruction which is used to clear upper 128 bits of YMM registers and
2197   // to avoid transaction penalty between AVX and SSE states. There is no
2198   // penalty if legacy SSE instructions are encoded using VEX prefix because
2199   // they always clear upper 128 bits. It should be used before calling
2200   // runtime code and native libraries.
2201   void vzeroupper();
2202 
2203   // AVX support for vectorized conditional move (float/double). The following two instructions used only coupled.
2204   void blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2205   void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2206   void blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2207   void cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2208   void blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2209   void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
2210 
2211  protected:
2212   // Next instructions require address alignment 16 bytes SSE mode.
2213   // They should be called only from corresponding MacroAssembler instructions.
2214   void andpd(XMMRegister dst, Address src);
2215   void andps(XMMRegister dst, Address src);
2216   void xorpd(XMMRegister dst, Address src);
2217   void xorps(XMMRegister dst, Address src);
2218 
2219 };
2220 
2221 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2222 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2223 // are applied.
2224 class InstructionAttr {
2225 public:
2226   InstructionAttr(
2227     int vector_len,     // The length of vector to be applied in encoding - for both AVX and EVEX
2228     bool rex_vex_w,     // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2229     bool legacy_mode,   // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2230     bool no_reg_mask,   // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used
2231     bool uses_vl)       // This instruction may have legacy constraints based on vector length for EVEX
2232     :
2233       _avx_vector_len(vector_len),
2234       _rex_vex_w(rex_vex_w),
2235       _rex_vex_w_reverted(false),
2236       _legacy_mode(legacy_mode),
2237       _no_reg_mask(no_reg_mask),
2238       _uses_vl(uses_vl),
2239       _tuple_type(Assembler::EVEX_ETUP),
2240       _input_size_in_bits(Assembler::EVEX_NObit),
2241       _is_evex_instruction(false),
2242       _evex_encoding(0),
2243       _is_clear_context(true),
2244       _is_extended_context(false),
2245       _current_assembler(NULL),
2246       _embedded_opmask_register_specifier(0) { // hard code k0
2247     if (UseAVX < 3) _legacy_mode = true;
2248   }
2249 
2250   ~InstructionAttr() {
2251     if (_current_assembler != NULL) {
2252       _current_assembler->clear_attributes();
2253     }
2254     _current_assembler = NULL;
2255   }
2256 
2257 private:
2258   int  _avx_vector_len;
2259   bool _rex_vex_w;
2260   bool _rex_vex_w_reverted;
2261   bool _legacy_mode;
2262   bool _no_reg_mask;
2263   bool _uses_vl;
2264   int  _tuple_type;
2265   int  _input_size_in_bits;
2266   bool _is_evex_instruction;
2267   int  _evex_encoding;
2268   bool _is_clear_context;
2269   bool _is_extended_context;
2270   int _embedded_opmask_register_specifier;
2271 
2272   Assembler *_current_assembler;
2273 
2274 public:
2275   // query functions for field accessors
2276   int  get_vector_len(void) const { return _avx_vector_len; }
2277   bool is_rex_vex_w(void) const { return _rex_vex_w; }
2278   bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2279   bool is_legacy_mode(void) const { return _legacy_mode; }
2280   bool is_no_reg_mask(void) const { return _no_reg_mask; }
2281   bool uses_vl(void) const { return _uses_vl; }
2282   int  get_tuple_type(void) const { return _tuple_type; }
2283   int  get_input_size(void) const { return _input_size_in_bits; }
2284   int  is_evex_instruction(void) const { return _is_evex_instruction; }
2285   int  get_evex_encoding(void) const { return _evex_encoding; }
2286   bool is_clear_context(void) const { return _is_clear_context; }
2287   bool is_extended_context(void) const { return _is_extended_context; }
2288   int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }
2289 
2290   // Set the vector len manually
2291   void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2292 
2293   // Set revert rex_vex_w for avx encoding
2294   void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2295 
2296   // Set rex_vex_w based on state
2297   void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2298 
2299   // Set the instruction to be encoded in AVX mode
2300   void set_is_legacy_mode(void) { _legacy_mode = true; }
2301 
2302   // Set the current instuction to be encoded as an EVEX instuction
2303   void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2304 
2305   // Internal encoding data used in compressed immediate offset programming
2306   void set_evex_encoding(int value) { _evex_encoding = value; }
2307 
2308   // Set the Evex.Z field to be used to clear all non directed XMM/YMM/ZMM components
2309   void reset_is_clear_context(void) { _is_clear_context = false; }
2310 
2311   // Map back to current asembler so that we can manage object level assocation
2312   void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2313 
2314   // Address modifiers used for compressed displacement calculation
2315   void set_address_attributes(int tuple_type, int input_size_in_bits) {
2316     if (VM_Version::supports_evex()) {
2317       _tuple_type = tuple_type;
2318       _input_size_in_bits = input_size_in_bits;
2319     }
2320   }
2321 
2322   // Set embedded opmask register specifier.
2323   void set_embedded_opmask_register_specifier(KRegister mask) {
2324     _embedded_opmask_register_specifier = (*mask).encoding() & 0x7;
2325   }
2326 
2327 };
2328 
2329 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP