1 /* 2 * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP 26 #define CPU_X86_VM_VM_VERSION_X86_HPP 27 28 #include "runtime/globals_extension.hpp" 29 #include "runtime/vm_version.hpp" 30 31 class VM_Version : public Abstract_VM_Version { 32 friend class VMStructs; 33 friend class JVMCIVMStructs; 34 35 public: 36 // cpuid result register layouts. These are all unions of a uint32_t 37 // (in case anyone wants access to the register as a whole) and a bitfield. 38 39 union StdCpuid1Eax { 40 uint32_t value; 41 struct { 42 uint32_t stepping : 4, 43 model : 4, 44 family : 4, 45 proc_type : 2, 46 : 2, 47 ext_model : 4, 48 ext_family : 8, 49 : 4; 50 } bits; 51 }; 52 53 union StdCpuid1Ebx { // example, unused 54 uint32_t value; 55 struct { 56 uint32_t brand_id : 8, 57 clflush_size : 8, 58 threads_per_cpu : 8, 59 apic_id : 8; 60 } bits; 61 }; 62 63 union StdCpuid1Ecx { 64 uint32_t value; 65 struct { 66 uint32_t sse3 : 1, 67 clmul : 1, 68 : 1, 69 monitor : 1, 70 : 1, 71 vmx : 1, 72 : 1, 73 est : 1, 74 : 1, 75 ssse3 : 1, 76 cid : 1, 77 : 1, 78 fma : 1, 79 cmpxchg16: 1, 80 : 4, 81 dca : 1, 82 sse4_1 : 1, 83 sse4_2 : 1, 84 : 2, 85 popcnt : 1, 86 : 1, 87 aes : 1, 88 : 1, 89 osxsave : 1, 90 avx : 1, 91 : 2, 92 hv : 1; 93 } bits; 94 }; 95 96 union StdCpuid1Edx { 97 uint32_t value; 98 struct { 99 uint32_t : 4, 100 tsc : 1, 101 : 3, 102 cmpxchg8 : 1, 103 : 6, 104 cmov : 1, 105 : 3, 106 clflush : 1, 107 : 3, 108 mmx : 1, 109 fxsr : 1, 110 sse : 1, 111 sse2 : 1, 112 : 1, 113 ht : 1, 114 : 3; 115 } bits; 116 }; 117 118 union DcpCpuid4Eax { 119 uint32_t value; 120 struct { 121 uint32_t cache_type : 5, 122 : 21, 123 cores_per_cpu : 6; 124 } bits; 125 }; 126 127 union DcpCpuid4Ebx { 128 uint32_t value; 129 struct { 130 uint32_t L1_line_size : 12, 131 partitions : 10, 132 associativity : 10; 133 } bits; 134 }; 135 136 union TplCpuidBEbx { 137 uint32_t value; 138 struct { 139 uint32_t logical_cpus : 16, 140 : 16; 141 } bits; 142 }; 143 144 union ExtCpuid1Ecx { 145 uint32_t value; 146 struct { 147 uint32_t LahfSahf : 1, 148 CmpLegacy : 1, 149 : 3, 150 lzcnt_intel : 1, 151 lzcnt : 1, 152 sse4a : 1, 153 misalignsse : 1, 154 prefetchw : 1, 155 : 22; 156 } bits; 157 }; 158 159 union ExtCpuid1Edx { 160 uint32_t value; 161 struct { 162 uint32_t : 22, 163 mmx_amd : 1, 164 mmx : 1, 165 fxsr : 1, 166 : 4, 167 long_mode : 1, 168 tdnow2 : 1, 169 tdnow : 1; 170 } bits; 171 }; 172 173 union ExtCpuid5Ex { 174 uint32_t value; 175 struct { 176 uint32_t L1_line_size : 8, 177 L1_tag_lines : 8, 178 L1_assoc : 8, 179 L1_size : 8; 180 } bits; 181 }; 182 183 union ExtCpuid7Edx { 184 uint32_t value; 185 struct { 186 uint32_t : 8, 187 tsc_invariance : 1, 188 : 23; 189 } bits; 190 }; 191 192 union ExtCpuid8Ecx { 193 uint32_t value; 194 struct { 195 uint32_t cores_per_cpu : 8, 196 : 24; 197 } bits; 198 }; 199 200 union SefCpuid7Eax { 201 uint32_t value; 202 }; 203 204 union SefCpuid7Ebx { 205 uint32_t value; 206 struct { 207 uint32_t fsgsbase : 1, 208 : 2, 209 bmi1 : 1, 210 : 1, 211 avx2 : 1, 212 : 2, 213 bmi2 : 1, 214 erms : 1, 215 : 1, 216 rtm : 1, 217 : 4, 218 avx512f : 1, 219 avx512dq : 1, 220 : 1, 221 adx : 1, 222 : 6, 223 avx512pf : 1, 224 avx512er : 1, 225 avx512cd : 1, 226 sha : 1, 227 avx512bw : 1, 228 avx512vl : 1; 229 } bits; 230 }; 231 232 union SefCpuid7Ecx { 233 uint32_t value; 234 struct { 235 uint32_t prefetchwt1 : 1, 236 avx512_vbmi : 1, 237 umip : 1, 238 pku : 1, 239 ospke : 1, 240 : 1, 241 avx512_vbmi2 : 1, 242 : 1, 243 gfni : 1, 244 vaes : 1, 245 avx512_vpclmulqdq : 1, 246 avx512_vnni : 1, 247 avx512_bitalg : 1, 248 : 1, 249 avx512_vpopcntdq : 1, 250 : 17; 251 } bits; 252 }; 253 254 union SefCpuid7Edx { 255 uint32_t value; 256 struct { 257 uint32_t : 2, 258 avx512_4vnniw : 1, 259 avx512_4fmaps : 1, 260 : 28; 261 } bits; 262 }; 263 264 union ExtCpuid1EEbx { 265 uint32_t value; 266 struct { 267 uint32_t : 8, 268 threads_per_core : 8, 269 : 16; 270 } bits; 271 }; 272 273 union XemXcr0Eax { 274 uint32_t value; 275 struct { 276 uint32_t x87 : 1, 277 sse : 1, 278 ymm : 1, 279 bndregs : 1, 280 bndcsr : 1, 281 opmask : 1, 282 zmm512 : 1, 283 zmm32 : 1, 284 : 24; 285 } bits; 286 }; 287 288 protected: 289 static int _cpu; 290 static int _model; 291 static int _stepping; 292 293 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV 294 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV 295 296 enum Feature_Flag { 297 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) 298 CPU_CMOV = (1 << 1), 299 CPU_FXSR = (1 << 2), 300 CPU_HT = (1 << 3), 301 CPU_MMX = (1 << 4), 302 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions 303 // may not necessarily support other 3dnow instructions 304 CPU_SSE = (1 << 6), 305 CPU_SSE2 = (1 << 7), 306 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) 307 CPU_SSSE3 = (1 << 9), 308 CPU_SSE4A = (1 << 10), 309 CPU_SSE4_1 = (1 << 11), 310 CPU_SSE4_2 = (1 << 12), 311 CPU_POPCNT = (1 << 13), 312 CPU_LZCNT = (1 << 14), 313 CPU_TSC = (1 << 15), 314 CPU_TSCINV = (1 << 16), 315 CPU_AVX = (1 << 17), 316 CPU_AVX2 = (1 << 18), 317 CPU_AES = (1 << 19), 318 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions 319 CPU_CLMUL = (1 << 21), // carryless multiply for CRC 320 CPU_BMI1 = (1 << 22), 321 CPU_BMI2 = (1 << 23), 322 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions 323 CPU_ADX = (1 << 25), 324 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions 325 CPU_AVX512DQ = (1 << 27), 326 CPU_AVX512PF = (1 << 28), 327 CPU_AVX512ER = (1 << 29), 328 CPU_AVX512CD = (1 << 30) 329 // Keeping sign bit 31 unassigned. 330 }; 331 332 #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit 333 #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length 334 #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions 335 #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions 336 #define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000)) // Vzeroupper instruction 337 #define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64(0x2000000000)) // Vector popcount 338 #define CPU_AVX512_VPCLMULQDQ ((uint64_t)UCONST64(0x4000000000)) //Vector carryless multiplication 339 #define CPU_VAES ((uint64_t)UCONST64(0x8000000000)) // Vector AES instructions 340 #define CPU_HV_PRESENT ((uint64_t)UCONST64(0x400000000000)) // for hypervisor detection 341 342 enum Extended_Family { 343 // AMD 344 CPU_FAMILY_AMD_11H = 0x11, 345 // ZX 346 CPU_FAMILY_ZX_CORE_F6 = 6, 347 CPU_FAMILY_ZX_CORE_F7 = 7, 348 // Intel 349 CPU_FAMILY_INTEL_CORE = 6, 350 CPU_MODEL_NEHALEM = 0x1e, 351 CPU_MODEL_NEHALEM_EP = 0x1a, 352 CPU_MODEL_NEHALEM_EX = 0x2e, 353 CPU_MODEL_WESTMERE = 0x25, 354 CPU_MODEL_WESTMERE_EP = 0x2c, 355 CPU_MODEL_WESTMERE_EX = 0x2f, 356 CPU_MODEL_SANDYBRIDGE = 0x2a, 357 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, 358 CPU_MODEL_IVYBRIDGE_EP = 0x3a, 359 CPU_MODEL_HASWELL_E3 = 0x3c, 360 CPU_MODEL_HASWELL_E7 = 0x3f, 361 CPU_MODEL_BROADWELL = 0x3d, 362 CPU_MODEL_SKYLAKE = 0x55 363 }; 364 365 // cpuid information block. All info derived from executing cpuid with 366 // various function numbers is stored here. Intel and AMD info is 367 // merged in this block: accessor methods disentangle it. 368 // 369 // The info block is laid out in subblocks of 4 dwords corresponding to 370 // eax, ebx, ecx and edx, whether or not they contain anything useful. 371 struct CpuidInfo { 372 // cpuid function 0 373 uint32_t std_max_function; 374 uint32_t std_vendor_name_0; 375 uint32_t std_vendor_name_1; 376 uint32_t std_vendor_name_2; 377 378 // cpuid function 1 379 StdCpuid1Eax std_cpuid1_eax; 380 StdCpuid1Ebx std_cpuid1_ebx; 381 StdCpuid1Ecx std_cpuid1_ecx; 382 StdCpuid1Edx std_cpuid1_edx; 383 384 // cpuid function 4 (deterministic cache parameters) 385 DcpCpuid4Eax dcp_cpuid4_eax; 386 DcpCpuid4Ebx dcp_cpuid4_ebx; 387 uint32_t dcp_cpuid4_ecx; // unused currently 388 uint32_t dcp_cpuid4_edx; // unused currently 389 390 // cpuid function 7 (structured extended features) 391 SefCpuid7Eax sef_cpuid7_eax; 392 SefCpuid7Ebx sef_cpuid7_ebx; 393 SefCpuid7Ecx sef_cpuid7_ecx; 394 SefCpuid7Edx sef_cpuid7_edx; 395 396 // cpuid function 0xB (processor topology) 397 // ecx = 0 398 uint32_t tpl_cpuidB0_eax; 399 TplCpuidBEbx tpl_cpuidB0_ebx; 400 uint32_t tpl_cpuidB0_ecx; // unused currently 401 uint32_t tpl_cpuidB0_edx; // unused currently 402 403 // ecx = 1 404 uint32_t tpl_cpuidB1_eax; 405 TplCpuidBEbx tpl_cpuidB1_ebx; 406 uint32_t tpl_cpuidB1_ecx; // unused currently 407 uint32_t tpl_cpuidB1_edx; // unused currently 408 409 // ecx = 2 410 uint32_t tpl_cpuidB2_eax; 411 TplCpuidBEbx tpl_cpuidB2_ebx; 412 uint32_t tpl_cpuidB2_ecx; // unused currently 413 uint32_t tpl_cpuidB2_edx; // unused currently 414 415 // cpuid function 0x80000000 // example, unused 416 uint32_t ext_max_function; 417 uint32_t ext_vendor_name_0; 418 uint32_t ext_vendor_name_1; 419 uint32_t ext_vendor_name_2; 420 421 // cpuid function 0x80000001 422 uint32_t ext_cpuid1_eax; // reserved 423 uint32_t ext_cpuid1_ebx; // reserved 424 ExtCpuid1Ecx ext_cpuid1_ecx; 425 ExtCpuid1Edx ext_cpuid1_edx; 426 427 // cpuid functions 0x80000002 thru 0x80000004: example, unused 428 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; 429 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; 430 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; 431 432 // cpuid function 0x80000005 // AMD L1, Intel reserved 433 uint32_t ext_cpuid5_eax; // unused currently 434 uint32_t ext_cpuid5_ebx; // reserved 435 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) 436 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) 437 438 // cpuid function 0x80000007 439 uint32_t ext_cpuid7_eax; // reserved 440 uint32_t ext_cpuid7_ebx; // reserved 441 uint32_t ext_cpuid7_ecx; // reserved 442 ExtCpuid7Edx ext_cpuid7_edx; // tscinv 443 444 // cpuid function 0x80000008 445 uint32_t ext_cpuid8_eax; // unused currently 446 uint32_t ext_cpuid8_ebx; // reserved 447 ExtCpuid8Ecx ext_cpuid8_ecx; 448 uint32_t ext_cpuid8_edx; // reserved 449 450 // cpuid function 0x8000001E // AMD 17h 451 uint32_t ext_cpuid1E_eax; 452 ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h) 453 uint32_t ext_cpuid1E_ecx; 454 uint32_t ext_cpuid1E_edx; // unused currently 455 456 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) 457 XemXcr0Eax xem_xcr0_eax; 458 uint32_t xem_xcr0_edx; // reserved 459 460 // Space to save ymm registers after signal handle 461 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 462 463 // Space to save zmm registers after signal handle 464 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31 465 }; 466 467 // The actual cpuid info block 468 static CpuidInfo _cpuid_info; 469 470 // Extractors and predicates 471 static uint32_t extended_cpu_family() { 472 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; 473 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; 474 return result; 475 } 476 477 static uint32_t extended_cpu_model() { 478 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; 479 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; 480 return result; 481 } 482 483 static uint32_t cpu_stepping() { 484 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; 485 return result; 486 } 487 488 static uint logical_processor_count() { 489 uint result = threads_per_core(); 490 return result; 491 } 492 493 static uint64_t feature_flags() { 494 uint64_t result = 0; 495 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) 496 result |= CPU_CX8; 497 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) 498 result |= CPU_CMOV; 499 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && 500 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) 501 result |= CPU_FXSR; 502 // HT flag is set for multi-core processors also. 503 if (threads_per_core() > 1) 504 result |= CPU_HT; 505 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && 506 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) 507 result |= CPU_MMX; 508 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) 509 result |= CPU_SSE; 510 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) 511 result |= CPU_SSE2; 512 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) 513 result |= CPU_SSE3; 514 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) 515 result |= CPU_SSSE3; 516 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) 517 result |= CPU_SSE4_1; 518 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) 519 result |= CPU_SSE4_2; 520 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) 521 result |= CPU_POPCNT; 522 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && 523 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && 524 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && 525 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { 526 result |= CPU_AVX; 527 result |= CPU_VZEROUPPER; 528 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) 529 result |= CPU_AVX2; 530 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 && 531 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 && 532 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 && 533 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) { 534 result |= CPU_AVX512F; 535 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0) 536 result |= CPU_AVX512CD; 537 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0) 538 result |= CPU_AVX512DQ; 539 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0) 540 result |= CPU_AVX512PF; 541 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0) 542 result |= CPU_AVX512ER; 543 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0) 544 result |= CPU_AVX512BW; 545 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0) 546 result |= CPU_AVX512VL; 547 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0) 548 result |= CPU_AVX512_VPOPCNTDQ; 549 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpclmulqdq != 0) 550 result |= CPU_AVX512_VPCLMULQDQ; 551 if (_cpuid_info.sef_cpuid7_ecx.bits.vaes != 0) 552 result |= CPU_VAES; 553 } 554 } 555 if (_cpuid_info.std_cpuid1_ecx.bits.hv != 0) 556 result |= CPU_HV_PRESENT; 557 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) 558 result |= CPU_BMI1; 559 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) 560 result |= CPU_TSC; 561 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) 562 result |= CPU_TSCINV; 563 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) 564 result |= CPU_AES; 565 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) 566 result |= CPU_ERMS; 567 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) 568 result |= CPU_CLMUL; 569 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) 570 result |= CPU_RTM; 571 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0) 572 result |= CPU_ADX; 573 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) 574 result |= CPU_BMI2; 575 if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0) 576 result |= CPU_SHA; 577 if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0) 578 result |= CPU_FMA; 579 580 // AMD features. 581 if (is_amd()) { 582 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || 583 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) 584 result |= CPU_3DNOW_PREFETCH; 585 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) 586 result |= CPU_LZCNT; 587 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 588 result |= CPU_SSE4A; 589 } 590 // Intel features. 591 if(is_intel()) { 592 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) 593 result |= CPU_LZCNT; 594 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw 595 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { 596 result |= CPU_3DNOW_PREFETCH; 597 } 598 } 599 600 // ZX features. 601 if (is_zx()) { 602 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) 603 result |= CPU_LZCNT; 604 // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw 605 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { 606 result |= CPU_3DNOW_PREFETCH; 607 } 608 } 609 610 return result; 611 } 612 613 static bool os_supports_avx_vectors() { 614 bool retVal = false; 615 if (supports_evex()) { 616 // Verify that OS save/restore all bits of EVEX registers 617 // during signal processing. 618 int nreg = 2 LP64_ONLY(+2); 619 retVal = true; 620 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register 621 if (_cpuid_info.zmm_save[i] != ymm_test_value()) { 622 retVal = false; 623 break; 624 } 625 } 626 } else if (supports_avx()) { 627 // Verify that OS save/restore all bits of AVX registers 628 // during signal processing. 629 int nreg = 2 LP64_ONLY(+2); 630 retVal = true; 631 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register 632 if (_cpuid_info.ymm_save[i] != ymm_test_value()) { 633 retVal = false; 634 break; 635 } 636 } 637 // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen 638 if (retVal == false) { 639 // Verify that OS save/restore all bits of EVEX registers 640 // during signal processing. 641 int nreg = 2 LP64_ONLY(+2); 642 retVal = true; 643 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register 644 if (_cpuid_info.zmm_save[i] != ymm_test_value()) { 645 retVal = false; 646 break; 647 } 648 } 649 } 650 } 651 return retVal; 652 } 653 654 static void get_processor_features(); 655 656 public: 657 // Offsets for cpuid asm stub 658 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } 659 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } 660 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } 661 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } 662 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } 663 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } 664 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } 665 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } 666 static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); } 667 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } 668 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } 669 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } 670 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } 671 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } 672 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); } 673 674 // The value used to check ymm register after signal handle 675 static int ymm_test_value() { return 0xCAFEBABE; } 676 677 static void get_cpu_info_wrapper(); 678 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } 679 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } 680 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } 681 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } 682 683 static void clean_cpuFeatures() { _features = 0; } 684 static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); } 685 static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); } 686 687 688 // Initialization 689 static void initialize(); 690 691 // Override Abstract_VM_Version implementation 692 static void print_platform_virtualization_info(outputStream*); 693 694 // Override Abstract_VM_Version implementation 695 static bool use_biased_locking(); 696 697 // Asserts 698 static void assert_is_initialized() { 699 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); 700 } 701 702 // 703 // Processor family: 704 // 3 - 386 705 // 4 - 486 706 // 5 - Pentium 707 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, 708 // Pentium M, Core Solo, Core Duo, Core2 Duo 709 // family 6 model: 9, 13, 14, 15 710 // 0x0f - Pentium 4, Opteron 711 // 712 // Note: The cpu family should be used to select between 713 // instruction sequences which are valid on all Intel 714 // processors. Use the feature test functions below to 715 // determine whether a particular instruction is supported. 716 // 717 static int cpu_family() { return _cpu;} 718 static bool is_P6() { return cpu_family() >= 6; } 719 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' 720 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' 721 static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS ' 722 static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton 723 static bool is_knights_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi 724 725 static bool supports_processor_topology() { 726 return (_cpuid_info.std_max_function >= 0xB) && 727 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. 728 // Some cpus have max cpuid >= 0xB but do not support processor topology. 729 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); 730 } 731 732 static uint cores_per_cpu() { 733 uint result = 1; 734 if (is_intel()) { 735 bool supports_topology = supports_processor_topology(); 736 if (supports_topology) { 737 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / 738 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 739 } 740 if (!supports_topology || result == 0) { 741 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); 742 } 743 } else if (is_amd()) { 744 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); 745 } else if (is_zx()) { 746 bool supports_topology = supports_processor_topology(); 747 if (supports_topology) { 748 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / 749 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 750 } 751 if (!supports_topology || result == 0) { 752 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); 753 } 754 } 755 return result; 756 } 757 758 static uint threads_per_core() { 759 uint result = 1; 760 if (is_intel() && supports_processor_topology()) { 761 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 762 } else if (is_zx() && supports_processor_topology()) { 763 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 764 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { 765 if (cpu_family() >= 0x17) { 766 result = _cpuid_info.ext_cpuid1E_ebx.bits.threads_per_core + 1; 767 } else { 768 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / 769 cores_per_cpu(); 770 } 771 } 772 return (result == 0 ? 1 : result); 773 } 774 775 static intx L1_line_size() { 776 intx result = 0; 777 if (is_intel()) { 778 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); 779 } else if (is_amd()) { 780 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; 781 } else if (is_zx()) { 782 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); 783 } 784 if (result < 32) // not defined ? 785 result = 32; // 32 bytes by default on x86 and other x64 786 return result; 787 } 788 789 static intx prefetch_data_size() { 790 return L1_line_size(); 791 } 792 793 // 794 // Feature identification 795 // 796 static bool supports_cpuid() { return _features != 0; } 797 static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; } 798 static bool supports_cmov() { return (_features & CPU_CMOV) != 0; } 799 static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; } 800 static bool supports_ht() { return (_features & CPU_HT) != 0; } 801 static bool supports_mmx() { return (_features & CPU_MMX) != 0; } 802 static bool supports_sse() { return (_features & CPU_SSE) != 0; } 803 static bool supports_sse2() { return (_features & CPU_SSE2) != 0; } 804 static bool supports_sse3() { return (_features & CPU_SSE3) != 0; } 805 static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; } 806 static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; } 807 static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; } 808 static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; } 809 static bool supports_avx() { return (_features & CPU_AVX) != 0; } 810 static bool supports_avx2() { return (_features & CPU_AVX2) != 0; } 811 static bool supports_tsc() { return (_features & CPU_TSC) != 0; } 812 static bool supports_aes() { return (_features & CPU_AES) != 0; } 813 static bool supports_erms() { return (_features & CPU_ERMS) != 0; } 814 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; } 815 static bool supports_rtm() { return (_features & CPU_RTM) != 0; } 816 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; } 817 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; } 818 static bool supports_adx() { return (_features & CPU_ADX) != 0; } 819 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; } 820 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; } 821 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; } 822 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; } 823 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; } 824 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; } 825 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; } 826 static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); } 827 static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); } 828 static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() && 829 supports_avx512bw() && supports_avx512dq()); } 830 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); } 831 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); } 832 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); } 833 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); } 834 static bool supports_sha() { return (_features & CPU_SHA) != 0; } 835 static bool supports_fma() { return (_features & CPU_FMA) != 0 && supports_avx(); } 836 static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; } 837 static bool supports_vpopcntdq() { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; } 838 static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; } 839 static bool supports_vaes() { return (_features & CPU_VAES) != 0; } 840 static bool supports_hv() { return (_features & CPU_HV_PRESENT) != 0; } 841 842 // Intel features 843 static bool is_intel_family_core() { return is_intel() && 844 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 845 846 static bool is_intel_skylake() { return is_intel_family_core() && 847 extended_cpu_model() == CPU_MODEL_SKYLAKE; } 848 849 static bool is_intel_tsc_synched_at_init() { 850 if (is_intel_family_core()) { 851 uint32_t ext_model = extended_cpu_model(); 852 if (ext_model == CPU_MODEL_NEHALEM_EP || 853 ext_model == CPU_MODEL_WESTMERE_EP || 854 ext_model == CPU_MODEL_SANDYBRIDGE_EP || 855 ext_model == CPU_MODEL_IVYBRIDGE_EP) { 856 // <= 2-socket invariant tsc support. EX versions are usually used 857 // in > 2-socket systems and likely don't synchronize tscs at 858 // initialization. 859 // Code that uses tsc values must be prepared for them to arbitrarily 860 // jump forward or backward. 861 return true; 862 } 863 } 864 return false; 865 } 866 867 // AMD features 868 static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; } 869 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } 870 static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; } 871 static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; } 872 873 static bool is_amd_Barcelona() { return is_amd() && 874 extended_cpu_family() == CPU_FAMILY_AMD_11H; } 875 876 // Intel and AMD newer cores support fast timestamps well 877 static bool supports_tscinv_bit() { 878 return (_features & CPU_TSCINV) != 0; 879 } 880 static bool supports_tscinv() { 881 return supports_tscinv_bit() && 882 ( (is_amd() && !is_amd_Barcelona()) || 883 is_intel_tsc_synched_at_init() ); 884 } 885 886 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). 887 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && 888 supports_sse3() && _model != 0x1C; } 889 890 static bool supports_compare_and_exchange() { return true; } 891 892 static intx allocate_prefetch_distance(bool use_watermark_prefetch) { 893 // Hardware prefetching (distance/size in bytes): 894 // Pentium 3 - 64 / 32 895 // Pentium 4 - 256 / 128 896 // Athlon - 64 / 32 ???? 897 // Opteron - 128 / 64 only when 2 sequential cache lines accessed 898 // Core - 128 / 64 899 // 900 // Software prefetching (distance in bytes / instruction with best score): 901 // Pentium 3 - 128 / prefetchnta 902 // Pentium 4 - 512 / prefetchnta 903 // Athlon - 128 / prefetchnta 904 // Opteron - 256 / prefetchnta 905 // Core - 256 / prefetchnta 906 // It will be used only when AllocatePrefetchStyle > 0 907 908 if (is_amd()) { // AMD 909 if (supports_sse2()) { 910 return 256; // Opteron 911 } else { 912 return 128; // Athlon 913 } 914 } else { // Intel 915 if (supports_sse3() && cpu_family() == 6) { 916 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus 917 return 192; 918 } else if (use_watermark_prefetch) { // watermark prefetching on Core 919 #ifdef _LP64 920 return 384; 921 #else 922 return 320; 923 #endif 924 } 925 } 926 if (supports_sse2()) { 927 if (cpu_family() == 6) { 928 return 256; // Pentium M, Core, Core2 929 } else { 930 return 512; // Pentium 4 931 } 932 } else { 933 return 128; // Pentium 3 (and all other old CPUs) 934 } 935 } 936 } 937 938 // SSE2 and later processors implement a 'pause' instruction 939 // that can be used for efficient implementation of 940 // the intrinsic for java.lang.Thread.onSpinWait() 941 static bool supports_on_spin_wait() { return supports_sse2(); } 942 943 #ifdef __APPLE__ 944 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64) 945 static bool is_cpu_emulated(); 946 #endif 947 948 // support functions for virtualization detection 949 private: 950 static void check_virtualizations(); 951 }; 952 953 #endif // CPU_X86_VM_VM_VERSION_X86_HPP