1 /* 2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2019, SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/collectedHeap.hpp" 36 #include "gc/shared/barrierSet.hpp" 37 #include "gc/shared/cardTableBarrierSet.hpp" 38 #include "memory/universe.hpp" 39 #include "nativeInst_ppc.hpp" 40 #include "oops/compressedOops.hpp" 41 #include "oops/objArrayKlass.hpp" 42 #include "runtime/frame.inline.hpp" 43 #include "runtime/safepointMechanism.inline.hpp" 44 #include "runtime/sharedRuntime.hpp" 45 46 #define __ _masm-> 47 48 49 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5; 50 51 52 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 53 Unimplemented(); return false; // Currently not used on this platform. 54 } 55 56 57 LIR_Opr LIR_Assembler::receiverOpr() { 58 return FrameMap::R3_oop_opr; 59 } 60 61 62 LIR_Opr LIR_Assembler::osrBufferPointer() { 63 return FrameMap::R3_opr; 64 } 65 66 67 // This specifies the stack pointer decrement needed to build the frame. 68 int LIR_Assembler::initial_frame_size_in_bytes() const { 69 return in_bytes(frame_map()->framesize_in_bytes()); 70 } 71 72 73 // Inline cache check: the inline cached class is in inline_cache_reg; 74 // we fetch the class of the receiver and compare it with the cached class. 75 // If they do not match we jump to slow case. 76 int LIR_Assembler::check_icache() { 77 int offset = __ offset(); 78 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg); 79 return offset; 80 } 81 82 void LIR_Assembler::clinit_barrier(ciMethod* method) { 83 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); 84 85 Label L_skip_barrier; 86 Register klass = R20; 87 88 metadata2reg(method->holder()->constant_encoding(), klass); 89 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/); 90 91 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0); 92 __ mtctr(klass); 93 __ bctr(); 94 95 __ bind(L_skip_barrier); 96 } 97 98 void LIR_Assembler::osr_entry() { 99 // On-stack-replacement entry sequence: 100 // 101 // 1. Create a new compiled activation. 102 // 2. Initialize local variables in the compiled activation. The expression 103 // stack must be empty at the osr_bci; it is not initialized. 104 // 3. Jump to the continuation address in compiled code to resume execution. 105 106 // OSR entry point 107 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 108 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 109 ValueStack* entry_state = osr_entry->end()->state(); 110 int number_of_locks = entry_state->locks_size(); 111 112 // Create a frame for the compiled activation. 113 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 114 115 // OSR buffer is 116 // 117 // locals[nlocals-1..0] 118 // monitors[number_of_locks-1..0] 119 // 120 // Locals is a direct copy of the interpreter frame so in the osr buffer 121 // the first slot in the local array is the last local from the interpreter 122 // and the last slot is local[0] (receiver) from the interpreter. 123 // 124 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 125 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 126 // in the interpreter frame (the method lock if a sync method). 127 128 // Initialize monitors in the compiled activation. 129 // R3: pointer to osr buffer 130 // 131 // All other registers are dead at this point and the locals will be 132 // copied into place by code emitted in the IR. 133 134 Register OSR_buf = osrBufferPointer()->as_register(); 135 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 136 int monitor_offset = BytesPerWord * method()->max_locals() + 137 (2 * BytesPerWord) * (number_of_locks - 1); 138 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 139 // the OSR buffer using 2 word entries: first the lock and then 140 // the oop. 141 for (int i = 0; i < number_of_locks; i++) { 142 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 143 #ifdef ASSERT 144 // Verify the interpreter's monitor has a non-null object. 145 { 146 Label L; 147 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf); 148 __ cmpdi(CCR0, R0, 0); 149 __ bne(CCR0, L); 150 __ stop("locked object is NULL"); 151 __ bind(L); 152 } 153 #endif // ASSERT 154 // Copy the lock field into the compiled activation. 155 Address ml = frame_map()->address_for_monitor_lock(i), 156 mo = frame_map()->address_for_monitor_object(i); 157 assert(ml.index() == noreg && mo.index() == noreg, "sanity"); 158 __ ld(R0, slot_offset + 0, OSR_buf); 159 __ std(R0, ml.disp(), ml.base()); 160 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf); 161 __ std(R0, mo.disp(), mo.base()); 162 } 163 } 164 } 165 166 167 int LIR_Assembler::emit_exception_handler() { 168 // If the last instruction is a call (typically to do a throw which 169 // is coming at the end after block reordering) the return address 170 // must still point into the code area in order to avoid assertion 171 // failures when searching for the corresponding bci => add a nop 172 // (was bug 5/14/1999 - gri). 173 __ nop(); 174 175 // Generate code for the exception handler. 176 address handler_base = __ start_a_stub(exception_handler_size()); 177 178 if (handler_base == NULL) { 179 // Not enough space left for the handler. 180 bailout("exception handler overflow"); 181 return -1; 182 } 183 184 int offset = code_offset(); 185 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)); 186 //__ load_const_optimized(R0, entry_point); 187 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point)); 188 __ mtctr(R0); 189 __ bctr(); 190 191 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 192 __ end_a_stub(); 193 194 return offset; 195 } 196 197 198 // Emit the code to remove the frame from the stack in the exception 199 // unwind path. 200 int LIR_Assembler::emit_unwind_handler() { 201 _masm->block_comment("Unwind handler"); 202 203 int offset = code_offset(); 204 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes(); 205 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31; 206 207 // Fetch the exception from TLS and clear out exception related thread state. 208 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread); 209 __ li(R0, 0); 210 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread); 211 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread); 212 213 __ bind(_unwind_handler_entry); 214 __ verify_not_null_oop(Rexception); 215 if (preserve_exception) { __ mr(Rexception_save, Rexception); } 216 217 // Perform needed unlocking 218 MonitorExitStub* stub = NULL; 219 if (method()->is_synchronized()) { 220 monitor_address(0, FrameMap::R4_opr); 221 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0); 222 __ unlock_object(R5, R6, R4, *stub->entry()); 223 __ bind(*stub->continuation()); 224 } 225 226 if (compilation()->env()->dtrace_method_probes()) { 227 Unimplemented(); 228 } 229 230 // Dispatch to the unwind logic. 231 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id); 232 //__ load_const_optimized(R0, unwind_stub); 233 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub)); 234 if (preserve_exception) { __ mr(Rexception, Rexception_save); } 235 __ mtctr(R0); 236 __ bctr(); 237 238 // Emit the slow path assembly. 239 if (stub != NULL) { 240 stub->emit_code(this); 241 } 242 243 return offset; 244 } 245 246 247 int LIR_Assembler::emit_deopt_handler() { 248 // If the last instruction is a call (typically to do a throw which 249 // is coming at the end after block reordering) the return address 250 // must still point into the code area in order to avoid assertion 251 // failures when searching for the corresponding bci => add a nop 252 // (was bug 5/14/1999 - gri). 253 __ nop(); 254 255 // Generate code for deopt handler. 256 address handler_base = __ start_a_stub(deopt_handler_size()); 257 258 if (handler_base == NULL) { 259 // Not enough space left for the handler. 260 bailout("deopt handler overflow"); 261 return -1; 262 } 263 264 int offset = code_offset(); 265 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type); 266 267 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 268 __ end_a_stub(); 269 270 return offset; 271 } 272 273 274 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 275 if (o == NULL) { 276 __ li(reg, 0); 277 } else { 278 AddressLiteral addrlit = __ constant_oop_address(o); 279 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg); 280 } 281 } 282 283 284 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 285 // Allocate a new index in table to hold the object once it's been patched. 286 int oop_index = __ oop_recorder()->allocate_oop_index(NULL); 287 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index); 288 289 AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index)); 290 __ load_const(reg, addrlit, R0); 291 292 patching_epilog(patch, lir_patch_normal, reg, info); 293 } 294 295 296 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) { 297 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation) 298 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg); 299 } 300 301 302 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) { 303 // Allocate a new index in table to hold the klass once it's been patched. 304 int index = __ oop_recorder()->allocate_metadata_index(NULL); 305 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index); 306 307 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index)); 308 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc"); 309 __ load_const(reg, addrlit, R0); 310 311 patching_epilog(patch, lir_patch_normal, reg, info); 312 } 313 314 315 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 316 const bool is_int = result->is_single_cpu(); 317 Register Rdividend = is_int ? left->as_register() : left->as_register_lo(); 318 Register Rdivisor = noreg; 319 Register Rscratch = temp->as_register(); 320 Register Rresult = is_int ? result->as_register() : result->as_register_lo(); 321 long divisor = -1; 322 323 if (right->is_register()) { 324 Rdivisor = is_int ? right->as_register() : right->as_register_lo(); 325 } else { 326 divisor = is_int ? right->as_constant_ptr()->as_jint() 327 : right->as_constant_ptr()->as_jlong(); 328 } 329 330 assert(Rdividend != Rscratch, ""); 331 assert(Rdivisor != Rscratch, ""); 332 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv"); 333 334 if (Rdivisor == noreg) { 335 if (divisor == 1) { // stupid, but can happen 336 if (code == lir_idiv) { 337 __ mr_if_needed(Rresult, Rdividend); 338 } else { 339 __ li(Rresult, 0); 340 } 341 342 } else if (is_power_of_2(divisor)) { 343 // Convert division by a power of two into some shifts and logical operations. 344 int log2 = log2_intptr(divisor); 345 346 // Round towards 0. 347 if (divisor == 2) { 348 if (is_int) { 349 __ srwi(Rscratch, Rdividend, 31); 350 } else { 351 __ srdi(Rscratch, Rdividend, 63); 352 } 353 } else { 354 if (is_int) { 355 __ srawi(Rscratch, Rdividend, 31); 356 } else { 357 __ sradi(Rscratch, Rdividend, 63); 358 } 359 __ clrldi(Rscratch, Rscratch, 64-log2); 360 } 361 __ add(Rscratch, Rdividend, Rscratch); 362 363 if (code == lir_idiv) { 364 if (is_int) { 365 __ srawi(Rresult, Rscratch, log2); 366 } else { 367 __ sradi(Rresult, Rscratch, log2); 368 } 369 } else { // lir_irem 370 __ clrrdi(Rscratch, Rscratch, log2); 371 __ sub(Rresult, Rdividend, Rscratch); 372 } 373 374 } else if (divisor == -1) { 375 if (code == lir_idiv) { 376 __ neg(Rresult, Rdividend); 377 } else { 378 __ li(Rresult, 0); 379 } 380 381 } else { 382 __ load_const_optimized(Rscratch, divisor); 383 if (code == lir_idiv) { 384 if (is_int) { 385 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1. 386 } else { 387 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1. 388 } 389 } else { 390 assert(Rscratch != R0, "need both"); 391 if (is_int) { 392 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1. 393 __ mullw(Rscratch, R0, Rscratch); 394 } else { 395 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1. 396 __ mulld(Rscratch, R0, Rscratch); 397 } 398 __ sub(Rresult, Rdividend, Rscratch); 399 } 400 401 } 402 return; 403 } 404 405 Label regular, done; 406 if (is_int) { 407 __ cmpwi(CCR0, Rdivisor, -1); 408 } else { 409 __ cmpdi(CCR0, Rdivisor, -1); 410 } 411 __ bne(CCR0, regular); 412 if (code == lir_idiv) { 413 __ neg(Rresult, Rdividend); 414 __ b(done); 415 __ bind(regular); 416 if (is_int) { 417 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1. 418 } else { 419 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1. 420 } 421 } else { // lir_irem 422 __ li(Rresult, 0); 423 __ b(done); 424 __ bind(regular); 425 if (is_int) { 426 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1. 427 __ mullw(Rscratch, Rscratch, Rdivisor); 428 } else { 429 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1. 430 __ mulld(Rscratch, Rscratch, Rdivisor); 431 } 432 __ sub(Rresult, Rdividend, Rscratch); 433 } 434 __ bind(done); 435 } 436 437 438 void LIR_Assembler::emit_op3(LIR_Op3* op) { 439 switch (op->code()) { 440 case lir_idiv: 441 case lir_irem: 442 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(), 443 op->result_opr(), op->info()); 444 break; 445 case lir_fmad: 446 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(), 447 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg()); 448 break; 449 case lir_fmaf: 450 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(), 451 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg()); 452 break; 453 default: ShouldNotReachHere(); break; 454 } 455 } 456 457 458 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 459 #ifdef ASSERT 460 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 461 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 462 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 463 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); 464 #endif 465 466 Label *L = op->label(); 467 if (op->cond() == lir_cond_always) { 468 __ b(*L); 469 } else { 470 Label done; 471 bool is_unordered = false; 472 if (op->code() == lir_cond_float_branch) { 473 assert(op->ublock() != NULL, "must have unordered successor"); 474 is_unordered = true; 475 } else { 476 assert(op->code() == lir_branch, "just checking"); 477 } 478 479 bool positive = false; 480 Assembler::Condition cond = Assembler::equal; 481 switch (op->cond()) { 482 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break; 483 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break; 484 case lir_cond_less: positive = true ; cond = Assembler::less ; break; 485 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru 486 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break; 487 case lir_cond_greater: positive = true ; cond = Assembler::greater; break; 488 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru 489 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break; 490 default: ShouldNotReachHere(); 491 } 492 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0; 493 int bi = Assembler::bi0(BOOL_RESULT, cond); 494 if (is_unordered) { 495 if (positive) { 496 if (op->ublock() == op->block()) { 497 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L); 498 } 499 } else { 500 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); } 501 } 502 } 503 __ bc_far_optimized(bo, bi, *L); 504 __ bind(done); 505 } 506 } 507 508 509 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 510 Bytecodes::Code code = op->bytecode(); 511 LIR_Opr src = op->in_opr(), 512 dst = op->result_opr(); 513 514 switch(code) { 515 case Bytecodes::_i2l: { 516 __ extsw(dst->as_register_lo(), src->as_register()); 517 break; 518 } 519 case Bytecodes::_l2i: { 520 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage 521 break; 522 } 523 case Bytecodes::_i2b: { 524 __ extsb(dst->as_register(), src->as_register()); 525 break; 526 } 527 case Bytecodes::_i2c: { 528 __ clrldi(dst->as_register(), src->as_register(), 64-16); 529 break; 530 } 531 case Bytecodes::_i2s: { 532 __ extsh(dst->as_register(), src->as_register()); 533 break; 534 } 535 case Bytecodes::_i2d: 536 case Bytecodes::_l2d: { 537 bool src_in_memory = !VM_Version::has_mtfprd(); 538 FloatRegister rdst = dst->as_double_reg(); 539 FloatRegister rsrc; 540 if (src_in_memory) { 541 rsrc = src->as_double_reg(); // via mem 542 } else { 543 // move src to dst register 544 if (code == Bytecodes::_i2d) { 545 __ mtfprwa(rdst, src->as_register()); 546 } else { 547 __ mtfprd(rdst, src->as_register_lo()); 548 } 549 rsrc = rdst; 550 } 551 __ fcfid(rdst, rsrc); 552 break; 553 } 554 case Bytecodes::_i2f: 555 case Bytecodes::_l2f: { 556 bool src_in_memory = !VM_Version::has_mtfprd(); 557 FloatRegister rdst = dst->as_float_reg(); 558 FloatRegister rsrc; 559 if (src_in_memory) { 560 rsrc = src->as_double_reg(); // via mem 561 } else { 562 // move src to dst register 563 if (code == Bytecodes::_i2f) { 564 __ mtfprwa(rdst, src->as_register()); 565 } else { 566 __ mtfprd(rdst, src->as_register_lo()); 567 } 568 rsrc = rdst; 569 } 570 if (VM_Version::has_fcfids()) { 571 __ fcfids(rdst, rsrc); 572 } else { 573 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility"); 574 __ fcfid(rdst, rsrc); 575 __ frsp(rdst, rdst); 576 } 577 break; 578 } 579 case Bytecodes::_f2d: { 580 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg()); 581 break; 582 } 583 case Bytecodes::_d2f: { 584 __ frsp(dst->as_float_reg(), src->as_double_reg()); 585 break; 586 } 587 case Bytecodes::_d2i: 588 case Bytecodes::_f2i: { 589 bool dst_in_memory = !VM_Version::has_mtfprd(); 590 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg(); 591 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL; 592 Label L; 593 // Result must be 0 if value is NaN; test by comparing value to itself. 594 __ fcmpu(CCR0, rsrc, rsrc); 595 if (dst_in_memory) { 596 __ li(R0, 0); // 0 in case of NAN 597 __ std(R0, addr.disp(), addr.base()); 598 } else { 599 __ li(dst->as_register(), 0); 600 } 601 __ bso(CCR0, L); 602 __ fctiwz(rsrc, rsrc); // USE_KILL 603 if (dst_in_memory) { 604 __ stfd(rsrc, addr.disp(), addr.base()); 605 } else { 606 __ mffprd(dst->as_register(), rsrc); 607 } 608 __ bind(L); 609 break; 610 } 611 case Bytecodes::_d2l: 612 case Bytecodes::_f2l: { 613 bool dst_in_memory = !VM_Version::has_mtfprd(); 614 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg(); 615 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL; 616 Label L; 617 // Result must be 0 if value is NaN; test by comparing value to itself. 618 __ fcmpu(CCR0, rsrc, rsrc); 619 if (dst_in_memory) { 620 __ li(R0, 0); // 0 in case of NAN 621 __ std(R0, addr.disp(), addr.base()); 622 } else { 623 __ li(dst->as_register_lo(), 0); 624 } 625 __ bso(CCR0, L); 626 __ fctidz(rsrc, rsrc); // USE_KILL 627 if (dst_in_memory) { 628 __ stfd(rsrc, addr.disp(), addr.base()); 629 } else { 630 __ mffprd(dst->as_register_lo(), rsrc); 631 } 632 __ bind(L); 633 break; 634 } 635 636 default: ShouldNotReachHere(); 637 } 638 } 639 640 641 void LIR_Assembler::align_call(LIR_Code) { 642 // do nothing since all instructions are word aligned on ppc 643 } 644 645 646 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) { 647 int start_offset = __ offset(); 648 // Put the entry point as a constant into the constant pool. 649 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none); 650 if (entry_point_toc_addr == NULL) { 651 bailout("const section overflow"); 652 return false; 653 } 654 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 655 656 // Emit the trampoline stub which will be related to the branch-and-link below. 657 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc); 658 if (!stub) { 659 bailout("no space for trampoline stub"); 660 return false; 661 } 662 return true; 663 } 664 665 666 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 667 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype"); 668 669 bool success = emit_trampoline_stub_for_call(op->addr()); 670 if (!success) { return; } 671 672 __ relocate(rtype); 673 // Note: At this point we do not have the address of the trampoline 674 // stub, and the entry point might be too far away for bl, so __ pc() 675 // serves as dummy and the bl will be patched later. 676 __ code()->set_insts_mark(); 677 __ bl(__ pc()); 678 add_call_info(code_offset(), op->info()); 679 } 680 681 682 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 683 __ calculate_address_from_global_toc(R2_TOC, __ method_toc()); 684 685 // Virtual call relocation will point to ic load. 686 address virtual_call_meta_addr = __ pc(); 687 // Load a clear inline cache. 688 AddressLiteral empty_ic((address) Universe::non_oop_word()); 689 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC); 690 if (!success) { 691 bailout("const section overflow"); 692 return; 693 } 694 // Call to fixup routine. Fixup routine uses ScopeDesc info 695 // to determine who we intended to call. 696 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 697 698 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC); 699 if (!success) { return; } 700 701 // Note: At this point we do not have the address of the trampoline 702 // stub, and the entry point might be too far away for bl, so __ pc() 703 // serves as dummy and the bl will be patched later. 704 __ bl(__ pc()); 705 add_call_info(code_offset(), op->info()); 706 } 707 708 709 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 710 ShouldNotReachHere(); // ic_call is used instead. 711 } 712 713 714 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) { 715 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info); 716 __ null_check(addr, stub->entry()); 717 append_code_stub(stub); 718 } 719 720 721 // Attention: caller must encode oop if needed 722 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) { 723 int store_offset; 724 if (!Assembler::is_simm16(offset)) { 725 // For offsets larger than a simm16 we setup the offset. 726 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case"); 727 __ load_const_optimized(R0, offset); 728 store_offset = store(from_reg, base, R0, type, wide); 729 } else { 730 store_offset = code_offset(); 731 switch (type) { 732 case T_BOOLEAN: // fall through 733 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break; 734 case T_CHAR : 735 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break; 736 case T_INT : __ stw(from_reg->as_register(), offset, base); break; 737 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break; 738 case T_ADDRESS: 739 case T_METADATA: __ std(from_reg->as_register(), offset, base); break; 740 case T_ARRAY : // fall through 741 case T_OBJECT: 742 { 743 if (UseCompressedOops && !wide) { 744 // Encoding done in caller 745 __ stw(from_reg->as_register(), offset, base); 746 } else { 747 __ std(from_reg->as_register(), offset, base); 748 } 749 __ verify_oop(from_reg->as_register()); 750 break; 751 } 752 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break; 753 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break; 754 default : ShouldNotReachHere(); 755 } 756 } 757 return store_offset; 758 } 759 760 761 // Attention: caller must encode oop if needed 762 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) { 763 int store_offset = code_offset(); 764 switch (type) { 765 case T_BOOLEAN: // fall through 766 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break; 767 case T_CHAR : 768 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break; 769 case T_INT : __ stwx(from_reg->as_register(), base, disp); break; 770 case T_LONG : 771 #ifdef _LP64 772 __ stdx(from_reg->as_register_lo(), base, disp); 773 #else 774 Unimplemented(); 775 #endif 776 break; 777 case T_ADDRESS: 778 __ stdx(from_reg->as_register(), base, disp); 779 break; 780 case T_ARRAY : // fall through 781 case T_OBJECT: 782 { 783 if (UseCompressedOops && !wide) { 784 // Encoding done in caller. 785 __ stwx(from_reg->as_register(), base, disp); 786 } else { 787 __ stdx(from_reg->as_register(), base, disp); 788 } 789 __ verify_oop(from_reg->as_register()); // kills R0 790 break; 791 } 792 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break; 793 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break; 794 default : ShouldNotReachHere(); 795 } 796 return store_offset; 797 } 798 799 800 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) { 801 int load_offset; 802 if (!Assembler::is_simm16(offset)) { 803 // For offsets larger than a simm16 we setup the offset. 804 __ load_const_optimized(R0, offset); 805 load_offset = load(base, R0, to_reg, type, wide); 806 } else { 807 load_offset = code_offset(); 808 switch(type) { 809 case T_BOOLEAN: // fall through 810 case T_BYTE : __ lbz(to_reg->as_register(), offset, base); 811 __ extsb(to_reg->as_register(), to_reg->as_register()); break; 812 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break; 813 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break; 814 case T_INT : __ lwa(to_reg->as_register(), offset, base); break; 815 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break; 816 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break; 817 case T_ADDRESS: 818 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) { 819 __ lwz(to_reg->as_register(), offset, base); 820 __ decode_klass_not_null(to_reg->as_register()); 821 } else { 822 __ ld(to_reg->as_register(), offset, base); 823 } 824 break; 825 case T_ARRAY : // fall through 826 case T_OBJECT: 827 { 828 if (UseCompressedOops && !wide) { 829 __ lwz(to_reg->as_register(), offset, base); 830 __ decode_heap_oop(to_reg->as_register()); 831 } else { 832 __ ld(to_reg->as_register(), offset, base); 833 } 834 __ verify_oop(to_reg->as_register()); 835 break; 836 } 837 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break; 838 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break; 839 default : ShouldNotReachHere(); 840 } 841 } 842 return load_offset; 843 } 844 845 846 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) { 847 int load_offset = code_offset(); 848 switch(type) { 849 case T_BOOLEAN: // fall through 850 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp); 851 __ extsb(to_reg->as_register(), to_reg->as_register()); break; 852 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break; 853 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break; 854 case T_INT : __ lwax(to_reg->as_register(), base, disp); break; 855 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break; 856 case T_ARRAY : // fall through 857 case T_OBJECT: 858 { 859 if (UseCompressedOops && !wide) { 860 __ lwzx(to_reg->as_register(), base, disp); 861 __ decode_heap_oop(to_reg->as_register()); 862 } else { 863 __ ldx(to_reg->as_register(), base, disp); 864 } 865 __ verify_oop(to_reg->as_register()); 866 break; 867 } 868 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break; 869 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break; 870 case T_LONG : 871 #ifdef _LP64 872 __ ldx(to_reg->as_register_lo(), base, disp); 873 #else 874 Unimplemented(); 875 #endif 876 break; 877 default : ShouldNotReachHere(); 878 } 879 return load_offset; 880 } 881 882 883 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 884 LIR_Const* c = src->as_constant_ptr(); 885 Register src_reg = R0; 886 switch (c->type()) { 887 case T_INT: 888 case T_FLOAT: { 889 int value = c->as_jint_bits(); 890 __ load_const_optimized(src_reg, value); 891 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 892 __ stw(src_reg, addr.disp(), addr.base()); 893 break; 894 } 895 case T_ADDRESS: { 896 int value = c->as_jint_bits(); 897 __ load_const_optimized(src_reg, value); 898 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 899 __ std(src_reg, addr.disp(), addr.base()); 900 break; 901 } 902 case T_OBJECT: { 903 jobject2reg(c->as_jobject(), src_reg); 904 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 905 __ std(src_reg, addr.disp(), addr.base()); 906 break; 907 } 908 case T_LONG: 909 case T_DOUBLE: { 910 int value = c->as_jlong_bits(); 911 __ load_const_optimized(src_reg, value); 912 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); 913 __ std(src_reg, addr.disp(), addr.base()); 914 break; 915 } 916 default: 917 Unimplemented(); 918 } 919 } 920 921 922 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 923 LIR_Const* c = src->as_constant_ptr(); 924 LIR_Address* addr = dest->as_address_ptr(); 925 Register base = addr->base()->as_pointer_register(); 926 LIR_Opr tmp = LIR_OprFact::illegalOpr; 927 int offset = -1; 928 // Null check for large offsets in LIRGenerator::do_StoreField. 929 bool needs_explicit_null_check = !ImplicitNullChecks; 930 931 if (info != NULL && needs_explicit_null_check) { 932 explicit_null_check(base, info); 933 } 934 935 switch (c->type()) { 936 case T_FLOAT: type = T_INT; 937 case T_INT: 938 case T_ADDRESS: { 939 tmp = FrameMap::R0_opr; 940 __ load_const_optimized(tmp->as_register(), c->as_jint_bits()); 941 break; 942 } 943 case T_DOUBLE: type = T_LONG; 944 case T_LONG: { 945 tmp = FrameMap::R0_long_opr; 946 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits()); 947 break; 948 } 949 case T_OBJECT: { 950 tmp = FrameMap::R0_opr; 951 if (UseCompressedOops && !wide && c->as_jobject() != NULL) { 952 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject()); 953 __ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw). 954 __ relocate(oop_addr.rspec(), /*compressed format*/ 1); 955 __ ori(R0, R0, oop_addr.value() & 0xffff); 956 } else { 957 jobject2reg(c->as_jobject(), R0); 958 } 959 break; 960 } 961 default: 962 Unimplemented(); 963 } 964 965 // Handle either reg+reg or reg+disp address. 966 if (addr->index()->is_valid()) { 967 assert(addr->disp() == 0, "must be zero"); 968 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); 969 } else { 970 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses"); 971 offset = store(tmp, base, addr->disp(), type, wide, false); 972 } 973 974 if (info != NULL) { 975 assert(offset != -1, "offset should've been set"); 976 if (!needs_explicit_null_check) { 977 add_debug_info_for_null_check(offset, info); 978 } 979 } 980 } 981 982 983 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 984 LIR_Const* c = src->as_constant_ptr(); 985 LIR_Opr to_reg = dest; 986 987 switch (c->type()) { 988 case T_INT: { 989 assert(patch_code == lir_patch_none, "no patching handled here"); 990 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); 991 break; 992 } 993 case T_ADDRESS: { 994 assert(patch_code == lir_patch_none, "no patching handled here"); 995 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ... 996 break; 997 } 998 case T_LONG: { 999 assert(patch_code == lir_patch_none, "no patching handled here"); 1000 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0); 1001 break; 1002 } 1003 1004 case T_OBJECT: { 1005 if (patch_code == lir_patch_none) { 1006 jobject2reg(c->as_jobject(), to_reg->as_register()); 1007 } else { 1008 jobject2reg_with_patching(to_reg->as_register(), info); 1009 } 1010 break; 1011 } 1012 1013 case T_METADATA: 1014 { 1015 if (patch_code == lir_patch_none) { 1016 metadata2reg(c->as_metadata(), to_reg->as_register()); 1017 } else { 1018 klass2reg_with_patching(to_reg->as_register(), info); 1019 } 1020 } 1021 break; 1022 1023 case T_FLOAT: 1024 { 1025 if (to_reg->is_single_fpu()) { 1026 address const_addr = __ float_constant(c->as_jfloat()); 1027 if (const_addr == NULL) { 1028 bailout("const section overflow"); 1029 break; 1030 } 1031 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1032 __ relocate(rspec); 1033 __ load_const(R0, const_addr); 1034 __ lfsx(to_reg->as_float_reg(), R0); 1035 } else { 1036 assert(to_reg->is_single_cpu(), "Must be a cpu register."); 1037 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0); 1038 } 1039 } 1040 break; 1041 1042 case T_DOUBLE: 1043 { 1044 if (to_reg->is_double_fpu()) { 1045 address const_addr = __ double_constant(c->as_jdouble()); 1046 if (const_addr == NULL) { 1047 bailout("const section overflow"); 1048 break; 1049 } 1050 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1051 __ relocate(rspec); 1052 __ load_const(R0, const_addr); 1053 __ lfdx(to_reg->as_double_reg(), R0); 1054 } else { 1055 assert(to_reg->is_double_cpu(), "Must be a long register."); 1056 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0); 1057 } 1058 } 1059 break; 1060 1061 default: 1062 ShouldNotReachHere(); 1063 } 1064 } 1065 1066 1067 Address LIR_Assembler::as_Address(LIR_Address* addr) { 1068 Unimplemented(); return Address(); 1069 } 1070 1071 1072 inline RegisterOrConstant index_or_disp(LIR_Address* addr) { 1073 if (addr->index()->is_illegal()) { 1074 return (RegisterOrConstant)(addr->disp()); 1075 } else { 1076 return (RegisterOrConstant)(addr->index()->as_pointer_register()); 1077 } 1078 } 1079 1080 1081 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1082 const Register tmp = R0; 1083 switch (type) { 1084 case T_INT: 1085 case T_FLOAT: { 1086 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1087 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1088 __ lwz(tmp, from.disp(), from.base()); 1089 __ stw(tmp, to.disp(), to.base()); 1090 break; 1091 } 1092 case T_ADDRESS: 1093 case T_OBJECT: { 1094 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1095 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1096 __ ld(tmp, from.disp(), from.base()); 1097 __ std(tmp, to.disp(), to.base()); 1098 break; 1099 } 1100 case T_LONG: 1101 case T_DOUBLE: { 1102 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); 1103 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1104 __ ld(tmp, from.disp(), from.base()); 1105 __ std(tmp, to.disp(), to.base()); 1106 break; 1107 } 1108 1109 default: 1110 ShouldNotReachHere(); 1111 } 1112 } 1113 1114 1115 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 1116 Unimplemented(); return Address(); 1117 } 1118 1119 1120 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 1121 Unimplemented(); return Address(); 1122 } 1123 1124 1125 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, 1126 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) { 1127 1128 assert(type != T_METADATA, "load of metadata ptr not supported"); 1129 LIR_Address* addr = src_opr->as_address_ptr(); 1130 LIR_Opr to_reg = dest; 1131 1132 Register src = addr->base()->as_pointer_register(); 1133 Register disp_reg = noreg; 1134 int disp_value = addr->disp(); 1135 bool needs_patching = (patch_code != lir_patch_none); 1136 // null check for large offsets in LIRGenerator::do_LoadField 1137 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks; 1138 1139 if (info != NULL && needs_explicit_null_check) { 1140 explicit_null_check(src, info); 1141 } 1142 1143 if (addr->base()->type() == T_OBJECT) { 1144 __ verify_oop(src); 1145 } 1146 1147 PatchingStub* patch = NULL; 1148 if (needs_patching) { 1149 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1150 assert(!to_reg->is_double_cpu() || 1151 patch_code == lir_patch_none || 1152 patch_code == lir_patch_normal, "patching doesn't match register"); 1153 } 1154 1155 if (addr->index()->is_illegal()) { 1156 if (!Assembler::is_simm16(disp_value)) { 1157 if (needs_patching) { 1158 __ load_const32(R0, 0); // patchable int 1159 } else { 1160 __ load_const_optimized(R0, disp_value); 1161 } 1162 disp_reg = R0; 1163 } 1164 } else { 1165 disp_reg = addr->index()->as_pointer_register(); 1166 assert(disp_value == 0, "can't handle 3 operand addresses"); 1167 } 1168 1169 // Remember the offset of the load. The patching_epilog must be done 1170 // before the call to add_debug_info, otherwise the PcDescs don't get 1171 // entered in increasing order. 1172 int offset; 1173 1174 if (disp_reg == noreg) { 1175 assert(Assembler::is_simm16(disp_value), "should have set this up"); 1176 offset = load(src, disp_value, to_reg, type, wide, unaligned); 1177 } else { 1178 assert(!unaligned, "unexpected"); 1179 offset = load(src, disp_reg, to_reg, type, wide); 1180 } 1181 1182 if (patch != NULL) { 1183 patching_epilog(patch, patch_code, src, info); 1184 } 1185 if (info != NULL && !needs_explicit_null_check) { 1186 add_debug_info_for_null_check(offset, info); 1187 } 1188 } 1189 1190 1191 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1192 Address addr; 1193 if (src->is_single_word()) { 1194 addr = frame_map()->address_for_slot(src->single_stack_ix()); 1195 } else if (src->is_double_word()) { 1196 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); 1197 } 1198 1199 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1200 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned); 1201 } 1202 1203 1204 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 1205 Address addr; 1206 if (dest->is_single_word()) { 1207 addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1208 } else if (dest->is_double_word()) { 1209 addr = frame_map()->address_for_slot(dest->double_stack_ix()); 1210 } 1211 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1212 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned); 1213 } 1214 1215 1216 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { 1217 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { 1218 if (from_reg->is_double_fpu()) { 1219 // double to double moves 1220 assert(to_reg->is_double_fpu(), "should match"); 1221 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg()); 1222 } else { 1223 // float to float moves 1224 assert(to_reg->is_single_fpu(), "should match"); 1225 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg()); 1226 } 1227 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { 1228 if (from_reg->is_double_cpu()) { 1229 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register()); 1230 } else if (to_reg->is_double_cpu()) { 1231 // int to int moves 1232 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register()); 1233 } else { 1234 // int to int moves 1235 __ mr_if_needed(to_reg->as_register(), from_reg->as_register()); 1236 } 1237 } else { 1238 ShouldNotReachHere(); 1239 } 1240 if (is_reference_type(to_reg->type())) { 1241 __ verify_oop(to_reg->as_register()); 1242 } 1243 } 1244 1245 1246 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, 1247 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, 1248 bool wide, bool unaligned) { 1249 assert(type != T_METADATA, "store of metadata ptr not supported"); 1250 LIR_Address* addr = dest->as_address_ptr(); 1251 1252 Register src = addr->base()->as_pointer_register(); 1253 Register disp_reg = noreg; 1254 int disp_value = addr->disp(); 1255 bool needs_patching = (patch_code != lir_patch_none); 1256 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide && 1257 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop; 1258 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value); 1259 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29. 1260 // Null check for large offsets in LIRGenerator::do_StoreField. 1261 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29; 1262 1263 if (info != NULL && needs_explicit_null_check) { 1264 explicit_null_check(src, info); 1265 } 1266 1267 if (addr->base()->is_oop_register()) { 1268 __ verify_oop(src); 1269 } 1270 1271 PatchingStub* patch = NULL; 1272 if (needs_patching) { 1273 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1274 assert(!from_reg->is_double_cpu() || 1275 patch_code == lir_patch_none || 1276 patch_code == lir_patch_normal, "patching doesn't match register"); 1277 } 1278 1279 if (addr->index()->is_illegal()) { 1280 if (load_disp) { 1281 disp_reg = use_R29 ? R29_TOC : R0; 1282 if (needs_patching) { 1283 __ load_const32(disp_reg, 0); // patchable int 1284 } else { 1285 __ load_const_optimized(disp_reg, disp_value); 1286 } 1287 } 1288 } else { 1289 disp_reg = addr->index()->as_pointer_register(); 1290 assert(disp_value == 0, "can't handle 3 operand addresses"); 1291 } 1292 1293 // remember the offset of the store. The patching_epilog must be done 1294 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get 1295 // entered in increasing order. 1296 int offset; 1297 1298 if (compress_oop) { 1299 Register co = __ encode_heap_oop(R0, from_reg->as_register()); 1300 from_reg = FrameMap::as_opr(co); 1301 } 1302 1303 if (disp_reg == noreg) { 1304 assert(Assembler::is_simm16(disp_value), "should have set this up"); 1305 offset = store(from_reg, src, disp_value, type, wide, unaligned); 1306 } else { 1307 assert(!unaligned, "unexpected"); 1308 offset = store(from_reg, src, disp_reg, type, wide); 1309 } 1310 1311 if (use_R29) { 1312 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit 1313 } 1314 1315 if (patch != NULL) { 1316 patching_epilog(patch, patch_code, src, info); 1317 } 1318 1319 if (info != NULL && !needs_explicit_null_check) { 1320 add_debug_info_for_null_check(offset, info); 1321 } 1322 } 1323 1324 1325 void LIR_Assembler::return_op(LIR_Opr result) { 1326 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone(). 1327 const Register polling_page = R12; 1328 1329 // Pop the stack before the safepoint code. 1330 int frame_size = initial_frame_size_in_bytes(); 1331 if (Assembler::is_simm(frame_size, 16)) { 1332 __ addi(R1_SP, R1_SP, frame_size); 1333 } else { 1334 __ pop_frame(); 1335 } 1336 1337 if (SafepointMechanism::uses_thread_local_poll()) { 1338 __ ld(polling_page, in_bytes(Thread::polling_page_offset()), R16_thread); 1339 } else { 1340 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page(), R0); 1341 } 1342 1343 // Restore return pc relative to callers' sp. 1344 __ ld(return_pc, _abi(lr), R1_SP); 1345 // Move return pc to LR. 1346 __ mtlr(return_pc); 1347 1348 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 1349 __ reserved_stack_check(return_pc); 1350 } 1351 1352 // We need to mark the code position where the load from the safepoint 1353 // polling page was emitted as relocInfo::poll_return_type here. 1354 __ relocate(relocInfo::poll_return_type); 1355 __ load_from_polling_page(polling_page); 1356 1357 // Return. 1358 __ blr(); 1359 } 1360 1361 1362 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 1363 const Register poll_addr = tmp->as_register(); 1364 if (SafepointMechanism::uses_thread_local_poll()) { 1365 __ ld(poll_addr, in_bytes(Thread::polling_page_offset()), R16_thread); 1366 } else { 1367 __ load_const_optimized(poll_addr, (intptr_t)os::get_polling_page(), R0); 1368 } 1369 if (info != NULL) { 1370 add_debug_info_for_branch(info); 1371 } 1372 int offset = __ offset(); 1373 __ relocate(relocInfo::poll_type); 1374 __ load_from_polling_page(poll_addr); 1375 1376 return offset; 1377 } 1378 1379 1380 void LIR_Assembler::emit_static_call_stub() { 1381 address call_pc = __ pc(); 1382 address stub = __ start_a_stub(static_call_stub_size()); 1383 if (stub == NULL) { 1384 bailout("static call stub overflow"); 1385 return; 1386 } 1387 1388 // For java_to_interp stubs we use R11_scratch1 as scratch register 1389 // and in call trampoline stubs we use R12_scratch2. This way we 1390 // can distinguish them (see is_NativeCallTrampolineStub_at()). 1391 const Register reg_scratch = R11_scratch1; 1392 1393 // Create a static stub relocation which relates this stub 1394 // with the call instruction at insts_call_instruction_offset in the 1395 // instructions code-section. 1396 int start = __ offset(); 1397 __ relocate(static_stub_Relocation::spec(call_pc)); 1398 1399 // Now, create the stub's code: 1400 // - load the TOC 1401 // - load the inline cache oop from the constant pool 1402 // - load the call target from the constant pool 1403 // - call 1404 __ calculate_address_from_global_toc(reg_scratch, __ method_toc()); 1405 AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL); 1406 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true); 1407 1408 if (ReoptimizeCallSequences) { 1409 __ b64_patchable((address)-1, relocInfo::none); 1410 } else { 1411 AddressLiteral a((address)-1); 1412 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true); 1413 __ mtctr(reg_scratch); 1414 __ bctr(); 1415 } 1416 if (!success) { 1417 bailout("const section overflow"); 1418 return; 1419 } 1420 1421 assert(__ offset() - start <= static_call_stub_size(), "stub too big"); 1422 __ end_a_stub(); 1423 } 1424 1425 1426 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1427 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual); 1428 if (opr1->is_single_fpu()) { 1429 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg()); 1430 } else if (opr1->is_double_fpu()) { 1431 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg()); 1432 } else if (opr1->is_single_cpu()) { 1433 if (opr2->is_constant()) { 1434 switch (opr2->as_constant_ptr()->type()) { 1435 case T_INT: 1436 { 1437 jint con = opr2->as_constant_ptr()->as_jint(); 1438 if (unsigned_comp) { 1439 if (Assembler::is_uimm(con, 16)) { 1440 __ cmplwi(BOOL_RESULT, opr1->as_register(), con); 1441 } else { 1442 __ load_const_optimized(R0, con); 1443 __ cmplw(BOOL_RESULT, opr1->as_register(), R0); 1444 } 1445 } else { 1446 if (Assembler::is_simm(con, 16)) { 1447 __ cmpwi(BOOL_RESULT, opr1->as_register(), con); 1448 } else { 1449 __ load_const_optimized(R0, con); 1450 __ cmpw(BOOL_RESULT, opr1->as_register(), R0); 1451 } 1452 } 1453 } 1454 break; 1455 1456 case T_OBJECT: 1457 // There are only equal/notequal comparisons on objects. 1458 { 1459 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); 1460 jobject con = opr2->as_constant_ptr()->as_jobject(); 1461 if (con == NULL) { 1462 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0); 1463 } else { 1464 jobject2reg(con, R0); 1465 __ cmpd(BOOL_RESULT, opr1->as_register(), R0); 1466 } 1467 } 1468 break; 1469 1470 default: 1471 ShouldNotReachHere(); 1472 break; 1473 } 1474 } else { 1475 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported"); 1476 if (is_reference_type(opr1->type())) { 1477 // There are only equal/notequal comparisons on objects. 1478 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); 1479 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register()); 1480 } else { 1481 if (unsigned_comp) { 1482 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register()); 1483 } else { 1484 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register()); 1485 } 1486 } 1487 } 1488 } else if (opr1->is_double_cpu()) { 1489 if (opr2->is_constant()) { 1490 jlong con = opr2->as_constant_ptr()->as_jlong(); 1491 if (unsigned_comp) { 1492 if (Assembler::is_uimm(con, 16)) { 1493 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con); 1494 } else { 1495 __ load_const_optimized(R0, con); 1496 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0); 1497 } 1498 } else { 1499 if (Assembler::is_simm(con, 16)) { 1500 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con); 1501 } else { 1502 __ load_const_optimized(R0, con); 1503 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0); 1504 } 1505 } 1506 } else if (opr2->is_register()) { 1507 if (unsigned_comp) { 1508 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo()); 1509 } else { 1510 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo()); 1511 } 1512 } else { 1513 ShouldNotReachHere(); 1514 } 1515 } else { 1516 ShouldNotReachHere(); 1517 } 1518 } 1519 1520 1521 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 1522 const Register Rdst = dst->as_register(); 1523 Label done; 1524 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1525 bool is_unordered_less = (code == lir_ucmp_fd2i); 1526 if (left->is_single_fpu()) { 1527 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg()); 1528 } else if (left->is_double_fpu()) { 1529 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg()); 1530 } else { 1531 ShouldNotReachHere(); 1532 } 1533 __ li(Rdst, is_unordered_less ? -1 : 1); 1534 __ bso(CCR0, done); 1535 } else if (code == lir_cmp_l2i) { 1536 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo()); 1537 } else { 1538 ShouldNotReachHere(); 1539 } 1540 __ mfcr(R0); // set bit 32..33 as follows: <: 0b10, =: 0b00, >: 0b01 1541 __ srwi(Rdst, R0, 30); 1542 __ srawi(R0, R0, 31); 1543 __ orr(Rdst, R0, Rdst); // set result as follows: <: -1, =: 0, >: 1 1544 __ bind(done); 1545 } 1546 1547 1548 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) { 1549 if (src->is_constant()) { 1550 lasm->const2reg(src, dst, lir_patch_none, NULL); 1551 } else if (src->is_register()) { 1552 lasm->reg2reg(src, dst); 1553 } else if (src->is_stack()) { 1554 lasm->stack2reg(src, dst, dst->type()); 1555 } else { 1556 ShouldNotReachHere(); 1557 } 1558 } 1559 1560 1561 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1562 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) { 1563 load_to_reg(this, opr1, result); // Condition doesn't matter. 1564 return; 1565 } 1566 1567 bool positive = false; 1568 Assembler::Condition cond = Assembler::equal; 1569 switch (condition) { 1570 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break; 1571 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break; 1572 case lir_cond_less: positive = true ; cond = Assembler::less ; break; 1573 case lir_cond_belowEqual: 1574 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break; 1575 case lir_cond_greater: positive = true ; cond = Assembler::greater; break; 1576 case lir_cond_aboveEqual: 1577 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break; 1578 default: ShouldNotReachHere(); 1579 } 1580 1581 // Try to use isel on >=Power7. 1582 if (VM_Version::has_isel() && result->is_cpu_register()) { 1583 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register(); 1584 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo(); 1585 1586 // We can use result_reg to load one operand if not already in register. 1587 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg, 1588 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg; 1589 1590 if (first != second) { 1591 if (!o1_is_reg) { 1592 load_to_reg(this, opr1, result); 1593 } 1594 1595 if (!o2_is_reg) { 1596 load_to_reg(this, opr2, result); 1597 } 1598 1599 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second); 1600 return; 1601 } 1602 } // isel 1603 1604 load_to_reg(this, opr1, result); 1605 1606 Label skip; 1607 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0; 1608 int bi = Assembler::bi0(BOOL_RESULT, cond); 1609 __ bc(bo, bi, skip); 1610 1611 load_to_reg(this, opr2, result); 1612 __ bind(skip); 1613 } 1614 1615 1616 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, 1617 CodeEmitInfo* info, bool pop_fpu_stack) { 1618 assert(info == NULL, "unused on this code path"); 1619 assert(left->is_register(), "wrong items state"); 1620 assert(dest->is_register(), "wrong items state"); 1621 1622 if (right->is_register()) { 1623 if (dest->is_float_kind()) { 1624 1625 FloatRegister lreg, rreg, res; 1626 if (right->is_single_fpu()) { 1627 lreg = left->as_float_reg(); 1628 rreg = right->as_float_reg(); 1629 res = dest->as_float_reg(); 1630 switch (code) { 1631 case lir_add: __ fadds(res, lreg, rreg); break; 1632 case lir_sub: __ fsubs(res, lreg, rreg); break; 1633 case lir_mul: // fall through 1634 case lir_mul_strictfp: __ fmuls(res, lreg, rreg); break; 1635 case lir_div: // fall through 1636 case lir_div_strictfp: __ fdivs(res, lreg, rreg); break; 1637 default: ShouldNotReachHere(); 1638 } 1639 } else { 1640 lreg = left->as_double_reg(); 1641 rreg = right->as_double_reg(); 1642 res = dest->as_double_reg(); 1643 switch (code) { 1644 case lir_add: __ fadd(res, lreg, rreg); break; 1645 case lir_sub: __ fsub(res, lreg, rreg); break; 1646 case lir_mul: // fall through 1647 case lir_mul_strictfp: __ fmul(res, lreg, rreg); break; 1648 case lir_div: // fall through 1649 case lir_div_strictfp: __ fdiv(res, lreg, rreg); break; 1650 default: ShouldNotReachHere(); 1651 } 1652 } 1653 1654 } else if (dest->is_double_cpu()) { 1655 1656 Register dst_lo = dest->as_register_lo(); 1657 Register op1_lo = left->as_pointer_register(); 1658 Register op2_lo = right->as_pointer_register(); 1659 1660 switch (code) { 1661 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break; 1662 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break; 1663 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break; 1664 default: ShouldNotReachHere(); 1665 } 1666 } else { 1667 assert (right->is_single_cpu(), "Just Checking"); 1668 1669 Register lreg = left->as_register(); 1670 Register res = dest->as_register(); 1671 Register rreg = right->as_register(); 1672 switch (code) { 1673 case lir_add: __ add (res, lreg, rreg); break; 1674 case lir_sub: __ sub (res, lreg, rreg); break; 1675 case lir_mul: __ mullw(res, lreg, rreg); break; 1676 default: ShouldNotReachHere(); 1677 } 1678 } 1679 } else { 1680 assert (right->is_constant(), "must be constant"); 1681 1682 if (dest->is_single_cpu()) { 1683 Register lreg = left->as_register(); 1684 Register res = dest->as_register(); 1685 int simm16 = right->as_constant_ptr()->as_jint(); 1686 1687 switch (code) { 1688 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int 1689 simm16 = -simm16; 1690 case lir_add: if (res == lreg && simm16 == 0) break; 1691 __ addi(res, lreg, simm16); break; 1692 case lir_mul: if (res == lreg && simm16 == 1) break; 1693 __ mulli(res, lreg, simm16); break; 1694 default: ShouldNotReachHere(); 1695 } 1696 } else { 1697 Register lreg = left->as_pointer_register(); 1698 Register res = dest->as_register_lo(); 1699 long con = right->as_constant_ptr()->as_jlong(); 1700 assert(Assembler::is_simm16(con), "must be simm16"); 1701 1702 switch (code) { 1703 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long 1704 con = -con; 1705 case lir_add: if (res == lreg && con == 0) break; 1706 __ addi(res, lreg, (int)con); break; 1707 case lir_mul: if (res == lreg && con == 1) break; 1708 __ mulli(res, lreg, (int)con); break; 1709 default: ShouldNotReachHere(); 1710 } 1711 } 1712 } 1713 } 1714 1715 1716 void LIR_Assembler::fpop() { 1717 Unimplemented(); 1718 // do nothing 1719 } 1720 1721 1722 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { 1723 switch (code) { 1724 case lir_sqrt: { 1725 __ fsqrt(dest->as_double_reg(), value->as_double_reg()); 1726 break; 1727 } 1728 case lir_abs: { 1729 __ fabs(dest->as_double_reg(), value->as_double_reg()); 1730 break; 1731 } 1732 default: { 1733 ShouldNotReachHere(); 1734 break; 1735 } 1736 } 1737 } 1738 1739 1740 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { 1741 if (right->is_constant()) { // see do_LogicOp 1742 long uimm; 1743 Register d, l; 1744 if (dest->is_single_cpu()) { 1745 uimm = right->as_constant_ptr()->as_jint(); 1746 d = dest->as_register(); 1747 l = left->as_register(); 1748 } else { 1749 uimm = right->as_constant_ptr()->as_jlong(); 1750 d = dest->as_register_lo(); 1751 l = left->as_register_lo(); 1752 } 1753 long uimms = (unsigned long)uimm >> 16, 1754 uimmss = (unsigned long)uimm >> 32; 1755 1756 switch (code) { 1757 case lir_logic_and: 1758 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2_long(uimm)) { 1759 __ andi(d, l, uimm); // special cases 1760 } else if (uimms != 0) { __ andis_(d, l, uimms); } 1761 else { __ andi_(d, l, uimm); } 1762 break; 1763 1764 case lir_logic_or: 1765 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); } 1766 else { __ ori(d, l, uimm); } 1767 break; 1768 1769 case lir_logic_xor: 1770 if (uimm == -1) { __ nand(d, l, l); } // special case 1771 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); } 1772 else { __ xori(d, l, uimm); } 1773 break; 1774 1775 default: ShouldNotReachHere(); 1776 } 1777 } else { 1778 assert(right->is_register(), "right should be in register"); 1779 1780 if (dest->is_single_cpu()) { 1781 switch (code) { 1782 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break; 1783 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break; 1784 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break; 1785 default: ShouldNotReachHere(); 1786 } 1787 } else { 1788 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : 1789 left->as_register_lo(); 1790 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : 1791 right->as_register_lo(); 1792 1793 switch (code) { 1794 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break; 1795 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break; 1796 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break; 1797 default: ShouldNotReachHere(); 1798 } 1799 } 1800 } 1801 } 1802 1803 1804 int LIR_Assembler::shift_amount(BasicType t) { 1805 int elem_size = type2aelembytes(t); 1806 switch (elem_size) { 1807 case 1 : return 0; 1808 case 2 : return 1; 1809 case 4 : return 2; 1810 case 8 : return 3; 1811 } 1812 ShouldNotReachHere(); 1813 return -1; 1814 } 1815 1816 1817 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 1818 info->add_register_oop(exceptionOop); 1819 1820 // Reuse the debug info from the safepoint poll for the throw op itself. 1821 address pc_for_athrow = __ pc(); 1822 int pc_for_athrow_offset = __ offset(); 1823 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); 1824 //__ relocate(rspec); 1825 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0); 1826 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true); 1827 add_call_info(pc_for_athrow_offset, info); // for exception handler 1828 1829 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id 1830 : Runtime1::handle_exception_nofpu_id); 1831 //__ load_const_optimized(R0, stub); 1832 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub)); 1833 __ mtctr(R0); 1834 __ bctr(); 1835 } 1836 1837 1838 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 1839 // Note: Not used with EnableDebuggingOnDemand. 1840 assert(exceptionOop->as_register() == R3, "should match"); 1841 __ b(_unwind_handler_entry); 1842 } 1843 1844 1845 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 1846 Register src = op->src()->as_register(); 1847 Register dst = op->dst()->as_register(); 1848 Register src_pos = op->src_pos()->as_register(); 1849 Register dst_pos = op->dst_pos()->as_register(); 1850 Register length = op->length()->as_register(); 1851 Register tmp = op->tmp()->as_register(); 1852 Register tmp2 = R0; 1853 1854 int flags = op->flags(); 1855 ciArrayKlass* default_type = op->expected_type(); 1856 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 1857 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 1858 1859 // Set up the arraycopy stub information. 1860 ArrayCopyStub* stub = op->stub(); 1861 const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame. 1862 1863 // Always do stub if no type information is available. It's ok if 1864 // the known type isn't loaded since the code sanity checks 1865 // in debug mode and the type isn't required when we know the exact type 1866 // also check that the type is an array type. 1867 if (op->expected_type() == NULL) { 1868 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() && 1869 length->is_nonvolatile(), "must preserve"); 1870 address copyfunc_addr = StubRoutines::generic_arraycopy(); 1871 assert(copyfunc_addr != NULL, "generic arraycopy stub required"); 1872 1873 // 3 parms are int. Convert to long. 1874 __ mr(R3_ARG1, src); 1875 __ extsw(R4_ARG2, src_pos); 1876 __ mr(R5_ARG3, dst); 1877 __ extsw(R6_ARG4, dst_pos); 1878 __ extsw(R7_ARG5, length); 1879 1880 #ifndef PRODUCT 1881 if (PrintC1Statistics) { 1882 address counter = (address)&Runtime1::_generic_arraycopystub_cnt; 1883 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 1884 __ lwz(R11_scratch1, simm16_offs, tmp); 1885 __ addi(R11_scratch1, R11_scratch1, 1); 1886 __ stw(R11_scratch1, simm16_offs, tmp); 1887 } 1888 #endif 1889 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0); 1890 1891 __ nand(tmp, R3_RET, R3_RET); 1892 __ subf(length, tmp, length); 1893 __ add(src_pos, tmp, src_pos); 1894 __ add(dst_pos, tmp, dst_pos); 1895 1896 __ cmpwi(CCR0, R3_RET, 0); 1897 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry()); 1898 __ bind(*stub->continuation()); 1899 return; 1900 } 1901 1902 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); 1903 Label cont, slow, copyfunc; 1904 1905 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check | 1906 LIR_OpArrayCopy::dst_null_check | 1907 LIR_OpArrayCopy::src_pos_positive_check | 1908 LIR_OpArrayCopy::dst_pos_positive_check | 1909 LIR_OpArrayCopy::length_positive_check); 1910 1911 // Use only one conditional branch for simple checks. 1912 if (simple_check_flag_set) { 1913 ConditionRegister combined_check = CCR1, tmp_check = CCR1; 1914 1915 // Make sure src and dst are non-null. 1916 if (flags & LIR_OpArrayCopy::src_null_check) { 1917 __ cmpdi(combined_check, src, 0); 1918 tmp_check = CCR0; 1919 } 1920 1921 if (flags & LIR_OpArrayCopy::dst_null_check) { 1922 __ cmpdi(tmp_check, dst, 0); 1923 if (tmp_check != combined_check) { 1924 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal); 1925 } 1926 tmp_check = CCR0; 1927 } 1928 1929 // Clear combined_check.eq if not already used. 1930 if (tmp_check == combined_check) { 1931 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal); 1932 tmp_check = CCR0; 1933 } 1934 1935 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 1936 // Test src_pos register. 1937 __ cmpwi(tmp_check, src_pos, 0); 1938 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less); 1939 } 1940 1941 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 1942 // Test dst_pos register. 1943 __ cmpwi(tmp_check, dst_pos, 0); 1944 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less); 1945 } 1946 1947 if (flags & LIR_OpArrayCopy::length_positive_check) { 1948 // Make sure length isn't negative. 1949 __ cmpwi(tmp_check, length, 0); 1950 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less); 1951 } 1952 1953 __ beq(combined_check, slow); 1954 } 1955 1956 // If the compiler was not able to prove that exact type of the source or the destination 1957 // of the arraycopy is an array type, check at runtime if the source or the destination is 1958 // an instance type. 1959 if (flags & LIR_OpArrayCopy::type_check) { 1960 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 1961 __ load_klass(tmp, dst); 1962 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp); 1963 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value); 1964 __ bge(CCR0, slow); 1965 } 1966 1967 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 1968 __ load_klass(tmp, src); 1969 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp); 1970 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value); 1971 __ bge(CCR0, slow); 1972 } 1973 } 1974 1975 // Higher 32bits must be null. 1976 __ extsw(length, length); 1977 1978 __ extsw(src_pos, src_pos); 1979 if (flags & LIR_OpArrayCopy::src_range_check) { 1980 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src); 1981 __ add(tmp, length, src_pos); 1982 __ cmpld(CCR0, tmp2, tmp); 1983 __ ble(CCR0, slow); 1984 } 1985 1986 __ extsw(dst_pos, dst_pos); 1987 if (flags & LIR_OpArrayCopy::dst_range_check) { 1988 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst); 1989 __ add(tmp, length, dst_pos); 1990 __ cmpld(CCR0, tmp2, tmp); 1991 __ ble(CCR0, slow); 1992 } 1993 1994 int shift = shift_amount(basic_type); 1995 1996 if (!(flags & LIR_OpArrayCopy::type_check)) { 1997 __ b(cont); 1998 } else { 1999 // We don't know the array types are compatible. 2000 if (basic_type != T_OBJECT) { 2001 // Simple test for basic type arrays. 2002 if (UseCompressedClassPointers) { 2003 // We don't need decode because we just need to compare. 2004 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src); 2005 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst); 2006 __ cmpw(CCR0, tmp, tmp2); 2007 } else { 2008 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src); 2009 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst); 2010 __ cmpd(CCR0, tmp, tmp2); 2011 } 2012 __ beq(CCR0, cont); 2013 } else { 2014 // For object arrays, if src is a sub class of dst then we can 2015 // safely do the copy. 2016 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 2017 2018 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf 2019 assert_different_registers(tmp, tmp2, sub_klass, super_klass); 2020 2021 __ load_klass(sub_klass, src); 2022 __ load_klass(super_klass, dst); 2023 2024 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2, 2025 &cont, copyfunc_addr != NULL ? ©func : &slow, NULL); 2026 2027 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id); 2028 //__ load_const_optimized(tmp, slow_stc, tmp2); 2029 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false); 2030 __ mtctr(tmp); 2031 __ bctrl(); // sets CR0 2032 __ beq(CCR0, cont); 2033 2034 if (copyfunc_addr != NULL) { // Use stub if available. 2035 __ bind(copyfunc); 2036 // Src is not a sub class of dst so we have to do a 2037 // per-element check. 2038 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2039 if ((flags & mask) != mask) { 2040 assert(flags & mask, "one of the two should be known to be an object array"); 2041 2042 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2043 __ load_klass(tmp, src); 2044 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2045 __ load_klass(tmp, dst); 2046 } 2047 2048 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp); 2049 2050 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2051 __ load_const_optimized(tmp, objArray_lh); 2052 __ cmpw(CCR0, tmp, tmp2); 2053 __ bne(CCR0, slow); 2054 } 2055 2056 Register src_ptr = R3_ARG1; 2057 Register dst_ptr = R4_ARG2; 2058 Register len = R5_ARG3; 2059 Register chk_off = R6_ARG4; 2060 Register super_k = R7_ARG5; 2061 2062 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type)); 2063 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type)); 2064 if (shift == 0) { 2065 __ add(src_ptr, src_pos, src_ptr); 2066 __ add(dst_ptr, dst_pos, dst_ptr); 2067 } else { 2068 __ sldi(tmp, src_pos, shift); 2069 __ sldi(tmp2, dst_pos, shift); 2070 __ add(src_ptr, tmp, src_ptr); 2071 __ add(dst_ptr, tmp2, dst_ptr); 2072 } 2073 2074 __ load_klass(tmp, dst); 2075 __ mr(len, length); 2076 2077 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset()); 2078 __ ld(super_k, ek_offset, tmp); 2079 2080 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 2081 __ lwz(chk_off, sco_offset, super_k); 2082 2083 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0); 2084 2085 #ifndef PRODUCT 2086 if (PrintC1Statistics) { 2087 Label failed; 2088 __ cmpwi(CCR0, R3_RET, 0); 2089 __ bne(CCR0, failed); 2090 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt; 2091 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 2092 __ lwz(R11_scratch1, simm16_offs, tmp); 2093 __ addi(R11_scratch1, R11_scratch1, 1); 2094 __ stw(R11_scratch1, simm16_offs, tmp); 2095 __ bind(failed); 2096 } 2097 #endif 2098 2099 __ nand(tmp, R3_RET, R3_RET); 2100 __ cmpwi(CCR0, R3_RET, 0); 2101 __ beq(CCR0, *stub->continuation()); 2102 2103 #ifndef PRODUCT 2104 if (PrintC1Statistics) { 2105 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt; 2106 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 2107 __ lwz(R11_scratch1, simm16_offs, tmp); 2108 __ addi(R11_scratch1, R11_scratch1, 1); 2109 __ stw(R11_scratch1, simm16_offs, tmp); 2110 } 2111 #endif 2112 2113 __ subf(length, tmp, length); 2114 __ add(src_pos, tmp, src_pos); 2115 __ add(dst_pos, tmp, dst_pos); 2116 } 2117 } 2118 } 2119 __ bind(slow); 2120 __ b(*stub->entry()); 2121 __ bind(cont); 2122 2123 #ifdef ASSERT 2124 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2125 // Sanity check the known type with the incoming class. For the 2126 // primitive case the types must match exactly with src.klass and 2127 // dst.klass each exactly matching the default type. For the 2128 // object array case, if no type check is needed then either the 2129 // dst type is exactly the expected type and the src type is a 2130 // subtype which we can't check or src is the same array as dst 2131 // but not necessarily exactly of type default_type. 2132 Label known_ok, halt; 2133 metadata2reg(op->expected_type()->constant_encoding(), tmp); 2134 if (UseCompressedClassPointers) { 2135 // Tmp holds the default type. It currently comes uncompressed after the 2136 // load of a constant, so encode it. 2137 __ encode_klass_not_null(tmp); 2138 // Load the raw value of the dst klass, since we will be comparing 2139 // uncompressed values directly. 2140 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst); 2141 __ cmpw(CCR0, tmp, tmp2); 2142 if (basic_type != T_OBJECT) { 2143 __ bne(CCR0, halt); 2144 // Load the raw value of the src klass. 2145 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src); 2146 __ cmpw(CCR0, tmp, tmp2); 2147 __ beq(CCR0, known_ok); 2148 } else { 2149 __ beq(CCR0, known_ok); 2150 __ cmpw(CCR0, src, dst); 2151 __ beq(CCR0, known_ok); 2152 } 2153 } else { 2154 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst); 2155 __ cmpd(CCR0, tmp, tmp2); 2156 if (basic_type != T_OBJECT) { 2157 __ bne(CCR0, halt); 2158 // Load the raw value of the src klass. 2159 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src); 2160 __ cmpd(CCR0, tmp, tmp2); 2161 __ beq(CCR0, known_ok); 2162 } else { 2163 __ beq(CCR0, known_ok); 2164 __ cmpd(CCR0, src, dst); 2165 __ beq(CCR0, known_ok); 2166 } 2167 } 2168 __ bind(halt); 2169 __ stop("incorrect type information in arraycopy"); 2170 __ bind(known_ok); 2171 } 2172 #endif 2173 2174 #ifndef PRODUCT 2175 if (PrintC1Statistics) { 2176 address counter = Runtime1::arraycopy_count_address(basic_type); 2177 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 2178 __ lwz(R11_scratch1, simm16_offs, tmp); 2179 __ addi(R11_scratch1, R11_scratch1, 1); 2180 __ stw(R11_scratch1, simm16_offs, tmp); 2181 } 2182 #endif 2183 2184 Register src_ptr = R3_ARG1; 2185 Register dst_ptr = R4_ARG2; 2186 Register len = R5_ARG3; 2187 2188 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type)); 2189 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type)); 2190 if (shift == 0) { 2191 __ add(src_ptr, src_pos, src_ptr); 2192 __ add(dst_ptr, dst_pos, dst_ptr); 2193 } else { 2194 __ sldi(tmp, src_pos, shift); 2195 __ sldi(tmp2, dst_pos, shift); 2196 __ add(src_ptr, tmp, src_ptr); 2197 __ add(dst_ptr, tmp2, dst_ptr); 2198 } 2199 2200 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2201 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2202 const char *name; 2203 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2204 2205 // Arraycopy stubs takes a length in number of elements, so don't scale it. 2206 __ mr(len, length); 2207 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0); 2208 2209 __ bind(*stub->continuation()); 2210 } 2211 2212 2213 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2214 if (dest->is_single_cpu()) { 2215 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5); 2216 #ifdef _LP64 2217 if (left->type() == T_OBJECT) { 2218 switch (code) { 2219 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break; 2220 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break; 2221 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break; 2222 default: ShouldNotReachHere(); 2223 } 2224 } else 2225 #endif 2226 switch (code) { 2227 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break; 2228 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break; 2229 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break; 2230 default: ShouldNotReachHere(); 2231 } 2232 } else { 2233 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6); 2234 switch (code) { 2235 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break; 2236 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break; 2237 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break; 2238 default: ShouldNotReachHere(); 2239 } 2240 } 2241 } 2242 2243 2244 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2245 #ifdef _LP64 2246 if (left->type() == T_OBJECT) { 2247 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t). 2248 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); } 2249 else { 2250 switch (code) { 2251 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break; 2252 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break; 2253 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break; 2254 default: ShouldNotReachHere(); 2255 } 2256 } 2257 return; 2258 } 2259 #endif 2260 2261 if (dest->is_single_cpu()) { 2262 count = count & 0x1F; // Java spec 2263 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); } 2264 else { 2265 switch (code) { 2266 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break; 2267 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break; 2268 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break; 2269 default: ShouldNotReachHere(); 2270 } 2271 } 2272 } else if (dest->is_double_cpu()) { 2273 count = count & 63; // Java spec 2274 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); } 2275 else { 2276 switch (code) { 2277 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break; 2278 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break; 2279 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break; 2280 default: ShouldNotReachHere(); 2281 } 2282 } 2283 } else { 2284 ShouldNotReachHere(); 2285 } 2286 } 2287 2288 2289 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 2290 if (op->init_check()) { 2291 if (!os::zero_page_read_protected() || !ImplicitNullChecks) { 2292 explicit_null_check(op->klass()->as_register(), op->stub()->info()); 2293 } else { 2294 add_debug_info_for_null_check_here(op->stub()->info()); 2295 } 2296 __ lbz(op->tmp1()->as_register(), 2297 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register()); 2298 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized); 2299 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry()); 2300 } 2301 __ allocate_object(op->obj()->as_register(), 2302 op->tmp1()->as_register(), 2303 op->tmp2()->as_register(), 2304 op->tmp3()->as_register(), 2305 op->header_size(), 2306 op->object_size(), 2307 op->klass()->as_register(), 2308 *op->stub()->entry()); 2309 2310 __ bind(*op->stub()->continuation()); 2311 __ verify_oop(op->obj()->as_register()); 2312 } 2313 2314 2315 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 2316 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); ) 2317 if (UseSlowPath || 2318 (!UseFastNewObjectArray && (is_reference_type(op->type()))) || 2319 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) { 2320 __ b(*op->stub()->entry()); 2321 } else { 2322 __ allocate_array(op->obj()->as_register(), 2323 op->len()->as_register(), 2324 op->tmp1()->as_register(), 2325 op->tmp2()->as_register(), 2326 op->tmp3()->as_register(), 2327 arrayOopDesc::header_size(op->type()), 2328 type2aelembytes(op->type()), 2329 op->klass()->as_register(), 2330 *op->stub()->entry()); 2331 } 2332 __ bind(*op->stub()->continuation()); 2333 } 2334 2335 2336 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, 2337 ciMethodData *md, ciProfileData *data, 2338 Register recv, Register tmp1, Label* update_done) { 2339 uint i; 2340 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2341 Label next_test; 2342 // See if the receiver is receiver[n]. 2343 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo); 2344 __ verify_klass_ptr(tmp1); 2345 __ cmpd(CCR0, recv, tmp1); 2346 __ bne(CCR0, next_test); 2347 2348 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2349 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2350 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2351 __ b(*update_done); 2352 2353 __ bind(next_test); 2354 } 2355 2356 // Didn't find receiver; find next empty slot and fill it in. 2357 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2358 Label next_test; 2359 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo); 2360 __ cmpdi(CCR0, tmp1, 0); 2361 __ bne(CCR0, next_test); 2362 __ li(tmp1, DataLayout::counter_increment); 2363 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo); 2364 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2365 __ b(*update_done); 2366 2367 __ bind(next_test); 2368 } 2369 } 2370 2371 2372 void LIR_Assembler::setup_md_access(ciMethod* method, int bci, 2373 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { 2374 md = method->method_data_or_null(); 2375 assert(md != NULL, "Sanity"); 2376 data = md->bci_to_data(bci); 2377 assert(data != NULL, "need data for checkcast"); 2378 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2379 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { 2380 // The offset is large so bias the mdo by the base of the slot so 2381 // that the ld can use simm16s to reference the slots of the data. 2382 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); 2383 } 2384 } 2385 2386 2387 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 2388 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub). 2389 Register k_RInfo = op->tmp1()->as_register(); 2390 Register klass_RInfo = op->tmp2()->as_register(); 2391 Register Rtmp1 = op->tmp3()->as_register(); 2392 Register dst = op->result_opr()->as_register(); 2393 ciKlass* k = op->klass(); 2394 bool should_profile = op->should_profile(); 2395 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps. 2396 bool reg_conflict = false; 2397 if (obj == k_RInfo) { 2398 k_RInfo = dst; 2399 reg_conflict = true; 2400 } else if (obj == klass_RInfo) { 2401 klass_RInfo = dst; 2402 reg_conflict = true; 2403 } else if (obj == Rtmp1) { 2404 Rtmp1 = dst; 2405 reg_conflict = true; 2406 } 2407 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1); 2408 2409 __ cmpdi(CCR0, obj, 0); 2410 2411 ciMethodData* md = NULL; 2412 ciProfileData* data = NULL; 2413 int mdo_offset_bias = 0; 2414 if (should_profile) { 2415 ciMethod* method = op->profiled_method(); 2416 assert(method != NULL, "Should have method"); 2417 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2418 2419 Register mdo = k_RInfo; 2420 Register data_val = Rtmp1; 2421 Label not_null; 2422 __ bne(CCR0, not_null); 2423 metadata2reg(md->constant_encoding(), mdo); 2424 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2425 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2426 __ ori(data_val, data_val, BitData::null_seen_byte_constant()); 2427 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2428 __ b(*obj_is_null); 2429 __ bind(not_null); 2430 } else { 2431 __ beq(CCR0, *obj_is_null); 2432 } 2433 2434 // get object class 2435 __ load_klass(klass_RInfo, obj); 2436 2437 if (k->is_loaded()) { 2438 metadata2reg(k->constant_encoding(), k_RInfo); 2439 } else { 2440 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 2441 } 2442 2443 Label profile_cast_failure, failure_restore_obj, profile_cast_success; 2444 Label *failure_target = should_profile ? &profile_cast_failure : failure; 2445 Label *success_target = should_profile ? &profile_cast_success : success; 2446 2447 if (op->fast_check()) { 2448 assert_different_registers(klass_RInfo, k_RInfo); 2449 __ cmpd(CCR0, k_RInfo, klass_RInfo); 2450 if (should_profile) { 2451 __ bne(CCR0, *failure_target); 2452 // Fall through to success case. 2453 } else { 2454 __ beq(CCR0, *success); 2455 // Fall through to failure case. 2456 } 2457 } else { 2458 bool need_slow_path = true; 2459 if (k->is_loaded()) { 2460 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) { 2461 need_slow_path = false; 2462 } 2463 // Perform the fast part of the checking logic. 2464 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL), 2465 failure_target, NULL, RegisterOrConstant(k->super_check_offset())); 2466 } else { 2467 // Perform the fast part of the checking logic. 2468 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target); 2469 } 2470 if (!need_slow_path) { 2471 if (!should_profile) { __ b(*success); } 2472 } else { 2473 // Call out-of-line instance of __ check_klass_subtype_slow_path(...): 2474 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id); 2475 // Stub needs fixed registers (tmp1-3). 2476 Register original_k_RInfo = op->tmp1()->as_register(); 2477 Register original_klass_RInfo = op->tmp2()->as_register(); 2478 Register original_Rtmp1 = op->tmp3()->as_register(); 2479 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast); 2480 bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile; 2481 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); } 2482 __ mr_if_needed(original_k_RInfo, k_RInfo); 2483 __ mr_if_needed(original_klass_RInfo, klass_RInfo); 2484 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); } 2485 //__ load_const_optimized(original_Rtmp1, entry, R0); 2486 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false); 2487 __ mtctr(original_Rtmp1); 2488 __ bctrl(); // sets CR0 2489 if (keep_obj_alive) { 2490 if (keep_klass_RInfo_alive) { __ mr(R0, obj); } 2491 __ mr(obj, dst); 2492 } 2493 if (should_profile) { 2494 __ bne(CCR0, *failure_target); 2495 if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); } 2496 // Fall through to success case. 2497 } else { 2498 __ beq(CCR0, *success); 2499 // Fall through to failure case. 2500 } 2501 } 2502 } 2503 2504 if (should_profile) { 2505 Register mdo = k_RInfo, recv = klass_RInfo; 2506 assert_different_registers(mdo, recv, Rtmp1); 2507 __ bind(profile_cast_success); 2508 metadata2reg(md->constant_encoding(), mdo); 2509 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2510 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success); 2511 __ b(*success); 2512 2513 // Cast failure case. 2514 __ bind(profile_cast_failure); 2515 metadata2reg(md->constant_encoding(), mdo); 2516 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2517 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2518 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment); 2519 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2520 } 2521 2522 __ bind(*failure); 2523 } 2524 2525 2526 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 2527 LIR_Code code = op->code(); 2528 if (code == lir_store_check) { 2529 Register value = op->object()->as_register(); 2530 Register array = op->array()->as_register(); 2531 Register k_RInfo = op->tmp1()->as_register(); 2532 Register klass_RInfo = op->tmp2()->as_register(); 2533 Register Rtmp1 = op->tmp3()->as_register(); 2534 bool should_profile = op->should_profile(); 2535 2536 __ verify_oop(value); 2537 CodeStub* stub = op->stub(); 2538 // Check if it needs to be profiled. 2539 ciMethodData* md = NULL; 2540 ciProfileData* data = NULL; 2541 int mdo_offset_bias = 0; 2542 if (should_profile) { 2543 ciMethod* method = op->profiled_method(); 2544 assert(method != NULL, "Should have method"); 2545 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2546 } 2547 Label profile_cast_success, failure, done; 2548 Label *success_target = should_profile ? &profile_cast_success : &done; 2549 2550 __ cmpdi(CCR0, value, 0); 2551 if (should_profile) { 2552 Label not_null; 2553 __ bne(CCR0, not_null); 2554 Register mdo = k_RInfo; 2555 Register data_val = Rtmp1; 2556 metadata2reg(md->constant_encoding(), mdo); 2557 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2558 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2559 __ ori(data_val, data_val, BitData::null_seen_byte_constant()); 2560 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2561 __ b(done); 2562 __ bind(not_null); 2563 } else { 2564 __ beq(CCR0, done); 2565 } 2566 if (!os::zero_page_read_protected() || !ImplicitNullChecks) { 2567 explicit_null_check(array, op->info_for_exception()); 2568 } else { 2569 add_debug_info_for_null_check_here(op->info_for_exception()); 2570 } 2571 __ load_klass(k_RInfo, array); 2572 __ load_klass(klass_RInfo, value); 2573 2574 // Get instance klass. 2575 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo); 2576 // Perform the fast part of the checking logic. 2577 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL); 2578 2579 // Call out-of-line instance of __ check_klass_subtype_slow_path(...): 2580 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id); 2581 //__ load_const_optimized(R0, slow_path); 2582 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path)); 2583 __ mtctr(R0); 2584 __ bctrl(); // sets CR0 2585 if (!should_profile) { 2586 __ beq(CCR0, done); 2587 __ bind(failure); 2588 } else { 2589 __ bne(CCR0, failure); 2590 // Fall through to the success case. 2591 2592 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2593 assert_different_registers(value, mdo, recv, tmp1); 2594 __ bind(profile_cast_success); 2595 metadata2reg(md->constant_encoding(), mdo); 2596 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2597 __ load_klass(recv, value); 2598 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done); 2599 __ b(done); 2600 2601 // Cast failure case. 2602 __ bind(failure); 2603 metadata2reg(md->constant_encoding(), mdo); 2604 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2605 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2606 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2607 __ addi(tmp1, tmp1, -DataLayout::counter_increment); 2608 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2609 } 2610 __ b(*stub->entry()); 2611 __ bind(done); 2612 2613 } else if (code == lir_checkcast) { 2614 Label success, failure; 2615 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success); 2616 __ b(*op->stub()->entry()); 2617 __ align(32, 12); 2618 __ bind(success); 2619 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register()); 2620 } else if (code == lir_instanceof) { 2621 Register dst = op->result_opr()->as_register(); 2622 Label success, failure, done; 2623 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure); 2624 __ li(dst, 0); 2625 __ b(done); 2626 __ align(32, 12); 2627 __ bind(success); 2628 __ li(dst, 1); 2629 __ bind(done); 2630 } else { 2631 ShouldNotReachHere(); 2632 } 2633 } 2634 2635 2636 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2637 Register addr = op->addr()->as_pointer_register(); 2638 Register cmp_value = noreg, new_value = noreg; 2639 bool is_64bit = false; 2640 2641 if (op->code() == lir_cas_long) { 2642 cmp_value = op->cmp_value()->as_register_lo(); 2643 new_value = op->new_value()->as_register_lo(); 2644 is_64bit = true; 2645 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2646 cmp_value = op->cmp_value()->as_register(); 2647 new_value = op->new_value()->as_register(); 2648 if (op->code() == lir_cas_obj) { 2649 if (UseCompressedOops) { 2650 Register t1 = op->tmp1()->as_register(); 2651 Register t2 = op->tmp2()->as_register(); 2652 cmp_value = __ encode_heap_oop(t1, cmp_value); 2653 new_value = __ encode_heap_oop(t2, new_value); 2654 } else { 2655 is_64bit = true; 2656 } 2657 } 2658 } else { 2659 Unimplemented(); 2660 } 2661 2662 if (is_64bit) { 2663 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr, 2664 MacroAssembler::MemBarNone, 2665 MacroAssembler::cmpxchgx_hint_atomic_update(), 2666 noreg, NULL, /*check without ldarx first*/true); 2667 } else { 2668 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr, 2669 MacroAssembler::MemBarNone, 2670 MacroAssembler::cmpxchgx_hint_atomic_update(), 2671 noreg, /*check without ldarx first*/true); 2672 } 2673 2674 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { 2675 __ isync(); 2676 } else { 2677 __ sync(); 2678 } 2679 } 2680 2681 2682 void LIR_Assembler::set_24bit_FPU() { 2683 Unimplemented(); 2684 } 2685 2686 void LIR_Assembler::reset_FPU() { 2687 Unimplemented(); 2688 } 2689 2690 2691 void LIR_Assembler::breakpoint() { 2692 __ illtrap(); 2693 } 2694 2695 2696 void LIR_Assembler::push(LIR_Opr opr) { 2697 Unimplemented(); 2698 } 2699 2700 void LIR_Assembler::pop(LIR_Opr opr) { 2701 Unimplemented(); 2702 } 2703 2704 2705 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { 2706 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 2707 Register dst = dst_opr->as_register(); 2708 Register reg = mon_addr.base(); 2709 int offset = mon_addr.disp(); 2710 // Compute pointer to BasicLock. 2711 __ add_const_optimized(dst, reg, offset); 2712 } 2713 2714 2715 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2716 Register obj = op->obj_opr()->as_register(); 2717 Register hdr = op->hdr_opr()->as_register(); 2718 Register lock = op->lock_opr()->as_register(); 2719 2720 // Obj may not be an oop. 2721 if (op->code() == lir_lock) { 2722 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); 2723 if (UseFastLocking) { 2724 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2725 // Add debug info for NullPointerException only if one is possible. 2726 if (op->info() != NULL) { 2727 if (!os::zero_page_read_protected() || !ImplicitNullChecks) { 2728 explicit_null_check(obj, op->info()); 2729 } else { 2730 add_debug_info_for_null_check_here(op->info()); 2731 } 2732 } 2733 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); 2734 } else { 2735 // always do slow locking 2736 // note: The slow locking code could be inlined here, however if we use 2737 // slow locking, speed doesn't matter anyway and this solution is 2738 // simpler and requires less duplicated code - additionally, the 2739 // slow locking code is the same in either case which simplifies 2740 // debugging. 2741 __ b(*op->stub()->entry()); 2742 } 2743 } else { 2744 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); 2745 if (UseFastLocking) { 2746 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2747 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2748 } else { 2749 // always do slow unlocking 2750 // note: The slow unlocking code could be inlined here, however if we use 2751 // slow unlocking, speed doesn't matter anyway and this solution is 2752 // simpler and requires less duplicated code - additionally, the 2753 // slow unlocking code is the same in either case which simplifies 2754 // debugging. 2755 __ b(*op->stub()->entry()); 2756 } 2757 } 2758 __ bind(*op->stub()->continuation()); 2759 } 2760 2761 2762 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2763 ciMethod* method = op->profiled_method(); 2764 int bci = op->profiled_bci(); 2765 ciMethod* callee = op->profiled_callee(); 2766 2767 // Update counter for all call types. 2768 ciMethodData* md = method->method_data_or_null(); 2769 assert(md != NULL, "Sanity"); 2770 ciProfileData* data = md->bci_to_data(bci); 2771 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 2772 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2773 Register mdo = op->mdo()->as_register(); 2774 #ifdef _LP64 2775 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); 2776 Register tmp1 = op->tmp1()->as_register_lo(); 2777 #else 2778 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); 2779 Register tmp1 = op->tmp1()->as_register(); 2780 #endif 2781 metadata2reg(md->constant_encoding(), mdo); 2782 int mdo_offset_bias = 0; 2783 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) + 2784 data->size_in_bytes())) { 2785 // The offset is large so bias the mdo by the base of the slot so 2786 // that the ld can use simm16s to reference the slots of the data. 2787 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); 2788 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2789 } 2790 2791 // Perform additional virtual call profiling for invokevirtual and 2792 // invokeinterface bytecodes 2793 if (op->should_profile_receiver_type()) { 2794 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2795 Register recv = op->recv()->as_register(); 2796 assert_different_registers(mdo, tmp1, recv); 2797 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2798 ciKlass* known_klass = op->known_holder(); 2799 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 2800 // We know the type that will be seen at this call site; we can 2801 // statically update the MethodData* rather than needing to do 2802 // dynamic tests on the receiver type. 2803 2804 // NOTE: we should probably put a lock around this search to 2805 // avoid collisions by concurrent compilations. 2806 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2807 uint i; 2808 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2809 ciKlass* receiver = vc_data->receiver(i); 2810 if (known_klass->equals(receiver)) { 2811 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2812 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2813 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2814 return; 2815 } 2816 } 2817 2818 // Receiver type not found in profile data; select an empty slot. 2819 2820 // Note that this is less efficient than it should be because it 2821 // always does a write to the receiver part of the 2822 // VirtualCallData rather than just the first time. 2823 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2824 ciKlass* receiver = vc_data->receiver(i); 2825 if (receiver == NULL) { 2826 metadata2reg(known_klass->constant_encoding(), tmp1); 2827 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo); 2828 2829 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2830 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2831 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2832 return; 2833 } 2834 } 2835 } else { 2836 __ load_klass(recv, recv); 2837 Label update_done; 2838 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); 2839 // Receiver did not match any saved receiver and there is no empty row for it. 2840 // Increment total counter to indicate polymorphic case. 2841 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2842 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2843 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2844 2845 __ bind(update_done); 2846 } 2847 } else { 2848 // Static call 2849 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2850 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2851 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2852 } 2853 } 2854 2855 2856 void LIR_Assembler::align_backward_branch_target() { 2857 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary. 2858 } 2859 2860 2861 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { 2862 Unimplemented(); 2863 } 2864 2865 2866 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 2867 // tmp must be unused 2868 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2869 assert(left->is_register(), "can only handle registers"); 2870 2871 if (left->is_single_cpu()) { 2872 __ neg(dest->as_register(), left->as_register()); 2873 } else if (left->is_single_fpu()) { 2874 __ fneg(dest->as_float_reg(), left->as_float_reg()); 2875 } else if (left->is_double_fpu()) { 2876 __ fneg(dest->as_double_reg(), left->as_double_reg()); 2877 } else { 2878 assert (left->is_double_cpu(), "Must be a long"); 2879 __ neg(dest->as_register_lo(), left->as_register_lo()); 2880 } 2881 } 2882 2883 2884 void LIR_Assembler::fxch(int i) { 2885 Unimplemented(); 2886 } 2887 2888 void LIR_Assembler::fld(int i) { 2889 Unimplemented(); 2890 } 2891 2892 void LIR_Assembler::ffree(int i) { 2893 Unimplemented(); 2894 } 2895 2896 2897 void LIR_Assembler::rt_call(LIR_Opr result, address dest, 2898 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 2899 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor). 2900 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) || 2901 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) { 2902 //__ load_const_optimized(R0, dest); 2903 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest)); 2904 __ mtctr(R0); 2905 __ bctrl(); 2906 assert(info != NULL, "sanity"); 2907 add_call_info_here(info); 2908 return; 2909 } 2910 2911 __ call_c_with_frame_resize(dest, /*no resizing*/ 0); 2912 if (info != NULL) { 2913 add_call_info_here(info); 2914 } 2915 } 2916 2917 2918 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 2919 ShouldNotReachHere(); // Not needed on _LP64. 2920 } 2921 2922 void LIR_Assembler::membar() { 2923 __ fence(); 2924 } 2925 2926 void LIR_Assembler::membar_acquire() { 2927 __ acquire(); 2928 } 2929 2930 void LIR_Assembler::membar_release() { 2931 __ release(); 2932 } 2933 2934 void LIR_Assembler::membar_loadload() { 2935 __ membar(Assembler::LoadLoad); 2936 } 2937 2938 void LIR_Assembler::membar_storestore() { 2939 __ membar(Assembler::StoreStore); 2940 } 2941 2942 void LIR_Assembler::membar_loadstore() { 2943 __ membar(Assembler::LoadStore); 2944 } 2945 2946 void LIR_Assembler::membar_storeload() { 2947 __ membar(Assembler::StoreLoad); 2948 } 2949 2950 void LIR_Assembler::on_spin_wait() { 2951 Unimplemented(); 2952 } 2953 2954 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 2955 assert(patch_code == lir_patch_none, "Patch code not supported"); 2956 LIR_Address* addr = addr_opr->as_address_ptr(); 2957 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform"); 2958 if (addr->index()->is_illegal()) { 2959 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp()); 2960 } else { 2961 assert(addr->disp() == 0, "can't have both: index and disp"); 2962 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register()); 2963 } 2964 } 2965 2966 2967 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 2968 ShouldNotReachHere(); 2969 } 2970 2971 2972 #ifdef ASSERT 2973 // Emit run-time assertion. 2974 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 2975 Unimplemented(); 2976 } 2977 #endif 2978 2979 2980 void LIR_Assembler::peephole(LIR_List* lir) { 2981 // Optimize instruction pairs before emitting. 2982 LIR_OpList* inst = lir->instructions_list(); 2983 for (int i = 1; i < inst->length(); i++) { 2984 LIR_Op* op = inst->at(i); 2985 2986 // 2 register-register-moves 2987 if (op->code() == lir_move) { 2988 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(), 2989 res2 = ((LIR_Op1*)op)->result_opr(); 2990 if (in2->is_register() && res2->is_register()) { 2991 LIR_Op* prev = inst->at(i - 1); 2992 if (prev && prev->code() == lir_move) { 2993 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(), 2994 res1 = ((LIR_Op1*)prev)->result_opr(); 2995 if (in1->is_same_register(res2) && in2->is_same_register(res1)) { 2996 inst->remove_at(i); 2997 } 2998 } 2999 } 3000 } 3001 3002 } 3003 return; 3004 } 3005 3006 3007 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 3008 const LIR_Address *addr = src->as_address_ptr(); 3009 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!"); 3010 const Register Rptr = addr->base()->as_pointer_register(), 3011 Rtmp = tmp->as_register(); 3012 Register Rco = noreg; 3013 if (UseCompressedOops && data->is_oop()) { 3014 Rco = __ encode_heap_oop(Rtmp, data->as_register()); 3015 } 3016 3017 Label Lretry; 3018 __ bind(Lretry); 3019 3020 if (data->type() == T_INT) { 3021 const Register Rold = dest->as_register(), 3022 Rsrc = data->as_register(); 3023 assert_different_registers(Rptr, Rtmp, Rold, Rsrc); 3024 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3025 if (code == lir_xadd) { 3026 __ add(Rtmp, Rsrc, Rold); 3027 __ stwcx_(Rtmp, Rptr); 3028 } else { 3029 __ stwcx_(Rsrc, Rptr); 3030 } 3031 } else if (data->is_oop()) { 3032 assert(code == lir_xchg, "xadd for oops"); 3033 const Register Rold = dest->as_register(); 3034 if (UseCompressedOops) { 3035 assert_different_registers(Rptr, Rold, Rco); 3036 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3037 __ stwcx_(Rco, Rptr); 3038 } else { 3039 const Register Robj = data->as_register(); 3040 assert_different_registers(Rptr, Rold, Robj); 3041 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3042 __ stdcx_(Robj, Rptr); 3043 } 3044 } else if (data->type() == T_LONG) { 3045 const Register Rold = dest->as_register_lo(), 3046 Rsrc = data->as_register_lo(); 3047 assert_different_registers(Rptr, Rtmp, Rold, Rsrc); 3048 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3049 if (code == lir_xadd) { 3050 __ add(Rtmp, Rsrc, Rold); 3051 __ stdcx_(Rtmp, Rptr); 3052 } else { 3053 __ stdcx_(Rsrc, Rptr); 3054 } 3055 } else { 3056 ShouldNotReachHere(); 3057 } 3058 3059 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3060 __ bne_predict_not_taken(CCR0, Lretry); 3061 } else { 3062 __ bne( CCR0, Lretry); 3063 } 3064 3065 if (UseCompressedOops && data->is_oop()) { 3066 __ decode_heap_oop(dest->as_register()); 3067 } 3068 } 3069 3070 3071 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3072 Register obj = op->obj()->as_register(); 3073 Register tmp = op->tmp()->as_pointer_register(); 3074 LIR_Address* mdo_addr = op->mdp()->as_address_ptr(); 3075 ciKlass* exact_klass = op->exact_klass(); 3076 intptr_t current_klass = op->current_klass(); 3077 bool not_null = op->not_null(); 3078 bool no_conflict = op->no_conflict(); 3079 3080 Label Lupdate, Ldo_update, Ldone; 3081 3082 bool do_null = !not_null; 3083 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3084 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3085 3086 assert(do_null || do_update, "why are we here?"); 3087 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3088 3089 __ verify_oop(obj); 3090 3091 if (do_null) { 3092 if (!TypeEntries::was_null_seen(current_klass)) { 3093 __ cmpdi(CCR0, obj, 0); 3094 __ bne(CCR0, Lupdate); 3095 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3096 __ ori(R0, R0, TypeEntries::null_seen); 3097 if (do_update) { 3098 __ b(Ldo_update); 3099 } else { 3100 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3101 } 3102 } else { 3103 if (do_update) { 3104 __ cmpdi(CCR0, obj, 0); 3105 __ beq(CCR0, Ldone); 3106 } 3107 } 3108 #ifdef ASSERT 3109 } else { 3110 __ cmpdi(CCR0, obj, 0); 3111 __ bne(CCR0, Lupdate); 3112 __ stop("unexpect null obj", 0x9652); 3113 #endif 3114 } 3115 3116 __ bind(Lupdate); 3117 if (do_update) { 3118 Label Lnext; 3119 const Register klass = R29_TOC; // kill and reload 3120 bool klass_reg_used = false; 3121 #ifdef ASSERT 3122 if (exact_klass != NULL) { 3123 Label ok; 3124 klass_reg_used = true; 3125 __ load_klass(klass, obj); 3126 metadata2reg(exact_klass->constant_encoding(), R0); 3127 __ cmpd(CCR0, klass, R0); 3128 __ beq(CCR0, ok); 3129 __ stop("exact klass and actual klass differ", 0x8564); 3130 __ bind(ok); 3131 } 3132 #endif 3133 3134 if (!no_conflict) { 3135 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3136 klass_reg_used = true; 3137 if (exact_klass != NULL) { 3138 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3139 metadata2reg(exact_klass->constant_encoding(), klass); 3140 } else { 3141 __ load_klass(klass, obj); 3142 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj 3143 } 3144 3145 // Like InterpreterMacroAssembler::profile_obj_type 3146 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask)); 3147 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask); 3148 __ cmpd(CCR1, R0, klass); 3149 // Klass seen before, nothing to do (regardless of unknown bit). 3150 //beq(CCR1, do_nothing); 3151 3152 __ andi_(R0, klass, TypeEntries::type_unknown); 3153 // Already unknown. Nothing to do anymore. 3154 //bne(CCR0, do_nothing); 3155 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne 3156 __ beq(CCR0, Lnext); 3157 3158 if (TypeEntries::is_type_none(current_klass)) { 3159 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask)); 3160 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0). 3161 __ beq(CCR0, Ldo_update); // First time here. Set profile type. 3162 } 3163 3164 } else { 3165 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3166 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3167 3168 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3169 __ andi_(R0, tmp, TypeEntries::type_unknown); 3170 // Already unknown. Nothing to do anymore. 3171 __ bne(CCR0, Lnext); 3172 } 3173 3174 // Different than before. Cannot keep accurate profile. 3175 __ ori(R0, tmp, TypeEntries::type_unknown); 3176 } else { 3177 // There's a single possible klass at this profile point 3178 assert(exact_klass != NULL, "should be"); 3179 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3180 3181 if (TypeEntries::is_type_none(current_klass)) { 3182 klass_reg_used = true; 3183 metadata2reg(exact_klass->constant_encoding(), klass); 3184 3185 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask)); 3186 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask); 3187 __ cmpd(CCR1, R0, klass); 3188 // Klass seen before, nothing to do (regardless of unknown bit). 3189 __ beq(CCR1, Lnext); 3190 #ifdef ASSERT 3191 { 3192 Label ok; 3193 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask)); 3194 __ beq(CCR0, ok); // First time here. 3195 3196 __ stop("unexpected profiling mismatch", 0x7865); 3197 __ bind(ok); 3198 } 3199 #endif 3200 // First time here. Set profile type. 3201 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0). 3202 } else { 3203 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3204 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3205 3206 // Already unknown. Nothing to do anymore. 3207 __ andi_(R0, tmp, TypeEntries::type_unknown); 3208 __ bne(CCR0, Lnext); 3209 3210 // Different than before. Cannot keep accurate profile. 3211 __ ori(R0, tmp, TypeEntries::type_unknown); 3212 } 3213 } 3214 3215 __ bind(Ldo_update); 3216 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3217 3218 __ bind(Lnext); 3219 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit 3220 } 3221 __ bind(Ldone); 3222 } 3223 3224 3225 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3226 assert(op->crc()->is_single_cpu(), "crc must be register"); 3227 assert(op->val()->is_single_cpu(), "byte value must be register"); 3228 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3229 Register crc = op->crc()->as_register(); 3230 Register val = op->val()->as_register(); 3231 Register res = op->result_opr()->as_register(); 3232 3233 assert_different_registers(val, crc, res); 3234 3235 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0); 3236 __ kernel_crc32_singleByteReg(crc, val, res, true); 3237 __ mr(res, crc); 3238 } 3239 3240 #undef __