1 /*
2 * Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2019, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "gc/shared/barrierSet.hpp"
37 #include "gc/shared/cardTableBarrierSet.hpp"
38 #include "memory/universe.hpp"
39 #include "nativeInst_s390.hpp"
40 #include "oops/objArrayKlass.hpp"
41 #include "runtime/frame.inline.hpp"
42 #include "runtime/safepointMechanism.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "vmreg_s390.inline.hpp"
45
46 #define __ _masm->
47
48 #ifndef PRODUCT
49 #undef __
50 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)->
51 #endif
52
53 //------------------------------------------------------------
54
55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
56 // Not used on ZARCH_64
57 ShouldNotCallThis();
58 return false;
59 }
60
61 LIR_Opr LIR_Assembler::receiverOpr() {
62 return FrameMap::Z_R2_oop_opr;
63 }
64
65 LIR_Opr LIR_Assembler::osrBufferPointer() {
66 return FrameMap::Z_R2_opr;
67 }
68
69 int LIR_Assembler::initial_frame_size_in_bytes() const {
70 return in_bytes(frame_map()->framesize_in_bytes());
71 }
72
73 // Inline cache check: done before the frame is built.
74 // The inline cached class is in Z_inline_cache(Z_R9).
75 // We fetch the class of the receiver and compare it with the cached class.
76 // If they do not match we jump to the slow case.
77 int LIR_Assembler::check_icache() {
78 Register receiver = receiverOpr()->as_register();
79 int offset = __ offset();
80 __ inline_cache_check(receiver, Z_inline_cache);
81 return offset;
82 }
83
84 void LIR_Assembler::clinit_barrier(ciMethod* method) {
85 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
86
87 Label L_skip_barrier;
88 Register klass = Z_R1_scratch;
89
90 metadata2reg(method->holder()->constant_encoding(), klass);
91 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
92
93 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
94 __ z_br(klass);
95
96 __ bind(L_skip_barrier);
97 }
98
99 void LIR_Assembler::osr_entry() {
100 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
101 //
102 // 1. Create a new compiled activation.
103 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
104 // at the osr_bci; it is not initialized.
105 // 3. Jump to the continuation address in compiled code to resume execution.
106
107 // OSR entry point
108 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
109 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
110 ValueStack* entry_state = osr_entry->end()->state();
111 int number_of_locks = entry_state->locks_size();
112
113 // Create a frame for the compiled activation.
114 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
115
116 // OSR buffer is
117 //
118 // locals[nlocals-1..0]
119 // monitors[number_of_locks-1..0]
120 //
121 // Locals is a direct copy of the interpreter frame so in the osr buffer
122 // the first slot in the local array is the last local from the interpreter
123 // and the last slot is local[0] (receiver) from the interpreter
124 //
125 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
126 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
127 // in the interpreter frame (the method lock if a sync method)
128
129 // Initialize monitors in the compiled activation.
130 // I0: pointer to osr buffer
131 //
132 // All other registers are dead at this point and the locals will be
133 // copied into place by code emitted in the IR.
134
135 Register OSR_buf = osrBufferPointer()->as_register();
136 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
137 int monitor_offset = BytesPerWord * method()->max_locals() +
138 (2 * BytesPerWord) * (number_of_locks - 1);
139 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
140 // the OSR buffer using 2 word entries: first the lock and then
141 // the oop.
142 for (int i = 0; i < number_of_locks; i++) {
143 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
144 // Verify the interpreter's monitor has a non-null object.
145 __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is NULL", __LINE__);
146 // Copy the lock field into the compiled activation.
147 __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf);
148 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i));
149 __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf);
150 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i));
151 }
152 }
153 }
154
155 // --------------------------------------------------------------------------------------------
156
157 address LIR_Assembler::emit_call_c(address a) {
158 __ align_call_far_patchable(__ pc());
159 address call_addr = __ call_c_opt(a);
160 if (call_addr == NULL) {
161 bailout("const section overflow");
162 }
163 return call_addr;
164 }
165
166 int LIR_Assembler::emit_exception_handler() {
167 // If the last instruction is a call (typically to do a throw which
168 // is coming at the end after block reordering) the return address
169 // must still point into the code area in order to avoid assertion
170 // failures when searching for the corresponding bci. => Add a nop.
171 // (was bug 5/14/1999 - gri)
172 __ nop();
173
174 // Generate code for exception handler.
175 address handler_base = __ start_a_stub(exception_handler_size());
176 if (handler_base == NULL) {
177 // Not enough space left for the handler.
178 bailout("exception handler overflow");
179 return -1;
180 }
181
182 int offset = code_offset();
183
184 address a = Runtime1::entry_for (Runtime1::handle_exception_from_callee_id);
185 address call_addr = emit_call_c(a);
186 CHECK_BAILOUT_(-1);
187 __ should_not_reach_here();
188 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
189 __ end_a_stub();
190
191 return offset;
192 }
193
194 // Emit the code to remove the frame from the stack in the exception
195 // unwind path.
196 int LIR_Assembler::emit_unwind_handler() {
197 #ifndef PRODUCT
198 if (CommentedAssembly) {
199 _masm->block_comment("Unwind handler");
200 }
201 #endif
202
203 int offset = code_offset();
204 Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved.
205 Register Rtmp1 = Z_R11;
206 Register Rtmp2 = Z_R12;
207
208 // Fetch the exception from TLS and clear out exception related thread state.
209 Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset());
210 Address exc_pc_addr = Address(Z_thread, JavaThread::exception_pc_offset());
211 __ z_lg(Z_EXC_OOP, exc_oop_addr);
212 __ clear_mem(exc_oop_addr, sizeof(oop));
213 __ clear_mem(exc_pc_addr, sizeof(intptr_t));
214
215 __ bind(_unwind_handler_entry);
216 __ verify_not_null_oop(Z_EXC_OOP);
217 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
218 __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.
219 }
220
221 // Preform needed unlocking.
222 MonitorExitStub* stub = NULL;
223 if (method()->is_synchronized()) {
224 // Runtime1::monitorexit_id expects lock address in Z_R1_scratch.
225 LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch);
226 monitor_address(0, lock);
227 stub = new MonitorExitStub(lock, true, 0);
228 __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry());
229 __ bind(*stub->continuation());
230 }
231
232 if (compilation()->env()->dtrace_method_probes()) {
233 ShouldNotReachHere(); // Not supported.
234 #if 0
235 __ mov(rdi, r15_thread);
236 __ mov_metadata(rsi, method()->constant_encoding());
237 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
238 #endif
239 }
240
241 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
242 __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved); // Restore the exception.
243 }
244
245 // Remove the activation and dispatch to the unwind handler.
246 __ pop_frame();
247 __ z_lg(Z_EXC_PC, _z_abi16(return_pc), Z_SP);
248
249 // Z_EXC_OOP: exception oop
250 // Z_EXC_PC: exception pc
251
252 // Dispatch to the unwind logic.
253 __ load_const_optimized(Z_R5, Runtime1::entry_for (Runtime1::unwind_exception_id));
254 __ z_br(Z_R5);
255
256 // Emit the slow path assembly.
257 if (stub != NULL) {
258 stub->emit_code(this);
259 }
260
261 return offset;
262 }
263
264 int LIR_Assembler::emit_deopt_handler() {
265 // If the last instruction is a call (typically to do a throw which
266 // is coming at the end after block reordering) the return address
267 // must still point into the code area in order to avoid assertion
268 // failures when searching for the corresponding bci. => Add a nop.
269 // (was bug 5/14/1999 - gri)
270 __ nop();
271
272 // Generate code for exception handler.
273 address handler_base = __ start_a_stub(deopt_handler_size());
274 if (handler_base == NULL) {
275 // Not enough space left for the handler.
276 bailout("deopt handler overflow");
277 return -1;
278 } int offset = code_offset();
279 // Size must be constant (see HandlerImpl::emit_deopt_handler).
280 __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack());
281 __ call(Z_R1_scratch);
282 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
283 __ end_a_stub();
284
285 return offset;
286 }
287
288 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
289 if (o == NULL) {
290 __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove.
291 } else {
292 AddressLiteral a = __ allocate_oop_address(o);
293 bool success = __ load_oop_from_toc(reg, a, reg);
294 if (!success) {
295 bailout("const section overflow");
296 }
297 }
298 }
299
300 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
301 // Allocate a new index in table to hold the object once it's been patched.
302 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
303 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
304
305 AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index));
306 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
307 // The NULL will be dynamically patched later so the sequence to
308 // load the address literal must not be optimized.
309 __ load_const(reg, addrlit);
310
311 patching_epilog(patch, lir_patch_normal, reg, info);
312 }
313
314 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) {
315 bool success = __ set_metadata_constant(md, reg);
316 if (!success) {
317 bailout("const section overflow");
318 return;
319 }
320 }
321
322 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
323 // Allocate a new index in table to hold the klass once it's been patched.
324 int index = __ oop_recorder()->allocate_metadata_index(NULL);
325 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
326 AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index));
327 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
328 // The NULL will be dynamically patched later so the sequence to
329 // load the address literal must not be optimized.
330 __ load_const(reg, addrlit);
331
332 patching_epilog(patch, lir_patch_normal, reg, info);
333 }
334
335 void LIR_Assembler::emit_op3(LIR_Op3* op) {
336 switch (op->code()) {
337 case lir_idiv:
338 case lir_irem:
339 arithmetic_idiv(op->code(),
340 op->in_opr1(),
341 op->in_opr2(),
342 op->in_opr3(),
343 op->result_opr(),
344 op->info());
345 break;
346 case lir_fmad: {
347 const FloatRegister opr1 = op->in_opr1()->as_double_reg(),
348 opr2 = op->in_opr2()->as_double_reg(),
349 opr3 = op->in_opr3()->as_double_reg(),
350 res = op->result_opr()->as_double_reg();
351 __ z_madbr(opr3, opr1, opr2);
352 if (res != opr3) { __ z_ldr(res, opr3); }
353 } break;
354 case lir_fmaf: {
355 const FloatRegister opr1 = op->in_opr1()->as_float_reg(),
356 opr2 = op->in_opr2()->as_float_reg(),
357 opr3 = op->in_opr3()->as_float_reg(),
358 res = op->result_opr()->as_float_reg();
359 __ z_maebr(opr3, opr1, opr2);
360 if (res != opr3) { __ z_ler(res, opr3); }
361 } break;
362 default: ShouldNotReachHere(); break;
363 }
364 }
365
366
367 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
368 #ifdef ASSERT
369 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
370 if (op->block() != NULL) { _branch_target_blocks.append(op->block()); }
371 if (op->ublock() != NULL) { _branch_target_blocks.append(op->ublock()); }
372 #endif
373
374 if (op->cond() == lir_cond_always) {
375 if (op->info() != NULL) { add_debug_info_for_branch(op->info()); }
376 __ branch_optimized(Assembler::bcondAlways, *(op->label()));
377 } else {
378 Assembler::branch_condition acond = Assembler::bcondZero;
379 if (op->code() == lir_cond_float_branch) {
380 assert(op->ublock() != NULL, "must have unordered successor");
381 __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label()));
382 }
383 switch (op->cond()) {
384 case lir_cond_equal: acond = Assembler::bcondEqual; break;
385 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; break;
386 case lir_cond_less: acond = Assembler::bcondLow; break;
387 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; break;
388 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; break;
389 case lir_cond_greater: acond = Assembler::bcondHigh; break;
390 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; break;
391 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; break;
392 default: ShouldNotReachHere();
393 }
394 __ branch_optimized(acond,*(op->label()));
395 }
396 }
397
398
399 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
400 LIR_Opr src = op->in_opr();
401 LIR_Opr dest = op->result_opr();
402
403 switch (op->bytecode()) {
404 case Bytecodes::_i2l:
405 __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT);
406 break;
407
408 case Bytecodes::_l2i:
409 __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG);
410 break;
411
412 case Bytecodes::_i2b:
413 __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT);
414 break;
415
416 case Bytecodes::_i2c:
417 __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT);
418 break;
419
420 case Bytecodes::_i2s:
421 __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT);
422 break;
423
424 case Bytecodes::_f2d:
425 assert(dest->is_double_fpu(), "check");
426 __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT);
427 break;
428
429 case Bytecodes::_d2f:
430 assert(dest->is_single_fpu(), "check");
431 __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE);
432 break;
433
434 case Bytecodes::_i2f:
435 __ z_cefbr(dest->as_float_reg(), src->as_register());
436 break;
437
438 case Bytecodes::_i2d:
439 __ z_cdfbr(dest->as_double_reg(), src->as_register());
440 break;
441
442 case Bytecodes::_l2f:
443 __ z_cegbr(dest->as_float_reg(), src->as_register_lo());
444 break;
445 case Bytecodes::_l2d:
446 __ z_cdgbr(dest->as_double_reg(), src->as_register_lo());
447 break;
448
449 case Bytecodes::_f2i:
450 case Bytecodes::_f2l: {
451 Label done;
452 FloatRegister Rsrc = src->as_float_reg();
453 Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo());
454 __ clear_reg(Rdst, true, false);
455 __ z_cebr(Rsrc, Rsrc);
456 __ z_brno(done); // NaN -> 0
457 if (op->bytecode() == Bytecodes::_f2i) {
458 __ z_cfebr(Rdst, Rsrc, Assembler::to_zero);
459 } else { // op->bytecode() == Bytecodes::_f2l
460 __ z_cgebr(Rdst, Rsrc, Assembler::to_zero);
461 }
462 __ bind(done);
463 }
464 break;
465
466 case Bytecodes::_d2i:
467 case Bytecodes::_d2l: {
468 Label done;
469 FloatRegister Rsrc = src->as_double_reg();
470 Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo());
471 __ clear_reg(Rdst, true, false); // Don't set CC.
472 __ z_cdbr(Rsrc, Rsrc);
473 __ z_brno(done); // NaN -> 0
474 if (op->bytecode() == Bytecodes::_d2i) {
475 __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero);
476 } else { // Bytecodes::_d2l
477 __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero);
478 }
479 __ bind(done);
480 }
481 break;
482
483 default: ShouldNotReachHere();
484 }
485 }
486
487 void LIR_Assembler::align_call(LIR_Code code) {
488 // End of call instruction must be 4 byte aligned.
489 int offset = __ offset();
490 switch (code) {
491 case lir_icvirtual_call:
492 offset += MacroAssembler::load_const_from_toc_size();
493 // no break
494 case lir_static_call:
495 case lir_optvirtual_call:
496 case lir_dynamic_call:
497 offset += NativeCall::call_far_pcrelative_displacement_offset;
498 break;
499 case lir_virtual_call: // currently, sparc-specific for niagara
500 default: ShouldNotReachHere();
501 }
502 if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) {
503 __ nop();
504 }
505 }
506
507 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
508 assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0,
509 "must be aligned (offset=%d)", __ offset());
510 assert(rtype == relocInfo::none ||
511 rtype == relocInfo::opt_virtual_call_type ||
512 rtype == relocInfo::static_call_type, "unexpected rtype");
513 // Prepend each BRASL with a nop.
514 __ relocate(rtype);
515 __ z_nop();
516 __ z_brasl(Z_R14, op->addr());
517 add_call_info(code_offset(), op->info());
518 }
519
520 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
521 address virtual_call_oop_addr = NULL;
522 AddressLiteral empty_ic((address) Universe::non_oop_word());
523 virtual_call_oop_addr = __ pc();
524 bool success = __ load_const_from_toc(Z_inline_cache, empty_ic);
525 if (!success) {
526 bailout("const section overflow");
527 return;
528 }
529
530 // CALL to fixup routine. Fixup routine uses ScopeDesc info
531 // to determine who we intended to call.
532 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
533 call(op, relocInfo::none);
534 }
535
536 // not supported
537 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
538 ShouldNotReachHere();
539 }
540
541 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
542 if (from_reg != to_reg) __ z_lgr(to_reg, from_reg);
543 }
544
545 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
546 assert(src->is_constant(), "should not call otherwise");
547 assert(dest->is_stack(), "should not call otherwise");
548 LIR_Const* c = src->as_constant_ptr();
549
550 unsigned int lmem = 0;
551 unsigned int lcon = 0;
552 int64_t cbits = 0;
553 Address dest_addr;
554 switch (c->type()) {
555 case T_INT: // fall through
556 case T_FLOAT:
557 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
558 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
559 break;
560
561 case T_ADDRESS:
562 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
563 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
564 break;
565
566 case T_OBJECT:
567 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
568 if (c->as_jobject() == NULL) {
569 __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8);
570 } else {
571 jobject2reg(c->as_jobject(), Z_R1_scratch);
572 __ reg2mem_opt(Z_R1_scratch, dest_addr, true);
573 }
574 return;
575
576 case T_LONG: // fall through
577 case T_DOUBLE:
578 dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
579 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
580 break;
581
582 default:
583 ShouldNotReachHere();
584 }
585
586 __ store_const(dest_addr, cbits, lmem, lcon);
587 }
588
589 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
590 assert(src->is_constant(), "should not call otherwise");
591 assert(dest->is_address(), "should not call otherwise");
592
593 LIR_Const* c = src->as_constant_ptr();
594 Address addr = as_Address(dest->as_address_ptr());
595
596 int store_offset = -1;
597
598 if (dest->as_address_ptr()->index()->is_valid()) {
599 switch (type) {
600 case T_INT: // fall through
601 case T_FLOAT:
602 __ load_const_optimized(Z_R0_scratch, c->as_jint_bits());
603 store_offset = __ offset();
604 if (Immediate::is_uimm12(addr.disp())) {
605 __ z_st(Z_R0_scratch, addr);
606 } else {
607 __ z_sty(Z_R0_scratch, addr);
608 }
609 break;
610
611 case T_ADDRESS:
612 __ load_const_optimized(Z_R1_scratch, c->as_jint_bits());
613 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
614 break;
615
616 case T_OBJECT: // fall through
617 case T_ARRAY:
618 if (c->as_jobject() == NULL) {
619 if (UseCompressedOops && !wide) {
620 __ clear_reg(Z_R1_scratch, false);
621 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
622 } else {
623 __ clear_reg(Z_R1_scratch, true);
624 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
625 }
626 } else {
627 jobject2reg(c->as_jobject(), Z_R1_scratch);
628 if (UseCompressedOops && !wide) {
629 __ encode_heap_oop(Z_R1_scratch);
630 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
631 } else {
632 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
633 }
634 }
635 assert(store_offset >= 0, "check");
636 break;
637
638 case T_LONG: // fall through
639 case T_DOUBLE:
640 __ load_const_optimized(Z_R1_scratch, (int64_t)(c->as_jlong_bits()));
641 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
642 break;
643
644 case T_BOOLEAN: // fall through
645 case T_BYTE:
646 __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint()));
647 store_offset = __ offset();
648 if (Immediate::is_uimm12(addr.disp())) {
649 __ z_stc(Z_R0_scratch, addr);
650 } else {
651 __ z_stcy(Z_R0_scratch, addr);
652 }
653 break;
654
655 case T_CHAR: // fall through
656 case T_SHORT:
657 __ load_const_optimized(Z_R0_scratch, (int16_t)(c->as_jint()));
658 store_offset = __ offset();
659 if (Immediate::is_uimm12(addr.disp())) {
660 __ z_sth(Z_R0_scratch, addr);
661 } else {
662 __ z_sthy(Z_R0_scratch, addr);
663 }
664 break;
665
666 default:
667 ShouldNotReachHere();
668 }
669
670 } else { // no index
671
672 unsigned int lmem = 0;
673 unsigned int lcon = 0;
674 int64_t cbits = 0;
675
676 switch (type) {
677 case T_INT: // fall through
678 case T_FLOAT:
679 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
680 break;
681
682 case T_ADDRESS:
683 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
684 break;
685
686 case T_OBJECT: // fall through
687 case T_ARRAY:
688 if (c->as_jobject() == NULL) {
689 if (UseCompressedOops && !wide) {
690 store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4);
691 } else {
692 store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8);
693 }
694 } else {
695 jobject2reg(c->as_jobject(), Z_R1_scratch);
696 if (UseCompressedOops && !wide) {
697 __ encode_heap_oop(Z_R1_scratch);
698 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
699 } else {
700 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
701 }
702 }
703 assert(store_offset >= 0, "check");
704 break;
705
706 case T_LONG: // fall through
707 case T_DOUBLE:
708 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
709 break;
710
711 case T_BOOLEAN: // fall through
712 case T_BYTE:
713 lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint());
714 break;
715
716 case T_CHAR: // fall through
717 case T_SHORT:
718 lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint());
719 break;
720
721 default:
722 ShouldNotReachHere();
723 }
724
725 if (store_offset == -1) {
726 store_offset = __ store_const(addr, cbits, lmem, lcon);
727 assert(store_offset >= 0, "check");
728 }
729 }
730
731 if (info != NULL) {
732 add_debug_info_for_null_check(store_offset, info);
733 }
734 }
735
736 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
737 assert(src->is_constant(), "should not call otherwise");
738 assert(dest->is_register(), "should not call otherwise");
739 LIR_Const* c = src->as_constant_ptr();
740
741 switch (c->type()) {
742 case T_INT: {
743 assert(patch_code == lir_patch_none, "no patching handled here");
744 __ load_const_optimized(dest->as_register(), c->as_jint());
745 break;
746 }
747
748 case T_ADDRESS: {
749 assert(patch_code == lir_patch_none, "no patching handled here");
750 __ load_const_optimized(dest->as_register(), c->as_jint());
751 break;
752 }
753
754 case T_LONG: {
755 assert(patch_code == lir_patch_none, "no patching handled here");
756 __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong());
757 break;
758 }
759
760 case T_OBJECT: {
761 if (patch_code != lir_patch_none) {
762 jobject2reg_with_patching(dest->as_register(), info);
763 } else {
764 jobject2reg(c->as_jobject(), dest->as_register());
765 }
766 break;
767 }
768
769 case T_METADATA: {
770 if (patch_code != lir_patch_none) {
771 klass2reg_with_patching(dest->as_register(), info);
772 } else {
773 metadata2reg(c->as_metadata(), dest->as_register());
774 }
775 break;
776 }
777
778 case T_FLOAT: {
779 Register toc_reg = Z_R1_scratch;
780 __ load_toc(toc_reg);
781 address const_addr = __ float_constant(c->as_jfloat());
782 if (const_addr == NULL) {
783 bailout("const section overflow");
784 break;
785 }
786 int displ = const_addr - _masm->code()->consts()->start();
787 if (dest->is_single_fpu()) {
788 __ z_ley(dest->as_float_reg(), displ, toc_reg);
789 } else {
790 assert(dest->is_single_cpu(), "Must be a cpu register.");
791 __ z_ly(dest->as_register(), displ, toc_reg);
792 }
793 }
794 break;
795
796 case T_DOUBLE: {
797 Register toc_reg = Z_R1_scratch;
798 __ load_toc(toc_reg);
799 address const_addr = __ double_constant(c->as_jdouble());
800 if (const_addr == NULL) {
801 bailout("const section overflow");
802 break;
803 }
804 int displ = const_addr - _masm->code()->consts()->start();
805 if (dest->is_double_fpu()) {
806 __ z_ldy(dest->as_double_reg(), displ, toc_reg);
807 } else {
808 assert(dest->is_double_cpu(), "Must be a long register.");
809 __ z_lg(dest->as_register_lo(), displ, toc_reg);
810 }
811 }
812 break;
813
814 default:
815 ShouldNotReachHere();
816 }
817 }
818
819 Address LIR_Assembler::as_Address(LIR_Address* addr) {
820 if (addr->base()->is_illegal()) {
821 Unimplemented();
822 }
823
824 Register base = addr->base()->as_pointer_register();
825
826 if (addr->index()->is_illegal()) {
827 return Address(base, addr->disp());
828 } else if (addr->index()->is_cpu_register()) {
829 Register index = addr->index()->as_pointer_register();
830 return Address(base, index, addr->disp());
831 } else if (addr->index()->is_constant()) {
832 intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp();
833 return Address(base, addr_offset);
834 } else {
835 ShouldNotReachHere();
836 return Address();
837 }
838 }
839
840 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
841 switch (type) {
842 case T_INT:
843 case T_FLOAT: {
844 Register tmp = Z_R1_scratch;
845 Address from = frame_map()->address_for_slot(src->single_stack_ix());
846 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
847 __ mem2reg_opt(tmp, from, false);
848 __ reg2mem_opt(tmp, to, false);
849 break;
850 }
851 case T_ADDRESS:
852 case T_OBJECT: {
853 Register tmp = Z_R1_scratch;
854 Address from = frame_map()->address_for_slot(src->single_stack_ix());
855 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
856 __ mem2reg_opt(tmp, from, true);
857 __ reg2mem_opt(tmp, to, true);
858 break;
859 }
860 case T_LONG:
861 case T_DOUBLE: {
862 Register tmp = Z_R1_scratch;
863 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
864 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
865 __ mem2reg_opt(tmp, from, true);
866 __ reg2mem_opt(tmp, to, true);
867 break;
868 }
869
870 default:
871 ShouldNotReachHere();
872 }
873 }
874
875 // 4-byte accesses only! Don't use it to access 8 bytes!
876 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
877 ShouldNotCallThis();
878 return 0; // unused
879 }
880
881 // 4-byte accesses only! Don't use it to access 8 bytes!
882 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
883 ShouldNotCallThis();
884 return 0; // unused
885 }
886
887 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code,
888 CodeEmitInfo* info, bool wide, bool unaligned) {
889
890 assert(type != T_METADATA, "load of metadata ptr not supported");
891 LIR_Address* addr = src_opr->as_address_ptr();
892 LIR_Opr to_reg = dest;
893
894 Register src = addr->base()->as_pointer_register();
895 Register disp_reg = Z_R0;
896 int disp_value = addr->disp();
897 bool needs_patching = (patch_code != lir_patch_none);
898
899 if (addr->base()->type() == T_OBJECT) {
900 __ verify_oop(src);
901 }
902
903 PatchingStub* patch = NULL;
904 if (needs_patching) {
905 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
906 assert(!to_reg->is_double_cpu() ||
907 patch_code == lir_patch_none ||
908 patch_code == lir_patch_normal, "patching doesn't match register");
909 }
910
911 if (addr->index()->is_illegal()) {
912 if (!Immediate::is_simm20(disp_value)) {
913 if (needs_patching) {
914 __ load_const(Z_R1_scratch, (intptr_t)0);
915 } else {
916 __ load_const_optimized(Z_R1_scratch, disp_value);
917 }
918 disp_reg = Z_R1_scratch;
919 disp_value = 0;
920 }
921 } else {
922 if (!Immediate::is_simm20(disp_value)) {
923 __ load_const_optimized(Z_R1_scratch, disp_value);
924 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
925 disp_reg = Z_R1_scratch;
926 disp_value = 0;
927 }
928 disp_reg = addr->index()->as_pointer_register();
929 }
930
931 // Remember the offset of the load. The patching_epilog must be done
932 // before the call to add_debug_info, otherwise the PcDescs don't get
933 // entered in increasing order.
934 int offset = code_offset();
935
936 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
937
938 bool short_disp = Immediate::is_uimm12(disp_value);
939
940 switch (type) {
941 case T_BOOLEAN: // fall through
942 case T_BYTE : __ z_lb(dest->as_register(), disp_value, disp_reg, src); break;
943 case T_CHAR : __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break;
944 case T_SHORT :
945 if (short_disp) {
946 __ z_lh(dest->as_register(), disp_value, disp_reg, src);
947 } else {
948 __ z_lhy(dest->as_register(), disp_value, disp_reg, src);
949 }
950 break;
951 case T_INT :
952 if (short_disp) {
953 __ z_l(dest->as_register(), disp_value, disp_reg, src);
954 } else {
955 __ z_ly(dest->as_register(), disp_value, disp_reg, src);
956 }
957 break;
958 case T_ADDRESS:
959 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
960 __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
961 __ decode_klass_not_null(dest->as_register());
962 } else {
963 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
964 }
965 break;
966 case T_ARRAY : // fall through
967 case T_OBJECT:
968 {
969 if (UseCompressedOops && !wide) {
970 __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
971 __ oop_decoder(dest->as_register(), dest->as_register(), true);
972 } else {
973 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
974 }
975 break;
976 }
977 case T_FLOAT:
978 if (short_disp) {
979 __ z_le(dest->as_float_reg(), disp_value, disp_reg, src);
980 } else {
981 __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src);
982 }
983 break;
984 case T_DOUBLE:
985 if (short_disp) {
986 __ z_ld(dest->as_double_reg(), disp_value, disp_reg, src);
987 } else {
988 __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src);
989 }
990 break;
991 case T_LONG : __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break;
992 default : ShouldNotReachHere();
993 }
994 if (type == T_ARRAY || type == T_OBJECT) {
995 __ verify_oop(dest->as_register());
996 }
997
998 if (patch != NULL) {
999 patching_epilog(patch, patch_code, src, info);
1000 }
1001 if (info != NULL) add_debug_info_for_null_check(offset, info);
1002 }
1003
1004 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1005 assert(src->is_stack(), "should not call otherwise");
1006 assert(dest->is_register(), "should not call otherwise");
1007
1008 if (dest->is_single_cpu()) {
1009 if (type == T_ARRAY || type == T_OBJECT) {
1010 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
1011 __ verify_oop(dest->as_register());
1012 } else if (type == T_METADATA) {
1013 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
1014 } else {
1015 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false);
1016 }
1017 } else if (dest->is_double_cpu()) {
1018 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix());
1019 __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true);
1020 } else if (dest->is_single_fpu()) {
1021 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1022 __ mem2freg_opt(dest->as_float_reg(), src_addr, false);
1023 } else if (dest->is_double_fpu()) {
1024 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1025 __ mem2freg_opt(dest->as_double_reg(), src_addr, true);
1026 } else {
1027 ShouldNotReachHere();
1028 }
1029 }
1030
1031 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1032 assert(src->is_register(), "should not call otherwise");
1033 assert(dest->is_stack(), "should not call otherwise");
1034
1035 if (src->is_single_cpu()) {
1036 const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
1037 if (type == T_OBJECT || type == T_ARRAY) {
1038 __ verify_oop(src->as_register());
1039 __ reg2mem_opt(src->as_register(), dst, true);
1040 } else if (type == T_METADATA) {
1041 __ reg2mem_opt(src->as_register(), dst, true);
1042 } else {
1043 __ reg2mem_opt(src->as_register(), dst, false);
1044 }
1045 } else if (src->is_double_cpu()) {
1046 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix());
1047 __ reg2mem_opt(src->as_register_lo(), dstLO, true);
1048 } else if (src->is_single_fpu()) {
1049 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1050 __ freg2mem_opt(src->as_float_reg(), dst_addr, false);
1051 } else if (src->is_double_fpu()) {
1052 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1053 __ freg2mem_opt(src->as_double_reg(), dst_addr, true);
1054 } else {
1055 ShouldNotReachHere();
1056 }
1057 }
1058
1059 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1060 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1061 if (from_reg->is_double_fpu()) {
1062 // double to double moves
1063 assert(to_reg->is_double_fpu(), "should match");
1064 __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg());
1065 } else {
1066 // float to float moves
1067 assert(to_reg->is_single_fpu(), "should match");
1068 __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg());
1069 }
1070 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1071 if (from_reg->is_double_cpu()) {
1072 __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1073 } else if (to_reg->is_double_cpu()) {
1074 // int to int moves
1075 __ z_lgr(to_reg->as_register_lo(), from_reg->as_register());
1076 } else {
1077 // int to int moves
1078 __ z_lgr(to_reg->as_register(), from_reg->as_register());
1079 }
1080 } else {
1081 ShouldNotReachHere();
1082 }
1083 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1084 __ verify_oop(to_reg->as_register());
1085 }
1086 }
1087
1088 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
1089 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1090 bool wide, bool unaligned) {
1091 assert(type != T_METADATA, "store of metadata ptr not supported");
1092 LIR_Address* addr = dest_opr->as_address_ptr();
1093
1094 Register dest = addr->base()->as_pointer_register();
1095 Register disp_reg = Z_R0;
1096 int disp_value = addr->disp();
1097 bool needs_patching = (patch_code != lir_patch_none);
1098
1099 if (addr->base()->is_oop_register()) {
1100 __ verify_oop(dest);
1101 }
1102
1103 PatchingStub* patch = NULL;
1104 if (needs_patching) {
1105 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1106 assert(!from->is_double_cpu() ||
1107 patch_code == lir_patch_none ||
1108 patch_code == lir_patch_normal, "patching doesn't match register");
1109 }
1110
1111 assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption");
1112 if (addr->index()->is_illegal()) {
1113 if (!Immediate::is_simm20(disp_value)) {
1114 if (needs_patching) {
1115 __ load_const(Z_R1_scratch, (intptr_t)0);
1116 } else {
1117 __ load_const_optimized(Z_R1_scratch, disp_value);
1118 }
1119 disp_reg = Z_R1_scratch;
1120 disp_value = 0;
1121 }
1122 } else {
1123 if (!Immediate::is_simm20(disp_value)) {
1124 __ load_const_optimized(Z_R1_scratch, disp_value);
1125 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
1126 disp_reg = Z_R1_scratch;
1127 disp_value = 0;
1128 }
1129 disp_reg = addr->index()->as_pointer_register();
1130 }
1131
1132 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
1133
1134 if (type == T_ARRAY || type == T_OBJECT) {
1135 __ verify_oop(from->as_register());
1136 }
1137
1138 bool short_disp = Immediate::is_uimm12(disp_value);
1139
1140 // Remember the offset of the store. The patching_epilog must be done
1141 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1142 // entered in increasing order.
1143 int offset = code_offset();
1144 switch (type) {
1145 case T_BOOLEAN: // fall through
1146 case T_BYTE :
1147 if (short_disp) {
1148 __ z_stc(from->as_register(), disp_value, disp_reg, dest);
1149 } else {
1150 __ z_stcy(from->as_register(), disp_value, disp_reg, dest);
1151 }
1152 break;
1153 case T_CHAR : // fall through
1154 case T_SHORT :
1155 if (short_disp) {
1156 __ z_sth(from->as_register(), disp_value, disp_reg, dest);
1157 } else {
1158 __ z_sthy(from->as_register(), disp_value, disp_reg, dest);
1159 }
1160 break;
1161 case T_INT :
1162 if (short_disp) {
1163 __ z_st(from->as_register(), disp_value, disp_reg, dest);
1164 } else {
1165 __ z_sty(from->as_register(), disp_value, disp_reg, dest);
1166 }
1167 break;
1168 case T_LONG : __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break;
1169 case T_ADDRESS: __ z_stg(from->as_register(), disp_value, disp_reg, dest); break;
1170 break;
1171 case T_ARRAY : // fall through
1172 case T_OBJECT:
1173 {
1174 if (UseCompressedOops && !wide) {
1175 Register compressed_src = Z_R14;
1176 __ oop_encoder(compressed_src, from->as_register(), true, (disp_reg != Z_R1) ? Z_R1 : Z_R0, -1, true);
1177 offset = code_offset();
1178 if (short_disp) {
1179 __ z_st(compressed_src, disp_value, disp_reg, dest);
1180 } else {
1181 __ z_sty(compressed_src, disp_value, disp_reg, dest);
1182 }
1183 } else {
1184 __ z_stg(from->as_register(), disp_value, disp_reg, dest);
1185 }
1186 break;
1187 }
1188 case T_FLOAT :
1189 if (short_disp) {
1190 __ z_ste(from->as_float_reg(), disp_value, disp_reg, dest);
1191 } else {
1192 __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest);
1193 }
1194 break;
1195 case T_DOUBLE:
1196 if (short_disp) {
1197 __ z_std(from->as_double_reg(), disp_value, disp_reg, dest);
1198 } else {
1199 __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest);
1200 }
1201 break;
1202 default: ShouldNotReachHere();
1203 }
1204
1205 if (patch != NULL) {
1206 patching_epilog(patch, patch_code, dest, info);
1207 }
1208
1209 if (info != NULL) add_debug_info_for_null_check(offset, info);
1210 }
1211
1212
1213 void LIR_Assembler::return_op(LIR_Opr result) {
1214 assert(result->is_illegal() ||
1215 (result->is_single_cpu() && result->as_register() == Z_R2) ||
1216 (result->is_double_cpu() && result->as_register_lo() == Z_R2) ||
1217 (result->is_single_fpu() && result->as_float_reg() == Z_F0) ||
1218 (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention");
1219
1220 if (SafepointMechanism::uses_thread_local_poll()) {
1221 __ z_lg(Z_R1_scratch, Address(Z_thread, Thread::polling_page_offset()));
1222 } else {
1223 AddressLiteral pp(os::get_polling_page());
1224 __ load_const_optimized(Z_R1_scratch, pp);
1225 }
1226
1227 // Pop the frame before the safepoint code.
1228 __ pop_frame_restore_retPC(initial_frame_size_in_bytes());
1229
1230 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1231 __ reserved_stack_check(Z_R14);
1232 }
1233
1234 // We need to mark the code position where the load from the safepoint
1235 // polling page was emitted as relocInfo::poll_return_type here.
1236 __ relocate(relocInfo::poll_return_type);
1237 __ load_from_polling_page(Z_R1_scratch);
1238
1239 __ z_br(Z_R14); // Return to caller.
1240 }
1241
1242 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1243 const Register poll_addr = tmp->as_register_lo();
1244 if (SafepointMechanism::uses_thread_local_poll()) {
1245 __ z_lg(poll_addr, Address(Z_thread, Thread::polling_page_offset()));
1246 } else {
1247 AddressLiteral pp(os::get_polling_page());
1248 __ load_const_optimized(poll_addr, pp);
1249 }
1250 guarantee(info != NULL, "Shouldn't be NULL");
1251 add_debug_info_for_branch(info);
1252 int offset = __ offset();
1253 __ relocate(relocInfo::poll_type);
1254 __ load_from_polling_page(poll_addr);
1255 return offset;
1256 }
1257
1258 void LIR_Assembler::emit_static_call_stub() {
1259
1260 // Stub is fixed up when the corresponding call is converted from calling
1261 // compiled code to calling interpreted code.
1262
1263 address call_pc = __ pc();
1264 address stub = __ start_a_stub(call_stub_size());
1265 if (stub == NULL) {
1266 bailout("static call stub overflow");
1267 return;
1268 }
1269
1270 int start = __ offset();
1271
1272 __ relocate(static_stub_Relocation::spec(call_pc));
1273
1274 // See also Matcher::interpreter_method_oop_reg().
1275 AddressLiteral meta = __ allocate_metadata_address(NULL);
1276 bool success = __ load_const_from_toc(Z_method, meta);
1277
1278 __ set_inst_mark();
1279 AddressLiteral a((address)-1);
1280 success = success && __ load_const_from_toc(Z_R1, a);
1281 if (!success) {
1282 bailout("const section overflow");
1283 return;
1284 }
1285
1286 __ z_br(Z_R1);
1287 assert(__ offset() - start <= call_stub_size(), "stub too big");
1288 __ end_a_stub(); // Update current stubs pointer and restore insts_end.
1289 }
1290
1291 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1292 bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
1293 if (opr1->is_single_cpu()) {
1294 Register reg1 = opr1->as_register();
1295 if (opr2->is_single_cpu()) {
1296 // cpu register - cpu register
1297 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1298 __ z_clgr(reg1, opr2->as_register());
1299 } else {
1300 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
1301 if (unsigned_comp) {
1302 __ z_clr(reg1, opr2->as_register());
1303 } else {
1304 __ z_cr(reg1, opr2->as_register());
1305 }
1306 }
1307 } else if (opr2->is_stack()) {
1308 // cpu register - stack
1309 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1310 __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1311 } else {
1312 if (unsigned_comp) {
1313 __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1314 } else {
1315 __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1316 }
1317 }
1318 } else if (opr2->is_constant()) {
1319 // cpu register - constant
1320 LIR_Const* c = opr2->as_constant_ptr();
1321 if (c->type() == T_INT) {
1322 if (unsigned_comp) {
1323 __ z_clfi(reg1, c->as_jint());
1324 } else {
1325 __ z_cfi(reg1, c->as_jint());
1326 }
1327 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
1328 // In 64bit oops are single register.
1329 jobject o = c->as_jobject();
1330 if (o == NULL) {
1331 __ z_ltgr(reg1, reg1);
1332 } else {
1333 jobject2reg(o, Z_R1_scratch);
1334 __ z_cgr(reg1, Z_R1_scratch);
1335 }
1336 } else {
1337 fatal("unexpected type: %s", basictype_to_str(c->type()));
1338 }
1339 // cpu register - address
1340 } else if (opr2->is_address()) {
1341 if (op->info() != NULL) {
1342 add_debug_info_for_null_check_here(op->info());
1343 }
1344 if (unsigned_comp) {
1345 __ z_cly(reg1, as_Address(opr2->as_address_ptr()));
1346 } else {
1347 __ z_cy(reg1, as_Address(opr2->as_address_ptr()));
1348 }
1349 } else {
1350 ShouldNotReachHere();
1351 }
1352
1353 } else if (opr1->is_double_cpu()) {
1354 assert(!unsigned_comp, "unexpected");
1355 Register xlo = opr1->as_register_lo();
1356 Register xhi = opr1->as_register_hi();
1357 if (opr2->is_double_cpu()) {
1358 __ z_cgr(xlo, opr2->as_register_lo());
1359 } else if (opr2->is_constant()) {
1360 // cpu register - constant 0
1361 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
1362 __ z_ltgr(xlo, xlo);
1363 } else {
1364 ShouldNotReachHere();
1365 }
1366
1367 } else if (opr1->is_single_fpu()) {
1368 if (opr2->is_single_fpu()) {
1369 __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg());
1370 } else {
1371 // stack slot
1372 Address addr = frame_map()->address_for_slot(opr2->single_stack_ix());
1373 if (Immediate::is_uimm12(addr.disp())) {
1374 __ z_ceb(opr1->as_float_reg(), addr);
1375 } else {
1376 __ z_ley(Z_fscratch_1, addr);
1377 __ z_cebr(opr1->as_float_reg(), Z_fscratch_1);
1378 }
1379 }
1380 } else if (opr1->is_double_fpu()) {
1381 if (opr2->is_double_fpu()) {
1382 __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg());
1383 } else {
1384 // stack slot
1385 Address addr = frame_map()->address_for_slot(opr2->double_stack_ix());
1386 if (Immediate::is_uimm12(addr.disp())) {
1387 __ z_cdb(opr1->as_double_reg(), addr);
1388 } else {
1389 __ z_ldy(Z_fscratch_1, addr);
1390 __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1);
1391 }
1392 }
1393 } else {
1394 ShouldNotReachHere();
1395 }
1396 }
1397
1398 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1399 Label done;
1400 Register dreg = dst->as_register();
1401
1402 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1403 assert((left->is_single_fpu() && right->is_single_fpu()) ||
1404 (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types");
1405 bool is_single = left->is_single_fpu();
1406 bool is_unordered_less = (code == lir_ucmp_fd2i);
1407 FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg();
1408 FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg();
1409 if (is_single) {
1410 __ z_cebr(lreg, rreg);
1411 } else {
1412 __ z_cdbr(lreg, rreg);
1413 }
1414 if (VM_Version::has_LoadStoreConditional()) {
1415 Register one = Z_R0_scratch;
1416 Register minus_one = Z_R1_scratch;
1417 __ z_lghi(minus_one, -1);
1418 __ z_lghi(one, 1);
1419 __ z_lghi(dreg, 0);
1420 __ z_locgr(dreg, one, is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered);
1421 __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow);
1422 } else {
1423 __ clear_reg(dreg, true, false);
1424 __ z_bre(done); // if (left == right) dst = 0
1425
1426 // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1
1427 __ z_lhi(dreg, 1);
1428 __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done);
1429
1430 // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1
1431 __ z_lhi(dreg, -1);
1432 }
1433 } else {
1434 assert(code == lir_cmp_l2i, "check");
1435 if (VM_Version::has_LoadStoreConditional()) {
1436 Register one = Z_R0_scratch;
1437 Register minus_one = Z_R1_scratch;
1438 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1439 __ z_lghi(minus_one, -1);
1440 __ z_lghi(one, 1);
1441 __ z_lghi(dreg, 0);
1442 __ z_locgr(dreg, one, Assembler::bcondHigh);
1443 __ z_locgr(dreg, minus_one, Assembler::bcondLow);
1444 } else {
1445 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1446 __ z_lghi(dreg, 0); // eq value
1447 __ z_bre(done);
1448 __ z_lghi(dreg, 1); // gt value
1449 __ z_brh(done);
1450 __ z_lghi(dreg, -1); // lt value
1451 }
1452 }
1453 __ bind(done);
1454 }
1455
1456 // result = condition ? opr1 : opr2
1457 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1458 Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual;
1459 switch (condition) {
1460 case lir_cond_equal: acond = Assembler::bcondEqual; ncond = Assembler::bcondNotEqual; break;
1461 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual; break;
1462 case lir_cond_less: acond = Assembler::bcondLow; ncond = Assembler::bcondNotLow; break;
1463 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1464 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1465 case lir_cond_greater: acond = Assembler::bcondHigh; ncond = Assembler::bcondNotHigh; break;
1466 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1467 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1468 default: ShouldNotReachHere();
1469 }
1470
1471 if (opr1->is_cpu_register()) {
1472 reg2reg(opr1, result);
1473 } else if (opr1->is_stack()) {
1474 stack2reg(opr1, result, result->type());
1475 } else if (opr1->is_constant()) {
1476 const2reg(opr1, result, lir_patch_none, NULL);
1477 } else {
1478 ShouldNotReachHere();
1479 }
1480
1481 if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) {
1482 // Optimized version that does not require a branch.
1483 if (opr2->is_single_cpu()) {
1484 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1485 __ z_locgr(result->as_register(), opr2->as_register(), ncond);
1486 } else if (opr2->is_double_cpu()) {
1487 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1488 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1489 __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond);
1490 } else if (opr2->is_single_stack()) {
1491 __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond);
1492 } else if (opr2->is_double_stack()) {
1493 __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond);
1494 } else {
1495 ShouldNotReachHere();
1496 }
1497 } else {
1498 Label skip;
1499 __ z_brc(acond, skip);
1500 if (opr2->is_cpu_register()) {
1501 reg2reg(opr2, result);
1502 } else if (opr2->is_stack()) {
1503 stack2reg(opr2, result, result->type());
1504 } else if (opr2->is_constant()) {
1505 const2reg(opr2, result, lir_patch_none, NULL);
1506 } else {
1507 ShouldNotReachHere();
1508 }
1509 __ bind(skip);
1510 }
1511 }
1512
1513 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1514 CodeEmitInfo* info, bool pop_fpu_stack) {
1515 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1516
1517 if (left->is_single_cpu()) {
1518 assert(left == dest, "left and dest must be equal");
1519 Register lreg = left->as_register();
1520
1521 if (right->is_single_cpu()) {
1522 // cpu register - cpu register
1523 Register rreg = right->as_register();
1524 switch (code) {
1525 case lir_add: __ z_ar (lreg, rreg); break;
1526 case lir_sub: __ z_sr (lreg, rreg); break;
1527 case lir_mul: __ z_msr(lreg, rreg); break;
1528 default: ShouldNotReachHere();
1529 }
1530
1531 } else if (right->is_stack()) {
1532 // cpu register - stack
1533 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1534 switch (code) {
1535 case lir_add: __ z_ay(lreg, raddr); break;
1536 case lir_sub: __ z_sy(lreg, raddr); break;
1537 default: ShouldNotReachHere();
1538 }
1539
1540 } else if (right->is_constant()) {
1541 // cpu register - constant
1542 jint c = right->as_constant_ptr()->as_jint();
1543 switch (code) {
1544 case lir_add: __ z_agfi(lreg, c); break;
1545 case lir_sub: __ z_agfi(lreg, -c); break; // note: -min_jint == min_jint
1546 case lir_mul: __ z_msfi(lreg, c); break;
1547 default: ShouldNotReachHere();
1548 }
1549
1550 } else {
1551 ShouldNotReachHere();
1552 }
1553
1554 } else if (left->is_double_cpu()) {
1555 assert(left == dest, "left and dest must be equal");
1556 Register lreg_lo = left->as_register_lo();
1557 Register lreg_hi = left->as_register_hi();
1558
1559 if (right->is_double_cpu()) {
1560 // cpu register - cpu register
1561 Register rreg_lo = right->as_register_lo();
1562 Register rreg_hi = right->as_register_hi();
1563 assert_different_registers(lreg_lo, rreg_lo);
1564 switch (code) {
1565 case lir_add:
1566 __ z_agr(lreg_lo, rreg_lo);
1567 break;
1568 case lir_sub:
1569 __ z_sgr(lreg_lo, rreg_lo);
1570 break;
1571 case lir_mul:
1572 __ z_msgr(lreg_lo, rreg_lo);
1573 break;
1574 default:
1575 ShouldNotReachHere();
1576 }
1577
1578 } else if (right->is_constant()) {
1579 // cpu register - constant
1580 jlong c = right->as_constant_ptr()->as_jlong_bits();
1581 switch (code) {
1582 case lir_add: __ z_agfi(lreg_lo, c); break;
1583 case lir_sub:
1584 if (c != min_jint) {
1585 __ z_agfi(lreg_lo, -c);
1586 } else {
1587 // -min_jint cannot be represented as simm32 in z_agfi
1588 // min_jint sign extended: 0xffffffff80000000
1589 // -min_jint as 64 bit integer: 0x0000000080000000
1590 // 0x80000000 can be represented as uimm32 in z_algfi
1591 // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000
1592 __ z_algfi(lreg_lo, UCONST64(0x80000000));
1593 }
1594 break;
1595 case lir_mul: __ z_msgfi(lreg_lo, c); break;
1596 default:
1597 ShouldNotReachHere();
1598 }
1599
1600 } else {
1601 ShouldNotReachHere();
1602 }
1603
1604 } else if (left->is_single_fpu()) {
1605 assert(left == dest, "left and dest must be equal");
1606 FloatRegister lreg = left->as_float_reg();
1607 FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg;
1608 Address raddr;
1609
1610 if (rreg == fnoreg) {
1611 assert(right->is_single_stack(), "constants should be loaded into register");
1612 raddr = frame_map()->address_for_slot(right->single_stack_ix());
1613 if (!Immediate::is_uimm12(raddr.disp())) {
1614 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false);
1615 }
1616 }
1617
1618 if (rreg != fnoreg) {
1619 switch (code) {
1620 case lir_add: __ z_aebr(lreg, rreg); break;
1621 case lir_sub: __ z_sebr(lreg, rreg); break;
1622 case lir_mul_strictfp: // fall through
1623 case lir_mul: __ z_meebr(lreg, rreg); break;
1624 case lir_div_strictfp: // fall through
1625 case lir_div: __ z_debr(lreg, rreg); break;
1626 default: ShouldNotReachHere();
1627 }
1628 } else {
1629 switch (code) {
1630 case lir_add: __ z_aeb(lreg, raddr); break;
1631 case lir_sub: __ z_seb(lreg, raddr); break;
1632 case lir_mul_strictfp: // fall through
1633 case lir_mul: __ z_meeb(lreg, raddr); break;
1634 case lir_div_strictfp: // fall through
1635 case lir_div: __ z_deb(lreg, raddr); break;
1636 default: ShouldNotReachHere();
1637 }
1638 }
1639 } else if (left->is_double_fpu()) {
1640 assert(left == dest, "left and dest must be equal");
1641 FloatRegister lreg = left->as_double_reg();
1642 FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg;
1643 Address raddr;
1644
1645 if (rreg == fnoreg) {
1646 assert(right->is_double_stack(), "constants should be loaded into register");
1647 raddr = frame_map()->address_for_slot(right->double_stack_ix());
1648 if (!Immediate::is_uimm12(raddr.disp())) {
1649 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true);
1650 }
1651 }
1652
1653 if (rreg != fnoreg) {
1654 switch (code) {
1655 case lir_add: __ z_adbr(lreg, rreg); break;
1656 case lir_sub: __ z_sdbr(lreg, rreg); break;
1657 case lir_mul_strictfp: // fall through
1658 case lir_mul: __ z_mdbr(lreg, rreg); break;
1659 case lir_div_strictfp: // fall through
1660 case lir_div: __ z_ddbr(lreg, rreg); break;
1661 default: ShouldNotReachHere();
1662 }
1663 } else {
1664 switch (code) {
1665 case lir_add: __ z_adb(lreg, raddr); break;
1666 case lir_sub: __ z_sdb(lreg, raddr); break;
1667 case lir_mul_strictfp: // fall through
1668 case lir_mul: __ z_mdb(lreg, raddr); break;
1669 case lir_div_strictfp: // fall through
1670 case lir_div: __ z_ddb(lreg, raddr); break;
1671 default: ShouldNotReachHere();
1672 }
1673 }
1674 } else if (left->is_address()) {
1675 assert(left == dest, "left and dest must be equal");
1676 assert(code == lir_add, "unsupported operation");
1677 assert(right->is_constant(), "unsupported operand");
1678 jint c = right->as_constant_ptr()->as_jint();
1679 LIR_Address* lir_addr = left->as_address_ptr();
1680 Address addr = as_Address(lir_addr);
1681 switch (lir_addr->type()) {
1682 case T_INT:
1683 __ add2mem_32(addr, c, Z_R1_scratch);
1684 break;
1685 case T_LONG:
1686 __ add2mem_64(addr, c, Z_R1_scratch);
1687 break;
1688 default:
1689 ShouldNotReachHere();
1690 }
1691 } else {
1692 ShouldNotReachHere();
1693 }
1694 }
1695
1696 void LIR_Assembler::fpop() {
1697 // do nothing
1698 }
1699
1700 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1701 switch (code) {
1702 case lir_sqrt: {
1703 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1704 FloatRegister src_reg = value->as_double_reg();
1705 FloatRegister dst_reg = dest->as_double_reg();
1706 __ z_sqdbr(dst_reg, src_reg);
1707 break;
1708 }
1709 case lir_abs: {
1710 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1711 FloatRegister src_reg = value->as_double_reg();
1712 FloatRegister dst_reg = dest->as_double_reg();
1713 __ z_lpdbr(dst_reg, src_reg);
1714 break;
1715 }
1716 default: {
1717 ShouldNotReachHere();
1718 break;
1719 }
1720 }
1721 }
1722
1723 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1724 if (left->is_single_cpu()) {
1725 Register reg = left->as_register();
1726 if (right->is_constant()) {
1727 int val = right->as_constant_ptr()->as_jint();
1728 switch (code) {
1729 case lir_logic_and: __ z_nilf(reg, val); break;
1730 case lir_logic_or: __ z_oilf(reg, val); break;
1731 case lir_logic_xor: __ z_xilf(reg, val); break;
1732 default: ShouldNotReachHere();
1733 }
1734 } else if (right->is_stack()) {
1735 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1736 switch (code) {
1737 case lir_logic_and: __ z_ny(reg, raddr); break;
1738 case lir_logic_or: __ z_oy(reg, raddr); break;
1739 case lir_logic_xor: __ z_xy(reg, raddr); break;
1740 default: ShouldNotReachHere();
1741 }
1742 } else {
1743 Register rright = right->as_register();
1744 switch (code) {
1745 case lir_logic_and: __ z_nr(reg, rright); break;
1746 case lir_logic_or : __ z_or(reg, rright); break;
1747 case lir_logic_xor: __ z_xr(reg, rright); break;
1748 default: ShouldNotReachHere();
1749 }
1750 }
1751 move_regs(reg, dst->as_register());
1752 } else {
1753 Register l_lo = left->as_register_lo();
1754 if (right->is_constant()) {
1755 __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong());
1756 switch (code) {
1757 case lir_logic_and:
1758 __ z_ngr(l_lo, Z_R1_scratch);
1759 break;
1760 case lir_logic_or:
1761 __ z_ogr(l_lo, Z_R1_scratch);
1762 break;
1763 case lir_logic_xor:
1764 __ z_xgr(l_lo, Z_R1_scratch);
1765 break;
1766 default: ShouldNotReachHere();
1767 }
1768 } else {
1769 Register r_lo;
1770 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
1771 r_lo = right->as_register();
1772 } else {
1773 r_lo = right->as_register_lo();
1774 }
1775 switch (code) {
1776 case lir_logic_and:
1777 __ z_ngr(l_lo, r_lo);
1778 break;
1779 case lir_logic_or:
1780 __ z_ogr(l_lo, r_lo);
1781 break;
1782 case lir_logic_xor:
1783 __ z_xgr(l_lo, r_lo);
1784 break;
1785 default: ShouldNotReachHere();
1786 }
1787 }
1788
1789 Register dst_lo = dst->as_register_lo();
1790
1791 move_regs(l_lo, dst_lo);
1792 }
1793 }
1794
1795 // See operand selection in LIRGenerator::do_ArithmeticOp_Int().
1796 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1797 if (left->is_double_cpu()) {
1798 // 64 bit integer case
1799 assert(left->is_double_cpu(), "left must be register");
1800 assert(right->is_double_cpu() || is_power_of_2_long(right->as_jlong()),
1801 "right must be register or power of 2 constant");
1802 assert(result->is_double_cpu(), "result must be register");
1803
1804 Register lreg = left->as_register_lo();
1805 Register dreg = result->as_register_lo();
1806
1807 if (right->is_constant()) {
1808 // Convert division by a power of two into some shifts and logical operations.
1809 Register treg1 = Z_R0_scratch;
1810 Register treg2 = Z_R1_scratch;
1811 jlong divisor = right->as_jlong();
1812 jlong log_divisor = log2_long(right->as_jlong());
1813
1814 if (divisor == min_jlong) {
1815 // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1.
1816 if (dreg == lreg) {
1817 NearLabel done;
1818 __ load_const_optimized(treg2, min_jlong);
1819 __ z_cgr(lreg, treg2);
1820 __ z_lghi(dreg, 0); // Preserves condition code.
1821 __ z_brne(done);
1822 __ z_lghi(dreg, 1); // min_jlong / min_jlong = 1
1823 __ bind(done);
1824 } else {
1825 assert_different_registers(dreg, lreg);
1826 NearLabel done;
1827 __ z_lghi(dreg, 0);
1828 __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done);
1829 __ z_lghi(dreg, 1);
1830 __ bind(done);
1831 }
1832 return;
1833 }
1834 __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG);
1835 if (divisor == 2) {
1836 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1837 } else {
1838 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1839 __ and_imm(treg2, divisor - 1, treg1, true);
1840 }
1841 if (code == lir_idiv) {
1842 __ z_agr(dreg, treg2);
1843 __ z_srag(dreg, dreg, log_divisor);
1844 } else {
1845 assert(code == lir_irem, "check");
1846 __ z_agr(treg2, dreg);
1847 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1848 __ z_sgr(dreg, treg2);
1849 }
1850 return;
1851 }
1852
1853 // Divisor is not a power of 2 constant.
1854 Register rreg = right->as_register_lo();
1855 Register treg = temp->as_register_lo();
1856 assert(right->is_double_cpu(), "right must be register");
1857 assert(lreg == Z_R11, "see ldivInOpr()");
1858 assert(rreg != lreg, "right register must not be same as left register");
1859 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) ||
1860 (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()");
1861
1862 Register R1 = lreg->predecessor();
1863 Register R2 = rreg;
1864 assert(code != lir_idiv || lreg==dreg, "see code below");
1865 if (code == lir_idiv) {
1866 __ z_lcgr(lreg, lreg);
1867 } else {
1868 __ clear_reg(dreg, true, false);
1869 }
1870 NearLabel done;
1871 __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done);
1872 if (code == lir_idiv) {
1873 __ z_lcgr(lreg, lreg); // Revert lcgr above.
1874 }
1875 if (ImplicitDiv0Checks) {
1876 // No debug info because the idiv won't trap.
1877 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1878 // which is unnecessary, too.
1879 add_debug_info_for_div0(__ offset(), info);
1880 }
1881 __ z_dsgr(R1, R2);
1882 __ bind(done);
1883 return;
1884 }
1885
1886 // 32 bit integer case
1887
1888 assert(left->is_single_cpu(), "left must be register");
1889 assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant");
1890 assert(result->is_single_cpu(), "result must be register");
1891
1892 Register lreg = left->as_register();
1893 Register dreg = result->as_register();
1894
1895 if (right->is_constant()) {
1896 // Convert division by a power of two into some shifts and logical operations.
1897 Register treg1 = Z_R0_scratch;
1898 Register treg2 = Z_R1_scratch;
1899 jlong divisor = right->as_jint();
1900 jlong log_divisor = log2_long(right->as_jint());
1901 __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend
1902 if (divisor == 2) {
1903 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1904 } else {
1905 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1906 __ and_imm(treg2, divisor - 1, treg1, true);
1907 }
1908 if (code == lir_idiv) {
1909 __ z_agr(dreg, treg2);
1910 __ z_srag(dreg, dreg, log_divisor);
1911 } else {
1912 assert(code == lir_irem, "check");
1913 __ z_agr(treg2, dreg);
1914 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1915 __ z_sgr(dreg, treg2);
1916 }
1917 return;
1918 }
1919
1920 // Divisor is not a power of 2 constant.
1921 Register rreg = right->as_register();
1922 Register treg = temp->as_register();
1923 assert(right->is_single_cpu(), "right must be register");
1924 assert(lreg == Z_R11, "left register must be rax,");
1925 assert(rreg != lreg, "right register must not be same as left register");
1926 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10)
1927 || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()");
1928
1929 Register R1 = lreg->predecessor();
1930 Register R2 = rreg;
1931 __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend
1932 if (ImplicitDiv0Checks) {
1933 // No debug info because the idiv won't trap.
1934 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1935 // which is unnecessary, too.
1936 add_debug_info_for_div0(__ offset(), info);
1937 }
1938 __ z_dsgfr(R1, R2);
1939 }
1940
1941 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1942 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1943 assert(exceptionPC->as_register() == Z_EXC_PC, "should match");
1944
1945 // Exception object is not added to oop map by LinearScan
1946 // (LinearScan assumes that no oops are in fixed registers).
1947 info->add_register_oop(exceptionOop);
1948
1949 // Reuse the debug info from the safepoint poll for the throw op itself.
1950 __ get_PC(Z_EXC_PC);
1951 add_call_info(__ offset(), info); // for exception handler
1952 address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1953 : Runtime1::handle_exception_nofpu_id);
1954 emit_call_c(stub);
1955 }
1956
1957 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1958 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1959
1960 __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry);
1961 }
1962
1963 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1964 ciArrayKlass* default_type = op->expected_type();
1965 Register src = op->src()->as_register();
1966 Register dst = op->dst()->as_register();
1967 Register src_pos = op->src_pos()->as_register();
1968 Register dst_pos = op->dst_pos()->as_register();
1969 Register length = op->length()->as_register();
1970 Register tmp = op->tmp()->as_register();
1971
1972 CodeStub* stub = op->stub();
1973 int flags = op->flags();
1974 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1975 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1976
1977 // If we don't know anything, just go through the generic arraycopy.
1978 if (default_type == NULL) {
1979 address copyfunc_addr = StubRoutines::generic_arraycopy();
1980
1981 if (copyfunc_addr == NULL) {
1982 // Take a slow path for generic arraycopy.
1983 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
1984 __ bind(*stub->continuation());
1985 return;
1986 }
1987
1988 // Save outgoing arguments in callee saved registers (C convention) in case
1989 // a call to System.arraycopy is needed.
1990 Register callee_saved_src = Z_R10;
1991 Register callee_saved_src_pos = Z_R11;
1992 Register callee_saved_dst = Z_R12;
1993 Register callee_saved_dst_pos = Z_R13;
1994 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
1995
1996 __ lgr_if_needed(callee_saved_src, src);
1997 __ lgr_if_needed(callee_saved_src_pos, src_pos);
1998 __ lgr_if_needed(callee_saved_dst, dst);
1999 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
2000 __ lgr_if_needed(callee_saved_length, length);
2001
2002 // C function requires 64 bit values.
2003 __ z_lgfr(src_pos, src_pos);
2004 __ z_lgfr(dst_pos, dst_pos);
2005 __ z_lgfr(length, length);
2006
2007 // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint.
2008
2009 // The arguments are in the corresponding registers.
2010 assert(Z_ARG1 == src, "assumption");
2011 assert(Z_ARG2 == src_pos, "assumption");
2012 assert(Z_ARG3 == dst, "assumption");
2013 assert(Z_ARG4 == dst_pos, "assumption");
2014 assert(Z_ARG5 == length, "assumption");
2015 #ifndef PRODUCT
2016 if (PrintC1Statistics) {
2017 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt);
2018 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2019 }
2020 #endif
2021 emit_call_c(copyfunc_addr);
2022 CHECK_BAILOUT();
2023
2024 __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2025
2026 __ z_lgr(tmp, Z_RET);
2027 __ z_xilf(tmp, -1);
2028
2029 // Restore values from callee saved registers so they are where the stub
2030 // expects them.
2031 __ lgr_if_needed(src, callee_saved_src);
2032 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2033 __ lgr_if_needed(dst, callee_saved_dst);
2034 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2035 __ lgr_if_needed(length, callee_saved_length);
2036
2037 __ z_sr(length, tmp);
2038 __ z_ar(src_pos, tmp);
2039 __ z_ar(dst_pos, tmp);
2040 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2041
2042 __ bind(*stub->continuation());
2043 return;
2044 }
2045
2046 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2047
2048 int elem_size = type2aelembytes(basic_type);
2049 int shift_amount;
2050
2051 switch (elem_size) {
2052 case 1 :
2053 shift_amount = 0;
2054 break;
2055 case 2 :
2056 shift_amount = 1;
2057 break;
2058 case 4 :
2059 shift_amount = 2;
2060 break;
2061 case 8 :
2062 shift_amount = 3;
2063 break;
2064 default:
2065 shift_amount = -1;
2066 ShouldNotReachHere();
2067 }
2068
2069 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2070 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2071 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2072 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2073
2074 // Length and pos's are all sign extended at this point on 64bit.
2075
2076 // test for NULL
2077 if (flags & LIR_OpArrayCopy::src_null_check) {
2078 __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2079 }
2080 if (flags & LIR_OpArrayCopy::dst_null_check) {
2081 __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2082 }
2083
2084 // Check if negative.
2085 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2086 __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2087 }
2088 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2089 __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2090 }
2091
2092 // If the compiler was not able to prove that exact type of the source or the destination
2093 // of the arraycopy is an array type, check at runtime if the source or the destination is
2094 // an instance type.
2095 if (flags & LIR_OpArrayCopy::type_check) {
2096 assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions");
2097
2098 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2099 __ load_klass(tmp, dst);
2100 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2101 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2102 }
2103
2104 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2105 __ load_klass(tmp, src);
2106 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2107 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2108 }
2109 }
2110
2111 if (flags & LIR_OpArrayCopy::src_range_check) {
2112 __ z_la(tmp, Address(src_pos, length));
2113 __ z_cl(tmp, src_length_addr);
2114 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2115 }
2116 if (flags & LIR_OpArrayCopy::dst_range_check) {
2117 __ z_la(tmp, Address(dst_pos, length));
2118 __ z_cl(tmp, dst_length_addr);
2119 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2120 }
2121
2122 if (flags & LIR_OpArrayCopy::length_positive_check) {
2123 __ z_ltr(length, length);
2124 __ branch_optimized(Assembler::bcondNegative, *stub->entry());
2125 }
2126
2127 // Stubs require 64 bit values.
2128 __ z_lgfr(src_pos, src_pos); // int -> long
2129 __ z_lgfr(dst_pos, dst_pos); // int -> long
2130 __ z_lgfr(length, length); // int -> long
2131
2132 if (flags & LIR_OpArrayCopy::type_check) {
2133 // We don't know the array types are compatible.
2134 if (basic_type != T_OBJECT) {
2135 // Simple test for basic type arrays.
2136 if (UseCompressedClassPointers) {
2137 __ z_l(tmp, src_klass_addr);
2138 __ z_c(tmp, dst_klass_addr);
2139 } else {
2140 __ z_lg(tmp, src_klass_addr);
2141 __ z_cg(tmp, dst_klass_addr);
2142 }
2143 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2144 } else {
2145 // For object arrays, if src is a sub class of dst then we can
2146 // safely do the copy.
2147 NearLabel cont, slow;
2148 Register src_klass = Z_R1_scratch;
2149 Register dst_klass = Z_R10;
2150
2151 __ load_klass(src_klass, src);
2152 __ load_klass(dst_klass, dst);
2153
2154 __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, NULL);
2155
2156 store_parameter(src_klass, 0); // sub
2157 store_parameter(dst_klass, 1); // super
2158 emit_call_c(Runtime1::entry_for (Runtime1::slow_subtype_check_id));
2159 CHECK_BAILOUT2(cont, slow);
2160 // Sets condition code 0 for match (2 otherwise).
2161 __ branch_optimized(Assembler::bcondEqual, cont);
2162
2163 __ bind(slow);
2164
2165 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2166 if (copyfunc_addr != NULL) { // use stub if available
2167 // Src is not a sub class of dst so we have to do a
2168 // per-element check.
2169
2170 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2171 if ((flags & mask) != mask) {
2172 // Check that at least both of them object arrays.
2173 assert(flags & mask, "one of the two should be known to be an object array");
2174
2175 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2176 __ load_klass(tmp, src);
2177 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2178 __ load_klass(tmp, dst);
2179 }
2180 Address klass_lh_addr(tmp, Klass::layout_helper_offset());
2181 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2182 __ load_const_optimized(Z_R1_scratch, objArray_lh);
2183 __ z_c(Z_R1_scratch, klass_lh_addr);
2184 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2185 }
2186
2187 // Save outgoing arguments in callee saved registers (C convention) in case
2188 // a call to System.arraycopy is needed.
2189 Register callee_saved_src = Z_R10;
2190 Register callee_saved_src_pos = Z_R11;
2191 Register callee_saved_dst = Z_R12;
2192 Register callee_saved_dst_pos = Z_R13;
2193 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
2194
2195 __ lgr_if_needed(callee_saved_src, src);
2196 __ lgr_if_needed(callee_saved_src_pos, src_pos);
2197 __ lgr_if_needed(callee_saved_dst, dst);
2198 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
2199 __ lgr_if_needed(callee_saved_length, length);
2200
2201 __ z_llgfr(length, length); // Higher 32bits must be null.
2202
2203 __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset
2204 __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset
2205
2206 __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type)));
2207 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2208 __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type)));
2209 assert_different_registers(Z_ARG2, dst, length);
2210
2211 __ z_lgr(Z_ARG3, length);
2212 assert_different_registers(Z_ARG3, dst);
2213
2214 __ load_klass(Z_ARG5, dst);
2215 __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset()));
2216 __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset()));
2217 emit_call_c(copyfunc_addr);
2218 CHECK_BAILOUT2(cont, slow);
2219
2220 #ifndef PRODUCT
2221 if (PrintC1Statistics) {
2222 NearLabel failed;
2223 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed);
2224 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt);
2225 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2226 __ bind(failed);
2227 }
2228 #endif
2229
2230 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2231
2232 #ifndef PRODUCT
2233 if (PrintC1Statistics) {
2234 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt);
2235 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2236 }
2237 #endif
2238
2239 __ z_lgr(tmp, Z_RET);
2240 __ z_xilf(tmp, -1);
2241
2242 // Restore previously spilled arguments
2243 __ lgr_if_needed(src, callee_saved_src);
2244 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2245 __ lgr_if_needed(dst, callee_saved_dst);
2246 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2247 __ lgr_if_needed(length, callee_saved_length);
2248
2249 __ z_sr(length, tmp);
2250 __ z_ar(src_pos, tmp);
2251 __ z_ar(dst_pos, tmp);
2252 }
2253
2254 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2255
2256 __ bind(cont);
2257 }
2258 }
2259
2260 #ifdef ASSERT
2261 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2262 // Sanity check the known type with the incoming class. For the
2263 // primitive case the types must match exactly with src.klass and
2264 // dst.klass each exactly matching the default type. For the
2265 // object array case, if no type check is needed then either the
2266 // dst type is exactly the expected type and the src type is a
2267 // subtype which we can't check or src is the same array as dst
2268 // but not necessarily exactly of type default_type.
2269 NearLabel known_ok, halt;
2270 metadata2reg(default_type->constant_encoding(), tmp);
2271 if (UseCompressedClassPointers) {
2272 __ encode_klass_not_null(tmp);
2273 }
2274
2275 if (basic_type != T_OBJECT) {
2276 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); }
2277 else { __ z_cg(tmp, dst_klass_addr); }
2278 __ branch_optimized(Assembler::bcondNotEqual, halt);
2279 if (UseCompressedClassPointers) { __ z_c (tmp, src_klass_addr); }
2280 else { __ z_cg(tmp, src_klass_addr); }
2281 __ branch_optimized(Assembler::bcondEqual, known_ok);
2282 } else {
2283 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); }
2284 else { __ z_cg(tmp, dst_klass_addr); }
2285 __ branch_optimized(Assembler::bcondEqual, known_ok);
2286 __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok);
2287 }
2288 __ bind(halt);
2289 __ stop("incorrect type information in arraycopy");
2290 __ bind(known_ok);
2291 }
2292 #endif
2293
2294 #ifndef PRODUCT
2295 if (PrintC1Statistics) {
2296 __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type));
2297 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2298 }
2299 #endif
2300
2301 __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset
2302 __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset
2303
2304 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2305 __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type)));
2306 assert_different_registers(Z_ARG2, length);
2307 __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type)));
2308 __ lgr_if_needed(Z_ARG3, length);
2309
2310 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2311 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2312 const char *name;
2313 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2314 __ call_VM_leaf(entry);
2315
2316 __ bind(*stub->continuation());
2317 }
2318
2319 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2320 if (dest->is_single_cpu()) {
2321 if (left->type() == T_OBJECT) {
2322 switch (code) {
2323 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2324 case lir_shr: __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2325 case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2326 default: ShouldNotReachHere();
2327 }
2328 } else {
2329 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2330 Register masked_count = Z_R1_scratch;
2331 __ z_lr(masked_count, count->as_register());
2332 __ z_nill(masked_count, 31);
2333 switch (code) {
2334 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break;
2335 case lir_shr: __ z_sra (dest->as_register(), 0, masked_count); break;
2336 case lir_ushr: __ z_srl (dest->as_register(), 0, masked_count); break;
2337 default: ShouldNotReachHere();
2338 }
2339 }
2340 } else {
2341 switch (code) {
2342 case lir_shl: __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2343 case lir_shr: __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2344 case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2345 default: ShouldNotReachHere();
2346 }
2347 }
2348 }
2349
2350 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2351 if (left->type() == T_OBJECT) {
2352 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2353 Register l = left->as_register();
2354 Register d = dest->as_register_lo();
2355 switch (code) {
2356 case lir_shl: __ z_sllg (d, l, count); break;
2357 case lir_shr: __ z_srag (d, l, count); break;
2358 case lir_ushr: __ z_srlg (d, l, count); break;
2359 default: ShouldNotReachHere();
2360 }
2361 return;
2362 }
2363 if (dest->is_single_cpu()) {
2364 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2365 count = count & 0x1F; // Java spec
2366 switch (code) {
2367 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), count); break;
2368 case lir_shr: __ z_sra (dest->as_register(), count); break;
2369 case lir_ushr: __ z_srl (dest->as_register(), count); break;
2370 default: ShouldNotReachHere();
2371 }
2372 } else if (dest->is_double_cpu()) {
2373 count = count & 63; // Java spec
2374 Register l = left->as_pointer_register();
2375 Register d = dest->as_pointer_register();
2376 switch (code) {
2377 case lir_shl: __ z_sllg (d, l, count); break;
2378 case lir_shr: __ z_srag (d, l, count); break;
2379 case lir_ushr: __ z_srlg (d, l, count); break;
2380 default: ShouldNotReachHere();
2381 }
2382 } else {
2383 ShouldNotReachHere();
2384 }
2385 }
2386
2387 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2388 if (op->init_check()) {
2389 // Make sure klass is initialized & doesn't have finalizer.
2390 const int state_offset = in_bytes(InstanceKlass::init_state_offset());
2391 Register iklass = op->klass()->as_register();
2392 add_debug_info_for_null_check_here(op->stub()->info());
2393 if (Immediate::is_uimm12(state_offset)) {
2394 __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized);
2395 } else {
2396 __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized);
2397 }
2398 __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far.
2399 }
2400 __ allocate_object(op->obj()->as_register(),
2401 op->tmp1()->as_register(),
2402 op->tmp2()->as_register(),
2403 op->header_size(),
2404 op->object_size(),
2405 op->klass()->as_register(),
2406 *op->stub()->entry());
2407 __ bind(*op->stub()->continuation());
2408 __ verify_oop(op->obj()->as_register());
2409 }
2410
2411 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2412 Register len = op->len()->as_register();
2413 __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
2414
2415 if (UseSlowPath ||
2416 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2417 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2418 __ z_brul(*op->stub()->entry());
2419 } else {
2420 __ allocate_array(op->obj()->as_register(),
2421 op->len()->as_register(),
2422 op->tmp1()->as_register(),
2423 op->tmp2()->as_register(),
2424 arrayOopDesc::header_size(op->type()),
2425 type2aelembytes(op->type()),
2426 op->klass()->as_register(),
2427 *op->stub()->entry());
2428 }
2429 __ bind(*op->stub()->continuation());
2430 }
2431
2432 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data,
2433 Register recv, Register tmp1, Label* update_done) {
2434 uint i;
2435 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2436 Label next_test;
2437 // See if the receiver is receiver[n].
2438 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2439 __ z_cg(recv, receiver_addr);
2440 __ z_brne(next_test);
2441 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
2442 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2443 __ branch_optimized(Assembler::bcondAlways, *update_done);
2444 __ bind(next_test);
2445 }
2446
2447 // Didn't find receiver; find next empty slot and fill it in.
2448 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2449 Label next_test;
2450 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2451 __ z_ltg(Z_R0_scratch, recv_addr);
2452 __ z_brne(next_test);
2453 __ z_stg(recv, recv_addr);
2454 __ load_const_optimized(tmp1, DataLayout::counter_increment);
2455 __ z_stg(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)), mdo);
2456 __ branch_optimized(Assembler::bcondAlways, *update_done);
2457 __ bind(next_test);
2458 }
2459 }
2460
2461 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2462 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2463 Unimplemented();
2464 }
2465
2466 void LIR_Assembler::store_parameter(Register r, int param_num) {
2467 assert(param_num >= 0, "invalid num");
2468 int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame;
2469 assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2470 __ z_stg(r, offset_in_bytes, Z_SP);
2471 }
2472
2473 void LIR_Assembler::store_parameter(jint c, int param_num) {
2474 assert(param_num >= 0, "invalid num");
2475 int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame;
2476 assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2477 __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true);
2478 }
2479
2480 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2481 // We always need a stub for the failure case.
2482 CodeStub* stub = op->stub();
2483 Register obj = op->object()->as_register();
2484 Register k_RInfo = op->tmp1()->as_register();
2485 Register klass_RInfo = op->tmp2()->as_register();
2486 Register dst = op->result_opr()->as_register();
2487 Register Rtmp1 = Z_R1_scratch;
2488 ciKlass* k = op->klass();
2489
2490 assert(!op->tmp3()->is_valid(), "tmp3's not needed");
2491
2492 // Check if it needs to be profiled.
2493 ciMethodData* md = NULL;
2494 ciProfileData* data = NULL;
2495
2496 if (op->should_profile()) {
2497 ciMethod* method = op->profiled_method();
2498 assert(method != NULL, "Should have method");
2499 int bci = op->profiled_bci();
2500 md = method->method_data_or_null();
2501 assert(md != NULL, "Sanity");
2502 data = md->bci_to_data(bci);
2503 assert(data != NULL, "need data for type check");
2504 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2505 }
2506
2507 // Temp operands do not overlap with inputs, if this is their last
2508 // use (end of range is exclusive), so a register conflict is possible.
2509 if (obj == k_RInfo) {
2510 k_RInfo = dst;
2511 } else if (obj == klass_RInfo) {
2512 klass_RInfo = dst;
2513 }
2514 assert_different_registers(obj, k_RInfo, klass_RInfo);
2515
2516 if (op->should_profile()) {
2517 NearLabel not_null;
2518 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2519 // Object is null; update MDO and exit.
2520 Register mdo = klass_RInfo;
2521 metadata2reg(md->constant_encoding(), mdo);
2522 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2523 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2524 __ or2mem_8(data_addr, header_bits);
2525 __ branch_optimized(Assembler::bcondAlways, *obj_is_null);
2526 __ bind(not_null);
2527 } else {
2528 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null);
2529 }
2530
2531 NearLabel profile_cast_failure, profile_cast_success;
2532 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2533 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2534
2535 // Patching may screw with our temporaries on sparc,
2536 // so let's do it before loading the class.
2537 if (k->is_loaded()) {
2538 metadata2reg(k->constant_encoding(), k_RInfo);
2539 } else {
2540 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2541 }
2542 assert(obj != k_RInfo, "must be different");
2543
2544 __ verify_oop(obj);
2545
2546 // Get object class.
2547 // Not a safepoint as obj null check happens earlier.
2548 if (op->fast_check()) {
2549 if (UseCompressedClassPointers) {
2550 __ load_klass(klass_RInfo, obj);
2551 __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target);
2552 } else {
2553 __ z_cg(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
2554 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2555 }
2556 // Successful cast, fall through to profile or jump.
2557 } else {
2558 bool need_slow_path = !k->is_loaded() ||
2559 ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset()));
2560 intptr_t super_check_offset = k->is_loaded() ? k->super_check_offset() : -1L;
2561 __ load_klass(klass_RInfo, obj);
2562 // Perform the fast part of the checking logic.
2563 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1,
2564 (need_slow_path ? success_target : NULL),
2565 failure_target, NULL,
2566 RegisterOrConstant(super_check_offset));
2567 if (need_slow_path) {
2568 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2569 address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id);
2570 store_parameter(klass_RInfo, 0); // sub
2571 store_parameter(k_RInfo, 1); // super
2572 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2573 CHECK_BAILOUT2(profile_cast_failure, profile_cast_success);
2574 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2575 // Fall through to success case.
2576 }
2577 }
2578
2579 if (op->should_profile()) {
2580 Register mdo = klass_RInfo, recv = k_RInfo;
2581 assert_different_registers(obj, mdo, recv);
2582 __ bind(profile_cast_success);
2583 metadata2reg(md->constant_encoding(), mdo);
2584 __ load_klass(recv, obj);
2585 type_profile_helper(mdo, md, data, recv, Rtmp1, success);
2586 __ branch_optimized(Assembler::bcondAlways, *success);
2587
2588 __ bind(profile_cast_failure);
2589 metadata2reg(md->constant_encoding(), mdo);
2590 __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1);
2591 __ branch_optimized(Assembler::bcondAlways, *failure);
2592 } else {
2593 __ branch_optimized(Assembler::bcondAlways, *success);
2594 }
2595 }
2596
2597 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2598 LIR_Code code = op->code();
2599 if (code == lir_store_check) {
2600 Register value = op->object()->as_register();
2601 Register array = op->array()->as_register();
2602 Register k_RInfo = op->tmp1()->as_register();
2603 Register klass_RInfo = op->tmp2()->as_register();
2604 Register Rtmp1 = Z_R1_scratch;
2605
2606 CodeStub* stub = op->stub();
2607
2608 // Check if it needs to be profiled.
2609 ciMethodData* md = NULL;
2610 ciProfileData* data = NULL;
2611
2612 assert_different_registers(value, k_RInfo, klass_RInfo);
2613
2614 if (op->should_profile()) {
2615 ciMethod* method = op->profiled_method();
2616 assert(method != NULL, "Should have method");
2617 int bci = op->profiled_bci();
2618 md = method->method_data_or_null();
2619 assert(md != NULL, "Sanity");
2620 data = md->bci_to_data(bci);
2621 assert(data != NULL, "need data for type check");
2622 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2623 }
2624 NearLabel profile_cast_success, profile_cast_failure, done;
2625 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2626 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2627
2628 if (op->should_profile()) {
2629 NearLabel not_null;
2630 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2631 // Object is null; update MDO and exit.
2632 Register mdo = klass_RInfo;
2633 metadata2reg(md->constant_encoding(), mdo);
2634 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2635 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2636 __ or2mem_8(data_addr, header_bits);
2637 __ branch_optimized(Assembler::bcondAlways, done);
2638 __ bind(not_null);
2639 } else {
2640 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done);
2641 }
2642
2643 add_debug_info_for_null_check_here(op->info_for_exception());
2644 __ load_klass(k_RInfo, array);
2645 __ load_klass(klass_RInfo, value);
2646
2647 // Get instance klass (it's already uncompressed).
2648 __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
2649 // Perform the fast part of the checking logic.
2650 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
2651 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2652 address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id);
2653 store_parameter(klass_RInfo, 0); // sub
2654 store_parameter(k_RInfo, 1); // super
2655 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2656 CHECK_BAILOUT3(profile_cast_success, profile_cast_failure, done);
2657 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2658 // Fall through to success case.
2659
2660 if (op->should_profile()) {
2661 Register mdo = klass_RInfo, recv = k_RInfo;
2662 assert_different_registers(value, mdo, recv);
2663 __ bind(profile_cast_success);
2664 metadata2reg(md->constant_encoding(), mdo);
2665 __ load_klass(recv, value);
2666 type_profile_helper(mdo, md, data, recv, Rtmp1, &done);
2667 __ branch_optimized(Assembler::bcondAlways, done);
2668
2669 __ bind(profile_cast_failure);
2670 metadata2reg(md->constant_encoding(), mdo);
2671 __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1);
2672 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2673 }
2674
2675 __ bind(done);
2676 } else {
2677 if (code == lir_checkcast) {
2678 Register obj = op->object()->as_register();
2679 Register dst = op->result_opr()->as_register();
2680 NearLabel success;
2681 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2682 __ bind(success);
2683 __ lgr_if_needed(dst, obj);
2684 } else {
2685 if (code == lir_instanceof) {
2686 Register obj = op->object()->as_register();
2687 Register dst = op->result_opr()->as_register();
2688 NearLabel success, failure, done;
2689 emit_typecheck_helper(op, &success, &failure, &failure);
2690 __ bind(failure);
2691 __ clear_reg(dst);
2692 __ branch_optimized(Assembler::bcondAlways, done);
2693 __ bind(success);
2694 __ load_const_optimized(dst, 1);
2695 __ bind(done);
2696 } else {
2697 ShouldNotReachHere();
2698 }
2699 }
2700 }
2701 }
2702
2703 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2704 Register addr = op->addr()->as_pointer_register();
2705 Register t1_cmp = Z_R1_scratch;
2706 if (op->code() == lir_cas_long) {
2707 assert(VM_Version::supports_cx8(), "wrong machine");
2708 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2709 Register new_value_lo = op->new_value()->as_register_lo();
2710 __ z_lgr(t1_cmp, cmp_value_lo);
2711 // Perform the compare and swap operation.
2712 __ z_csg(t1_cmp, new_value_lo, 0, addr);
2713 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2714 Register cmp_value = op->cmp_value()->as_register();
2715 Register new_value = op->new_value()->as_register();
2716 if (op->code() == lir_cas_obj) {
2717 if (UseCompressedOops) {
2718 t1_cmp = op->tmp1()->as_register();
2719 Register t2_new = op->tmp2()->as_register();
2720 assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new);
2721 __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/);
2722 __ oop_encoder(t2_new, new_value, true /*maybe null*/);
2723 __ z_cs(t1_cmp, t2_new, 0, addr);
2724 } else {
2725 __ z_lgr(t1_cmp, cmp_value);
2726 __ z_csg(t1_cmp, new_value, 0, addr);
2727 }
2728 } else {
2729 __ z_lr(t1_cmp, cmp_value);
2730 __ z_cs(t1_cmp, new_value, 0, addr);
2731 }
2732 } else {
2733 ShouldNotReachHere(); // new lir_cas_??
2734 }
2735 }
2736
2737 void LIR_Assembler::set_24bit_FPU() {
2738 ShouldNotCallThis(); // x86 only
2739 }
2740
2741 void LIR_Assembler::reset_FPU() {
2742 ShouldNotCallThis(); // x86 only
2743 }
2744
2745 void LIR_Assembler::breakpoint() {
2746 Unimplemented();
2747 // __ breakpoint_trap();
2748 }
2749
2750 void LIR_Assembler::push(LIR_Opr opr) {
2751 ShouldNotCallThis(); // unused
2752 }
2753
2754 void LIR_Assembler::pop(LIR_Opr opr) {
2755 ShouldNotCallThis(); // unused
2756 }
2757
2758 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2759 Address addr = frame_map()->address_for_monitor_lock(monitor_no);
2760 __ add2reg(dst_opr->as_register(), addr.disp(), addr.base());
2761 }
2762
2763 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2764 Register obj = op->obj_opr()->as_register(); // May not be an oop.
2765 Register hdr = op->hdr_opr()->as_register();
2766 Register lock = op->lock_opr()->as_register();
2767 if (!UseFastLocking) {
2768 __ branch_optimized(Assembler::bcondAlways, *op->stub()->entry());
2769 } else if (op->code() == lir_lock) {
2770 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2771 // Add debug info for NullPointerException only if one is possible.
2772 if (op->info() != NULL) {
2773 add_debug_info_for_null_check_here(op->info());
2774 }
2775 __ lock_object(hdr, obj, lock, *op->stub()->entry());
2776 // done
2777 } else if (op->code() == lir_unlock) {
2778 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2779 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2780 } else {
2781 ShouldNotReachHere();
2782 }
2783 __ bind(*op->stub()->continuation());
2784 }
2785
2786 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2787 ciMethod* method = op->profiled_method();
2788 int bci = op->profiled_bci();
2789 ciMethod* callee = op->profiled_callee();
2790
2791 // Update counter for all call types.
2792 ciMethodData* md = method->method_data_or_null();
2793 assert(md != NULL, "Sanity");
2794 ciProfileData* data = md->bci_to_data(bci);
2795 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2796 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2797 Register mdo = op->mdo()->as_register();
2798 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2799 Register tmp1 = op->tmp1()->as_register_lo();
2800 metadata2reg(md->constant_encoding(), mdo);
2801
2802 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2803 // Perform additional virtual call profiling for invokevirtual and
2804 // invokeinterface bytecodes
2805 if (op->should_profile_receiver_type()) {
2806 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2807 Register recv = op->recv()->as_register();
2808 assert_different_registers(mdo, tmp1, recv);
2809 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2810 ciKlass* known_klass = op->known_holder();
2811 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2812 // We know the type that will be seen at this call site; we can
2813 // statically update the MethodData* rather than needing to do
2814 // dynamic tests on the receiver type.
2815
2816 // NOTE: we should probably put a lock around this search to
2817 // avoid collisions by concurrent compilations.
2818 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2819 uint i;
2820 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2821 ciKlass* receiver = vc_data->receiver(i);
2822 if (known_klass->equals(receiver)) {
2823 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2824 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2825 return;
2826 }
2827 }
2828
2829 // Receiver type not found in profile data. Select an empty slot.
2830
2831 // Note that this is less efficient than it should be because it
2832 // always does a write to the receiver part of the
2833 // VirtualCallData rather than just the first time.
2834 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2835 ciKlass* receiver = vc_data->receiver(i);
2836 if (receiver == NULL) {
2837 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2838 metadata2reg(known_klass->constant_encoding(), tmp1);
2839 __ z_stg(tmp1, recv_addr);
2840 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2841 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2842 return;
2843 }
2844 }
2845 } else {
2846 __ load_klass(recv, recv);
2847 NearLabel update_done;
2848 type_profile_helper(mdo, md, data, recv, tmp1, &update_done);
2849 // Receiver did not match any saved receiver and there is no empty row for it.
2850 // Increment total counter to indicate polymorphic case.
2851 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2852 __ bind(update_done);
2853 }
2854 } else {
2855 // static call
2856 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2857 }
2858 }
2859
2860 void LIR_Assembler::align_backward_branch_target() {
2861 __ align(OptoLoopAlignment);
2862 }
2863
2864 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2865 ShouldNotCallThis(); // There are no delay slots on ZARCH_64.
2866 }
2867
2868 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2869 // tmp must be unused
2870 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2871 assert(left->is_register(), "can only handle registers");
2872
2873 if (left->is_single_cpu()) {
2874 __ z_lcr(dest->as_register(), left->as_register());
2875 } else if (left->is_single_fpu()) {
2876 __ z_lcebr(dest->as_float_reg(), left->as_float_reg());
2877 } else if (left->is_double_fpu()) {
2878 __ z_lcdbr(dest->as_double_reg(), left->as_double_reg());
2879 } else {
2880 assert(left->is_double_cpu(), "Must be a long");
2881 __ z_lcgr(dest->as_register_lo(), left->as_register_lo());
2882 }
2883 }
2884
2885 void LIR_Assembler::fxch(int i) {
2886 ShouldNotCallThis(); // x86 only
2887 }
2888
2889 void LIR_Assembler::fld(int i) {
2890 ShouldNotCallThis(); // x86 only
2891 }
2892
2893 void LIR_Assembler::ffree(int i) {
2894 ShouldNotCallThis(); // x86 only
2895 }
2896
2897 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2898 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2899 assert(!tmp->is_valid(), "don't need temporary");
2900 emit_call_c(dest);
2901 CHECK_BAILOUT();
2902 if (info != NULL) {
2903 add_call_info_here(info);
2904 }
2905 }
2906
2907 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2908 ShouldNotCallThis(); // not needed on ZARCH_64
2909 }
2910
2911 void LIR_Assembler::membar() {
2912 __ z_fence();
2913 }
2914
2915 void LIR_Assembler::membar_acquire() {
2916 __ z_acquire();
2917 }
2918
2919 void LIR_Assembler::membar_release() {
2920 __ z_release();
2921 }
2922
2923 void LIR_Assembler::membar_loadload() {
2924 __ z_acquire();
2925 }
2926
2927 void LIR_Assembler::membar_storestore() {
2928 __ z_release();
2929 }
2930
2931 void LIR_Assembler::membar_loadstore() {
2932 __ z_acquire();
2933 }
2934
2935 void LIR_Assembler::membar_storeload() {
2936 __ z_fence();
2937 }
2938
2939 void LIR_Assembler::on_spin_wait() {
2940 Unimplemented();
2941 }
2942
2943 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2944 assert(patch_code == lir_patch_none, "Patch code not supported");
2945 LIR_Address* addr = addr_opr->as_address_ptr();
2946 assert(addr->scale() == LIR_Address::times_1, "scaling unsupported");
2947 __ load_address(dest->as_pointer_register(), as_Address(addr));
2948 }
2949
2950 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2951 ShouldNotCallThis(); // unused
2952 }
2953
2954 #ifdef ASSERT
2955 // Emit run-time assertion.
2956 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2957 Unimplemented();
2958 }
2959 #endif
2960
2961 void LIR_Assembler::peephole(LIR_List*) {
2962 // Do nothing for now.
2963 }
2964
2965 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2966 assert(code == lir_xadd, "lir_xchg not supported");
2967 Address src_addr = as_Address(src->as_address_ptr());
2968 Register base = src_addr.base();
2969 intptr_t disp = src_addr.disp();
2970 if (src_addr.index()->is_valid()) {
2971 // LAA and LAAG do not support index register.
2972 __ load_address(Z_R1_scratch, src_addr);
2973 base = Z_R1_scratch;
2974 disp = 0;
2975 }
2976 if (data->type() == T_INT) {
2977 __ z_laa(dest->as_register(), data->as_register(), disp, base);
2978 } else if (data->type() == T_LONG) {
2979 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
2980 __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base);
2981 } else {
2982 ShouldNotReachHere();
2983 }
2984 }
2985
2986 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2987 Register obj = op->obj()->as_register();
2988 Register tmp1 = op->tmp()->as_pointer_register();
2989 Register tmp2 = Z_R1_scratch;
2990 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2991 ciKlass* exact_klass = op->exact_klass();
2992 intptr_t current_klass = op->current_klass();
2993 bool not_null = op->not_null();
2994 bool no_conflict = op->no_conflict();
2995
2996 Label update, next, none, null_seen, init_klass;
2997
2998 bool do_null = !not_null;
2999 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3000 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3001
3002 assert(do_null || do_update, "why are we here?");
3003 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3004
3005 __ verify_oop(obj);
3006
3007 if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) {
3008 __ z_ltgr(tmp1, obj);
3009 }
3010 if (do_null) {
3011 __ z_brnz(update);
3012 if (!TypeEntries::was_null_seen(current_klass)) {
3013 __ z_lg(tmp1, mdo_addr);
3014 __ z_oill(tmp1, TypeEntries::null_seen);
3015 __ z_stg(tmp1, mdo_addr);
3016 }
3017 if (do_update) {
3018 __ z_bru(next);
3019 }
3020 } else {
3021 __ asm_assert_ne("unexpect null obj", __LINE__);
3022 }
3023
3024 __ bind(update);
3025
3026 if (do_update) {
3027 #ifdef ASSERT
3028 if (exact_klass != NULL) {
3029 __ load_klass(tmp1, tmp1);
3030 metadata2reg(exact_klass->constant_encoding(), tmp2);
3031 __ z_cgr(tmp1, tmp2);
3032 __ asm_assert_eq("exact klass and actual klass differ", __LINE__);
3033 }
3034 #endif
3035
3036 Label do_update;
3037 __ z_lg(tmp2, mdo_addr);
3038
3039 if (!no_conflict) {
3040 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3041 if (exact_klass != NULL) {
3042 metadata2reg(exact_klass->constant_encoding(), tmp1);
3043 } else {
3044 __ load_klass(tmp1, tmp1);
3045 }
3046
3047 // Klass seen before: nothing to do (regardless of unknown bit).
3048 __ z_lgr(Z_R0_scratch, tmp2);
3049 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
3050 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
3051 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3052
3053 // Already unknown: Nothing to do anymore.
3054 __ z_tmll(tmp2, TypeEntries::type_unknown);
3055 __ z_brc(Assembler::bcondAllOne, next);
3056
3057 if (TypeEntries::is_type_none(current_klass)) {
3058 __ z_lgr(Z_R0_scratch, tmp2);
3059 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3060 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3061 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass);
3062 }
3063 } else {
3064 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3065 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3066
3067 // Already unknown: Nothing to do anymore.
3068 __ z_tmll(tmp2, TypeEntries::type_unknown);
3069 __ z_brc(Assembler::bcondAllOne, next);
3070 }
3071
3072 // Different than before. Cannot keep accurate profile.
3073 __ z_oill(tmp2, TypeEntries::type_unknown);
3074 __ z_bru(do_update);
3075 } else {
3076 // There's a single possible klass at this profile point.
3077 assert(exact_klass != NULL, "should be");
3078 if (TypeEntries::is_type_none(current_klass)) {
3079 metadata2reg(exact_klass->constant_encoding(), tmp1);
3080 __ z_lgr(Z_R0_scratch, tmp2);
3081 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
3082 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
3083 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3084 #ifdef ASSERT
3085 {
3086 Label ok;
3087 __ z_lgr(Z_R0_scratch, tmp2);
3088 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3089 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3090 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok);
3091 __ stop("unexpected profiling mismatch");
3092 __ bind(ok);
3093 }
3094 #endif
3095
3096 } else {
3097 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3098 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3099
3100 // Already unknown: Nothing to do anymore.
3101 __ z_tmll(tmp2, TypeEntries::type_unknown);
3102 __ z_brc(Assembler::bcondAllOne, next);
3103 __ z_oill(tmp2, TypeEntries::type_unknown);
3104 __ z_bru(do_update);
3105 }
3106 }
3107
3108 __ bind(init_klass);
3109 // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3110 __ z_ogr(tmp2, tmp1);
3111
3112 __ bind(do_update);
3113 __ z_stg(tmp2, mdo_addr);
3114
3115 __ bind(next);
3116 }
3117 }
3118
3119 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3120 assert(op->crc()->is_single_cpu(), "crc must be register");
3121 assert(op->val()->is_single_cpu(), "byte value must be register");
3122 assert(op->result_opr()->is_single_cpu(), "result must be register");
3123 Register crc = op->crc()->as_register();
3124 Register val = op->val()->as_register();
3125 Register res = op->result_opr()->as_register();
3126
3127 assert_different_registers(val, crc, res);
3128
3129 __ load_const_optimized(res, StubRoutines::crc_table_addr());
3130 __ kernel_crc32_singleByteReg(crc, val, res, true);
3131 __ z_lgfr(res, crc);
3132 }
3133
3134 #undef __