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src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp
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rev 56376 : 8231448: s390 and ppc - replace JVM type comparisons to T_OBJECT and T_ARRAY with call to is_reference_type
*** 970,979 ****
--- 970,980 ----
__ z_llgf(dest->as_register(), disp_value, disp_reg, src);
__ oop_decoder(dest->as_register(), dest->as_register(), true);
} else {
__ z_lg(dest->as_register(), disp_value, disp_reg, src);
}
+ __ verify_oop(dest->as_register());
break;
}
case T_FLOAT:
if (short_disp) {
__ z_le(dest->as_float_reg(), disp_value, disp_reg, src);
*** 989,1001 ****
}
break;
case T_LONG : __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break;
default : ShouldNotReachHere();
}
- if (type == T_ARRAY || type == T_OBJECT) {
- __ verify_oop(dest->as_register());
- }
if (patch != NULL) {
patching_epilog(patch, patch_code, src, info);
}
if (info != NULL) add_debug_info_for_null_check(offset, info);
--- 990,999 ----
*** 1004,1014 ****
void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
assert(src->is_stack(), "should not call otherwise");
assert(dest->is_register(), "should not call otherwise");
if (dest->is_single_cpu()) {
! if (type == T_ARRAY || type == T_OBJECT) {
__ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
__ verify_oop(dest->as_register());
} else if (type == T_METADATA) {
__ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
} else {
--- 1002,1012 ----
void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
assert(src->is_stack(), "should not call otherwise");
assert(dest->is_register(), "should not call otherwise");
if (dest->is_single_cpu()) {
! if (is_reference_type(type)) {
__ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
__ verify_oop(dest->as_register());
} else if (type == T_METADATA) {
__ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
} else {
*** 1032,1042 ****
assert(src->is_register(), "should not call otherwise");
assert(dest->is_stack(), "should not call otherwise");
if (src->is_single_cpu()) {
const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
! if (type == T_OBJECT || type == T_ARRAY) {
__ verify_oop(src->as_register());
__ reg2mem_opt(src->as_register(), dst, true);
} else if (type == T_METADATA) {
__ reg2mem_opt(src->as_register(), dst, true);
} else {
--- 1030,1040 ----
assert(src->is_register(), "should not call otherwise");
assert(dest->is_stack(), "should not call otherwise");
if (src->is_single_cpu()) {
const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
! if (is_reference_type(type)) {
__ verify_oop(src->as_register());
__ reg2mem_opt(src->as_register(), dst, true);
} else if (type == T_METADATA) {
__ reg2mem_opt(src->as_register(), dst, true);
} else {
*** 1078,1088 ****
__ z_lgr(to_reg->as_register(), from_reg->as_register());
}
} else {
ShouldNotReachHere();
}
! if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
__ verify_oop(to_reg->as_register());
}
}
void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
--- 1076,1086 ----
__ z_lgr(to_reg->as_register(), from_reg->as_register());
}
} else {
ShouldNotReachHere();
}
! if (is_reference_type(to_reg->type())) {
__ verify_oop(to_reg->as_register());
}
}
void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
*** 1129,1139 ****
disp_reg = addr->index()->as_pointer_register();
}
assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
! if (type == T_ARRAY || type == T_OBJECT) {
__ verify_oop(from->as_register());
}
bool short_disp = Immediate::is_uimm12(disp_value);
--- 1127,1137 ----
disp_reg = addr->index()->as_pointer_register();
}
assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
! if (is_reference_type(type)) {
__ verify_oop(from->as_register());
}
bool short_disp = Immediate::is_uimm12(disp_value);
*** 1292,1314 ****
bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
if (opr1->is_single_cpu()) {
Register reg1 = opr1->as_register();
if (opr2->is_single_cpu()) {
// cpu register - cpu register
! if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
__ z_clgr(reg1, opr2->as_register());
} else {
! assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
if (unsigned_comp) {
__ z_clr(reg1, opr2->as_register());
} else {
__ z_cr(reg1, opr2->as_register());
}
}
} else if (opr2->is_stack()) {
// cpu register - stack
! if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
__ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
} else {
if (unsigned_comp) {
__ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
} else {
--- 1290,1312 ----
bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
if (opr1->is_single_cpu()) {
Register reg1 = opr1->as_register();
if (opr2->is_single_cpu()) {
// cpu register - cpu register
! if (is_reference_type(opr1->type())) {
__ z_clgr(reg1, opr2->as_register());
} else {
! assert(! is_reference_type(opr2->type()), "cmp int, oop?");
if (unsigned_comp) {
__ z_clr(reg1, opr2->as_register());
} else {
__ z_cr(reg1, opr2->as_register());
}
}
} else if (opr2->is_stack()) {
// cpu register - stack
! if (is_reference_type(opr1->type())) {
__ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
} else {
if (unsigned_comp) {
__ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
} else {
*** 1322,1332 ****
if (unsigned_comp) {
__ z_clfi(reg1, c->as_jint());
} else {
__ z_cfi(reg1, c->as_jint());
}
! } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
// In 64bit oops are single register.
jobject o = c->as_jobject();
if (o == NULL) {
__ z_ltgr(reg1, reg1);
} else {
--- 1320,1330 ----
if (unsigned_comp) {
__ z_clfi(reg1, c->as_jint());
} else {
__ z_cfi(reg1, c->as_jint());
}
! } else if (is_reference_type(c->type())) {
// In 64bit oops are single register.
jobject o = c->as_jobject();
if (o == NULL) {
__ z_ltgr(reg1, reg1);
} else {
*** 1765,1775 ****
break;
default: ShouldNotReachHere();
}
} else {
Register r_lo;
! if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
r_lo = right->as_register();
} else {
r_lo = right->as_register_lo();
}
switch (code) {
--- 1763,1773 ----
break;
default: ShouldNotReachHere();
}
} else {
Register r_lo;
! if (is_reference_type(right->type())) {
r_lo = right->as_register();
} else {
r_lo = right->as_register_lo();
}
switch (code) {
*** 2411,2422 ****
void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
Register len = op->len()->as_register();
__ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
if (UseSlowPath ||
! (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
! (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
__ z_brul(*op->stub()->entry());
} else {
__ allocate_array(op->obj()->as_register(),
op->len()->as_register(),
op->tmp1()->as_register(),
--- 2409,2420 ----
void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
Register len = op->len()->as_register();
__ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
if (UseSlowPath ||
! (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
! (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
__ z_brul(*op->stub()->entry());
} else {
__ allocate_array(op->obj()->as_register(),
op->len()->as_register(),
op->tmp1()->as_register(),
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