1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2017, SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "asm/macroAssembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "memory/resourceArea.hpp" 31 #include "prims/jvm.h" 32 #include "runtime/java.hpp" 33 #include "runtime/os.hpp" 34 #include "runtime/stubCodeGenerator.hpp" 35 #include "utilities/align.hpp" 36 #include "utilities/defaultStream.hpp" 37 #include "utilities/globalDefinitions.hpp" 38 #include "vm_version_ppc.hpp" 39 40 # include <sys/sysinfo.h> 41 42 bool VM_Version::_is_determine_features_test_running = false; 43 uint64_t VM_Version::_dscr_val = 0; 44 45 #define MSG(flag) \ 46 if (flag && !FLAG_IS_DEFAULT(flag)) \ 47 jio_fprintf(defaultStream::error_stream(), \ 48 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \ 49 " -XX:+" #flag " will be disabled!\n"); 50 51 void VM_Version::initialize() { 52 53 // Test which instructions are supported and measure cache line size. 54 determine_features(); 55 56 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. 57 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { 58 if (VM_Version::has_lqarx()) { 59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8); 60 } else if (VM_Version::has_popcntw()) { 61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7); 62 } else if (VM_Version::has_cmpb()) { 63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6); 64 } else if (VM_Version::has_popcntb()) { 65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5); 66 } else { 67 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0); 68 } 69 } 70 71 bool PowerArchitecturePPC64_ok = false; 72 switch (PowerArchitecturePPC64) { 73 case 8: if (!VM_Version::has_lqarx() ) break; 74 case 7: if (!VM_Version::has_popcntw()) break; 75 case 6: if (!VM_Version::has_cmpb() ) break; 76 case 5: if (!VM_Version::has_popcntb()) break; 77 case 0: PowerArchitecturePPC64_ok = true; break; 78 default: break; 79 } 80 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to " 81 UINTX_FORMAT " on this machine", PowerArchitecturePPC64); 82 83 // Power 8: Configure Data Stream Control Register. 84 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) { 85 config_dscr(); 86 } 87 88 if (!UseSIGTRAP) { 89 MSG(TrapBasedICMissChecks); 90 MSG(TrapBasedNotEntrantChecks); 91 MSG(TrapBasedNullChecks); 92 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false); 93 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false); 94 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false); 95 } 96 97 #ifdef COMPILER2 98 if (!UseSIGTRAP) { 99 MSG(TrapBasedRangeChecks); 100 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false); 101 } 102 103 // On Power6 test for section size. 104 if (PowerArchitecturePPC64 == 6) { 105 determine_section_size(); 106 // TODO: PPC port } else { 107 // TODO: PPC port PdScheduling::power6SectorSize = 0x20; 108 } 109 110 MaxVectorSize = 8; 111 #endif 112 113 // Create and print feature-string. 114 char buf[(num_features+1) * 16]; // Max 16 chars per feature. 115 jio_snprintf(buf, sizeof(buf), 116 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 117 (has_fsqrt() ? " fsqrt" : ""), 118 (has_isel() ? " isel" : ""), 119 (has_lxarxeh() ? " lxarxeh" : ""), 120 (has_cmpb() ? " cmpb" : ""), 121 //(has_mftgpr()? " mftgpr" : ""), 122 (has_popcntb() ? " popcntb" : ""), 123 (has_popcntw() ? " popcntw" : ""), 124 (has_fcfids() ? " fcfids" : ""), 125 (has_vand() ? " vand" : ""), 126 (has_lqarx() ? " lqarx" : ""), 127 (has_vcipher() ? " aes" : ""), 128 (has_vpmsumb() ? " vpmsumb" : ""), 129 (has_tcheck() ? " tcheck" : ""), 130 (has_mfdscr() ? " mfdscr" : ""), 131 (has_vsx() ? " vsx" : ""), 132 (has_ldbrx() ? " ldbrx" : ""), 133 (has_stdbrx() ? " stdbrx" : "") 134 // Make sure number of %s matches num_features! 135 ); 136 _features_string = os::strdup(buf); 137 if (Verbose) { 138 print_features(); 139 } 140 141 // PPC64 supports 8-byte compare-exchange operations (see 142 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr) 143 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile). 144 _supports_cx8 = true; 145 146 // Used by C1. 147 _supports_atomic_getset4 = true; 148 _supports_atomic_getadd4 = true; 149 _supports_atomic_getset8 = true; 150 _supports_atomic_getadd8 = true; 151 152 UseSSE = 0; // Only on x86 and x64 153 154 intx cache_line_size = L1_data_cache_line_size(); 155 156 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; 157 158 if (AllocatePrefetchStyle == 4) { 159 AllocatePrefetchStepSize = cache_line_size; // Need exact value. 160 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default. 161 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined? 162 } else { 163 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size; 164 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value. 165 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined? 166 } 167 168 assert(AllocatePrefetchLines > 0, "invalid value"); 169 if (AllocatePrefetchLines < 1) { // Set valid value in product VM. 170 AllocatePrefetchLines = 1; // Conservative value. 171 } 172 173 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) { 174 AllocatePrefetchStyle = 1; // Fall back if inappropriate. 175 } 176 177 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 178 179 // If defined(VM_LITTLE_ENDIAN) and running on Power8 or newer hardware, 180 // the implementation uses the vector instructions available with Power8. 181 // In all other cases, the implementation uses only generally available instructions. 182 if (!UseCRC32Intrinsics) { 183 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 184 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); 185 } 186 } 187 188 // Implementation does not use any of the vector instructions available with Power8. 189 // Their exploitation is still pending (aka "work in progress"). 190 if (!UseCRC32CIntrinsics) { 191 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 192 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); 193 } 194 } 195 196 // TODO: Provide implementation. 197 if (UseAdler32Intrinsics) { 198 warning("Adler32Intrinsics not available on this CPU."); 199 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 200 } 201 202 // The AES intrinsic stubs require AES instruction support. 203 #if defined(VM_LITTLE_ENDIAN) 204 if (has_vcipher()) { 205 if (FLAG_IS_DEFAULT(UseAES)) { 206 UseAES = true; 207 } 208 } else if (UseAES) { 209 if (!FLAG_IS_DEFAULT(UseAES)) 210 warning("AES instructions are not available on this CPU"); 211 FLAG_SET_DEFAULT(UseAES, false); 212 } 213 214 if (UseAES && has_vcipher()) { 215 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 216 UseAESIntrinsics = true; 217 } 218 } else if (UseAESIntrinsics) { 219 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 220 warning("AES intrinsics are not available on this CPU"); 221 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 222 } 223 224 #else 225 if (UseAES) { 226 warning("AES instructions are not available on this CPU"); 227 FLAG_SET_DEFAULT(UseAES, false); 228 } 229 if (UseAESIntrinsics) { 230 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 231 warning("AES intrinsics are not available on this CPU"); 232 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 233 } 234 #endif 235 236 if (UseAESCTRIntrinsics) { 237 warning("AES/CTR intrinsics are not available on this CPU"); 238 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 239 } 240 241 if (UseGHASHIntrinsics) { 242 warning("GHASH intrinsics are not available on this CPU"); 243 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 244 } 245 246 if (FLAG_IS_DEFAULT(UseFMA)) { 247 FLAG_SET_DEFAULT(UseFMA, true); 248 } 249 250 if (UseSHA) { 251 warning("SHA instructions are not available on this CPU"); 252 FLAG_SET_DEFAULT(UseSHA, false); 253 } 254 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { 255 warning("SHA intrinsics are not available on this CPU"); 256 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 257 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 258 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 259 } 260 261 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 262 UseMultiplyToLenIntrinsic = true; 263 } 264 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 265 UseMontgomeryMultiplyIntrinsic = true; 266 } 267 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 268 UseMontgomerySquareIntrinsic = true; 269 } 270 271 if (UseVectorizedMismatchIntrinsic) { 272 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 273 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 274 } 275 276 277 // Adjust RTM (Restricted Transactional Memory) flags. 278 if (UseRTMLocking) { 279 // If CPU or OS are too old: 280 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 281 // setting during arguments processing. See use_biased_locking(). 282 // VM_Version_init() is executed after UseBiasedLocking is used 283 // in Thread::allocate(). 284 if (!has_tcheck()) { 285 vm_exit_during_initialization("RTM instructions are not available on this CPU"); 286 } 287 bool os_too_old = true; 288 #ifdef AIX 289 // Actually, this is supported since AIX 7.1.. Unfortunately, this first 290 // contained bugs, so that it can only be enabled after AIX 7.1.3.30. 291 // The Java property os.version, which is used in RTM tests to decide 292 // whether the feature is available, only knows major and minor versions. 293 // We don't want to change this property, as user code might depend on it. 294 // So the tests can not check on subversion 3.30, and we only enable RTM 295 // with AIX 7.2. 296 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2. 297 os_too_old = false; 298 } 299 #endif 300 #ifdef LINUX 301 // At least Linux kernel 4.2, as the problematic behavior of syscalls 302 // being called in the middle of a transaction has been addressed. 303 // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894 304 // in Linux kernel source tree: https://goo.gl/Kc5i7A 305 if (os::Linux::os_version_is_known()) { 306 if (os::Linux::os_version() >= 0x040200) 307 os_too_old = false; 308 } else { 309 vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown."); 310 } 311 #endif 312 if (os_too_old) { 313 vm_exit_during_initialization("RTM is not supported on this OS version."); 314 } 315 } 316 317 if (UseRTMLocking) { 318 #if INCLUDE_RTM_OPT 319 if (!UnlockExperimentalVMOptions) { 320 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. " 321 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); 322 } else { 323 warning("UseRTMLocking is only available as experimental option on this platform."); 324 } 325 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { 326 // RTM locking should be used only for applications with 327 // high lock contention. For now we do not use it by default. 328 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); 329 } 330 if (!is_power_of_2(RTMTotalCountIncrRate)) { 331 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); 332 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); 333 } 334 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { 335 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); 336 FLAG_SET_DEFAULT(RTMAbortRatio, 50); 337 } 338 if (RTMSpinLoopCount < 0) { 339 warning("RTMSpinLoopCount must not be a negative value, resetting it to 0"); 340 FLAG_SET_DEFAULT(RTMSpinLoopCount, 0); 341 } 342 #else 343 // Only C2 does RTM locking optimization. 344 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 345 // setting during arguments processing. See use_biased_locking(). 346 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); 347 #endif 348 } else { // !UseRTMLocking 349 if (UseRTMForStackLocks) { 350 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { 351 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); 352 } 353 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); 354 } 355 if (UseRTMDeopt) { 356 FLAG_SET_DEFAULT(UseRTMDeopt, false); 357 } 358 if (PrintPreciseRTMLockingStatistics) { 359 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); 360 } 361 } 362 363 // This machine allows unaligned memory accesses 364 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 365 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 366 } 367 } 368 369 bool VM_Version::use_biased_locking() { 370 #if INCLUDE_RTM_OPT 371 // RTM locking is most useful when there is high lock contention and 372 // low data contention. With high lock contention the lock is usually 373 // inflated and biased locking is not suitable for that case. 374 // RTM locking code requires that biased locking is off. 375 // Note: we can't switch off UseBiasedLocking in get_processor_features() 376 // because it is used by Thread::allocate() which is called before 377 // VM_Version::initialize(). 378 if (UseRTMLocking && UseBiasedLocking) { 379 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { 380 FLAG_SET_DEFAULT(UseBiasedLocking, false); 381 } else { 382 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); 383 UseBiasedLocking = false; 384 } 385 } 386 #endif 387 return UseBiasedLocking; 388 } 389 390 void VM_Version::print_features() { 391 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size()); 392 } 393 394 #ifdef COMPILER2 395 // Determine section size on power6: If section size is 8 instructions, 396 // there should be a difference between the two testloops of ~15 %. If 397 // no difference is detected the section is assumed to be 32 instructions. 398 void VM_Version::determine_section_size() { 399 400 int unroll = 80; 401 402 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord; 403 404 // Allocate space for the code. 405 ResourceMark rm; 406 CodeBuffer cb("detect_section_size", code_size, 0); 407 MacroAssembler* a = new MacroAssembler(&cb); 408 409 uint32_t *code = (uint32_t *)a->pc(); 410 // Emit code. 411 void (*test1)() = (void(*)())(void *)a->function_entry(); 412 413 Label l1; 414 415 a->li(R4, 1); 416 a->sldi(R4, R4, 28); 417 a->b(l1); 418 a->align(CodeEntryAlignment); 419 420 a->bind(l1); 421 422 for (int i = 0; i < unroll; i++) { 423 // Schleife 1 424 // ------- sector 0 ------------ 425 // ;; 0 426 a->nop(); // 1 427 a->fpnop0(); // 2 428 a->fpnop1(); // 3 429 a->addi(R4,R4, -1); // 4 430 431 // ;; 1 432 a->nop(); // 5 433 a->fmr(F6, F6); // 6 434 a->fmr(F7, F7); // 7 435 a->endgroup(); // 8 436 // ------- sector 8 ------------ 437 438 // ;; 2 439 a->nop(); // 9 440 a->nop(); // 10 441 a->fmr(F8, F8); // 11 442 a->fmr(F9, F9); // 12 443 444 // ;; 3 445 a->nop(); // 13 446 a->fmr(F10, F10); // 14 447 a->fmr(F11, F11); // 15 448 a->endgroup(); // 16 449 // -------- sector 16 ------------- 450 451 // ;; 4 452 a->nop(); // 17 453 a->nop(); // 18 454 a->fmr(F15, F15); // 19 455 a->fmr(F16, F16); // 20 456 457 // ;; 5 458 a->nop(); // 21 459 a->fmr(F17, F17); // 22 460 a->fmr(F18, F18); // 23 461 a->endgroup(); // 24 462 // ------- sector 24 ------------ 463 464 // ;; 6 465 a->nop(); // 25 466 a->nop(); // 26 467 a->fmr(F19, F19); // 27 468 a->fmr(F20, F20); // 28 469 470 // ;; 7 471 a->nop(); // 29 472 a->fmr(F21, F21); // 30 473 a->fmr(F22, F22); // 31 474 a->brnop0(); // 32 475 476 // ------- sector 32 ------------ 477 } 478 479 // ;; 8 480 a->cmpdi(CCR0, R4, unroll); // 33 481 a->bge(CCR0, l1); // 34 482 a->blr(); 483 484 // Emit code. 485 void (*test2)() = (void(*)())(void *)a->function_entry(); 486 // uint32_t *code = (uint32_t *)a->pc(); 487 488 Label l2; 489 490 a->li(R4, 1); 491 a->sldi(R4, R4, 28); 492 a->b(l2); 493 a->align(CodeEntryAlignment); 494 495 a->bind(l2); 496 497 for (int i = 0; i < unroll; i++) { 498 // Schleife 2 499 // ------- sector 0 ------------ 500 // ;; 0 501 a->brnop0(); // 1 502 a->nop(); // 2 503 //a->cmpdi(CCR0, R4, unroll); 504 a->fpnop0(); // 3 505 a->fpnop1(); // 4 506 a->addi(R4,R4, -1); // 5 507 508 // ;; 1 509 510 a->nop(); // 6 511 a->fmr(F6, F6); // 7 512 a->fmr(F7, F7); // 8 513 // ------- sector 8 --------------- 514 515 // ;; 2 516 a->endgroup(); // 9 517 518 // ;; 3 519 a->nop(); // 10 520 a->nop(); // 11 521 a->fmr(F8, F8); // 12 522 523 // ;; 4 524 a->fmr(F9, F9); // 13 525 a->nop(); // 14 526 a->fmr(F10, F10); // 15 527 528 // ;; 5 529 a->fmr(F11, F11); // 16 530 // -------- sector 16 ------------- 531 532 // ;; 6 533 a->endgroup(); // 17 534 535 // ;; 7 536 a->nop(); // 18 537 a->nop(); // 19 538 a->fmr(F15, F15); // 20 539 540 // ;; 8 541 a->fmr(F16, F16); // 21 542 a->nop(); // 22 543 a->fmr(F17, F17); // 23 544 545 // ;; 9 546 a->fmr(F18, F18); // 24 547 // -------- sector 24 ------------- 548 549 // ;; 10 550 a->endgroup(); // 25 551 552 // ;; 11 553 a->nop(); // 26 554 a->nop(); // 27 555 a->fmr(F19, F19); // 28 556 557 // ;; 12 558 a->fmr(F20, F20); // 29 559 a->nop(); // 30 560 a->fmr(F21, F21); // 31 561 562 // ;; 13 563 a->fmr(F22, F22); // 32 564 } 565 566 // -------- sector 32 ------------- 567 // ;; 14 568 a->cmpdi(CCR0, R4, unroll); // 33 569 a->bge(CCR0, l2); // 34 570 571 a->blr(); 572 uint32_t *code_end = (uint32_t *)a->pc(); 573 a->flush(); 574 575 double loop1_seconds,loop2_seconds, rel_diff; 576 uint64_t start1, stop1; 577 578 start1 = os::current_thread_cpu_time(false); 579 (*test1)(); 580 stop1 = os::current_thread_cpu_time(false); 581 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0); 582 583 584 start1 = os::current_thread_cpu_time(false); 585 (*test2)(); 586 stop1 = os::current_thread_cpu_time(false); 587 588 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0); 589 590 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100; 591 592 if (PrintAssembly) { 593 ttyLocker ttyl; 594 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 595 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 596 tty->print_cr("Time loop1 :%f", loop1_seconds); 597 tty->print_cr("Time loop2 :%f", loop2_seconds); 598 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff); 599 600 if (rel_diff > 12.0) { 601 tty->print_cr("Section Size 8 Instructions"); 602 } else{ 603 tty->print_cr("Section Size 32 Instructions or Power5"); 604 } 605 } 606 607 #if 0 // TODO: PPC port 608 // Set sector size (if not set explicitly). 609 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) { 610 if (rel_diff > 12.0) { 611 PdScheduling::power6SectorSize = 0x20; 612 } else { 613 PdScheduling::power6SectorSize = 0x80; 614 } 615 } else if (Power6SectorSize128PPC64) { 616 PdScheduling::power6SectorSize = 0x80; 617 } else { 618 PdScheduling::power6SectorSize = 0x20; 619 } 620 #endif 621 if (UsePower6SchedulerPPC64) Unimplemented(); 622 } 623 #endif // COMPILER2 624 625 void VM_Version::determine_features() { 626 #if defined(ABI_ELFv2) 627 // 1 InstWord per call for the blr instruction. 628 const int code_size = (num_features+1+2*1)*BytesPerInstWord; 629 #else 630 // 7 InstWords for each call (function descriptor + blr instruction). 631 const int code_size = (num_features+1+2*7)*BytesPerInstWord; 632 #endif 633 int features = 0; 634 635 // create test area 636 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size). 637 char test_area[BUFFER_SIZE]; 638 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1]; 639 640 // Allocate space for the code. 641 ResourceMark rm; 642 CodeBuffer cb("detect_cpu_features", code_size, 0); 643 MacroAssembler* a = new MacroAssembler(&cb); 644 645 // Must be set to true so we can generate the test code. 646 _features = VM_Version::all_features_m; 647 648 // Emit code. 649 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); 650 uint32_t *code = (uint32_t *)a->pc(); 651 // Don't use R0 in ldarx. 652 // Keep R3_ARG1 unmodified, it contains &field (see below). 653 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). 654 a->fsqrt(F3, F4); // code[0] -> fsqrt_m 655 a->fsqrts(F3, F4); // code[1] -> fsqrts_m 656 a->isel(R7, R5, R6, 0); // code[2] -> isel_m 657 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m 658 a->cmpb(R7, R5, R6); // code[4] -> cmpb 659 a->popcntb(R7, R5); // code[5] -> popcntb 660 a->popcntw(R7, R5); // code[6] -> popcntw 661 a->fcfids(F3, F4); // code[7] -> fcfids 662 a->vand(VR0, VR0, VR0); // code[8] -> vand 663 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16 664 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m 665 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher 666 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb 667 a->tcheck(0); // code[12] -> tcheck 668 a->mfdscr(R0); // code[13] -> mfdscr 669 a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx 670 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> ldbrx 671 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[16] -> stdbrx 672 a->blr(); 673 674 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. 675 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); 676 a->dcbz(R3_ARG1); // R3_ARG1 = addr 677 a->blr(); 678 679 uint32_t *code_end = (uint32_t *)a->pc(); 680 a->flush(); 681 _features = VM_Version::unknown_m; 682 683 // Print the detection code. 684 if (PrintAssembly) { 685 ttyLocker ttyl; 686 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 687 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 688 } 689 690 // Measure cache line size. 691 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. 692 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle. 693 int count = 0; // count zeroed bytes 694 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++; 695 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); 696 _L1_data_cache_line_size = count; 697 698 // Execute code. Illegal instructions will be replaced by 0 in the signal handler. 699 VM_Version::_is_determine_features_test_running = true; 700 // We must align the first argument to 16 bytes because of the lqarx check. 701 (*test)(align_up((address)mid_of_test_area, 16), 0); 702 VM_Version::_is_determine_features_test_running = false; 703 704 // determine which instructions are legal. 705 int feature_cntr = 0; 706 if (code[feature_cntr++]) features |= fsqrt_m; 707 if (code[feature_cntr++]) features |= fsqrts_m; 708 if (code[feature_cntr++]) features |= isel_m; 709 if (code[feature_cntr++]) features |= lxarxeh_m; 710 if (code[feature_cntr++]) features |= cmpb_m; 711 if (code[feature_cntr++]) features |= popcntb_m; 712 if (code[feature_cntr++]) features |= popcntw_m; 713 if (code[feature_cntr++]) features |= fcfids_m; 714 if (code[feature_cntr++]) features |= vand_m; 715 if (code[feature_cntr++]) features |= lqarx_m; 716 if (code[feature_cntr++]) features |= vcipher_m; 717 if (code[feature_cntr++]) features |= vpmsumb_m; 718 if (code[feature_cntr++]) features |= tcheck_m; 719 if (code[feature_cntr++]) features |= mfdscr_m; 720 if (code[feature_cntr++]) features |= vsx_m; 721 if (code[feature_cntr++]) features |= ldbrx_m; 722 if (code[feature_cntr++]) features |= stdbrx_m; 723 724 // Print the detection code. 725 if (PrintAssembly) { 726 ttyLocker ttyl; 727 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code)); 728 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 729 } 730 731 _features = features; 732 } 733 734 // Power 8: Configure Data Stream Control Register. 735 void VM_Version::config_dscr() { 736 // 7 InstWords for each call (function descriptor + blr instruction). 737 const int code_size = (2+2*7)*BytesPerInstWord; 738 739 // Allocate space for the code. 740 ResourceMark rm; 741 CodeBuffer cb("config_dscr", code_size, 0); 742 MacroAssembler* a = new MacroAssembler(&cb); 743 744 // Emit code. 745 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry(); 746 uint32_t *code = (uint32_t *)a->pc(); 747 a->mfdscr(R3); 748 a->blr(); 749 750 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry(); 751 a->mtdscr(R3); 752 a->blr(); 753 754 uint32_t *code_end = (uint32_t *)a->pc(); 755 a->flush(); 756 757 // Print the detection code. 758 if (PrintAssembly) { 759 ttyLocker ttyl; 760 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code)); 761 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 762 } 763 764 // Apply the configuration if needed. 765 _dscr_val = (*get_dscr)(); 766 if (Verbose) { 767 tty->print_cr("dscr value was 0x%lx" , _dscr_val); 768 } 769 bool change_requested = false; 770 if (DSCR_PPC64 != (uintx)-1) { 771 _dscr_val = DSCR_PPC64; 772 change_requested = true; 773 } 774 if (DSCR_DPFD_PPC64 <= 7) { 775 uint64_t mask = 0x7; 776 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) { 777 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64); 778 change_requested = true; 779 } 780 } 781 if (DSCR_URG_PPC64 <= 7) { 782 uint64_t mask = 0x7 << 6; 783 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) { 784 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6); 785 change_requested = true; 786 } 787 } 788 if (change_requested) { 789 (*set_dscr)(_dscr_val); 790 if (Verbose) { 791 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)()); 792 } 793 } 794 } 795 796 static uint64_t saved_features = 0; 797 798 void VM_Version::allow_all() { 799 saved_features = _features; 800 _features = all_features_m; 801 } 802 803 void VM_Version::revert() { 804 _features = saved_features; 805 }