64 } else if (VM_Version::has_popcntb()) {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
66 } else {
67 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
68 }
69 }
70
71 bool PowerArchitecturePPC64_ok = false;
72 switch (PowerArchitecturePPC64) {
73 case 8: if (!VM_Version::has_lqarx() ) break;
74 case 7: if (!VM_Version::has_popcntw()) break;
75 case 6: if (!VM_Version::has_cmpb() ) break;
76 case 5: if (!VM_Version::has_popcntb()) break;
77 case 0: PowerArchitecturePPC64_ok = true; break;
78 default: break;
79 }
80 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
81 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
82
83 // Power 8: Configure Data Stream Control Register.
84 if (has_mfdscr()) {
85 config_dscr();
86 }
87
88 if (!UseSIGTRAP) {
89 MSG(TrapBasedICMissChecks);
90 MSG(TrapBasedNotEntrantChecks);
91 MSG(TrapBasedNullChecks);
92 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
93 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
94 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
95 }
96
97 #ifdef COMPILER2
98 if (!UseSIGTRAP) {
99 MSG(TrapBasedRangeChecks);
100 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
101 }
102
103 // On Power6 test for section size.
104 if (PowerArchitecturePPC64 == 6) {
681 _features = VM_Version::unknown_m;
682
683 // Print the detection code.
684 if (PrintAssembly) {
685 ttyLocker ttyl;
686 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
687 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
688 }
689
690 // Measure cache line size.
691 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
692 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
693 int count = 0; // count zeroed bytes
694 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
695 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
696 _L1_data_cache_line_size = count;
697
698 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
699 VM_Version::_is_determine_features_test_running = true;
700 // We must align the first argument to 16 bytes because of the lqarx check.
701 (*test)(align_up(mid_of_test_area, 16), (uint64_t)0);
702 VM_Version::_is_determine_features_test_running = false;
703
704 // determine which instructions are legal.
705 int feature_cntr = 0;
706 if (code[feature_cntr++]) features |= fsqrt_m;
707 if (code[feature_cntr++]) features |= fsqrts_m;
708 if (code[feature_cntr++]) features |= isel_m;
709 if (code[feature_cntr++]) features |= lxarxeh_m;
710 if (code[feature_cntr++]) features |= cmpb_m;
711 if (code[feature_cntr++]) features |= popcntb_m;
712 if (code[feature_cntr++]) features |= popcntw_m;
713 if (code[feature_cntr++]) features |= fcfids_m;
714 if (code[feature_cntr++]) features |= vand_m;
715 if (code[feature_cntr++]) features |= lqarx_m;
716 if (code[feature_cntr++]) features |= vcipher_m;
717 if (code[feature_cntr++]) features |= vpmsumb_m;
718 if (code[feature_cntr++]) features |= tcheck_m;
719 if (code[feature_cntr++]) features |= mfdscr_m;
720 if (code[feature_cntr++]) features |= vsx_m;
721 if (code[feature_cntr++]) features |= ldbrx_m;
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64 } else if (VM_Version::has_popcntb()) {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
66 } else {
67 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
68 }
69 }
70
71 bool PowerArchitecturePPC64_ok = false;
72 switch (PowerArchitecturePPC64) {
73 case 8: if (!VM_Version::has_lqarx() ) break;
74 case 7: if (!VM_Version::has_popcntw()) break;
75 case 6: if (!VM_Version::has_cmpb() ) break;
76 case 5: if (!VM_Version::has_popcntb()) break;
77 case 0: PowerArchitecturePPC64_ok = true; break;
78 default: break;
79 }
80 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
81 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
82
83 // Power 8: Configure Data Stream Control Register.
84 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
85 config_dscr();
86 }
87
88 if (!UseSIGTRAP) {
89 MSG(TrapBasedICMissChecks);
90 MSG(TrapBasedNotEntrantChecks);
91 MSG(TrapBasedNullChecks);
92 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
93 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
94 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
95 }
96
97 #ifdef COMPILER2
98 if (!UseSIGTRAP) {
99 MSG(TrapBasedRangeChecks);
100 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
101 }
102
103 // On Power6 test for section size.
104 if (PowerArchitecturePPC64 == 6) {
681 _features = VM_Version::unknown_m;
682
683 // Print the detection code.
684 if (PrintAssembly) {
685 ttyLocker ttyl;
686 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
687 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
688 }
689
690 // Measure cache line size.
691 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
692 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
693 int count = 0; // count zeroed bytes
694 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
695 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
696 _L1_data_cache_line_size = count;
697
698 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
699 VM_Version::_is_determine_features_test_running = true;
700 // We must align the first argument to 16 bytes because of the lqarx check.
701 (*test)(align_up((address)mid_of_test_area, 16), 0);
702 VM_Version::_is_determine_features_test_running = false;
703
704 // determine which instructions are legal.
705 int feature_cntr = 0;
706 if (code[feature_cntr++]) features |= fsqrt_m;
707 if (code[feature_cntr++]) features |= fsqrts_m;
708 if (code[feature_cntr++]) features |= isel_m;
709 if (code[feature_cntr++]) features |= lxarxeh_m;
710 if (code[feature_cntr++]) features |= cmpb_m;
711 if (code[feature_cntr++]) features |= popcntb_m;
712 if (code[feature_cntr++]) features |= popcntw_m;
713 if (code[feature_cntr++]) features |= fcfids_m;
714 if (code[feature_cntr++]) features |= vand_m;
715 if (code[feature_cntr++]) features |= lqarx_m;
716 if (code[feature_cntr++]) features |= vcipher_m;
717 if (code[feature_cntr++]) features |= vpmsumb_m;
718 if (code[feature_cntr++]) features |= tcheck_m;
719 if (code[feature_cntr++]) features |= mfdscr_m;
720 if (code[feature_cntr++]) features |= vsx_m;
721 if (code[feature_cntr++]) features |= ldbrx_m;
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