1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/cardTableModRefBS.hpp"
31 #include "gc/shared/collectedHeap.inline.hpp"
32 #include "interpreter/interpreter.hpp"
33 #include "memory/resourceArea.hpp"
34 #include "memory/universe.hpp"
35 #include "oops/klass.inline.hpp"
36 #include "prims/methodHandles.hpp"
37 #include "runtime/biasedLocking.hpp"
38 #include "runtime/interfaceSupport.hpp"
39 #include "runtime/objectMonitor.hpp"
40 #include "runtime/os.hpp"
41 #include "runtime/safepoint.hpp"
42 #include "runtime/safepointMechanism.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "runtime/thread.hpp"
46 #include "utilities/macros.hpp"
47 #if INCLUDE_ALL_GCS
48 #include "gc/g1/g1CollectedHeap.inline.hpp"
49 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
50 #include "gc/g1/heapRegion.hpp"
51 #endif // INCLUDE_ALL_GCS
52 #include "crc32c.h"
53 #ifdef COMPILER2
54 #include "opto/intrinsicnode.hpp"
55 #endif
56
57 #ifdef PRODUCT
58 #define BLOCK_COMMENT(str) /* nothing */
59 #define STOP(error) stop(error)
60 #else
61 #define BLOCK_COMMENT(str) block_comment(str)
62 #define STOP(error) block_comment(error); stop(error)
63 #endif
64
65 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
66
67 #ifdef ASSERT
68 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
69 #endif
70
71 static Assembler::Condition reverse[] = {
72 Assembler::noOverflow /* overflow = 0x0 */ ,
73 Assembler::overflow /* noOverflow = 0x1 */ ,
74 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
75 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
76 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
77 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
78 Assembler::above /* belowEqual = 0x6 */ ,
79 Assembler::belowEqual /* above = 0x7 */ ,
80 Assembler::positive /* negative = 0x8 */ ,
81 Assembler::negative /* positive = 0x9 */ ,
82 Assembler::noParity /* parity = 0xa */ ,
83 Assembler::parity /* noParity = 0xb */ ,
84 Assembler::greaterEqual /* less = 0xc */ ,
85 Assembler::less /* greaterEqual = 0xd */ ,
86 Assembler::greater /* lessEqual = 0xe */ ,
87 Assembler::lessEqual /* greater = 0xf, */
88
89 };
90
91
92 // Implementation of MacroAssembler
93
94 // First all the versions that have distinct versions depending on 32/64 bit
95 // Unless the difference is trivial (1 line or so).
96
97 #ifndef _LP64
98
99 // 32bit versions
100
101 Address MacroAssembler::as_Address(AddressLiteral adr) {
102 return Address(adr.target(), adr.rspec());
103 }
104
105 Address MacroAssembler::as_Address(ArrayAddress adr) {
106 return Address::make_array(adr);
107 }
108
109 void MacroAssembler::call_VM_leaf_base(address entry_point,
110 int number_of_arguments) {
111 call(RuntimeAddress(entry_point));
112 increment(rsp, number_of_arguments * wordSize);
113 }
114
115 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
116 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
117 }
118
119 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
120 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
121 }
122
123 void MacroAssembler::cmpoop(Address src1, jobject obj) {
124 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
125 }
126
127 void MacroAssembler::cmpoop(Register src1, jobject obj) {
128 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
129 }
130
131 void MacroAssembler::extend_sign(Register hi, Register lo) {
132 // According to Intel Doc. AP-526, "Integer Divide", p.18.
133 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
134 cdql();
135 } else {
136 movl(hi, lo);
137 sarl(hi, 31);
138 }
139 }
140
141 void MacroAssembler::jC2(Register tmp, Label& L) {
142 // set parity bit if FPU flag C2 is set (via rax)
143 save_rax(tmp);
144 fwait(); fnstsw_ax();
145 sahf();
146 restore_rax(tmp);
147 // branch
148 jcc(Assembler::parity, L);
149 }
150
151 void MacroAssembler::jnC2(Register tmp, Label& L) {
152 // set parity bit if FPU flag C2 is set (via rax)
153 save_rax(tmp);
154 fwait(); fnstsw_ax();
155 sahf();
156 restore_rax(tmp);
157 // branch
158 jcc(Assembler::noParity, L);
159 }
160
161 // 32bit can do a case table jump in one instruction but we no longer allow the base
162 // to be installed in the Address class
163 void MacroAssembler::jump(ArrayAddress entry) {
164 jmp(as_Address(entry));
165 }
166
167 // Note: y_lo will be destroyed
168 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
169 // Long compare for Java (semantics as described in JVM spec.)
170 Label high, low, done;
171
172 cmpl(x_hi, y_hi);
173 jcc(Assembler::less, low);
174 jcc(Assembler::greater, high);
175 // x_hi is the return register
176 xorl(x_hi, x_hi);
177 cmpl(x_lo, y_lo);
178 jcc(Assembler::below, low);
179 jcc(Assembler::equal, done);
180
181 bind(high);
182 xorl(x_hi, x_hi);
183 increment(x_hi);
184 jmp(done);
185
186 bind(low);
187 xorl(x_hi, x_hi);
188 decrementl(x_hi);
189
190 bind(done);
191 }
192
193 void MacroAssembler::lea(Register dst, AddressLiteral src) {
194 mov_literal32(dst, (int32_t)src.target(), src.rspec());
195 }
196
197 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
198 // leal(dst, as_Address(adr));
199 // see note in movl as to why we must use a move
200 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
201 }
202
203 void MacroAssembler::leave() {
204 mov(rsp, rbp);
205 pop(rbp);
206 }
207
208 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
209 // Multiplication of two Java long values stored on the stack
210 // as illustrated below. Result is in rdx:rax.
211 //
212 // rsp ---> [ ?? ] \ \
213 // .... | y_rsp_offset |
214 // [ y_lo ] / (in bytes) | x_rsp_offset
215 // [ y_hi ] | (in bytes)
216 // .... |
217 // [ x_lo ] /
218 // [ x_hi ]
219 // ....
220 //
221 // Basic idea: lo(result) = lo(x_lo * y_lo)
222 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
223 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
224 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
225 Label quick;
226 // load x_hi, y_hi and check if quick
227 // multiplication is possible
228 movl(rbx, x_hi);
229 movl(rcx, y_hi);
230 movl(rax, rbx);
231 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
232 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
233 // do full multiplication
234 // 1st step
235 mull(y_lo); // x_hi * y_lo
236 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
237 // 2nd step
238 movl(rax, x_lo);
239 mull(rcx); // x_lo * y_hi
240 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
241 // 3rd step
242 bind(quick); // note: rbx, = 0 if quick multiply!
243 movl(rax, x_lo);
244 mull(y_lo); // x_lo * y_lo
245 addl(rdx, rbx); // correct hi(x_lo * y_lo)
246 }
247
248 void MacroAssembler::lneg(Register hi, Register lo) {
249 negl(lo);
250 adcl(hi, 0);
251 negl(hi);
252 }
253
254 void MacroAssembler::lshl(Register hi, Register lo) {
255 // Java shift left long support (semantics as described in JVM spec., p.305)
256 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
257 // shift value is in rcx !
258 assert(hi != rcx, "must not use rcx");
259 assert(lo != rcx, "must not use rcx");
260 const Register s = rcx; // shift count
261 const int n = BitsPerWord;
262 Label L;
263 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
264 cmpl(s, n); // if (s < n)
265 jcc(Assembler::less, L); // else (s >= n)
266 movl(hi, lo); // x := x << n
267 xorl(lo, lo);
268 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
269 bind(L); // s (mod n) < n
270 shldl(hi, lo); // x := x << s
271 shll(lo);
272 }
273
274
275 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
276 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
277 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
278 assert(hi != rcx, "must not use rcx");
279 assert(lo != rcx, "must not use rcx");
280 const Register s = rcx; // shift count
281 const int n = BitsPerWord;
282 Label L;
283 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
284 cmpl(s, n); // if (s < n)
285 jcc(Assembler::less, L); // else (s >= n)
286 movl(lo, hi); // x := x >> n
287 if (sign_extension) sarl(hi, 31);
288 else xorl(hi, hi);
289 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
290 bind(L); // s (mod n) < n
291 shrdl(lo, hi); // x := x >> s
292 if (sign_extension) sarl(hi);
293 else shrl(hi);
294 }
295
296 void MacroAssembler::movoop(Register dst, jobject obj) {
297 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
298 }
299
300 void MacroAssembler::movoop(Address dst, jobject obj) {
301 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
302 }
303
304 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
305 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
309 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
310 }
311
312 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
313 // scratch register is not used,
314 // it is defined to match parameters of 64-bit version of this method.
315 if (src.is_lval()) {
316 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
317 } else {
318 movl(dst, as_Address(src));
319 }
320 }
321
322 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
323 movl(as_Address(dst), src);
324 }
325
326 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
327 movl(dst, as_Address(src));
328 }
329
330 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
331 void MacroAssembler::movptr(Address dst, intptr_t src) {
332 movl(dst, src);
333 }
334
335
336 void MacroAssembler::pop_callee_saved_registers() {
337 pop(rcx);
338 pop(rdx);
339 pop(rdi);
340 pop(rsi);
341 }
342
343 void MacroAssembler::pop_fTOS() {
344 fld_d(Address(rsp, 0));
345 addl(rsp, 2 * wordSize);
346 }
347
348 void MacroAssembler::push_callee_saved_registers() {
349 push(rsi);
350 push(rdi);
351 push(rdx);
352 push(rcx);
353 }
354
355 void MacroAssembler::push_fTOS() {
356 subl(rsp, 2 * wordSize);
357 fstp_d(Address(rsp, 0));
358 }
359
360
361 void MacroAssembler::pushoop(jobject obj) {
362 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
363 }
364
365 void MacroAssembler::pushklass(Metadata* obj) {
366 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
367 }
368
369 void MacroAssembler::pushptr(AddressLiteral src) {
370 if (src.is_lval()) {
371 push_literal32((int32_t)src.target(), src.rspec());
372 } else {
373 pushl(as_Address(src));
374 }
375 }
376
377 void MacroAssembler::set_word_if_not_zero(Register dst) {
378 xorl(dst, dst);
379 set_byte_if_not_zero(dst);
380 }
381
382 static void pass_arg0(MacroAssembler* masm, Register arg) {
383 masm->push(arg);
384 }
385
386 static void pass_arg1(MacroAssembler* masm, Register arg) {
387 masm->push(arg);
388 }
389
390 static void pass_arg2(MacroAssembler* masm, Register arg) {
391 masm->push(arg);
392 }
393
394 static void pass_arg3(MacroAssembler* masm, Register arg) {
395 masm->push(arg);
396 }
397
398 #ifndef PRODUCT
399 extern "C" void findpc(intptr_t x);
400 #endif
401
402 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
403 // In order to get locks to work, we need to fake a in_VM state
404 JavaThread* thread = JavaThread::current();
405 JavaThreadState saved_state = thread->thread_state();
406 thread->set_thread_state(_thread_in_vm);
407 if (ShowMessageBoxOnError) {
408 JavaThread* thread = JavaThread::current();
409 JavaThreadState saved_state = thread->thread_state();
410 thread->set_thread_state(_thread_in_vm);
411 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
412 ttyLocker ttyl;
413 BytecodeCounter::print();
414 }
415 // To see where a verify_oop failed, get $ebx+40/X for this frame.
416 // This is the value of eip which points to where verify_oop will return.
417 if (os::message_box(msg, "Execution stopped, print registers?")) {
418 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
419 BREAKPOINT;
420 }
421 } else {
422 ttyLocker ttyl;
423 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
424 }
425 // Don't assert holding the ttyLock
426 assert(false, "DEBUG MESSAGE: %s", msg);
427 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
428 }
429
430 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
431 ttyLocker ttyl;
432 FlagSetting fs(Debugging, true);
433 tty->print_cr("eip = 0x%08x", eip);
434 #ifndef PRODUCT
435 if ((WizardMode || Verbose) && PrintMiscellaneous) {
436 tty->cr();
437 findpc(eip);
438 tty->cr();
439 }
440 #endif
441 #define PRINT_REG(rax) \
442 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
443 PRINT_REG(rax);
444 PRINT_REG(rbx);
445 PRINT_REG(rcx);
446 PRINT_REG(rdx);
447 PRINT_REG(rdi);
448 PRINT_REG(rsi);
449 PRINT_REG(rbp);
450 PRINT_REG(rsp);
451 #undef PRINT_REG
452 // Print some words near top of staack.
453 int* dump_sp = (int*) rsp;
454 for (int col1 = 0; col1 < 8; col1++) {
455 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
456 os::print_location(tty, *dump_sp++);
457 }
458 for (int row = 0; row < 16; row++) {
459 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
460 for (int col = 0; col < 8; col++) {
461 tty->print(" 0x%08x", *dump_sp++);
462 }
463 tty->cr();
464 }
465 // Print some instructions around pc:
466 Disassembler::decode((address)eip-64, (address)eip);
467 tty->print_cr("--------");
468 Disassembler::decode((address)eip, (address)eip+32);
469 }
470
471 void MacroAssembler::stop(const char* msg) {
472 ExternalAddress message((address)msg);
473 // push address of message
474 pushptr(message.addr());
475 { Label L; call(L, relocInfo::none); bind(L); } // push eip
476 pusha(); // push registers
477 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
478 hlt();
479 }
480
481 void MacroAssembler::warn(const char* msg) {
482 push_CPU_state();
483
484 ExternalAddress message((address) msg);
485 // push address of message
486 pushptr(message.addr());
487
488 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
489 addl(rsp, wordSize); // discard argument
490 pop_CPU_state();
491 }
492
493 void MacroAssembler::print_state() {
494 { Label L; call(L, relocInfo::none); bind(L); } // push eip
495 pusha(); // push registers
496
497 push_CPU_state();
498 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
499 pop_CPU_state();
500
501 popa();
502 addl(rsp, wordSize);
503 }
504
505 #else // _LP64
506
507 // 64 bit versions
508
509 Address MacroAssembler::as_Address(AddressLiteral adr) {
510 // amd64 always does this as a pc-rel
511 // we can be absolute or disp based on the instruction type
512 // jmp/call are displacements others are absolute
513 assert(!adr.is_lval(), "must be rval");
514 assert(reachable(adr), "must be");
515 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
516
517 }
518
519 Address MacroAssembler::as_Address(ArrayAddress adr) {
520 AddressLiteral base = adr.base();
521 lea(rscratch1, base);
522 Address index = adr.index();
523 assert(index._disp == 0, "must not have disp"); // maybe it can?
524 Address array(rscratch1, index._index, index._scale, index._disp);
525 return array;
526 }
527
528 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
529 Label L, E;
530
531 #ifdef _WIN64
532 // Windows always allocates space for it's register args
533 assert(num_args <= 4, "only register arguments supported");
534 subq(rsp, frame::arg_reg_save_area_bytes);
535 #endif
536
537 // Align stack if necessary
538 testl(rsp, 15);
539 jcc(Assembler::zero, L);
540
541 subq(rsp, 8);
542 {
543 call(RuntimeAddress(entry_point));
544 }
545 addq(rsp, 8);
546 jmp(E);
547
548 bind(L);
549 {
550 call(RuntimeAddress(entry_point));
551 }
552
553 bind(E);
554
555 #ifdef _WIN64
556 // restore stack pointer
557 addq(rsp, frame::arg_reg_save_area_bytes);
558 #endif
559
560 }
561
562 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
563 assert(!src2.is_lval(), "should use cmpptr");
564
565 if (reachable(src2)) {
566 cmpq(src1, as_Address(src2));
567 } else {
568 lea(rscratch1, src2);
569 Assembler::cmpq(src1, Address(rscratch1, 0));
570 }
571 }
572
573 int MacroAssembler::corrected_idivq(Register reg) {
574 // Full implementation of Java ldiv and lrem; checks for special
575 // case as described in JVM spec., p.243 & p.271. The function
576 // returns the (pc) offset of the idivl instruction - may be needed
577 // for implicit exceptions.
578 //
579 // normal case special case
580 //
581 // input : rax: dividend min_long
582 // reg: divisor (may not be eax/edx) -1
583 //
584 // output: rax: quotient (= rax idiv reg) min_long
585 // rdx: remainder (= rax irem reg) 0
586 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
587 static const int64_t min_long = 0x8000000000000000;
588 Label normal_case, special_case;
589
590 // check for special case
591 cmp64(rax, ExternalAddress((address) &min_long));
592 jcc(Assembler::notEqual, normal_case);
593 xorl(rdx, rdx); // prepare rdx for possible special case (where
594 // remainder = 0)
595 cmpq(reg, -1);
596 jcc(Assembler::equal, special_case);
597
598 // handle normal case
599 bind(normal_case);
600 cdqq();
601 int idivq_offset = offset();
602 idivq(reg);
603
604 // normal and special case exit
605 bind(special_case);
606
607 return idivq_offset;
608 }
609
610 void MacroAssembler::decrementq(Register reg, int value) {
611 if (value == min_jint) { subq(reg, value); return; }
612 if (value < 0) { incrementq(reg, -value); return; }
613 if (value == 0) { ; return; }
614 if (value == 1 && UseIncDec) { decq(reg) ; return; }
615 /* else */ { subq(reg, value) ; return; }
616 }
617
618 void MacroAssembler::decrementq(Address dst, int value) {
619 if (value == min_jint) { subq(dst, value); return; }
620 if (value < 0) { incrementq(dst, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { decq(dst) ; return; }
623 /* else */ { subq(dst, value) ; return; }
624 }
625
626 void MacroAssembler::incrementq(AddressLiteral dst) {
627 if (reachable(dst)) {
628 incrementq(as_Address(dst));
629 } else {
630 lea(rscratch1, dst);
631 incrementq(Address(rscratch1, 0));
632 }
633 }
634
635 void MacroAssembler::incrementq(Register reg, int value) {
636 if (value == min_jint) { addq(reg, value); return; }
637 if (value < 0) { decrementq(reg, -value); return; }
638 if (value == 0) { ; return; }
639 if (value == 1 && UseIncDec) { incq(reg) ; return; }
640 /* else */ { addq(reg, value) ; return; }
641 }
642
643 void MacroAssembler::incrementq(Address dst, int value) {
644 if (value == min_jint) { addq(dst, value); return; }
645 if (value < 0) { decrementq(dst, -value); return; }
646 if (value == 0) { ; return; }
647 if (value == 1 && UseIncDec) { incq(dst) ; return; }
648 /* else */ { addq(dst, value) ; return; }
649 }
650
651 // 32bit can do a case table jump in one instruction but we no longer allow the base
652 // to be installed in the Address class
653 void MacroAssembler::jump(ArrayAddress entry) {
654 lea(rscratch1, entry.base());
655 Address dispatch = entry.index();
656 assert(dispatch._base == noreg, "must be");
657 dispatch._base = rscratch1;
658 jmp(dispatch);
659 }
660
661 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
662 ShouldNotReachHere(); // 64bit doesn't use two regs
663 cmpq(x_lo, y_lo);
664 }
665
666 void MacroAssembler::lea(Register dst, AddressLiteral src) {
667 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
668 }
669
670 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
671 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
672 movptr(dst, rscratch1);
673 }
674
675 void MacroAssembler::leave() {
676 // %%% is this really better? Why not on 32bit too?
677 emit_int8((unsigned char)0xC9); // LEAVE
678 }
679
680 void MacroAssembler::lneg(Register hi, Register lo) {
681 ShouldNotReachHere(); // 64bit doesn't use two regs
682 negq(lo);
683 }
684
685 void MacroAssembler::movoop(Register dst, jobject obj) {
686 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
687 }
688
689 void MacroAssembler::movoop(Address dst, jobject obj) {
690 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
691 movq(dst, rscratch1);
692 }
693
694 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
695 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
696 }
697
698 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
699 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
700 movq(dst, rscratch1);
701 }
702
703 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
704 if (src.is_lval()) {
705 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
706 } else {
707 if (reachable(src)) {
708 movq(dst, as_Address(src));
709 } else {
710 lea(scratch, src);
711 movq(dst, Address(scratch, 0));
712 }
713 }
714 }
715
716 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
717 movq(as_Address(dst), src);
718 }
719
720 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
721 movq(dst, as_Address(src));
722 }
723
724 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
725 void MacroAssembler::movptr(Address dst, intptr_t src) {
726 mov64(rscratch1, src);
727 movq(dst, rscratch1);
728 }
729
730 // These are mostly for initializing NULL
731 void MacroAssembler::movptr(Address dst, int32_t src) {
732 movslq(dst, src);
733 }
734
735 void MacroAssembler::movptr(Register dst, int32_t src) {
736 mov64(dst, (intptr_t)src);
737 }
738
739 void MacroAssembler::pushoop(jobject obj) {
740 movoop(rscratch1, obj);
741 push(rscratch1);
742 }
743
744 void MacroAssembler::pushklass(Metadata* obj) {
745 mov_metadata(rscratch1, obj);
746 push(rscratch1);
747 }
748
749 void MacroAssembler::pushptr(AddressLiteral src) {
750 lea(rscratch1, src);
751 if (src.is_lval()) {
752 push(rscratch1);
753 } else {
754 pushq(Address(rscratch1, 0));
755 }
756 }
757
758 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
759 // we must set sp to zero to clear frame
760 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
761 // must clear fp, so that compiled frames are not confused; it is
762 // possible that we need it only for debugging
763 if (clear_fp) {
764 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
765 }
766
767 // Always clear the pc because it could have been set by make_walkable()
768 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
769 vzeroupper();
770 }
771
772 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
773 Register last_java_fp,
774 address last_java_pc) {
775 vzeroupper();
776 // determine last_java_sp register
777 if (!last_java_sp->is_valid()) {
778 last_java_sp = rsp;
779 }
780
781 // last_java_fp is optional
782 if (last_java_fp->is_valid()) {
783 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
784 last_java_fp);
785 }
786
787 // last_java_pc is optional
788 if (last_java_pc != NULL) {
789 Address java_pc(r15_thread,
790 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
791 lea(rscratch1, InternalAddress(last_java_pc));
792 movptr(java_pc, rscratch1);
793 }
794
795 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
796 }
797
798 static void pass_arg0(MacroAssembler* masm, Register arg) {
799 if (c_rarg0 != arg ) {
800 masm->mov(c_rarg0, arg);
801 }
802 }
803
804 static void pass_arg1(MacroAssembler* masm, Register arg) {
805 if (c_rarg1 != arg ) {
806 masm->mov(c_rarg1, arg);
807 }
808 }
809
810 static void pass_arg2(MacroAssembler* masm, Register arg) {
811 if (c_rarg2 != arg ) {
812 masm->mov(c_rarg2, arg);
813 }
814 }
815
816 static void pass_arg3(MacroAssembler* masm, Register arg) {
817 if (c_rarg3 != arg ) {
818 masm->mov(c_rarg3, arg);
819 }
820 }
821
822 void MacroAssembler::stop(const char* msg) {
823 address rip = pc();
824 pusha(); // get regs on stack
825 lea(c_rarg0, ExternalAddress((address) msg));
826 lea(c_rarg1, InternalAddress(rip));
827 movq(c_rarg2, rsp); // pass pointer to regs array
828 andq(rsp, -16); // align stack as required by ABI
829 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
830 hlt();
831 }
832
833 void MacroAssembler::warn(const char* msg) {
834 push(rbp);
835 movq(rbp, rsp);
836 andq(rsp, -16); // align stack as required by push_CPU_state and call
837 push_CPU_state(); // keeps alignment at 16 bytes
838 lea(c_rarg0, ExternalAddress((address) msg));
839 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
840 pop_CPU_state();
841 mov(rsp, rbp);
842 pop(rbp);
843 }
844
845 void MacroAssembler::print_state() {
846 address rip = pc();
847 pusha(); // get regs on stack
848 push(rbp);
849 movq(rbp, rsp);
850 andq(rsp, -16); // align stack as required by push_CPU_state and call
851 push_CPU_state(); // keeps alignment at 16 bytes
852
853 lea(c_rarg0, InternalAddress(rip));
854 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
855 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
856
857 pop_CPU_state();
858 mov(rsp, rbp);
859 pop(rbp);
860 popa();
861 }
862
863 #ifndef PRODUCT
864 extern "C" void findpc(intptr_t x);
865 #endif
866
867 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
868 // In order to get locks to work, we need to fake a in_VM state
869 if (ShowMessageBoxOnError) {
870 JavaThread* thread = JavaThread::current();
871 JavaThreadState saved_state = thread->thread_state();
872 thread->set_thread_state(_thread_in_vm);
873 #ifndef PRODUCT
874 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
875 ttyLocker ttyl;
876 BytecodeCounter::print();
877 }
878 #endif
879 // To see where a verify_oop failed, get $ebx+40/X for this frame.
880 // XXX correct this offset for amd64
881 // This is the value of eip which points to where verify_oop will return.
882 if (os::message_box(msg, "Execution stopped, print registers?")) {
883 print_state64(pc, regs);
884 BREAKPOINT;
885 assert(false, "start up GDB");
886 }
887 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
888 } else {
889 ttyLocker ttyl;
890 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
891 msg);
892 assert(false, "DEBUG MESSAGE: %s", msg);
893 }
894 }
895
896 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
897 ttyLocker ttyl;
898 FlagSetting fs(Debugging, true);
899 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
900 #ifndef PRODUCT
901 tty->cr();
902 findpc(pc);
903 tty->cr();
904 #endif
905 #define PRINT_REG(rax, value) \
906 { tty->print("%s = ", #rax); os::print_location(tty, value); }
907 PRINT_REG(rax, regs[15]);
908 PRINT_REG(rbx, regs[12]);
909 PRINT_REG(rcx, regs[14]);
910 PRINT_REG(rdx, regs[13]);
911 PRINT_REG(rdi, regs[8]);
912 PRINT_REG(rsi, regs[9]);
913 PRINT_REG(rbp, regs[10]);
914 PRINT_REG(rsp, regs[11]);
915 PRINT_REG(r8 , regs[7]);
916 PRINT_REG(r9 , regs[6]);
917 PRINT_REG(r10, regs[5]);
918 PRINT_REG(r11, regs[4]);
919 PRINT_REG(r12, regs[3]);
920 PRINT_REG(r13, regs[2]);
921 PRINT_REG(r14, regs[1]);
922 PRINT_REG(r15, regs[0]);
923 #undef PRINT_REG
924 // Print some words near top of staack.
925 int64_t* rsp = (int64_t*) regs[11];
926 int64_t* dump_sp = rsp;
927 for (int col1 = 0; col1 < 8; col1++) {
928 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
929 os::print_location(tty, *dump_sp++);
930 }
931 for (int row = 0; row < 25; row++) {
932 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
933 for (int col = 0; col < 4; col++) {
934 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
935 }
936 tty->cr();
937 }
938 // Print some instructions around pc:
939 Disassembler::decode((address)pc-64, (address)pc);
940 tty->print_cr("--------");
941 Disassembler::decode((address)pc, (address)pc+32);
942 }
943
944 #endif // _LP64
945
946 // Now versions that are common to 32/64 bit
947
948 void MacroAssembler::addptr(Register dst, int32_t imm32) {
949 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
950 }
951
952 void MacroAssembler::addptr(Register dst, Register src) {
953 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
954 }
955
956 void MacroAssembler::addptr(Address dst, Register src) {
957 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
958 }
959
960 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
961 if (reachable(src)) {
962 Assembler::addsd(dst, as_Address(src));
963 } else {
964 lea(rscratch1, src);
965 Assembler::addsd(dst, Address(rscratch1, 0));
966 }
967 }
968
969 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
970 if (reachable(src)) {
971 addss(dst, as_Address(src));
972 } else {
973 lea(rscratch1, src);
974 addss(dst, Address(rscratch1, 0));
975 }
976 }
977
978 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
979 if (reachable(src)) {
980 Assembler::addpd(dst, as_Address(src));
981 } else {
982 lea(rscratch1, src);
983 Assembler::addpd(dst, Address(rscratch1, 0));
984 }
985 }
986
987 void MacroAssembler::align(int modulus) {
988 align(modulus, offset());
989 }
990
991 void MacroAssembler::align(int modulus, int target) {
992 if (target % modulus != 0) {
993 nop(modulus - (target % modulus));
994 }
995 }
996
997 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
998 // Used in sign-masking with aligned address.
999 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1000 if (reachable(src)) {
1001 Assembler::andpd(dst, as_Address(src));
1002 } else {
1003 lea(rscratch1, src);
1004 Assembler::andpd(dst, Address(rscratch1, 0));
1005 }
1006 }
1007
1008 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1009 // Used in sign-masking with aligned address.
1010 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1011 if (reachable(src)) {
1012 Assembler::andps(dst, as_Address(src));
1013 } else {
1014 lea(rscratch1, src);
1015 Assembler::andps(dst, Address(rscratch1, 0));
1016 }
1017 }
1018
1019 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1020 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1021 }
1022
1023 void MacroAssembler::atomic_incl(Address counter_addr) {
1024 if (os::is_MP())
1025 lock();
1026 incrementl(counter_addr);
1027 }
1028
1029 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1030 if (reachable(counter_addr)) {
1031 atomic_incl(as_Address(counter_addr));
1032 } else {
1033 lea(scr, counter_addr);
1034 atomic_incl(Address(scr, 0));
1035 }
1036 }
1037
1038 #ifdef _LP64
1039 void MacroAssembler::atomic_incq(Address counter_addr) {
1040 if (os::is_MP())
1041 lock();
1042 incrementq(counter_addr);
1043 }
1044
1045 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1046 if (reachable(counter_addr)) {
1047 atomic_incq(as_Address(counter_addr));
1048 } else {
1049 lea(scr, counter_addr);
1050 atomic_incq(Address(scr, 0));
1051 }
1052 }
1053 #endif
1054
1055 // Writes to stack successive pages until offset reached to check for
1056 // stack overflow + shadow pages. This clobbers tmp.
1057 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1058 movptr(tmp, rsp);
1059 // Bang stack for total size given plus shadow page size.
1060 // Bang one page at a time because large size can bang beyond yellow and
1061 // red zones.
1062 Label loop;
1063 bind(loop);
1064 movl(Address(tmp, (-os::vm_page_size())), size );
1065 subptr(tmp, os::vm_page_size());
1066 subl(size, os::vm_page_size());
1067 jcc(Assembler::greater, loop);
1068
1069 // Bang down shadow pages too.
1070 // At this point, (tmp-0) is the last address touched, so don't
1071 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1072 // was post-decremented.) Skip this address by starting at i=1, and
1073 // touch a few more pages below. N.B. It is important to touch all
1074 // the way down including all pages in the shadow zone.
1075 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1076 // this could be any sized move but this is can be a debugging crumb
1077 // so the bigger the better.
1078 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1079 }
1080 }
1081
1082 void MacroAssembler::reserved_stack_check() {
1083 // testing if reserved zone needs to be enabled
1084 Label no_reserved_zone_enabling;
1085 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1086 NOT_LP64(get_thread(rsi);)
1087
1088 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1089 jcc(Assembler::below, no_reserved_zone_enabling);
1090
1091 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1092 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1093 should_not_reach_here();
1094
1095 bind(no_reserved_zone_enabling);
1096 }
1097
1098 int MacroAssembler::biased_locking_enter(Register lock_reg,
1099 Register obj_reg,
1100 Register swap_reg,
1101 Register tmp_reg,
1102 bool swap_reg_contains_mark,
1103 Label& done,
1104 Label* slow_case,
1105 BiasedLockingCounters* counters) {
1106 assert(UseBiasedLocking, "why call this otherwise?");
1107 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1108 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1109 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1110 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1111 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1112 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1113
1114 if (PrintBiasedLockingStatistics && counters == NULL) {
1115 counters = BiasedLocking::counters();
1116 }
1117 // Biased locking
1118 // See whether the lock is currently biased toward our thread and
1119 // whether the epoch is still valid
1120 // Note that the runtime guarantees sufficient alignment of JavaThread
1121 // pointers to allow age to be placed into low bits
1122 // First check to see whether biasing is even enabled for this object
1123 Label cas_label;
1124 int null_check_offset = -1;
1125 if (!swap_reg_contains_mark) {
1126 null_check_offset = offset();
1127 movptr(swap_reg, mark_addr);
1128 }
1129 movptr(tmp_reg, swap_reg);
1130 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1131 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1132 jcc(Assembler::notEqual, cas_label);
1133 // The bias pattern is present in the object's header. Need to check
1134 // whether the bias owner and the epoch are both still current.
1135 #ifndef _LP64
1136 // Note that because there is no current thread register on x86_32 we
1137 // need to store off the mark word we read out of the object to
1138 // avoid reloading it and needing to recheck invariants below. This
1139 // store is unfortunate but it makes the overall code shorter and
1140 // simpler.
1141 movptr(saved_mark_addr, swap_reg);
1142 #endif
1143 if (swap_reg_contains_mark) {
1144 null_check_offset = offset();
1145 }
1146 load_prototype_header(tmp_reg, obj_reg);
1147 #ifdef _LP64
1148 orptr(tmp_reg, r15_thread);
1149 xorptr(tmp_reg, swap_reg);
1150 Register header_reg = tmp_reg;
1151 #else
1152 xorptr(tmp_reg, swap_reg);
1153 get_thread(swap_reg);
1154 xorptr(swap_reg, tmp_reg);
1155 Register header_reg = swap_reg;
1156 #endif
1157 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1158 if (counters != NULL) {
1159 cond_inc32(Assembler::zero,
1160 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1161 }
1162 jcc(Assembler::equal, done);
1163
1164 Label try_revoke_bias;
1165 Label try_rebias;
1166
1167 // At this point we know that the header has the bias pattern and
1168 // that we are not the bias owner in the current epoch. We need to
1169 // figure out more details about the state of the header in order to
1170 // know what operations can be legally performed on the object's
1171 // header.
1172
1173 // If the low three bits in the xor result aren't clear, that means
1174 // the prototype header is no longer biased and we have to revoke
1175 // the bias on this object.
1176 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1177 jccb(Assembler::notZero, try_revoke_bias);
1178
1179 // Biasing is still enabled for this data type. See whether the
1180 // epoch of the current bias is still valid, meaning that the epoch
1181 // bits of the mark word are equal to the epoch bits of the
1182 // prototype header. (Note that the prototype header's epoch bits
1183 // only change at a safepoint.) If not, attempt to rebias the object
1184 // toward the current thread. Note that we must be absolutely sure
1185 // that the current epoch is invalid in order to do this because
1186 // otherwise the manipulations it performs on the mark word are
1187 // illegal.
1188 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1189 jccb(Assembler::notZero, try_rebias);
1190
1191 // The epoch of the current bias is still valid but we know nothing
1192 // about the owner; it might be set or it might be clear. Try to
1193 // acquire the bias of the object using an atomic operation. If this
1194 // fails we will go in to the runtime to revoke the object's bias.
1195 // Note that we first construct the presumed unbiased header so we
1196 // don't accidentally blow away another thread's valid bias.
1197 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1198 andptr(swap_reg,
1199 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1200 #ifdef _LP64
1201 movptr(tmp_reg, swap_reg);
1202 orptr(tmp_reg, r15_thread);
1203 #else
1204 get_thread(tmp_reg);
1205 orptr(tmp_reg, swap_reg);
1206 #endif
1207 if (os::is_MP()) {
1208 lock();
1209 }
1210 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1211 // If the biasing toward our thread failed, this means that
1212 // another thread succeeded in biasing it toward itself and we
1213 // need to revoke that bias. The revocation will occur in the
1214 // interpreter runtime in the slow case.
1215 if (counters != NULL) {
1216 cond_inc32(Assembler::zero,
1217 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1218 }
1219 if (slow_case != NULL) {
1220 jcc(Assembler::notZero, *slow_case);
1221 }
1222 jmp(done);
1223
1224 bind(try_rebias);
1225 // At this point we know the epoch has expired, meaning that the
1226 // current "bias owner", if any, is actually invalid. Under these
1227 // circumstances _only_, we are allowed to use the current header's
1228 // value as the comparison value when doing the cas to acquire the
1229 // bias in the current epoch. In other words, we allow transfer of
1230 // the bias from one thread to another directly in this situation.
1231 //
1232 // FIXME: due to a lack of registers we currently blow away the age
1233 // bits in this situation. Should attempt to preserve them.
1234 load_prototype_header(tmp_reg, obj_reg);
1235 #ifdef _LP64
1236 orptr(tmp_reg, r15_thread);
1237 #else
1238 get_thread(swap_reg);
1239 orptr(tmp_reg, swap_reg);
1240 movptr(swap_reg, saved_mark_addr);
1241 #endif
1242 if (os::is_MP()) {
1243 lock();
1244 }
1245 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1246 // If the biasing toward our thread failed, then another thread
1247 // succeeded in biasing it toward itself and we need to revoke that
1248 // bias. The revocation will occur in the runtime in the slow case.
1249 if (counters != NULL) {
1250 cond_inc32(Assembler::zero,
1251 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1252 }
1253 if (slow_case != NULL) {
1254 jcc(Assembler::notZero, *slow_case);
1255 }
1256 jmp(done);
1257
1258 bind(try_revoke_bias);
1259 // The prototype mark in the klass doesn't have the bias bit set any
1260 // more, indicating that objects of this data type are not supposed
1261 // to be biased any more. We are going to try to reset the mark of
1262 // this object to the prototype value and fall through to the
1263 // CAS-based locking scheme. Note that if our CAS fails, it means
1264 // that another thread raced us for the privilege of revoking the
1265 // bias of this particular object, so it's okay to continue in the
1266 // normal locking code.
1267 //
1268 // FIXME: due to a lack of registers we currently blow away the age
1269 // bits in this situation. Should attempt to preserve them.
1270 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1271 load_prototype_header(tmp_reg, obj_reg);
1272 if (os::is_MP()) {
1273 lock();
1274 }
1275 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1276 // Fall through to the normal CAS-based lock, because no matter what
1277 // the result of the above CAS, some thread must have succeeded in
1278 // removing the bias bit from the object's header.
1279 if (counters != NULL) {
1280 cond_inc32(Assembler::zero,
1281 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1282 }
1283
1284 bind(cas_label);
1285
1286 return null_check_offset;
1287 }
1288
1289 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1290 assert(UseBiasedLocking, "why call this otherwise?");
1291
1292 // Check for biased locking unlock case, which is a no-op
1293 // Note: we do not have to check the thread ID for two reasons.
1294 // First, the interpreter checks for IllegalMonitorStateException at
1295 // a higher level. Second, if the bias was revoked while we held the
1296 // lock, the object could not be rebiased toward another thread, so
1297 // the bias bit would be clear.
1298 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1299 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1300 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1301 jcc(Assembler::equal, done);
1302 }
1303
1304 #ifdef COMPILER2
1305
1306 #if INCLUDE_RTM_OPT
1307
1308 // Update rtm_counters based on abort status
1309 // input: abort_status
1310 // rtm_counters (RTMLockingCounters*)
1311 // flags are killed
1312 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1313
1314 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1315 if (PrintPreciseRTMLockingStatistics) {
1316 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1317 Label check_abort;
1318 testl(abort_status, (1<<i));
1319 jccb(Assembler::equal, check_abort);
1320 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1321 bind(check_abort);
1322 }
1323 }
1324 }
1325
1326 // Branch if (random & (count-1) != 0), count is 2^n
1327 // tmp, scr and flags are killed
1328 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1329 assert(tmp == rax, "");
1330 assert(scr == rdx, "");
1331 rdtsc(); // modifies EDX:EAX
1332 andptr(tmp, count-1);
1333 jccb(Assembler::notZero, brLabel);
1334 }
1335
1336 // Perform abort ratio calculation, set no_rtm bit if high ratio
1337 // input: rtm_counters_Reg (RTMLockingCounters* address)
1338 // tmpReg, rtm_counters_Reg and flags are killed
1339 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1340 Register rtm_counters_Reg,
1341 RTMLockingCounters* rtm_counters,
1342 Metadata* method_data) {
1343 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1344
1345 if (RTMLockingCalculationDelay > 0) {
1346 // Delay calculation
1347 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1348 testptr(tmpReg, tmpReg);
1349 jccb(Assembler::equal, L_done);
1350 }
1351 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1352 // Aborted transactions = abort_count * 100
1353 // All transactions = total_count * RTMTotalCountIncrRate
1354 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1355
1356 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1357 cmpptr(tmpReg, RTMAbortThreshold);
1358 jccb(Assembler::below, L_check_always_rtm2);
1359 imulptr(tmpReg, tmpReg, 100);
1360
1361 Register scrReg = rtm_counters_Reg;
1362 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1363 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1364 imulptr(scrReg, scrReg, RTMAbortRatio);
1365 cmpptr(tmpReg, scrReg);
1366 jccb(Assembler::below, L_check_always_rtm1);
1367 if (method_data != NULL) {
1368 // set rtm_state to "no rtm" in MDO
1369 mov_metadata(tmpReg, method_data);
1370 if (os::is_MP()) {
1371 lock();
1372 }
1373 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1374 }
1375 jmpb(L_done);
1376 bind(L_check_always_rtm1);
1377 // Reload RTMLockingCounters* address
1378 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1379 bind(L_check_always_rtm2);
1380 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1381 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1382 jccb(Assembler::below, L_done);
1383 if (method_data != NULL) {
1384 // set rtm_state to "always rtm" in MDO
1385 mov_metadata(tmpReg, method_data);
1386 if (os::is_MP()) {
1387 lock();
1388 }
1389 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1390 }
1391 bind(L_done);
1392 }
1393
1394 // Update counters and perform abort ratio calculation
1395 // input: abort_status_Reg
1396 // rtm_counters_Reg, flags are killed
1397 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1398 Register rtm_counters_Reg,
1399 RTMLockingCounters* rtm_counters,
1400 Metadata* method_data,
1401 bool profile_rtm) {
1402
1403 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1404 // update rtm counters based on rax value at abort
1405 // reads abort_status_Reg, updates flags
1406 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1407 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1408 if (profile_rtm) {
1409 // Save abort status because abort_status_Reg is used by following code.
1410 if (RTMRetryCount > 0) {
1411 push(abort_status_Reg);
1412 }
1413 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1414 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1415 // restore abort status
1416 if (RTMRetryCount > 0) {
1417 pop(abort_status_Reg);
1418 }
1419 }
1420 }
1421
1422 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1423 // inputs: retry_count_Reg
1424 // : abort_status_Reg
1425 // output: retry_count_Reg decremented by 1
1426 // flags are killed
1427 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1428 Label doneRetry;
1429 assert(abort_status_Reg == rax, "");
1430 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1431 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1432 // if reason is in 0x6 and retry count != 0 then retry
1433 andptr(abort_status_Reg, 0x6);
1434 jccb(Assembler::zero, doneRetry);
1435 testl(retry_count_Reg, retry_count_Reg);
1436 jccb(Assembler::zero, doneRetry);
1437 pause();
1438 decrementl(retry_count_Reg);
1439 jmp(retryLabel);
1440 bind(doneRetry);
1441 }
1442
1443 // Spin and retry if lock is busy,
1444 // inputs: box_Reg (monitor address)
1445 // : retry_count_Reg
1446 // output: retry_count_Reg decremented by 1
1447 // : clear z flag if retry count exceeded
1448 // tmp_Reg, scr_Reg, flags are killed
1449 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1450 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1451 Label SpinLoop, SpinExit, doneRetry;
1452 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1453
1454 testl(retry_count_Reg, retry_count_Reg);
1455 jccb(Assembler::zero, doneRetry);
1456 decrementl(retry_count_Reg);
1457 movptr(scr_Reg, RTMSpinLoopCount);
1458
1459 bind(SpinLoop);
1460 pause();
1461 decrementl(scr_Reg);
1462 jccb(Assembler::lessEqual, SpinExit);
1463 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1464 testptr(tmp_Reg, tmp_Reg);
1465 jccb(Assembler::notZero, SpinLoop);
1466
1467 bind(SpinExit);
1468 jmp(retryLabel);
1469 bind(doneRetry);
1470 incrementl(retry_count_Reg); // clear z flag
1471 }
1472
1473 // Use RTM for normal stack locks
1474 // Input: objReg (object to lock)
1475 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1476 Register retry_on_abort_count_Reg,
1477 RTMLockingCounters* stack_rtm_counters,
1478 Metadata* method_data, bool profile_rtm,
1479 Label& DONE_LABEL, Label& IsInflated) {
1480 assert(UseRTMForStackLocks, "why call this otherwise?");
1481 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1482 assert(tmpReg == rax, "");
1483 assert(scrReg == rdx, "");
1484 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1485
1486 if (RTMRetryCount > 0) {
1487 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1488 bind(L_rtm_retry);
1489 }
1490 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1491 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1492 jcc(Assembler::notZero, IsInflated);
1493
1494 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1495 Label L_noincrement;
1496 if (RTMTotalCountIncrRate > 1) {
1497 // tmpReg, scrReg and flags are killed
1498 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1499 }
1500 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1501 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1502 bind(L_noincrement);
1503 }
1504 xbegin(L_on_abort);
1505 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1506 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1507 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1508 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1509
1510 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1511 if (UseRTMXendForLockBusy) {
1512 xend();
1513 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1514 jmp(L_decrement_retry);
1515 }
1516 else {
1517 xabort(0);
1518 }
1519 bind(L_on_abort);
1520 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1521 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1522 }
1523 bind(L_decrement_retry);
1524 if (RTMRetryCount > 0) {
1525 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1526 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1527 }
1528 }
1529
1530 // Use RTM for inflating locks
1531 // inputs: objReg (object to lock)
1532 // boxReg (on-stack box address (displaced header location) - KILLED)
1533 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1534 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1535 Register scrReg, Register retry_on_busy_count_Reg,
1536 Register retry_on_abort_count_Reg,
1537 RTMLockingCounters* rtm_counters,
1538 Metadata* method_data, bool profile_rtm,
1539 Label& DONE_LABEL) {
1540 assert(UseRTMLocking, "why call this otherwise?");
1541 assert(tmpReg == rax, "");
1542 assert(scrReg == rdx, "");
1543 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1544 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1545
1546 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1547 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1548 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1549
1550 if (RTMRetryCount > 0) {
1551 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1552 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1553 bind(L_rtm_retry);
1554 }
1555 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1556 Label L_noincrement;
1557 if (RTMTotalCountIncrRate > 1) {
1558 // tmpReg, scrReg and flags are killed
1559 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1560 }
1561 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1562 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1563 bind(L_noincrement);
1564 }
1565 xbegin(L_on_abort);
1566 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1567 movptr(tmpReg, Address(tmpReg, owner_offset));
1568 testptr(tmpReg, tmpReg);
1569 jcc(Assembler::zero, DONE_LABEL);
1570 if (UseRTMXendForLockBusy) {
1571 xend();
1572 jmp(L_decrement_retry);
1573 }
1574 else {
1575 xabort(0);
1576 }
1577 bind(L_on_abort);
1578 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1579 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1580 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1581 }
1582 if (RTMRetryCount > 0) {
1583 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1584 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1585 }
1586
1587 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1588 testptr(tmpReg, tmpReg) ;
1589 jccb(Assembler::notZero, L_decrement_retry) ;
1590
1591 // Appears unlocked - try to swing _owner from null to non-null.
1592 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1593 #ifdef _LP64
1594 Register threadReg = r15_thread;
1595 #else
1596 get_thread(scrReg);
1597 Register threadReg = scrReg;
1598 #endif
1599 if (os::is_MP()) {
1600 lock();
1601 }
1602 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1603
1604 if (RTMRetryCount > 0) {
1605 // success done else retry
1606 jccb(Assembler::equal, DONE_LABEL) ;
1607 bind(L_decrement_retry);
1608 // Spin and retry if lock is busy.
1609 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1610 }
1611 else {
1612 bind(L_decrement_retry);
1613 }
1614 }
1615
1616 #endif // INCLUDE_RTM_OPT
1617
1618 // Fast_Lock and Fast_Unlock used by C2
1619
1620 // Because the transitions from emitted code to the runtime
1621 // monitorenter/exit helper stubs are so slow it's critical that
1622 // we inline both the stack-locking fast-path and the inflated fast path.
1623 //
1624 // See also: cmpFastLock and cmpFastUnlock.
1625 //
1626 // What follows is a specialized inline transliteration of the code
1627 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1628 // another option would be to emit TrySlowEnter and TrySlowExit methods
1629 // at startup-time. These methods would accept arguments as
1630 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1631 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1632 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1633 // In practice, however, the # of lock sites is bounded and is usually small.
1634 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1635 // if the processor uses simple bimodal branch predictors keyed by EIP
1636 // Since the helper routines would be called from multiple synchronization
1637 // sites.
1638 //
1639 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1640 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1641 // to those specialized methods. That'd give us a mostly platform-independent
1642 // implementation that the JITs could optimize and inline at their pleasure.
1643 // Done correctly, the only time we'd need to cross to native could would be
1644 // to park() or unpark() threads. We'd also need a few more unsafe operators
1645 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1646 // (b) explicit barriers or fence operations.
1647 //
1648 // TODO:
1649 //
1650 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1651 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1652 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1653 // the lock operators would typically be faster than reifying Self.
1654 //
1655 // * Ideally I'd define the primitives as:
1656 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1657 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1658 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1659 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1660 // Furthermore the register assignments are overconstrained, possibly resulting in
1661 // sub-optimal code near the synchronization site.
1662 //
1663 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1664 // Alternately, use a better sp-proximity test.
1665 //
1666 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1667 // Either one is sufficient to uniquely identify a thread.
1668 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1669 //
1670 // * Intrinsify notify() and notifyAll() for the common cases where the
1671 // object is locked by the calling thread but the waitlist is empty.
1672 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1673 //
1674 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1675 // But beware of excessive branch density on AMD Opterons.
1676 //
1677 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1678 // or failure of the fast-path. If the fast-path fails then we pass
1679 // control to the slow-path, typically in C. In Fast_Lock and
1680 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1681 // will emit a conditional branch immediately after the node.
1682 // So we have branches to branches and lots of ICC.ZF games.
1683 // Instead, it might be better to have C2 pass a "FailureLabel"
1684 // into Fast_Lock and Fast_Unlock. In the case of success, control
1685 // will drop through the node. ICC.ZF is undefined at exit.
1686 // In the case of failure, the node will branch directly to the
1687 // FailureLabel
1688
1689
1690 // obj: object to lock
1691 // box: on-stack box address (displaced header location) - KILLED
1692 // rax,: tmp -- KILLED
1693 // scr: tmp -- KILLED
1694 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1695 Register scrReg, Register cx1Reg, Register cx2Reg,
1696 BiasedLockingCounters* counters,
1697 RTMLockingCounters* rtm_counters,
1698 RTMLockingCounters* stack_rtm_counters,
1699 Metadata* method_data,
1700 bool use_rtm, bool profile_rtm) {
1701 // Ensure the register assignments are disjoint
1702 assert(tmpReg == rax, "");
1703
1704 if (use_rtm) {
1705 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1706 } else {
1707 assert(cx1Reg == noreg, "");
1708 assert(cx2Reg == noreg, "");
1709 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1710 }
1711
1712 if (counters != NULL) {
1713 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1714 }
1715 if (EmitSync & 1) {
1716 // set box->dhw = markOopDesc::unused_mark()
1717 // Force all sync thru slow-path: slow_enter() and slow_exit()
1718 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1719 cmpptr (rsp, (int32_t)NULL_WORD);
1720 } else {
1721 // Possible cases that we'll encounter in fast_lock
1722 // ------------------------------------------------
1723 // * Inflated
1724 // -- unlocked
1725 // -- Locked
1726 // = by self
1727 // = by other
1728 // * biased
1729 // -- by Self
1730 // -- by other
1731 // * neutral
1732 // * stack-locked
1733 // -- by self
1734 // = sp-proximity test hits
1735 // = sp-proximity test generates false-negative
1736 // -- by other
1737 //
1738
1739 Label IsInflated, DONE_LABEL;
1740
1741 // it's stack-locked, biased or neutral
1742 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1743 // order to reduce the number of conditional branches in the most common cases.
1744 // Beware -- there's a subtle invariant that fetch of the markword
1745 // at [FETCH], below, will never observe a biased encoding (*101b).
1746 // If this invariant is not held we risk exclusion (safety) failure.
1747 if (UseBiasedLocking && !UseOptoBiasInlining) {
1748 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1749 }
1750
1751 #if INCLUDE_RTM_OPT
1752 if (UseRTMForStackLocks && use_rtm) {
1753 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1754 stack_rtm_counters, method_data, profile_rtm,
1755 DONE_LABEL, IsInflated);
1756 }
1757 #endif // INCLUDE_RTM_OPT
1758
1759 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1760 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1761 jccb(Assembler::notZero, IsInflated);
1762
1763 // Attempt stack-locking ...
1764 orptr (tmpReg, markOopDesc::unlocked_value);
1765 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1766 if (os::is_MP()) {
1767 lock();
1768 }
1769 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1770 if (counters != NULL) {
1771 cond_inc32(Assembler::equal,
1772 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1773 }
1774 jcc(Assembler::equal, DONE_LABEL); // Success
1775
1776 // Recursive locking.
1777 // The object is stack-locked: markword contains stack pointer to BasicLock.
1778 // Locked by current thread if difference with current SP is less than one page.
1779 subptr(tmpReg, rsp);
1780 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1781 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1782 movptr(Address(boxReg, 0), tmpReg);
1783 if (counters != NULL) {
1784 cond_inc32(Assembler::equal,
1785 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1786 }
1787 jmp(DONE_LABEL);
1788
1789 bind(IsInflated);
1790 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1791
1792 #if INCLUDE_RTM_OPT
1793 // Use the same RTM locking code in 32- and 64-bit VM.
1794 if (use_rtm) {
1795 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1796 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1797 } else {
1798 #endif // INCLUDE_RTM_OPT
1799
1800 #ifndef _LP64
1801 // The object is inflated.
1802
1803 // boxReg refers to the on-stack BasicLock in the current frame.
1804 // We'd like to write:
1805 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1806 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1807 // additional latency as we have another ST in the store buffer that must drain.
1808
1809 if (EmitSync & 8192) {
1810 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1811 get_thread (scrReg);
1812 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1813 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1814 if (os::is_MP()) {
1815 lock();
1816 }
1817 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1818 } else
1819 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1820 // register juggle because we need tmpReg for cmpxchgptr below
1821 movptr(scrReg, boxReg);
1822 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1823
1824 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1825 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1826 // prefetchw [eax + Offset(_owner)-2]
1827 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1828 }
1829
1830 if ((EmitSync & 64) == 0) {
1831 // Optimistic form: consider XORL tmpReg,tmpReg
1832 movptr(tmpReg, NULL_WORD);
1833 } else {
1834 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1835 // Test-And-CAS instead of CAS
1836 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1837 testptr(tmpReg, tmpReg); // Locked ?
1838 jccb (Assembler::notZero, DONE_LABEL);
1839 }
1840
1841 // Appears unlocked - try to swing _owner from null to non-null.
1842 // Ideally, I'd manifest "Self" with get_thread and then attempt
1843 // to CAS the register containing Self into m->Owner.
1844 // But we don't have enough registers, so instead we can either try to CAS
1845 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1846 // we later store "Self" into m->Owner. Transiently storing a stack address
1847 // (rsp or the address of the box) into m->owner is harmless.
1848 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1849 if (os::is_MP()) {
1850 lock();
1851 }
1852 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1853 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1854 // If we weren't able to swing _owner from NULL to the BasicLock
1855 // then take the slow path.
1856 jccb (Assembler::notZero, DONE_LABEL);
1857 // update _owner from BasicLock to thread
1858 get_thread (scrReg); // beware: clobbers ICCs
1859 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1860 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1861
1862 // If the CAS fails we can either retry or pass control to the slow-path.
1863 // We use the latter tactic.
1864 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1865 // If the CAS was successful ...
1866 // Self has acquired the lock
1867 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1868 // Intentional fall-through into DONE_LABEL ...
1869 } else {
1870 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1871 movptr(boxReg, tmpReg);
1872
1873 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1874 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1875 // prefetchw [eax + Offset(_owner)-2]
1876 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1877 }
1878
1879 if ((EmitSync & 64) == 0) {
1880 // Optimistic form
1881 xorptr (tmpReg, tmpReg);
1882 } else {
1883 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1884 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1885 testptr(tmpReg, tmpReg); // Locked ?
1886 jccb (Assembler::notZero, DONE_LABEL);
1887 }
1888
1889 // Appears unlocked - try to swing _owner from null to non-null.
1890 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1891 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1892 get_thread (scrReg);
1893 if (os::is_MP()) {
1894 lock();
1895 }
1896 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1897
1898 // If the CAS fails we can either retry or pass control to the slow-path.
1899 // We use the latter tactic.
1900 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1901 // If the CAS was successful ...
1902 // Self has acquired the lock
1903 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1904 // Intentional fall-through into DONE_LABEL ...
1905 }
1906 #else // _LP64
1907 // It's inflated
1908 movq(scrReg, tmpReg);
1909 xorq(tmpReg, tmpReg);
1910
1911 if (os::is_MP()) {
1912 lock();
1913 }
1914 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1915 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1916 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1917 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1918 // Intentional fall-through into DONE_LABEL ...
1919 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1920 #endif // _LP64
1921 #if INCLUDE_RTM_OPT
1922 } // use_rtm()
1923 #endif
1924 // DONE_LABEL is a hot target - we'd really like to place it at the
1925 // start of cache line by padding with NOPs.
1926 // See the AMD and Intel software optimization manuals for the
1927 // most efficient "long" NOP encodings.
1928 // Unfortunately none of our alignment mechanisms suffice.
1929 bind(DONE_LABEL);
1930
1931 // At DONE_LABEL the icc ZFlag is set as follows ...
1932 // Fast_Unlock uses the same protocol.
1933 // ZFlag == 1 -> Success
1934 // ZFlag == 0 -> Failure - force control through the slow-path
1935 }
1936 }
1937
1938 // obj: object to unlock
1939 // box: box address (displaced header location), killed. Must be EAX.
1940 // tmp: killed, cannot be obj nor box.
1941 //
1942 // Some commentary on balanced locking:
1943 //
1944 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1945 // Methods that don't have provably balanced locking are forced to run in the
1946 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1947 // The interpreter provides two properties:
1948 // I1: At return-time the interpreter automatically and quietly unlocks any
1949 // objects acquired the current activation (frame). Recall that the
1950 // interpreter maintains an on-stack list of locks currently held by
1951 // a frame.
1952 // I2: If a method attempts to unlock an object that is not held by the
1953 // the frame the interpreter throws IMSX.
1954 //
1955 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1956 // B() doesn't have provably balanced locking so it runs in the interpreter.
1957 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1958 // is still locked by A().
1959 //
1960 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1961 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1962 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1963 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1964 // Arguably given that the spec legislates the JNI case as undefined our implementation
1965 // could reasonably *avoid* checking owner in Fast_Unlock().
1966 // In the interest of performance we elide m->Owner==Self check in unlock.
1967 // A perfectly viable alternative is to elide the owner check except when
1968 // Xcheck:jni is enabled.
1969
1970 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1971 assert(boxReg == rax, "");
1972 assert_different_registers(objReg, boxReg, tmpReg);
1973
1974 if (EmitSync & 4) {
1975 // Disable - inhibit all inlining. Force control through the slow-path
1976 cmpptr (rsp, 0);
1977 } else {
1978 Label DONE_LABEL, Stacked, CheckSucc;
1979
1980 // Critically, the biased locking test must have precedence over
1981 // and appear before the (box->dhw == 0) recursive stack-lock test.
1982 if (UseBiasedLocking && !UseOptoBiasInlining) {
1983 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1984 }
1985
1986 #if INCLUDE_RTM_OPT
1987 if (UseRTMForStackLocks && use_rtm) {
1988 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1989 Label L_regular_unlock;
1990 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1991 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1992 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1993 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1994 xend(); // otherwise end...
1995 jmp(DONE_LABEL); // ... and we're done
1996 bind(L_regular_unlock);
1997 }
1998 #endif
1999
2000 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2001 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2002 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2003 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2004 jccb (Assembler::zero, Stacked);
2005
2006 // It's inflated.
2007 #if INCLUDE_RTM_OPT
2008 if (use_rtm) {
2009 Label L_regular_inflated_unlock;
2010 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2011 movptr(boxReg, Address(tmpReg, owner_offset));
2012 testptr(boxReg, boxReg);
2013 jccb(Assembler::notZero, L_regular_inflated_unlock);
2014 xend();
2015 jmpb(DONE_LABEL);
2016 bind(L_regular_inflated_unlock);
2017 }
2018 #endif
2019
2020 // Despite our balanced locking property we still check that m->_owner == Self
2021 // as java routines or native JNI code called by this thread might
2022 // have released the lock.
2023 // Refer to the comments in synchronizer.cpp for how we might encode extra
2024 // state in _succ so we can avoid fetching EntryList|cxq.
2025 //
2026 // I'd like to add more cases in fast_lock() and fast_unlock() --
2027 // such as recursive enter and exit -- but we have to be wary of
2028 // I$ bloat, T$ effects and BP$ effects.
2029 //
2030 // If there's no contention try a 1-0 exit. That is, exit without
2031 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2032 // we detect and recover from the race that the 1-0 exit admits.
2033 //
2034 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2035 // before it STs null into _owner, releasing the lock. Updates
2036 // to data protected by the critical section must be visible before
2037 // we drop the lock (and thus before any other thread could acquire
2038 // the lock and observe the fields protected by the lock).
2039 // IA32's memory-model is SPO, so STs are ordered with respect to
2040 // each other and there's no need for an explicit barrier (fence).
2041 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2042 #ifndef _LP64
2043 get_thread (boxReg);
2044 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2045 // prefetchw [ebx + Offset(_owner)-2]
2046 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2047 }
2048
2049 // Note that we could employ various encoding schemes to reduce
2050 // the number of loads below (currently 4) to just 2 or 3.
2051 // Refer to the comments in synchronizer.cpp.
2052 // In practice the chain of fetches doesn't seem to impact performance, however.
2053 xorptr(boxReg, boxReg);
2054 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2055 // Attempt to reduce branch density - AMD's branch predictor.
2056 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2057 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2058 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2059 jccb (Assembler::notZero, DONE_LABEL);
2060 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2061 jmpb (DONE_LABEL);
2062 } else {
2063 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2064 jccb (Assembler::notZero, DONE_LABEL);
2065 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2066 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2067 jccb (Assembler::notZero, CheckSucc);
2068 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2069 jmpb (DONE_LABEL);
2070 }
2071
2072 // The Following code fragment (EmitSync & 65536) improves the performance of
2073 // contended applications and contended synchronization microbenchmarks.
2074 // Unfortunately the emission of the code - even though not executed - causes regressions
2075 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2076 // with an equal number of never-executed NOPs results in the same regression.
2077 // We leave it off by default.
2078
2079 if ((EmitSync & 65536) != 0) {
2080 Label LSuccess, LGoSlowPath ;
2081
2082 bind (CheckSucc);
2083
2084 // Optional pre-test ... it's safe to elide this
2085 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2086 jccb(Assembler::zero, LGoSlowPath);
2087
2088 // We have a classic Dekker-style idiom:
2089 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2090 // There are a number of ways to implement the barrier:
2091 // (1) lock:andl &m->_owner, 0
2092 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2093 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2094 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2095 // (2) If supported, an explicit MFENCE is appealing.
2096 // In older IA32 processors MFENCE is slower than lock:add or xchg
2097 // particularly if the write-buffer is full as might be the case if
2098 // if stores closely precede the fence or fence-equivalent instruction.
2099 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2100 // as the situation has changed with Nehalem and Shanghai.
2101 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2102 // The $lines underlying the top-of-stack should be in M-state.
2103 // The locked add instruction is serializing, of course.
2104 // (4) Use xchg, which is serializing
2105 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2106 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2107 // The integer condition codes will tell us if succ was 0.
2108 // Since _succ and _owner should reside in the same $line and
2109 // we just stored into _owner, it's likely that the $line
2110 // remains in M-state for the lock:orl.
2111 //
2112 // We currently use (3), although it's likely that switching to (2)
2113 // is correct for the future.
2114
2115 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2116 if (os::is_MP()) {
2117 lock(); addptr(Address(rsp, 0), 0);
2118 }
2119 // Ratify _succ remains non-null
2120 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2121 jccb (Assembler::notZero, LSuccess);
2122
2123 xorptr(boxReg, boxReg); // box is really EAX
2124 if (os::is_MP()) { lock(); }
2125 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2126 // There's no successor so we tried to regrab the lock with the
2127 // placeholder value. If that didn't work, then another thread
2128 // grabbed the lock so we're done (and exit was a success).
2129 jccb (Assembler::notEqual, LSuccess);
2130 // Since we're low on registers we installed rsp as a placeholding in _owner.
2131 // Now install Self over rsp. This is safe as we're transitioning from
2132 // non-null to non=null
2133 get_thread (boxReg);
2134 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2135 // Intentional fall-through into LGoSlowPath ...
2136
2137 bind (LGoSlowPath);
2138 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2139 jmpb (DONE_LABEL);
2140
2141 bind (LSuccess);
2142 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2143 jmpb (DONE_LABEL);
2144 }
2145
2146 bind (Stacked);
2147 // It's not inflated and it's not recursively stack-locked and it's not biased.
2148 // It must be stack-locked.
2149 // Try to reset the header to displaced header.
2150 // The "box" value on the stack is stable, so we can reload
2151 // and be assured we observe the same value as above.
2152 movptr(tmpReg, Address(boxReg, 0));
2153 if (os::is_MP()) {
2154 lock();
2155 }
2156 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2157 // Intention fall-thru into DONE_LABEL
2158
2159 // DONE_LABEL is a hot target - we'd really like to place it at the
2160 // start of cache line by padding with NOPs.
2161 // See the AMD and Intel software optimization manuals for the
2162 // most efficient "long" NOP encodings.
2163 // Unfortunately none of our alignment mechanisms suffice.
2164 if ((EmitSync & 65536) == 0) {
2165 bind (CheckSucc);
2166 }
2167 #else // _LP64
2168 // It's inflated
2169 if (EmitSync & 1024) {
2170 // Emit code to check that _owner == Self
2171 // We could fold the _owner test into subsequent code more efficiently
2172 // than using a stand-alone check, but since _owner checking is off by
2173 // default we don't bother. We also might consider predicating the
2174 // _owner==Self check on Xcheck:jni or running on a debug build.
2175 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2176 xorptr(boxReg, r15_thread);
2177 } else {
2178 xorptr(boxReg, boxReg);
2179 }
2180 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2181 jccb (Assembler::notZero, DONE_LABEL);
2182 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2183 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2184 jccb (Assembler::notZero, CheckSucc);
2185 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2186 jmpb (DONE_LABEL);
2187
2188 if ((EmitSync & 65536) == 0) {
2189 // Try to avoid passing control into the slow_path ...
2190 Label LSuccess, LGoSlowPath ;
2191 bind (CheckSucc);
2192
2193 // The following optional optimization can be elided if necessary
2194 // Effectively: if (succ == null) goto SlowPath
2195 // The code reduces the window for a race, however,
2196 // and thus benefits performance.
2197 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2198 jccb (Assembler::zero, LGoSlowPath);
2199
2200 xorptr(boxReg, boxReg);
2201 if ((EmitSync & 16) && os::is_MP()) {
2202 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2203 } else {
2204 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2205 if (os::is_MP()) {
2206 // Memory barrier/fence
2207 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2208 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2209 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2210 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2211 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2212 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2213 lock(); addl(Address(rsp, 0), 0);
2214 }
2215 }
2216 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2217 jccb (Assembler::notZero, LSuccess);
2218
2219 // Rare inopportune interleaving - race.
2220 // The successor vanished in the small window above.
2221 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2222 // We need to ensure progress and succession.
2223 // Try to reacquire the lock.
2224 // If that fails then the new owner is responsible for succession and this
2225 // thread needs to take no further action and can exit via the fast path (success).
2226 // If the re-acquire succeeds then pass control into the slow path.
2227 // As implemented, this latter mode is horrible because we generated more
2228 // coherence traffic on the lock *and* artifically extended the critical section
2229 // length while by virtue of passing control into the slow path.
2230
2231 // box is really RAX -- the following CMPXCHG depends on that binding
2232 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2233 if (os::is_MP()) { lock(); }
2234 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2235 // There's no successor so we tried to regrab the lock.
2236 // If that didn't work, then another thread grabbed the
2237 // lock so we're done (and exit was a success).
2238 jccb (Assembler::notEqual, LSuccess);
2239 // Intentional fall-through into slow-path
2240
2241 bind (LGoSlowPath);
2242 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2243 jmpb (DONE_LABEL);
2244
2245 bind (LSuccess);
2246 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2247 jmpb (DONE_LABEL);
2248 }
2249
2250 bind (Stacked);
2251 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2252 if (os::is_MP()) { lock(); }
2253 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2254
2255 if (EmitSync & 65536) {
2256 bind (CheckSucc);
2257 }
2258 #endif
2259 bind(DONE_LABEL);
2260 }
2261 }
2262 #endif // COMPILER2
2263
2264 void MacroAssembler::c2bool(Register x) {
2265 // implements x == 0 ? 0 : 1
2266 // note: must only look at least-significant byte of x
2267 // since C-style booleans are stored in one byte
2268 // only! (was bug)
2269 andl(x, 0xFF);
2270 setb(Assembler::notZero, x);
2271 }
2272
2273 // Wouldn't need if AddressLiteral version had new name
2274 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2275 Assembler::call(L, rtype);
2276 }
2277
2278 void MacroAssembler::call(Register entry) {
2279 Assembler::call(entry);
2280 }
2281
2282 void MacroAssembler::call(AddressLiteral entry) {
2283 if (reachable(entry)) {
2284 Assembler::call_literal(entry.target(), entry.rspec());
2285 } else {
2286 lea(rscratch1, entry);
2287 Assembler::call(rscratch1);
2288 }
2289 }
2290
2291 void MacroAssembler::ic_call(address entry, jint method_index) {
2292 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2293 movptr(rax, (intptr_t)Universe::non_oop_word());
2294 call(AddressLiteral(entry, rh));
2295 }
2296
2297 // Implementation of call_VM versions
2298
2299 void MacroAssembler::call_VM(Register oop_result,
2300 address entry_point,
2301 bool check_exceptions) {
2302 Label C, E;
2303 call(C, relocInfo::none);
2304 jmp(E);
2305
2306 bind(C);
2307 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2308 ret(0);
2309
2310 bind(E);
2311 }
2312
2313 void MacroAssembler::call_VM(Register oop_result,
2314 address entry_point,
2315 Register arg_1,
2316 bool check_exceptions) {
2317 Label C, E;
2318 call(C, relocInfo::none);
2319 jmp(E);
2320
2321 bind(C);
2322 pass_arg1(this, arg_1);
2323 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2324 ret(0);
2325
2326 bind(E);
2327 }
2328
2329 void MacroAssembler::call_VM(Register oop_result,
2330 address entry_point,
2331 Register arg_1,
2332 Register arg_2,
2333 bool check_exceptions) {
2334 Label C, E;
2335 call(C, relocInfo::none);
2336 jmp(E);
2337
2338 bind(C);
2339
2340 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2341
2342 pass_arg2(this, arg_2);
2343 pass_arg1(this, arg_1);
2344 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2345 ret(0);
2346
2347 bind(E);
2348 }
2349
2350 void MacroAssembler::call_VM(Register oop_result,
2351 address entry_point,
2352 Register arg_1,
2353 Register arg_2,
2354 Register arg_3,
2355 bool check_exceptions) {
2356 Label C, E;
2357 call(C, relocInfo::none);
2358 jmp(E);
2359
2360 bind(C);
2361
2362 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2363 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2364 pass_arg3(this, arg_3);
2365
2366 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2367 pass_arg2(this, arg_2);
2368
2369 pass_arg1(this, arg_1);
2370 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2371 ret(0);
2372
2373 bind(E);
2374 }
2375
2376 void MacroAssembler::call_VM(Register oop_result,
2377 Register last_java_sp,
2378 address entry_point,
2379 int number_of_arguments,
2380 bool check_exceptions) {
2381 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2382 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2383 }
2384
2385 void MacroAssembler::call_VM(Register oop_result,
2386 Register last_java_sp,
2387 address entry_point,
2388 Register arg_1,
2389 bool check_exceptions) {
2390 pass_arg1(this, arg_1);
2391 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2392 }
2393
2394 void MacroAssembler::call_VM(Register oop_result,
2395 Register last_java_sp,
2396 address entry_point,
2397 Register arg_1,
2398 Register arg_2,
2399 bool check_exceptions) {
2400
2401 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2402 pass_arg2(this, arg_2);
2403 pass_arg1(this, arg_1);
2404 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2405 }
2406
2407 void MacroAssembler::call_VM(Register oop_result,
2408 Register last_java_sp,
2409 address entry_point,
2410 Register arg_1,
2411 Register arg_2,
2412 Register arg_3,
2413 bool check_exceptions) {
2414 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2415 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2416 pass_arg3(this, arg_3);
2417 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2418 pass_arg2(this, arg_2);
2419 pass_arg1(this, arg_1);
2420 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2421 }
2422
2423 void MacroAssembler::super_call_VM(Register oop_result,
2424 Register last_java_sp,
2425 address entry_point,
2426 int number_of_arguments,
2427 bool check_exceptions) {
2428 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2429 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2430 }
2431
2432 void MacroAssembler::super_call_VM(Register oop_result,
2433 Register last_java_sp,
2434 address entry_point,
2435 Register arg_1,
2436 bool check_exceptions) {
2437 pass_arg1(this, arg_1);
2438 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2439 }
2440
2441 void MacroAssembler::super_call_VM(Register oop_result,
2442 Register last_java_sp,
2443 address entry_point,
2444 Register arg_1,
2445 Register arg_2,
2446 bool check_exceptions) {
2447
2448 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2449 pass_arg2(this, arg_2);
2450 pass_arg1(this, arg_1);
2451 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2452 }
2453
2454 void MacroAssembler::super_call_VM(Register oop_result,
2455 Register last_java_sp,
2456 address entry_point,
2457 Register arg_1,
2458 Register arg_2,
2459 Register arg_3,
2460 bool check_exceptions) {
2461 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2462 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2463 pass_arg3(this, arg_3);
2464 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2465 pass_arg2(this, arg_2);
2466 pass_arg1(this, arg_1);
2467 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2468 }
2469
2470 void MacroAssembler::call_VM_base(Register oop_result,
2471 Register java_thread,
2472 Register last_java_sp,
2473 address entry_point,
2474 int number_of_arguments,
2475 bool check_exceptions) {
2476 // determine java_thread register
2477 if (!java_thread->is_valid()) {
2478 #ifdef _LP64
2479 java_thread = r15_thread;
2480 #else
2481 java_thread = rdi;
2482 get_thread(java_thread);
2483 #endif // LP64
2484 }
2485 // determine last_java_sp register
2486 if (!last_java_sp->is_valid()) {
2487 last_java_sp = rsp;
2488 }
2489 // debugging support
2490 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2491 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2492 #ifdef ASSERT
2493 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2494 // r12 is the heapbase.
2495 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2496 #endif // ASSERT
2497
2498 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2499 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2500
2501 // push java thread (becomes first argument of C function)
2502
2503 NOT_LP64(push(java_thread); number_of_arguments++);
2504 LP64_ONLY(mov(c_rarg0, r15_thread));
2505
2506 // set last Java frame before call
2507 assert(last_java_sp != rbp, "can't use ebp/rbp");
2508
2509 // Only interpreter should have to set fp
2510 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2511
2512 // do the call, remove parameters
2513 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2514
2515 // restore the thread (cannot use the pushed argument since arguments
2516 // may be overwritten by C code generated by an optimizing compiler);
2517 // however can use the register value directly if it is callee saved.
2518 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2519 // rdi & rsi (also r15) are callee saved -> nothing to do
2520 #ifdef ASSERT
2521 guarantee(java_thread != rax, "change this code");
2522 push(rax);
2523 { Label L;
2524 get_thread(rax);
2525 cmpptr(java_thread, rax);
2526 jcc(Assembler::equal, L);
2527 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2528 bind(L);
2529 }
2530 pop(rax);
2531 #endif
2532 } else {
2533 get_thread(java_thread);
2534 }
2535 // reset last Java frame
2536 // Only interpreter should have to clear fp
2537 reset_last_Java_frame(java_thread, true);
2538
2539 // C++ interp handles this in the interpreter
2540 check_and_handle_popframe(java_thread);
2541 check_and_handle_earlyret(java_thread);
2542
2543 if (check_exceptions) {
2544 // check for pending exceptions (java_thread is set upon return)
2545 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2546 #ifndef _LP64
2547 jump_cc(Assembler::notEqual,
2548 RuntimeAddress(StubRoutines::forward_exception_entry()));
2549 #else
2550 // This used to conditionally jump to forward_exception however it is
2551 // possible if we relocate that the branch will not reach. So we must jump
2552 // around so we can always reach
2553
2554 Label ok;
2555 jcc(Assembler::equal, ok);
2556 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2557 bind(ok);
2558 #endif // LP64
2559 }
2560
2561 // get oop result if there is one and reset the value in the thread
2562 if (oop_result->is_valid()) {
2563 get_vm_result(oop_result, java_thread);
2564 }
2565 }
2566
2567 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2568
2569 // Calculate the value for last_Java_sp
2570 // somewhat subtle. call_VM does an intermediate call
2571 // which places a return address on the stack just under the
2572 // stack pointer as the user finsihed with it. This allows
2573 // use to retrieve last_Java_pc from last_Java_sp[-1].
2574 // On 32bit we then have to push additional args on the stack to accomplish
2575 // the actual requested call. On 64bit call_VM only can use register args
2576 // so the only extra space is the return address that call_VM created.
2577 // This hopefully explains the calculations here.
2578
2579 #ifdef _LP64
2580 // We've pushed one address, correct last_Java_sp
2581 lea(rax, Address(rsp, wordSize));
2582 #else
2583 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2584 #endif // LP64
2585
2586 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2587
2588 }
2589
2590 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2591 void MacroAssembler::call_VM_leaf0(address entry_point) {
2592 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2593 }
2594
2595 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2596 call_VM_leaf_base(entry_point, number_of_arguments);
2597 }
2598
2599 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2600 pass_arg0(this, arg_0);
2601 call_VM_leaf(entry_point, 1);
2602 }
2603
2604 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2605
2606 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2607 pass_arg1(this, arg_1);
2608 pass_arg0(this, arg_0);
2609 call_VM_leaf(entry_point, 2);
2610 }
2611
2612 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2613 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2614 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2615 pass_arg2(this, arg_2);
2616 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2617 pass_arg1(this, arg_1);
2618 pass_arg0(this, arg_0);
2619 call_VM_leaf(entry_point, 3);
2620 }
2621
2622 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2623 pass_arg0(this, arg_0);
2624 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2625 }
2626
2627 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2628
2629 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2630 pass_arg1(this, arg_1);
2631 pass_arg0(this, arg_0);
2632 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2633 }
2634
2635 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2636 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2637 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2638 pass_arg2(this, arg_2);
2639 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2640 pass_arg1(this, arg_1);
2641 pass_arg0(this, arg_0);
2642 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2643 }
2644
2645 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2646 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2647 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2648 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2649 pass_arg3(this, arg_3);
2650 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2651 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2652 pass_arg2(this, arg_2);
2653 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2654 pass_arg1(this, arg_1);
2655 pass_arg0(this, arg_0);
2656 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2657 }
2658
2659 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2660 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2661 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2662 verify_oop(oop_result, "broken oop in call_VM_base");
2663 }
2664
2665 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2666 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2667 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2668 }
2669
2670 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2671 }
2672
2673 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2674 }
2675
2676 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2677 if (reachable(src1)) {
2678 cmpl(as_Address(src1), imm);
2679 } else {
2680 lea(rscratch1, src1);
2681 cmpl(Address(rscratch1, 0), imm);
2682 }
2683 }
2684
2685 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2686 assert(!src2.is_lval(), "use cmpptr");
2687 if (reachable(src2)) {
2688 cmpl(src1, as_Address(src2));
2689 } else {
2690 lea(rscratch1, src2);
2691 cmpl(src1, Address(rscratch1, 0));
2692 }
2693 }
2694
2695 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2696 Assembler::cmpl(src1, imm);
2697 }
2698
2699 void MacroAssembler::cmp32(Register src1, Address src2) {
2700 Assembler::cmpl(src1, src2);
2701 }
2702
2703 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2704 ucomisd(opr1, opr2);
2705
2706 Label L;
2707 if (unordered_is_less) {
2708 movl(dst, -1);
2709 jcc(Assembler::parity, L);
2710 jcc(Assembler::below , L);
2711 movl(dst, 0);
2712 jcc(Assembler::equal , L);
2713 increment(dst);
2714 } else { // unordered is greater
2715 movl(dst, 1);
2716 jcc(Assembler::parity, L);
2717 jcc(Assembler::above , L);
2718 movl(dst, 0);
2719 jcc(Assembler::equal , L);
2720 decrementl(dst);
2721 }
2722 bind(L);
2723 }
2724
2725 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2726 ucomiss(opr1, opr2);
2727
2728 Label L;
2729 if (unordered_is_less) {
2730 movl(dst, -1);
2731 jcc(Assembler::parity, L);
2732 jcc(Assembler::below , L);
2733 movl(dst, 0);
2734 jcc(Assembler::equal , L);
2735 increment(dst);
2736 } else { // unordered is greater
2737 movl(dst, 1);
2738 jcc(Assembler::parity, L);
2739 jcc(Assembler::above , L);
2740 movl(dst, 0);
2741 jcc(Assembler::equal , L);
2742 decrementl(dst);
2743 }
2744 bind(L);
2745 }
2746
2747
2748 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2749 if (reachable(src1)) {
2750 cmpb(as_Address(src1), imm);
2751 } else {
2752 lea(rscratch1, src1);
2753 cmpb(Address(rscratch1, 0), imm);
2754 }
2755 }
2756
2757 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2758 #ifdef _LP64
2759 if (src2.is_lval()) {
2760 movptr(rscratch1, src2);
2761 Assembler::cmpq(src1, rscratch1);
2762 } else if (reachable(src2)) {
2763 cmpq(src1, as_Address(src2));
2764 } else {
2765 lea(rscratch1, src2);
2766 Assembler::cmpq(src1, Address(rscratch1, 0));
2767 }
2768 #else
2769 if (src2.is_lval()) {
2770 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2771 } else {
2772 cmpl(src1, as_Address(src2));
2773 }
2774 #endif // _LP64
2775 }
2776
2777 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2778 assert(src2.is_lval(), "not a mem-mem compare");
2779 #ifdef _LP64
2780 // moves src2's literal address
2781 movptr(rscratch1, src2);
2782 Assembler::cmpq(src1, rscratch1);
2783 #else
2784 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2785 #endif // _LP64
2786 }
2787
2788 void MacroAssembler::cmpoop(Register src1, Register src2) {
2789 cmpptr(src1, src2);
2790 }
2791
2792 void MacroAssembler::cmpoop(Register src1, Address src2) {
2793 cmpptr(src1, src2);
2794 }
2795
2796 #ifdef _LP64
2797 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2798 movoop(rscratch1, src2);
2799 cmpptr(src1, rscratch1);
2800 }
2801 #endif
2802
2803 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2804 if (reachable(adr)) {
2805 if (os::is_MP())
2806 lock();
2807 cmpxchgptr(reg, as_Address(adr));
2808 } else {
2809 lea(rscratch1, adr);
2810 if (os::is_MP())
2811 lock();
2812 cmpxchgptr(reg, Address(rscratch1, 0));
2813 }
2814 }
2815
2816 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2817 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2818 }
2819
2820 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2821 if (reachable(src)) {
2822 Assembler::comisd(dst, as_Address(src));
2823 } else {
2824 lea(rscratch1, src);
2825 Assembler::comisd(dst, Address(rscratch1, 0));
2826 }
2827 }
2828
2829 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2830 if (reachable(src)) {
2831 Assembler::comiss(dst, as_Address(src));
2832 } else {
2833 lea(rscratch1, src);
2834 Assembler::comiss(dst, Address(rscratch1, 0));
2835 }
2836 }
2837
2838
2839 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2840 Condition negated_cond = negate_condition(cond);
2841 Label L;
2842 jcc(negated_cond, L);
2843 pushf(); // Preserve flags
2844 atomic_incl(counter_addr);
2845 popf();
2846 bind(L);
2847 }
2848
2849 int MacroAssembler::corrected_idivl(Register reg) {
2850 // Full implementation of Java idiv and irem; checks for
2851 // special case as described in JVM spec., p.243 & p.271.
2852 // The function returns the (pc) offset of the idivl
2853 // instruction - may be needed for implicit exceptions.
2854 //
2855 // normal case special case
2856 //
2857 // input : rax,: dividend min_int
2858 // reg: divisor (may not be rax,/rdx) -1
2859 //
2860 // output: rax,: quotient (= rax, idiv reg) min_int
2861 // rdx: remainder (= rax, irem reg) 0
2862 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2863 const int min_int = 0x80000000;
2864 Label normal_case, special_case;
2865
2866 // check for special case
2867 cmpl(rax, min_int);
2868 jcc(Assembler::notEqual, normal_case);
2869 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2870 cmpl(reg, -1);
2871 jcc(Assembler::equal, special_case);
2872
2873 // handle normal case
2874 bind(normal_case);
2875 cdql();
2876 int idivl_offset = offset();
2877 idivl(reg);
2878
2879 // normal and special case exit
2880 bind(special_case);
2881
2882 return idivl_offset;
2883 }
2884
2885
2886
2887 void MacroAssembler::decrementl(Register reg, int value) {
2888 if (value == min_jint) {subl(reg, value) ; return; }
2889 if (value < 0) { incrementl(reg, -value); return; }
2890 if (value == 0) { ; return; }
2891 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2892 /* else */ { subl(reg, value) ; return; }
2893 }
2894
2895 void MacroAssembler::decrementl(Address dst, int value) {
2896 if (value == min_jint) {subl(dst, value) ; return; }
2897 if (value < 0) { incrementl(dst, -value); return; }
2898 if (value == 0) { ; return; }
2899 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2900 /* else */ { subl(dst, value) ; return; }
2901 }
2902
2903 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2904 assert (shift_value > 0, "illegal shift value");
2905 Label _is_positive;
2906 testl (reg, reg);
2907 jcc (Assembler::positive, _is_positive);
2908 int offset = (1 << shift_value) - 1 ;
2909
2910 if (offset == 1) {
2911 incrementl(reg);
2912 } else {
2913 addl(reg, offset);
2914 }
2915
2916 bind (_is_positive);
2917 sarl(reg, shift_value);
2918 }
2919
2920 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2921 if (reachable(src)) {
2922 Assembler::divsd(dst, as_Address(src));
2923 } else {
2924 lea(rscratch1, src);
2925 Assembler::divsd(dst, Address(rscratch1, 0));
2926 }
2927 }
2928
2929 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2930 if (reachable(src)) {
2931 Assembler::divss(dst, as_Address(src));
2932 } else {
2933 lea(rscratch1, src);
2934 Assembler::divss(dst, Address(rscratch1, 0));
2935 }
2936 }
2937
2938 // !defined(COMPILER2) is because of stupid core builds
2939 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2940 void MacroAssembler::empty_FPU_stack() {
2941 if (VM_Version::supports_mmx()) {
2942 emms();
2943 } else {
2944 for (int i = 8; i-- > 0; ) ffree(i);
2945 }
2946 }
2947 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2948
2949
2950 // Defines obj, preserves var_size_in_bytes
2951 void MacroAssembler::eden_allocate(Register obj,
2952 Register var_size_in_bytes,
2953 int con_size_in_bytes,
2954 Register t1,
2955 Label& slow_case) {
2956 assert(obj == rax, "obj must be in rax, for cmpxchg");
2957 assert_different_registers(obj, var_size_in_bytes, t1);
2958 if (!Universe::heap()->supports_inline_contig_alloc()) {
2959 jmp(slow_case);
2960 } else {
2961 Register end = t1;
2962 Label retry;
2963 bind(retry);
2964 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2965 movptr(obj, heap_top);
2966 if (var_size_in_bytes == noreg) {
2967 lea(end, Address(obj, con_size_in_bytes));
2968 } else {
2969 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2970 }
2971 // if end < obj then we wrapped around => object too long => slow case
2972 cmpptr(end, obj);
2973 jcc(Assembler::below, slow_case);
2974 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2975 jcc(Assembler::above, slow_case);
2976 // Compare obj with the top addr, and if still equal, store the new top addr in
2977 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2978 // it otherwise. Use lock prefix for atomicity on MPs.
2979 locked_cmpxchgptr(end, heap_top);
2980 jcc(Assembler::notEqual, retry);
2981 }
2982 }
2983
2984 void MacroAssembler::enter() {
2985 push(rbp);
2986 mov(rbp, rsp);
2987 }
2988
2989 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2990 void MacroAssembler::fat_nop() {
2991 if (UseAddressNop) {
2992 addr_nop_5();
2993 } else {
2994 emit_int8(0x26); // es:
2995 emit_int8(0x2e); // cs:
2996 emit_int8(0x64); // fs:
2997 emit_int8(0x65); // gs:
2998 emit_int8((unsigned char)0x90);
2999 }
3000 }
3001
3002 void MacroAssembler::fcmp(Register tmp) {
3003 fcmp(tmp, 1, true, true);
3004 }
3005
3006 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
3007 assert(!pop_right || pop_left, "usage error");
3008 if (VM_Version::supports_cmov()) {
3009 assert(tmp == noreg, "unneeded temp");
3010 if (pop_left) {
3011 fucomip(index);
3012 } else {
3013 fucomi(index);
3014 }
3015 if (pop_right) {
3016 fpop();
3017 }
3018 } else {
3019 assert(tmp != noreg, "need temp");
3020 if (pop_left) {
3021 if (pop_right) {
3022 fcompp();
3023 } else {
3024 fcomp(index);
3025 }
3026 } else {
3027 fcom(index);
3028 }
3029 // convert FPU condition into eflags condition via rax,
3030 save_rax(tmp);
3031 fwait(); fnstsw_ax();
3032 sahf();
3033 restore_rax(tmp);
3034 }
3035 // condition codes set as follows:
3036 //
3037 // CF (corresponds to C0) if x < y
3038 // PF (corresponds to C2) if unordered
3039 // ZF (corresponds to C3) if x = y
3040 }
3041
3042 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3043 fcmp2int(dst, unordered_is_less, 1, true, true);
3044 }
3045
3046 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3047 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3048 Label L;
3049 if (unordered_is_less) {
3050 movl(dst, -1);
3051 jcc(Assembler::parity, L);
3052 jcc(Assembler::below , L);
3053 movl(dst, 0);
3054 jcc(Assembler::equal , L);
3055 increment(dst);
3056 } else { // unordered is greater
3057 movl(dst, 1);
3058 jcc(Assembler::parity, L);
3059 jcc(Assembler::above , L);
3060 movl(dst, 0);
3061 jcc(Assembler::equal , L);
3062 decrementl(dst);
3063 }
3064 bind(L);
3065 }
3066
3067 void MacroAssembler::fld_d(AddressLiteral src) {
3068 fld_d(as_Address(src));
3069 }
3070
3071 void MacroAssembler::fld_s(AddressLiteral src) {
3072 fld_s(as_Address(src));
3073 }
3074
3075 void MacroAssembler::fld_x(AddressLiteral src) {
3076 Assembler::fld_x(as_Address(src));
3077 }
3078
3079 void MacroAssembler::fldcw(AddressLiteral src) {
3080 Assembler::fldcw(as_Address(src));
3081 }
3082
3083 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3084 if (reachable(src)) {
3085 Assembler::mulpd(dst, as_Address(src));
3086 } else {
3087 lea(rscratch1, src);
3088 Assembler::mulpd(dst, Address(rscratch1, 0));
3089 }
3090 }
3091
3092 void MacroAssembler::increase_precision() {
3093 subptr(rsp, BytesPerWord);
3094 fnstcw(Address(rsp, 0));
3095 movl(rax, Address(rsp, 0));
3096 orl(rax, 0x300);
3097 push(rax);
3098 fldcw(Address(rsp, 0));
3099 pop(rax);
3100 }
3101
3102 void MacroAssembler::restore_precision() {
3103 fldcw(Address(rsp, 0));
3104 addptr(rsp, BytesPerWord);
3105 }
3106
3107 void MacroAssembler::fpop() {
3108 ffree();
3109 fincstp();
3110 }
3111
3112 void MacroAssembler::load_float(Address src) {
3113 if (UseSSE >= 1) {
3114 movflt(xmm0, src);
3115 } else {
3116 LP64_ONLY(ShouldNotReachHere());
3117 NOT_LP64(fld_s(src));
3118 }
3119 }
3120
3121 void MacroAssembler::store_float(Address dst) {
3122 if (UseSSE >= 1) {
3123 movflt(dst, xmm0);
3124 } else {
3125 LP64_ONLY(ShouldNotReachHere());
3126 NOT_LP64(fstp_s(dst));
3127 }
3128 }
3129
3130 void MacroAssembler::load_double(Address src) {
3131 if (UseSSE >= 2) {
3132 movdbl(xmm0, src);
3133 } else {
3134 LP64_ONLY(ShouldNotReachHere());
3135 NOT_LP64(fld_d(src));
3136 }
3137 }
3138
3139 void MacroAssembler::store_double(Address dst) {
3140 if (UseSSE >= 2) {
3141 movdbl(dst, xmm0);
3142 } else {
3143 LP64_ONLY(ShouldNotReachHere());
3144 NOT_LP64(fstp_d(dst));
3145 }
3146 }
3147
3148 void MacroAssembler::fremr(Register tmp) {
3149 save_rax(tmp);
3150 { Label L;
3151 bind(L);
3152 fprem();
3153 fwait(); fnstsw_ax();
3154 #ifdef _LP64
3155 testl(rax, 0x400);
3156 jcc(Assembler::notEqual, L);
3157 #else
3158 sahf();
3159 jcc(Assembler::parity, L);
3160 #endif // _LP64
3161 }
3162 restore_rax(tmp);
3163 // Result is in ST0.
3164 // Note: fxch & fpop to get rid of ST1
3165 // (otherwise FPU stack could overflow eventually)
3166 fxch(1);
3167 fpop();
3168 }
3169
3170 // dst = c = a * b + c
3171 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3172 Assembler::vfmadd231sd(c, a, b);
3173 if (dst != c) {
3174 movdbl(dst, c);
3175 }
3176 }
3177
3178 // dst = c = a * b + c
3179 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3180 Assembler::vfmadd231ss(c, a, b);
3181 if (dst != c) {
3182 movflt(dst, c);
3183 }
3184 }
3185
3186 // dst = c = a * b + c
3187 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3188 Assembler::vfmadd231pd(c, a, b, vector_len);
3189 if (dst != c) {
3190 vmovdqu(dst, c);
3191 }
3192 }
3193
3194 // dst = c = a * b + c
3195 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3196 Assembler::vfmadd231ps(c, a, b, vector_len);
3197 if (dst != c) {
3198 vmovdqu(dst, c);
3199 }
3200 }
3201
3202 // dst = c = a * b + c
3203 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3204 Assembler::vfmadd231pd(c, a, b, vector_len);
3205 if (dst != c) {
3206 vmovdqu(dst, c);
3207 }
3208 }
3209
3210 // dst = c = a * b + c
3211 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3212 Assembler::vfmadd231ps(c, a, b, vector_len);
3213 if (dst != c) {
3214 vmovdqu(dst, c);
3215 }
3216 }
3217
3218 void MacroAssembler::incrementl(AddressLiteral dst) {
3219 if (reachable(dst)) {
3220 incrementl(as_Address(dst));
3221 } else {
3222 lea(rscratch1, dst);
3223 incrementl(Address(rscratch1, 0));
3224 }
3225 }
3226
3227 void MacroAssembler::incrementl(ArrayAddress dst) {
3228 incrementl(as_Address(dst));
3229 }
3230
3231 void MacroAssembler::incrementl(Register reg, int value) {
3232 if (value == min_jint) {addl(reg, value) ; return; }
3233 if (value < 0) { decrementl(reg, -value); return; }
3234 if (value == 0) { ; return; }
3235 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3236 /* else */ { addl(reg, value) ; return; }
3237 }
3238
3239 void MacroAssembler::incrementl(Address dst, int value) {
3240 if (value == min_jint) {addl(dst, value) ; return; }
3241 if (value < 0) { decrementl(dst, -value); return; }
3242 if (value == 0) { ; return; }
3243 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3244 /* else */ { addl(dst, value) ; return; }
3245 }
3246
3247 void MacroAssembler::jump(AddressLiteral dst) {
3248 if (reachable(dst)) {
3249 jmp_literal(dst.target(), dst.rspec());
3250 } else {
3251 lea(rscratch1, dst);
3252 jmp(rscratch1);
3253 }
3254 }
3255
3256 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3257 if (reachable(dst)) {
3258 InstructionMark im(this);
3259 relocate(dst.reloc());
3260 const int short_size = 2;
3261 const int long_size = 6;
3262 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3263 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3264 // 0111 tttn #8-bit disp
3265 emit_int8(0x70 | cc);
3266 emit_int8((offs - short_size) & 0xFF);
3267 } else {
3268 // 0000 1111 1000 tttn #32-bit disp
3269 emit_int8(0x0F);
3270 emit_int8((unsigned char)(0x80 | cc));
3271 emit_int32(offs - long_size);
3272 }
3273 } else {
3274 #ifdef ASSERT
3275 warning("reversing conditional branch");
3276 #endif /* ASSERT */
3277 Label skip;
3278 jccb(reverse[cc], skip);
3279 lea(rscratch1, dst);
3280 Assembler::jmp(rscratch1);
3281 bind(skip);
3282 }
3283 }
3284
3285 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3286 if (reachable(src)) {
3287 Assembler::ldmxcsr(as_Address(src));
3288 } else {
3289 lea(rscratch1, src);
3290 Assembler::ldmxcsr(Address(rscratch1, 0));
3291 }
3292 }
3293
3294 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3295 int off;
3296 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3297 off = offset();
3298 movsbl(dst, src); // movsxb
3299 } else {
3300 off = load_unsigned_byte(dst, src);
3301 shll(dst, 24);
3302 sarl(dst, 24);
3303 }
3304 return off;
3305 }
3306
3307 // Note: load_signed_short used to be called load_signed_word.
3308 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3309 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3310 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3311 int MacroAssembler::load_signed_short(Register dst, Address src) {
3312 int off;
3313 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3314 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3315 // version but this is what 64bit has always done. This seems to imply
3316 // that users are only using 32bits worth.
3317 off = offset();
3318 movswl(dst, src); // movsxw
3319 } else {
3320 off = load_unsigned_short(dst, src);
3321 shll(dst, 16);
3322 sarl(dst, 16);
3323 }
3324 return off;
3325 }
3326
3327 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3328 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3329 // and "3.9 Partial Register Penalties", p. 22).
3330 int off;
3331 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3332 off = offset();
3333 movzbl(dst, src); // movzxb
3334 } else {
3335 xorl(dst, dst);
3336 off = offset();
3337 movb(dst, src);
3338 }
3339 return off;
3340 }
3341
3342 // Note: load_unsigned_short used to be called load_unsigned_word.
3343 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3344 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3345 // and "3.9 Partial Register Penalties", p. 22).
3346 int off;
3347 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3348 off = offset();
3349 movzwl(dst, src); // movzxw
3350 } else {
3351 xorl(dst, dst);
3352 off = offset();
3353 movw(dst, src);
3354 }
3355 return off;
3356 }
3357
3358 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3359 switch (size_in_bytes) {
3360 #ifndef _LP64
3361 case 8:
3362 assert(dst2 != noreg, "second dest register required");
3363 movl(dst, src);
3364 movl(dst2, src.plus_disp(BytesPerInt));
3365 break;
3366 #else
3367 case 8: movq(dst, src); break;
3368 #endif
3369 case 4: movl(dst, src); break;
3370 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3371 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3372 default: ShouldNotReachHere();
3373 }
3374 }
3375
3376 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3377 switch (size_in_bytes) {
3378 #ifndef _LP64
3379 case 8:
3380 assert(src2 != noreg, "second source register required");
3381 movl(dst, src);
3382 movl(dst.plus_disp(BytesPerInt), src2);
3383 break;
3384 #else
3385 case 8: movq(dst, src); break;
3386 #endif
3387 case 4: movl(dst, src); break;
3388 case 2: movw(dst, src); break;
3389 case 1: movb(dst, src); break;
3390 default: ShouldNotReachHere();
3391 }
3392 }
3393
3394 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3395 if (reachable(dst)) {
3396 movl(as_Address(dst), src);
3397 } else {
3398 lea(rscratch1, dst);
3399 movl(Address(rscratch1, 0), src);
3400 }
3401 }
3402
3403 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3404 if (reachable(src)) {
3405 movl(dst, as_Address(src));
3406 } else {
3407 lea(rscratch1, src);
3408 movl(dst, Address(rscratch1, 0));
3409 }
3410 }
3411
3412 // C++ bool manipulation
3413
3414 void MacroAssembler::movbool(Register dst, Address src) {
3415 if(sizeof(bool) == 1)
3416 movb(dst, src);
3417 else if(sizeof(bool) == 2)
3418 movw(dst, src);
3419 else if(sizeof(bool) == 4)
3420 movl(dst, src);
3421 else
3422 // unsupported
3423 ShouldNotReachHere();
3424 }
3425
3426 void MacroAssembler::movbool(Address dst, bool boolconst) {
3427 if(sizeof(bool) == 1)
3428 movb(dst, (int) boolconst);
3429 else if(sizeof(bool) == 2)
3430 movw(dst, (int) boolconst);
3431 else if(sizeof(bool) == 4)
3432 movl(dst, (int) boolconst);
3433 else
3434 // unsupported
3435 ShouldNotReachHere();
3436 }
3437
3438 void MacroAssembler::movbool(Address dst, Register src) {
3439 if(sizeof(bool) == 1)
3440 movb(dst, src);
3441 else if(sizeof(bool) == 2)
3442 movw(dst, src);
3443 else if(sizeof(bool) == 4)
3444 movl(dst, src);
3445 else
3446 // unsupported
3447 ShouldNotReachHere();
3448 }
3449
3450 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3451 movb(as_Address(dst), src);
3452 }
3453
3454 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3455 if (reachable(src)) {
3456 movdl(dst, as_Address(src));
3457 } else {
3458 lea(rscratch1, src);
3459 movdl(dst, Address(rscratch1, 0));
3460 }
3461 }
3462
3463 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3464 if (reachable(src)) {
3465 movq(dst, as_Address(src));
3466 } else {
3467 lea(rscratch1, src);
3468 movq(dst, Address(rscratch1, 0));
3469 }
3470 }
3471
3472 void MacroAssembler::setvectmask(Register dst, Register src) {
3473 Assembler::movl(dst, 1);
3474 Assembler::shlxl(dst, dst, src);
3475 Assembler::decl(dst);
3476 Assembler::kmovdl(k1, dst);
3477 Assembler::movl(dst, src);
3478 }
3479
3480 void MacroAssembler::restorevectmask() {
3481 Assembler::knotwl(k1, k0);
3482 }
3483
3484 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3485 if (reachable(src)) {
3486 if (UseXmmLoadAndClearUpper) {
3487 movsd (dst, as_Address(src));
3488 } else {
3489 movlpd(dst, as_Address(src));
3490 }
3491 } else {
3492 lea(rscratch1, src);
3493 if (UseXmmLoadAndClearUpper) {
3494 movsd (dst, Address(rscratch1, 0));
3495 } else {
3496 movlpd(dst, Address(rscratch1, 0));
3497 }
3498 }
3499 }
3500
3501 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3502 if (reachable(src)) {
3503 movss(dst, as_Address(src));
3504 } else {
3505 lea(rscratch1, src);
3506 movss(dst, Address(rscratch1, 0));
3507 }
3508 }
3509
3510 void MacroAssembler::movptr(Register dst, Register src) {
3511 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3512 }
3513
3514 void MacroAssembler::movptr(Register dst, Address src) {
3515 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3516 }
3517
3518 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3519 void MacroAssembler::movptr(Register dst, intptr_t src) {
3520 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3521 }
3522
3523 void MacroAssembler::movptr(Address dst, Register src) {
3524 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3525 }
3526
3527 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3528 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3529 Assembler::vextractf32x4(dst, src, 0);
3530 } else {
3531 Assembler::movdqu(dst, src);
3532 }
3533 }
3534
3535 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3536 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3537 Assembler::vinsertf32x4(dst, dst, src, 0);
3538 } else {
3539 Assembler::movdqu(dst, src);
3540 }
3541 }
3542
3543 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3544 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3545 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3546 } else {
3547 Assembler::movdqu(dst, src);
3548 }
3549 }
3550
3551 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3552 if (reachable(src)) {
3553 movdqu(dst, as_Address(src));
3554 } else {
3555 lea(scratchReg, src);
3556 movdqu(dst, Address(scratchReg, 0));
3557 }
3558 }
3559
3560 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3561 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3562 vextractf64x4_low(dst, src);
3563 } else {
3564 Assembler::vmovdqu(dst, src);
3565 }
3566 }
3567
3568 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3569 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3570 vinsertf64x4_low(dst, src);
3571 } else {
3572 Assembler::vmovdqu(dst, src);
3573 }
3574 }
3575
3576 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3577 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3578 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3579 }
3580 else {
3581 Assembler::vmovdqu(dst, src);
3582 }
3583 }
3584
3585 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3586 if (reachable(src)) {
3587 vmovdqu(dst, as_Address(src));
3588 }
3589 else {
3590 lea(rscratch1, src);
3591 vmovdqu(dst, Address(rscratch1, 0));
3592 }
3593 }
3594
3595 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3596 if (reachable(src)) {
3597 Assembler::movdqa(dst, as_Address(src));
3598 } else {
3599 lea(rscratch1, src);
3600 Assembler::movdqa(dst, Address(rscratch1, 0));
3601 }
3602 }
3603
3604 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3605 if (reachable(src)) {
3606 Assembler::movsd(dst, as_Address(src));
3607 } else {
3608 lea(rscratch1, src);
3609 Assembler::movsd(dst, Address(rscratch1, 0));
3610 }
3611 }
3612
3613 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3614 if (reachable(src)) {
3615 Assembler::movss(dst, as_Address(src));
3616 } else {
3617 lea(rscratch1, src);
3618 Assembler::movss(dst, Address(rscratch1, 0));
3619 }
3620 }
3621
3622 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3623 if (reachable(src)) {
3624 Assembler::mulsd(dst, as_Address(src));
3625 } else {
3626 lea(rscratch1, src);
3627 Assembler::mulsd(dst, Address(rscratch1, 0));
3628 }
3629 }
3630
3631 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3632 if (reachable(src)) {
3633 Assembler::mulss(dst, as_Address(src));
3634 } else {
3635 lea(rscratch1, src);
3636 Assembler::mulss(dst, Address(rscratch1, 0));
3637 }
3638 }
3639
3640 void MacroAssembler::null_check(Register reg, int offset) {
3641 if (needs_explicit_null_check(offset)) {
3642 // provoke OS NULL exception if reg = NULL by
3643 // accessing M[reg] w/o changing any (non-CC) registers
3644 // NOTE: cmpl is plenty here to provoke a segv
3645 cmpptr(rax, Address(reg, 0));
3646 // Note: should probably use testl(rax, Address(reg, 0));
3647 // may be shorter code (however, this version of
3648 // testl needs to be implemented first)
3649 } else {
3650 // nothing to do, (later) access of M[reg + offset]
3651 // will provoke OS NULL exception if reg = NULL
3652 }
3653 }
3654
3655 void MacroAssembler::os_breakpoint() {
3656 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3657 // (e.g., MSVC can't call ps() otherwise)
3658 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3659 }
3660
3661 void MacroAssembler::unimplemented(const char* what) {
3662 char* b = new char[1024];
3663 jio_snprintf(b, 1024, "unimplemented: %s", what);
3664 stop(b);
3665 }
3666
3667 #ifdef _LP64
3668 #define XSTATE_BV 0x200
3669 #endif
3670
3671 void MacroAssembler::pop_CPU_state() {
3672 pop_FPU_state();
3673 pop_IU_state();
3674 }
3675
3676 void MacroAssembler::pop_FPU_state() {
3677 #ifndef _LP64
3678 frstor(Address(rsp, 0));
3679 #else
3680 fxrstor(Address(rsp, 0));
3681 #endif
3682 addptr(rsp, FPUStateSizeInWords * wordSize);
3683 }
3684
3685 void MacroAssembler::pop_IU_state() {
3686 popa();
3687 LP64_ONLY(addq(rsp, 8));
3688 popf();
3689 }
3690
3691 // Save Integer and Float state
3692 // Warning: Stack must be 16 byte aligned (64bit)
3693 void MacroAssembler::push_CPU_state() {
3694 push_IU_state();
3695 push_FPU_state();
3696 }
3697
3698 void MacroAssembler::push_FPU_state() {
3699 subptr(rsp, FPUStateSizeInWords * wordSize);
3700 #ifndef _LP64
3701 fnsave(Address(rsp, 0));
3702 fwait();
3703 #else
3704 fxsave(Address(rsp, 0));
3705 #endif // LP64
3706 }
3707
3708 void MacroAssembler::push_IU_state() {
3709 // Push flags first because pusha kills them
3710 pushf();
3711 // Make sure rsp stays 16-byte aligned
3712 LP64_ONLY(subq(rsp, 8));
3713 pusha();
3714 }
3715
3716 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3717 if (!java_thread->is_valid()) {
3718 java_thread = rdi;
3719 get_thread(java_thread);
3720 }
3721 // we must set sp to zero to clear frame
3722 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3723 if (clear_fp) {
3724 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3725 }
3726
3727 // Always clear the pc because it could have been set by make_walkable()
3728 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3729
3730 vzeroupper();
3731 }
3732
3733 void MacroAssembler::restore_rax(Register tmp) {
3734 if (tmp == noreg) pop(rax);
3735 else if (tmp != rax) mov(rax, tmp);
3736 }
3737
3738 void MacroAssembler::round_to(Register reg, int modulus) {
3739 addptr(reg, modulus - 1);
3740 andptr(reg, -modulus);
3741 }
3742
3743 void MacroAssembler::save_rax(Register tmp) {
3744 if (tmp == noreg) push(rax);
3745 else if (tmp != rax) mov(tmp, rax);
3746 }
3747
3748 // Write serialization page so VM thread can do a pseudo remote membar.
3749 // We use the current thread pointer to calculate a thread specific
3750 // offset to write to within the page. This minimizes bus traffic
3751 // due to cache line collision.
3752 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3753 movl(tmp, thread);
3754 shrl(tmp, os::get_serialize_page_shift_count());
3755 andl(tmp, (os::vm_page_size() - sizeof(int)));
3756
3757 Address index(noreg, tmp, Address::times_1);
3758 ExternalAddress page(os::get_memory_serialize_page());
3759
3760 // Size of store must match masking code above
3761 movl(as_Address(ArrayAddress(page, index)), tmp);
3762 }
3763
3764 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3765 if (SafepointMechanism::uses_thread_local_poll()) {
3766 #ifndef AMD64
3767 if (thread_reg == noreg) {
3768 thread_reg = temp_reg;
3769 get_thread(thread_reg);
3770 }
3771 #endif
3772 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3773 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3774 } else {
3775 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3776 SafepointSynchronize::_not_synchronized);
3777 jcc(Assembler::notEqual, slow_path);
3778 }
3779 }
3780
3781 // Calls to C land
3782 //
3783 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3784 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3785 // has to be reset to 0. This is required to allow proper stack traversal.
3786 void MacroAssembler::set_last_Java_frame(Register java_thread,
3787 Register last_java_sp,
3788 Register last_java_fp,
3789 address last_java_pc) {
3790 vzeroupper();
3791 // determine java_thread register
3792 if (!java_thread->is_valid()) {
3793 java_thread = rdi;
3794 get_thread(java_thread);
3795 }
3796 // determine last_java_sp register
3797 if (!last_java_sp->is_valid()) {
3798 last_java_sp = rsp;
3799 }
3800
3801 // last_java_fp is optional
3802
3803 if (last_java_fp->is_valid()) {
3804 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3805 }
3806
3807 // last_java_pc is optional
3808
3809 if (last_java_pc != NULL) {
3810 lea(Address(java_thread,
3811 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3812 InternalAddress(last_java_pc));
3813
3814 }
3815 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3816 }
3817
3818 void MacroAssembler::shlptr(Register dst, int imm8) {
3819 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3820 }
3821
3822 void MacroAssembler::shrptr(Register dst, int imm8) {
3823 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3824 }
3825
3826 void MacroAssembler::sign_extend_byte(Register reg) {
3827 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3828 movsbl(reg, reg); // movsxb
3829 } else {
3830 shll(reg, 24);
3831 sarl(reg, 24);
3832 }
3833 }
3834
3835 void MacroAssembler::sign_extend_short(Register reg) {
3836 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3837 movswl(reg, reg); // movsxw
3838 } else {
3839 shll(reg, 16);
3840 sarl(reg, 16);
3841 }
3842 }
3843
3844 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3845 assert(reachable(src), "Address should be reachable");
3846 testl(dst, as_Address(src));
3847 }
3848
3849 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3850 int dst_enc = dst->encoding();
3851 int src_enc = src->encoding();
3852 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3853 Assembler::pcmpeqb(dst, src);
3854 } else if ((dst_enc < 16) && (src_enc < 16)) {
3855 Assembler::pcmpeqb(dst, src);
3856 } else if (src_enc < 16) {
3857 subptr(rsp, 64);
3858 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3859 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3860 Assembler::pcmpeqb(xmm0, src);
3861 movdqu(dst, xmm0);
3862 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3863 addptr(rsp, 64);
3864 } else if (dst_enc < 16) {
3865 subptr(rsp, 64);
3866 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3867 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3868 Assembler::pcmpeqb(dst, xmm0);
3869 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3870 addptr(rsp, 64);
3871 } else {
3872 subptr(rsp, 64);
3873 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3874 subptr(rsp, 64);
3875 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3876 movdqu(xmm0, src);
3877 movdqu(xmm1, dst);
3878 Assembler::pcmpeqb(xmm1, xmm0);
3879 movdqu(dst, xmm1);
3880 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3881 addptr(rsp, 64);
3882 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3883 addptr(rsp, 64);
3884 }
3885 }
3886
3887 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3888 int dst_enc = dst->encoding();
3889 int src_enc = src->encoding();
3890 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3891 Assembler::pcmpeqw(dst, src);
3892 } else if ((dst_enc < 16) && (src_enc < 16)) {
3893 Assembler::pcmpeqw(dst, src);
3894 } else if (src_enc < 16) {
3895 subptr(rsp, 64);
3896 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3897 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3898 Assembler::pcmpeqw(xmm0, src);
3899 movdqu(dst, xmm0);
3900 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3901 addptr(rsp, 64);
3902 } else if (dst_enc < 16) {
3903 subptr(rsp, 64);
3904 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3905 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3906 Assembler::pcmpeqw(dst, xmm0);
3907 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3908 addptr(rsp, 64);
3909 } else {
3910 subptr(rsp, 64);
3911 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3912 subptr(rsp, 64);
3913 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3914 movdqu(xmm0, src);
3915 movdqu(xmm1, dst);
3916 Assembler::pcmpeqw(xmm1, xmm0);
3917 movdqu(dst, xmm1);
3918 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3919 addptr(rsp, 64);
3920 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3921 addptr(rsp, 64);
3922 }
3923 }
3924
3925 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3926 int dst_enc = dst->encoding();
3927 if (dst_enc < 16) {
3928 Assembler::pcmpestri(dst, src, imm8);
3929 } else {
3930 subptr(rsp, 64);
3931 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3932 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3933 Assembler::pcmpestri(xmm0, src, imm8);
3934 movdqu(dst, xmm0);
3935 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3936 addptr(rsp, 64);
3937 }
3938 }
3939
3940 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3941 int dst_enc = dst->encoding();
3942 int src_enc = src->encoding();
3943 if ((dst_enc < 16) && (src_enc < 16)) {
3944 Assembler::pcmpestri(dst, src, imm8);
3945 } else if (src_enc < 16) {
3946 subptr(rsp, 64);
3947 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3948 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3949 Assembler::pcmpestri(xmm0, src, imm8);
3950 movdqu(dst, xmm0);
3951 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3952 addptr(rsp, 64);
3953 } else if (dst_enc < 16) {
3954 subptr(rsp, 64);
3955 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3956 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3957 Assembler::pcmpestri(dst, xmm0, imm8);
3958 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3959 addptr(rsp, 64);
3960 } else {
3961 subptr(rsp, 64);
3962 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3963 subptr(rsp, 64);
3964 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3965 movdqu(xmm0, src);
3966 movdqu(xmm1, dst);
3967 Assembler::pcmpestri(xmm1, xmm0, imm8);
3968 movdqu(dst, xmm1);
3969 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3970 addptr(rsp, 64);
3971 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3972 addptr(rsp, 64);
3973 }
3974 }
3975
3976 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3977 int dst_enc = dst->encoding();
3978 int src_enc = src->encoding();
3979 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3980 Assembler::pmovzxbw(dst, src);
3981 } else if ((dst_enc < 16) && (src_enc < 16)) {
3982 Assembler::pmovzxbw(dst, src);
3983 } else if (src_enc < 16) {
3984 subptr(rsp, 64);
3985 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3986 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3987 Assembler::pmovzxbw(xmm0, src);
3988 movdqu(dst, xmm0);
3989 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3990 addptr(rsp, 64);
3991 } else if (dst_enc < 16) {
3992 subptr(rsp, 64);
3993 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3994 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3995 Assembler::pmovzxbw(dst, xmm0);
3996 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3997 addptr(rsp, 64);
3998 } else {
3999 subptr(rsp, 64);
4000 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4001 subptr(rsp, 64);
4002 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4003 movdqu(xmm0, src);
4004 movdqu(xmm1, dst);
4005 Assembler::pmovzxbw(xmm1, xmm0);
4006 movdqu(dst, xmm1);
4007 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4008 addptr(rsp, 64);
4009 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4010 addptr(rsp, 64);
4011 }
4012 }
4013
4014 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
4015 int dst_enc = dst->encoding();
4016 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4017 Assembler::pmovzxbw(dst, src);
4018 } else if (dst_enc < 16) {
4019 Assembler::pmovzxbw(dst, src);
4020 } else {
4021 subptr(rsp, 64);
4022 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4023 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4024 Assembler::pmovzxbw(xmm0, src);
4025 movdqu(dst, xmm0);
4026 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4027 addptr(rsp, 64);
4028 }
4029 }
4030
4031 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
4032 int src_enc = src->encoding();
4033 if (src_enc < 16) {
4034 Assembler::pmovmskb(dst, src);
4035 } else {
4036 subptr(rsp, 64);
4037 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4038 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4039 Assembler::pmovmskb(dst, xmm0);
4040 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4041 addptr(rsp, 64);
4042 }
4043 }
4044
4045 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
4046 int dst_enc = dst->encoding();
4047 int src_enc = src->encoding();
4048 if ((dst_enc < 16) && (src_enc < 16)) {
4049 Assembler::ptest(dst, src);
4050 } else if (src_enc < 16) {
4051 subptr(rsp, 64);
4052 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4053 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4054 Assembler::ptest(xmm0, src);
4055 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4056 addptr(rsp, 64);
4057 } else if (dst_enc < 16) {
4058 subptr(rsp, 64);
4059 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4060 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4061 Assembler::ptest(dst, xmm0);
4062 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4063 addptr(rsp, 64);
4064 } else {
4065 subptr(rsp, 64);
4066 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4067 subptr(rsp, 64);
4068 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4069 movdqu(xmm0, src);
4070 movdqu(xmm1, dst);
4071 Assembler::ptest(xmm1, xmm0);
4072 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4073 addptr(rsp, 64);
4074 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4075 addptr(rsp, 64);
4076 }
4077 }
4078
4079 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4080 if (reachable(src)) {
4081 Assembler::sqrtsd(dst, as_Address(src));
4082 } else {
4083 lea(rscratch1, src);
4084 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4085 }
4086 }
4087
4088 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4089 if (reachable(src)) {
4090 Assembler::sqrtss(dst, as_Address(src));
4091 } else {
4092 lea(rscratch1, src);
4093 Assembler::sqrtss(dst, Address(rscratch1, 0));
4094 }
4095 }
4096
4097 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4098 if (reachable(src)) {
4099 Assembler::subsd(dst, as_Address(src));
4100 } else {
4101 lea(rscratch1, src);
4102 Assembler::subsd(dst, Address(rscratch1, 0));
4103 }
4104 }
4105
4106 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4107 if (reachable(src)) {
4108 Assembler::subss(dst, as_Address(src));
4109 } else {
4110 lea(rscratch1, src);
4111 Assembler::subss(dst, Address(rscratch1, 0));
4112 }
4113 }
4114
4115 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4116 if (reachable(src)) {
4117 Assembler::ucomisd(dst, as_Address(src));
4118 } else {
4119 lea(rscratch1, src);
4120 Assembler::ucomisd(dst, Address(rscratch1, 0));
4121 }
4122 }
4123
4124 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4125 if (reachable(src)) {
4126 Assembler::ucomiss(dst, as_Address(src));
4127 } else {
4128 lea(rscratch1, src);
4129 Assembler::ucomiss(dst, Address(rscratch1, 0));
4130 }
4131 }
4132
4133 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4134 // Used in sign-bit flipping with aligned address.
4135 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4136 if (reachable(src)) {
4137 Assembler::xorpd(dst, as_Address(src));
4138 } else {
4139 lea(rscratch1, src);
4140 Assembler::xorpd(dst, Address(rscratch1, 0));
4141 }
4142 }
4143
4144 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4145 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4146 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4147 }
4148 else {
4149 Assembler::xorpd(dst, src);
4150 }
4151 }
4152
4153 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4154 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4155 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4156 } else {
4157 Assembler::xorps(dst, src);
4158 }
4159 }
4160
4161 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4162 // Used in sign-bit flipping with aligned address.
4163 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4164 if (reachable(src)) {
4165 Assembler::xorps(dst, as_Address(src));
4166 } else {
4167 lea(rscratch1, src);
4168 Assembler::xorps(dst, Address(rscratch1, 0));
4169 }
4170 }
4171
4172 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4173 // Used in sign-bit flipping with aligned address.
4174 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4175 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4176 if (reachable(src)) {
4177 Assembler::pshufb(dst, as_Address(src));
4178 } else {
4179 lea(rscratch1, src);
4180 Assembler::pshufb(dst, Address(rscratch1, 0));
4181 }
4182 }
4183
4184 // AVX 3-operands instructions
4185
4186 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4187 if (reachable(src)) {
4188 vaddsd(dst, nds, as_Address(src));
4189 } else {
4190 lea(rscratch1, src);
4191 vaddsd(dst, nds, Address(rscratch1, 0));
4192 }
4193 }
4194
4195 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4196 if (reachable(src)) {
4197 vaddss(dst, nds, as_Address(src));
4198 } else {
4199 lea(rscratch1, src);
4200 vaddss(dst, nds, Address(rscratch1, 0));
4201 }
4202 }
4203
4204 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4205 int dst_enc = dst->encoding();
4206 int nds_enc = nds->encoding();
4207 int src_enc = src->encoding();
4208 if ((dst_enc < 16) && (nds_enc < 16)) {
4209 vandps(dst, nds, negate_field, vector_len);
4210 } else if ((src_enc < 16) && (dst_enc < 16)) {
4211 evmovdqul(src, nds, Assembler::AVX_512bit);
4212 vandps(dst, src, negate_field, vector_len);
4213 } else if (src_enc < 16) {
4214 evmovdqul(src, nds, Assembler::AVX_512bit);
4215 vandps(src, src, negate_field, vector_len);
4216 evmovdqul(dst, src, Assembler::AVX_512bit);
4217 } else if (dst_enc < 16) {
4218 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4219 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4220 vandps(dst, xmm0, negate_field, vector_len);
4221 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4222 } else {
4223 if (src_enc != dst_enc) {
4224 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4225 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4226 vandps(xmm0, xmm0, negate_field, vector_len);
4227 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4228 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4229 } else {
4230 subptr(rsp, 64);
4231 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4232 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4233 vandps(xmm0, xmm0, negate_field, vector_len);
4234 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4235 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4236 addptr(rsp, 64);
4237 }
4238 }
4239 }
4240
4241 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4242 int dst_enc = dst->encoding();
4243 int nds_enc = nds->encoding();
4244 int src_enc = src->encoding();
4245 if ((dst_enc < 16) && (nds_enc < 16)) {
4246 vandpd(dst, nds, negate_field, vector_len);
4247 } else if ((src_enc < 16) && (dst_enc < 16)) {
4248 evmovdqul(src, nds, Assembler::AVX_512bit);
4249 vandpd(dst, src, negate_field, vector_len);
4250 } else if (src_enc < 16) {
4251 evmovdqul(src, nds, Assembler::AVX_512bit);
4252 vandpd(src, src, negate_field, vector_len);
4253 evmovdqul(dst, src, Assembler::AVX_512bit);
4254 } else if (dst_enc < 16) {
4255 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4256 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4257 vandpd(dst, xmm0, negate_field, vector_len);
4258 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4259 } else {
4260 if (src_enc != dst_enc) {
4261 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4262 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4263 vandpd(xmm0, xmm0, negate_field, vector_len);
4264 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4265 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4266 } else {
4267 subptr(rsp, 64);
4268 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4269 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4270 vandpd(xmm0, xmm0, negate_field, vector_len);
4271 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4272 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4273 addptr(rsp, 64);
4274 }
4275 }
4276 }
4277
4278 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4279 int dst_enc = dst->encoding();
4280 int nds_enc = nds->encoding();
4281 int src_enc = src->encoding();
4282 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4283 Assembler::vpaddb(dst, nds, src, vector_len);
4284 } else if ((dst_enc < 16) && (src_enc < 16)) {
4285 Assembler::vpaddb(dst, dst, src, vector_len);
4286 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4287 // use nds as scratch for src
4288 evmovdqul(nds, src, Assembler::AVX_512bit);
4289 Assembler::vpaddb(dst, dst, nds, vector_len);
4290 } else if ((src_enc < 16) && (nds_enc < 16)) {
4291 // use nds as scratch for dst
4292 evmovdqul(nds, dst, Assembler::AVX_512bit);
4293 Assembler::vpaddb(nds, nds, src, vector_len);
4294 evmovdqul(dst, nds, Assembler::AVX_512bit);
4295 } else if (dst_enc < 16) {
4296 // use nds as scatch for xmm0 to hold src
4297 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4298 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4299 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4300 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4301 } else {
4302 // worse case scenario, all regs are in the upper bank
4303 subptr(rsp, 64);
4304 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4305 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4306 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4307 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4308 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4309 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4310 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4311 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4312 addptr(rsp, 64);
4313 }
4314 }
4315
4316 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4317 int dst_enc = dst->encoding();
4318 int nds_enc = nds->encoding();
4319 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4320 Assembler::vpaddb(dst, nds, src, vector_len);
4321 } else if (dst_enc < 16) {
4322 Assembler::vpaddb(dst, dst, src, vector_len);
4323 } else if (nds_enc < 16) {
4324 // implies dst_enc in upper bank with src as scratch
4325 evmovdqul(nds, dst, Assembler::AVX_512bit);
4326 Assembler::vpaddb(nds, nds, src, vector_len);
4327 evmovdqul(dst, nds, Assembler::AVX_512bit);
4328 } else {
4329 // worse case scenario, all regs in upper bank
4330 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4331 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4332 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4333 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4334 }
4335 }
4336
4337 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4338 int dst_enc = dst->encoding();
4339 int nds_enc = nds->encoding();
4340 int src_enc = src->encoding();
4341 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4342 Assembler::vpaddw(dst, nds, src, vector_len);
4343 } else if ((dst_enc < 16) && (src_enc < 16)) {
4344 Assembler::vpaddw(dst, dst, src, vector_len);
4345 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4346 // use nds as scratch for src
4347 evmovdqul(nds, src, Assembler::AVX_512bit);
4348 Assembler::vpaddw(dst, dst, nds, vector_len);
4349 } else if ((src_enc < 16) && (nds_enc < 16)) {
4350 // use nds as scratch for dst
4351 evmovdqul(nds, dst, Assembler::AVX_512bit);
4352 Assembler::vpaddw(nds, nds, src, vector_len);
4353 evmovdqul(dst, nds, Assembler::AVX_512bit);
4354 } else if (dst_enc < 16) {
4355 // use nds as scatch for xmm0 to hold src
4356 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4357 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4358 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4359 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4360 } else {
4361 // worse case scenario, all regs are in the upper bank
4362 subptr(rsp, 64);
4363 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4364 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4365 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4366 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4367 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4368 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4369 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4370 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4371 addptr(rsp, 64);
4372 }
4373 }
4374
4375 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4376 int dst_enc = dst->encoding();
4377 int nds_enc = nds->encoding();
4378 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4379 Assembler::vpaddw(dst, nds, src, vector_len);
4380 } else if (dst_enc < 16) {
4381 Assembler::vpaddw(dst, dst, src, vector_len);
4382 } else if (nds_enc < 16) {
4383 // implies dst_enc in upper bank with src as scratch
4384 evmovdqul(nds, dst, Assembler::AVX_512bit);
4385 Assembler::vpaddw(nds, nds, src, vector_len);
4386 evmovdqul(dst, nds, Assembler::AVX_512bit);
4387 } else {
4388 // worse case scenario, all regs in upper bank
4389 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4390 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4391 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4392 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4393 }
4394 }
4395
4396 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4397 if (reachable(src)) {
4398 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4399 } else {
4400 lea(rscratch1, src);
4401 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4402 }
4403 }
4404
4405 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4406 int dst_enc = dst->encoding();
4407 int src_enc = src->encoding();
4408 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4409 Assembler::vpbroadcastw(dst, src);
4410 } else if ((dst_enc < 16) && (src_enc < 16)) {
4411 Assembler::vpbroadcastw(dst, src);
4412 } else if (src_enc < 16) {
4413 subptr(rsp, 64);
4414 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4415 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4416 Assembler::vpbroadcastw(xmm0, src);
4417 movdqu(dst, xmm0);
4418 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4419 addptr(rsp, 64);
4420 } else if (dst_enc < 16) {
4421 subptr(rsp, 64);
4422 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4423 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4424 Assembler::vpbroadcastw(dst, xmm0);
4425 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4426 addptr(rsp, 64);
4427 } else {
4428 subptr(rsp, 64);
4429 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4430 subptr(rsp, 64);
4431 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4432 movdqu(xmm0, src);
4433 movdqu(xmm1, dst);
4434 Assembler::vpbroadcastw(xmm1, xmm0);
4435 movdqu(dst, xmm1);
4436 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4437 addptr(rsp, 64);
4438 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4439 addptr(rsp, 64);
4440 }
4441 }
4442
4443 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4444 int dst_enc = dst->encoding();
4445 int nds_enc = nds->encoding();
4446 int src_enc = src->encoding();
4447 assert(dst_enc == nds_enc, "");
4448 if ((dst_enc < 16) && (src_enc < 16)) {
4449 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4450 } else if (src_enc < 16) {
4451 subptr(rsp, 64);
4452 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4453 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4454 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4455 movdqu(dst, xmm0);
4456 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4457 addptr(rsp, 64);
4458 } else if (dst_enc < 16) {
4459 subptr(rsp, 64);
4460 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4461 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4462 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4463 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4464 addptr(rsp, 64);
4465 } else {
4466 subptr(rsp, 64);
4467 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4468 subptr(rsp, 64);
4469 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4470 movdqu(xmm0, src);
4471 movdqu(xmm1, dst);
4472 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4473 movdqu(dst, xmm1);
4474 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4475 addptr(rsp, 64);
4476 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4477 addptr(rsp, 64);
4478 }
4479 }
4480
4481 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4482 int dst_enc = dst->encoding();
4483 int nds_enc = nds->encoding();
4484 int src_enc = src->encoding();
4485 assert(dst_enc == nds_enc, "");
4486 if ((dst_enc < 16) && (src_enc < 16)) {
4487 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4488 } else if (src_enc < 16) {
4489 subptr(rsp, 64);
4490 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4491 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4492 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4493 movdqu(dst, xmm0);
4494 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4495 addptr(rsp, 64);
4496 } else if (dst_enc < 16) {
4497 subptr(rsp, 64);
4498 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4499 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4500 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4501 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4502 addptr(rsp, 64);
4503 } else {
4504 subptr(rsp, 64);
4505 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4506 subptr(rsp, 64);
4507 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4508 movdqu(xmm0, src);
4509 movdqu(xmm1, dst);
4510 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4511 movdqu(dst, xmm1);
4512 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4513 addptr(rsp, 64);
4514 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4515 addptr(rsp, 64);
4516 }
4517 }
4518
4519 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4520 int dst_enc = dst->encoding();
4521 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4522 Assembler::vpmovzxbw(dst, src, vector_len);
4523 } else if (dst_enc < 16) {
4524 Assembler::vpmovzxbw(dst, src, vector_len);
4525 } else {
4526 subptr(rsp, 64);
4527 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4528 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4529 Assembler::vpmovzxbw(xmm0, src, vector_len);
4530 movdqu(dst, xmm0);
4531 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4532 addptr(rsp, 64);
4533 }
4534 }
4535
4536 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4537 int src_enc = src->encoding();
4538 if (src_enc < 16) {
4539 Assembler::vpmovmskb(dst, src);
4540 } else {
4541 subptr(rsp, 64);
4542 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4543 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4544 Assembler::vpmovmskb(dst, xmm0);
4545 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4546 addptr(rsp, 64);
4547 }
4548 }
4549
4550 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4551 int dst_enc = dst->encoding();
4552 int nds_enc = nds->encoding();
4553 int src_enc = src->encoding();
4554 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4555 Assembler::vpmullw(dst, nds, src, vector_len);
4556 } else if ((dst_enc < 16) && (src_enc < 16)) {
4557 Assembler::vpmullw(dst, dst, src, vector_len);
4558 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4559 // use nds as scratch for src
4560 evmovdqul(nds, src, Assembler::AVX_512bit);
4561 Assembler::vpmullw(dst, dst, nds, vector_len);
4562 } else if ((src_enc < 16) && (nds_enc < 16)) {
4563 // use nds as scratch for dst
4564 evmovdqul(nds, dst, Assembler::AVX_512bit);
4565 Assembler::vpmullw(nds, nds, src, vector_len);
4566 evmovdqul(dst, nds, Assembler::AVX_512bit);
4567 } else if (dst_enc < 16) {
4568 // use nds as scatch for xmm0 to hold src
4569 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4570 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4571 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4572 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4573 } else {
4574 // worse case scenario, all regs are in the upper bank
4575 subptr(rsp, 64);
4576 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4577 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4578 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4579 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4580 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4581 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4582 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4583 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4584 addptr(rsp, 64);
4585 }
4586 }
4587
4588 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4589 int dst_enc = dst->encoding();
4590 int nds_enc = nds->encoding();
4591 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4592 Assembler::vpmullw(dst, nds, src, vector_len);
4593 } else if (dst_enc < 16) {
4594 Assembler::vpmullw(dst, dst, src, vector_len);
4595 } else if (nds_enc < 16) {
4596 // implies dst_enc in upper bank with src as scratch
4597 evmovdqul(nds, dst, Assembler::AVX_512bit);
4598 Assembler::vpmullw(nds, nds, src, vector_len);
4599 evmovdqul(dst, nds, Assembler::AVX_512bit);
4600 } else {
4601 // worse case scenario, all regs in upper bank
4602 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4603 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4604 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4605 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4606 }
4607 }
4608
4609 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4610 int dst_enc = dst->encoding();
4611 int nds_enc = nds->encoding();
4612 int src_enc = src->encoding();
4613 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4614 Assembler::vpsubb(dst, nds, src, vector_len);
4615 } else if ((dst_enc < 16) && (src_enc < 16)) {
4616 Assembler::vpsubb(dst, dst, src, vector_len);
4617 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4618 // use nds as scratch for src
4619 evmovdqul(nds, src, Assembler::AVX_512bit);
4620 Assembler::vpsubb(dst, dst, nds, vector_len);
4621 } else if ((src_enc < 16) && (nds_enc < 16)) {
4622 // use nds as scratch for dst
4623 evmovdqul(nds, dst, Assembler::AVX_512bit);
4624 Assembler::vpsubb(nds, nds, src, vector_len);
4625 evmovdqul(dst, nds, Assembler::AVX_512bit);
4626 } else if (dst_enc < 16) {
4627 // use nds as scatch for xmm0 to hold src
4628 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4629 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4630 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4631 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4632 } else {
4633 // worse case scenario, all regs are in the upper bank
4634 subptr(rsp, 64);
4635 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4636 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4637 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4638 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4639 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4640 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4641 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4642 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4643 addptr(rsp, 64);
4644 }
4645 }
4646
4647 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4648 int dst_enc = dst->encoding();
4649 int nds_enc = nds->encoding();
4650 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4651 Assembler::vpsubb(dst, nds, src, vector_len);
4652 } else if (dst_enc < 16) {
4653 Assembler::vpsubb(dst, dst, src, vector_len);
4654 } else if (nds_enc < 16) {
4655 // implies dst_enc in upper bank with src as scratch
4656 evmovdqul(nds, dst, Assembler::AVX_512bit);
4657 Assembler::vpsubb(nds, nds, src, vector_len);
4658 evmovdqul(dst, nds, Assembler::AVX_512bit);
4659 } else {
4660 // worse case scenario, all regs in upper bank
4661 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4662 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4663 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4664 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4665 }
4666 }
4667
4668 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4669 int dst_enc = dst->encoding();
4670 int nds_enc = nds->encoding();
4671 int src_enc = src->encoding();
4672 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4673 Assembler::vpsubw(dst, nds, src, vector_len);
4674 } else if ((dst_enc < 16) && (src_enc < 16)) {
4675 Assembler::vpsubw(dst, dst, src, vector_len);
4676 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4677 // use nds as scratch for src
4678 evmovdqul(nds, src, Assembler::AVX_512bit);
4679 Assembler::vpsubw(dst, dst, nds, vector_len);
4680 } else if ((src_enc < 16) && (nds_enc < 16)) {
4681 // use nds as scratch for dst
4682 evmovdqul(nds, dst, Assembler::AVX_512bit);
4683 Assembler::vpsubw(nds, nds, src, vector_len);
4684 evmovdqul(dst, nds, Assembler::AVX_512bit);
4685 } else if (dst_enc < 16) {
4686 // use nds as scatch for xmm0 to hold src
4687 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4688 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4689 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4690 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4691 } else {
4692 // worse case scenario, all regs are in the upper bank
4693 subptr(rsp, 64);
4694 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4695 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4696 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4697 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4698 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4699 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4700 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4701 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4702 addptr(rsp, 64);
4703 }
4704 }
4705
4706 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4707 int dst_enc = dst->encoding();
4708 int nds_enc = nds->encoding();
4709 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4710 Assembler::vpsubw(dst, nds, src, vector_len);
4711 } else if (dst_enc < 16) {
4712 Assembler::vpsubw(dst, dst, src, vector_len);
4713 } else if (nds_enc < 16) {
4714 // implies dst_enc in upper bank with src as scratch
4715 evmovdqul(nds, dst, Assembler::AVX_512bit);
4716 Assembler::vpsubw(nds, nds, src, vector_len);
4717 evmovdqul(dst, nds, Assembler::AVX_512bit);
4718 } else {
4719 // worse case scenario, all regs in upper bank
4720 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4721 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4722 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4723 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4724 }
4725 }
4726
4727 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4728 int dst_enc = dst->encoding();
4729 int nds_enc = nds->encoding();
4730 int shift_enc = shift->encoding();
4731 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4732 Assembler::vpsraw(dst, nds, shift, vector_len);
4733 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4734 Assembler::vpsraw(dst, dst, shift, vector_len);
4735 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4736 // use nds_enc as scratch with shift
4737 evmovdqul(nds, shift, Assembler::AVX_512bit);
4738 Assembler::vpsraw(dst, dst, nds, vector_len);
4739 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4740 // use nds as scratch with dst
4741 evmovdqul(nds, dst, Assembler::AVX_512bit);
4742 Assembler::vpsraw(nds, nds, shift, vector_len);
4743 evmovdqul(dst, nds, Assembler::AVX_512bit);
4744 } else if (dst_enc < 16) {
4745 // use nds to save a copy of xmm0 and hold shift
4746 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4747 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4748 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4749 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4750 } else if (nds_enc < 16) {
4751 // use nds as dest as temps
4752 evmovdqul(nds, dst, Assembler::AVX_512bit);
4753 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4754 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4755 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4756 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4757 evmovdqul(dst, nds, Assembler::AVX_512bit);
4758 } else {
4759 // worse case scenario, all regs are in the upper bank
4760 subptr(rsp, 64);
4761 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4762 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4763 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4764 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4765 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4766 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4767 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4768 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4769 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4770 addptr(rsp, 64);
4771 }
4772 }
4773
4774 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4775 int dst_enc = dst->encoding();
4776 int nds_enc = nds->encoding();
4777 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4778 Assembler::vpsraw(dst, nds, shift, vector_len);
4779 } else if (dst_enc < 16) {
4780 Assembler::vpsraw(dst, dst, shift, vector_len);
4781 } else if (nds_enc < 16) {
4782 // use nds as scratch
4783 evmovdqul(nds, dst, Assembler::AVX_512bit);
4784 Assembler::vpsraw(nds, nds, shift, vector_len);
4785 evmovdqul(dst, nds, Assembler::AVX_512bit);
4786 } else {
4787 // use nds as scratch for xmm0
4788 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4789 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4790 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4791 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4792 }
4793 }
4794
4795 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4796 int dst_enc = dst->encoding();
4797 int nds_enc = nds->encoding();
4798 int shift_enc = shift->encoding();
4799 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4800 Assembler::vpsrlw(dst, nds, shift, vector_len);
4801 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4802 Assembler::vpsrlw(dst, dst, shift, vector_len);
4803 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4804 // use nds_enc as scratch with shift
4805 evmovdqul(nds, shift, Assembler::AVX_512bit);
4806 Assembler::vpsrlw(dst, dst, nds, vector_len);
4807 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4808 // use nds as scratch with dst
4809 evmovdqul(nds, dst, Assembler::AVX_512bit);
4810 Assembler::vpsrlw(nds, nds, shift, vector_len);
4811 evmovdqul(dst, nds, Assembler::AVX_512bit);
4812 } else if (dst_enc < 16) {
4813 // use nds to save a copy of xmm0 and hold shift
4814 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4815 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4816 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4817 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4818 } else if (nds_enc < 16) {
4819 // use nds as dest as temps
4820 evmovdqul(nds, dst, Assembler::AVX_512bit);
4821 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4822 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4823 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4824 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4825 evmovdqul(dst, nds, Assembler::AVX_512bit);
4826 } else {
4827 // worse case scenario, all regs are in the upper bank
4828 subptr(rsp, 64);
4829 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4830 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4831 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4832 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4833 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4834 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4835 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4836 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4837 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4838 addptr(rsp, 64);
4839 }
4840 }
4841
4842 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4843 int dst_enc = dst->encoding();
4844 int nds_enc = nds->encoding();
4845 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4846 Assembler::vpsrlw(dst, nds, shift, vector_len);
4847 } else if (dst_enc < 16) {
4848 Assembler::vpsrlw(dst, dst, shift, vector_len);
4849 } else if (nds_enc < 16) {
4850 // use nds as scratch
4851 evmovdqul(nds, dst, Assembler::AVX_512bit);
4852 Assembler::vpsrlw(nds, nds, shift, vector_len);
4853 evmovdqul(dst, nds, Assembler::AVX_512bit);
4854 } else {
4855 // use nds as scratch for xmm0
4856 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4857 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4858 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4859 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4860 }
4861 }
4862
4863 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4864 int dst_enc = dst->encoding();
4865 int nds_enc = nds->encoding();
4866 int shift_enc = shift->encoding();
4867 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4868 Assembler::vpsllw(dst, nds, shift, vector_len);
4869 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4870 Assembler::vpsllw(dst, dst, shift, vector_len);
4871 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4872 // use nds_enc as scratch with shift
4873 evmovdqul(nds, shift, Assembler::AVX_512bit);
4874 Assembler::vpsllw(dst, dst, nds, vector_len);
4875 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4876 // use nds as scratch with dst
4877 evmovdqul(nds, dst, Assembler::AVX_512bit);
4878 Assembler::vpsllw(nds, nds, shift, vector_len);
4879 evmovdqul(dst, nds, Assembler::AVX_512bit);
4880 } else if (dst_enc < 16) {
4881 // use nds to save a copy of xmm0 and hold shift
4882 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4883 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4884 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4885 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4886 } else if (nds_enc < 16) {
4887 // use nds as dest as temps
4888 evmovdqul(nds, dst, Assembler::AVX_512bit);
4889 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4890 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4891 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4892 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4893 evmovdqul(dst, nds, Assembler::AVX_512bit);
4894 } else {
4895 // worse case scenario, all regs are in the upper bank
4896 subptr(rsp, 64);
4897 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4898 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4899 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4900 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4901 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4902 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4903 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4904 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4905 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4906 addptr(rsp, 64);
4907 }
4908 }
4909
4910 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4911 int dst_enc = dst->encoding();
4912 int nds_enc = nds->encoding();
4913 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4914 Assembler::vpsllw(dst, nds, shift, vector_len);
4915 } else if (dst_enc < 16) {
4916 Assembler::vpsllw(dst, dst, shift, vector_len);
4917 } else if (nds_enc < 16) {
4918 // use nds as scratch
4919 evmovdqul(nds, dst, Assembler::AVX_512bit);
4920 Assembler::vpsllw(nds, nds, shift, vector_len);
4921 evmovdqul(dst, nds, Assembler::AVX_512bit);
4922 } else {
4923 // use nds as scratch for xmm0
4924 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4925 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4926 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4927 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4928 }
4929 }
4930
4931 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4932 int dst_enc = dst->encoding();
4933 int src_enc = src->encoding();
4934 if ((dst_enc < 16) && (src_enc < 16)) {
4935 Assembler::vptest(dst, src);
4936 } else if (src_enc < 16) {
4937 subptr(rsp, 64);
4938 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4939 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4940 Assembler::vptest(xmm0, src);
4941 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4942 addptr(rsp, 64);
4943 } else if (dst_enc < 16) {
4944 subptr(rsp, 64);
4945 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4946 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4947 Assembler::vptest(dst, xmm0);
4948 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4949 addptr(rsp, 64);
4950 } else {
4951 subptr(rsp, 64);
4952 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4953 subptr(rsp, 64);
4954 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4955 movdqu(xmm0, src);
4956 movdqu(xmm1, dst);
4957 Assembler::vptest(xmm1, xmm0);
4958 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4959 addptr(rsp, 64);
4960 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4961 addptr(rsp, 64);
4962 }
4963 }
4964
4965 // This instruction exists within macros, ergo we cannot control its input
4966 // when emitted through those patterns.
4967 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4968 if (VM_Version::supports_avx512nobw()) {
4969 int dst_enc = dst->encoding();
4970 int src_enc = src->encoding();
4971 if (dst_enc == src_enc) {
4972 if (dst_enc < 16) {
4973 Assembler::punpcklbw(dst, src);
4974 } else {
4975 subptr(rsp, 64);
4976 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4977 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4978 Assembler::punpcklbw(xmm0, xmm0);
4979 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4980 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4981 addptr(rsp, 64);
4982 }
4983 } else {
4984 if ((src_enc < 16) && (dst_enc < 16)) {
4985 Assembler::punpcklbw(dst, src);
4986 } else if (src_enc < 16) {
4987 subptr(rsp, 64);
4988 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4989 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4990 Assembler::punpcklbw(xmm0, src);
4991 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4992 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4993 addptr(rsp, 64);
4994 } else if (dst_enc < 16) {
4995 subptr(rsp, 64);
4996 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4997 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4998 Assembler::punpcklbw(dst, xmm0);
4999 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5000 addptr(rsp, 64);
5001 } else {
5002 subptr(rsp, 64);
5003 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5004 subptr(rsp, 64);
5005 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
5006 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5007 evmovdqul(xmm1, src, Assembler::AVX_512bit);
5008 Assembler::punpcklbw(xmm0, xmm1);
5009 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5010 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
5011 addptr(rsp, 64);
5012 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5013 addptr(rsp, 64);
5014 }
5015 }
5016 } else {
5017 Assembler::punpcklbw(dst, src);
5018 }
5019 }
5020
5021 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
5022 if (VM_Version::supports_avx512vl()) {
5023 Assembler::pshufd(dst, src, mode);
5024 } else {
5025 int dst_enc = dst->encoding();
5026 if (dst_enc < 16) {
5027 Assembler::pshufd(dst, src, mode);
5028 } else {
5029 subptr(rsp, 64);
5030 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5031 Assembler::pshufd(xmm0, src, mode);
5032 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5033 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5034 addptr(rsp, 64);
5035 }
5036 }
5037 }
5038
5039 // This instruction exists within macros, ergo we cannot control its input
5040 // when emitted through those patterns.
5041 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
5042 if (VM_Version::supports_avx512nobw()) {
5043 int dst_enc = dst->encoding();
5044 int src_enc = src->encoding();
5045 if (dst_enc == src_enc) {
5046 if (dst_enc < 16) {
5047 Assembler::pshuflw(dst, src, mode);
5048 } else {
5049 subptr(rsp, 64);
5050 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5051 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5052 Assembler::pshuflw(xmm0, xmm0, mode);
5053 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5054 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5055 addptr(rsp, 64);
5056 }
5057 } else {
5058 if ((src_enc < 16) && (dst_enc < 16)) {
5059 Assembler::pshuflw(dst, src, mode);
5060 } else if (src_enc < 16) {
5061 subptr(rsp, 64);
5062 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5063 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5064 Assembler::pshuflw(xmm0, src, mode);
5065 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5066 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5067 addptr(rsp, 64);
5068 } else if (dst_enc < 16) {
5069 subptr(rsp, 64);
5070 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5071 evmovdqul(xmm0, src, Assembler::AVX_512bit);
5072 Assembler::pshuflw(dst, xmm0, mode);
5073 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5074 addptr(rsp, 64);
5075 } else {
5076 subptr(rsp, 64);
5077 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5078 subptr(rsp, 64);
5079 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
5080 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5081 evmovdqul(xmm1, src, Assembler::AVX_512bit);
5082 Assembler::pshuflw(xmm0, xmm1, mode);
5083 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5084 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
5085 addptr(rsp, 64);
5086 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5087 addptr(rsp, 64);
5088 }
5089 }
5090 } else {
5091 Assembler::pshuflw(dst, src, mode);
5092 }
5093 }
5094
5095 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5096 if (reachable(src)) {
5097 vandpd(dst, nds, as_Address(src), vector_len);
5098 } else {
5099 lea(rscratch1, src);
5100 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
5101 }
5102 }
5103
5104 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5105 if (reachable(src)) {
5106 vandps(dst, nds, as_Address(src), vector_len);
5107 } else {
5108 lea(rscratch1, src);
5109 vandps(dst, nds, Address(rscratch1, 0), vector_len);
5110 }
5111 }
5112
5113 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5114 if (reachable(src)) {
5115 vdivsd(dst, nds, as_Address(src));
5116 } else {
5117 lea(rscratch1, src);
5118 vdivsd(dst, nds, Address(rscratch1, 0));
5119 }
5120 }
5121
5122 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5123 if (reachable(src)) {
5124 vdivss(dst, nds, as_Address(src));
5125 } else {
5126 lea(rscratch1, src);
5127 vdivss(dst, nds, Address(rscratch1, 0));
5128 }
5129 }
5130
5131 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5132 if (reachable(src)) {
5133 vmulsd(dst, nds, as_Address(src));
5134 } else {
5135 lea(rscratch1, src);
5136 vmulsd(dst, nds, Address(rscratch1, 0));
5137 }
5138 }
5139
5140 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5141 if (reachable(src)) {
5142 vmulss(dst, nds, as_Address(src));
5143 } else {
5144 lea(rscratch1, src);
5145 vmulss(dst, nds, Address(rscratch1, 0));
5146 }
5147 }
5148
5149 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5150 if (reachable(src)) {
5151 vsubsd(dst, nds, as_Address(src));
5152 } else {
5153 lea(rscratch1, src);
5154 vsubsd(dst, nds, Address(rscratch1, 0));
5155 }
5156 }
5157
5158 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5159 if (reachable(src)) {
5160 vsubss(dst, nds, as_Address(src));
5161 } else {
5162 lea(rscratch1, src);
5163 vsubss(dst, nds, Address(rscratch1, 0));
5164 }
5165 }
5166
5167 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5168 int nds_enc = nds->encoding();
5169 int dst_enc = dst->encoding();
5170 bool dst_upper_bank = (dst_enc > 15);
5171 bool nds_upper_bank = (nds_enc > 15);
5172 if (VM_Version::supports_avx512novl() &&
5173 (nds_upper_bank || dst_upper_bank)) {
5174 if (dst_upper_bank) {
5175 subptr(rsp, 64);
5176 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5177 movflt(xmm0, nds);
5178 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5179 movflt(dst, xmm0);
5180 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5181 addptr(rsp, 64);
5182 } else {
5183 movflt(dst, nds);
5184 vxorps(dst, dst, src, Assembler::AVX_128bit);
5185 }
5186 } else {
5187 vxorps(dst, nds, src, Assembler::AVX_128bit);
5188 }
5189 }
5190
5191 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5192 int nds_enc = nds->encoding();
5193 int dst_enc = dst->encoding();
5194 bool dst_upper_bank = (dst_enc > 15);
5195 bool nds_upper_bank = (nds_enc > 15);
5196 if (VM_Version::supports_avx512novl() &&
5197 (nds_upper_bank || dst_upper_bank)) {
5198 if (dst_upper_bank) {
5199 subptr(rsp, 64);
5200 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5201 movdbl(xmm0, nds);
5202 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5203 movdbl(dst, xmm0);
5204 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5205 addptr(rsp, 64);
5206 } else {
5207 movdbl(dst, nds);
5208 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5209 }
5210 } else {
5211 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5212 }
5213 }
5214
5215 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5216 if (reachable(src)) {
5217 vxorpd(dst, nds, as_Address(src), vector_len);
5218 } else {
5219 lea(rscratch1, src);
5220 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5221 }
5222 }
5223
5224 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5225 if (reachable(src)) {
5226 vxorps(dst, nds, as_Address(src), vector_len);
5227 } else {
5228 lea(rscratch1, src);
5229 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5230 }
5231 }
5232
5233
5234 void MacroAssembler::resolve_jobject(Register value,
5235 Register thread,
5236 Register tmp) {
5237 assert_different_registers(value, thread, tmp);
5238 Label done, not_weak;
5239 testptr(value, value);
5240 jcc(Assembler::zero, done); // Use NULL as-is.
5241 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5242 jcc(Assembler::zero, not_weak);
5243 // Resolve jweak.
5244 movptr(value, Address(value, -JNIHandles::weak_tag_value));
5245 verify_oop(value);
5246 #if INCLUDE_ALL_GCS
5247 if (UseG1GC) {
5248 g1_write_barrier_pre(noreg /* obj */,
5249 value /* pre_val */,
5250 thread /* thread */,
5251 tmp /* tmp */,
5252 true /* tosca_live */,
5253 true /* expand_call */);
5254 }
5255 #endif // INCLUDE_ALL_GCS
5256 jmp(done);
5257 bind(not_weak);
5258 // Resolve (untagged) jobject.
5259 movptr(value, Address(value, 0));
5260 verify_oop(value);
5261 bind(done);
5262 }
5263
5264 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5265 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5266 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5267 // The inverted mask is sign-extended
5268 andptr(possibly_jweak, inverted_jweak_mask);
5269 }
5270
5271 //////////////////////////////////////////////////////////////////////////////////
5272 #if INCLUDE_ALL_GCS
5273
5274 void MacroAssembler::g1_write_barrier_pre(Register obj,
5275 Register pre_val,
5276 Register thread,
5277 Register tmp,
5278 bool tosca_live,
5279 bool expand_call) {
5280
5281 // If expand_call is true then we expand the call_VM_leaf macro
5282 // directly to skip generating the check by
5283 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5284
5285 #ifdef _LP64
5286 assert(thread == r15_thread, "must be");
5287 #endif // _LP64
5288
5289 Label done;
5290 Label runtime;
5291
5292 assert(pre_val != noreg, "check this code");
5293
5294 if (obj != noreg) {
5295 assert_different_registers(obj, pre_val, tmp);
5296 assert(pre_val != rax, "check this code");
5297 }
5298
5299 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5300 SATBMarkQueue::byte_offset_of_active()));
5301 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5302 SATBMarkQueue::byte_offset_of_index()));
5303 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5304 SATBMarkQueue::byte_offset_of_buf()));
5305
5306
5307 // Is marking active?
5308 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5309 cmpl(in_progress, 0);
5310 } else {
5311 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5312 cmpb(in_progress, 0);
5313 }
5314 jcc(Assembler::equal, done);
5315
5316 // Do we need to load the previous value?
5317 if (obj != noreg) {
5318 load_heap_oop(pre_val, Address(obj, 0));
5319 }
5320
5321 // Is the previous value null?
5322 cmpptr(pre_val, (int32_t) NULL_WORD);
5323 jcc(Assembler::equal, done);
5324
5325 // Can we store original value in the thread's buffer?
5326 // Is index == 0?
5327 // (The index field is typed as size_t.)
5328
5329 movptr(tmp, index); // tmp := *index_adr
5330 cmpptr(tmp, 0); // tmp == 0?
5331 jcc(Assembler::equal, runtime); // If yes, goto runtime
5332
5333 subptr(tmp, wordSize); // tmp := tmp - wordSize
5334 movptr(index, tmp); // *index_adr := tmp
5335 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
5336
5337 // Record the previous value
5338 movptr(Address(tmp, 0), pre_val);
5339 jmp(done);
5340
5341 bind(runtime);
5342 // save the live input values
5343 if(tosca_live) push(rax);
5344
5345 if (obj != noreg && obj != rax)
5346 push(obj);
5347
5348 if (pre_val != rax)
5349 push(pre_val);
5350
5351 // Calling the runtime using the regular call_VM_leaf mechanism generates
5352 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5353 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5354 //
5355 // If we care generating the pre-barrier without a frame (e.g. in the
5356 // intrinsified Reference.get() routine) then ebp might be pointing to
5357 // the caller frame and so this check will most likely fail at runtime.
5358 //
5359 // Expanding the call directly bypasses the generation of the check.
5360 // So when we do not have have a full interpreter frame on the stack
5361 // expand_call should be passed true.
5362
5363 NOT_LP64( push(thread); )
5364
5365 if (expand_call) {
5366 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5367 pass_arg1(this, thread);
5368 pass_arg0(this, pre_val);
5369 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5370 } else {
5371 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5372 }
5373
5374 NOT_LP64( pop(thread); )
5375
5376 // save the live input values
5377 if (pre_val != rax)
5378 pop(pre_val);
5379
5380 if (obj != noreg && obj != rax)
5381 pop(obj);
5382
5383 if(tosca_live) pop(rax);
5384
5385 bind(done);
5386 }
5387
5388 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5389 Register new_val,
5390 Register thread,
5391 Register tmp,
5392 Register tmp2) {
5393 #ifdef _LP64
5394 assert(thread == r15_thread, "must be");
5395 #endif // _LP64
5396
5397 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5398 DirtyCardQueue::byte_offset_of_index()));
5399 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5400 DirtyCardQueue::byte_offset_of_buf()));
5401
5402 CardTableModRefBS* ct =
5403 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
5404 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5405
5406 Label done;
5407 Label runtime;
5408
5409 // Does store cross heap regions?
5410
5411 movptr(tmp, store_addr);
5412 xorptr(tmp, new_val);
5413 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5414 jcc(Assembler::equal, done);
5415
5416 // crosses regions, storing NULL?
5417
5418 cmpptr(new_val, (int32_t) NULL_WORD);
5419 jcc(Assembler::equal, done);
5420
5421 // storing region crossing non-NULL, is card already dirty?
5422
5423 const Register card_addr = tmp;
5424 const Register cardtable = tmp2;
5425
5426 movptr(card_addr, store_addr);
5427 shrptr(card_addr, CardTableModRefBS::card_shift);
5428 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5429 // a valid address and therefore is not properly handled by the relocation code.
5430 movptr(cardtable, (intptr_t)ct->byte_map_base);
5431 addptr(card_addr, cardtable);
5432
5433 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5434 jcc(Assembler::equal, done);
5435
5436 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5437 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5438 jcc(Assembler::equal, done);
5439
5440
5441 // storing a region crossing, non-NULL oop, card is clean.
5442 // dirty card and log.
5443
5444 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5445
5446 cmpl(queue_index, 0);
5447 jcc(Assembler::equal, runtime);
5448 subl(queue_index, wordSize);
5449 movptr(tmp2, buffer);
5450 #ifdef _LP64
5451 movslq(rscratch1, queue_index);
5452 addq(tmp2, rscratch1);
5453 movq(Address(tmp2, 0), card_addr);
5454 #else
5455 addl(tmp2, queue_index);
5456 movl(Address(tmp2, 0), card_addr);
5457 #endif
5458 jmp(done);
5459
5460 bind(runtime);
5461 // save the live input values
5462 push(store_addr);
5463 push(new_val);
5464 #ifdef _LP64
5465 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5466 #else
5467 push(thread);
5468 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5469 pop(thread);
5470 #endif
5471 pop(new_val);
5472 pop(store_addr);
5473
5474 bind(done);
5475 }
5476
5477 #endif // INCLUDE_ALL_GCS
5478 //////////////////////////////////////////////////////////////////////////////////
5479
5480
5481 void MacroAssembler::store_check(Register obj, Address dst) {
5482 store_check(obj);
5483 }
5484
5485 void MacroAssembler::store_check(Register obj) {
5486 // Does a store check for the oop in register obj. The content of
5487 // register obj is destroyed afterwards.
5488 BarrierSet* bs = Universe::heap()->barrier_set();
5489 assert(bs->kind() == BarrierSet::CardTableForRS ||
5490 bs->kind() == BarrierSet::CardTableExtension,
5491 "Wrong barrier set kind");
5492
5493 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5494 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5495
5496 shrptr(obj, CardTableModRefBS::card_shift);
5497
5498 Address card_addr;
5499
5500 // The calculation for byte_map_base is as follows:
5501 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5502 // So this essentially converts an address to a displacement and it will
5503 // never need to be relocated. On 64bit however the value may be too
5504 // large for a 32bit displacement.
5505 intptr_t disp = (intptr_t) ct->byte_map_base;
5506 if (is_simm32(disp)) {
5507 card_addr = Address(noreg, obj, Address::times_1, disp);
5508 } else {
5509 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5510 // displacement and done in a single instruction given favorable mapping and a
5511 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5512 // entry and that entry is not properly handled by the relocation code.
5513 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5514 Address index(noreg, obj, Address::times_1);
5515 card_addr = as_Address(ArrayAddress(cardtable, index));
5516 }
5517
5518 int dirty = CardTableModRefBS::dirty_card_val();
5519 if (UseCondCardMark) {
5520 Label L_already_dirty;
5521 if (UseConcMarkSweepGC) {
5522 membar(Assembler::StoreLoad);
5523 }
5524 cmpb(card_addr, dirty);
5525 jcc(Assembler::equal, L_already_dirty);
5526 movb(card_addr, dirty);
5527 bind(L_already_dirty);
5528 } else {
5529 movb(card_addr, dirty);
5530 }
5531 }
5532
5533 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5534 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5535 }
5536
5537 // Force generation of a 4 byte immediate value even if it fits into 8bit
5538 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5539 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5540 }
5541
5542 void MacroAssembler::subptr(Register dst, Register src) {
5543 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5544 }
5545
5546 // C++ bool manipulation
5547 void MacroAssembler::testbool(Register dst) {
5548 if(sizeof(bool) == 1)
5549 testb(dst, 0xff);
5550 else if(sizeof(bool) == 2) {
5551 // testw implementation needed for two byte bools
5552 ShouldNotReachHere();
5553 } else if(sizeof(bool) == 4)
5554 testl(dst, dst);
5555 else
5556 // unsupported
5557 ShouldNotReachHere();
5558 }
5559
5560 void MacroAssembler::testptr(Register dst, Register src) {
5561 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5562 }
5563
5564 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5565 void MacroAssembler::tlab_allocate(Register obj,
5566 Register var_size_in_bytes,
5567 int con_size_in_bytes,
5568 Register t1,
5569 Register t2,
5570 Label& slow_case) {
5571 assert_different_registers(obj, t1, t2);
5572 assert_different_registers(obj, var_size_in_bytes, t1);
5573 Register end = t2;
5574 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5575
5576 verify_tlab();
5577
5578 NOT_LP64(get_thread(thread));
5579
5580 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5581 if (var_size_in_bytes == noreg) {
5582 lea(end, Address(obj, con_size_in_bytes));
5583 } else {
5584 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5585 }
5586 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5587 jcc(Assembler::above, slow_case);
5588
5589 // update the tlab top pointer
5590 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5591
5592 // recover var_size_in_bytes if necessary
5593 if (var_size_in_bytes == end) {
5594 subptr(var_size_in_bytes, obj);
5595 }
5596 verify_tlab();
5597 }
5598
5599 // Preserves rbx, and rdx.
5600 Register MacroAssembler::tlab_refill(Label& retry,
5601 Label& try_eden,
5602 Label& slow_case) {
5603 Register top = rax;
5604 Register t1 = rcx; // object size
5605 Register t2 = rsi;
5606 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5607 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5608 Label do_refill, discard_tlab;
5609
5610 if (!Universe::heap()->supports_inline_contig_alloc()) {
5611 // No allocation in the shared eden.
5612 jmp(slow_case);
5613 }
5614
5615 NOT_LP64(get_thread(thread_reg));
5616
5617 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5618 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5619
5620 // calculate amount of free space
5621 subptr(t1, top);
5622 shrptr(t1, LogHeapWordSize);
5623
5624 // Retain tlab and allocate object in shared space if
5625 // the amount free in the tlab is too large to discard.
5626 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5627 jcc(Assembler::lessEqual, discard_tlab);
5628
5629 // Retain
5630 // %%% yuck as movptr...
5631 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5632 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5633 if (TLABStats) {
5634 // increment number of slow_allocations
5635 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5636 }
5637 jmp(try_eden);
5638
5639 bind(discard_tlab);
5640 if (TLABStats) {
5641 // increment number of refills
5642 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5643 // accumulate wastage -- t1 is amount free in tlab
5644 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5645 }
5646
5647 // if tlab is currently allocated (top or end != null) then
5648 // fill [top, end + alignment_reserve) with array object
5649 testptr(top, top);
5650 jcc(Assembler::zero, do_refill);
5651
5652 // set up the mark word
5653 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5654 // set the length to the remaining space
5655 subptr(t1, typeArrayOopDesc::header_size(T_INT));
5656 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5657 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5658 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5659 // set klass to intArrayKlass
5660 // dubious reloc why not an oop reloc?
5661 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5662 // store klass last. concurrent gcs assumes klass length is valid if
5663 // klass field is not null.
5664 store_klass(top, t1);
5665
5666 movptr(t1, top);
5667 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5668 incr_allocated_bytes(thread_reg, t1, 0);
5669
5670 // refill the tlab with an eden allocation
5671 bind(do_refill);
5672 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5673 shlptr(t1, LogHeapWordSize);
5674 // allocate new tlab, address returned in top
5675 eden_allocate(top, t1, 0, t2, slow_case);
5676
5677 // Check that t1 was preserved in eden_allocate.
5678 #ifdef ASSERT
5679 if (UseTLAB) {
5680 Label ok;
5681 Register tsize = rsi;
5682 assert_different_registers(tsize, thread_reg, t1);
5683 push(tsize);
5684 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5685 shlptr(tsize, LogHeapWordSize);
5686 cmpptr(t1, tsize);
5687 jcc(Assembler::equal, ok);
5688 STOP("assert(t1 != tlab size)");
5689 should_not_reach_here();
5690
5691 bind(ok);
5692 pop(tsize);
5693 }
5694 #endif
5695 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5696 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5697 addptr(top, t1);
5698 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5699 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5700
5701 if (ZeroTLAB) {
5702 // This is a fast TLAB refill, therefore the GC is not notified of it.
5703 // So compiled code must fill the new TLAB with zeroes.
5704 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5705 zero_memory(top, t1, 0, t2);
5706 }
5707
5708 verify_tlab();
5709 jmp(retry);
5710
5711 return thread_reg; // for use by caller
5712 }
5713
5714 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5715 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5716 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5717 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5718 Label done;
5719
5720 testptr(length_in_bytes, length_in_bytes);
5721 jcc(Assembler::zero, done);
5722
5723 // initialize topmost word, divide index by 2, check if odd and test if zero
5724 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5725 #ifdef ASSERT
5726 {
5727 Label L;
5728 testptr(length_in_bytes, BytesPerWord - 1);
5729 jcc(Assembler::zero, L);
5730 stop("length must be a multiple of BytesPerWord");
5731 bind(L);
5732 }
5733 #endif
5734 Register index = length_in_bytes;
5735 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5736 if (UseIncDec) {
5737 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5738 } else {
5739 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5740 shrptr(index, 1);
5741 }
5742 #ifndef _LP64
5743 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5744 {
5745 Label even;
5746 // note: if index was a multiple of 8, then it cannot
5747 // be 0 now otherwise it must have been 0 before
5748 // => if it is even, we don't need to check for 0 again
5749 jcc(Assembler::carryClear, even);
5750 // clear topmost word (no jump would be needed if conditional assignment worked here)
5751 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5752 // index could be 0 now, must check again
5753 jcc(Assembler::zero, done);
5754 bind(even);
5755 }
5756 #endif // !_LP64
5757 // initialize remaining object fields: index is a multiple of 2 now
5758 {
5759 Label loop;
5760 bind(loop);
5761 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5762 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5763 decrement(index);
5764 jcc(Assembler::notZero, loop);
5765 }
5766
5767 bind(done);
5768 }
5769
5770 void MacroAssembler::incr_allocated_bytes(Register thread,
5771 Register var_size_in_bytes,
5772 int con_size_in_bytes,
5773 Register t1) {
5774 if (!thread->is_valid()) {
5775 #ifdef _LP64
5776 thread = r15_thread;
5777 #else
5778 assert(t1->is_valid(), "need temp reg");
5779 thread = t1;
5780 get_thread(thread);
5781 #endif
5782 }
5783
5784 #ifdef _LP64
5785 if (var_size_in_bytes->is_valid()) {
5786 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5787 } else {
5788 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5789 }
5790 #else
5791 if (var_size_in_bytes->is_valid()) {
5792 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5793 } else {
5794 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5795 }
5796 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5797 #endif
5798 }
5799
5800 // Look up the method for a megamorphic invokeinterface call.
5801 // The target method is determined by <intf_klass, itable_index>.
5802 // The receiver klass is in recv_klass.
5803 // On success, the result will be in method_result, and execution falls through.
5804 // On failure, execution transfers to the given label.
5805 void MacroAssembler::lookup_interface_method(Register recv_klass,
5806 Register intf_klass,
5807 RegisterOrConstant itable_index,
5808 Register method_result,
5809 Register scan_temp,
5810 Label& L_no_such_interface) {
5811 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5812 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5813 "caller must use same register for non-constant itable index as for method");
5814
5815 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5816 int vtable_base = in_bytes(Klass::vtable_start_offset());
5817 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5818 int scan_step = itableOffsetEntry::size() * wordSize;
5819 int vte_size = vtableEntry::size_in_bytes();
5820 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5821 assert(vte_size == wordSize, "else adjust times_vte_scale");
5822
5823 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5824
5825 // %%% Could store the aligned, prescaled offset in the klassoop.
5826 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5827
5828 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5829 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5830 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5831
5832 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5833 // if (scan->interface() == intf) {
5834 // result = (klass + scan->offset() + itable_index);
5835 // }
5836 // }
5837 Label search, found_method;
5838
5839 for (int peel = 1; peel >= 0; peel--) {
5840 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5841 cmpptr(intf_klass, method_result);
5842
5843 if (peel) {
5844 jccb(Assembler::equal, found_method);
5845 } else {
5846 jccb(Assembler::notEqual, search);
5847 // (invert the test to fall through to found_method...)
5848 }
5849
5850 if (!peel) break;
5851
5852 bind(search);
5853
5854 // Check that the previous entry is non-null. A null entry means that
5855 // the receiver class doesn't implement the interface, and wasn't the
5856 // same as when the caller was compiled.
5857 testptr(method_result, method_result);
5858 jcc(Assembler::zero, L_no_such_interface);
5859 addptr(scan_temp, scan_step);
5860 }
5861
5862 bind(found_method);
5863
5864 // Got a hit.
5865 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5866 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5867 }
5868
5869
5870 // virtual method calling
5871 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5872 RegisterOrConstant vtable_index,
5873 Register method_result) {
5874 const int base = in_bytes(Klass::vtable_start_offset());
5875 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5876 Address vtable_entry_addr(recv_klass,
5877 vtable_index, Address::times_ptr,
5878 base + vtableEntry::method_offset_in_bytes());
5879 movptr(method_result, vtable_entry_addr);
5880 }
5881
5882
5883 void MacroAssembler::check_klass_subtype(Register sub_klass,
5884 Register super_klass,
5885 Register temp_reg,
5886 Label& L_success) {
5887 Label L_failure;
5888 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5889 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5890 bind(L_failure);
5891 }
5892
5893
5894 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5895 Register super_klass,
5896 Register temp_reg,
5897 Label* L_success,
5898 Label* L_failure,
5899 Label* L_slow_path,
5900 RegisterOrConstant super_check_offset) {
5901 assert_different_registers(sub_klass, super_klass, temp_reg);
5902 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5903 if (super_check_offset.is_register()) {
5904 assert_different_registers(sub_klass, super_klass,
5905 super_check_offset.as_register());
5906 } else if (must_load_sco) {
5907 assert(temp_reg != noreg, "supply either a temp or a register offset");
5908 }
5909
5910 Label L_fallthrough;
5911 int label_nulls = 0;
5912 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5913 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5914 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5915 assert(label_nulls <= 1, "at most one NULL in the batch");
5916
5917 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5918 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5919 Address super_check_offset_addr(super_klass, sco_offset);
5920
5921 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5922 // range of a jccb. If this routine grows larger, reconsider at
5923 // least some of these.
5924 #define local_jcc(assembler_cond, label) \
5925 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5926 else jcc( assembler_cond, label) /*omit semi*/
5927
5928 // Hacked jmp, which may only be used just before L_fallthrough.
5929 #define final_jmp(label) \
5930 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5931 else jmp(label) /*omit semi*/
5932
5933 // If the pointers are equal, we are done (e.g., String[] elements).
5934 // This self-check enables sharing of secondary supertype arrays among
5935 // non-primary types such as array-of-interface. Otherwise, each such
5936 // type would need its own customized SSA.
5937 // We move this check to the front of the fast path because many
5938 // type checks are in fact trivially successful in this manner,
5939 // so we get a nicely predicted branch right at the start of the check.
5940 cmpptr(sub_klass, super_klass);
5941 local_jcc(Assembler::equal, *L_success);
5942
5943 // Check the supertype display:
5944 if (must_load_sco) {
5945 // Positive movl does right thing on LP64.
5946 movl(temp_reg, super_check_offset_addr);
5947 super_check_offset = RegisterOrConstant(temp_reg);
5948 }
5949 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5950 cmpptr(super_klass, super_check_addr); // load displayed supertype
5951
5952 // This check has worked decisively for primary supers.
5953 // Secondary supers are sought in the super_cache ('super_cache_addr').
5954 // (Secondary supers are interfaces and very deeply nested subtypes.)
5955 // This works in the same check above because of a tricky aliasing
5956 // between the super_cache and the primary super display elements.
5957 // (The 'super_check_addr' can address either, as the case requires.)
5958 // Note that the cache is updated below if it does not help us find
5959 // what we need immediately.
5960 // So if it was a primary super, we can just fail immediately.
5961 // Otherwise, it's the slow path for us (no success at this point).
5962
5963 if (super_check_offset.is_register()) {
5964 local_jcc(Assembler::equal, *L_success);
5965 cmpl(super_check_offset.as_register(), sc_offset);
5966 if (L_failure == &L_fallthrough) {
5967 local_jcc(Assembler::equal, *L_slow_path);
5968 } else {
5969 local_jcc(Assembler::notEqual, *L_failure);
5970 final_jmp(*L_slow_path);
5971 }
5972 } else if (super_check_offset.as_constant() == sc_offset) {
5973 // Need a slow path; fast failure is impossible.
5974 if (L_slow_path == &L_fallthrough) {
5975 local_jcc(Assembler::equal, *L_success);
5976 } else {
5977 local_jcc(Assembler::notEqual, *L_slow_path);
5978 final_jmp(*L_success);
5979 }
5980 } else {
5981 // No slow path; it's a fast decision.
5982 if (L_failure == &L_fallthrough) {
5983 local_jcc(Assembler::equal, *L_success);
5984 } else {
5985 local_jcc(Assembler::notEqual, *L_failure);
5986 final_jmp(*L_success);
5987 }
5988 }
5989
5990 bind(L_fallthrough);
5991
5992 #undef local_jcc
5993 #undef final_jmp
5994 }
5995
5996
5997 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5998 Register super_klass,
5999 Register temp_reg,
6000 Register temp2_reg,
6001 Label* L_success,
6002 Label* L_failure,
6003 bool set_cond_codes) {
6004 assert_different_registers(sub_klass, super_klass, temp_reg);
6005 if (temp2_reg != noreg)
6006 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
6007 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
6008
6009 Label L_fallthrough;
6010 int label_nulls = 0;
6011 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
6012 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
6013 assert(label_nulls <= 1, "at most one NULL in the batch");
6014
6015 // a couple of useful fields in sub_klass:
6016 int ss_offset = in_bytes(Klass::secondary_supers_offset());
6017 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
6018 Address secondary_supers_addr(sub_klass, ss_offset);
6019 Address super_cache_addr( sub_klass, sc_offset);
6020
6021 // Do a linear scan of the secondary super-klass chain.
6022 // This code is rarely used, so simplicity is a virtue here.
6023 // The repne_scan instruction uses fixed registers, which we must spill.
6024 // Don't worry too much about pre-existing connections with the input regs.
6025
6026 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
6027 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
6028
6029 // Get super_klass value into rax (even if it was in rdi or rcx).
6030 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
6031 if (super_klass != rax || UseCompressedOops) {
6032 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
6033 mov(rax, super_klass);
6034 }
6035 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
6036 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
6037
6038 #ifndef PRODUCT
6039 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
6040 ExternalAddress pst_counter_addr((address) pst_counter);
6041 NOT_LP64( incrementl(pst_counter_addr) );
6042 LP64_ONLY( lea(rcx, pst_counter_addr) );
6043 LP64_ONLY( incrementl(Address(rcx, 0)) );
6044 #endif //PRODUCT
6045
6046 // We will consult the secondary-super array.
6047 movptr(rdi, secondary_supers_addr);
6048 // Load the array length. (Positive movl does right thing on LP64.)
6049 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
6050 // Skip to start of data.
6051 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
6052
6053 // Scan RCX words at [RDI] for an occurrence of RAX.
6054 // Set NZ/Z based on last compare.
6055 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
6056 // not change flags (only scas instruction which is repeated sets flags).
6057 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
6058
6059 testptr(rax,rax); // Set Z = 0
6060 repne_scan();
6061
6062 // Unspill the temp. registers:
6063 if (pushed_rdi) pop(rdi);
6064 if (pushed_rcx) pop(rcx);
6065 if (pushed_rax) pop(rax);
6066
6067 if (set_cond_codes) {
6068 // Special hack for the AD files: rdi is guaranteed non-zero.
6069 assert(!pushed_rdi, "rdi must be left non-NULL");
6070 // Also, the condition codes are properly set Z/NZ on succeed/failure.
6071 }
6072
6073 if (L_failure == &L_fallthrough)
6074 jccb(Assembler::notEqual, *L_failure);
6075 else jcc(Assembler::notEqual, *L_failure);
6076
6077 // Success. Cache the super we found and proceed in triumph.
6078 movptr(super_cache_addr, super_klass);
6079
6080 if (L_success != &L_fallthrough) {
6081 jmp(*L_success);
6082 }
6083
6084 #undef IS_A_TEMP
6085
6086 bind(L_fallthrough);
6087 }
6088
6089
6090 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
6091 if (VM_Version::supports_cmov()) {
6092 cmovl(cc, dst, src);
6093 } else {
6094 Label L;
6095 jccb(negate_condition(cc), L);
6096 movl(dst, src);
6097 bind(L);
6098 }
6099 }
6100
6101 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
6102 if (VM_Version::supports_cmov()) {
6103 cmovl(cc, dst, src);
6104 } else {
6105 Label L;
6106 jccb(negate_condition(cc), L);
6107 movl(dst, src);
6108 bind(L);
6109 }
6110 }
6111
6112 void MacroAssembler::verify_oop(Register reg, const char* s) {
6113 if (!VerifyOops) return;
6114
6115 // Pass register number to verify_oop_subroutine
6116 const char* b = NULL;
6117 {
6118 ResourceMark rm;
6119 stringStream ss;
6120 ss.print("verify_oop: %s: %s", reg->name(), s);
6121 b = code_string(ss.as_string());
6122 }
6123 BLOCK_COMMENT("verify_oop {");
6124 #ifdef _LP64
6125 push(rscratch1); // save r10, trashed by movptr()
6126 #endif
6127 push(rax); // save rax,
6128 push(reg); // pass register argument
6129 ExternalAddress buffer((address) b);
6130 // avoid using pushptr, as it modifies scratch registers
6131 // and our contract is not to modify anything
6132 movptr(rax, buffer.addr());
6133 push(rax);
6134 // call indirectly to solve generation ordering problem
6135 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6136 call(rax);
6137 // Caller pops the arguments (oop, message) and restores rax, r10
6138 BLOCK_COMMENT("} verify_oop");
6139 }
6140
6141
6142 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
6143 Register tmp,
6144 int offset) {
6145 intptr_t value = *delayed_value_addr;
6146 if (value != 0)
6147 return RegisterOrConstant(value + offset);
6148
6149 // load indirectly to solve generation ordering problem
6150 movptr(tmp, ExternalAddress((address) delayed_value_addr));
6151
6152 #ifdef ASSERT
6153 { Label L;
6154 testptr(tmp, tmp);
6155 if (WizardMode) {
6156 const char* buf = NULL;
6157 {
6158 ResourceMark rm;
6159 stringStream ss;
6160 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
6161 buf = code_string(ss.as_string());
6162 }
6163 jcc(Assembler::notZero, L);
6164 STOP(buf);
6165 } else {
6166 jccb(Assembler::notZero, L);
6167 hlt();
6168 }
6169 bind(L);
6170 }
6171 #endif
6172
6173 if (offset != 0)
6174 addptr(tmp, offset);
6175
6176 return RegisterOrConstant(tmp);
6177 }
6178
6179
6180 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6181 int extra_slot_offset) {
6182 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6183 int stackElementSize = Interpreter::stackElementSize;
6184 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6185 #ifdef ASSERT
6186 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6187 assert(offset1 - offset == stackElementSize, "correct arithmetic");
6188 #endif
6189 Register scale_reg = noreg;
6190 Address::ScaleFactor scale_factor = Address::no_scale;
6191 if (arg_slot.is_constant()) {
6192 offset += arg_slot.as_constant() * stackElementSize;
6193 } else {
6194 scale_reg = arg_slot.as_register();
6195 scale_factor = Address::times(stackElementSize);
6196 }
6197 offset += wordSize; // return PC is on stack
6198 return Address(rsp, scale_reg, scale_factor, offset);
6199 }
6200
6201
6202 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6203 if (!VerifyOops) return;
6204
6205 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6206 // Pass register number to verify_oop_subroutine
6207 const char* b = NULL;
6208 {
6209 ResourceMark rm;
6210 stringStream ss;
6211 ss.print("verify_oop_addr: %s", s);
6212 b = code_string(ss.as_string());
6213 }
6214 #ifdef _LP64
6215 push(rscratch1); // save r10, trashed by movptr()
6216 #endif
6217 push(rax); // save rax,
6218 // addr may contain rsp so we will have to adjust it based on the push
6219 // we just did (and on 64 bit we do two pushes)
6220 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6221 // stores rax into addr which is backwards of what was intended.
6222 if (addr.uses(rsp)) {
6223 lea(rax, addr);
6224 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6225 } else {
6226 pushptr(addr);
6227 }
6228
6229 ExternalAddress buffer((address) b);
6230 // pass msg argument
6231 // avoid using pushptr, as it modifies scratch registers
6232 // and our contract is not to modify anything
6233 movptr(rax, buffer.addr());
6234 push(rax);
6235
6236 // call indirectly to solve generation ordering problem
6237 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6238 call(rax);
6239 // Caller pops the arguments (addr, message) and restores rax, r10.
6240 }
6241
6242 void MacroAssembler::verify_tlab() {
6243 #ifdef ASSERT
6244 if (UseTLAB && VerifyOops) {
6245 Label next, ok;
6246 Register t1 = rsi;
6247 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6248
6249 push(t1);
6250 NOT_LP64(push(thread_reg));
6251 NOT_LP64(get_thread(thread_reg));
6252
6253 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6254 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6255 jcc(Assembler::aboveEqual, next);
6256 STOP("assert(top >= start)");
6257 should_not_reach_here();
6258
6259 bind(next);
6260 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6261 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6262 jcc(Assembler::aboveEqual, ok);
6263 STOP("assert(top <= end)");
6264 should_not_reach_here();
6265
6266 bind(ok);
6267 NOT_LP64(pop(thread_reg));
6268 pop(t1);
6269 }
6270 #endif
6271 }
6272
6273 class ControlWord {
6274 public:
6275 int32_t _value;
6276
6277 int rounding_control() const { return (_value >> 10) & 3 ; }
6278 int precision_control() const { return (_value >> 8) & 3 ; }
6279 bool precision() const { return ((_value >> 5) & 1) != 0; }
6280 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6281 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6282 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6283 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6284 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6285
6286 void print() const {
6287 // rounding control
6288 const char* rc;
6289 switch (rounding_control()) {
6290 case 0: rc = "round near"; break;
6291 case 1: rc = "round down"; break;
6292 case 2: rc = "round up "; break;
6293 case 3: rc = "chop "; break;
6294 };
6295 // precision control
6296 const char* pc;
6297 switch (precision_control()) {
6298 case 0: pc = "24 bits "; break;
6299 case 1: pc = "reserved"; break;
6300 case 2: pc = "53 bits "; break;
6301 case 3: pc = "64 bits "; break;
6302 };
6303 // flags
6304 char f[9];
6305 f[0] = ' ';
6306 f[1] = ' ';
6307 f[2] = (precision ()) ? 'P' : 'p';
6308 f[3] = (underflow ()) ? 'U' : 'u';
6309 f[4] = (overflow ()) ? 'O' : 'o';
6310 f[5] = (zero_divide ()) ? 'Z' : 'z';
6311 f[6] = (denormalized()) ? 'D' : 'd';
6312 f[7] = (invalid ()) ? 'I' : 'i';
6313 f[8] = '\x0';
6314 // output
6315 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6316 }
6317
6318 };
6319
6320 class StatusWord {
6321 public:
6322 int32_t _value;
6323
6324 bool busy() const { return ((_value >> 15) & 1) != 0; }
6325 bool C3() const { return ((_value >> 14) & 1) != 0; }
6326 bool C2() const { return ((_value >> 10) & 1) != 0; }
6327 bool C1() const { return ((_value >> 9) & 1) != 0; }
6328 bool C0() const { return ((_value >> 8) & 1) != 0; }
6329 int top() const { return (_value >> 11) & 7 ; }
6330 bool error_status() const { return ((_value >> 7) & 1) != 0; }
6331 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
6332 bool precision() const { return ((_value >> 5) & 1) != 0; }
6333 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6334 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6335 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6336 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6337 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6338
6339 void print() const {
6340 // condition codes
6341 char c[5];
6342 c[0] = (C3()) ? '3' : '-';
6343 c[1] = (C2()) ? '2' : '-';
6344 c[2] = (C1()) ? '1' : '-';
6345 c[3] = (C0()) ? '0' : '-';
6346 c[4] = '\x0';
6347 // flags
6348 char f[9];
6349 f[0] = (error_status()) ? 'E' : '-';
6350 f[1] = (stack_fault ()) ? 'S' : '-';
6351 f[2] = (precision ()) ? 'P' : '-';
6352 f[3] = (underflow ()) ? 'U' : '-';
6353 f[4] = (overflow ()) ? 'O' : '-';
6354 f[5] = (zero_divide ()) ? 'Z' : '-';
6355 f[6] = (denormalized()) ? 'D' : '-';
6356 f[7] = (invalid ()) ? 'I' : '-';
6357 f[8] = '\x0';
6358 // output
6359 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
6360 }
6361
6362 };
6363
6364 class TagWord {
6365 public:
6366 int32_t _value;
6367
6368 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
6369
6370 void print() const {
6371 printf("%04x", _value & 0xFFFF);
6372 }
6373
6374 };
6375
6376 class FPU_Register {
6377 public:
6378 int32_t _m0;
6379 int32_t _m1;
6380 int16_t _ex;
6381
6382 bool is_indefinite() const {
6383 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6384 }
6385
6386 void print() const {
6387 char sign = (_ex < 0) ? '-' : '+';
6388 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
6389 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
6390 };
6391
6392 };
6393
6394 class FPU_State {
6395 public:
6396 enum {
6397 register_size = 10,
6398 number_of_registers = 8,
6399 register_mask = 7
6400 };
6401
6402 ControlWord _control_word;
6403 StatusWord _status_word;
6404 TagWord _tag_word;
6405 int32_t _error_offset;
6406 int32_t _error_selector;
6407 int32_t _data_offset;
6408 int32_t _data_selector;
6409 int8_t _register[register_size * number_of_registers];
6410
6411 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6412 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
6413
6414 const char* tag_as_string(int tag) const {
6415 switch (tag) {
6416 case 0: return "valid";
6417 case 1: return "zero";
6418 case 2: return "special";
6419 case 3: return "empty";
6420 }
6421 ShouldNotReachHere();
6422 return NULL;
6423 }
6424
6425 void print() const {
6426 // print computation registers
6427 { int t = _status_word.top();
6428 for (int i = 0; i < number_of_registers; i++) {
6429 int j = (i - t) & register_mask;
6430 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6431 st(j)->print();
6432 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6433 }
6434 }
6435 printf("\n");
6436 // print control registers
6437 printf("ctrl = "); _control_word.print(); printf("\n");
6438 printf("stat = "); _status_word .print(); printf("\n");
6439 printf("tags = "); _tag_word .print(); printf("\n");
6440 }
6441
6442 };
6443
6444 class Flag_Register {
6445 public:
6446 int32_t _value;
6447
6448 bool overflow() const { return ((_value >> 11) & 1) != 0; }
6449 bool direction() const { return ((_value >> 10) & 1) != 0; }
6450 bool sign() const { return ((_value >> 7) & 1) != 0; }
6451 bool zero() const { return ((_value >> 6) & 1) != 0; }
6452 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
6453 bool parity() const { return ((_value >> 2) & 1) != 0; }
6454 bool carry() const { return ((_value >> 0) & 1) != 0; }
6455
6456 void print() const {
6457 // flags
6458 char f[8];
6459 f[0] = (overflow ()) ? 'O' : '-';
6460 f[1] = (direction ()) ? 'D' : '-';
6461 f[2] = (sign ()) ? 'S' : '-';
6462 f[3] = (zero ()) ? 'Z' : '-';
6463 f[4] = (auxiliary_carry()) ? 'A' : '-';
6464 f[5] = (parity ()) ? 'P' : '-';
6465 f[6] = (carry ()) ? 'C' : '-';
6466 f[7] = '\x0';
6467 // output
6468 printf("%08x flags = %s", _value, f);
6469 }
6470
6471 };
6472
6473 class IU_Register {
6474 public:
6475 int32_t _value;
6476
6477 void print() const {
6478 printf("%08x %11d", _value, _value);
6479 }
6480
6481 };
6482
6483 class IU_State {
6484 public:
6485 Flag_Register _eflags;
6486 IU_Register _rdi;
6487 IU_Register _rsi;
6488 IU_Register _rbp;
6489 IU_Register _rsp;
6490 IU_Register _rbx;
6491 IU_Register _rdx;
6492 IU_Register _rcx;
6493 IU_Register _rax;
6494
6495 void print() const {
6496 // computation registers
6497 printf("rax, = "); _rax.print(); printf("\n");
6498 printf("rbx, = "); _rbx.print(); printf("\n");
6499 printf("rcx = "); _rcx.print(); printf("\n");
6500 printf("rdx = "); _rdx.print(); printf("\n");
6501 printf("rdi = "); _rdi.print(); printf("\n");
6502 printf("rsi = "); _rsi.print(); printf("\n");
6503 printf("rbp, = "); _rbp.print(); printf("\n");
6504 printf("rsp = "); _rsp.print(); printf("\n");
6505 printf("\n");
6506 // control registers
6507 printf("flgs = "); _eflags.print(); printf("\n");
6508 }
6509 };
6510
6511
6512 class CPU_State {
6513 public:
6514 FPU_State _fpu_state;
6515 IU_State _iu_state;
6516
6517 void print() const {
6518 printf("--------------------------------------------------\n");
6519 _iu_state .print();
6520 printf("\n");
6521 _fpu_state.print();
6522 printf("--------------------------------------------------\n");
6523 }
6524
6525 };
6526
6527
6528 static void _print_CPU_state(CPU_State* state) {
6529 state->print();
6530 };
6531
6532
6533 void MacroAssembler::print_CPU_state() {
6534 push_CPU_state();
6535 push(rsp); // pass CPU state
6536 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6537 addptr(rsp, wordSize); // discard argument
6538 pop_CPU_state();
6539 }
6540
6541
6542 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6543 static int counter = 0;
6544 FPU_State* fs = &state->_fpu_state;
6545 counter++;
6546 // For leaf calls, only verify that the top few elements remain empty.
6547 // We only need 1 empty at the top for C2 code.
6548 if( stack_depth < 0 ) {
6549 if( fs->tag_for_st(7) != 3 ) {
6550 printf("FPR7 not empty\n");
6551 state->print();
6552 assert(false, "error");
6553 return false;
6554 }
6555 return true; // All other stack states do not matter
6556 }
6557
6558 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6559 "bad FPU control word");
6560
6561 // compute stack depth
6562 int i = 0;
6563 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6564 int d = i;
6565 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6566 // verify findings
6567 if (i != FPU_State::number_of_registers) {
6568 // stack not contiguous
6569 printf("%s: stack not contiguous at ST%d\n", s, i);
6570 state->print();
6571 assert(false, "error");
6572 return false;
6573 }
6574 // check if computed stack depth corresponds to expected stack depth
6575 if (stack_depth < 0) {
6576 // expected stack depth is -stack_depth or less
6577 if (d > -stack_depth) {
6578 // too many elements on the stack
6579 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6580 state->print();
6581 assert(false, "error");
6582 return false;
6583 }
6584 } else {
6585 // expected stack depth is stack_depth
6586 if (d != stack_depth) {
6587 // wrong stack depth
6588 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6589 state->print();
6590 assert(false, "error");
6591 return false;
6592 }
6593 }
6594 // everything is cool
6595 return true;
6596 }
6597
6598
6599 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6600 if (!VerifyFPU) return;
6601 push_CPU_state();
6602 push(rsp); // pass CPU state
6603 ExternalAddress msg((address) s);
6604 // pass message string s
6605 pushptr(msg.addr());
6606 push(stack_depth); // pass stack depth
6607 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6608 addptr(rsp, 3 * wordSize); // discard arguments
6609 // check for error
6610 { Label L;
6611 testl(rax, rax);
6612 jcc(Assembler::notZero, L);
6613 int3(); // break if error condition
6614 bind(L);
6615 }
6616 pop_CPU_state();
6617 }
6618
6619 void MacroAssembler::restore_cpu_control_state_after_jni() {
6620 // Either restore the MXCSR register after returning from the JNI Call
6621 // or verify that it wasn't changed (with -Xcheck:jni flag).
6622 if (VM_Version::supports_sse()) {
6623 if (RestoreMXCSROnJNICalls) {
6624 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6625 } else if (CheckJNICalls) {
6626 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6627 }
6628 }
6629 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6630 vzeroupper();
6631 // Reset k1 to 0xffff.
6632 if (VM_Version::supports_evex()) {
6633 push(rcx);
6634 movl(rcx, 0xffff);
6635 kmovwl(k1, rcx);
6636 pop(rcx);
6637 }
6638
6639 #ifndef _LP64
6640 // Either restore the x87 floating pointer control word after returning
6641 // from the JNI call or verify that it wasn't changed.
6642 if (CheckJNICalls) {
6643 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6644 }
6645 #endif // _LP64
6646 }
6647
6648 // ((OopHandle)result).resolve();
6649 void MacroAssembler::resolve_oop_handle(Register result) {
6650 // OopHandle::resolve is an indirection.
6651 movptr(result, Address(result, 0));
6652 }
6653
6654 void MacroAssembler::load_mirror(Register mirror, Register method) {
6655 // get mirror
6656 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6657 movptr(mirror, Address(method, Method::const_offset()));
6658 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6659 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6660 movptr(mirror, Address(mirror, mirror_offset));
6661 resolve_oop_handle(mirror);
6662 }
6663
6664 void MacroAssembler::load_klass(Register dst, Register src) {
6665 #ifdef _LP64
6666 if (UseCompressedClassPointers) {
6667 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6668 decode_klass_not_null(dst);
6669 } else
6670 #endif
6671 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6672 }
6673
6674 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6675 load_klass(dst, src);
6676 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6677 }
6678
6679 void MacroAssembler::store_klass(Register dst, Register src) {
6680 #ifdef _LP64
6681 if (UseCompressedClassPointers) {
6682 encode_klass_not_null(src);
6683 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6684 } else
6685 #endif
6686 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6687 }
6688
6689 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6690 #ifdef _LP64
6691 // FIXME: Must change all places where we try to load the klass.
6692 if (UseCompressedOops) {
6693 movl(dst, src);
6694 decode_heap_oop(dst);
6695 } else
6696 #endif
6697 movptr(dst, src);
6698 }
6699
6700 // Doesn't do verfication, generates fixed size code
6701 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6702 #ifdef _LP64
6703 if (UseCompressedOops) {
6704 movl(dst, src);
6705 decode_heap_oop_not_null(dst);
6706 } else
6707 #endif
6708 movptr(dst, src);
6709 }
6710
6711 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6712 #ifdef _LP64
6713 if (UseCompressedOops) {
6714 assert(!dst.uses(src), "not enough registers");
6715 encode_heap_oop(src);
6716 movl(dst, src);
6717 } else
6718 #endif
6719 movptr(dst, src);
6720 }
6721
6722 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6723 assert_different_registers(src1, tmp);
6724 #ifdef _LP64
6725 if (UseCompressedOops) {
6726 bool did_push = false;
6727 if (tmp == noreg) {
6728 tmp = rax;
6729 push(tmp);
6730 did_push = true;
6731 assert(!src2.uses(rsp), "can't push");
6732 }
6733 load_heap_oop(tmp, src2);
6734 cmpptr(src1, tmp);
6735 if (did_push) pop(tmp);
6736 } else
6737 #endif
6738 cmpptr(src1, src2);
6739 }
6740
6741 // Used for storing NULLs.
6742 void MacroAssembler::store_heap_oop_null(Address dst) {
6743 #ifdef _LP64
6744 if (UseCompressedOops) {
6745 movl(dst, (int32_t)NULL_WORD);
6746 } else {
6747 movslq(dst, (int32_t)NULL_WORD);
6748 }
6749 #else
6750 movl(dst, (int32_t)NULL_WORD);
6751 #endif
6752 }
6753
6754 #ifdef _LP64
6755 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6756 if (UseCompressedClassPointers) {
6757 // Store to klass gap in destination
6758 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6759 }
6760 }
6761
6762 #ifdef ASSERT
6763 void MacroAssembler::verify_heapbase(const char* msg) {
6764 assert (UseCompressedOops, "should be compressed");
6765 assert (Universe::heap() != NULL, "java heap should be initialized");
6766 if (CheckCompressedOops) {
6767 Label ok;
6768 push(rscratch1); // cmpptr trashes rscratch1
6769 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6770 jcc(Assembler::equal, ok);
6771 STOP(msg);
6772 bind(ok);
6773 pop(rscratch1);
6774 }
6775 }
6776 #endif
6777
6778 // Algorithm must match oop.inline.hpp encode_heap_oop.
6779 void MacroAssembler::encode_heap_oop(Register r) {
6780 #ifdef ASSERT
6781 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6782 #endif
6783 verify_oop(r, "broken oop in encode_heap_oop");
6784 if (Universe::narrow_oop_base() == NULL) {
6785 if (Universe::narrow_oop_shift() != 0) {
6786 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6787 shrq(r, LogMinObjAlignmentInBytes);
6788 }
6789 return;
6790 }
6791 testq(r, r);
6792 cmovq(Assembler::equal, r, r12_heapbase);
6793 subq(r, r12_heapbase);
6794 shrq(r, LogMinObjAlignmentInBytes);
6795 }
6796
6797 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6798 #ifdef ASSERT
6799 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6800 if (CheckCompressedOops) {
6801 Label ok;
6802 testq(r, r);
6803 jcc(Assembler::notEqual, ok);
6804 STOP("null oop passed to encode_heap_oop_not_null");
6805 bind(ok);
6806 }
6807 #endif
6808 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6809 if (Universe::narrow_oop_base() != NULL) {
6810 subq(r, r12_heapbase);
6811 }
6812 if (Universe::narrow_oop_shift() != 0) {
6813 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6814 shrq(r, LogMinObjAlignmentInBytes);
6815 }
6816 }
6817
6818 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6819 #ifdef ASSERT
6820 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6821 if (CheckCompressedOops) {
6822 Label ok;
6823 testq(src, src);
6824 jcc(Assembler::notEqual, ok);
6825 STOP("null oop passed to encode_heap_oop_not_null2");
6826 bind(ok);
6827 }
6828 #endif
6829 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6830 if (dst != src) {
6831 movq(dst, src);
6832 }
6833 if (Universe::narrow_oop_base() != NULL) {
6834 subq(dst, r12_heapbase);
6835 }
6836 if (Universe::narrow_oop_shift() != 0) {
6837 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6838 shrq(dst, LogMinObjAlignmentInBytes);
6839 }
6840 }
6841
6842 void MacroAssembler::decode_heap_oop(Register r) {
6843 #ifdef ASSERT
6844 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6845 #endif
6846 if (Universe::narrow_oop_base() == NULL) {
6847 if (Universe::narrow_oop_shift() != 0) {
6848 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6849 shlq(r, LogMinObjAlignmentInBytes);
6850 }
6851 } else {
6852 Label done;
6853 shlq(r, LogMinObjAlignmentInBytes);
6854 jccb(Assembler::equal, done);
6855 addq(r, r12_heapbase);
6856 bind(done);
6857 }
6858 verify_oop(r, "broken oop in decode_heap_oop");
6859 }
6860
6861 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6862 // Note: it will change flags
6863 assert (UseCompressedOops, "should only be used for compressed headers");
6864 assert (Universe::heap() != NULL, "java heap should be initialized");
6865 // Cannot assert, unverified entry point counts instructions (see .ad file)
6866 // vtableStubs also counts instructions in pd_code_size_limit.
6867 // Also do not verify_oop as this is called by verify_oop.
6868 if (Universe::narrow_oop_shift() != 0) {
6869 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6870 shlq(r, LogMinObjAlignmentInBytes);
6871 if (Universe::narrow_oop_base() != NULL) {
6872 addq(r, r12_heapbase);
6873 }
6874 } else {
6875 assert (Universe::narrow_oop_base() == NULL, "sanity");
6876 }
6877 }
6878
6879 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6880 // Note: it will change flags
6881 assert (UseCompressedOops, "should only be used for compressed headers");
6882 assert (Universe::heap() != NULL, "java heap should be initialized");
6883 // Cannot assert, unverified entry point counts instructions (see .ad file)
6884 // vtableStubs also counts instructions in pd_code_size_limit.
6885 // Also do not verify_oop as this is called by verify_oop.
6886 if (Universe::narrow_oop_shift() != 0) {
6887 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6888 if (LogMinObjAlignmentInBytes == Address::times_8) {
6889 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6890 } else {
6891 if (dst != src) {
6892 movq(dst, src);
6893 }
6894 shlq(dst, LogMinObjAlignmentInBytes);
6895 if (Universe::narrow_oop_base() != NULL) {
6896 addq(dst, r12_heapbase);
6897 }
6898 }
6899 } else {
6900 assert (Universe::narrow_oop_base() == NULL, "sanity");
6901 if (dst != src) {
6902 movq(dst, src);
6903 }
6904 }
6905 }
6906
6907 void MacroAssembler::encode_klass_not_null(Register r) {
6908 if (Universe::narrow_klass_base() != NULL) {
6909 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6910 assert(r != r12_heapbase, "Encoding a klass in r12");
6911 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6912 subq(r, r12_heapbase);
6913 }
6914 if (Universe::narrow_klass_shift() != 0) {
6915 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6916 shrq(r, LogKlassAlignmentInBytes);
6917 }
6918 if (Universe::narrow_klass_base() != NULL) {
6919 reinit_heapbase();
6920 }
6921 }
6922
6923 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6924 if (dst == src) {
6925 encode_klass_not_null(src);
6926 } else {
6927 if (Universe::narrow_klass_base() != NULL) {
6928 mov64(dst, (int64_t)Universe::narrow_klass_base());
6929 negq(dst);
6930 addq(dst, src);
6931 } else {
6932 movptr(dst, src);
6933 }
6934 if (Universe::narrow_klass_shift() != 0) {
6935 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6936 shrq(dst, LogKlassAlignmentInBytes);
6937 }
6938 }
6939 }
6940
6941 // Function instr_size_for_decode_klass_not_null() counts the instructions
6942 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6943 // when (Universe::heap() != NULL). Hence, if the instructions they
6944 // generate change, then this method needs to be updated.
6945 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6946 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6947 if (Universe::narrow_klass_base() != NULL) {
6948 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6949 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6950 } else {
6951 // longest load decode klass function, mov64, leaq
6952 return 16;
6953 }
6954 }
6955
6956 // !!! If the instructions that get generated here change then function
6957 // instr_size_for_decode_klass_not_null() needs to get updated.
6958 void MacroAssembler::decode_klass_not_null(Register r) {
6959 // Note: it will change flags
6960 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6961 assert(r != r12_heapbase, "Decoding a klass in r12");
6962 // Cannot assert, unverified entry point counts instructions (see .ad file)
6963 // vtableStubs also counts instructions in pd_code_size_limit.
6964 // Also do not verify_oop as this is called by verify_oop.
6965 if (Universe::narrow_klass_shift() != 0) {
6966 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6967 shlq(r, LogKlassAlignmentInBytes);
6968 }
6969 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6970 if (Universe::narrow_klass_base() != NULL) {
6971 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6972 addq(r, r12_heapbase);
6973 reinit_heapbase();
6974 }
6975 }
6976
6977 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6978 // Note: it will change flags
6979 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6980 if (dst == src) {
6981 decode_klass_not_null(dst);
6982 } else {
6983 // Cannot assert, unverified entry point counts instructions (see .ad file)
6984 // vtableStubs also counts instructions in pd_code_size_limit.
6985 // Also do not verify_oop as this is called by verify_oop.
6986 mov64(dst, (int64_t)Universe::narrow_klass_base());
6987 if (Universe::narrow_klass_shift() != 0) {
6988 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6989 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6990 leaq(dst, Address(dst, src, Address::times_8, 0));
6991 } else {
6992 addq(dst, src);
6993 }
6994 }
6995 }
6996
6997 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6998 assert (UseCompressedOops, "should only be used for compressed headers");
6999 assert (Universe::heap() != NULL, "java heap should be initialized");
7000 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7001 int oop_index = oop_recorder()->find_index(obj);
7002 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7003 mov_narrow_oop(dst, oop_index, rspec);
7004 }
7005
7006 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
7007 assert (UseCompressedOops, "should only be used for compressed headers");
7008 assert (Universe::heap() != NULL, "java heap should be initialized");
7009 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7010 int oop_index = oop_recorder()->find_index(obj);
7011 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7012 mov_narrow_oop(dst, oop_index, rspec);
7013 }
7014
7015 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
7016 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7017 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7018 int klass_index = oop_recorder()->find_index(k);
7019 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7020 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
7021 }
7022
7023 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
7024 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7025 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7026 int klass_index = oop_recorder()->find_index(k);
7027 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7028 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
7029 }
7030
7031 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
7032 assert (UseCompressedOops, "should only be used for compressed headers");
7033 assert (Universe::heap() != NULL, "java heap should be initialized");
7034 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7035 int oop_index = oop_recorder()->find_index(obj);
7036 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7037 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
7038 }
7039
7040 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
7041 assert (UseCompressedOops, "should only be used for compressed headers");
7042 assert (Universe::heap() != NULL, "java heap should be initialized");
7043 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7044 int oop_index = oop_recorder()->find_index(obj);
7045 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7046 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
7047 }
7048
7049 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
7050 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7051 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7052 int klass_index = oop_recorder()->find_index(k);
7053 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7054 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
7055 }
7056
7057 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
7058 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7059 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7060 int klass_index = oop_recorder()->find_index(k);
7061 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7062 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
7063 }
7064
7065 void MacroAssembler::reinit_heapbase() {
7066 if (UseCompressedOops || UseCompressedClassPointers) {
7067 if (Universe::heap() != NULL) {
7068 if (Universe::narrow_oop_base() == NULL) {
7069 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
7070 } else {
7071 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
7072 }
7073 } else {
7074 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
7075 }
7076 }
7077 }
7078
7079 #endif // _LP64
7080
7081 // C2 compiled method's prolog code.
7082 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
7083
7084 // WARNING: Initial instruction MUST be 5 bytes or longer so that
7085 // NativeJump::patch_verified_entry will be able to patch out the entry
7086 // code safely. The push to verify stack depth is ok at 5 bytes,
7087 // the frame allocation can be either 3 or 6 bytes. So if we don't do
7088 // stack bang then we must use the 6 byte frame allocation even if
7089 // we have no frame. :-(
7090 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
7091
7092 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
7093 // Remove word for return addr
7094 framesize -= wordSize;
7095 stack_bang_size -= wordSize;
7096
7097 // Calls to C2R adapters often do not accept exceptional returns.
7098 // We require that their callers must bang for them. But be careful, because
7099 // some VM calls (such as call site linkage) can use several kilobytes of
7100 // stack. But the stack safety zone should account for that.
7101 // See bugs 4446381, 4468289, 4497237.
7102 if (stack_bang_size > 0) {
7103 generate_stack_overflow_check(stack_bang_size);
7104
7105 // We always push rbp, so that on return to interpreter rbp, will be
7106 // restored correctly and we can correct the stack.
7107 push(rbp);
7108 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7109 if (PreserveFramePointer) {
7110 mov(rbp, rsp);
7111 }
7112 // Remove word for ebp
7113 framesize -= wordSize;
7114
7115 // Create frame
7116 if (framesize) {
7117 subptr(rsp, framesize);
7118 }
7119 } else {
7120 // Create frame (force generation of a 4 byte immediate value)
7121 subptr_imm32(rsp, framesize);
7122
7123 // Save RBP register now.
7124 framesize -= wordSize;
7125 movptr(Address(rsp, framesize), rbp);
7126 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7127 if (PreserveFramePointer) {
7128 movptr(rbp, rsp);
7129 if (framesize > 0) {
7130 addptr(rbp, framesize);
7131 }
7132 }
7133 }
7134
7135 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
7136 framesize -= wordSize;
7137 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
7138 }
7139
7140 #ifndef _LP64
7141 // If method sets FPU control word do it now
7142 if (fp_mode_24b) {
7143 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
7144 }
7145 if (UseSSE >= 2 && VerifyFPU) {
7146 verify_FPU(0, "FPU stack must be clean on entry");
7147 }
7148 #endif
7149
7150 #ifdef ASSERT
7151 if (VerifyStackAtCalls) {
7152 Label L;
7153 push(rax);
7154 mov(rax, rsp);
7155 andptr(rax, StackAlignmentInBytes-1);
7156 cmpptr(rax, StackAlignmentInBytes-wordSize);
7157 pop(rax);
7158 jcc(Assembler::equal, L);
7159 STOP("Stack is not properly aligned!");
7160 bind(L);
7161 }
7162 #endif
7163
7164 }
7165
7166 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
7167 // cnt - number of qwords (8-byte words).
7168 // base - start address, qword aligned.
7169 // is_large - if optimizers know cnt is larger than InitArrayShortSize
7170 assert(base==rdi, "base register must be edi for rep stos");
7171 assert(tmp==rax, "tmp register must be eax for rep stos");
7172 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7173 assert(InitArrayShortSize % BytesPerLong == 0,
7174 "InitArrayShortSize should be the multiple of BytesPerLong");
7175
7176 Label DONE;
7177
7178 xorptr(tmp, tmp);
7179
7180 if (!is_large) {
7181 Label LOOP, LONG;
7182 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7183 jccb(Assembler::greater, LONG);
7184
7185 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7186
7187 decrement(cnt);
7188 jccb(Assembler::negative, DONE); // Zero length
7189
7190 // Use individual pointer-sized stores for small counts:
7191 BIND(LOOP);
7192 movptr(Address(base, cnt, Address::times_ptr), tmp);
7193 decrement(cnt);
7194 jccb(Assembler::greaterEqual, LOOP);
7195 jmpb(DONE);
7196
7197 BIND(LONG);
7198 }
7199
7200 // Use longer rep-prefixed ops for non-small counts:
7201 if (UseFastStosb) {
7202 shlptr(cnt, 3); // convert to number of bytes
7203 rep_stosb();
7204 } else {
7205 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7206 rep_stos();
7207 }
7208
7209 BIND(DONE);
7210 }
7211
7212 #ifdef COMPILER2
7213
7214 // IndexOf for constant substrings with size >= 8 chars
7215 // which don't need to be loaded through stack.
7216 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7217 Register cnt1, Register cnt2,
7218 int int_cnt2, Register result,
7219 XMMRegister vec, Register tmp,
7220 int ae) {
7221 ShortBranchVerifier sbv(this);
7222 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7223 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7224
7225 // This method uses the pcmpestri instruction with bound registers
7226 // inputs:
7227 // xmm - substring
7228 // rax - substring length (elements count)
7229 // mem - scanned string
7230 // rdx - string length (elements count)
7231 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7232 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7233 // outputs:
7234 // rcx - matched index in string
7235 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7236 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7237 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7238 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7239 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7240
7241 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7242 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7243 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7244
7245 // Note, inline_string_indexOf() generates checks:
7246 // if (substr.count > string.count) return -1;
7247 // if (substr.count == 0) return 0;
7248 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7249
7250 // Load substring.
7251 if (ae == StrIntrinsicNode::UL) {
7252 pmovzxbw(vec, Address(str2, 0));
7253 } else {
7254 movdqu(vec, Address(str2, 0));
7255 }
7256 movl(cnt2, int_cnt2);
7257 movptr(result, str1); // string addr
7258
7259 if (int_cnt2 > stride) {
7260 jmpb(SCAN_TO_SUBSTR);
7261
7262 // Reload substr for rescan, this code
7263 // is executed only for large substrings (> 8 chars)
7264 bind(RELOAD_SUBSTR);
7265 if (ae == StrIntrinsicNode::UL) {
7266 pmovzxbw(vec, Address(str2, 0));
7267 } else {
7268 movdqu(vec, Address(str2, 0));
7269 }
7270 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7271
7272 bind(RELOAD_STR);
7273 // We came here after the beginning of the substring was
7274 // matched but the rest of it was not so we need to search
7275 // again. Start from the next element after the previous match.
7276
7277 // cnt2 is number of substring reminding elements and
7278 // cnt1 is number of string reminding elements when cmp failed.
7279 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7280 subl(cnt1, cnt2);
7281 addl(cnt1, int_cnt2);
7282 movl(cnt2, int_cnt2); // Now restore cnt2
7283
7284 decrementl(cnt1); // Shift to next element
7285 cmpl(cnt1, cnt2);
7286 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7287
7288 addptr(result, (1<<scale1));
7289
7290 } // (int_cnt2 > 8)
7291
7292 // Scan string for start of substr in 16-byte vectors
7293 bind(SCAN_TO_SUBSTR);
7294 pcmpestri(vec, Address(result, 0), mode);
7295 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7296 subl(cnt1, stride);
7297 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7298 cmpl(cnt1, cnt2);
7299 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7300 addptr(result, 16);
7301 jmpb(SCAN_TO_SUBSTR);
7302
7303 // Found a potential substr
7304 bind(FOUND_CANDIDATE);
7305 // Matched whole vector if first element matched (tmp(rcx) == 0).
7306 if (int_cnt2 == stride) {
7307 jccb(Assembler::overflow, RET_FOUND); // OF == 1
7308 } else { // int_cnt2 > 8
7309 jccb(Assembler::overflow, FOUND_SUBSTR);
7310 }
7311 // After pcmpestri tmp(rcx) contains matched element index
7312 // Compute start addr of substr
7313 lea(result, Address(result, tmp, scale1));
7314
7315 // Make sure string is still long enough
7316 subl(cnt1, tmp);
7317 cmpl(cnt1, cnt2);
7318 if (int_cnt2 == stride) {
7319 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7320 } else { // int_cnt2 > 8
7321 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7322 }
7323 // Left less then substring.
7324
7325 bind(RET_NOT_FOUND);
7326 movl(result, -1);
7327 jmp(EXIT);
7328
7329 if (int_cnt2 > stride) {
7330 // This code is optimized for the case when whole substring
7331 // is matched if its head is matched.
7332 bind(MATCH_SUBSTR_HEAD);
7333 pcmpestri(vec, Address(result, 0), mode);
7334 // Reload only string if does not match
7335 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
7336
7337 Label CONT_SCAN_SUBSTR;
7338 // Compare the rest of substring (> 8 chars).
7339 bind(FOUND_SUBSTR);
7340 // First 8 chars are already matched.
7341 negptr(cnt2);
7342 addptr(cnt2, stride);
7343
7344 bind(SCAN_SUBSTR);
7345 subl(cnt1, stride);
7346 cmpl(cnt2, -stride); // Do not read beyond substring
7347 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7348 // Back-up strings to avoid reading beyond substring:
7349 // cnt1 = cnt1 - cnt2 + 8
7350 addl(cnt1, cnt2); // cnt2 is negative
7351 addl(cnt1, stride);
7352 movl(cnt2, stride); negptr(cnt2);
7353 bind(CONT_SCAN_SUBSTR);
7354 if (int_cnt2 < (int)G) {
7355 int tail_off1 = int_cnt2<<scale1;
7356 int tail_off2 = int_cnt2<<scale2;
7357 if (ae == StrIntrinsicNode::UL) {
7358 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7359 } else {
7360 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7361 }
7362 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7363 } else {
7364 // calculate index in register to avoid integer overflow (int_cnt2*2)
7365 movl(tmp, int_cnt2);
7366 addptr(tmp, cnt2);
7367 if (ae == StrIntrinsicNode::UL) {
7368 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7369 } else {
7370 movdqu(vec, Address(str2, tmp, scale2, 0));
7371 }
7372 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7373 }
7374 // Need to reload strings pointers if not matched whole vector
7375 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7376 addptr(cnt2, stride);
7377 jcc(Assembler::negative, SCAN_SUBSTR);
7378 // Fall through if found full substring
7379
7380 } // (int_cnt2 > 8)
7381
7382 bind(RET_FOUND);
7383 // Found result if we matched full small substring.
7384 // Compute substr offset
7385 subptr(result, str1);
7386 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7387 shrl(result, 1); // index
7388 }
7389 bind(EXIT);
7390
7391 } // string_indexofC8
7392
7393 // Small strings are loaded through stack if they cross page boundary.
7394 void MacroAssembler::string_indexof(Register str1, Register str2,
7395 Register cnt1, Register cnt2,
7396 int int_cnt2, Register result,
7397 XMMRegister vec, Register tmp,
7398 int ae) {
7399 ShortBranchVerifier sbv(this);
7400 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7401 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7402
7403 //
7404 // int_cnt2 is length of small (< 8 chars) constant substring
7405 // or (-1) for non constant substring in which case its length
7406 // is in cnt2 register.
7407 //
7408 // Note, inline_string_indexOf() generates checks:
7409 // if (substr.count > string.count) return -1;
7410 // if (substr.count == 0) return 0;
7411 //
7412 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7413 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7414 // This method uses the pcmpestri instruction with bound registers
7415 // inputs:
7416 // xmm - substring
7417 // rax - substring length (elements count)
7418 // mem - scanned string
7419 // rdx - string length (elements count)
7420 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7421 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7422 // outputs:
7423 // rcx - matched index in string
7424 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7425 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7426 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7427 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7428
7429 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7430 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7431 FOUND_CANDIDATE;
7432
7433 { //========================================================
7434 // We don't know where these strings are located
7435 // and we can't read beyond them. Load them through stack.
7436 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7437
7438 movptr(tmp, rsp); // save old SP
7439
7440 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7441 if (int_cnt2 == (1>>scale2)) { // One byte
7442 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7443 load_unsigned_byte(result, Address(str2, 0));
7444 movdl(vec, result); // move 32 bits
7445 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7446 // Not enough header space in 32-bit VM: 12+3 = 15.
7447 movl(result, Address(str2, -1));
7448 shrl(result, 8);
7449 movdl(vec, result); // move 32 bits
7450 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7451 load_unsigned_short(result, Address(str2, 0));
7452 movdl(vec, result); // move 32 bits
7453 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7454 movdl(vec, Address(str2, 0)); // move 32 bits
7455 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7456 movq(vec, Address(str2, 0)); // move 64 bits
7457 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7458 // Array header size is 12 bytes in 32-bit VM
7459 // + 6 bytes for 3 chars == 18 bytes,
7460 // enough space to load vec and shift.
7461 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7462 if (ae == StrIntrinsicNode::UL) {
7463 int tail_off = int_cnt2-8;
7464 pmovzxbw(vec, Address(str2, tail_off));
7465 psrldq(vec, -2*tail_off);
7466 }
7467 else {
7468 int tail_off = int_cnt2*(1<<scale2);
7469 movdqu(vec, Address(str2, tail_off-16));
7470 psrldq(vec, 16-tail_off);
7471 }
7472 }
7473 } else { // not constant substring
7474 cmpl(cnt2, stride);
7475 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7476
7477 // We can read beyond string if srt+16 does not cross page boundary
7478 // since heaps are aligned and mapped by pages.
7479 assert(os::vm_page_size() < (int)G, "default page should be small");
7480 movl(result, str2); // We need only low 32 bits
7481 andl(result, (os::vm_page_size()-1));
7482 cmpl(result, (os::vm_page_size()-16));
7483 jccb(Assembler::belowEqual, CHECK_STR);
7484
7485 // Move small strings to stack to allow load 16 bytes into vec.
7486 subptr(rsp, 16);
7487 int stk_offset = wordSize-(1<<scale2);
7488 push(cnt2);
7489
7490 bind(COPY_SUBSTR);
7491 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7492 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7493 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7494 } else if (ae == StrIntrinsicNode::UU) {
7495 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7496 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7497 }
7498 decrement(cnt2);
7499 jccb(Assembler::notZero, COPY_SUBSTR);
7500
7501 pop(cnt2);
7502 movptr(str2, rsp); // New substring address
7503 } // non constant
7504
7505 bind(CHECK_STR);
7506 cmpl(cnt1, stride);
7507 jccb(Assembler::aboveEqual, BIG_STRINGS);
7508
7509 // Check cross page boundary.
7510 movl(result, str1); // We need only low 32 bits
7511 andl(result, (os::vm_page_size()-1));
7512 cmpl(result, (os::vm_page_size()-16));
7513 jccb(Assembler::belowEqual, BIG_STRINGS);
7514
7515 subptr(rsp, 16);
7516 int stk_offset = -(1<<scale1);
7517 if (int_cnt2 < 0) { // not constant
7518 push(cnt2);
7519 stk_offset += wordSize;
7520 }
7521 movl(cnt2, cnt1);
7522
7523 bind(COPY_STR);
7524 if (ae == StrIntrinsicNode::LL) {
7525 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7526 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7527 } else {
7528 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7529 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7530 }
7531 decrement(cnt2);
7532 jccb(Assembler::notZero, COPY_STR);
7533
7534 if (int_cnt2 < 0) { // not constant
7535 pop(cnt2);
7536 }
7537 movptr(str1, rsp); // New string address
7538
7539 bind(BIG_STRINGS);
7540 // Load substring.
7541 if (int_cnt2 < 0) { // -1
7542 if (ae == StrIntrinsicNode::UL) {
7543 pmovzxbw(vec, Address(str2, 0));
7544 } else {
7545 movdqu(vec, Address(str2, 0));
7546 }
7547 push(cnt2); // substr count
7548 push(str2); // substr addr
7549 push(str1); // string addr
7550 } else {
7551 // Small (< 8 chars) constant substrings are loaded already.
7552 movl(cnt2, int_cnt2);
7553 }
7554 push(tmp); // original SP
7555
7556 } // Finished loading
7557
7558 //========================================================
7559 // Start search
7560 //
7561
7562 movptr(result, str1); // string addr
7563
7564 if (int_cnt2 < 0) { // Only for non constant substring
7565 jmpb(SCAN_TO_SUBSTR);
7566
7567 // SP saved at sp+0
7568 // String saved at sp+1*wordSize
7569 // Substr saved at sp+2*wordSize
7570 // Substr count saved at sp+3*wordSize
7571
7572 // Reload substr for rescan, this code
7573 // is executed only for large substrings (> 8 chars)
7574 bind(RELOAD_SUBSTR);
7575 movptr(str2, Address(rsp, 2*wordSize));
7576 movl(cnt2, Address(rsp, 3*wordSize));
7577 if (ae == StrIntrinsicNode::UL) {
7578 pmovzxbw(vec, Address(str2, 0));
7579 } else {
7580 movdqu(vec, Address(str2, 0));
7581 }
7582 // We came here after the beginning of the substring was
7583 // matched but the rest of it was not so we need to search
7584 // again. Start from the next element after the previous match.
7585 subptr(str1, result); // Restore counter
7586 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7587 shrl(str1, 1);
7588 }
7589 addl(cnt1, str1);
7590 decrementl(cnt1); // Shift to next element
7591 cmpl(cnt1, cnt2);
7592 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7593
7594 addptr(result, (1<<scale1));
7595 } // non constant
7596
7597 // Scan string for start of substr in 16-byte vectors
7598 bind(SCAN_TO_SUBSTR);
7599 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7600 pcmpestri(vec, Address(result, 0), mode);
7601 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7602 subl(cnt1, stride);
7603 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7604 cmpl(cnt1, cnt2);
7605 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7606 addptr(result, 16);
7607
7608 bind(ADJUST_STR);
7609 cmpl(cnt1, stride); // Do not read beyond string
7610 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7611 // Back-up string to avoid reading beyond string.
7612 lea(result, Address(result, cnt1, scale1, -16));
7613 movl(cnt1, stride);
7614 jmpb(SCAN_TO_SUBSTR);
7615
7616 // Found a potential substr
7617 bind(FOUND_CANDIDATE);
7618 // After pcmpestri tmp(rcx) contains matched element index
7619
7620 // Make sure string is still long enough
7621 subl(cnt1, tmp);
7622 cmpl(cnt1, cnt2);
7623 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7624 // Left less then substring.
7625
7626 bind(RET_NOT_FOUND);
7627 movl(result, -1);
7628 jmpb(CLEANUP);
7629
7630 bind(FOUND_SUBSTR);
7631 // Compute start addr of substr
7632 lea(result, Address(result, tmp, scale1));
7633 if (int_cnt2 > 0) { // Constant substring
7634 // Repeat search for small substring (< 8 chars)
7635 // from new point without reloading substring.
7636 // Have to check that we don't read beyond string.
7637 cmpl(tmp, stride-int_cnt2);
7638 jccb(Assembler::greater, ADJUST_STR);
7639 // Fall through if matched whole substring.
7640 } else { // non constant
7641 assert(int_cnt2 == -1, "should be != 0");
7642
7643 addl(tmp, cnt2);
7644 // Found result if we matched whole substring.
7645 cmpl(tmp, stride);
7646 jccb(Assembler::lessEqual, RET_FOUND);
7647
7648 // Repeat search for small substring (<= 8 chars)
7649 // from new point 'str1' without reloading substring.
7650 cmpl(cnt2, stride);
7651 // Have to check that we don't read beyond string.
7652 jccb(Assembler::lessEqual, ADJUST_STR);
7653
7654 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7655 // Compare the rest of substring (> 8 chars).
7656 movptr(str1, result);
7657
7658 cmpl(tmp, cnt2);
7659 // First 8 chars are already matched.
7660 jccb(Assembler::equal, CHECK_NEXT);
7661
7662 bind(SCAN_SUBSTR);
7663 pcmpestri(vec, Address(str1, 0), mode);
7664 // Need to reload strings pointers if not matched whole vector
7665 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7666
7667 bind(CHECK_NEXT);
7668 subl(cnt2, stride);
7669 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7670 addptr(str1, 16);
7671 if (ae == StrIntrinsicNode::UL) {
7672 addptr(str2, 8);
7673 } else {
7674 addptr(str2, 16);
7675 }
7676 subl(cnt1, stride);
7677 cmpl(cnt2, stride); // Do not read beyond substring
7678 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7679 // Back-up strings to avoid reading beyond substring.
7680
7681 if (ae == StrIntrinsicNode::UL) {
7682 lea(str2, Address(str2, cnt2, scale2, -8));
7683 lea(str1, Address(str1, cnt2, scale1, -16));
7684 } else {
7685 lea(str2, Address(str2, cnt2, scale2, -16));
7686 lea(str1, Address(str1, cnt2, scale1, -16));
7687 }
7688 subl(cnt1, cnt2);
7689 movl(cnt2, stride);
7690 addl(cnt1, stride);
7691 bind(CONT_SCAN_SUBSTR);
7692 if (ae == StrIntrinsicNode::UL) {
7693 pmovzxbw(vec, Address(str2, 0));
7694 } else {
7695 movdqu(vec, Address(str2, 0));
7696 }
7697 jmp(SCAN_SUBSTR);
7698
7699 bind(RET_FOUND_LONG);
7700 movptr(str1, Address(rsp, wordSize));
7701 } // non constant
7702
7703 bind(RET_FOUND);
7704 // Compute substr offset
7705 subptr(result, str1);
7706 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7707 shrl(result, 1); // index
7708 }
7709 bind(CLEANUP);
7710 pop(rsp); // restore SP
7711
7712 } // string_indexof
7713
7714 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7715 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7716 ShortBranchVerifier sbv(this);
7717 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7718
7719 int stride = 8;
7720
7721 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7722 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7723 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7724 FOUND_SEQ_CHAR, DONE_LABEL;
7725
7726 movptr(result, str1);
7727 if (UseAVX >= 2) {
7728 cmpl(cnt1, stride);
7729 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7730 cmpl(cnt1, 2*stride);
7731 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7732 movdl(vec1, ch);
7733 vpbroadcastw(vec1, vec1);
7734 vpxor(vec2, vec2);
7735 movl(tmp, cnt1);
7736 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7737 andl(cnt1,0x0000000F); //tail count (in chars)
7738
7739 bind(SCAN_TO_16_CHAR_LOOP);
7740 vmovdqu(vec3, Address(result, 0));
7741 vpcmpeqw(vec3, vec3, vec1, 1);
7742 vptest(vec2, vec3);
7743 jcc(Assembler::carryClear, FOUND_CHAR);
7744 addptr(result, 32);
7745 subl(tmp, 2*stride);
7746 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7747 jmp(SCAN_TO_8_CHAR);
7748 bind(SCAN_TO_8_CHAR_INIT);
7749 movdl(vec1, ch);
7750 pshuflw(vec1, vec1, 0x00);
7751 pshufd(vec1, vec1, 0);
7752 pxor(vec2, vec2);
7753 }
7754 bind(SCAN_TO_8_CHAR);
7755 cmpl(cnt1, stride);
7756 if (UseAVX >= 2) {
7757 jcc(Assembler::less, SCAN_TO_CHAR);
7758 } else {
7759 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7760 movdl(vec1, ch);
7761 pshuflw(vec1, vec1, 0x00);
7762 pshufd(vec1, vec1, 0);
7763 pxor(vec2, vec2);
7764 }
7765 movl(tmp, cnt1);
7766 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7767 andl(cnt1,0x00000007); //tail count (in chars)
7768
7769 bind(SCAN_TO_8_CHAR_LOOP);
7770 movdqu(vec3, Address(result, 0));
7771 pcmpeqw(vec3, vec1);
7772 ptest(vec2, vec3);
7773 jcc(Assembler::carryClear, FOUND_CHAR);
7774 addptr(result, 16);
7775 subl(tmp, stride);
7776 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7777 bind(SCAN_TO_CHAR);
7778 testl(cnt1, cnt1);
7779 jcc(Assembler::zero, RET_NOT_FOUND);
7780 bind(SCAN_TO_CHAR_LOOP);
7781 load_unsigned_short(tmp, Address(result, 0));
7782 cmpl(ch, tmp);
7783 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7784 addptr(result, 2);
7785 subl(cnt1, 1);
7786 jccb(Assembler::zero, RET_NOT_FOUND);
7787 jmp(SCAN_TO_CHAR_LOOP);
7788
7789 bind(RET_NOT_FOUND);
7790 movl(result, -1);
7791 jmpb(DONE_LABEL);
7792
7793 bind(FOUND_CHAR);
7794 if (UseAVX >= 2) {
7795 vpmovmskb(tmp, vec3);
7796 } else {
7797 pmovmskb(tmp, vec3);
7798 }
7799 bsfl(ch, tmp);
7800 addl(result, ch);
7801
7802 bind(FOUND_SEQ_CHAR);
7803 subptr(result, str1);
7804 shrl(result, 1);
7805
7806 bind(DONE_LABEL);
7807 } // string_indexof_char
7808
7809 // helper function for string_compare
7810 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7811 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7812 Address::ScaleFactor scale2, Register index, int ae) {
7813 if (ae == StrIntrinsicNode::LL) {
7814 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7815 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7816 } else if (ae == StrIntrinsicNode::UU) {
7817 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7818 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7819 } else {
7820 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7821 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7822 }
7823 }
7824
7825 // Compare strings, used for char[] and byte[].
7826 void MacroAssembler::string_compare(Register str1, Register str2,
7827 Register cnt1, Register cnt2, Register result,
7828 XMMRegister vec1, int ae) {
7829 ShortBranchVerifier sbv(this);
7830 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7831 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7832 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7833 int stride2x2 = 0x40;
7834 Address::ScaleFactor scale = Address::no_scale;
7835 Address::ScaleFactor scale1 = Address::no_scale;
7836 Address::ScaleFactor scale2 = Address::no_scale;
7837
7838 if (ae != StrIntrinsicNode::LL) {
7839 stride2x2 = 0x20;
7840 }
7841
7842 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7843 shrl(cnt2, 1);
7844 }
7845 // Compute the minimum of the string lengths and the
7846 // difference of the string lengths (stack).
7847 // Do the conditional move stuff
7848 movl(result, cnt1);
7849 subl(cnt1, cnt2);
7850 push(cnt1);
7851 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7852
7853 // Is the minimum length zero?
7854 testl(cnt2, cnt2);
7855 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7856 if (ae == StrIntrinsicNode::LL) {
7857 // Load first bytes
7858 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7859 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7860 } else if (ae == StrIntrinsicNode::UU) {
7861 // Load first characters
7862 load_unsigned_short(result, Address(str1, 0));
7863 load_unsigned_short(cnt1, Address(str2, 0));
7864 } else {
7865 load_unsigned_byte(result, Address(str1, 0));
7866 load_unsigned_short(cnt1, Address(str2, 0));
7867 }
7868 subl(result, cnt1);
7869 jcc(Assembler::notZero, POP_LABEL);
7870
7871 if (ae == StrIntrinsicNode::UU) {
7872 // Divide length by 2 to get number of chars
7873 shrl(cnt2, 1);
7874 }
7875 cmpl(cnt2, 1);
7876 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7877
7878 // Check if the strings start at the same location and setup scale and stride
7879 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7880 cmpptr(str1, str2);
7881 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7882 if (ae == StrIntrinsicNode::LL) {
7883 scale = Address::times_1;
7884 stride = 16;
7885 } else {
7886 scale = Address::times_2;
7887 stride = 8;
7888 }
7889 } else {
7890 scale1 = Address::times_1;
7891 scale2 = Address::times_2;
7892 // scale not used
7893 stride = 8;
7894 }
7895
7896 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7897 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7898 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7899 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7900 Label COMPARE_TAIL_LONG;
7901 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7902
7903 int pcmpmask = 0x19;
7904 if (ae == StrIntrinsicNode::LL) {
7905 pcmpmask &= ~0x01;
7906 }
7907
7908 // Setup to compare 16-chars (32-bytes) vectors,
7909 // start from first character again because it has aligned address.
7910 if (ae == StrIntrinsicNode::LL) {
7911 stride2 = 32;
7912 } else {
7913 stride2 = 16;
7914 }
7915 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7916 adr_stride = stride << scale;
7917 } else {
7918 adr_stride1 = 8; //stride << scale1;
7919 adr_stride2 = 16; //stride << scale2;
7920 }
7921
7922 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7923 // rax and rdx are used by pcmpestri as elements counters
7924 movl(result, cnt2);
7925 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7926 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7927
7928 // fast path : compare first 2 8-char vectors.
7929 bind(COMPARE_16_CHARS);
7930 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7931 movdqu(vec1, Address(str1, 0));
7932 } else {
7933 pmovzxbw(vec1, Address(str1, 0));
7934 }
7935 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7936 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7937
7938 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7939 movdqu(vec1, Address(str1, adr_stride));
7940 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7941 } else {
7942 pmovzxbw(vec1, Address(str1, adr_stride1));
7943 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7944 }
7945 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7946 addl(cnt1, stride);
7947
7948 // Compare the characters at index in cnt1
7949 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7950 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7951 subl(result, cnt2);
7952 jmp(POP_LABEL);
7953
7954 // Setup the registers to start vector comparison loop
7955 bind(COMPARE_WIDE_VECTORS);
7956 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7957 lea(str1, Address(str1, result, scale));
7958 lea(str2, Address(str2, result, scale));
7959 } else {
7960 lea(str1, Address(str1, result, scale1));
7961 lea(str2, Address(str2, result, scale2));
7962 }
7963 subl(result, stride2);
7964 subl(cnt2, stride2);
7965 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7966 negptr(result);
7967
7968 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7969 bind(COMPARE_WIDE_VECTORS_LOOP);
7970
7971 #ifdef _LP64
7972 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7973 cmpl(cnt2, stride2x2);
7974 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7975 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7976 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7977
7978 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7979 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7980 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7981 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7982 } else {
7983 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7984 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7985 }
7986 kortestql(k7, k7);
7987 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7988 addptr(result, stride2x2); // update since we already compared at this addr
7989 subl(cnt2, stride2x2); // and sub the size too
7990 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7991
7992 vpxor(vec1, vec1);
7993 jmpb(COMPARE_WIDE_TAIL);
7994 }//if (VM_Version::supports_avx512vlbw())
7995 #endif // _LP64
7996
7997
7998 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7999 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8000 vmovdqu(vec1, Address(str1, result, scale));
8001 vpxor(vec1, Address(str2, result, scale));
8002 } else {
8003 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
8004 vpxor(vec1, Address(str2, result, scale2));
8005 }
8006 vptest(vec1, vec1);
8007 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
8008 addptr(result, stride2);
8009 subl(cnt2, stride2);
8010 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
8011 // clean upper bits of YMM registers
8012 vpxor(vec1, vec1);
8013
8014 // compare wide vectors tail
8015 bind(COMPARE_WIDE_TAIL);
8016 testptr(result, result);
8017 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8018
8019 movl(result, stride2);
8020 movl(cnt2, result);
8021 negptr(result);
8022 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8023
8024 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
8025 bind(VECTOR_NOT_EQUAL);
8026 // clean upper bits of YMM registers
8027 vpxor(vec1, vec1);
8028 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8029 lea(str1, Address(str1, result, scale));
8030 lea(str2, Address(str2, result, scale));
8031 } else {
8032 lea(str1, Address(str1, result, scale1));
8033 lea(str2, Address(str2, result, scale2));
8034 }
8035 jmp(COMPARE_16_CHARS);
8036
8037 // Compare tail chars, length between 1 to 15 chars
8038 bind(COMPARE_TAIL_LONG);
8039 movl(cnt2, result);
8040 cmpl(cnt2, stride);
8041 jcc(Assembler::less, COMPARE_SMALL_STR);
8042
8043 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8044 movdqu(vec1, Address(str1, 0));
8045 } else {
8046 pmovzxbw(vec1, Address(str1, 0));
8047 }
8048 pcmpestri(vec1, Address(str2, 0), pcmpmask);
8049 jcc(Assembler::below, COMPARE_INDEX_CHAR);
8050 subptr(cnt2, stride);
8051 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8052 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8053 lea(str1, Address(str1, result, scale));
8054 lea(str2, Address(str2, result, scale));
8055 } else {
8056 lea(str1, Address(str1, result, scale1));
8057 lea(str2, Address(str2, result, scale2));
8058 }
8059 negptr(cnt2);
8060 jmpb(WHILE_HEAD_LABEL);
8061
8062 bind(COMPARE_SMALL_STR);
8063 } else if (UseSSE42Intrinsics) {
8064 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
8065 int pcmpmask = 0x19;
8066 // Setup to compare 8-char (16-byte) vectors,
8067 // start from first character again because it has aligned address.
8068 movl(result, cnt2);
8069 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
8070 if (ae == StrIntrinsicNode::LL) {
8071 pcmpmask &= ~0x01;
8072 }
8073 jcc(Assembler::zero, COMPARE_TAIL);
8074 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8075 lea(str1, Address(str1, result, scale));
8076 lea(str2, Address(str2, result, scale));
8077 } else {
8078 lea(str1, Address(str1, result, scale1));
8079 lea(str2, Address(str2, result, scale2));
8080 }
8081 negptr(result);
8082
8083 // pcmpestri
8084 // inputs:
8085 // vec1- substring
8086 // rax - negative string length (elements count)
8087 // mem - scanned string
8088 // rdx - string length (elements count)
8089 // pcmpmask - cmp mode: 11000 (string compare with negated result)
8090 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
8091 // outputs:
8092 // rcx - first mismatched element index
8093 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
8094
8095 bind(COMPARE_WIDE_VECTORS);
8096 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8097 movdqu(vec1, Address(str1, result, scale));
8098 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8099 } else {
8100 pmovzxbw(vec1, Address(str1, result, scale1));
8101 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8102 }
8103 // After pcmpestri cnt1(rcx) contains mismatched element index
8104
8105 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
8106 addptr(result, stride);
8107 subptr(cnt2, stride);
8108 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
8109
8110 // compare wide vectors tail
8111 testptr(result, result);
8112 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8113
8114 movl(cnt2, stride);
8115 movl(result, stride);
8116 negptr(result);
8117 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8118 movdqu(vec1, Address(str1, result, scale));
8119 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8120 } else {
8121 pmovzxbw(vec1, Address(str1, result, scale1));
8122 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8123 }
8124 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
8125
8126 // Mismatched characters in the vectors
8127 bind(VECTOR_NOT_EQUAL);
8128 addptr(cnt1, result);
8129 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
8130 subl(result, cnt2);
8131 jmpb(POP_LABEL);
8132
8133 bind(COMPARE_TAIL); // limit is zero
8134 movl(cnt2, result);
8135 // Fallthru to tail compare
8136 }
8137 // Shift str2 and str1 to the end of the arrays, negate min
8138 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8139 lea(str1, Address(str1, cnt2, scale));
8140 lea(str2, Address(str2, cnt2, scale));
8141 } else {
8142 lea(str1, Address(str1, cnt2, scale1));
8143 lea(str2, Address(str2, cnt2, scale2));
8144 }
8145 decrementl(cnt2); // first character was compared already
8146 negptr(cnt2);
8147
8148 // Compare the rest of the elements
8149 bind(WHILE_HEAD_LABEL);
8150 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
8151 subl(result, cnt1);
8152 jccb(Assembler::notZero, POP_LABEL);
8153 increment(cnt2);
8154 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
8155
8156 // Strings are equal up to min length. Return the length difference.
8157 bind(LENGTH_DIFF_LABEL);
8158 pop(result);
8159 if (ae == StrIntrinsicNode::UU) {
8160 // Divide diff by 2 to get number of chars
8161 sarl(result, 1);
8162 }
8163 jmpb(DONE_LABEL);
8164
8165 #ifdef _LP64
8166 if (VM_Version::supports_avx512vlbw()) {
8167
8168 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
8169
8170 kmovql(cnt1, k7);
8171 notq(cnt1);
8172 bsfq(cnt2, cnt1);
8173 if (ae != StrIntrinsicNode::LL) {
8174 // Divide diff by 2 to get number of chars
8175 sarl(cnt2, 1);
8176 }
8177 addq(result, cnt2);
8178 if (ae == StrIntrinsicNode::LL) {
8179 load_unsigned_byte(cnt1, Address(str2, result));
8180 load_unsigned_byte(result, Address(str1, result));
8181 } else if (ae == StrIntrinsicNode::UU) {
8182 load_unsigned_short(cnt1, Address(str2, result, scale));
8183 load_unsigned_short(result, Address(str1, result, scale));
8184 } else {
8185 load_unsigned_short(cnt1, Address(str2, result, scale2));
8186 load_unsigned_byte(result, Address(str1, result, scale1));
8187 }
8188 subl(result, cnt1);
8189 jmpb(POP_LABEL);
8190 }//if (VM_Version::supports_avx512vlbw())
8191 #endif // _LP64
8192
8193 // Discard the stored length difference
8194 bind(POP_LABEL);
8195 pop(cnt1);
8196
8197 // That's it
8198 bind(DONE_LABEL);
8199 if(ae == StrIntrinsicNode::UL) {
8200 negl(result);
8201 }
8202
8203 }
8204
8205 // Search for Non-ASCII character (Negative byte value) in a byte array,
8206 // return true if it has any and false otherwise.
8207 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
8208 // @HotSpotIntrinsicCandidate
8209 // private static boolean hasNegatives(byte[] ba, int off, int len) {
8210 // for (int i = off; i < off + len; i++) {
8211 // if (ba[i] < 0) {
8212 // return true;
8213 // }
8214 // }
8215 // return false;
8216 // }
8217 void MacroAssembler::has_negatives(Register ary1, Register len,
8218 Register result, Register tmp1,
8219 XMMRegister vec1, XMMRegister vec2) {
8220 // rsi: byte array
8221 // rcx: len
8222 // rax: result
8223 ShortBranchVerifier sbv(this);
8224 assert_different_registers(ary1, len, result, tmp1);
8225 assert_different_registers(vec1, vec2);
8226 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8227
8228 // len == 0
8229 testl(len, len);
8230 jcc(Assembler::zero, FALSE_LABEL);
8231
8232 if ((UseAVX > 2) && // AVX512
8233 VM_Version::supports_avx512vlbw() &&
8234 VM_Version::supports_bmi2()) {
8235
8236 set_vector_masking(); // opening of the stub context for programming mask registers
8237
8238 Label test_64_loop, test_tail;
8239 Register tmp3_aliased = len;
8240
8241 movl(tmp1, len);
8242 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
8243
8244 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
8245 andl(len, ~(64 - 1)); // vector count (in chars)
8246 jccb(Assembler::zero, test_tail);
8247
8248 lea(ary1, Address(ary1, len, Address::times_1));
8249 negptr(len);
8250
8251 bind(test_64_loop);
8252 // Check whether our 64 elements of size byte contain negatives
8253 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
8254 kortestql(k2, k2);
8255 jcc(Assembler::notZero, TRUE_LABEL);
8256
8257 addptr(len, 64);
8258 jccb(Assembler::notZero, test_64_loop);
8259
8260
8261 bind(test_tail);
8262 // bail out when there is nothing to be done
8263 testl(tmp1, -1);
8264 jcc(Assembler::zero, FALSE_LABEL);
8265
8266 // Save k1
8267 kmovql(k3, k1);
8268
8269 // ~(~0 << len) applied up to two times (for 32-bit scenario)
8270 #ifdef _LP64
8271 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
8272 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
8273 notq(tmp3_aliased);
8274 kmovql(k1, tmp3_aliased);
8275 #else
8276 Label k_init;
8277 jmp(k_init);
8278
8279 // We could not read 64-bits from a general purpose register thus we move
8280 // data required to compose 64 1's to the instruction stream
8281 // We emit 64 byte wide series of elements from 0..63 which later on would
8282 // be used as a compare targets with tail count contained in tmp1 register.
8283 // Result would be a k1 register having tmp1 consecutive number or 1
8284 // counting from least significant bit.
8285 address tmp = pc();
8286 emit_int64(0x0706050403020100);
8287 emit_int64(0x0F0E0D0C0B0A0908);
8288 emit_int64(0x1716151413121110);
8289 emit_int64(0x1F1E1D1C1B1A1918);
8290 emit_int64(0x2726252423222120);
8291 emit_int64(0x2F2E2D2C2B2A2928);
8292 emit_int64(0x3736353433323130);
8293 emit_int64(0x3F3E3D3C3B3A3938);
8294
8295 bind(k_init);
8296 lea(len, InternalAddress(tmp));
8297 // create mask to test for negative byte inside a vector
8298 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
8299 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
8300
8301 #endif
8302 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
8303 ktestq(k2, k1);
8304 // Restore k1
8305 kmovql(k1, k3);
8306 jcc(Assembler::notZero, TRUE_LABEL);
8307
8308 jmp(FALSE_LABEL);
8309
8310 clear_vector_masking(); // closing of the stub context for programming mask registers
8311 } else {
8312 movl(result, len); // copy
8313
8314 if (UseAVX == 2 && UseSSE >= 2) {
8315 // With AVX2, use 32-byte vector compare
8316 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8317
8318 // Compare 32-byte vectors
8319 andl(result, 0x0000001f); // tail count (in bytes)
8320 andl(len, 0xffffffe0); // vector count (in bytes)
8321 jccb(Assembler::zero, COMPARE_TAIL);
8322
8323 lea(ary1, Address(ary1, len, Address::times_1));
8324 negptr(len);
8325
8326 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
8327 movdl(vec2, tmp1);
8328 vpbroadcastd(vec2, vec2);
8329
8330 bind(COMPARE_WIDE_VECTORS);
8331 vmovdqu(vec1, Address(ary1, len, Address::times_1));
8332 vptest(vec1, vec2);
8333 jccb(Assembler::notZero, TRUE_LABEL);
8334 addptr(len, 32);
8335 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8336
8337 testl(result, result);
8338 jccb(Assembler::zero, FALSE_LABEL);
8339
8340 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8341 vptest(vec1, vec2);
8342 jccb(Assembler::notZero, TRUE_LABEL);
8343 jmpb(FALSE_LABEL);
8344
8345 bind(COMPARE_TAIL); // len is zero
8346 movl(len, result);
8347 // Fallthru to tail compare
8348 } else if (UseSSE42Intrinsics) {
8349 // With SSE4.2, use double quad vector compare
8350 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8351
8352 // Compare 16-byte vectors
8353 andl(result, 0x0000000f); // tail count (in bytes)
8354 andl(len, 0xfffffff0); // vector count (in bytes)
8355 jccb(Assembler::zero, COMPARE_TAIL);
8356
8357 lea(ary1, Address(ary1, len, Address::times_1));
8358 negptr(len);
8359
8360 movl(tmp1, 0x80808080);
8361 movdl(vec2, tmp1);
8362 pshufd(vec2, vec2, 0);
8363
8364 bind(COMPARE_WIDE_VECTORS);
8365 movdqu(vec1, Address(ary1, len, Address::times_1));
8366 ptest(vec1, vec2);
8367 jccb(Assembler::notZero, TRUE_LABEL);
8368 addptr(len, 16);
8369 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8370
8371 testl(result, result);
8372 jccb(Assembler::zero, FALSE_LABEL);
8373
8374 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8375 ptest(vec1, vec2);
8376 jccb(Assembler::notZero, TRUE_LABEL);
8377 jmpb(FALSE_LABEL);
8378
8379 bind(COMPARE_TAIL); // len is zero
8380 movl(len, result);
8381 // Fallthru to tail compare
8382 }
8383 }
8384 // Compare 4-byte vectors
8385 andl(len, 0xfffffffc); // vector count (in bytes)
8386 jccb(Assembler::zero, COMPARE_CHAR);
8387
8388 lea(ary1, Address(ary1, len, Address::times_1));
8389 negptr(len);
8390
8391 bind(COMPARE_VECTORS);
8392 movl(tmp1, Address(ary1, len, Address::times_1));
8393 andl(tmp1, 0x80808080);
8394 jccb(Assembler::notZero, TRUE_LABEL);
8395 addptr(len, 4);
8396 jcc(Assembler::notZero, COMPARE_VECTORS);
8397
8398 // Compare trailing char (final 2 bytes), if any
8399 bind(COMPARE_CHAR);
8400 testl(result, 0x2); // tail char
8401 jccb(Assembler::zero, COMPARE_BYTE);
8402 load_unsigned_short(tmp1, Address(ary1, 0));
8403 andl(tmp1, 0x00008080);
8404 jccb(Assembler::notZero, TRUE_LABEL);
8405 subptr(result, 2);
8406 lea(ary1, Address(ary1, 2));
8407
8408 bind(COMPARE_BYTE);
8409 testl(result, 0x1); // tail byte
8410 jccb(Assembler::zero, FALSE_LABEL);
8411 load_unsigned_byte(tmp1, Address(ary1, 0));
8412 andl(tmp1, 0x00000080);
8413 jccb(Assembler::notEqual, TRUE_LABEL);
8414 jmpb(FALSE_LABEL);
8415
8416 bind(TRUE_LABEL);
8417 movl(result, 1); // return true
8418 jmpb(DONE);
8419
8420 bind(FALSE_LABEL);
8421 xorl(result, result); // return false
8422
8423 // That's it
8424 bind(DONE);
8425 if (UseAVX >= 2 && UseSSE >= 2) {
8426 // clean upper bits of YMM registers
8427 vpxor(vec1, vec1);
8428 vpxor(vec2, vec2);
8429 }
8430 }
8431 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8432 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8433 Register limit, Register result, Register chr,
8434 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8435 ShortBranchVerifier sbv(this);
8436 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8437
8438 int length_offset = arrayOopDesc::length_offset_in_bytes();
8439 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8440
8441 if (is_array_equ) {
8442 // Check the input args
8443 cmpoop(ary1, ary2);
8444 jcc(Assembler::equal, TRUE_LABEL);
8445
8446 // Need additional checks for arrays_equals.
8447 testptr(ary1, ary1);
8448 jcc(Assembler::zero, FALSE_LABEL);
8449 testptr(ary2, ary2);
8450 jcc(Assembler::zero, FALSE_LABEL);
8451
8452 // Check the lengths
8453 movl(limit, Address(ary1, length_offset));
8454 cmpl(limit, Address(ary2, length_offset));
8455 jcc(Assembler::notEqual, FALSE_LABEL);
8456 }
8457
8458 // count == 0
8459 testl(limit, limit);
8460 jcc(Assembler::zero, TRUE_LABEL);
8461
8462 if (is_array_equ) {
8463 // Load array address
8464 lea(ary1, Address(ary1, base_offset));
8465 lea(ary2, Address(ary2, base_offset));
8466 }
8467
8468 if (is_array_equ && is_char) {
8469 // arrays_equals when used for char[].
8470 shll(limit, 1); // byte count != 0
8471 }
8472 movl(result, limit); // copy
8473
8474 if (UseAVX >= 2) {
8475 // With AVX2, use 32-byte vector compare
8476 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8477
8478 // Compare 32-byte vectors
8479 andl(result, 0x0000001f); // tail count (in bytes)
8480 andl(limit, 0xffffffe0); // vector count (in bytes)
8481 jcc(Assembler::zero, COMPARE_TAIL);
8482
8483 lea(ary1, Address(ary1, limit, Address::times_1));
8484 lea(ary2, Address(ary2, limit, Address::times_1));
8485 negptr(limit);
8486
8487 bind(COMPARE_WIDE_VECTORS);
8488
8489 #ifdef _LP64
8490 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8491 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8492
8493 cmpl(limit, -64);
8494 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8495
8496 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8497
8498 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8499 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8500 kortestql(k7, k7);
8501 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8502 addptr(limit, 64); // update since we already compared at this addr
8503 cmpl(limit, -64);
8504 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8505
8506 // At this point we may still need to compare -limit+result bytes.
8507 // We could execute the next two instruction and just continue via non-wide path:
8508 // cmpl(limit, 0);
8509 // jcc(Assembler::equal, COMPARE_TAIL); // true
8510 // But since we stopped at the points ary{1,2}+limit which are
8511 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8512 // (|limit| <= 32 and result < 32),
8513 // we may just compare the last 64 bytes.
8514 //
8515 addptr(result, -64); // it is safe, bc we just came from this area
8516 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8517 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8518 kortestql(k7, k7);
8519 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8520
8521 jmp(TRUE_LABEL);
8522
8523 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8524
8525 }//if (VM_Version::supports_avx512vlbw())
8526 #endif //_LP64
8527
8528 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8529 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8530 vpxor(vec1, vec2);
8531
8532 vptest(vec1, vec1);
8533 jcc(Assembler::notZero, FALSE_LABEL);
8534 addptr(limit, 32);
8535 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8536
8537 testl(result, result);
8538 jcc(Assembler::zero, TRUE_LABEL);
8539
8540 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8541 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8542 vpxor(vec1, vec2);
8543
8544 vptest(vec1, vec1);
8545 jccb(Assembler::notZero, FALSE_LABEL);
8546 jmpb(TRUE_LABEL);
8547
8548 bind(COMPARE_TAIL); // limit is zero
8549 movl(limit, result);
8550 // Fallthru to tail compare
8551 } else if (UseSSE42Intrinsics) {
8552 // With SSE4.2, use double quad vector compare
8553 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8554
8555 // Compare 16-byte vectors
8556 andl(result, 0x0000000f); // tail count (in bytes)
8557 andl(limit, 0xfffffff0); // vector count (in bytes)
8558 jcc(Assembler::zero, COMPARE_TAIL);
8559
8560 lea(ary1, Address(ary1, limit, Address::times_1));
8561 lea(ary2, Address(ary2, limit, Address::times_1));
8562 negptr(limit);
8563
8564 bind(COMPARE_WIDE_VECTORS);
8565 movdqu(vec1, Address(ary1, limit, Address::times_1));
8566 movdqu(vec2, Address(ary2, limit, Address::times_1));
8567 pxor(vec1, vec2);
8568
8569 ptest(vec1, vec1);
8570 jcc(Assembler::notZero, FALSE_LABEL);
8571 addptr(limit, 16);
8572 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8573
8574 testl(result, result);
8575 jcc(Assembler::zero, TRUE_LABEL);
8576
8577 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8578 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8579 pxor(vec1, vec2);
8580
8581 ptest(vec1, vec1);
8582 jccb(Assembler::notZero, FALSE_LABEL);
8583 jmpb(TRUE_LABEL);
8584
8585 bind(COMPARE_TAIL); // limit is zero
8586 movl(limit, result);
8587 // Fallthru to tail compare
8588 }
8589
8590 // Compare 4-byte vectors
8591 andl(limit, 0xfffffffc); // vector count (in bytes)
8592 jccb(Assembler::zero, COMPARE_CHAR);
8593
8594 lea(ary1, Address(ary1, limit, Address::times_1));
8595 lea(ary2, Address(ary2, limit, Address::times_1));
8596 negptr(limit);
8597
8598 bind(COMPARE_VECTORS);
8599 movl(chr, Address(ary1, limit, Address::times_1));
8600 cmpl(chr, Address(ary2, limit, Address::times_1));
8601 jccb(Assembler::notEqual, FALSE_LABEL);
8602 addptr(limit, 4);
8603 jcc(Assembler::notZero, COMPARE_VECTORS);
8604
8605 // Compare trailing char (final 2 bytes), if any
8606 bind(COMPARE_CHAR);
8607 testl(result, 0x2); // tail char
8608 jccb(Assembler::zero, COMPARE_BYTE);
8609 load_unsigned_short(chr, Address(ary1, 0));
8610 load_unsigned_short(limit, Address(ary2, 0));
8611 cmpl(chr, limit);
8612 jccb(Assembler::notEqual, FALSE_LABEL);
8613
8614 if (is_array_equ && is_char) {
8615 bind(COMPARE_BYTE);
8616 } else {
8617 lea(ary1, Address(ary1, 2));
8618 lea(ary2, Address(ary2, 2));
8619
8620 bind(COMPARE_BYTE);
8621 testl(result, 0x1); // tail byte
8622 jccb(Assembler::zero, TRUE_LABEL);
8623 load_unsigned_byte(chr, Address(ary1, 0));
8624 load_unsigned_byte(limit, Address(ary2, 0));
8625 cmpl(chr, limit);
8626 jccb(Assembler::notEqual, FALSE_LABEL);
8627 }
8628 bind(TRUE_LABEL);
8629 movl(result, 1); // return true
8630 jmpb(DONE);
8631
8632 bind(FALSE_LABEL);
8633 xorl(result, result); // return false
8634
8635 // That's it
8636 bind(DONE);
8637 if (UseAVX >= 2) {
8638 // clean upper bits of YMM registers
8639 vpxor(vec1, vec1);
8640 vpxor(vec2, vec2);
8641 }
8642 }
8643
8644 #endif
8645
8646 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8647 Register to, Register value, Register count,
8648 Register rtmp, XMMRegister xtmp) {
8649 ShortBranchVerifier sbv(this);
8650 assert_different_registers(to, value, count, rtmp);
8651 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8652 Label L_fill_2_bytes, L_fill_4_bytes;
8653
8654 int shift = -1;
8655 switch (t) {
8656 case T_BYTE:
8657 shift = 2;
8658 break;
8659 case T_SHORT:
8660 shift = 1;
8661 break;
8662 case T_INT:
8663 shift = 0;
8664 break;
8665 default: ShouldNotReachHere();
8666 }
8667
8668 if (t == T_BYTE) {
8669 andl(value, 0xff);
8670 movl(rtmp, value);
8671 shll(rtmp, 8);
8672 orl(value, rtmp);
8673 }
8674 if (t == T_SHORT) {
8675 andl(value, 0xffff);
8676 }
8677 if (t == T_BYTE || t == T_SHORT) {
8678 movl(rtmp, value);
8679 shll(rtmp, 16);
8680 orl(value, rtmp);
8681 }
8682
8683 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8684 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8685 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8686 // align source address at 4 bytes address boundary
8687 if (t == T_BYTE) {
8688 // One byte misalignment happens only for byte arrays
8689 testptr(to, 1);
8690 jccb(Assembler::zero, L_skip_align1);
8691 movb(Address(to, 0), value);
8692 increment(to);
8693 decrement(count);
8694 BIND(L_skip_align1);
8695 }
8696 // Two bytes misalignment happens only for byte and short (char) arrays
8697 testptr(to, 2);
8698 jccb(Assembler::zero, L_skip_align2);
8699 movw(Address(to, 0), value);
8700 addptr(to, 2);
8701 subl(count, 1<<(shift-1));
8702 BIND(L_skip_align2);
8703 }
8704 if (UseSSE < 2) {
8705 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8706 // Fill 32-byte chunks
8707 subl(count, 8 << shift);
8708 jcc(Assembler::less, L_check_fill_8_bytes);
8709 align(16);
8710
8711 BIND(L_fill_32_bytes_loop);
8712
8713 for (int i = 0; i < 32; i += 4) {
8714 movl(Address(to, i), value);
8715 }
8716
8717 addptr(to, 32);
8718 subl(count, 8 << shift);
8719 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8720 BIND(L_check_fill_8_bytes);
8721 addl(count, 8 << shift);
8722 jccb(Assembler::zero, L_exit);
8723 jmpb(L_fill_8_bytes);
8724
8725 //
8726 // length is too short, just fill qwords
8727 //
8728 BIND(L_fill_8_bytes_loop);
8729 movl(Address(to, 0), value);
8730 movl(Address(to, 4), value);
8731 addptr(to, 8);
8732 BIND(L_fill_8_bytes);
8733 subl(count, 1 << (shift + 1));
8734 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8735 // fall through to fill 4 bytes
8736 } else {
8737 Label L_fill_32_bytes;
8738 if (!UseUnalignedLoadStores) {
8739 // align to 8 bytes, we know we are 4 byte aligned to start
8740 testptr(to, 4);
8741 jccb(Assembler::zero, L_fill_32_bytes);
8742 movl(Address(to, 0), value);
8743 addptr(to, 4);
8744 subl(count, 1<<shift);
8745 }
8746 BIND(L_fill_32_bytes);
8747 {
8748 assert( UseSSE >= 2, "supported cpu only" );
8749 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8750 if (UseAVX > 2) {
8751 movl(rtmp, 0xffff);
8752 kmovwl(k1, rtmp);
8753 }
8754 movdl(xtmp, value);
8755 if (UseAVX > 2 && UseUnalignedLoadStores) {
8756 // Fill 64-byte chunks
8757 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8758 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8759
8760 subl(count, 16 << shift);
8761 jcc(Assembler::less, L_check_fill_32_bytes);
8762 align(16);
8763
8764 BIND(L_fill_64_bytes_loop);
8765 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8766 addptr(to, 64);
8767 subl(count, 16 << shift);
8768 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8769
8770 BIND(L_check_fill_32_bytes);
8771 addl(count, 8 << shift);
8772 jccb(Assembler::less, L_check_fill_8_bytes);
8773 vmovdqu(Address(to, 0), xtmp);
8774 addptr(to, 32);
8775 subl(count, 8 << shift);
8776
8777 BIND(L_check_fill_8_bytes);
8778 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8779 // Fill 64-byte chunks
8780 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8781 vpbroadcastd(xtmp, xtmp);
8782
8783 subl(count, 16 << shift);
8784 jcc(Assembler::less, L_check_fill_32_bytes);
8785 align(16);
8786
8787 BIND(L_fill_64_bytes_loop);
8788 vmovdqu(Address(to, 0), xtmp);
8789 vmovdqu(Address(to, 32), xtmp);
8790 addptr(to, 64);
8791 subl(count, 16 << shift);
8792 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8793
8794 BIND(L_check_fill_32_bytes);
8795 addl(count, 8 << shift);
8796 jccb(Assembler::less, L_check_fill_8_bytes);
8797 vmovdqu(Address(to, 0), xtmp);
8798 addptr(to, 32);
8799 subl(count, 8 << shift);
8800
8801 BIND(L_check_fill_8_bytes);
8802 // clean upper bits of YMM registers
8803 movdl(xtmp, value);
8804 pshufd(xtmp, xtmp, 0);
8805 } else {
8806 // Fill 32-byte chunks
8807 pshufd(xtmp, xtmp, 0);
8808
8809 subl(count, 8 << shift);
8810 jcc(Assembler::less, L_check_fill_8_bytes);
8811 align(16);
8812
8813 BIND(L_fill_32_bytes_loop);
8814
8815 if (UseUnalignedLoadStores) {
8816 movdqu(Address(to, 0), xtmp);
8817 movdqu(Address(to, 16), xtmp);
8818 } else {
8819 movq(Address(to, 0), xtmp);
8820 movq(Address(to, 8), xtmp);
8821 movq(Address(to, 16), xtmp);
8822 movq(Address(to, 24), xtmp);
8823 }
8824
8825 addptr(to, 32);
8826 subl(count, 8 << shift);
8827 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8828
8829 BIND(L_check_fill_8_bytes);
8830 }
8831 addl(count, 8 << shift);
8832 jccb(Assembler::zero, L_exit);
8833 jmpb(L_fill_8_bytes);
8834
8835 //
8836 // length is too short, just fill qwords
8837 //
8838 BIND(L_fill_8_bytes_loop);
8839 movq(Address(to, 0), xtmp);
8840 addptr(to, 8);
8841 BIND(L_fill_8_bytes);
8842 subl(count, 1 << (shift + 1));
8843 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8844 }
8845 }
8846 // fill trailing 4 bytes
8847 BIND(L_fill_4_bytes);
8848 testl(count, 1<<shift);
8849 jccb(Assembler::zero, L_fill_2_bytes);
8850 movl(Address(to, 0), value);
8851 if (t == T_BYTE || t == T_SHORT) {
8852 addptr(to, 4);
8853 BIND(L_fill_2_bytes);
8854 // fill trailing 2 bytes
8855 testl(count, 1<<(shift-1));
8856 jccb(Assembler::zero, L_fill_byte);
8857 movw(Address(to, 0), value);
8858 if (t == T_BYTE) {
8859 addptr(to, 2);
8860 BIND(L_fill_byte);
8861 // fill trailing byte
8862 testl(count, 1);
8863 jccb(Assembler::zero, L_exit);
8864 movb(Address(to, 0), value);
8865 } else {
8866 BIND(L_fill_byte);
8867 }
8868 } else {
8869 BIND(L_fill_2_bytes);
8870 }
8871 BIND(L_exit);
8872 }
8873
8874 // encode char[] to byte[] in ISO_8859_1
8875 //@HotSpotIntrinsicCandidate
8876 //private static int implEncodeISOArray(byte[] sa, int sp,
8877 //byte[] da, int dp, int len) {
8878 // int i = 0;
8879 // for (; i < len; i++) {
8880 // char c = StringUTF16.getChar(sa, sp++);
8881 // if (c > '\u00FF')
8882 // break;
8883 // da[dp++] = (byte)c;
8884 // }
8885 // return i;
8886 //}
8887 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8888 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8889 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8890 Register tmp5, Register result) {
8891
8892 // rsi: src
8893 // rdi: dst
8894 // rdx: len
8895 // rcx: tmp5
8896 // rax: result
8897 ShortBranchVerifier sbv(this);
8898 assert_different_registers(src, dst, len, tmp5, result);
8899 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8900
8901 // set result
8902 xorl(result, result);
8903 // check for zero length
8904 testl(len, len);
8905 jcc(Assembler::zero, L_done);
8906
8907 movl(result, len);
8908
8909 // Setup pointers
8910 lea(src, Address(src, len, Address::times_2)); // char[]
8911 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8912 negptr(len);
8913
8914 if (UseSSE42Intrinsics || UseAVX >= 2) {
8915 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8916 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8917
8918 if (UseAVX >= 2) {
8919 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8920 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8921 movdl(tmp1Reg, tmp5);
8922 vpbroadcastd(tmp1Reg, tmp1Reg);
8923 jmp(L_chars_32_check);
8924
8925 bind(L_copy_32_chars);
8926 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8927 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8928 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8929 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8930 jccb(Assembler::notZero, L_copy_32_chars_exit);
8931 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8932 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8933 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8934
8935 bind(L_chars_32_check);
8936 addptr(len, 32);
8937 jcc(Assembler::lessEqual, L_copy_32_chars);
8938
8939 bind(L_copy_32_chars_exit);
8940 subptr(len, 16);
8941 jccb(Assembler::greater, L_copy_16_chars_exit);
8942
8943 } else if (UseSSE42Intrinsics) {
8944 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8945 movdl(tmp1Reg, tmp5);
8946 pshufd(tmp1Reg, tmp1Reg, 0);
8947 jmpb(L_chars_16_check);
8948 }
8949
8950 bind(L_copy_16_chars);
8951 if (UseAVX >= 2) {
8952 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8953 vptest(tmp2Reg, tmp1Reg);
8954 jcc(Assembler::notZero, L_copy_16_chars_exit);
8955 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8956 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8957 } else {
8958 if (UseAVX > 0) {
8959 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8960 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8961 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8962 } else {
8963 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8964 por(tmp2Reg, tmp3Reg);
8965 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8966 por(tmp2Reg, tmp4Reg);
8967 }
8968 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8969 jccb(Assembler::notZero, L_copy_16_chars_exit);
8970 packuswb(tmp3Reg, tmp4Reg);
8971 }
8972 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8973
8974 bind(L_chars_16_check);
8975 addptr(len, 16);
8976 jcc(Assembler::lessEqual, L_copy_16_chars);
8977
8978 bind(L_copy_16_chars_exit);
8979 if (UseAVX >= 2) {
8980 // clean upper bits of YMM registers
8981 vpxor(tmp2Reg, tmp2Reg);
8982 vpxor(tmp3Reg, tmp3Reg);
8983 vpxor(tmp4Reg, tmp4Reg);
8984 movdl(tmp1Reg, tmp5);
8985 pshufd(tmp1Reg, tmp1Reg, 0);
8986 }
8987 subptr(len, 8);
8988 jccb(Assembler::greater, L_copy_8_chars_exit);
8989
8990 bind(L_copy_8_chars);
8991 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8992 ptest(tmp3Reg, tmp1Reg);
8993 jccb(Assembler::notZero, L_copy_8_chars_exit);
8994 packuswb(tmp3Reg, tmp1Reg);
8995 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8996 addptr(len, 8);
8997 jccb(Assembler::lessEqual, L_copy_8_chars);
8998
8999 bind(L_copy_8_chars_exit);
9000 subptr(len, 8);
9001 jccb(Assembler::zero, L_done);
9002 }
9003
9004 bind(L_copy_1_char);
9005 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
9006 testl(tmp5, 0xff00); // check if Unicode char
9007 jccb(Assembler::notZero, L_copy_1_char_exit);
9008 movb(Address(dst, len, Address::times_1, 0), tmp5);
9009 addptr(len, 1);
9010 jccb(Assembler::less, L_copy_1_char);
9011
9012 bind(L_copy_1_char_exit);
9013 addptr(result, len); // len is negative count of not processed elements
9014
9015 bind(L_done);
9016 }
9017
9018 #ifdef _LP64
9019 /**
9020 * Helper for multiply_to_len().
9021 */
9022 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
9023 addq(dest_lo, src1);
9024 adcq(dest_hi, 0);
9025 addq(dest_lo, src2);
9026 adcq(dest_hi, 0);
9027 }
9028
9029 /**
9030 * Multiply 64 bit by 64 bit first loop.
9031 */
9032 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
9033 Register y, Register y_idx, Register z,
9034 Register carry, Register product,
9035 Register idx, Register kdx) {
9036 //
9037 // jlong carry, x[], y[], z[];
9038 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9039 // huge_128 product = y[idx] * x[xstart] + carry;
9040 // z[kdx] = (jlong)product;
9041 // carry = (jlong)(product >>> 64);
9042 // }
9043 // z[xstart] = carry;
9044 //
9045
9046 Label L_first_loop, L_first_loop_exit;
9047 Label L_one_x, L_one_y, L_multiply;
9048
9049 decrementl(xstart);
9050 jcc(Assembler::negative, L_one_x);
9051
9052 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9053 rorq(x_xstart, 32); // convert big-endian to little-endian
9054
9055 bind(L_first_loop);
9056 decrementl(idx);
9057 jcc(Assembler::negative, L_first_loop_exit);
9058 decrementl(idx);
9059 jcc(Assembler::negative, L_one_y);
9060 movq(y_idx, Address(y, idx, Address::times_4, 0));
9061 rorq(y_idx, 32); // convert big-endian to little-endian
9062 bind(L_multiply);
9063 movq(product, x_xstart);
9064 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
9065 addq(product, carry);
9066 adcq(rdx, 0);
9067 subl(kdx, 2);
9068 movl(Address(z, kdx, Address::times_4, 4), product);
9069 shrq(product, 32);
9070 movl(Address(z, kdx, Address::times_4, 0), product);
9071 movq(carry, rdx);
9072 jmp(L_first_loop);
9073
9074 bind(L_one_y);
9075 movl(y_idx, Address(y, 0));
9076 jmp(L_multiply);
9077
9078 bind(L_one_x);
9079 movl(x_xstart, Address(x, 0));
9080 jmp(L_first_loop);
9081
9082 bind(L_first_loop_exit);
9083 }
9084
9085 /**
9086 * Multiply 64 bit by 64 bit and add 128 bit.
9087 */
9088 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
9089 Register yz_idx, Register idx,
9090 Register carry, Register product, int offset) {
9091 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
9092 // z[kdx] = (jlong)product;
9093
9094 movq(yz_idx, Address(y, idx, Address::times_4, offset));
9095 rorq(yz_idx, 32); // convert big-endian to little-endian
9096 movq(product, x_xstart);
9097 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9098 movq(yz_idx, Address(z, idx, Address::times_4, offset));
9099 rorq(yz_idx, 32); // convert big-endian to little-endian
9100
9101 add2_with_carry(rdx, product, carry, yz_idx);
9102
9103 movl(Address(z, idx, Address::times_4, offset+4), product);
9104 shrq(product, 32);
9105 movl(Address(z, idx, Address::times_4, offset), product);
9106
9107 }
9108
9109 /**
9110 * Multiply 128 bit by 128 bit. Unrolled inner loop.
9111 */
9112 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
9113 Register yz_idx, Register idx, Register jdx,
9114 Register carry, Register product,
9115 Register carry2) {
9116 // jlong carry, x[], y[], z[];
9117 // int kdx = ystart+1;
9118 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9119 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
9120 // z[kdx+idx+1] = (jlong)product;
9121 // jlong carry2 = (jlong)(product >>> 64);
9122 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
9123 // z[kdx+idx] = (jlong)product;
9124 // carry = (jlong)(product >>> 64);
9125 // }
9126 // idx += 2;
9127 // if (idx > 0) {
9128 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
9129 // z[kdx+idx] = (jlong)product;
9130 // carry = (jlong)(product >>> 64);
9131 // }
9132 //
9133
9134 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9135
9136 movl(jdx, idx);
9137 andl(jdx, 0xFFFFFFFC);
9138 shrl(jdx, 2);
9139
9140 bind(L_third_loop);
9141 subl(jdx, 1);
9142 jcc(Assembler::negative, L_third_loop_exit);
9143 subl(idx, 4);
9144
9145 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
9146 movq(carry2, rdx);
9147
9148 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
9149 movq(carry, rdx);
9150 jmp(L_third_loop);
9151
9152 bind (L_third_loop_exit);
9153
9154 andl (idx, 0x3);
9155 jcc(Assembler::zero, L_post_third_loop_done);
9156
9157 Label L_check_1;
9158 subl(idx, 2);
9159 jcc(Assembler::negative, L_check_1);
9160
9161 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
9162 movq(carry, rdx);
9163
9164 bind (L_check_1);
9165 addl (idx, 0x2);
9166 andl (idx, 0x1);
9167 subl(idx, 1);
9168 jcc(Assembler::negative, L_post_third_loop_done);
9169
9170 movl(yz_idx, Address(y, idx, Address::times_4, 0));
9171 movq(product, x_xstart);
9172 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9173 movl(yz_idx, Address(z, idx, Address::times_4, 0));
9174
9175 add2_with_carry(rdx, product, yz_idx, carry);
9176
9177 movl(Address(z, idx, Address::times_4, 0), product);
9178 shrq(product, 32);
9179
9180 shlq(rdx, 32);
9181 orq(product, rdx);
9182 movq(carry, product);
9183
9184 bind(L_post_third_loop_done);
9185 }
9186
9187 /**
9188 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9189 *
9190 */
9191 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9192 Register carry, Register carry2,
9193 Register idx, Register jdx,
9194 Register yz_idx1, Register yz_idx2,
9195 Register tmp, Register tmp3, Register tmp4) {
9196 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9197
9198 // jlong carry, x[], y[], z[];
9199 // int kdx = ystart+1;
9200 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9201 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9202 // jlong carry2 = (jlong)(tmp3 >>> 64);
9203 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
9204 // carry = (jlong)(tmp4 >>> 64);
9205 // z[kdx+idx+1] = (jlong)tmp3;
9206 // z[kdx+idx] = (jlong)tmp4;
9207 // }
9208 // idx += 2;
9209 // if (idx > 0) {
9210 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9211 // z[kdx+idx] = (jlong)yz_idx1;
9212 // carry = (jlong)(yz_idx1 >>> 64);
9213 // }
9214 //
9215
9216 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9217
9218 movl(jdx, idx);
9219 andl(jdx, 0xFFFFFFFC);
9220 shrl(jdx, 2);
9221
9222 bind(L_third_loop);
9223 subl(jdx, 1);
9224 jcc(Assembler::negative, L_third_loop_exit);
9225 subl(idx, 4);
9226
9227 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
9228 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9229 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
9230 rorxq(yz_idx2, yz_idx2, 32);
9231
9232 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9233 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
9234
9235 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
9236 rorxq(yz_idx1, yz_idx1, 32);
9237 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9238 rorxq(yz_idx2, yz_idx2, 32);
9239
9240 if (VM_Version::supports_adx()) {
9241 adcxq(tmp3, carry);
9242 adoxq(tmp3, yz_idx1);
9243
9244 adcxq(tmp4, tmp);
9245 adoxq(tmp4, yz_idx2);
9246
9247 movl(carry, 0); // does not affect flags
9248 adcxq(carry2, carry);
9249 adoxq(carry2, carry);
9250 } else {
9251 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9252 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9253 }
9254 movq(carry, carry2);
9255
9256 movl(Address(z, idx, Address::times_4, 12), tmp3);
9257 shrq(tmp3, 32);
9258 movl(Address(z, idx, Address::times_4, 8), tmp3);
9259
9260 movl(Address(z, idx, Address::times_4, 4), tmp4);
9261 shrq(tmp4, 32);
9262 movl(Address(z, idx, Address::times_4, 0), tmp4);
9263
9264 jmp(L_third_loop);
9265
9266 bind (L_third_loop_exit);
9267
9268 andl (idx, 0x3);
9269 jcc(Assembler::zero, L_post_third_loop_done);
9270
9271 Label L_check_1;
9272 subl(idx, 2);
9273 jcc(Assembler::negative, L_check_1);
9274
9275 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
9276 rorxq(yz_idx1, yz_idx1, 32);
9277 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9278 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9279 rorxq(yz_idx2, yz_idx2, 32);
9280
9281 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9282
9283 movl(Address(z, idx, Address::times_4, 4), tmp3);
9284 shrq(tmp3, 32);
9285 movl(Address(z, idx, Address::times_4, 0), tmp3);
9286 movq(carry, tmp4);
9287
9288 bind (L_check_1);
9289 addl (idx, 0x2);
9290 andl (idx, 0x1);
9291 subl(idx, 1);
9292 jcc(Assembler::negative, L_post_third_loop_done);
9293 movl(tmp4, Address(y, idx, Address::times_4, 0));
9294 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
9295 movl(tmp4, Address(z, idx, Address::times_4, 0));
9296
9297 add2_with_carry(carry2, tmp3, tmp4, carry);
9298
9299 movl(Address(z, idx, Address::times_4, 0), tmp3);
9300 shrq(tmp3, 32);
9301
9302 shlq(carry2, 32);
9303 orq(tmp3, carry2);
9304 movq(carry, tmp3);
9305
9306 bind(L_post_third_loop_done);
9307 }
9308
9309 /**
9310 * Code for BigInteger::multiplyToLen() instrinsic.
9311 *
9312 * rdi: x
9313 * rax: xlen
9314 * rsi: y
9315 * rcx: ylen
9316 * r8: z
9317 * r11: zlen
9318 * r12: tmp1
9319 * r13: tmp2
9320 * r14: tmp3
9321 * r15: tmp4
9322 * rbx: tmp5
9323 *
9324 */
9325 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9326 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9327 ShortBranchVerifier sbv(this);
9328 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9329
9330 push(tmp1);
9331 push(tmp2);
9332 push(tmp3);
9333 push(tmp4);
9334 push(tmp5);
9335
9336 push(xlen);
9337 push(zlen);
9338
9339 const Register idx = tmp1;
9340 const Register kdx = tmp2;
9341 const Register xstart = tmp3;
9342
9343 const Register y_idx = tmp4;
9344 const Register carry = tmp5;
9345 const Register product = xlen;
9346 const Register x_xstart = zlen; // reuse register
9347
9348 // First Loop.
9349 //
9350 // final static long LONG_MASK = 0xffffffffL;
9351 // int xstart = xlen - 1;
9352 // int ystart = ylen - 1;
9353 // long carry = 0;
9354 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9355 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9356 // z[kdx] = (int)product;
9357 // carry = product >>> 32;
9358 // }
9359 // z[xstart] = (int)carry;
9360 //
9361
9362 movl(idx, ylen); // idx = ylen;
9363 movl(kdx, zlen); // kdx = xlen+ylen;
9364 xorq(carry, carry); // carry = 0;
9365
9366 Label L_done;
9367
9368 movl(xstart, xlen);
9369 decrementl(xstart);
9370 jcc(Assembler::negative, L_done);
9371
9372 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9373
9374 Label L_second_loop;
9375 testl(kdx, kdx);
9376 jcc(Assembler::zero, L_second_loop);
9377
9378 Label L_carry;
9379 subl(kdx, 1);
9380 jcc(Assembler::zero, L_carry);
9381
9382 movl(Address(z, kdx, Address::times_4, 0), carry);
9383 shrq(carry, 32);
9384 subl(kdx, 1);
9385
9386 bind(L_carry);
9387 movl(Address(z, kdx, Address::times_4, 0), carry);
9388
9389 // Second and third (nested) loops.
9390 //
9391 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9392 // carry = 0;
9393 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9394 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9395 // (z[k] & LONG_MASK) + carry;
9396 // z[k] = (int)product;
9397 // carry = product >>> 32;
9398 // }
9399 // z[i] = (int)carry;
9400 // }
9401 //
9402 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9403
9404 const Register jdx = tmp1;
9405
9406 bind(L_second_loop);
9407 xorl(carry, carry); // carry = 0;
9408 movl(jdx, ylen); // j = ystart+1
9409
9410 subl(xstart, 1); // i = xstart-1;
9411 jcc(Assembler::negative, L_done);
9412
9413 push (z);
9414
9415 Label L_last_x;
9416 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9417 subl(xstart, 1); // i = xstart-1;
9418 jcc(Assembler::negative, L_last_x);
9419
9420 if (UseBMI2Instructions) {
9421 movq(rdx, Address(x, xstart, Address::times_4, 0));
9422 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9423 } else {
9424 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9425 rorq(x_xstart, 32); // convert big-endian to little-endian
9426 }
9427
9428 Label L_third_loop_prologue;
9429 bind(L_third_loop_prologue);
9430
9431 push (x);
9432 push (xstart);
9433 push (ylen);
9434
9435
9436 if (UseBMI2Instructions) {
9437 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9438 } else { // !UseBMI2Instructions
9439 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9440 }
9441
9442 pop(ylen);
9443 pop(xlen);
9444 pop(x);
9445 pop(z);
9446
9447 movl(tmp3, xlen);
9448 addl(tmp3, 1);
9449 movl(Address(z, tmp3, Address::times_4, 0), carry);
9450 subl(tmp3, 1);
9451 jccb(Assembler::negative, L_done);
9452
9453 shrq(carry, 32);
9454 movl(Address(z, tmp3, Address::times_4, 0), carry);
9455 jmp(L_second_loop);
9456
9457 // Next infrequent code is moved outside loops.
9458 bind(L_last_x);
9459 if (UseBMI2Instructions) {
9460 movl(rdx, Address(x, 0));
9461 } else {
9462 movl(x_xstart, Address(x, 0));
9463 }
9464 jmp(L_third_loop_prologue);
9465
9466 bind(L_done);
9467
9468 pop(zlen);
9469 pop(xlen);
9470
9471 pop(tmp5);
9472 pop(tmp4);
9473 pop(tmp3);
9474 pop(tmp2);
9475 pop(tmp1);
9476 }
9477
9478 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9479 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9480 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9481 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9482 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9483 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9484 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9485 Label SAME_TILL_END, DONE;
9486 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9487
9488 //scale is in rcx in both Win64 and Unix
9489 ShortBranchVerifier sbv(this);
9490
9491 shlq(length);
9492 xorq(result, result);
9493
9494 if ((UseAVX > 2) &&
9495 VM_Version::supports_avx512vlbw()) {
9496 set_vector_masking(); // opening of the stub context for programming mask registers
9497 cmpq(length, 64);
9498 jcc(Assembler::less, VECTOR32_TAIL);
9499 movq(tmp1, length);
9500 andq(tmp1, 0x3F); // tail count
9501 andq(length, ~(0x3F)); //vector count
9502
9503 bind(VECTOR64_LOOP);
9504 // AVX512 code to compare 64 byte vectors.
9505 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9506 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9507 kortestql(k7, k7);
9508 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9509 addq(result, 64);
9510 subq(length, 64);
9511 jccb(Assembler::notZero, VECTOR64_LOOP);
9512
9513 //bind(VECTOR64_TAIL);
9514 testq(tmp1, tmp1);
9515 jcc(Assembler::zero, SAME_TILL_END);
9516
9517 bind(VECTOR64_TAIL);
9518 // AVX512 code to compare upto 63 byte vectors.
9519 // Save k1
9520 kmovql(k3, k1);
9521 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9522 shlxq(tmp2, tmp2, tmp1);
9523 notq(tmp2);
9524 kmovql(k1, tmp2);
9525
9526 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9527 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9528
9529 ktestql(k7, k1);
9530 // Restore k1
9531 kmovql(k1, k3);
9532 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9533
9534 bind(VECTOR64_NOT_EQUAL);
9535 kmovql(tmp1, k7);
9536 notq(tmp1);
9537 tzcntq(tmp1, tmp1);
9538 addq(result, tmp1);
9539 shrq(result);
9540 jmp(DONE);
9541 bind(VECTOR32_TAIL);
9542 clear_vector_masking(); // closing of the stub context for programming mask registers
9543 }
9544
9545 cmpq(length, 8);
9546 jcc(Assembler::equal, VECTOR8_LOOP);
9547 jcc(Assembler::less, VECTOR4_TAIL);
9548
9549 if (UseAVX >= 2) {
9550
9551 cmpq(length, 16);
9552 jcc(Assembler::equal, VECTOR16_LOOP);
9553 jcc(Assembler::less, VECTOR8_LOOP);
9554
9555 cmpq(length, 32);
9556 jccb(Assembler::less, VECTOR16_TAIL);
9557
9558 subq(length, 32);
9559 bind(VECTOR32_LOOP);
9560 vmovdqu(rymm0, Address(obja, result));
9561 vmovdqu(rymm1, Address(objb, result));
9562 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9563 vptest(rymm2, rymm2);
9564 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9565 addq(result, 32);
9566 subq(length, 32);
9567 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9568 addq(length, 32);
9569 jcc(Assembler::equal, SAME_TILL_END);
9570 //falling through if less than 32 bytes left //close the branch here.
9571
9572 bind(VECTOR16_TAIL);
9573 cmpq(length, 16);
9574 jccb(Assembler::less, VECTOR8_TAIL);
9575 bind(VECTOR16_LOOP);
9576 movdqu(rymm0, Address(obja, result));
9577 movdqu(rymm1, Address(objb, result));
9578 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9579 ptest(rymm2, rymm2);
9580 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9581 addq(result, 16);
9582 subq(length, 16);
9583 jcc(Assembler::equal, SAME_TILL_END);
9584 //falling through if less than 16 bytes left
9585 } else {//regular intrinsics
9586
9587 cmpq(length, 16);
9588 jccb(Assembler::less, VECTOR8_TAIL);
9589
9590 subq(length, 16);
9591 bind(VECTOR16_LOOP);
9592 movdqu(rymm0, Address(obja, result));
9593 movdqu(rymm1, Address(objb, result));
9594 pxor(rymm0, rymm1);
9595 ptest(rymm0, rymm0);
9596 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9597 addq(result, 16);
9598 subq(length, 16);
9599 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9600 addq(length, 16);
9601 jcc(Assembler::equal, SAME_TILL_END);
9602 //falling through if less than 16 bytes left
9603 }
9604
9605 bind(VECTOR8_TAIL);
9606 cmpq(length, 8);
9607 jccb(Assembler::less, VECTOR4_TAIL);
9608 bind(VECTOR8_LOOP);
9609 movq(tmp1, Address(obja, result));
9610 movq(tmp2, Address(objb, result));
9611 xorq(tmp1, tmp2);
9612 testq(tmp1, tmp1);
9613 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9614 addq(result, 8);
9615 subq(length, 8);
9616 jcc(Assembler::equal, SAME_TILL_END);
9617 //falling through if less than 8 bytes left
9618
9619 bind(VECTOR4_TAIL);
9620 cmpq(length, 4);
9621 jccb(Assembler::less, BYTES_TAIL);
9622 bind(VECTOR4_LOOP);
9623 movl(tmp1, Address(obja, result));
9624 xorl(tmp1, Address(objb, result));
9625 testl(tmp1, tmp1);
9626 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9627 addq(result, 4);
9628 subq(length, 4);
9629 jcc(Assembler::equal, SAME_TILL_END);
9630 //falling through if less than 4 bytes left
9631
9632 bind(BYTES_TAIL);
9633 bind(BYTES_LOOP);
9634 load_unsigned_byte(tmp1, Address(obja, result));
9635 load_unsigned_byte(tmp2, Address(objb, result));
9636 xorl(tmp1, tmp2);
9637 testl(tmp1, tmp1);
9638 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9639 decq(length);
9640 jccb(Assembler::zero, SAME_TILL_END);
9641 incq(result);
9642 load_unsigned_byte(tmp1, Address(obja, result));
9643 load_unsigned_byte(tmp2, Address(objb, result));
9644 xorl(tmp1, tmp2);
9645 testl(tmp1, tmp1);
9646 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9647 decq(length);
9648 jccb(Assembler::zero, SAME_TILL_END);
9649 incq(result);
9650 load_unsigned_byte(tmp1, Address(obja, result));
9651 load_unsigned_byte(tmp2, Address(objb, result));
9652 xorl(tmp1, tmp2);
9653 testl(tmp1, tmp1);
9654 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9655 jmpb(SAME_TILL_END);
9656
9657 if (UseAVX >= 2) {
9658 bind(VECTOR32_NOT_EQUAL);
9659 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9660 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9661 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9662 vpmovmskb(tmp1, rymm0);
9663 bsfq(tmp1, tmp1);
9664 addq(result, tmp1);
9665 shrq(result);
9666 jmpb(DONE);
9667 }
9668
9669 bind(VECTOR16_NOT_EQUAL);
9670 if (UseAVX >= 2) {
9671 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9672 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9673 pxor(rymm0, rymm2);
9674 } else {
9675 pcmpeqb(rymm2, rymm2);
9676 pxor(rymm0, rymm1);
9677 pcmpeqb(rymm0, rymm1);
9678 pxor(rymm0, rymm2);
9679 }
9680 pmovmskb(tmp1, rymm0);
9681 bsfq(tmp1, tmp1);
9682 addq(result, tmp1);
9683 shrq(result);
9684 jmpb(DONE);
9685
9686 bind(VECTOR8_NOT_EQUAL);
9687 bind(VECTOR4_NOT_EQUAL);
9688 bsfq(tmp1, tmp1);
9689 shrq(tmp1, 3);
9690 addq(result, tmp1);
9691 bind(BYTES_NOT_EQUAL);
9692 shrq(result);
9693 jmpb(DONE);
9694
9695 bind(SAME_TILL_END);
9696 mov64(result, -1);
9697
9698 bind(DONE);
9699 }
9700
9701 //Helper functions for square_to_len()
9702
9703 /**
9704 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9705 * Preserves x and z and modifies rest of the registers.
9706 */
9707 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9708 // Perform square and right shift by 1
9709 // Handle odd xlen case first, then for even xlen do the following
9710 // jlong carry = 0;
9711 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9712 // huge_128 product = x[j:j+1] * x[j:j+1];
9713 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9714 // z[i+2:i+3] = (jlong)(product >>> 1);
9715 // carry = (jlong)product;
9716 // }
9717
9718 xorq(tmp5, tmp5); // carry
9719 xorq(rdxReg, rdxReg);
9720 xorl(tmp1, tmp1); // index for x
9721 xorl(tmp4, tmp4); // index for z
9722
9723 Label L_first_loop, L_first_loop_exit;
9724
9725 testl(xlen, 1);
9726 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9727
9728 // Square and right shift by 1 the odd element using 32 bit multiply
9729 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9730 imulq(raxReg, raxReg);
9731 shrq(raxReg, 1);
9732 adcq(tmp5, 0);
9733 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9734 incrementl(tmp1);
9735 addl(tmp4, 2);
9736
9737 // Square and right shift by 1 the rest using 64 bit multiply
9738 bind(L_first_loop);
9739 cmpptr(tmp1, xlen);
9740 jccb(Assembler::equal, L_first_loop_exit);
9741
9742 // Square
9743 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9744 rorq(raxReg, 32); // convert big-endian to little-endian
9745 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9746
9747 // Right shift by 1 and save carry
9748 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9749 rcrq(rdxReg, 1);
9750 rcrq(raxReg, 1);
9751 adcq(tmp5, 0);
9752
9753 // Store result in z
9754 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9755 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9756
9757 // Update indices for x and z
9758 addl(tmp1, 2);
9759 addl(tmp4, 4);
9760 jmp(L_first_loop);
9761
9762 bind(L_first_loop_exit);
9763 }
9764
9765
9766 /**
9767 * Perform the following multiply add operation using BMI2 instructions
9768 * carry:sum = sum + op1*op2 + carry
9769 * op2 should be in rdx
9770 * op2 is preserved, all other registers are modified
9771 */
9772 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9773 // assert op2 is rdx
9774 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9775 addq(sum, carry);
9776 adcq(tmp2, 0);
9777 addq(sum, op1);
9778 adcq(tmp2, 0);
9779 movq(carry, tmp2);
9780 }
9781
9782 /**
9783 * Perform the following multiply add operation:
9784 * carry:sum = sum + op1*op2 + carry
9785 * Preserves op1, op2 and modifies rest of registers
9786 */
9787 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9788 // rdx:rax = op1 * op2
9789 movq(raxReg, op2);
9790 mulq(op1);
9791
9792 // rdx:rax = sum + carry + rdx:rax
9793 addq(sum, carry);
9794 adcq(rdxReg, 0);
9795 addq(sum, raxReg);
9796 adcq(rdxReg, 0);
9797
9798 // carry:sum = rdx:sum
9799 movq(carry, rdxReg);
9800 }
9801
9802 /**
9803 * Add 64 bit long carry into z[] with carry propogation.
9804 * Preserves z and carry register values and modifies rest of registers.
9805 *
9806 */
9807 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9808 Label L_fourth_loop, L_fourth_loop_exit;
9809
9810 movl(tmp1, 1);
9811 subl(zlen, 2);
9812 addq(Address(z, zlen, Address::times_4, 0), carry);
9813
9814 bind(L_fourth_loop);
9815 jccb(Assembler::carryClear, L_fourth_loop_exit);
9816 subl(zlen, 2);
9817 jccb(Assembler::negative, L_fourth_loop_exit);
9818 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9819 jmp(L_fourth_loop);
9820 bind(L_fourth_loop_exit);
9821 }
9822
9823 /**
9824 * Shift z[] left by 1 bit.
9825 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9826 *
9827 */
9828 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9829
9830 Label L_fifth_loop, L_fifth_loop_exit;
9831
9832 // Fifth loop
9833 // Perform primitiveLeftShift(z, zlen, 1)
9834
9835 const Register prev_carry = tmp1;
9836 const Register new_carry = tmp4;
9837 const Register value = tmp2;
9838 const Register zidx = tmp3;
9839
9840 // int zidx, carry;
9841 // long value;
9842 // carry = 0;
9843 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9844 // (carry:value) = (z[i] << 1) | carry ;
9845 // z[i] = value;
9846 // }
9847
9848 movl(zidx, zlen);
9849 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9850
9851 bind(L_fifth_loop);
9852 decl(zidx); // Use decl to preserve carry flag
9853 decl(zidx);
9854 jccb(Assembler::negative, L_fifth_loop_exit);
9855
9856 if (UseBMI2Instructions) {
9857 movq(value, Address(z, zidx, Address::times_4, 0));
9858 rclq(value, 1);
9859 rorxq(value, value, 32);
9860 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9861 }
9862 else {
9863 // clear new_carry
9864 xorl(new_carry, new_carry);
9865
9866 // Shift z[i] by 1, or in previous carry and save new carry
9867 movq(value, Address(z, zidx, Address::times_4, 0));
9868 shlq(value, 1);
9869 adcl(new_carry, 0);
9870
9871 orq(value, prev_carry);
9872 rorq(value, 0x20);
9873 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9874
9875 // Set previous carry = new carry
9876 movl(prev_carry, new_carry);
9877 }
9878 jmp(L_fifth_loop);
9879
9880 bind(L_fifth_loop_exit);
9881 }
9882
9883
9884 /**
9885 * Code for BigInteger::squareToLen() intrinsic
9886 *
9887 * rdi: x
9888 * rsi: len
9889 * r8: z
9890 * rcx: zlen
9891 * r12: tmp1
9892 * r13: tmp2
9893 * r14: tmp3
9894 * r15: tmp4
9895 * rbx: tmp5
9896 *
9897 */
9898 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9899
9900 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9901 push(tmp1);
9902 push(tmp2);
9903 push(tmp3);
9904 push(tmp4);
9905 push(tmp5);
9906
9907 // First loop
9908 // Store the squares, right shifted one bit (i.e., divided by 2).
9909 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9910
9911 // Add in off-diagonal sums.
9912 //
9913 // Second, third (nested) and fourth loops.
9914 // zlen +=2;
9915 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9916 // carry = 0;
9917 // long op2 = x[xidx:xidx+1];
9918 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9919 // k -= 2;
9920 // long op1 = x[j:j+1];
9921 // long sum = z[k:k+1];
9922 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9923 // z[k:k+1] = sum;
9924 // }
9925 // add_one_64(z, k, carry, tmp_regs);
9926 // }
9927
9928 const Register carry = tmp5;
9929 const Register sum = tmp3;
9930 const Register op1 = tmp4;
9931 Register op2 = tmp2;
9932
9933 push(zlen);
9934 push(len);
9935 addl(zlen,2);
9936 bind(L_second_loop);
9937 xorq(carry, carry);
9938 subl(zlen, 4);
9939 subl(len, 2);
9940 push(zlen);
9941 push(len);
9942 cmpl(len, 0);
9943 jccb(Assembler::lessEqual, L_second_loop_exit);
9944
9945 // Multiply an array by one 64 bit long.
9946 if (UseBMI2Instructions) {
9947 op2 = rdxReg;
9948 movq(op2, Address(x, len, Address::times_4, 0));
9949 rorxq(op2, op2, 32);
9950 }
9951 else {
9952 movq(op2, Address(x, len, Address::times_4, 0));
9953 rorq(op2, 32);
9954 }
9955
9956 bind(L_third_loop);
9957 decrementl(len);
9958 jccb(Assembler::negative, L_third_loop_exit);
9959 decrementl(len);
9960 jccb(Assembler::negative, L_last_x);
9961
9962 movq(op1, Address(x, len, Address::times_4, 0));
9963 rorq(op1, 32);
9964
9965 bind(L_multiply);
9966 subl(zlen, 2);
9967 movq(sum, Address(z, zlen, Address::times_4, 0));
9968
9969 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9970 if (UseBMI2Instructions) {
9971 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9972 }
9973 else {
9974 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9975 }
9976
9977 movq(Address(z, zlen, Address::times_4, 0), sum);
9978
9979 jmp(L_third_loop);
9980 bind(L_third_loop_exit);
9981
9982 // Fourth loop
9983 // Add 64 bit long carry into z with carry propogation.
9984 // Uses offsetted zlen.
9985 add_one_64(z, zlen, carry, tmp1);
9986
9987 pop(len);
9988 pop(zlen);
9989 jmp(L_second_loop);
9990
9991 // Next infrequent code is moved outside loops.
9992 bind(L_last_x);
9993 movl(op1, Address(x, 0));
9994 jmp(L_multiply);
9995
9996 bind(L_second_loop_exit);
9997 pop(len);
9998 pop(zlen);
9999 pop(len);
10000 pop(zlen);
10001
10002 // Fifth loop
10003 // Shift z left 1 bit.
10004 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
10005
10006 // z[zlen-1] |= x[len-1] & 1;
10007 movl(tmp3, Address(x, len, Address::times_4, -4));
10008 andl(tmp3, 1);
10009 orl(Address(z, zlen, Address::times_4, -4), tmp3);
10010
10011 pop(tmp5);
10012 pop(tmp4);
10013 pop(tmp3);
10014 pop(tmp2);
10015 pop(tmp1);
10016 }
10017
10018 /**
10019 * Helper function for mul_add()
10020 * Multiply the in[] by int k and add to out[] starting at offset offs using
10021 * 128 bit by 32 bit multiply and return the carry in tmp5.
10022 * Only quad int aligned length of in[] is operated on in this function.
10023 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
10024 * This function preserves out, in and k registers.
10025 * len and offset point to the appropriate index in "in" & "out" correspondingly
10026 * tmp5 has the carry.
10027 * other registers are temporary and are modified.
10028 *
10029 */
10030 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
10031 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
10032 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
10033
10034 Label L_first_loop, L_first_loop_exit;
10035
10036 movl(tmp1, len);
10037 shrl(tmp1, 2);
10038
10039 bind(L_first_loop);
10040 subl(tmp1, 1);
10041 jccb(Assembler::negative, L_first_loop_exit);
10042
10043 subl(len, 4);
10044 subl(offset, 4);
10045
10046 Register op2 = tmp2;
10047 const Register sum = tmp3;
10048 const Register op1 = tmp4;
10049 const Register carry = tmp5;
10050
10051 if (UseBMI2Instructions) {
10052 op2 = rdxReg;
10053 }
10054
10055 movq(op1, Address(in, len, Address::times_4, 8));
10056 rorq(op1, 32);
10057 movq(sum, Address(out, offset, Address::times_4, 8));
10058 rorq(sum, 32);
10059 if (UseBMI2Instructions) {
10060 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10061 }
10062 else {
10063 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10064 }
10065 // Store back in big endian from little endian
10066 rorq(sum, 0x20);
10067 movq(Address(out, offset, Address::times_4, 8), sum);
10068
10069 movq(op1, Address(in, len, Address::times_4, 0));
10070 rorq(op1, 32);
10071 movq(sum, Address(out, offset, Address::times_4, 0));
10072 rorq(sum, 32);
10073 if (UseBMI2Instructions) {
10074 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10075 }
10076 else {
10077 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10078 }
10079 // Store back in big endian from little endian
10080 rorq(sum, 0x20);
10081 movq(Address(out, offset, Address::times_4, 0), sum);
10082
10083 jmp(L_first_loop);
10084 bind(L_first_loop_exit);
10085 }
10086
10087 /**
10088 * Code for BigInteger::mulAdd() intrinsic
10089 *
10090 * rdi: out
10091 * rsi: in
10092 * r11: offs (out.length - offset)
10093 * rcx: len
10094 * r8: k
10095 * r12: tmp1
10096 * r13: tmp2
10097 * r14: tmp3
10098 * r15: tmp4
10099 * rbx: tmp5
10100 * Multiply the in[] by word k and add to out[], return the carry in rax
10101 */
10102 void MacroAssembler::mul_add(Register out, Register in, Register offs,
10103 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
10104 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
10105
10106 Label L_carry, L_last_in, L_done;
10107
10108 // carry = 0;
10109 // for (int j=len-1; j >= 0; j--) {
10110 // long product = (in[j] & LONG_MASK) * kLong +
10111 // (out[offs] & LONG_MASK) + carry;
10112 // out[offs--] = (int)product;
10113 // carry = product >>> 32;
10114 // }
10115 //
10116 push(tmp1);
10117 push(tmp2);
10118 push(tmp3);
10119 push(tmp4);
10120 push(tmp5);
10121
10122 Register op2 = tmp2;
10123 const Register sum = tmp3;
10124 const Register op1 = tmp4;
10125 const Register carry = tmp5;
10126
10127 if (UseBMI2Instructions) {
10128 op2 = rdxReg;
10129 movl(op2, k);
10130 }
10131 else {
10132 movl(op2, k);
10133 }
10134
10135 xorq(carry, carry);
10136
10137 //First loop
10138
10139 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
10140 //The carry is in tmp5
10141 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
10142
10143 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
10144 decrementl(len);
10145 jccb(Assembler::negative, L_carry);
10146 decrementl(len);
10147 jccb(Assembler::negative, L_last_in);
10148
10149 movq(op1, Address(in, len, Address::times_4, 0));
10150 rorq(op1, 32);
10151
10152 subl(offs, 2);
10153 movq(sum, Address(out, offs, Address::times_4, 0));
10154 rorq(sum, 32);
10155
10156 if (UseBMI2Instructions) {
10157 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10158 }
10159 else {
10160 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10161 }
10162
10163 // Store back in big endian from little endian
10164 rorq(sum, 0x20);
10165 movq(Address(out, offs, Address::times_4, 0), sum);
10166
10167 testl(len, len);
10168 jccb(Assembler::zero, L_carry);
10169
10170 //Multiply the last in[] entry, if any
10171 bind(L_last_in);
10172 movl(op1, Address(in, 0));
10173 movl(sum, Address(out, offs, Address::times_4, -4));
10174
10175 movl(raxReg, k);
10176 mull(op1); //tmp4 * eax -> edx:eax
10177 addl(sum, carry);
10178 adcl(rdxReg, 0);
10179 addl(sum, raxReg);
10180 adcl(rdxReg, 0);
10181 movl(carry, rdxReg);
10182
10183 movl(Address(out, offs, Address::times_4, -4), sum);
10184
10185 bind(L_carry);
10186 //return tmp5/carry as carry in rax
10187 movl(rax, carry);
10188
10189 bind(L_done);
10190 pop(tmp5);
10191 pop(tmp4);
10192 pop(tmp3);
10193 pop(tmp2);
10194 pop(tmp1);
10195 }
10196 #endif
10197
10198 /**
10199 * Emits code to update CRC-32 with a byte value according to constants in table
10200 *
10201 * @param [in,out]crc Register containing the crc.
10202 * @param [in]val Register containing the byte to fold into the CRC.
10203 * @param [in]table Register containing the table of crc constants.
10204 *
10205 * uint32_t crc;
10206 * val = crc_table[(val ^ crc) & 0xFF];
10207 * crc = val ^ (crc >> 8);
10208 *
10209 */
10210 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10211 xorl(val, crc);
10212 andl(val, 0xFF);
10213 shrl(crc, 8); // unsigned shift
10214 xorl(crc, Address(table, val, Address::times_4, 0));
10215 }
10216
10217 /**
10218 * Fold 128-bit data chunk
10219 */
10220 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10221 if (UseAVX > 0) {
10222 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10223 vpclmulldq(xcrc, xK, xcrc); // [63:0]
10224 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10225 pxor(xcrc, xtmp);
10226 } else {
10227 movdqa(xtmp, xcrc);
10228 pclmulhdq(xtmp, xK); // [123:64]
10229 pclmulldq(xcrc, xK); // [63:0]
10230 pxor(xcrc, xtmp);
10231 movdqu(xtmp, Address(buf, offset));
10232 pxor(xcrc, xtmp);
10233 }
10234 }
10235
10236 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10237 if (UseAVX > 0) {
10238 vpclmulhdq(xtmp, xK, xcrc);
10239 vpclmulldq(xcrc, xK, xcrc);
10240 pxor(xcrc, xbuf);
10241 pxor(xcrc, xtmp);
10242 } else {
10243 movdqa(xtmp, xcrc);
10244 pclmulhdq(xtmp, xK);
10245 pclmulldq(xcrc, xK);
10246 pxor(xcrc, xbuf);
10247 pxor(xcrc, xtmp);
10248 }
10249 }
10250
10251 /**
10252 * 8-bit folds to compute 32-bit CRC
10253 *
10254 * uint64_t xcrc;
10255 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10256 */
10257 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10258 movdl(tmp, xcrc);
10259 andl(tmp, 0xFF);
10260 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10261 psrldq(xcrc, 1); // unsigned shift one byte
10262 pxor(xcrc, xtmp);
10263 }
10264
10265 /**
10266 * uint32_t crc;
10267 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10268 */
10269 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10270 movl(tmp, crc);
10271 andl(tmp, 0xFF);
10272 shrl(crc, 8);
10273 xorl(crc, Address(table, tmp, Address::times_4, 0));
10274 }
10275
10276 /**
10277 * @param crc register containing existing CRC (32-bit)
10278 * @param buf register pointing to input byte buffer (byte*)
10279 * @param len register containing number of bytes
10280 * @param table register that will contain address of CRC table
10281 * @param tmp scratch register
10282 */
10283 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10284 assert_different_registers(crc, buf, len, table, tmp, rax);
10285
10286 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10287 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10288
10289 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10290 // context for the registers used, where all instructions below are using 128-bit mode
10291 // On EVEX without VL and BW, these instructions will all be AVX.
10292 if (VM_Version::supports_avx512vlbw()) {
10293 movl(tmp, 0xffff);
10294 kmovwl(k1, tmp);
10295 }
10296
10297 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10298 notl(crc); // ~crc
10299 cmpl(len, 16);
10300 jcc(Assembler::less, L_tail);
10301
10302 // Align buffer to 16 bytes
10303 movl(tmp, buf);
10304 andl(tmp, 0xF);
10305 jccb(Assembler::zero, L_aligned);
10306 subl(tmp, 16);
10307 addl(len, tmp);
10308
10309 align(4);
10310 BIND(L_align_loop);
10311 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10312 update_byte_crc32(crc, rax, table);
10313 increment(buf);
10314 incrementl(tmp);
10315 jccb(Assembler::less, L_align_loop);
10316
10317 BIND(L_aligned);
10318 movl(tmp, len); // save
10319 shrl(len, 4);
10320 jcc(Assembler::zero, L_tail_restore);
10321
10322 // Fold crc into first bytes of vector
10323 movdqa(xmm1, Address(buf, 0));
10324 movdl(rax, xmm1);
10325 xorl(crc, rax);
10326 if (VM_Version::supports_sse4_1()) {
10327 pinsrd(xmm1, crc, 0);
10328 } else {
10329 pinsrw(xmm1, crc, 0);
10330 shrl(crc, 16);
10331 pinsrw(xmm1, crc, 1);
10332 }
10333 addptr(buf, 16);
10334 subl(len, 4); // len > 0
10335 jcc(Assembler::less, L_fold_tail);
10336
10337 movdqa(xmm2, Address(buf, 0));
10338 movdqa(xmm3, Address(buf, 16));
10339 movdqa(xmm4, Address(buf, 32));
10340 addptr(buf, 48);
10341 subl(len, 3);
10342 jcc(Assembler::lessEqual, L_fold_512b);
10343
10344 // Fold total 512 bits of polynomial on each iteration,
10345 // 128 bits per each of 4 parallel streams.
10346 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10347
10348 align(32);
10349 BIND(L_fold_512b_loop);
10350 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10351 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10352 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10353 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10354 addptr(buf, 64);
10355 subl(len, 4);
10356 jcc(Assembler::greater, L_fold_512b_loop);
10357
10358 // Fold 512 bits to 128 bits.
10359 BIND(L_fold_512b);
10360 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10361 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10362 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10363 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10364
10365 // Fold the rest of 128 bits data chunks
10366 BIND(L_fold_tail);
10367 addl(len, 3);
10368 jccb(Assembler::lessEqual, L_fold_128b);
10369 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10370
10371 BIND(L_fold_tail_loop);
10372 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10373 addptr(buf, 16);
10374 decrementl(len);
10375 jccb(Assembler::greater, L_fold_tail_loop);
10376
10377 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10378 BIND(L_fold_128b);
10379 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10380 if (UseAVX > 0) {
10381 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10382 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10383 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10384 } else {
10385 movdqa(xmm2, xmm0);
10386 pclmulqdq(xmm2, xmm1, 0x1);
10387 movdqa(xmm3, xmm0);
10388 pand(xmm3, xmm2);
10389 pclmulqdq(xmm0, xmm3, 0x1);
10390 }
10391 psrldq(xmm1, 8);
10392 psrldq(xmm2, 4);
10393 pxor(xmm0, xmm1);
10394 pxor(xmm0, xmm2);
10395
10396 // 8 8-bit folds to compute 32-bit CRC.
10397 for (int j = 0; j < 4; j++) {
10398 fold_8bit_crc32(xmm0, table, xmm1, rax);
10399 }
10400 movdl(crc, xmm0); // mov 32 bits to general register
10401 for (int j = 0; j < 4; j++) {
10402 fold_8bit_crc32(crc, table, rax);
10403 }
10404
10405 BIND(L_tail_restore);
10406 movl(len, tmp); // restore
10407 BIND(L_tail);
10408 andl(len, 0xf);
10409 jccb(Assembler::zero, L_exit);
10410
10411 // Fold the rest of bytes
10412 align(4);
10413 BIND(L_tail_loop);
10414 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10415 update_byte_crc32(crc, rax, table);
10416 increment(buf);
10417 decrementl(len);
10418 jccb(Assembler::greater, L_tail_loop);
10419
10420 BIND(L_exit);
10421 notl(crc); // ~c
10422 }
10423
10424 #ifdef _LP64
10425 // S. Gueron / Information Processing Letters 112 (2012) 184
10426 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10427 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10428 // Output: the 64-bit carry-less product of B * CONST
10429 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10430 Register tmp1, Register tmp2, Register tmp3) {
10431 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10432 if (n > 0) {
10433 addq(tmp3, n * 256 * 8);
10434 }
10435 // Q1 = TABLEExt[n][B & 0xFF];
10436 movl(tmp1, in);
10437 andl(tmp1, 0x000000FF);
10438 shll(tmp1, 3);
10439 addq(tmp1, tmp3);
10440 movq(tmp1, Address(tmp1, 0));
10441
10442 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10443 movl(tmp2, in);
10444 shrl(tmp2, 8);
10445 andl(tmp2, 0x000000FF);
10446 shll(tmp2, 3);
10447 addq(tmp2, tmp3);
10448 movq(tmp2, Address(tmp2, 0));
10449
10450 shlq(tmp2, 8);
10451 xorq(tmp1, tmp2);
10452
10453 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10454 movl(tmp2, in);
10455 shrl(tmp2, 16);
10456 andl(tmp2, 0x000000FF);
10457 shll(tmp2, 3);
10458 addq(tmp2, tmp3);
10459 movq(tmp2, Address(tmp2, 0));
10460
10461 shlq(tmp2, 16);
10462 xorq(tmp1, tmp2);
10463
10464 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10465 shrl(in, 24);
10466 andl(in, 0x000000FF);
10467 shll(in, 3);
10468 addq(in, tmp3);
10469 movq(in, Address(in, 0));
10470
10471 shlq(in, 24);
10472 xorq(in, tmp1);
10473 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10474 }
10475
10476 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10477 Register in_out,
10478 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10479 XMMRegister w_xtmp2,
10480 Register tmp1,
10481 Register n_tmp2, Register n_tmp3) {
10482 if (is_pclmulqdq_supported) {
10483 movdl(w_xtmp1, in_out); // modified blindly
10484
10485 movl(tmp1, const_or_pre_comp_const_index);
10486 movdl(w_xtmp2, tmp1);
10487 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10488
10489 movdq(in_out, w_xtmp1);
10490 } else {
10491 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10492 }
10493 }
10494
10495 // Recombination Alternative 2: No bit-reflections
10496 // T1 = (CRC_A * U1) << 1
10497 // T2 = (CRC_B * U2) << 1
10498 // C1 = T1 >> 32
10499 // C2 = T2 >> 32
10500 // T1 = T1 & 0xFFFFFFFF
10501 // T2 = T2 & 0xFFFFFFFF
10502 // T1 = CRC32(0, T1)
10503 // T2 = CRC32(0, T2)
10504 // C1 = C1 ^ T1
10505 // C2 = C2 ^ T2
10506 // CRC = C1 ^ C2 ^ CRC_C
10507 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10508 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10509 Register tmp1, Register tmp2,
10510 Register n_tmp3) {
10511 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10512 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10513 shlq(in_out, 1);
10514 movl(tmp1, in_out);
10515 shrq(in_out, 32);
10516 xorl(tmp2, tmp2);
10517 crc32(tmp2, tmp1, 4);
10518 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10519 shlq(in1, 1);
10520 movl(tmp1, in1);
10521 shrq(in1, 32);
10522 xorl(tmp2, tmp2);
10523 crc32(tmp2, tmp1, 4);
10524 xorl(in1, tmp2);
10525 xorl(in_out, in1);
10526 xorl(in_out, in2);
10527 }
10528
10529 // Set N to predefined value
10530 // Subtract from a lenght of a buffer
10531 // execute in a loop:
10532 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10533 // for i = 1 to N do
10534 // CRC_A = CRC32(CRC_A, A[i])
10535 // CRC_B = CRC32(CRC_B, B[i])
10536 // CRC_C = CRC32(CRC_C, C[i])
10537 // end for
10538 // Recombine
10539 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10540 Register in_out1, Register in_out2, Register in_out3,
10541 Register tmp1, Register tmp2, Register tmp3,
10542 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10543 Register tmp4, Register tmp5,
10544 Register n_tmp6) {
10545 Label L_processPartitions;
10546 Label L_processPartition;
10547 Label L_exit;
10548
10549 bind(L_processPartitions);
10550 cmpl(in_out1, 3 * size);
10551 jcc(Assembler::less, L_exit);
10552 xorl(tmp1, tmp1);
10553 xorl(tmp2, tmp2);
10554 movq(tmp3, in_out2);
10555 addq(tmp3, size);
10556
10557 bind(L_processPartition);
10558 crc32(in_out3, Address(in_out2, 0), 8);
10559 crc32(tmp1, Address(in_out2, size), 8);
10560 crc32(tmp2, Address(in_out2, size * 2), 8);
10561 addq(in_out2, 8);
10562 cmpq(in_out2, tmp3);
10563 jcc(Assembler::less, L_processPartition);
10564 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10565 w_xtmp1, w_xtmp2, w_xtmp3,
10566 tmp4, tmp5,
10567 n_tmp6);
10568 addq(in_out2, 2 * size);
10569 subl(in_out1, 3 * size);
10570 jmp(L_processPartitions);
10571
10572 bind(L_exit);
10573 }
10574 #else
10575 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10576 Register tmp1, Register tmp2, Register tmp3,
10577 XMMRegister xtmp1, XMMRegister xtmp2) {
10578 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10579 if (n > 0) {
10580 addl(tmp3, n * 256 * 8);
10581 }
10582 // Q1 = TABLEExt[n][B & 0xFF];
10583 movl(tmp1, in_out);
10584 andl(tmp1, 0x000000FF);
10585 shll(tmp1, 3);
10586 addl(tmp1, tmp3);
10587 movq(xtmp1, Address(tmp1, 0));
10588
10589 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10590 movl(tmp2, in_out);
10591 shrl(tmp2, 8);
10592 andl(tmp2, 0x000000FF);
10593 shll(tmp2, 3);
10594 addl(tmp2, tmp3);
10595 movq(xtmp2, Address(tmp2, 0));
10596
10597 psllq(xtmp2, 8);
10598 pxor(xtmp1, xtmp2);
10599
10600 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10601 movl(tmp2, in_out);
10602 shrl(tmp2, 16);
10603 andl(tmp2, 0x000000FF);
10604 shll(tmp2, 3);
10605 addl(tmp2, tmp3);
10606 movq(xtmp2, Address(tmp2, 0));
10607
10608 psllq(xtmp2, 16);
10609 pxor(xtmp1, xtmp2);
10610
10611 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10612 shrl(in_out, 24);
10613 andl(in_out, 0x000000FF);
10614 shll(in_out, 3);
10615 addl(in_out, tmp3);
10616 movq(xtmp2, Address(in_out, 0));
10617
10618 psllq(xtmp2, 24);
10619 pxor(xtmp1, xtmp2); // Result in CXMM
10620 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10621 }
10622
10623 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10624 Register in_out,
10625 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10626 XMMRegister w_xtmp2,
10627 Register tmp1,
10628 Register n_tmp2, Register n_tmp3) {
10629 if (is_pclmulqdq_supported) {
10630 movdl(w_xtmp1, in_out);
10631
10632 movl(tmp1, const_or_pre_comp_const_index);
10633 movdl(w_xtmp2, tmp1);
10634 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10635 // Keep result in XMM since GPR is 32 bit in length
10636 } else {
10637 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10638 }
10639 }
10640
10641 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10642 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10643 Register tmp1, Register tmp2,
10644 Register n_tmp3) {
10645 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10646 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10647
10648 psllq(w_xtmp1, 1);
10649 movdl(tmp1, w_xtmp1);
10650 psrlq(w_xtmp1, 32);
10651 movdl(in_out, w_xtmp1);
10652
10653 xorl(tmp2, tmp2);
10654 crc32(tmp2, tmp1, 4);
10655 xorl(in_out, tmp2);
10656
10657 psllq(w_xtmp2, 1);
10658 movdl(tmp1, w_xtmp2);
10659 psrlq(w_xtmp2, 32);
10660 movdl(in1, w_xtmp2);
10661
10662 xorl(tmp2, tmp2);
10663 crc32(tmp2, tmp1, 4);
10664 xorl(in1, tmp2);
10665 xorl(in_out, in1);
10666 xorl(in_out, in2);
10667 }
10668
10669 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10670 Register in_out1, Register in_out2, Register in_out3,
10671 Register tmp1, Register tmp2, Register tmp3,
10672 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10673 Register tmp4, Register tmp5,
10674 Register n_tmp6) {
10675 Label L_processPartitions;
10676 Label L_processPartition;
10677 Label L_exit;
10678
10679 bind(L_processPartitions);
10680 cmpl(in_out1, 3 * size);
10681 jcc(Assembler::less, L_exit);
10682 xorl(tmp1, tmp1);
10683 xorl(tmp2, tmp2);
10684 movl(tmp3, in_out2);
10685 addl(tmp3, size);
10686
10687 bind(L_processPartition);
10688 crc32(in_out3, Address(in_out2, 0), 4);
10689 crc32(tmp1, Address(in_out2, size), 4);
10690 crc32(tmp2, Address(in_out2, size*2), 4);
10691 crc32(in_out3, Address(in_out2, 0+4), 4);
10692 crc32(tmp1, Address(in_out2, size+4), 4);
10693 crc32(tmp2, Address(in_out2, size*2+4), 4);
10694 addl(in_out2, 8);
10695 cmpl(in_out2, tmp3);
10696 jcc(Assembler::less, L_processPartition);
10697
10698 push(tmp3);
10699 push(in_out1);
10700 push(in_out2);
10701 tmp4 = tmp3;
10702 tmp5 = in_out1;
10703 n_tmp6 = in_out2;
10704
10705 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10706 w_xtmp1, w_xtmp2, w_xtmp3,
10707 tmp4, tmp5,
10708 n_tmp6);
10709
10710 pop(in_out2);
10711 pop(in_out1);
10712 pop(tmp3);
10713
10714 addl(in_out2, 2 * size);
10715 subl(in_out1, 3 * size);
10716 jmp(L_processPartitions);
10717
10718 bind(L_exit);
10719 }
10720 #endif //LP64
10721
10722 #ifdef _LP64
10723 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10724 // Input: A buffer I of L bytes.
10725 // Output: the CRC32C value of the buffer.
10726 // Notations:
10727 // Write L = 24N + r, with N = floor (L/24).
10728 // r = L mod 24 (0 <= r < 24).
10729 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10730 // N quadwords, and R consists of r bytes.
10731 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10732 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10733 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10734 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10735 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10736 Register tmp1, Register tmp2, Register tmp3,
10737 Register tmp4, Register tmp5, Register tmp6,
10738 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10739 bool is_pclmulqdq_supported) {
10740 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10741 Label L_wordByWord;
10742 Label L_byteByByteProlog;
10743 Label L_byteByByte;
10744 Label L_exit;
10745
10746 if (is_pclmulqdq_supported ) {
10747 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10748 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10749
10750 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10751 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10752
10753 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10754 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10755 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10756 } else {
10757 const_or_pre_comp_const_index[0] = 1;
10758 const_or_pre_comp_const_index[1] = 0;
10759
10760 const_or_pre_comp_const_index[2] = 3;
10761 const_or_pre_comp_const_index[3] = 2;
10762
10763 const_or_pre_comp_const_index[4] = 5;
10764 const_or_pre_comp_const_index[5] = 4;
10765 }
10766 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10767 in2, in1, in_out,
10768 tmp1, tmp2, tmp3,
10769 w_xtmp1, w_xtmp2, w_xtmp3,
10770 tmp4, tmp5,
10771 tmp6);
10772 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10773 in2, in1, in_out,
10774 tmp1, tmp2, tmp3,
10775 w_xtmp1, w_xtmp2, w_xtmp3,
10776 tmp4, tmp5,
10777 tmp6);
10778 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10779 in2, in1, in_out,
10780 tmp1, tmp2, tmp3,
10781 w_xtmp1, w_xtmp2, w_xtmp3,
10782 tmp4, tmp5,
10783 tmp6);
10784 movl(tmp1, in2);
10785 andl(tmp1, 0x00000007);
10786 negl(tmp1);
10787 addl(tmp1, in2);
10788 addq(tmp1, in1);
10789
10790 BIND(L_wordByWord);
10791 cmpq(in1, tmp1);
10792 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10793 crc32(in_out, Address(in1, 0), 4);
10794 addq(in1, 4);
10795 jmp(L_wordByWord);
10796
10797 BIND(L_byteByByteProlog);
10798 andl(in2, 0x00000007);
10799 movl(tmp2, 1);
10800
10801 BIND(L_byteByByte);
10802 cmpl(tmp2, in2);
10803 jccb(Assembler::greater, L_exit);
10804 crc32(in_out, Address(in1, 0), 1);
10805 incq(in1);
10806 incl(tmp2);
10807 jmp(L_byteByByte);
10808
10809 BIND(L_exit);
10810 }
10811 #else
10812 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10813 Register tmp1, Register tmp2, Register tmp3,
10814 Register tmp4, Register tmp5, Register tmp6,
10815 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10816 bool is_pclmulqdq_supported) {
10817 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10818 Label L_wordByWord;
10819 Label L_byteByByteProlog;
10820 Label L_byteByByte;
10821 Label L_exit;
10822
10823 if (is_pclmulqdq_supported) {
10824 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10825 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10826
10827 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10828 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10829
10830 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10831 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10832 } else {
10833 const_or_pre_comp_const_index[0] = 1;
10834 const_or_pre_comp_const_index[1] = 0;
10835
10836 const_or_pre_comp_const_index[2] = 3;
10837 const_or_pre_comp_const_index[3] = 2;
10838
10839 const_or_pre_comp_const_index[4] = 5;
10840 const_or_pre_comp_const_index[5] = 4;
10841 }
10842 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10843 in2, in1, in_out,
10844 tmp1, tmp2, tmp3,
10845 w_xtmp1, w_xtmp2, w_xtmp3,
10846 tmp4, tmp5,
10847 tmp6);
10848 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10849 in2, in1, in_out,
10850 tmp1, tmp2, tmp3,
10851 w_xtmp1, w_xtmp2, w_xtmp3,
10852 tmp4, tmp5,
10853 tmp6);
10854 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10855 in2, in1, in_out,
10856 tmp1, tmp2, tmp3,
10857 w_xtmp1, w_xtmp2, w_xtmp3,
10858 tmp4, tmp5,
10859 tmp6);
10860 movl(tmp1, in2);
10861 andl(tmp1, 0x00000007);
10862 negl(tmp1);
10863 addl(tmp1, in2);
10864 addl(tmp1, in1);
10865
10866 BIND(L_wordByWord);
10867 cmpl(in1, tmp1);
10868 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10869 crc32(in_out, Address(in1,0), 4);
10870 addl(in1, 4);
10871 jmp(L_wordByWord);
10872
10873 BIND(L_byteByByteProlog);
10874 andl(in2, 0x00000007);
10875 movl(tmp2, 1);
10876
10877 BIND(L_byteByByte);
10878 cmpl(tmp2, in2);
10879 jccb(Assembler::greater, L_exit);
10880 movb(tmp1, Address(in1, 0));
10881 crc32(in_out, tmp1, 1);
10882 incl(in1);
10883 incl(tmp2);
10884 jmp(L_byteByByte);
10885
10886 BIND(L_exit);
10887 }
10888 #endif // LP64
10889 #undef BIND
10890 #undef BLOCK_COMMENT
10891
10892 // Compress char[] array to byte[].
10893 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10894 // @HotSpotIntrinsicCandidate
10895 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10896 // for (int i = 0; i < len; i++) {
10897 // int c = src[srcOff++];
10898 // if (c >>> 8 != 0) {
10899 // return 0;
10900 // }
10901 // dst[dstOff++] = (byte)c;
10902 // }
10903 // return len;
10904 // }
10905 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10906 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10907 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10908 Register tmp5, Register result) {
10909 Label copy_chars_loop, return_length, return_zero, done, below_threshold;
10910
10911 // rsi: src
10912 // rdi: dst
10913 // rdx: len
10914 // rcx: tmp5
10915 // rax: result
10916
10917 // rsi holds start addr of source char[] to be compressed
10918 // rdi holds start addr of destination byte[]
10919 // rdx holds length
10920
10921 assert(len != result, "");
10922
10923 // save length for return
10924 push(len);
10925
10926 if ((UseAVX > 2) && // AVX512
10927 VM_Version::supports_avx512vlbw() &&
10928 VM_Version::supports_bmi2()) {
10929
10930 set_vector_masking(); // opening of the stub context for programming mask registers
10931
10932 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero;
10933
10934 // alignement
10935 Label post_alignement;
10936
10937 // if length of the string is less than 16, handle it in an old fashioned
10938 // way
10939 testl(len, -32);
10940 jcc(Assembler::zero, below_threshold);
10941
10942 // First check whether a character is compressable ( <= 0xFF).
10943 // Create mask to test for Unicode chars inside zmm vector
10944 movl(result, 0x00FF);
10945 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10946
10947 // Save k1
10948 kmovql(k3, k1);
10949
10950 testl(len, -64);
10951 jcc(Assembler::zero, post_alignement);
10952
10953 movl(tmp5, dst);
10954 andl(tmp5, (32 - 1));
10955 negl(tmp5);
10956 andl(tmp5, (32 - 1));
10957
10958 // bail out when there is nothing to be done
10959 testl(tmp5, 0xFFFFFFFF);
10960 jcc(Assembler::zero, post_alignement);
10961
10962 // ~(~0 << len), where len is the # of remaining elements to process
10963 movl(result, 0xFFFFFFFF);
10964 shlxl(result, result, tmp5);
10965 notl(result);
10966 kmovdl(k1, result);
10967
10968 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10969 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10970 ktestd(k2, k1);
10971 jcc(Assembler::carryClear, restore_k1_return_zero);
10972
10973 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10974
10975 addptr(src, tmp5);
10976 addptr(src, tmp5);
10977 addptr(dst, tmp5);
10978 subl(len, tmp5);
10979
10980 bind(post_alignement);
10981 // end of alignement
10982
10983 movl(tmp5, len);
10984 andl(tmp5, (32 - 1)); // tail count (in chars)
10985 andl(len, ~(32 - 1)); // vector count (in chars)
10986 jcc(Assembler::zero, copy_loop_tail);
10987
10988 lea(src, Address(src, len, Address::times_2));
10989 lea(dst, Address(dst, len, Address::times_1));
10990 negptr(len);
10991
10992 bind(copy_32_loop);
10993 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10994 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10995 kortestdl(k2, k2);
10996 jcc(Assembler::carryClear, restore_k1_return_zero);
10997
10998 // All elements in current processed chunk are valid candidates for
10999 // compression. Write a truncated byte elements to the memory.
11000 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
11001 addptr(len, 32);
11002 jcc(Assembler::notZero, copy_32_loop);
11003
11004 bind(copy_loop_tail);
11005 // bail out when there is nothing to be done
11006 testl(tmp5, 0xFFFFFFFF);
11007 // Restore k1
11008 kmovql(k1, k3);
11009 jcc(Assembler::zero, return_length);
11010
11011 movl(len, tmp5);
11012
11013 // ~(~0 << len), where len is the # of remaining elements to process
11014 movl(result, 0xFFFFFFFF);
11015 shlxl(result, result, len);
11016 notl(result);
11017
11018 kmovdl(k1, result);
11019
11020 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
11021 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
11022 ktestd(k2, k1);
11023 jcc(Assembler::carryClear, restore_k1_return_zero);
11024
11025 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
11026 // Restore k1
11027 kmovql(k1, k3);
11028 jmp(return_length);
11029
11030 bind(restore_k1_return_zero);
11031 // Restore k1
11032 kmovql(k1, k3);
11033 jmp(return_zero);
11034
11035 clear_vector_masking(); // closing of the stub context for programming mask registers
11036 }
11037 if (UseSSE42Intrinsics) {
11038 Label copy_32_loop, copy_16, copy_tail;
11039
11040 bind(below_threshold);
11041
11042 movl(result, len);
11043
11044 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
11045
11046 // vectored compression
11047 andl(len, 0xfffffff0); // vector count (in chars)
11048 andl(result, 0x0000000f); // tail count (in chars)
11049 testl(len, len);
11050 jccb(Assembler::zero, copy_16);
11051
11052 // compress 16 chars per iter
11053 movdl(tmp1Reg, tmp5);
11054 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
11055 pxor(tmp4Reg, tmp4Reg);
11056
11057 lea(src, Address(src, len, Address::times_2));
11058 lea(dst, Address(dst, len, Address::times_1));
11059 negptr(len);
11060
11061 bind(copy_32_loop);
11062 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
11063 por(tmp4Reg, tmp2Reg);
11064 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
11065 por(tmp4Reg, tmp3Reg);
11066 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
11067 jcc(Assembler::notZero, return_zero);
11068 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
11069 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
11070 addptr(len, 16);
11071 jcc(Assembler::notZero, copy_32_loop);
11072
11073 // compress next vector of 8 chars (if any)
11074 bind(copy_16);
11075 movl(len, result);
11076 andl(len, 0xfffffff8); // vector count (in chars)
11077 andl(result, 0x00000007); // tail count (in chars)
11078 testl(len, len);
11079 jccb(Assembler::zero, copy_tail);
11080
11081 movdl(tmp1Reg, tmp5);
11082 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
11083 pxor(tmp3Reg, tmp3Reg);
11084
11085 movdqu(tmp2Reg, Address(src, 0));
11086 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
11087 jccb(Assembler::notZero, return_zero);
11088 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
11089 movq(Address(dst, 0), tmp2Reg);
11090 addptr(src, 16);
11091 addptr(dst, 8);
11092
11093 bind(copy_tail);
11094 movl(len, result);
11095 }
11096 // compress 1 char per iter
11097 testl(len, len);
11098 jccb(Assembler::zero, return_length);
11099 lea(src, Address(src, len, Address::times_2));
11100 lea(dst, Address(dst, len, Address::times_1));
11101 negptr(len);
11102
11103 bind(copy_chars_loop);
11104 load_unsigned_short(result, Address(src, len, Address::times_2));
11105 testl(result, 0xff00); // check if Unicode char
11106 jccb(Assembler::notZero, return_zero);
11107 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
11108 increment(len);
11109 jcc(Assembler::notZero, copy_chars_loop);
11110
11111 // if compression succeeded, return length
11112 bind(return_length);
11113 pop(result);
11114 jmpb(done);
11115
11116 // if compression failed, return 0
11117 bind(return_zero);
11118 xorl(result, result);
11119 addptr(rsp, wordSize);
11120
11121 bind(done);
11122 }
11123
11124 // Inflate byte[] array to char[].
11125 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
11126 // @HotSpotIntrinsicCandidate
11127 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
11128 // for (int i = 0; i < len; i++) {
11129 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
11130 // }
11131 // }
11132 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
11133 XMMRegister tmp1, Register tmp2) {
11134 Label copy_chars_loop, done, below_threshold;
11135 // rsi: src
11136 // rdi: dst
11137 // rdx: len
11138 // rcx: tmp2
11139
11140 // rsi holds start addr of source byte[] to be inflated
11141 // rdi holds start addr of destination char[]
11142 // rdx holds length
11143 assert_different_registers(src, dst, len, tmp2);
11144
11145 if ((UseAVX > 2) && // AVX512
11146 VM_Version::supports_avx512vlbw() &&
11147 VM_Version::supports_bmi2()) {
11148
11149 set_vector_masking(); // opening of the stub context for programming mask registers
11150
11151 Label copy_32_loop, copy_tail;
11152 Register tmp3_aliased = len;
11153
11154 // if length of the string is less than 16, handle it in an old fashioned
11155 // way
11156 testl(len, -16);
11157 jcc(Assembler::zero, below_threshold);
11158
11159 // In order to use only one arithmetic operation for the main loop we use
11160 // this pre-calculation
11161 movl(tmp2, len);
11162 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
11163 andl(len, -32); // vector count
11164 jccb(Assembler::zero, copy_tail);
11165
11166 lea(src, Address(src, len, Address::times_1));
11167 lea(dst, Address(dst, len, Address::times_2));
11168 negptr(len);
11169
11170
11171 // inflate 32 chars per iter
11172 bind(copy_32_loop);
11173 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
11174 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
11175 addptr(len, 32);
11176 jcc(Assembler::notZero, copy_32_loop);
11177
11178 bind(copy_tail);
11179 // bail out when there is nothing to be done
11180 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
11181 jcc(Assembler::zero, done);
11182
11183 // Save k1
11184 kmovql(k2, k1);
11185
11186 // ~(~0 << length), where length is the # of remaining elements to process
11187 movl(tmp3_aliased, -1);
11188 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
11189 notl(tmp3_aliased);
11190 kmovdl(k1, tmp3_aliased);
11191 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
11192 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
11193
11194 // Restore k1
11195 kmovql(k1, k2);
11196 jmp(done);
11197
11198 clear_vector_masking(); // closing of the stub context for programming mask registers
11199 }
11200 if (UseSSE42Intrinsics) {
11201 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
11202
11203 movl(tmp2, len);
11204
11205 if (UseAVX > 1) {
11206 andl(tmp2, (16 - 1));
11207 andl(len, -16);
11208 jccb(Assembler::zero, copy_new_tail);
11209 } else {
11210 andl(tmp2, 0x00000007); // tail count (in chars)
11211 andl(len, 0xfffffff8); // vector count (in chars)
11212 jccb(Assembler::zero, copy_tail);
11213 }
11214
11215 // vectored inflation
11216 lea(src, Address(src, len, Address::times_1));
11217 lea(dst, Address(dst, len, Address::times_2));
11218 negptr(len);
11219
11220 if (UseAVX > 1) {
11221 bind(copy_16_loop);
11222 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
11223 vmovdqu(Address(dst, len, Address::times_2), tmp1);
11224 addptr(len, 16);
11225 jcc(Assembler::notZero, copy_16_loop);
11226
11227 bind(below_threshold);
11228 bind(copy_new_tail);
11229 if ((UseAVX > 2) &&
11230 VM_Version::supports_avx512vlbw() &&
11231 VM_Version::supports_bmi2()) {
11232 movl(tmp2, len);
11233 } else {
11234 movl(len, tmp2);
11235 }
11236 andl(tmp2, 0x00000007);
11237 andl(len, 0xFFFFFFF8);
11238 jccb(Assembler::zero, copy_tail);
11239
11240 pmovzxbw(tmp1, Address(src, 0));
11241 movdqu(Address(dst, 0), tmp1);
11242 addptr(src, 8);
11243 addptr(dst, 2 * 8);
11244
11245 jmp(copy_tail, true);
11246 }
11247
11248 // inflate 8 chars per iter
11249 bind(copy_8_loop);
11250 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
11251 movdqu(Address(dst, len, Address::times_2), tmp1);
11252 addptr(len, 8);
11253 jcc(Assembler::notZero, copy_8_loop);
11254
11255 bind(copy_tail);
11256 movl(len, tmp2);
11257
11258 cmpl(len, 4);
11259 jccb(Assembler::less, copy_bytes);
11260
11261 movdl(tmp1, Address(src, 0)); // load 4 byte chars
11262 pmovzxbw(tmp1, tmp1);
11263 movq(Address(dst, 0), tmp1);
11264 subptr(len, 4);
11265 addptr(src, 4);
11266 addptr(dst, 8);
11267
11268 bind(copy_bytes);
11269 }
11270 testl(len, len);
11271 jccb(Assembler::zero, done);
11272 lea(src, Address(src, len, Address::times_1));
11273 lea(dst, Address(dst, len, Address::times_2));
11274 negptr(len);
11275
11276 // inflate 1 char per iter
11277 bind(copy_chars_loop);
11278 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
11279 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
11280 increment(len);
11281 jcc(Assembler::notZero, copy_chars_loop);
11282
11283 bind(done);
11284 }
11285
11286 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
11287 switch (cond) {
11288 // Note some conditions are synonyms for others
11289 case Assembler::zero: return Assembler::notZero;
11290 case Assembler::notZero: return Assembler::zero;
11291 case Assembler::less: return Assembler::greaterEqual;
11292 case Assembler::lessEqual: return Assembler::greater;
11293 case Assembler::greater: return Assembler::lessEqual;
11294 case Assembler::greaterEqual: return Assembler::less;
11295 case Assembler::below: return Assembler::aboveEqual;
11296 case Assembler::belowEqual: return Assembler::above;
11297 case Assembler::above: return Assembler::belowEqual;
11298 case Assembler::aboveEqual: return Assembler::below;
11299 case Assembler::overflow: return Assembler::noOverflow;
11300 case Assembler::noOverflow: return Assembler::overflow;
11301 case Assembler::negative: return Assembler::positive;
11302 case Assembler::positive: return Assembler::negative;
11303 case Assembler::parity: return Assembler::noParity;
11304 case Assembler::noParity: return Assembler::parity;
11305 }
11306 ShouldNotReachHere(); return Assembler::overflow;
11307 }
11308
11309 SkipIfEqual::SkipIfEqual(
11310 MacroAssembler* masm, const bool* flag_addr, bool value) {
11311 _masm = masm;
11312 _masm->cmp8(ExternalAddress((address)flag_addr), value);
11313 _masm->jcc(Assembler::equal, _label);
11314 }
11315
11316 SkipIfEqual::~SkipIfEqual() {
11317 _masm->bind(_label);
11318 }
11319
11320 // 32-bit Windows has its own fast-path implementation
11321 // of get_thread
11322 #if !defined(WIN32) || defined(_LP64)
11323
11324 // This is simply a call to Thread::current()
11325 void MacroAssembler::get_thread(Register thread) {
11326 if (thread != rax) {
11327 push(rax);
11328 }
11329 LP64_ONLY(push(rdi);)
11330 LP64_ONLY(push(rsi);)
11331 push(rdx);
11332 push(rcx);
11333 #ifdef _LP64
11334 push(r8);
11335 push(r9);
11336 push(r10);
11337 push(r11);
11338 #endif
11339
11340 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11341
11342 #ifdef _LP64
11343 pop(r11);
11344 pop(r10);
11345 pop(r9);
11346 pop(r8);
11347 #endif
11348 pop(rcx);
11349 pop(rdx);
11350 LP64_ONLY(pop(rsi);)
11351 LP64_ONLY(pop(rdi);)
11352 if (thread != rax) {
11353 mov(thread, rax);
11354 pop(rax);
11355 }
11356 }
11357
11358 #endif