2546 transition(state, state);
2547
2548 assert(_desc->calls_vm(),
2549 "inconsistent calls_vm information"); // call in remove_activation
2550
2551 if (_desc->bytecode() == Bytecodes::_return_register_finalizer) {
2552 assert(state == vtos, "only valid state");
2553 Register robj = LP64_ONLY(c_rarg1) NOT_LP64(rax);
2554 __ movptr(robj, aaddress(0));
2555 __ load_klass(rdi, robj);
2556 __ movl(rdi, Address(rdi, Klass::access_flags_offset()));
2557 __ testl(rdi, JVM_ACC_HAS_FINALIZER);
2558 Label skip_register_finalizer;
2559 __ jcc(Assembler::zero, skip_register_finalizer);
2560
2561 __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::register_finalizer), robj);
2562
2563 __ bind(skip_register_finalizer);
2564 }
2565
2566 #ifdef _LP64
2567 if (SafepointMechanism::uses_thread_local_poll() && _desc->bytecode() != Bytecodes::_return_register_finalizer) {
2568 Label no_safepoint;
2569 NOT_PRODUCT(__ block_comment("Thread-local Safepoint poll"));
2570 __ testb(Address(r15_thread, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
2571 __ jcc(Assembler::zero, no_safepoint);
2572 __ push(state);
2573 __ call_VM(noreg, CAST_FROM_FN_PTR(address,
2574 InterpreterRuntime::at_safepoint));
2575 __ pop(state);
2576 __ bind(no_safepoint);
2577 }
2578 #endif
2579
2580 // Narrow result if state is itos but result type is smaller.
2581 // Need to narrow in the return bytecode rather than in generate_return_entry
2582 // since compiled code callers expect the result to already be narrowed.
2583 if (state == itos) {
2584 __ narrow(rax);
2585 }
2586 __ remove_activation(state, rbcp);
2587
2588 __ jmp(rbcp);
2589 }
2590
2591 // ----------------------------------------------------------------------------
2592 // Volatile variables demand their effects be made known to all CPU's
2593 // in order. Store buffers on most chips allow reads & writes to
2594 // reorder; the JMM's ReadAfterWrite.java test fails in -Xint mode
2595 // without some kind of memory barrier (i.e., it's not sufficient that
2596 // the interpreter does not reorder volatile references, the hardware
2597 // also must not reorder them).
2598 //
|
2546 transition(state, state);
2547
2548 assert(_desc->calls_vm(),
2549 "inconsistent calls_vm information"); // call in remove_activation
2550
2551 if (_desc->bytecode() == Bytecodes::_return_register_finalizer) {
2552 assert(state == vtos, "only valid state");
2553 Register robj = LP64_ONLY(c_rarg1) NOT_LP64(rax);
2554 __ movptr(robj, aaddress(0));
2555 __ load_klass(rdi, robj);
2556 __ movl(rdi, Address(rdi, Klass::access_flags_offset()));
2557 __ testl(rdi, JVM_ACC_HAS_FINALIZER);
2558 Label skip_register_finalizer;
2559 __ jcc(Assembler::zero, skip_register_finalizer);
2560
2561 __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::register_finalizer), robj);
2562
2563 __ bind(skip_register_finalizer);
2564 }
2565
2566 if (SafepointMechanism::uses_thread_local_poll() && _desc->bytecode() != Bytecodes::_return_register_finalizer) {
2567 Label no_safepoint;
2568 NOT_PRODUCT(__ block_comment("Thread-local Safepoint poll"));
2569 #ifdef AMD64
2570 __ testb(Address(r15_thread, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
2571 #else
2572 const Register thread = rdi;
2573 __ get_thread(thread);
2574 __ testb(Address(thread, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
2575 #endif
2576 __ jcc(Assembler::zero, no_safepoint);
2577 __ push(state);
2578 __ call_VM(noreg, CAST_FROM_FN_PTR(address,
2579 InterpreterRuntime::at_safepoint));
2580 __ pop(state);
2581 __ bind(no_safepoint);
2582 }
2583
2584 // Narrow result if state is itos but result type is smaller.
2585 // Need to narrow in the return bytecode rather than in generate_return_entry
2586 // since compiled code callers expect the result to already be narrowed.
2587 if (state == itos) {
2588 __ narrow(rax);
2589 }
2590 __ remove_activation(state, rbcp);
2591
2592 __ jmp(rbcp);
2593 }
2594
2595 // ----------------------------------------------------------------------------
2596 // Volatile variables demand their effects be made known to all CPU's
2597 // in order. Store buffers on most chips allow reads & writes to
2598 // reorder; the JMM's ReadAfterWrite.java test fails in -Xint mode
2599 // without some kind of memory barrier (i.e., it's not sufficient that
2600 // the interpreter does not reorder volatile references, the hardware
2601 // also must not reorder them).
2602 //
|