src/hotspot/os_cpu/aix_ppc/atomic_aix_ppc.hpp

rev 54056 : 8220441: [PPC64] Clobber memory effect missing for memory barriers in atomics
Reviewed-by:

@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2018 SAP SE. All rights reserved.
+ * Copyright (c) 2012, 2019 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 only, as
  * published by the Free Software Foundation.

@@ -68,36 +68,27 @@
 //                           Load|Store,
 //                           Load|Load,
 //                          Store|Load
 //
 
-#define strasm_sync                       "\n  sync    \n"
-#define strasm_lwsync                     "\n  lwsync  \n"
-#define strasm_isync                      "\n  isync   \n"
-#define strasm_release                    strasm_lwsync
-#define strasm_acquire                    strasm_lwsync
-#define strasm_fence                      strasm_sync
-#define strasm_nobarrier                  ""
-#define strasm_nobarrier_clobber_memory   ""
-
 inline void pre_membar(atomic_memory_order order) {
   switch (order) {
     case memory_order_relaxed:
     case memory_order_acquire: break;
     case memory_order_release:
-    case memory_order_acq_rel: __asm__ __volatile__ (strasm_lwsync); break;
-    default /*conservative*/ : __asm__ __volatile__ (strasm_sync); break;
+    case memory_order_acq_rel: __asm__ __volatile__ ("lwsync" : : : "memory"); break;
+    default /*conservative*/ : __asm__ __volatile__ ("sync"   : : : "memory"); break;
   }
 }
 
 inline void post_membar(atomic_memory_order order) {
   switch (order) {
     case memory_order_relaxed:
     case memory_order_release: break;
     case memory_order_acquire:
-    case memory_order_acq_rel: __asm__ __volatile__ (strasm_isync); break;
-    default /*conservative*/ : __asm__ __volatile__ (strasm_sync); break;
+    case memory_order_acq_rel: __asm__ __volatile__ ("isync"  : : : "memory"); break;
+    default /*conservative*/ : __asm__ __volatile__ ("sync"   : : : "memory"); break;
   }
 }
 
 
 template<size_t byte_size>

@@ -406,15 +397,6 @@
   post_membar(order);
 
   return old_value;
 }
 
-#undef strasm_sync
-#undef strasm_lwsync
-#undef strasm_isync
-#undef strasm_release
-#undef strasm_acquire
-#undef strasm_fence
-#undef strasm_nobarrier
-#undef strasm_nobarrier_clobber_memory
-
 #endif // OS_CPU_AIX_PPC_ATOMIC_AIX_PPC_HPP