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src/hotspot/cpu/arm/jniFastGetField_arm.cpp
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rev 55759 : 8227680: FastJNIAccessors: Check for JVMTI field access event requests at runtime
Summary: Check JvmtiExport::_field_access_count != 0 at runtime
Reviewed-by:
*** 1,7 ****
/*
! * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
--- 1,7 ----
/*
! * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*** 97,122 ****
ResourceMark rm;
BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE);
CodeBuffer cbuf(blob);
MacroAssembler* masm = new MacroAssembler(&cbuf);
fast_entry = __ pc();
// Safepoint check
InlinedAddress safepoint_counter_addr(SafepointSynchronize::safepoint_counter_addr());
- Label slow_case;
__ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
__ push(RegisterSet(R0, R3)); // save incoming arguments for slow case
__ ldr_s32(Rsafept_cnt, Address(Rsafepoint_counter_addr));
__ tbnz(Rsafept_cnt, 0, slow_case);
__ bic(R1, R1, JNIHandles::weak_tag_mask);
// Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
__ andr(Rtmp1, Rsafept_cnt, (unsigned)1);
__ ldr(Robj, Address(R1, Rtmp1));
Address field_addr;
if (type != T_BOOLEAN
&& type != T_INT
#ifndef __ABI_HARD__
--- 97,134 ----
ResourceMark rm;
BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE);
CodeBuffer cbuf(blob);
MacroAssembler* masm = new MacroAssembler(&cbuf);
fast_entry = __ pc();
+ Label slow_case;
// Safepoint check
InlinedAddress safepoint_counter_addr(SafepointSynchronize::safepoint_counter_addr());
__ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
__ push(RegisterSet(R0, R3)); // save incoming arguments for slow case
__ ldr_s32(Rsafept_cnt, Address(Rsafepoint_counter_addr));
__ tbnz(Rsafept_cnt, 0, slow_case);
__ bic(R1, R1, JNIHandles::weak_tag_mask);
+ if (JvmtiExport::can_post_field_access()) {
+ // Using barrier to order wrt. JVMTI check and load of result.
+ __ membar(Assembler::LoadLoad, Rtmp1);
+
+ // Check to see if a field access watch has been set before we
+ // take the fast path.
+ __ ldr_global_s32(Rtmp1, (address)JvmtiExport::get_field_access_count_addr());
+ __ cbnz(Rtmp1, slow_case);
+
+ __ ldr(Robj, Address(R1));
+ } else {
// Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
__ andr(Rtmp1, Rsafept_cnt, (unsigned)1);
__ ldr(Robj, Address(R1, Rtmp1));
+ }
Address field_addr;
if (type != T_BOOLEAN
&& type != T_INT
#ifndef __ABI_HARD__
*** 168,191 ****
#endif // __ABI_HARD__
default:
ShouldNotReachHere();
}
! // Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
#ifdef __ABI_HARD__
if (type == T_FLOAT || type == T_DOUBLE) {
- __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
__ fmrrd(Rres, Rres_hi, D0);
! __ eor(Rtmp2, Rres, Rres);
! __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr, Rtmp2));
! } else
#endif // __ABI_HARD__
! {
! __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
__ eor(Rtmp2, Rres, Rres);
__ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr, Rtmp2));
}
__ cmp(Rsafept_cnt2, Rsafept_cnt);
// discards saved R0 R1 R2 R3
__ add(SP, SP, 4 * wordSize, eq);
__ bx(LR, eq);
--- 180,206 ----
#endif // __ABI_HARD__
default:
ShouldNotReachHere();
}
! __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
#ifdef __ABI_HARD__
if (type == T_FLOAT || type == T_DOUBLE) {
__ fmrrd(Rres, Rres_hi, D0);
! }
#endif // __ABI_HARD__
!
! if (JvmtiExport::can_post_field_access()) {
! // Order JVMTI check and load of result wrt. succeeding check.
! __ membar(Assembler::LoadLoad, Rtmp2);
! __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr));
! } else {
! // Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
__ eor(Rtmp2, Rres, Rres);
__ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr, Rtmp2));
}
+
__ cmp(Rsafept_cnt2, Rsafept_cnt);
// discards saved R0 R1 R2 R3
__ add(SP, SP, 4 * wordSize, eq);
__ bx(LR, eq);
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