1 /*
2 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
82 const Register Robj = R1;
83 const Register Rres = R0;
84 const Register Rres_hi = R1;
85 const Register Rsafept_cnt = Rtemp;
86 const Register Rsafept_cnt2 = Rsafepoint_counter_addr;
87 const Register Rtmp1 = R3; // same as Rsafepoint_counter_addr
88 const Register Rtmp2 = R2; // same as jfieldID
89
90 assert_different_registers(Rsafepoint_counter_addr, Rsafept_cnt, Robj, Rres, LR);
91 assert_different_registers(Rsafept_cnt, R1, R2, Rtmp1, LR);
92 assert_different_registers(Rsafepoint_counter_addr, Rsafept_cnt, Rres, Rres_hi, Rtmp2, LR);
93 assert_different_registers(Rsafept_cnt2, Rsafept_cnt, Rres, Rres_hi, LR);
94
95 address fast_entry;
96
97 ResourceMark rm;
98 BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE);
99 CodeBuffer cbuf(blob);
100 MacroAssembler* masm = new MacroAssembler(&cbuf);
101 fast_entry = __ pc();
102
103 // Safepoint check
104 InlinedAddress safepoint_counter_addr(SafepointSynchronize::safepoint_counter_addr());
105 Label slow_case;
106 __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
107
108 __ push(RegisterSet(R0, R3)); // save incoming arguments for slow case
109
110 __ ldr_s32(Rsafept_cnt, Address(Rsafepoint_counter_addr));
111 __ tbnz(Rsafept_cnt, 0, slow_case);
112
113 __ bic(R1, R1, JNIHandles::weak_tag_mask);
114
115 // Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
116 __ andr(Rtmp1, Rsafept_cnt, (unsigned)1);
117 __ ldr(Robj, Address(R1, Rtmp1));
118
119 Address field_addr;
120 if (type != T_BOOLEAN
121 && type != T_INT
122 #ifndef __ABI_HARD__
123 && type != T_FLOAT
124 #endif // !__ABI_HARD__
125 ) {
126 // Only ldr and ldrb support embedded shift, other loads do not
127 __ add(Robj, Robj, AsmOperand(R2, lsr, 2));
128 field_addr = Address(Robj);
129 } else {
130 field_addr = Address(Robj, R2, lsr, 2);
131 }
132 assert(count < LIST_CAPACITY, "LIST_CAPACITY too small");
133 speculative_load_pclist[count] = __ pc();
134
135 switch (type) {
136 case T_BOOLEAN:
137 __ ldrb(Rres, field_addr);
153 break;
154 case T_LONG:
155 #ifndef __ABI_HARD__
156 case T_DOUBLE:
157 #endif
158 // Safe to use ldrd since long and double fields are 8-byte aligned
159 __ ldrd(Rres, field_addr);
160 break;
161 #ifdef __ABI_HARD__
162 case T_FLOAT:
163 __ ldr_float(S0, field_addr);
164 break;
165 case T_DOUBLE:
166 __ ldr_double(D0, field_addr);
167 break;
168 #endif // __ABI_HARD__
169 default:
170 ShouldNotReachHere();
171 }
172
173 // Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
174 #ifdef __ABI_HARD__
175 if (type == T_FLOAT || type == T_DOUBLE) {
176 __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
177 __ fmrrd(Rres, Rres_hi, D0);
178 __ eor(Rtmp2, Rres, Rres);
179 __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr, Rtmp2));
180 } else
181 #endif // __ABI_HARD__
182 {
183 __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
184 __ eor(Rtmp2, Rres, Rres);
185 __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr, Rtmp2));
186 }
187 __ cmp(Rsafept_cnt2, Rsafept_cnt);
188 // discards saved R0 R1 R2 R3
189 __ add(SP, SP, 4 * wordSize, eq);
190 __ bx(LR, eq);
191
192 slowcase_entry_pclist[count++] = __ pc();
193
194 __ bind(slow_case);
195 __ pop(RegisterSet(R0, R3));
196 // thumb mode switch handled by MacroAssembler::jump if needed
197 __ jump(slow_case_addr, relocInfo::none, Rtemp);
198
199 __ bind_literal(safepoint_counter_addr);
200
201 __ flush();
202
203 guarantee((__ pc() - fast_entry) <= BUFFER_SIZE, "BUFFER_SIZE too small");
204
205 return fast_entry;
206 }
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1 /*
2 * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
82 const Register Robj = R1;
83 const Register Rres = R0;
84 const Register Rres_hi = R1;
85 const Register Rsafept_cnt = Rtemp;
86 const Register Rsafept_cnt2 = Rsafepoint_counter_addr;
87 const Register Rtmp1 = R3; // same as Rsafepoint_counter_addr
88 const Register Rtmp2 = R2; // same as jfieldID
89
90 assert_different_registers(Rsafepoint_counter_addr, Rsafept_cnt, Robj, Rres, LR);
91 assert_different_registers(Rsafept_cnt, R1, R2, Rtmp1, LR);
92 assert_different_registers(Rsafepoint_counter_addr, Rsafept_cnt, Rres, Rres_hi, Rtmp2, LR);
93 assert_different_registers(Rsafept_cnt2, Rsafept_cnt, Rres, Rres_hi, LR);
94
95 address fast_entry;
96
97 ResourceMark rm;
98 BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE);
99 CodeBuffer cbuf(blob);
100 MacroAssembler* masm = new MacroAssembler(&cbuf);
101 fast_entry = __ pc();
102 Label slow_case;
103
104 // Safepoint check
105 InlinedAddress safepoint_counter_addr(SafepointSynchronize::safepoint_counter_addr());
106 __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
107
108 __ push(RegisterSet(R0, R3)); // save incoming arguments for slow case
109
110 __ ldr_s32(Rsafept_cnt, Address(Rsafepoint_counter_addr));
111 __ tbnz(Rsafept_cnt, 0, slow_case);
112
113 __ bic(R1, R1, JNIHandles::weak_tag_mask);
114
115 if (JvmtiExport::can_post_field_access()) {
116 // Using barrier to order wrt. JVMTI check and load of result.
117 __ membar(Assembler::LoadLoad, Rtmp1);
118
119 // Check to see if a field access watch has been set before we
120 // take the fast path.
121 __ ldr_global_s32(Rtmp1, (address)JvmtiExport::get_field_access_count_addr());
122 __ cbnz(Rtmp1, slow_case);
123
124 __ ldr(Robj, Address(R1));
125 } else {
126 // Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
127 __ andr(Rtmp1, Rsafept_cnt, (unsigned)1);
128 __ ldr(Robj, Address(R1, Rtmp1));
129 }
130
131 Address field_addr;
132 if (type != T_BOOLEAN
133 && type != T_INT
134 #ifndef __ABI_HARD__
135 && type != T_FLOAT
136 #endif // !__ABI_HARD__
137 ) {
138 // Only ldr and ldrb support embedded shift, other loads do not
139 __ add(Robj, Robj, AsmOperand(R2, lsr, 2));
140 field_addr = Address(Robj);
141 } else {
142 field_addr = Address(Robj, R2, lsr, 2);
143 }
144 assert(count < LIST_CAPACITY, "LIST_CAPACITY too small");
145 speculative_load_pclist[count] = __ pc();
146
147 switch (type) {
148 case T_BOOLEAN:
149 __ ldrb(Rres, field_addr);
165 break;
166 case T_LONG:
167 #ifndef __ABI_HARD__
168 case T_DOUBLE:
169 #endif
170 // Safe to use ldrd since long and double fields are 8-byte aligned
171 __ ldrd(Rres, field_addr);
172 break;
173 #ifdef __ABI_HARD__
174 case T_FLOAT:
175 __ ldr_float(S0, field_addr);
176 break;
177 case T_DOUBLE:
178 __ ldr_double(D0, field_addr);
179 break;
180 #endif // __ABI_HARD__
181 default:
182 ShouldNotReachHere();
183 }
184
185 __ ldr_literal(Rsafepoint_counter_addr, safepoint_counter_addr);
186 #ifdef __ABI_HARD__
187 if (type == T_FLOAT || type == T_DOUBLE) {
188 __ fmrrd(Rres, Rres_hi, D0);
189 }
190 #endif // __ABI_HARD__
191
192 if (JvmtiExport::can_post_field_access()) {
193 // Order JVMTI check and load of result wrt. succeeding check.
194 __ membar(Assembler::LoadLoad, Rtmp2);
195 __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr));
196 } else {
197 // Address dependency restricts memory access ordering. It's cheaper than explicit LoadLoad barrier
198 __ eor(Rtmp2, Rres, Rres);
199 __ ldr_s32(Rsafept_cnt2, Address(Rsafepoint_counter_addr, Rtmp2));
200 }
201
202 __ cmp(Rsafept_cnt2, Rsafept_cnt);
203 // discards saved R0 R1 R2 R3
204 __ add(SP, SP, 4 * wordSize, eq);
205 __ bx(LR, eq);
206
207 slowcase_entry_pclist[count++] = __ pc();
208
209 __ bind(slow_case);
210 __ pop(RegisterSet(R0, R3));
211 // thumb mode switch handled by MacroAssembler::jump if needed
212 __ jump(slow_case_addr, relocInfo::none, Rtemp);
213
214 __ bind_literal(safepoint_counter_addr);
215
216 __ flush();
217
218 guarantee((__ pc() - fast_entry) <= BUFFER_SIZE, "BUFFER_SIZE too small");
219
220 return fast_entry;
221 }
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