# HG changeset patch
# User mdoerr
# Date 1565630412 -7200
#      Mon Aug 12 19:20:12 2019 +0200
# Node ID ee58b6dcb9c8acfea0e1950be8d07100e46e7c24
# Parent  9f44485e7441a60d041285aef2c0d7a908c2f5bd
8229422: Taskqueue: Outdated selection of weak memory model platforms
Reviewed-by:

diff --git a/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp b/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp
--- a/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp
+++ b/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp
@@ -34,6 +34,8 @@
 
 #define SUPPORTS_NATIVE_CX8
 
+// aarch64 is not CPU_MULTI_COPY_ATOMIC
+
 // According to the ARMv8 ARM, "Concurrent modification and execution
 // of instructions can lead to the resulting instruction performing
 // any behavior that can be achieved by executing any sequence of
diff --git a/src/hotspot/cpu/arm/globalDefinitions_arm.hpp b/src/hotspot/cpu/arm/globalDefinitions_arm.hpp
--- a/src/hotspot/cpu/arm/globalDefinitions_arm.hpp
+++ b/src/hotspot/cpu/arm/globalDefinitions_arm.hpp
@@ -45,6 +45,8 @@
 #define SUPPORTS_NATIVE_CX8
 #endif
 
+// arm32 is not CPU_MULTI_COPY_ATOMIC
+
 #define STUBROUTINES_MD_HPP    "stubRoutines_arm.hpp"
 #define INTERP_MASM_MD_HPP     "interp_masm_arm.hpp"
 #define TEMPLATETABLE_MD_HPP   "templateTable_arm.hpp"
diff --git a/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp b/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp
--- a/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp
+++ b/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp
@@ -41,8 +41,7 @@
 
 #define SUPPORTS_NATIVE_CX8
 
-// The PPC CPUs are NOT multiple-copy-atomic.
-#define CPU_NOT_MULTIPLE_COPY_ATOMIC
+// PPC64 is not CPU_MULTI_COPY_ATOMIC
 
 // The expected size in bytes of a cache line, used to pad data structures.
 #define DEFAULT_CACHE_LINE_SIZE 128
diff --git a/src/hotspot/cpu/s390/globalDefinitions_s390.hpp b/src/hotspot/cpu/s390/globalDefinitions_s390.hpp
--- a/src/hotspot/cpu/s390/globalDefinitions_s390.hpp
+++ b/src/hotspot/cpu/s390/globalDefinitions_s390.hpp
@@ -42,6 +42,9 @@
 
 #define SUPPORTS_NATIVE_CX8
 
+// s390 has this property:
+#define CPU_MULTI_COPY_ATOMIC
+
 // Indicates whether the C calling conventions require that
 // 32-bit integer argument values are extended to 64 bits.
 // This is the case on z/Architecture.
diff --git a/src/hotspot/cpu/sparc/globalDefinitions_sparc.hpp b/src/hotspot/cpu/sparc/globalDefinitions_sparc.hpp
--- a/src/hotspot/cpu/sparc/globalDefinitions_sparc.hpp
+++ b/src/hotspot/cpu/sparc/globalDefinitions_sparc.hpp
@@ -36,6 +36,9 @@
 
 #define SUPPORTS_NATIVE_CX8
 
+// SPARC has this property:
+#define CPU_MULTI_COPY_ATOMIC
+
 // The expected size in bytes of a cache line, used to pad data structures.
 #if defined(TIERED)
   // tiered, 64-bit, large machine
diff --git a/src/hotspot/cpu/x86/globalDefinitions_x86.hpp b/src/hotspot/cpu/x86/globalDefinitions_x86.hpp
--- a/src/hotspot/cpu/x86/globalDefinitions_x86.hpp
+++ b/src/hotspot/cpu/x86/globalDefinitions_x86.hpp
@@ -33,6 +33,9 @@
 
 #define SUPPORTS_NATIVE_CX8
 
+// x86 has this property:
+#define CPU_MULTI_COPY_ATOMIC
+
 // The expected size in bytes of a cache line, used to pad data structures.
 #if defined(TIERED)
   #ifdef _LP64
diff --git a/src/hotspot/share/gc/shared/taskqueue.inline.hpp b/src/hotspot/share/gc/shared/taskqueue.inline.hpp
--- a/src/hotspot/share/gc/shared/taskqueue.inline.hpp
+++ b/src/hotspot/share/gc/shared/taskqueue.inline.hpp
@@ -207,7 +207,7 @@
   // Architectures with weak memory model require a barrier here
   // to guarantee that bottom is not older than age,
   // which is crucial for the correctness of the algorithm.
-#if !(defined SPARC || defined IA32 || defined AMD64)
+#ifndef CPU_MULTI_COPY_ATOMIC
   OrderAccess::fence();
 #endif
   uint localBot = OrderAccess::load_acquire(&_bottom);
diff --git a/src/hotspot/share/opto/parse1.cpp b/src/hotspot/share/opto/parse1.cpp
--- a/src/hotspot/share/opto/parse1.cpp
+++ b/src/hotspot/share/opto/parse1.cpp
@@ -996,8 +996,10 @@
   //
   if (method()->is_initializer() &&
         (wrote_final() ||
-           PPC64_ONLY(wrote_volatile() ||)
-           (AlwaysSafeConstructors && wrote_fields()))) {
+           (AlwaysSafeConstructors && wrote_fields()) ||
+           (support_IRIW_for_not_multiple_copy_atomic_cpu && wrote_volatile())
+        )
+     ) {
     _exits.insert_mem_bar(Op_MemBarRelease, alloc_with_final());
 
     // If Memory barrier is created for final fields write
diff --git a/src/hotspot/share/utilities/globalDefinitions.hpp b/src/hotspot/share/utilities/globalDefinitions.hpp
--- a/src/hotspot/share/utilities/globalDefinitions.hpp
+++ b/src/hotspot/share/utilities/globalDefinitions.hpp
@@ -481,10 +481,13 @@
 // assure their ordering, instead of after volatile stores.
 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
-#ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC
-const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true;
+#ifdef CPU_MULTI_COPY_ATOMIC
+// Not needed.
+const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
 #else
-const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
+// From all non-multi-copy-atomic architectures, only PPC64 supports IRIW at the moment.
+// Final decision is subject to JEP 188: Java Memory Model Update.
+const bool support_IRIW_for_not_multiple_copy_atomic_cpu = PPC64_ONLY(true) NOT_PPC64(false);
 #endif
 
 // The expected size in bytes of a cache line, used to pad data structures.