16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_GLOBALDEFINITIONS_X86_HPP
26 #define CPU_X86_GLOBALDEFINITIONS_X86_HPP
27
28 const int StackAlignmentInBytes = 16;
29
30 // Indicates whether the C calling conventions require that
31 // 32-bit integer argument values are extended to 64 bits.
32 const bool CCallingConventionRequiresIntsAsLongs = false;
33
34 #define SUPPORTS_NATIVE_CX8
35
36 // The expected size in bytes of a cache line, used to pad data structures.
37 #if defined(TIERED)
38 #ifdef _LP64
39 // tiered, 64-bit, large machine
40 #define DEFAULT_CACHE_LINE_SIZE 128
41 #else
42 // tiered, 32-bit, medium machine
43 #define DEFAULT_CACHE_LINE_SIZE 64
44 #endif
45 #elif defined(COMPILER1)
46 // pure C1, 32-bit, small machine
47 // i486 was the last Intel chip with 16-byte cache line size
48 #define DEFAULT_CACHE_LINE_SIZE 32
49 #elif defined(COMPILER2)
50 #ifdef _LP64
51 // pure C2, 64-bit, large machine
52 #define DEFAULT_CACHE_LINE_SIZE 128
53 #else
54 // pure C2, 32-bit, medium machine
55 #define DEFAULT_CACHE_LINE_SIZE 64
|
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_GLOBALDEFINITIONS_X86_HPP
26 #define CPU_X86_GLOBALDEFINITIONS_X86_HPP
27
28 const int StackAlignmentInBytes = 16;
29
30 // Indicates whether the C calling conventions require that
31 // 32-bit integer argument values are extended to 64 bits.
32 const bool CCallingConventionRequiresIntsAsLongs = false;
33
34 #define SUPPORTS_NATIVE_CX8
35
36 // x86 has this property:
37 #define CPU_MULTI_COPY_ATOMIC
38
39 // The expected size in bytes of a cache line, used to pad data structures.
40 #if defined(TIERED)
41 #ifdef _LP64
42 // tiered, 64-bit, large machine
43 #define DEFAULT_CACHE_LINE_SIZE 128
44 #else
45 // tiered, 32-bit, medium machine
46 #define DEFAULT_CACHE_LINE_SIZE 64
47 #endif
48 #elif defined(COMPILER1)
49 // pure C1, 32-bit, small machine
50 // i486 was the last Intel chip with 16-byte cache line size
51 #define DEFAULT_CACHE_LINE_SIZE 32
52 #elif defined(COMPILER2)
53 #ifdef _LP64
54 // pure C2, 64-bit, large machine
55 #define DEFAULT_CACHE_LINE_SIZE 128
56 #else
57 // pure C2, 32-bit, medium machine
58 #define DEFAULT_CACHE_LINE_SIZE 64
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